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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; |
architecture RTL of FIFO is
function func1 return integer is begin end FUNCTION func1;
function func1 return integer is begin end FUNCTION func1;
function func1 return integer is begin end FUNCTION func1;
begin
end architecture RTL;
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLKIN : in std_logic;
-- Clock out ports
CLKOUT : out std_logic;
CLKOUT2 : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLKIN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 39,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 34,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 17,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLKOUT,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLKOUT2,
I => clkout1);
end xilinx;
|
entity ent2 is
end entity;
architecture a of ent2 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
entity ent2 is
end entity;
architecture a of ent2 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
entity ent2 is
end entity;
architecture a of ent2 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_Subsystem.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.23.17:41:24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Subsystem is
port (
height : out std_logic_vector(15 downto 0); -- height.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
vertex_row : out std_logic_vector(15 downto 0); -- vertex_row.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
vertex_col : out std_logic_vector(15 downto 0); -- vertex_col.wire
width : out std_logic_vector(15 downto 0); -- width.wire
write : in std_logic := '0' -- write.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Subsystem;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_Subsystem is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNZCCH64DU is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNZCCH64DU;
component alt_dspbuilder_delay_GNXULFMRSU is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNXULFMRSU;
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_cast_GNEFMFJW6A is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNEFMFJW6A;
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay9sclrgnd_output_wire : std_logic; -- Delay9sclrGND:output -> Delay9:sclr
signal delay8sclrgnd_output_wire : std_logic; -- Delay8sclrGND:output -> Delay8:sclr
signal delay7sclrgnd_output_wire : std_logic; -- Delay7sclrGND:output -> Delay7:sclr
signal decoder7sclrgnd_output_wire : std_logic; -- Decoder7sclrGND:output -> Decoder7:sclr
signal decoder7enavcc_output_wire : std_logic; -- Decoder7enaVCC:output -> Decoder7:ena
signal delay10sclrgnd_output_wire : std_logic; -- Delay10sclrGND:output -> Delay10:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal decoder6sclrgnd_output_wire : std_logic; -- Decoder6sclrGND:output -> Decoder6:sclr
signal decoder6enavcc_output_wire : std_logic; -- Decoder6enaVCC:output -> Decoder6:ena
signal delay11sclrgnd_output_wire : std_logic; -- Delay11sclrGND:output -> Delay11:sclr
signal decoder5sclrgnd_output_wire : std_logic; -- Decoder5sclrGND:output -> Decoder5:sclr
signal decoder5enavcc_output_wire : std_logic; -- Decoder5enaVCC:output -> Decoder5:ena
signal decoder4sclrgnd_output_wire : std_logic; -- Decoder4sclrGND:output -> Decoder4:sclr
signal decoder4enavcc_output_wire : std_logic; -- Decoder4enaVCC:output -> Decoder4:ena
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Bus_Conversion8:input]
signal bus_conversion8_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion8:output -> Delay10:input
signal delay10_output_wire : std_logic_vector(15 downto 0); -- Delay10:output -> Delay11:input
signal bus_conversion1_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion1:output -> Delay4:input
signal delay4_output_wire : std_logic_vector(15 downto 0); -- Delay4:output -> Delay5:input
signal bus_conversion2_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion2:output -> Delay6:input
signal delay6_output_wire : std_logic_vector(15 downto 0); -- Delay6:output -> Delay7:input
signal bus_conversion3_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion3:output -> Delay8:input
signal delay8_output_wire : std_logic_vector(15 downto 0); -- Delay8:output -> Delay9:input
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator1:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator1:data1, Logical_Bit_Operator4:data1, Logical_Bit_Operator6:data1, Logical_Bit_Operator8:data1]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay4:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay5:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay6:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay7:ena
signal decoder4_dec_wire : std_logic; -- Decoder4:dec -> Logical_Bit_Operator6:data0
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Delay8:ena
signal decoder5_dec_wire : std_logic; -- Decoder5:dec -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Delay9:ena
signal decoder6_dec_wire : std_logic; -- Decoder6:dec -> Logical_Bit_Operator8:data0
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Delay10:ena
signal decoder7_dec_wire : std_logic; -- Decoder7:dec -> Logical_Bit_Operator9:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Delay11:ena
signal delay5_output_wire : std_logic_vector(15 downto 0); -- Delay5:output -> vertex_col_0:input
signal delay7_output_wire : std_logic_vector(15 downto 0); -- Delay7:output -> vertex_row_0:input
signal delay9_output_wire : std_logic_vector(15 downto 0); -- Delay9:output -> width_0:input
signal delay11_output_wire : std_logic_vector(15 downto 0); -- Delay11:output -> height_0:input
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> [cast0:input, cast1:input, cast2:input, cast3:input]
signal cast0_output_wire : std_logic_vector(1 downto 0); -- cast0:output -> Decoder:data
signal cast1_output_wire : std_logic_vector(1 downto 0); -- cast1:output -> Decoder2:data
signal cast2_output_wire : std_logic_vector(1 downto 0); -- cast2:output -> Decoder4:data
signal cast3_output_wire : std_logic_vector(1 downto 0); -- cast3:output -> Decoder6:data
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder4:aclr, Decoder5:aclr, Decoder6:aclr, Decoder7:aclr, Decoder:aclr, Delay10:aclr, Delay11:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay7:aclr, Delay8:aclr, Delay9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder4:clock, Decoder5:clock, Decoder6:clock, Decoder7:clock, Decoder:clock, Delay10:clock, Delay11:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay7:clock, Delay8:clock, Delay9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
vertex_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay7_output_wire, -- input.wire
output => vertex_row -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => open, -- data0.wire
data1 => decoder5_dec_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => decoder4_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
vertex_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay5_output_wire, -- input.wire
output => vertex_col -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => open, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay11_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => open, -- data0.wire
data1 => decoder7_dec_wire -- data1.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => decoder6_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => open, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast1_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => open, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => open, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay9_output_wire, -- input.wire
output => width -- output.wire
);
delay6 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => bus_conversion2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNXULFMRSU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000001111111",
width => 16
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNXULFMRSU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000001111111",
width => 16
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay9 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => delay8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay9_output_wire, -- output.wire
sclr => delay9sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator7_result_wire -- ena.wire
);
delay9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay9sclrgnd_output_wire -- output.wire
);
delay8 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => bus_conversion3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay8_output_wire, -- output.wire
sclr => delay8sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator6_result_wire -- ena.wire
);
delay8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay8sclrgnd_output_wire -- output.wire
);
delay7 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => delay6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay7_output_wire, -- output.wire
sclr => delay7sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay7sclrgnd_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
decoder7 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => open, -- data.wire
dec => decoder7_dec_wire, -- dec.wire
sclr => decoder7sclrgnd_output_wire, -- sclr.wire
ena => decoder7enavcc_output_wire -- ena.wire
);
decoder7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder7sclrgnd_output_wire -- output.wire
);
decoder7enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder7enavcc_output_wire -- output.wire
);
delay10 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => bus_conversion8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay10_output_wire, -- output.wire
sclr => delay10sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator8_result_wire -- ena.wire
);
delay10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay10sclrgnd_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNEQGKKPXW
generic map (
decode => "10",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
decoder6 : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast3_output_wire, -- data.wire
dec => decoder6_dec_wire, -- dec.wire
sclr => decoder6sclrgnd_output_wire, -- sclr.wire
ena => decoder6enavcc_output_wire -- ena.wire
);
decoder6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder6sclrgnd_output_wire -- output.wire
);
decoder6enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder6enavcc_output_wire -- output.wire
);
delay11 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => delay10_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay11_output_wire, -- output.wire
sclr => delay11sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator9_result_wire -- ena.wire
);
delay11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay11sclrgnd_output_wire -- output.wire
);
decoder5 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => open, -- data.wire
dec => decoder5_dec_wire, -- dec.wire
sclr => decoder5sclrgnd_output_wire, -- sclr.wire
ena => decoder5enavcc_output_wire -- ena.wire
);
decoder5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder5sclrgnd_output_wire -- output.wire
);
decoder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder5enavcc_output_wire -- output.wire
);
decoder4 : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast2_output_wire, -- data.wire
dec => decoder4_dec_wire, -- dec.wire
sclr => decoder4sclrgnd_output_wire, -- sclr.wire
ena => decoder4enavcc_output_wire -- ena.wire
);
decoder4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder4sclrgnd_output_wire -- output.wire
);
decoder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder4enavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GNEFMFJW6A
generic map (
round => 0,
saturate => 0
)
port map (
input => addr_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNEFMFJW6A
generic map (
round => 0,
saturate => 0
)
port map (
input => addr_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GNEFMFJW6A
generic map (
round => 0,
saturate => 0
)
port map (
input => addr_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNEFMFJW6A
generic map (
round => 0,
saturate => 0
)
port map (
input => addr_0_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_Subsystem
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : zhilyan@clarkson.edu
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:25:05 PM
-- Design Name:
-- Module Name: ALU4Bit - ALU_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SLT_MUX is
Port ( F_pre : in STD_LOGIC_VECTOR (31 downto 0); -- before merge in the slt
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
Overflow : in STD_LOGIC;
SltOpVal : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (31 downto 0)); --after merge in the slt
end SLT_MUX;
architecture SLTM_Func of SLT_MUX is
signal SltOpVal_wire : STD_LOGIC; -- set less than operation valid, valid is 1
signal Set : STD_LOGIC; -- set when the sign of the F_pre xor overflow is 1
--Because 0 in 32bit is 0000_0000_0000_0000_0000_0000_0000_0000, sign bit is 0.
--When A = B, result of subject is 0, will not Set.
begin
SltOpVal_wire <= (not P3) and P2 and P1 and P0;
SltOpVal <= SltOpVal_wire;
Set <= F_pre(31) xor Overflow; -- operand A less than operand B
F(31) <= (not SltOpVal_wire) and F_pre(31);
F(30) <= (not SltOpVal_wire) and F_pre(30);
F(29) <= (not SltOpVal_wire) and F_pre(29);
F(28) <= (not SltOpVal_wire) and F_pre(28);
F(27) <= (not SltOpVal_wire) and F_pre(27);
F(26) <= (not SltOpVal_wire) and F_pre(26);
F(25) <= (not SltOpVal_wire) and F_pre(25);
F(24) <= (not SltOpVal_wire) and F_pre(24);
F(23) <= (not SltOpVal_wire) and F_pre(23);
F(22) <= (not SltOpVal_wire) and F_pre(22);
F(21) <= (not SltOpVal_wire) and F_pre(21);
F(20) <= (not SltOpVal_wire) and F_pre(20);
F(19) <= (not SltOpVal_wire) and F_pre(19);
F(18) <= (not SltOpVal_wire) and F_pre(18);
F(17) <= (not SltOpVal_wire) and F_pre(17);
F(16) <= (not SltOpVal_wire) and F_pre(16);
F(15) <= (not SltOpVal_wire) and F_pre(15);
F(14) <= (not SltOpVal_wire) and F_pre(14);
F(13) <= (not SltOpVal_wire) and F_pre(13);
F(12) <= (not SltOpVal_wire) and F_pre(12);
F(11) <= (not SltOpVal_wire) and F_pre(11);
F(10) <= (not SltOpVal_wire) and F_pre(10);
F(9) <= (not SltOpVal_wire) and F_pre(9);
F(8) <= (not SltOpVal_wire) and F_pre(8);
F(7) <= (not SltOpVal_wire) and F_pre(7);
F(6) <= (not SltOpVal_wire) and F_pre(6);
F(5) <= (not SltOpVal_wire) and F_pre(5);
F(4) <= (not SltOpVal_wire) and F_pre(4);
F(3) <= (not SltOpVal_wire) and F_pre(3);
F(2) <= (not SltOpVal_wire) and F_pre(2);
F(1) <= (not SltOpVal_wire) and F_pre(1);
F(0) <= (SltOpVal_wire and Set) or ((not SltOpVal_wire) and F_pre(0));
end SLTM_Func;
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : zhilyan@clarkson.edu
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:25:05 PM
-- Design Name:
-- Module Name: ALU4Bit - ALU_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SLT_MUX is
Port ( F_pre : in STD_LOGIC_VECTOR (31 downto 0); -- before merge in the slt
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
Overflow : in STD_LOGIC;
SltOpVal : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (31 downto 0)); --after merge in the slt
end SLT_MUX;
architecture SLTM_Func of SLT_MUX is
signal SltOpVal_wire : STD_LOGIC; -- set less than operation valid, valid is 1
signal Set : STD_LOGIC; -- set when the sign of the F_pre xor overflow is 1
--Because 0 in 32bit is 0000_0000_0000_0000_0000_0000_0000_0000, sign bit is 0.
--When A = B, result of subject is 0, will not Set.
begin
SltOpVal_wire <= (not P3) and P2 and P1 and P0;
SltOpVal <= SltOpVal_wire;
Set <= F_pre(31) xor Overflow; -- operand A less than operand B
F(31) <= (not SltOpVal_wire) and F_pre(31);
F(30) <= (not SltOpVal_wire) and F_pre(30);
F(29) <= (not SltOpVal_wire) and F_pre(29);
F(28) <= (not SltOpVal_wire) and F_pre(28);
F(27) <= (not SltOpVal_wire) and F_pre(27);
F(26) <= (not SltOpVal_wire) and F_pre(26);
F(25) <= (not SltOpVal_wire) and F_pre(25);
F(24) <= (not SltOpVal_wire) and F_pre(24);
F(23) <= (not SltOpVal_wire) and F_pre(23);
F(22) <= (not SltOpVal_wire) and F_pre(22);
F(21) <= (not SltOpVal_wire) and F_pre(21);
F(20) <= (not SltOpVal_wire) and F_pre(20);
F(19) <= (not SltOpVal_wire) and F_pre(19);
F(18) <= (not SltOpVal_wire) and F_pre(18);
F(17) <= (not SltOpVal_wire) and F_pre(17);
F(16) <= (not SltOpVal_wire) and F_pre(16);
F(15) <= (not SltOpVal_wire) and F_pre(15);
F(14) <= (not SltOpVal_wire) and F_pre(14);
F(13) <= (not SltOpVal_wire) and F_pre(13);
F(12) <= (not SltOpVal_wire) and F_pre(12);
F(11) <= (not SltOpVal_wire) and F_pre(11);
F(10) <= (not SltOpVal_wire) and F_pre(10);
F(9) <= (not SltOpVal_wire) and F_pre(9);
F(8) <= (not SltOpVal_wire) and F_pre(8);
F(7) <= (not SltOpVal_wire) and F_pre(7);
F(6) <= (not SltOpVal_wire) and F_pre(6);
F(5) <= (not SltOpVal_wire) and F_pre(5);
F(4) <= (not SltOpVal_wire) and F_pre(4);
F(3) <= (not SltOpVal_wire) and F_pre(3);
F(2) <= (not SltOpVal_wire) and F_pre(2);
F(1) <= (not SltOpVal_wire) and F_pre(1);
F(0) <= (SltOpVal_wire and Set) or ((not SltOpVal_wire) and F_pre(0));
end SLTM_Func;
|
library verilog;
use verilog.vl_types.all;
entity altsqrt is
generic(
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt"
);
port(
radical : in vl_logic_vector;
clk : in vl_logic;
ena : in vl_logic;
aclr : in vl_logic;
q : out vl_logic_vector;
remainder : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of q_port_width : constant is 1;
attribute mti_svvh_generic_type of r_port_width : constant is 1;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altsqrt;
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BlinkTb is
end BlinkTb;
-- Testes funcionais à entidade Blink.
architecture Stimulus of BlinkTb is
signal s_clock, s_load, s_enable : std_logic;
signal s_numberIn, s_numberOut : std_logic_vector(3 downto 0);
begin
uut: entity work.Blink(Behavioral)
port map(clock => s_clock,
enable => s_enable,
numberIn => s_numberIn,
numberOut => s_numberOut,
load => s_load);
clk_proc:process
begin
s_clock <= '1';
wait for 10 ns;
s_clock <= '0';
wait for 10 ns;
end process;
comb_proc:process
begin
s_load <= '1';
s_numberIn <= "1010";
s_enable <= '1';
wait for 100 ns;
s_enable <= '0';
wait for 35 ns;
end process;
end Stimulus; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Vactcapofkplusone;
architecture struct of kn_kalman_Vactcapofkplusone is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
signal Z2 : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vrefofkplusone, datab => Vactcapdashofkplusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => Z1, datab => Kofkplusone, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Vactcapdashofkplusone, datab => Z2, result => Vactcapofkplusone);
end struct;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 6 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano6 is
generic (
g_report_file_name : string := "work/usb_test_nano6.rpt"
);
end entity;
architecture arch of usb_test_nano6 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
interrupt => interrupt,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable data : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable pipe : integer;
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1';
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
sctb_trace("Fifo read: " & hstr(data));
result := data;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path:path", g_report_file_name);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
sctb_open_region("Testing In request and out request at the same time, using split", 0);
io_write_word(Command_SplitCtl, X"8132"); -- Hub Address 1, Port 2, Speed = FS, EP = interrupt
io_write_word(Command_DevEP, X"0004");
io_write_word(Command_MaxTrans, X"0100");
io_write_word(Command_Length, X"0400");
io_write_word(Command_MemHi, X"0005");
io_write_word(Command_MemLo, X"0000");
io_write_word(c_nano_numpipes, X"0002" ); -- Set active pipes to 2
io_write_word(Command_SplitCtl + Command_Size, X"8132"); -- Hub Address 1, Port 2, Speed = FS, EP = interrupt
io_write_word(Command_DevEP + Command_Size, X"0005");
io_write_word(Command_MaxTrans + Command_Size, X"0200");
io_write_word(Command_Length + Command_Size, X"0600");
io_write_word(Command_MemHi + Command_Size, X"0004");
io_write_word(Command_MemLo + Command_Size, X"0000");
io_write_word(Command + Command_Size, X"8041"); -- out with mem read
io_write_word(Command, X"4042"); -- in with mem write
read_attr_fifo(data);
pipe := Command_size * to_integer(unsigned(data));
io_read_word(Command_Result + pipe, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length + pipe, data);
sctb_trace("Command length: " & hstr(data));
sctb_check(data, X"0000", "All data should have been transferred.");
read_attr_fifo(data);
pipe := Command_size * to_integer(unsigned(data));
io_read_word(Command_Result + pipe, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length + pipe, data);
sctb_trace("Command length: " & hstr(data));
sctb_check(data, X"0000", "All data should have been transferred.");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
-- restart; mem load -infile nano_code.hex -format hex /usb_test_nano4/i_harness/i_host/i_nano/i_buf_ram/mem; run 1100 us |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2103.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02103ent IS
END c07s02b04x00p20n01i02103ent;
ARCHITECTURE c07s02b04x00p20n01i02103arch OF c07s02b04x00p20n01i02103ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_8 is positive_v (1 to 8);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
alias l_alias : positive_v (1 to 2) is l_operand (2 to 3);
alias r_alias : positive_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT(result = ( 89 , 1 , 1 , 1 ))
report "***PASSED TEST: c07s02b04x00p20n01i02103"
severity NOTE;
assert (result = ( 89 , 1 , 1 , 1 ))
report "***FAILED TEST: c07s02b04x00p20n01i02103 - Concatenation of two RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02103arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2103.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02103ent IS
END c07s02b04x00p20n01i02103ent;
ARCHITECTURE c07s02b04x00p20n01i02103arch OF c07s02b04x00p20n01i02103ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_8 is positive_v (1 to 8);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
alias l_alias : positive_v (1 to 2) is l_operand (2 to 3);
alias r_alias : positive_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT(result = ( 89 , 1 , 1 , 1 ))
report "***PASSED TEST: c07s02b04x00p20n01i02103"
severity NOTE;
assert (result = ( 89 , 1 , 1 , 1 ))
report "***FAILED TEST: c07s02b04x00p20n01i02103 - Concatenation of two RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02103arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2103.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02103ent IS
END c07s02b04x00p20n01i02103ent;
ARCHITECTURE c07s02b04x00p20n01i02103arch OF c07s02b04x00p20n01i02103ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_8 is positive_v (1 to 8);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
alias l_alias : positive_v (1 to 2) is l_operand (2 to 3);
alias r_alias : positive_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT(result = ( 89 , 1 , 1 , 1 ))
report "***PASSED TEST: c07s02b04x00p20n01i02103"
severity NOTE;
assert (result = ( 89 , 1 , 1 , 1 ))
report "***FAILED TEST: c07s02b04x00p20n01i02103 - Concatenation of two RECORD arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02103arch;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04900_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of clock signal: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_04900_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_04900_good;
--CODE
architecture Behavioral of CNE_04900_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop:process(i_Clock, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable='1') then -- D Flip-Flop enabled
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:51:10 01/07/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab-master/dma/tb_dma_rx.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma_rx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma_rx IS
END tb_dma_rx;
ARCHITECTURE behavior OF tb_dma_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma_rx
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : OUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Start_RX : IN std_logic;
End_RX : OUT std_logic;
DataIn : IN std_logic_vector(7 downto 0);
Read_DI : OUT std_logic;
Empty : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Start_RX : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := X"AA";
signal Empty : std_logic := '1';
--Outputs
signal Databus : std_logic_vector(7 downto 0);
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal End_RX : std_logic;
signal Read_DI : std_logic;
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma_rx PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Start_RX => Start_RX,
End_RX => End_RX,
DataIn => DataIn,
Read_DI => Read_DI,
Empty => Empty
);
-- Clock process definitions
Clk <= not Clk after Clk_period;
-- Stimulus
Reset <= '1' after 100 ns;
Empty <= '1', '0' after 100 ns, '1' after 300 ns, '0' after 350 ns, '1' after 500 ns,
'0' after 650 ns;
Start_RX <= '0', '1' after 150 ns, '0' after 175 ns, '1' after 400 ns, '0' after 425 ns,
'1' after 600 ns, '0' after 625 ns, '1' after 700 ns, '0' after 725 ns;
END;
|
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clock : in std_logic;
rstn : in std_logic;
enable : in std_logic;
-- mode : in std_logic;
cnt_out : out std_logic_vector(9 downto 0)
);
end;
architecture logica of counter is
signal count : std_logic_vector(9 downto 0);
begin
process(clock, rstn, enable)
begin
if rstn = '0' then
count <= (others => '0');
elsif rising_edge(clock) and enable = '1' then
-- case mode is
-- when '1' =>
case count is
when "1111100111" => count <= "1111100111";
when OTHERS => count <= count+1;
end case;
-- when '0' =>
-- case count is
-- when "0000000000" => count <= "0000000000";
-- when OTHERS => count <= count-1;
-- end case;
-- end case;
end if;
end process;
cnt_out <= count;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
entity ControlUnit is
generic (BitWidth: integer;
InstructionWidth: integer);
port(
rst : in std_logic;
clk : in std_logic;
----------------------------------------
Instr_In : in std_logic_vector (InstructionWidth-1 downto 0);
Instr_Add : out std_logic_vector (BitWidth-1 downto 0);
----------------------------------------
MemRdAddress : out std_logic_vector (BitWidth-1 downto 0);
MemWrtAddress: out std_logic_vector (BitWidth-1 downto 0);
Mem_RW : out std_logic;
----------------------------------------
DPU_Flags : in std_logic_vector (3 downto 0);
DataToDPU : out std_logic_vector (BitWidth-1 downto 0);
CommandToDPU : out std_logic_vector (10 downto 0);
Reg_in_sel : out std_logic_vector (7 downto 0);
Reg_out_sel : out std_logic_vector (2 downto 0);
DataFromDPU : in std_logic_vector (BitWidth-1 downto 0)
);
end ControlUnit;
architecture RTL of ControlUnit is
---------------------------------------------
-- Signals and Types
---------------------------------------------
TYPE STATE_TYPE IS (F, D, Ex,WB);
signal State_in, State_out :STATE_TYPE;
TYPE Instruction IS (PUSH,POP,
JMPEQ,Jmp_rel,Jmp,JmpZ,JmpOV,JmpC,
FlipA,And_A_R,OR_A_R,XOR_A_R,NegA,
ShiftA_R,ShiftA_L,ShiftArithL,ShiftArithR,
RRC,RLC,
LoadPC,SavePC,
Add_A_R, Add_A_Mem,Add_A_Dir, Sub_A_R,Sub_A_Mem,Sub_A_Dir,IncA,DecA,
Load_A_Mem,Load_R0_Mem,Load_R0_Dir,Store_A_Mem,load_A_R,load_R_A,Load_Ind_A,
ClearZ,ClearOV,ClearC, ClearACC,
NOP,HALT);
signal Instr:Instruction := NOP;
signal SP_in, SP_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0');
signal PC_in, PC_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0');
signal InstrReg_out: std_logic_vector (InstructionWidth-1 downto 0) := (others => '0');
---------------------------------------------
-- OpCode Aliases
---------------------------------------------
alias opcpde : std_logic_vector (5 downto 0) is InstrReg_out (InstructionWidth-1 downto BitWidth);
begin
---------------------------------------------
-- Registers setting
---------------------------------------------
process (clk,rst)
begin
if rst = '1' then
State_out <= F;
SP_out <= (others => '0');
PC_out <= (others => '0');
InstrReg_out <= (others => '0');
elsif clk'event and clk='1' then
State_out <= State_in;
SP_out <= SP_in;
PC_out <= PC_in;
InstrReg_out <= Instr_In;
end if;
end process;
---------------------------------------------
-----------------------------------------------------------
--Control FSM
-----------------------------------------------------------
process(State_out,PC_out,Instr,InstrReg_out,DataFromDPU, SP_out, DPU_Flags)
begin
SP_in <= SP_out;
PC_in <= PC_out;
Instr_Add <= PC_out;
Mem_RW <= '0';
MemRdAddress <= (others => '0');
MemWrtAddress <= (others => '0');
DataToDPU <= (others => '0');
CommandToDPU <= "00000001000"; --do not do anything
Reg_in_sel<="00000000";
Reg_out_sel<="000";
case State_out IS
--Fetch--------------------------------------------------------------------------
WHEN F =>
State_in <= D;
--Decode-------------------------------------------------------------------------
WHEN D =>
State_in <= Ex;
--Execution------------------------------------------------------------------------
WHEN Ex =>
State_in <= WB;
-----------------------Arithmetic--------------------------
if Instr = Add_A_R then
CommandToDPU <= "00000000010";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr = Add_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000000";
elsif Instr = Add_A_Dir then
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000001";
-----------------------------------------------
elsif Instr = Sub_A_R then
CommandToDPU <= "00000000110";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr = Sub_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000100";
elsif Instr = Sub_A_Dir then
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000101";
-----------------------------------------------
elsif Instr = IncA then
CommandToDPU <= "00000000011";
elsif Instr = DecA then
CommandToDPU <= "00000000111";
-----------------------Shift-------------------------------
elsif Instr = ShiftA_R then
CommandToDPU <= "00000011100";
elsif Instr = ShiftA_L then
CommandToDPU <= "00000100000";
elsif Instr = ShiftArithL then
CommandToDPU <= "00000101100";
elsif Instr = ShiftArithR then
CommandToDPU <= "00000101000";
elsif Instr = RRC then
CommandToDPU <= "00000111000";
elsif Instr = RLC then
CommandToDPU <= "00000111100";
-----------------------Logical-----------------------------
elsif Instr = NegA then
CommandToDPU <= "00000100100";
elsif Instr = FlipA then
CommandToDPU <= "00000110000";
elsif Instr = And_A_R then
CommandToDPU <= "00000010010";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr = OR_A_R then
CommandToDPU <= "00000010110";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr = XOR_A_R then
CommandToDPU <= "00000011010";
Reg_out_sel<= InstrReg_out (2 downto 0);
-----------------------Memory------------------------------
elsif Instr = Load_R0_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
Mem_RW <= '0';
CommandToDPU <= "11000001000";
Reg_in_sel<= "00000001";
elsif Instr = Load_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
Mem_RW <= '0';
CommandToDPU <= "00000001100";
elsif Instr = SavePC then
DataToDPU <= PC_out;
CommandToDPU <= "00000001101";
elsif Instr = Load_R0_Dir then
CommandToDPU <= "01000001000";
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
Reg_in_sel<= "00000001";
Reg_out_sel<= "000";
elsif Instr = Load_Ind_A then
MemRdAddress <= DataFromDPU;
Mem_RW <= '0';
CommandToDPU <= "00000001100";
Reg_in_sel<= "00000000";
Reg_out_sel<= "000";
elsif Instr = load_A_R then
CommandToDPU <= "00000001100";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr = load_R_A then
CommandToDPU <= "10000001000";
Reg_in_sel<= InstrReg_out (7 downto 0);
-----------------------Stack-------------------------------
elsif Instr = POP then
MemRdAddress <= SP_out - "00000001";
SP_in <= SP_out - 1;
Mem_RW <= '0';
CommandToDPU <= "00000001100";
-----------------------ClearFlags--------------------------
elsif Instr = ClearZ then
CommandToDPU <= "00001001000";
elsif Instr = ClearOV then
CommandToDPU <= "00010001000";
elsif Instr = ClearC then
CommandToDPU <= "00100001000";
elsif Instr = ClearACC then
CommandToDPU <= "00000110100";
else
CommandToDPU <= "00000001000"; --do not do anything
end if;
--WriteBack------------------------------------------------------------------------
WHEN WB =>
State_in <= F;
if Instr = Store_A_Mem then
MemWrtAddress <= InstrReg_out (BitWidth-1 downto 0);
Mem_RW <= '1';
PC_in <= PC_out+1;
elsif Instr = HALT then
PC_in <= PC_out;
State_in <= WB;
-----------------------Jump--------------------------------
elsif Instr = Jmp then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
elsif Instr = JmpOV and DPU_Flags(0) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
elsif Instr = JmpZ and DPU_Flags(1) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
elsif Instr = JMPEQ and DPU_Flags(2) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
elsif Instr = JmpC and DPU_Flags(3) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
elsif Instr= Jmp_rel then
PC_in <= PC_out + InstrReg_out (BitWidth-1 downto 0);
elsif Instr= LoadPC then
PC_in <= DataFromDPU ;
State_in <= F;
-----------------------Stack OP----------------------------
elsif Instr= PUSH then
PC_in <= PC_out+1;
MemWrtAddress <= SP_out;
SP_in <= SP_out + 1;
Mem_RW <= '1';
else
PC_in <= PC_out+1;
end if;
END case;
end process;
------------------------------------------------
-- Instr decoder
------------------------------------------------
process (opcpde)
begin
case opcpde is
when "000000" => Instr <= Add_A_R;
when "000001" => Instr <= Add_A_Mem;
when "000010" => Instr <= Add_A_Dir;
when "000011" => Instr <= Sub_A_R;
when "000100" => Instr <= Sub_A_Mem;
when "000101" => Instr <= Sub_A_Dir;
when "000110" => Instr <= IncA;
when "000111" => Instr <= DecA;
when "001000" => Instr <= ShiftArithR;
when "001001" => Instr <= ShiftArithL;
when "001010" => Instr <= ShiftA_R;
when "001011" => Instr <= ShiftA_L;
when "001100" => Instr <= RRC;
when "001101" => Instr <= RLC;
when "001110" => Instr <= And_A_R;
when "001111" => Instr <= OR_A_R;
when "010000" => Instr <= XOR_A_R;
when "010001" => Instr <= FlipA;
when "010010" => Instr <= NegA;
when "010011" => Instr <= Jmp;
when "010100" => Instr <= JmpZ;
when "010101" => Instr <= JmpOV;
when "010110" => Instr <= JmpC;
when "010111" => Instr <= Jmp_rel;
when "011000" => Instr <= JMPEQ;
when "011001" => Instr <= ClearZ;
when "011010" => Instr <= ClearOV;
when "011011" => Instr <= ClearC;
when "011100" => Instr <= ClearACC;
when "011101" => Instr <= LoadPC;
when "011110" => Instr <= SavePC;
when "011111" => Instr <= Load_A_Mem;
when "100000" => Instr <= Store_A_Mem;
when "100001" => Instr <= Load_R0_Dir;
when "100010" => Instr <= Load_R0_Mem;
when "100011" => Instr <= load_A_R;
when "100100" => Instr <= load_R_A;
when "100101" => Instr <= Load_Ind_A ;
when "111100" => Instr <= PUSH;
when "111101" => Instr <= POP;
when "111110" => Instr <= NOP;
when "111111" => Instr <= HALT;
when others => Instr <= NOP;
end case;
end process;
end RTL;
|
-------------------------------------------------------------------------------
-- hard_ethernet_mac_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_ll_temac_v2_03_a;
use xps_ll_temac_v2_03_a.all;
entity hard_ethernet_mac_wrapper is
port (
TemacIntc0_Irpt : out std_logic;
TemacIntc1_Irpt : out std_logic;
TemacPhy_RST_n : out std_logic;
GTX_CLK_0 : in std_logic;
MGTCLK_P : in std_logic;
MGTCLK_N : in std_logic;
REFCLK : in std_logic;
DCLK : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Core_Clk : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0);
LlinkTemac0_CLK : in std_logic;
LlinkTemac0_RST : in std_logic;
LlinkTemac0_SOP_n : in std_logic;
LlinkTemac0_EOP_n : in std_logic;
LlinkTemac0_SOF_n : in std_logic;
LlinkTemac0_EOF_n : in std_logic;
LlinkTemac0_REM : in std_logic_vector(0 to 3);
LlinkTemac0_Data : in std_logic_vector(0 to 31);
LlinkTemac0_SRC_RDY_n : in std_logic;
Temac0Llink_DST_RDY_n : out std_logic;
Temac0Llink_SOP_n : out std_logic;
Temac0Llink_EOP_n : out std_logic;
Temac0Llink_SOF_n : out std_logic;
Temac0Llink_EOF_n : out std_logic;
Temac0Llink_REM : out std_logic_vector(0 to 3);
Temac0Llink_Data : out std_logic_vector(0 to 31);
Temac0Llink_SRC_RDY_n : out std_logic;
LlinkTemac0_DST_RDY_n : in std_logic;
LlinkTemac1_CLK : in std_logic;
LlinkTemac1_RST : in std_logic;
LlinkTemac1_SOP_n : in std_logic;
LlinkTemac1_EOP_n : in std_logic;
LlinkTemac1_SOF_n : in std_logic;
LlinkTemac1_EOF_n : in std_logic;
LlinkTemac1_REM : in std_logic_vector(0 to 3);
LlinkTemac1_Data : in std_logic_vector(0 to 31);
LlinkTemac1_SRC_RDY_n : in std_logic;
Temac1Llink_DST_RDY_n : out std_logic;
Temac1Llink_SOP_n : out std_logic;
Temac1Llink_EOP_n : out std_logic;
Temac1Llink_SOF_n : out std_logic;
Temac1Llink_EOF_n : out std_logic;
Temac1Llink_REM : out std_logic_vector(0 to 3);
Temac1Llink_Data : out std_logic_vector(0 to 31);
Temac1Llink_SRC_RDY_n : out std_logic;
LlinkTemac1_DST_RDY_n : in std_logic;
MII_TXD_0 : out std_logic_vector(3 downto 0);
MII_TX_EN_0 : out std_logic;
MII_TX_ER_0 : out std_logic;
MII_RXD_0 : in std_logic_vector(3 downto 0);
MII_RX_DV_0 : in std_logic;
MII_RX_ER_0 : in std_logic;
MII_RX_CLK_0 : in std_logic;
MII_TX_CLK_0 : in std_logic;
MII_TXD_1 : out std_logic_vector(3 downto 0);
MII_TX_EN_1 : out std_logic;
MII_TX_ER_1 : out std_logic;
MII_RXD_1 : in std_logic_vector(3 downto 0);
MII_RX_DV_1 : in std_logic;
MII_RX_ER_1 : in std_logic;
MII_RX_CLK_1 : in std_logic;
MII_TX_CLK_1 : in std_logic;
GMII_TXD_0 : out std_logic_vector(7 downto 0);
GMII_TX_EN_0 : out std_logic;
GMII_TX_ER_0 : out std_logic;
GMII_TX_CLK_0 : out std_logic;
GMII_RXD_0 : in std_logic_vector(7 downto 0);
GMII_RX_DV_0 : in std_logic;
GMII_RX_ER_0 : in std_logic;
GMII_RX_CLK_0 : in std_logic;
GMII_TXD_1 : out std_logic_vector(7 downto 0);
GMII_TX_EN_1 : out std_logic;
GMII_TX_ER_1 : out std_logic;
GMII_TX_CLK_1 : out std_logic;
GMII_RXD_1 : in std_logic_vector(7 downto 0);
GMII_RX_DV_1 : in std_logic;
GMII_RX_ER_1 : in std_logic;
GMII_RX_CLK_1 : in std_logic;
TXP_0 : out std_logic;
TXN_0 : out std_logic;
RXP_0 : in std_logic;
RXN_0 : in std_logic;
TXP_1 : out std_logic;
TXN_1 : out std_logic;
RXP_1 : in std_logic;
RXN_1 : in std_logic;
RGMII_TXD_0 : out std_logic_vector(3 downto 0);
RGMII_TX_CTL_0 : out std_logic;
RGMII_TXC_0 : out std_logic;
RGMII_RXD_0 : in std_logic_vector(3 downto 0);
RGMII_RX_CTL_0 : in std_logic;
RGMII_RXC_0 : in std_logic;
RGMII_TXD_1 : out std_logic_vector(3 downto 0);
RGMII_TX_CTL_1 : out std_logic;
RGMII_TXC_1 : out std_logic;
RGMII_RXD_1 : in std_logic_vector(3 downto 0);
RGMII_RX_CTL_1 : in std_logic;
RGMII_RXC_1 : in std_logic;
MDC_0 : out std_logic;
MDC_1 : out std_logic;
HostMiimRdy : in std_logic;
HostRdData : in std_logic_vector(31 downto 0);
HostMiimSel : out std_logic;
HostReq : out std_logic;
HostAddr : out std_logic_vector(9 downto 0);
HostEmac1Sel : out std_logic;
Temac0AvbTxClk : out std_logic;
Temac0AvbTxClkEn : out std_logic;
Temac0AvbRxClk : out std_logic;
Temac0AvbRxClkEn : out std_logic;
Avb2Mac0TxData : in std_logic_vector(7 downto 0);
Avb2Mac0TxDataValid : in std_logic;
Avb2Mac0TxUnderrun : in std_logic;
Mac02AvbTxAck : out std_logic;
Mac02AvbRxData : out std_logic_vector(7 downto 0);
Mac02AvbRxDataValid : out std_logic;
Mac02AvbRxFrameGood : out std_logic;
Mac02AvbRxFrameBad : out std_logic;
Temac02AvbTxData : out std_logic_vector(7 downto 0);
Temac02AvbTxDataValid : out std_logic;
Temac02AvbTxUnderrun : out std_logic;
Avb2Temac0TxAck : in std_logic;
Avb2Temac0RxData : in std_logic_vector(7 downto 0);
Avb2Temac0RxDataValid : in std_logic;
Avb2Temac0RxFrameGood : in std_logic;
Avb2Temac0RxFrameBad : in std_logic;
Temac1AvbTxClk : out std_logic;
Temac1AvbTxClkEn : out std_logic;
Temac1AvbRxClk : out std_logic;
Temac1AvbRxClkEn : out std_logic;
Avb2Mac1TxData : in std_logic_vector(7 downto 0);
Avb2Mac1TxDataValid : in std_logic;
Avb2Mac1TxUnderrun : in std_logic;
Mac12AvbTxAck : out std_logic;
Mac12AvbRxData : out std_logic_vector(7 downto 0);
Mac12AvbRxDataValid : out std_logic;
Mac12AvbRxFrameGood : out std_logic;
Mac12AvbRxFrameBad : out std_logic;
Temac12AvbTxData : out std_logic_vector(7 downto 0);
Temac12AvbTxDataValid : out std_logic;
Temac12AvbTxUnderrun : out std_logic;
Avb2Temac1TxAck : in std_logic;
Avb2Temac1RxData : in std_logic_vector(7 downto 0);
Avb2Temac1RxDataValid : in std_logic;
Avb2Temac1RxFrameGood : in std_logic;
Avb2Temac1RxFrameBad : in std_logic;
TxClientClk_0 : out std_logic;
ClientTxStat_0 : out std_logic;
ClientTxStatsVld_0 : out std_logic;
ClientTxStatsByteVld_0 : out std_logic;
RxClientClk_0 : out std_logic;
ClientRxStats_0 : out std_logic_vector(6 downto 0);
ClientRxStatsVld_0 : out std_logic;
ClientRxStatsByteVld_0 : out std_logic;
TxClientClk_1 : out std_logic;
ClientTxStat_1 : out std_logic;
ClientTxStatsVld_1 : out std_logic;
ClientTxStatsByteVld_1 : out std_logic;
RxClientClk_1 : out std_logic;
ClientRxStats_1 : out std_logic_vector(6 downto 0);
ClientRxStatsVld_1 : out std_logic;
ClientRxStatsByteVld_1 : out std_logic;
MDIO_0_I : in std_logic;
MDIO_0_O : out std_logic;
MDIO_0_T : out std_logic;
MDIO_1_I : in std_logic;
MDIO_1_O : out std_logic;
MDIO_1_T : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of hard_ethernet_mac_wrapper : entity is "xps_ll_temac_v2_03_a";
end hard_ethernet_mac_wrapper;
architecture STRUCTURE of hard_ethernet_mac_wrapper is
component xps_ll_temac is
generic (
C_NUM_IDELAYCTRL : INTEGER;
C_SUBFAMILY : string;
C_RESERVED : INTEGER;
C_FAMILY : STRING;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_INCLUDE_IO : INTEGER;
C_PHY_TYPE : INTEGER;
C_TEMAC1_ENABLED : INTEGER;
C_TEMAC0_TXFIFO : INTEGER;
C_TEMAC0_RXFIFO : INTEGER;
C_TEMAC1_TXFIFO : INTEGER;
C_TEMAC1_RXFIFO : INTEGER;
C_BUS2CORE_CLK_RATIO : INTEGER;
C_TEMAC_TYPE : INTEGER;
C_TEMAC0_TXCSUM : INTEGER;
C_TEMAC0_RXCSUM : INTEGER;
C_TEMAC1_TXCSUM : INTEGER;
C_TEMAC1_RXCSUM : INTEGER;
C_TEMAC0_PHYADDR : std_logic_vector;
C_TEMAC1_PHYADDR : std_logic_vector;
C_TEMAC0_TXVLAN_TRAN : INTEGER;
C_TEMAC0_RXVLAN_TRAN : INTEGER;
C_TEMAC1_TXVLAN_TRAN : INTEGER;
C_TEMAC1_RXVLAN_TRAN : INTEGER;
C_TEMAC0_TXVLAN_TAG : INTEGER;
C_TEMAC0_RXVLAN_TAG : INTEGER;
C_TEMAC1_TXVLAN_TAG : INTEGER;
C_TEMAC1_RXVLAN_TAG : INTEGER;
C_TEMAC0_TXVLAN_STRP : INTEGER;
C_TEMAC0_RXVLAN_STRP : INTEGER;
C_TEMAC1_TXVLAN_STRP : INTEGER;
C_TEMAC1_RXVLAN_STRP : INTEGER;
C_TEMAC0_MCAST_EXTEND : INTEGER;
C_TEMAC1_MCAST_EXTEND : INTEGER;
C_TEMAC0_STATS : INTEGER;
C_TEMAC1_STATS : INTEGER;
C_TEMAC0_AVB : INTEGER;
C_TEMAC1_AVB : INTEGER;
C_SIMULATION : INTEGER
);
port (
TemacIntc0_Irpt : out std_logic;
TemacIntc1_Irpt : out std_logic;
TemacPhy_RST_n : out std_logic;
GTX_CLK_0 : in std_logic;
MGTCLK_P : in std_logic;
MGTCLK_N : in std_logic;
REFCLK : in std_logic;
DCLK : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Core_Clk : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
LlinkTemac0_CLK : in std_logic;
LlinkTemac0_RST : in std_logic;
LlinkTemac0_SOP_n : in std_logic;
LlinkTemac0_EOP_n : in std_logic;
LlinkTemac0_SOF_n : in std_logic;
LlinkTemac0_EOF_n : in std_logic;
LlinkTemac0_REM : in std_logic_vector(0 to 3);
LlinkTemac0_Data : in std_logic_vector(0 to 31);
LlinkTemac0_SRC_RDY_n : in std_logic;
Temac0Llink_DST_RDY_n : out std_logic;
Temac0Llink_SOP_n : out std_logic;
Temac0Llink_EOP_n : out std_logic;
Temac0Llink_SOF_n : out std_logic;
Temac0Llink_EOF_n : out std_logic;
Temac0Llink_REM : out std_logic_vector(0 to 3);
Temac0Llink_Data : out std_logic_vector(0 to 31);
Temac0Llink_SRC_RDY_n : out std_logic;
LlinkTemac0_DST_RDY_n : in std_logic;
LlinkTemac1_CLK : in std_logic;
LlinkTemac1_RST : in std_logic;
LlinkTemac1_SOP_n : in std_logic;
LlinkTemac1_EOP_n : in std_logic;
LlinkTemac1_SOF_n : in std_logic;
LlinkTemac1_EOF_n : in std_logic;
LlinkTemac1_REM : in std_logic_vector(0 to 3);
LlinkTemac1_Data : in std_logic_vector(0 to 31);
LlinkTemac1_SRC_RDY_n : in std_logic;
Temac1Llink_DST_RDY_n : out std_logic;
Temac1Llink_SOP_n : out std_logic;
Temac1Llink_EOP_n : out std_logic;
Temac1Llink_SOF_n : out std_logic;
Temac1Llink_EOF_n : out std_logic;
Temac1Llink_REM : out std_logic_vector(0 to 3);
Temac1Llink_Data : out std_logic_vector(0 to 31);
Temac1Llink_SRC_RDY_n : out std_logic;
LlinkTemac1_DST_RDY_n : in std_logic;
MII_TXD_0 : out std_logic_vector(3 downto 0);
MII_TX_EN_0 : out std_logic;
MII_TX_ER_0 : out std_logic;
MII_RXD_0 : in std_logic_vector(3 downto 0);
MII_RX_DV_0 : in std_logic;
MII_RX_ER_0 : in std_logic;
MII_RX_CLK_0 : in std_logic;
MII_TX_CLK_0 : in std_logic;
MII_TXD_1 : out std_logic_vector(3 downto 0);
MII_TX_EN_1 : out std_logic;
MII_TX_ER_1 : out std_logic;
MII_RXD_1 : in std_logic_vector(3 downto 0);
MII_RX_DV_1 : in std_logic;
MII_RX_ER_1 : in std_logic;
MII_RX_CLK_1 : in std_logic;
MII_TX_CLK_1 : in std_logic;
GMII_TXD_0 : out std_logic_vector(7 downto 0);
GMII_TX_EN_0 : out std_logic;
GMII_TX_ER_0 : out std_logic;
GMII_TX_CLK_0 : out std_logic;
GMII_RXD_0 : in std_logic_vector(7 downto 0);
GMII_RX_DV_0 : in std_logic;
GMII_RX_ER_0 : in std_logic;
GMII_RX_CLK_0 : in std_logic;
GMII_TXD_1 : out std_logic_vector(7 downto 0);
GMII_TX_EN_1 : out std_logic;
GMII_TX_ER_1 : out std_logic;
GMII_TX_CLK_1 : out std_logic;
GMII_RXD_1 : in std_logic_vector(7 downto 0);
GMII_RX_DV_1 : in std_logic;
GMII_RX_ER_1 : in std_logic;
GMII_RX_CLK_1 : in std_logic;
TXP_0 : out std_logic;
TXN_0 : out std_logic;
RXP_0 : in std_logic;
RXN_0 : in std_logic;
TXP_1 : out std_logic;
TXN_1 : out std_logic;
RXP_1 : in std_logic;
RXN_1 : in std_logic;
RGMII_TXD_0 : out std_logic_vector(3 downto 0);
RGMII_TX_CTL_0 : out std_logic;
RGMII_TXC_0 : out std_logic;
RGMII_RXD_0 : in std_logic_vector(3 downto 0);
RGMII_RX_CTL_0 : in std_logic;
RGMII_RXC_0 : in std_logic;
RGMII_TXD_1 : out std_logic_vector(3 downto 0);
RGMII_TX_CTL_1 : out std_logic;
RGMII_TXC_1 : out std_logic;
RGMII_RXD_1 : in std_logic_vector(3 downto 0);
RGMII_RX_CTL_1 : in std_logic;
RGMII_RXC_1 : in std_logic;
MDC_0 : out std_logic;
MDC_1 : out std_logic;
HostMiimRdy : in std_logic;
HostRdData : in std_logic_vector(31 downto 0);
HostMiimSel : out std_logic;
HostReq : out std_logic;
HostAddr : out std_logic_vector(9 downto 0);
HostEmac1Sel : out std_logic;
Temac0AvbTxClk : out std_logic;
Temac0AvbTxClkEn : out std_logic;
Temac0AvbRxClk : out std_logic;
Temac0AvbRxClkEn : out std_logic;
Avb2Mac0TxData : in std_logic_vector(7 downto 0);
Avb2Mac0TxDataValid : in std_logic;
Avb2Mac0TxUnderrun : in std_logic;
Mac02AvbTxAck : out std_logic;
Mac02AvbRxData : out std_logic_vector(7 downto 0);
Mac02AvbRxDataValid : out std_logic;
Mac02AvbRxFrameGood : out std_logic;
Mac02AvbRxFrameBad : out std_logic;
Temac02AvbTxData : out std_logic_vector(7 downto 0);
Temac02AvbTxDataValid : out std_logic;
Temac02AvbTxUnderrun : out std_logic;
Avb2Temac0TxAck : in std_logic;
Avb2Temac0RxData : in std_logic_vector(7 downto 0);
Avb2Temac0RxDataValid : in std_logic;
Avb2Temac0RxFrameGood : in std_logic;
Avb2Temac0RxFrameBad : in std_logic;
Temac1AvbTxClk : out std_logic;
Temac1AvbTxClkEn : out std_logic;
Temac1AvbRxClk : out std_logic;
Temac1AvbRxClkEn : out std_logic;
Avb2Mac1TxData : in std_logic_vector(7 downto 0);
Avb2Mac1TxDataValid : in std_logic;
Avb2Mac1TxUnderrun : in std_logic;
Mac12AvbTxAck : out std_logic;
Mac12AvbRxData : out std_logic_vector(7 downto 0);
Mac12AvbRxDataValid : out std_logic;
Mac12AvbRxFrameGood : out std_logic;
Mac12AvbRxFrameBad : out std_logic;
Temac12AvbTxData : out std_logic_vector(7 downto 0);
Temac12AvbTxDataValid : out std_logic;
Temac12AvbTxUnderrun : out std_logic;
Avb2Temac1TxAck : in std_logic;
Avb2Temac1RxData : in std_logic_vector(7 downto 0);
Avb2Temac1RxDataValid : in std_logic;
Avb2Temac1RxFrameGood : in std_logic;
Avb2Temac1RxFrameBad : in std_logic;
TxClientClk_0 : out std_logic;
ClientTxStat_0 : out std_logic;
ClientTxStatsVld_0 : out std_logic;
ClientTxStatsByteVld_0 : out std_logic;
RxClientClk_0 : out std_logic;
ClientRxStats_0 : out std_logic_vector(6 downto 0);
ClientRxStatsVld_0 : out std_logic;
ClientRxStatsByteVld_0 : out std_logic;
TxClientClk_1 : out std_logic;
ClientTxStat_1 : out std_logic;
ClientTxStatsVld_1 : out std_logic;
ClientTxStatsByteVld_1 : out std_logic;
RxClientClk_1 : out std_logic;
ClientRxStats_1 : out std_logic_vector(6 downto 0);
ClientRxStatsVld_1 : out std_logic;
ClientRxStatsByteVld_1 : out std_logic;
MDIO_0_I : in std_logic;
MDIO_0_O : out std_logic;
MDIO_0_T : out std_logic;
MDIO_1_I : in std_logic;
MDIO_1_O : out std_logic;
MDIO_1_T : out std_logic
);
end component;
begin
Hard_Ethernet_MAC : xps_ll_temac
generic map (
C_NUM_IDELAYCTRL => 0,
C_SUBFAMILY => "FX",
C_RESERVED => 0,
C_FAMILY => "virtex5",
C_BASEADDR => X"83c80000",
C_HIGHADDR => X"83cfffff",
C_SPLB_DWIDTH => 128,
C_SPLB_AWIDTH => 32,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_MID_WIDTH => 1,
C_SPLB_P2P => 0,
C_INCLUDE_IO => 1,
C_PHY_TYPE => 0,
C_TEMAC1_ENABLED => 0,
C_TEMAC0_TXFIFO => 4096,
C_TEMAC0_RXFIFO => 4096,
C_TEMAC1_TXFIFO => 4096,
C_TEMAC1_RXFIFO => 4096,
C_BUS2CORE_CLK_RATIO => 1,
C_TEMAC_TYPE => 0,
C_TEMAC0_TXCSUM => 0,
C_TEMAC0_RXCSUM => 0,
C_TEMAC1_TXCSUM => 0,
C_TEMAC1_RXCSUM => 0,
C_TEMAC0_PHYADDR => B"00001",
C_TEMAC1_PHYADDR => B"00010",
C_TEMAC0_TXVLAN_TRAN => 0,
C_TEMAC0_RXVLAN_TRAN => 0,
C_TEMAC1_TXVLAN_TRAN => 0,
C_TEMAC1_RXVLAN_TRAN => 0,
C_TEMAC0_TXVLAN_TAG => 0,
C_TEMAC0_RXVLAN_TAG => 0,
C_TEMAC1_TXVLAN_TAG => 0,
C_TEMAC1_RXVLAN_TAG => 0,
C_TEMAC0_TXVLAN_STRP => 0,
C_TEMAC0_RXVLAN_STRP => 0,
C_TEMAC1_TXVLAN_STRP => 0,
C_TEMAC1_RXVLAN_STRP => 0,
C_TEMAC0_MCAST_EXTEND => 0,
C_TEMAC1_MCAST_EXTEND => 0,
C_TEMAC0_STATS => 0,
C_TEMAC1_STATS => 0,
C_TEMAC0_AVB => 0,
C_TEMAC1_AVB => 0,
C_SIMULATION => 0
)
port map (
TemacIntc0_Irpt => TemacIntc0_Irpt,
TemacIntc1_Irpt => TemacIntc1_Irpt,
TemacPhy_RST_n => TemacPhy_RST_n,
GTX_CLK_0 => GTX_CLK_0,
MGTCLK_P => MGTCLK_P,
MGTCLK_N => MGTCLK_N,
REFCLK => REFCLK,
DCLK => DCLK,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
Core_Clk => Core_Clk,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
LlinkTemac0_CLK => LlinkTemac0_CLK,
LlinkTemac0_RST => LlinkTemac0_RST,
LlinkTemac0_SOP_n => LlinkTemac0_SOP_n,
LlinkTemac0_EOP_n => LlinkTemac0_EOP_n,
LlinkTemac0_SOF_n => LlinkTemac0_SOF_n,
LlinkTemac0_EOF_n => LlinkTemac0_EOF_n,
LlinkTemac0_REM => LlinkTemac0_REM,
LlinkTemac0_Data => LlinkTemac0_Data,
LlinkTemac0_SRC_RDY_n => LlinkTemac0_SRC_RDY_n,
Temac0Llink_DST_RDY_n => Temac0Llink_DST_RDY_n,
Temac0Llink_SOP_n => Temac0Llink_SOP_n,
Temac0Llink_EOP_n => Temac0Llink_EOP_n,
Temac0Llink_SOF_n => Temac0Llink_SOF_n,
Temac0Llink_EOF_n => Temac0Llink_EOF_n,
Temac0Llink_REM => Temac0Llink_REM,
Temac0Llink_Data => Temac0Llink_Data,
Temac0Llink_SRC_RDY_n => Temac0Llink_SRC_RDY_n,
LlinkTemac0_DST_RDY_n => LlinkTemac0_DST_RDY_n,
LlinkTemac1_CLK => LlinkTemac1_CLK,
LlinkTemac1_RST => LlinkTemac1_RST,
LlinkTemac1_SOP_n => LlinkTemac1_SOP_n,
LlinkTemac1_EOP_n => LlinkTemac1_EOP_n,
LlinkTemac1_SOF_n => LlinkTemac1_SOF_n,
LlinkTemac1_EOF_n => LlinkTemac1_EOF_n,
LlinkTemac1_REM => LlinkTemac1_REM,
LlinkTemac1_Data => LlinkTemac1_Data,
LlinkTemac1_SRC_RDY_n => LlinkTemac1_SRC_RDY_n,
Temac1Llink_DST_RDY_n => Temac1Llink_DST_RDY_n,
Temac1Llink_SOP_n => Temac1Llink_SOP_n,
Temac1Llink_EOP_n => Temac1Llink_EOP_n,
Temac1Llink_SOF_n => Temac1Llink_SOF_n,
Temac1Llink_EOF_n => Temac1Llink_EOF_n,
Temac1Llink_REM => Temac1Llink_REM,
Temac1Llink_Data => Temac1Llink_Data,
Temac1Llink_SRC_RDY_n => Temac1Llink_SRC_RDY_n,
LlinkTemac1_DST_RDY_n => LlinkTemac1_DST_RDY_n,
MII_TXD_0 => MII_TXD_0,
MII_TX_EN_0 => MII_TX_EN_0,
MII_TX_ER_0 => MII_TX_ER_0,
MII_RXD_0 => MII_RXD_0,
MII_RX_DV_0 => MII_RX_DV_0,
MII_RX_ER_0 => MII_RX_ER_0,
MII_RX_CLK_0 => MII_RX_CLK_0,
MII_TX_CLK_0 => MII_TX_CLK_0,
MII_TXD_1 => MII_TXD_1,
MII_TX_EN_1 => MII_TX_EN_1,
MII_TX_ER_1 => MII_TX_ER_1,
MII_RXD_1 => MII_RXD_1,
MII_RX_DV_1 => MII_RX_DV_1,
MII_RX_ER_1 => MII_RX_ER_1,
MII_RX_CLK_1 => MII_RX_CLK_1,
MII_TX_CLK_1 => MII_TX_CLK_1,
GMII_TXD_0 => GMII_TXD_0,
GMII_TX_EN_0 => GMII_TX_EN_0,
GMII_TX_ER_0 => GMII_TX_ER_0,
GMII_TX_CLK_0 => GMII_TX_CLK_0,
GMII_RXD_0 => GMII_RXD_0,
GMII_RX_DV_0 => GMII_RX_DV_0,
GMII_RX_ER_0 => GMII_RX_ER_0,
GMII_RX_CLK_0 => GMII_RX_CLK_0,
GMII_TXD_1 => GMII_TXD_1,
GMII_TX_EN_1 => GMII_TX_EN_1,
GMII_TX_ER_1 => GMII_TX_ER_1,
GMII_TX_CLK_1 => GMII_TX_CLK_1,
GMII_RXD_1 => GMII_RXD_1,
GMII_RX_DV_1 => GMII_RX_DV_1,
GMII_RX_ER_1 => GMII_RX_ER_1,
GMII_RX_CLK_1 => GMII_RX_CLK_1,
TXP_0 => TXP_0,
TXN_0 => TXN_0,
RXP_0 => RXP_0,
RXN_0 => RXN_0,
TXP_1 => TXP_1,
TXN_1 => TXN_1,
RXP_1 => RXP_1,
RXN_1 => RXN_1,
RGMII_TXD_0 => RGMII_TXD_0,
RGMII_TX_CTL_0 => RGMII_TX_CTL_0,
RGMII_TXC_0 => RGMII_TXC_0,
RGMII_RXD_0 => RGMII_RXD_0,
RGMII_RX_CTL_0 => RGMII_RX_CTL_0,
RGMII_RXC_0 => RGMII_RXC_0,
RGMII_TXD_1 => RGMII_TXD_1,
RGMII_TX_CTL_1 => RGMII_TX_CTL_1,
RGMII_TXC_1 => RGMII_TXC_1,
RGMII_RXD_1 => RGMII_RXD_1,
RGMII_RX_CTL_1 => RGMII_RX_CTL_1,
RGMII_RXC_1 => RGMII_RXC_1,
MDC_0 => MDC_0,
MDC_1 => MDC_1,
HostMiimRdy => HostMiimRdy,
HostRdData => HostRdData,
HostMiimSel => HostMiimSel,
HostReq => HostReq,
HostAddr => HostAddr,
HostEmac1Sel => HostEmac1Sel,
Temac0AvbTxClk => Temac0AvbTxClk,
Temac0AvbTxClkEn => Temac0AvbTxClkEn,
Temac0AvbRxClk => Temac0AvbRxClk,
Temac0AvbRxClkEn => Temac0AvbRxClkEn,
Avb2Mac0TxData => Avb2Mac0TxData,
Avb2Mac0TxDataValid => Avb2Mac0TxDataValid,
Avb2Mac0TxUnderrun => Avb2Mac0TxUnderrun,
Mac02AvbTxAck => Mac02AvbTxAck,
Mac02AvbRxData => Mac02AvbRxData,
Mac02AvbRxDataValid => Mac02AvbRxDataValid,
Mac02AvbRxFrameGood => Mac02AvbRxFrameGood,
Mac02AvbRxFrameBad => Mac02AvbRxFrameBad,
Temac02AvbTxData => Temac02AvbTxData,
Temac02AvbTxDataValid => Temac02AvbTxDataValid,
Temac02AvbTxUnderrun => Temac02AvbTxUnderrun,
Avb2Temac0TxAck => Avb2Temac0TxAck,
Avb2Temac0RxData => Avb2Temac0RxData,
Avb2Temac0RxDataValid => Avb2Temac0RxDataValid,
Avb2Temac0RxFrameGood => Avb2Temac0RxFrameGood,
Avb2Temac0RxFrameBad => Avb2Temac0RxFrameBad,
Temac1AvbTxClk => Temac1AvbTxClk,
Temac1AvbTxClkEn => Temac1AvbTxClkEn,
Temac1AvbRxClk => Temac1AvbRxClk,
Temac1AvbRxClkEn => Temac1AvbRxClkEn,
Avb2Mac1TxData => Avb2Mac1TxData,
Avb2Mac1TxDataValid => Avb2Mac1TxDataValid,
Avb2Mac1TxUnderrun => Avb2Mac1TxUnderrun,
Mac12AvbTxAck => Mac12AvbTxAck,
Mac12AvbRxData => Mac12AvbRxData,
Mac12AvbRxDataValid => Mac12AvbRxDataValid,
Mac12AvbRxFrameGood => Mac12AvbRxFrameGood,
Mac12AvbRxFrameBad => Mac12AvbRxFrameBad,
Temac12AvbTxData => Temac12AvbTxData,
Temac12AvbTxDataValid => Temac12AvbTxDataValid,
Temac12AvbTxUnderrun => Temac12AvbTxUnderrun,
Avb2Temac1TxAck => Avb2Temac1TxAck,
Avb2Temac1RxData => Avb2Temac1RxData,
Avb2Temac1RxDataValid => Avb2Temac1RxDataValid,
Avb2Temac1RxFrameGood => Avb2Temac1RxFrameGood,
Avb2Temac1RxFrameBad => Avb2Temac1RxFrameBad,
TxClientClk_0 => TxClientClk_0,
ClientTxStat_0 => ClientTxStat_0,
ClientTxStatsVld_0 => ClientTxStatsVld_0,
ClientTxStatsByteVld_0 => ClientTxStatsByteVld_0,
RxClientClk_0 => RxClientClk_0,
ClientRxStats_0 => ClientRxStats_0,
ClientRxStatsVld_0 => ClientRxStatsVld_0,
ClientRxStatsByteVld_0 => ClientRxStatsByteVld_0,
TxClientClk_1 => TxClientClk_1,
ClientTxStat_1 => ClientTxStat_1,
ClientTxStatsVld_1 => ClientTxStatsVld_1,
ClientTxStatsByteVld_1 => ClientTxStatsByteVld_1,
RxClientClk_1 => RxClientClk_1,
ClientRxStats_1 => ClientRxStats_1,
ClientRxStatsVld_1 => ClientRxStatsVld_1,
ClientRxStatsByteVld_1 => ClientRxStatsByteVld_1,
MDIO_0_I => MDIO_0_I,
MDIO_0_O => MDIO_0_O,
MDIO_0_T => MDIO_0_T,
MDIO_1_I => MDIO_1_I,
MDIO_1_O => MDIO_1_O,
MDIO_1_T => MDIO_1_T
);
end architecture STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (3 downto 0):= "0100";
s: out std_logic_vector (6 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
-- Alteração feita para relatório.
s <= "1111110" when e = "0000" else
"0110000" when e = "0001" else
"1101101" when e = "0010" else
"1111001" when e = "0011" else
"0110010" when e = "0100" else
"1011010" when e = "0101" else
"1011111" when e = "0110" else
"1110000" when e = "0111" else
"1111111" when e = "1000" else
"1111011" when e = "1001";
end Behavioral;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
Subsets and Splits