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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Module Name: transceiver_clocking - Behavioral
--
-- Description: Input buffers for the GTX reference clock
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity transceiver_clocking is
Port ( refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtrefclk0 : out STD_LOGIC;
gtrefclk1 : out STD_LOGIC);
end transceiver_clocking;
architecture Behavioral of transceiver_clocking is
signal buffered_clk0 : std_logic;
signal buffered_clk1 : std_logic;
begin
i_buff0: IBUFDS_GTE2 port map (
I => refclk0_p,
IB => refclk0_n,
CEB => '0',
O => gtrefclk0
);
i_buff1: IBUFDS_GTE2 port map (
I => refclk1_p,
IB => refclk1_n,
CEB => '0',
O => gtrefclk1
);
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
--function log2(i : integer) return integer;
function Header_gen(network_size_x, source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
-- gen_bit_reversed_packet needs fixing !!!
--procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
-- finish_time: in time; signal clk: in std_logic;
-- signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
-- signal port_in: out std_logic_vector);
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(network_size_x, source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
variable source_x, source_y, destination_x, destination_y: integer;
begin
-- We only need network_size_x for calculation of X and Y coordinates of a node!
source_x := source mod network_size_x;
source_y := source / network_size_x;
destination_x := destination mod network_size_x;
destination_y := destination / network_size_x;
Header_flit := Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)) &
XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(network_size_x, source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node_x, source_node_y, destination_node_x, destination_node_y, source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
source_node_y := to_integer(unsigned(port_in(28 downto 22)));
source_node_x := to_integer(unsigned(port_in(21 downto 15)));
destination_node_y := to_integer(unsigned(port_in(14 downto 8)));
destination_node_x := to_integer(unsigned(port_in(7 downto 1)));
-- We only needs network_size_x for computing the node ID (convert from (X,Y) coordinate to Node ID)!
source_node := (source_node_y * network_size_x) + source_node_x;
destination_node := (destination_node_y * network_size_x) + destination_node_x;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hash_array_pkg.all;
entity brutus_top is
generic (
M : integer := 2
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component md5_demux
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component md5_mux
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(M-1 downto 0); --
o_mux_sel : out unsigned(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_demux, s_len_demux_md5_0, s_len_demux_md5_1 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_demux, s_string1_demux_md5_0, s_string1_demux_md5_1 : unsigned(31 downto 0);
signal s_string2_pp_demux, s_string2_demux_md5_0, s_string2_demux_md5_1 : unsigned(31 downto 0);
signal hm0_0, hm1_0, hm2_0, hm3_0 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hm0_1, hm1_1, hm2_1, hm3_1 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hc0_0, hc1_0, hc2_0, hc3_0 : unsigned(31 downto 0); -- hashes from mux to comp
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_demux_start, demux_md5_start_0, demux_md5_start_1 : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
--signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
signal s_ctrl_demux_sel, s_ctrl_mux_sel : unsigned(M-1 downto 0);
signal temp_hash_0, temp_hash_1 : unsigned(127 downto 0);
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_demux_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => s_ctrl_demux_sel,
o_mux_sel => s_ctrl_mux_sel
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => hc0_0,
i_hash_1 => hc1_0,
i_hash_2 => hc2_0,
i_hash_3 => hc3_0,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_demux,
o_data_1 => s_string2_pp_demux,
o_length => s_len_pp_demux
);
demux_inst: md5_demux
generic map (
N => M
)
port map (
i_md5_indata.start => ctrl_demux_start,
i_md5_indata.data_0 => s_string1_pp_demux,
i_md5_indata.data_1 => s_string2_pp_demux,
i_md5_indata.len => s_len_pp_demux,
i_select => s_ctrl_demux_sel,
o_md5_indata_0.start => demux_md5_start_0,
o_md5_indata_0.data_0 => s_string1_demux_md5_0,
o_md5_indata_0.data_1 => s_string2_demux_md5_0,
o_md5_indata_0.len => s_len_demux_md5_0,
o_md5_indata_1.start => demux_md5_start_1,
o_md5_indata_1.data_0 => s_string1_demux_md5_1,
o_md5_indata_1.data_1 => s_string2_demux_md5_1,
o_md5_indata_1.len => s_len_demux_md5_1
);
MD5_inst_0: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_0,
i_data_0 => s_string1_demux_md5_0,
i_data_1 => s_string2_demux_md5_0,
i_length => s_len_demux_md5_0,
o_done => md5_ctrl_done, -- only first md5 connected to controller
o_hash_0 => hm0_0, --o_hash(31 downto 0),
o_hash_1 => hm1_0, --o_hash(63 downto 32),
o_hash_2 => hm2_0, --o_hash(95 downto 64),
o_hash_3 => hm3_0 --o_hash(127 downto 96)
);
MD5_inst_1: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_1,
i_data_0 => s_string1_demux_md5_1,
i_data_1 => s_string2_demux_md5_1,
i_length => s_len_demux_md5_1,
o_done => open,
o_hash_0 => hm0_1, --o_hash(31 downto 0),
o_hash_1 => hm1_1, --o_hash(63 downto 32),
o_hash_2 => hm2_1, --o_hash(95 downto 64),
o_hash_3 => hm3_1 --o_hash(127 downto 96)
);
temp_hash_0 <= hm0_0 & hm1_0 & hm2_0 & hm3_0;
temp_hash_1 <= hm0_1 & hm1_1 & hm2_1 & hm3_1;
mux_inst: md5_mux
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_hash_0 => temp_hash_0,
i_hash_1 => temp_hash_1,
i_select => s_ctrl_mux_sel,
o_hash_0 => hc0_0,
o_hash_1 => hc1_0,
o_hash_2 => hc2_0,
o_hash_3 => hc3_0
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hash_array_pkg.all;
entity brutus_top is
generic (
M : integer := 2
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component md5_demux
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component md5_mux
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(M-1 downto 0); --
o_mux_sel : out unsigned(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_demux, s_len_demux_md5_0, s_len_demux_md5_1 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_demux, s_string1_demux_md5_0, s_string1_demux_md5_1 : unsigned(31 downto 0);
signal s_string2_pp_demux, s_string2_demux_md5_0, s_string2_demux_md5_1 : unsigned(31 downto 0);
signal hm0_0, hm1_0, hm2_0, hm3_0 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hm0_1, hm1_1, hm2_1, hm3_1 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hc0_0, hc1_0, hc2_0, hc3_0 : unsigned(31 downto 0); -- hashes from mux to comp
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_demux_start, demux_md5_start_0, demux_md5_start_1 : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
--signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
signal s_ctrl_demux_sel, s_ctrl_mux_sel : unsigned(M-1 downto 0);
signal temp_hash_0, temp_hash_1 : unsigned(127 downto 0);
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_demux_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => s_ctrl_demux_sel,
o_mux_sel => s_ctrl_mux_sel
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => hc0_0,
i_hash_1 => hc1_0,
i_hash_2 => hc2_0,
i_hash_3 => hc3_0,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_demux,
o_data_1 => s_string2_pp_demux,
o_length => s_len_pp_demux
);
demux_inst: md5_demux
generic map (
N => M
)
port map (
i_md5_indata.start => ctrl_demux_start,
i_md5_indata.data_0 => s_string1_pp_demux,
i_md5_indata.data_1 => s_string2_pp_demux,
i_md5_indata.len => s_len_pp_demux,
i_select => s_ctrl_demux_sel,
o_md5_indata_0.start => demux_md5_start_0,
o_md5_indata_0.data_0 => s_string1_demux_md5_0,
o_md5_indata_0.data_1 => s_string2_demux_md5_0,
o_md5_indata_0.len => s_len_demux_md5_0,
o_md5_indata_1.start => demux_md5_start_1,
o_md5_indata_1.data_0 => s_string1_demux_md5_1,
o_md5_indata_1.data_1 => s_string2_demux_md5_1,
o_md5_indata_1.len => s_len_demux_md5_1
);
MD5_inst_0: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_0,
i_data_0 => s_string1_demux_md5_0,
i_data_1 => s_string2_demux_md5_0,
i_length => s_len_demux_md5_0,
o_done => md5_ctrl_done, -- only first md5 connected to controller
o_hash_0 => hm0_0, --o_hash(31 downto 0),
o_hash_1 => hm1_0, --o_hash(63 downto 32),
o_hash_2 => hm2_0, --o_hash(95 downto 64),
o_hash_3 => hm3_0 --o_hash(127 downto 96)
);
MD5_inst_1: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_1,
i_data_0 => s_string1_demux_md5_1,
i_data_1 => s_string2_demux_md5_1,
i_length => s_len_demux_md5_1,
o_done => open,
o_hash_0 => hm0_1, --o_hash(31 downto 0),
o_hash_1 => hm1_1, --o_hash(63 downto 32),
o_hash_2 => hm2_1, --o_hash(95 downto 64),
o_hash_3 => hm3_1 --o_hash(127 downto 96)
);
temp_hash_0 <= hm0_0 & hm1_0 & hm2_0 & hm3_0;
temp_hash_1 <= hm0_1 & hm1_1 & hm2_1 & hm3_1;
mux_inst: md5_mux
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_hash_0 => temp_hash_0,
i_hash_1 => temp_hash_1,
i_select => s_ctrl_mux_sel,
o_hash_0 => hc0_0,
o_hash_1 => hc1_0,
o_hash_2 => hc2_0,
o_hash_3 => hc3_0
);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruction_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruction_Memory_tb_ARCH OF Instruction_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruction_Memory_synth_inst:ENTITY work.Instruction_Memory_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: axi2ahb
-- File: axi2ahb.vhd
-- Author: Martin George
--
-- AXI/AHB bridge allowing Altera HPS to access LEON3 bus.
-- AHB master interface currently only supports OKAY response from slave.
-- AXI slave only supports incrementing bursts of length 1-16 transfers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
Entity axi2ahb is
generic(
hindex : integer := 0;
idsize : integer := 6;
lensize : integer := 4;
fifo_depth : integer := 16
);
port(
ahb_clk : in std_logic;
axi_clk : in std_logic;
resetn : in std_logic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
s_axi_araddr : in std_logic_vector ( 31 downto 0 );
s_axi_arburst : in std_logic_vector ( 1 downto 0 );
s_axi_arcache : in std_logic_vector ( 3 downto 0 );
s_axi_arid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_arlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_arlock : in std_logic_vector (1 downto 0);
s_axi_arprot : in std_logic_vector ( 2 downto 0 );
s_axi_arqos : in std_logic_vector ( 3 downto 0 );
s_axi_arready : out std_logic;
s_axi_arsize : in std_logic_vector ( 2 downto 0 );
s_axi_arvalid : in std_logic;
s_axi_awaddr : in std_logic_vector ( 31 downto 0 );
s_axi_awburst : in std_logic_vector ( 1 downto 0 );
s_axi_awcache : in std_logic_vector ( 3 downto 0 );
s_axi_awid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_awlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_awlock : in std_logic_vector (1 downto 0);
s_axi_awprot : in std_logic_vector ( 2 downto 0 );
s_axi_awqos : in std_logic_vector ( 3 downto 0 );
s_axi_awready : out std_logic;
s_axi_awsize : in std_logic_vector ( 2 downto 0 );
s_axi_awvalid : in std_logic;
s_axi_bid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector ( 1 downto 0 );
s_axi_bvalid : out std_logic;
s_axi_rdata : out std_logic_vector ( 31 downto 0 );
s_axi_rid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_rlast : out std_logic;
s_axi_rready : in std_logic;
s_axi_rresp : out std_logic_vector ( 1 downto 0 );
s_axi_rvalid : out std_logic;
s_axi_wdata : in std_logic_vector ( 31 downto 0 );
s_axi_wid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_wlast : in std_logic;
s_axi_wready : out std_logic;
s_axi_wstrb : in std_logic_vector ( 3 downto 0 );
s_axi_wvalid : in std_logic
);
end;
architecture rtl of axi2ahb is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AXI2AHB, 0, 0, 0),
others => zero32);
type axi_w_state_type is (w_start, w_wait, w_data_fifo, w_ahb, w_done);
type axi_r_state_type is (r_start, r_wait, r_data_fifo, r_done);
type ahb_rw_state_type is (idle, w_req, w_first_addr, w_data_addr, w_done, r_req,
r_first_addr, r_data_addr, r_done);
type fifo is array (fifo_depth-1 downto 0) of std_logic_vector(31 downto 0);
type ahb_record is record
--States--
ahb_rw_state : ahb_rw_state_type;
--Outputs--
hwrite : std_logic;
hbusreq : std_logic;
hlock : std_logic;
hsize : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hwaddr : std_logic_vector(9 downto 0);
hraddr : std_logic_vector(9 downto 0);
hburst : std_logic_vector(2 downto 0);
inc_sel : std_logic_vector(2 downto 0);
--FIFO signals--
rfifo : fifo;
rfifo_w_ptr : integer range 0 to fifo_depth-1;
wfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
ahb_haddr_stop : std_logic;
ahb_w_en_ack : std_logic;
ahb_r_done : std_logic;
ahb_w_done : std_logic;
addr_incr : integer range 0 to 15;
end record;
type axi_record is record
--States--
axi_w_state : axi_w_state_type;
axi_r_state : axi_r_state_type;
--Outputs--
arready : std_logic;
awready : std_logic;
bvalid : std_logic;
rdata : std_logic_vector ( 31 downto 0 );
rlast : std_logic;
rvalid : std_logic;
wready : std_logic;
--FIFO signals--
wfifo : fifo;
wfifo_w_ptr : integer range 0 to fifo_depth-1;
rfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
--Write--
awaddr : std_logic_vector(31 downto 0);
awburst : std_logic_vector(1 downto 0);
awlen : std_logic_vector(lensize-1 downto 0);
awsize : std_logic_vector(2 downto 0);
awid : std_logic_vector(idsize-1 downto 0);
--Read--
arid : std_logic_vector(idsize-1 downto 0);
araddr : std_logic_vector(31 downto 0);
arburst : std_logic_vector(1 downto 0);
arlen : std_logic_vector(lensize-1 downto 0);
arsize : std_logic_vector(2 downto 0);
--AHB--
ahb_r_en : std_logic;
ahb_w_en : std_logic;
end record;
signal h, hin : ahb_record;
signal x, xin : axi_record;
begin
comb: process(resetn, ahbi, x, h, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arid, s_axi_arlen, s_axi_arlock,
s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid,
s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awid,
s_axi_awlen, s_axi_awlock, s_axi_awprot, s_axi_awqos,
s_axi_awsize, s_axi_awvalid, s_axi_bready, s_axi_rready,
s_axi_wdata, s_axi_wid, s_axi_wlast, s_axi_wstrb, s_axi_wvalid)
variable vx : axi_record;
variable vh : ahb_record;
begin
vx := x;
vh := h;
-- AXI WRITE STATES
case x.axi_w_state is
when w_start =>
vx.awready := '1';
vx.wready := '0';
vx.ahb_w_en := '0';
vx.bvalid := '0';
if s_axi_awvalid = '1' then
vx.axi_w_state := w_wait;
vx.awready := '0';
vx.awlen := s_axi_awlen;
vx.awburst := s_axi_awburst;
vx.awsize := s_axi_awsize;
vx.awaddr := s_axi_awaddr;
vx.awid := s_axi_awid;
end if;
when w_wait =>
vx.awready := '0';
if h.ahb_w_done = '1' then
vx.wfifo_w_ptr := 0;
vx.axi_w_state := w_data_fifo;
end if;
when w_data_fifo =>
vx.awready := '0';
vx.wfifo_w_ptr := x.wfifo_w_ptr;
vx.wready := '0';
if s_axi_wvalid = '1' then
vx.wready := '1';
if s_axi_wlast = '1' then
vx.axi_w_state := w_ahb;
else
vx.wfifo_w_ptr := x.wfifo_w_ptr + 1;
end if;
end if;
when w_ahb =>
vx.wready := '0';
vx.ahb_w_en := '1';
if h.ahb_w_en_ack = '1' then
vx.ahb_w_en := '0';
vx.bvalid := '1';
vx.axi_w_state := w_done;
end if;
when w_done =>
if s_axi_bready = '1' then
vx.bvalid := '0';
vx.axi_w_state := w_start;
else
end if;
end case;
-- AXI READ STATES
case x.axi_r_state is
when r_start =>
vx.arready := '1';
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
if s_axi_arvalid = '1' then
vx.arready := '0';
vx.ahb_r_en := '1';
vx.arlen := s_axi_arlen;
vx.arburst := s_axi_arburst;
vx.arsize := s_axi_arsize;
vx.araddr := s_axi_araddr;
vx.arid := s_axi_arid;
vx.axi_r_state := r_wait;
end if;
when r_wait =>
vx.arready := '0';
if h.ahb_r_done = '1' then
vx.ahb_r_en := '0';
vx.axi_r_state := r_data_fifo;
end if;
when r_data_fifo =>
vx.rdata := h.rfifo(x.rfifo_r_ptr);
vx.rvalid := '1';
vx.rfifo_r_ptr := x.rfifo_r_ptr;
-- if x.rfifo_r_ptr = conv_integer(x.arlen) then
if x.rfifo_r_ptr = h.rfifo_w_ptr then
vx.rlast := '1';
vx.axi_r_state := r_done;
elsif s_axi_rready = '1' then
vx.rfifo_r_ptr := x.rfifo_r_ptr + 1;
end if;
when r_done =>
vx.rvalid := '1';
if s_axi_rready = '1' then
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
vx.axi_r_state := r_start;
else
end if;
end case;
-- AHB READ/WRITE STATES
case h.ahb_rw_state is
when idle =>
vh.ahb_w_en_ack := '0';
vh.ahb_r_done := '0';
vh.htrans := "00";
if x.ahb_w_en = '1' then
vh.ahb_w_done := '0';
vh.ahb_rw_state := w_req;
vh.hsize := x.awsize;
vh.inc_sel := x.awsize;
elsif x.ahb_r_en = '1' then
vh.ahb_r_done := '0';
vh.ahb_rw_state := r_req;
vh.hsize := "010";
vh.inc_sel := x.arsize;
else
end if;
-- WRITE STATES
when w_req =>
vh.ahb_w_en_ack := '1';
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '1';
if conv_integer(x.awlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := w_first_addr;
else
end if;
when w_first_addr =>
vh.htrans := "10";
vh.hwaddr := x.awaddr(9 downto 0);
vh.haddr := x.awaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not x.awaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not x.awaddr(1);
when others =>
end case;
vh.ahb_rw_state := w_data_addr;
when w_data_addr =>
vh.htrans := "11";
vh.hwdata := x.wfifo(h.wfifo_r_ptr);
if h.wfifo_r_ptr = x.wfifo_w_ptr then
vh.htrans := "00";
vh.ahb_rw_state := w_done;
elsif ahbi.hready = '1' then
vh.hwaddr := h.hwaddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hwaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not vh.hwaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not vh.hwaddr(1);
when others =>
end case;
vh.wfifo_r_ptr := h.wfifo_r_ptr + 1;
end if;
when w_done =>
if ahbi.hready = '1' then
vh.ahb_haddr_stop := '0';
vh.htrans := "00";
vh.wfifo_r_ptr := 0;
vh.ahb_w_en_ack := '0';
vh.ahb_w_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vh.ahb_rw_state := idle;
else
end if;
-- READ STATES
when r_req =>
vh.rfifo_w_ptr := 0;
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '0';
if conv_integer(x.arlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := r_first_addr;
vh.htrans := "10";
vh.haddr := x.araddr;
vh.hraddr := x.araddr(9 downto 0);
else
end if;
when r_first_addr =>
if ahbi.hready = '1' then
if h.rfifo_w_ptr /= conv_integer(x.arlen) then
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
vh.ahb_rw_state := r_data_addr;
end if;
when r_data_addr =>
if ahbi.hready = '1' then
vh.rfifo(h.rfifo_w_ptr) := ahbi.hrdata;
if h.rfifo_w_ptr = conv_integer(x.arlen) then
vh.htrans := "00";
vh.ahb_rw_state := r_done;
else
vh.htrans := "11";
vh.rfifo_w_ptr := h.rfifo_w_ptr + 1;
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
else
end if;
when r_done =>
vh.htrans := "00";
vh.ahb_r_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vx.ahb_r_en := '0';
vh.ahb_rw_state := idle;
end case;
-- WDATA muxing
if (s_axi_wvalid and h.ahb_w_done) = '1' then
case s_axi_wstrb is
when "0001" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0);
when "0010" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8);
when "0100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16);
when "1000" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24);
when "0011" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 0)
& s_axi_wdata(15 downto 0);
when "1100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 16)
& s_axi_wdata(31 downto 16);
when "1111" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata;
when others =>
end case;
end if;
-- HADDR increment
case h.inc_sel is
when "000" =>
vh.addr_incr := 1;
when "001" =>
vh.addr_incr := 2;
when others =>
vh.addr_incr := 4;
end case;
if resetn = '0' then
vx.axi_w_state := w_start;
vx.axi_r_state := r_start;
vh.ahb_rw_state := idle;
vh.rfifo := (others => (others => '0'));
vx.wfifo := (others => (others => '0'));
vh.hbusreq := '0';
vh.hlock := '0';
vh.hwdata := (others => '0');
vh.haddr := (others => '0');
vx.awlen := (others => '0');
vx.awburst := (others => '0');
vx.awsize := (others => '0');
vx.awaddr := (others => '0');
vx.awid := (others => '0');
vx.wready := '0';
vx.arready := '0';
vx.awready := '0';
vx.rdata := (others => '0');
vx.araddr := (others => '0');
vx.arburst := (others => '0');
vx.arlen := (others => '0');
vx.arid := (others => '0');
vx.bvalid := '0';
vx.rlast := '0';
vx.rvalid := '0';
vx.wready := '0';
vh.ahb_r_done := '0';
vx.ahb_r_en := '0';
vx.ahb_w_en := '0';
vh.hwrite := '0';
vh.hsize := (others => '0');
vh.ahb_w_done := '1';
vx.arsize := (others => '0');
vh.hburst := (others => '0');
end if;
xin <= vx;
hin <= vh;
end process;
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ahbo.hirq <= (others => '0');
ahbo.haddr <= h.haddr;
ahbo.htrans <= h.htrans;
ahbo.hprot <= "0011";
ahbo.hburst <= h.hburst;
ahbo.hbusreq <= h.hbusreq;
ahbo.hwrite <= h.hwrite;
ahbo.hwdata <= h.hwdata;
ahbo.hlock <= h.hlock;
ahbo.hsize <= h.hsize;
s_axi_bid <= x.awid;
s_axi_rid <= x.arid;
s_axi_arready <= x.arready;
s_axi_awready <= x.awready;
s_axi_bresp <= "00";
s_axi_bvalid <= x.bvalid;
s_axi_rdata <= x.rdata;
s_axi_rlast <= x.rlast;
s_axi_rresp <= "00";
s_axi_rvalid <= x.rvalid;
s_axi_wready <= x.wready;
--AXI synchronous--
axi_sync: process(axi_clk)
begin
if rising_edge(axi_clk) then
x <= xin;
end if;
end process;
--AHB synchronous--
ahb_sync: process(ahb_clk)
begin
if rising_edge(ahb_clk) then
h <= hin;
end if;
end process;
end;
|
-- #############################################################################
-- DE0_Nano_SoC_LT24_top_level.vhd
-- ===============================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_LT24_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_LT24_ADC_BUSY : in std_logic;
GPIO_0_LT24_ADC_CS_N : out std_logic;
GPIO_0_LT24_ADC_DCLK : out std_logic;
GPIO_0_LT24_ADC_DIN : out std_logic;
GPIO_0_LT24_ADC_DOUT : in std_logic;
GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_LT24_top_level;
architecture rtl of DE0_Nano_SoC_LT24_top_level is
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover always (s_write -> not(s_read));
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.graphics_types_pkg.all;
use work.colors_pkg.all;
use work.sprites_pkg.all;
use std.textio.all;
use std.env.all;
entity sprites_engine_tb is
end;
architecture testbench of sprites_engine_tb is
signal clock, reset: std_logic := '0';
signal raster_position: point_type;
signal sprite_pixel: palette_color_type;
signal sprite_pixel_is_valid: boolean;
procedure wait_clock_cycles(cycles_count: integer) is
begin
for i in 1 to cycles_count loop
wait until clock'event and clock = '1';
end loop;
end;
constant TOP_LEFT_SQUARE_BITMAP: paletted_bitmap_type := (
(1, 1, 1, 1, 1, 1, 1, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 1, 1, 1, 1, 1, 1, 1)
);
constant BOTTOM_RIGHT_TRIANGLE_BITMAP: paletted_bitmap_type := (
(1, 1, 1, 1, 1, 1, 1, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 2, 1),
(1, 0, 0, 0, 0, 2, 2, 1),
(1, 0, 0, 2, 2, 2, 2, 1),
(1, 0, 2, 2, 2, 2, 2, 1),
(1, 2, 2, 2, 2, 2, 2, 1),
(1, 1, 1, 1, 1, 1, 1, 1)
);
constant SPRITES: sprites_array_type := (
(x => 1, y => 1, bitmap => TOP_LEFT_SQUARE_BITMAP, enabled => true),
(x => 1, y => 1, bitmap => BOTTOM_RIGHT_TRIANGLE_BITMAP, enabled => true)
);
constant SPRITES_COORDINATES: point_array_type(SPRITES'range) := (
(0, 0),
(16, 0)
);
constant SPRITES_COLLISION_QUERY: sprite_collision_query_type := ( (0,1), (0,1) );
signal sprite_collisions_results: bool_vector(SPRITES_COLLISION_QUERY'range);
begin
uut: entity work.sprites_engine
generic map (
SPRITES_INITIAL_VALUES => (
(x => 1, y => 1, bitmap => TOP_LEFT_SQUARE_BITMAP, enabled => true),
(x => 5, y => 5, bitmap => BOTTOM_RIGHT_TRIANGLE_BITMAP, enabled => true)
),
SPRITES_COLLISION_QUERY => ( (0,1), (0,1) )
)
port map(
clock => clock,
reset => reset,
raster_position => raster_position,
sprites_coordinates => SPRITES_COORDINATES,
sprite_pixel => sprite_pixel,
sprite_pixel_is_valid => sprite_pixel_is_valid,
sprite_collisions_results => sprite_collisions_results,
sprites_enabled => (others => true)
);
clock <= not clock after 10 ns;
process
variable row: line;
begin
report "starting...";
reset <= '1';
wait_clock_cycles(2);
reset <= '0';
for y in 0 to 15 loop
for x in 0 to 15 loop
raster_position <= (x, y);
wait_clock_cycles(1);
write(row, sprite_pixel, field => 2);
end loop;
writeline(output, row);
end loop;
finish;
end process;
end; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
entity foo is end;
architecture bar of foo is
shared variable INDEX: INTEGER range 0 to 99 := 0;
shared variable COUNT: POSITIVE;
shared variable MEMORY: BIT_MATRIX (0 to 7, 0 to 1023);
begin end;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-- file : BIST_addsub.vhdl
-- version : jeu. nov. 4 00:49:28 CET 2010
-- this file implements a combinatorial unit, injects a fault and compares
-- the result with a reference unit.
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BIST_addsub is
end BIST_addsub;
architecture BIST of BIST_addsub is
signal result, clk, reset : std_ulogic;
signal operandes : std_ulogic_vector(66 downto 1);
signal result_dut, result_ref : std_ulogic_vector(33 downto 1);
begin
-- the test vector generator
lfsr : entity work.lfsr4
generic map(size => 66)
port map (
clk => clk,
reset => reset,
lfsr => operandes);
-- operandes(1) : add/substract
-- operandes(2) : carry in
-- operandes(34 downto 3) : substractend
-- operandes(66 downto 35) : addend
-- reference add/sub unit
reference: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
-- A-B = A+(-B) = A+(not B + 1) :
if (operandes(1) = '1') then
substractend := not substractend;
end if;
-- calcule l'addition avec les retenues
res := unsigned(addend) + unsigned(substractend);
-- écrit la retenue sortante mais pas entrante
result_ref <= std_ulogic_vector(res(34 downto 2));
end process;
-- add/sub with a fault
faulty: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
if (operandes(1) = '1') then
substractend := not substractend;
end if;
res := unsigned(addend) + unsigned(substractend);
-- fault injection :
if (operandes(34 downto 28) = "0110110") then
res(33) := '1';
end if;
result_dut <= std_ulogic_vector(res(34 downto 2));
end process;
process
function sulv2txt(s : std_ulogic_vector) return string is
variable t : string(s'range);
variable u : string(3 downto 1);
begin
for i in s'range loop
u := std_ulogic'image(s(i));
t(i) := u(2);
end loop;
return t;
end sulv2txt;
variable r : std_ulogic_vector(33 downto 1);
begin
clk <= '0';
reset <= '1';
wait for 1 ns;
reset <= '0';
for i in 1 to 100000 loop
clk <= '1'; wait for 1 ns;
clk <= '0'; wait for 1 ns;
r := result_ref xor result_dut;
if (r /= (33 downto 1=>'0')) then
report integer'image(i) & " : " & sulv2txt(operandes) & " - " & sulv2txt(r);
end if;
end loop;
wait;
end process;
end BIST;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:13 10/09/2015
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
-- Definicion del multiplexor
with Sel select
Tiempo <= DecHor when "00",
UniHor when "01",
DecMin when "10",
UniMin when others;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Testbench for the T410 system toplevel.
--
-- $Id: tb_t410-c.vhd,v 1.1 2006-06-11 22:19:32 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_t410_behav_c0 of tb_t410 is
for behav
for t410_b: t410
use configuration work.t410_struct_c0;
end for;
for tb_elems_b: tb_elems
use configuration work.tb_elems_behav_c0;
end for;
end for;
end tb_t410_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY ZynqDesign_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END ZynqDesign_rst_processing_system7_0_100M_0;
ARCHITECTURE ZynqDesign_rst_processing_system7_0_100M_0_arch OF ZynqDesign_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END ZynqDesign_rst_processing_system7_0_100M_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2004/04/06 11:19:53 wig Exp $
-- $Date: 2004/04/06 11:19:53 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 11:19:53 wig
-- Adding result/autoopen
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ab : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb2.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb2 is
end entity Task4_ent_tb2;
architecture Task4_arch_tb2 of Task4_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 14
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb2;
configuration Task4_cfg_tb2 of Task4_ent_tb2 is
for Task4_arch_tb2
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb2;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb2.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb2 is
end entity Task4_ent_tb2;
architecture Task4_arch_tb2 of Task4_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 14
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb2;
configuration Task4_cfg_tb2 of Task4_ent_tb2 is
for Task4_arch_tb2
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb2;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
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