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library verilog;
use verilog.vl_types.all;
entity Transmit is
port(
Transmit_CLK : in vl_logic;
Line_Num : in vl_logic_vector(7 downto 0);
Focus_Num : in vl_logic_vector(1 downto 0);
Pr_Gate : in vl_logic;
RX_Gate : in vl_logic;
Sample_Gate : out vl_logic;
P : out vl_logic_vector(15 downto 0);
N : out vl_logic_vector(15 downto 0);
HV_SW_CLR : out vl_logic;
HV_SW_LE : out vl_logic;
HV_SW_CLK : out vl_logic;
HV_SW_DOUT : out vl_logic;
AX : out vl_logic_vector(3 downto 0);
AY : out vl_logic_vector(2 downto 0);
MT_CS : out vl_logic;
MT_Strobe : out vl_logic;
MT_Data : out vl_logic
);
end Transmit;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00434
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (1)
-- 7.2.4 (4)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00434(ARCH00434)
-- ENT00434_Test_Bench(ARCH00434_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.ARITHMETIC.ALL ;
entity ENT00434 is
generic (
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00434 ;
architecture ARCH00434 of ENT00434 is
constant c2_int_1 : integer :=
10 * i_int_1 + i_int_1 * i_int_2 + i_int_1 * i_int_1 -
i_int_2 * c_int_2 ;
constant c2_t_int_1 : t_int :=
(1) * 500 + (i_t_int_1 / 2) * i_t_int_2 + i_t_int_1 * 2 -
i_t_int_2 * i_t_int_2 ;
constant c2_st_int_1 : st_int :=
(-0) * i_st_int_2 + i_st_int_1 * (i_t_int_1 / 10) +
(i_st_int_1 * i_t_int_2) - (i_st_int_2 / 10) * i_t_int_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
--
begin
-- static expression
case bool is
when (
10 * c_int_1 + c_int_1 * c_int_2 + c_int_1 * c_int_1 -
c_int_2 * c_int_2 = 81 and
(1) * 500 + (c_t_int_1 / 2) * c_t_int_2 + c_t_int_1 * 2 -
c_t_int_2 * c_t_int_2 = 741 and
(-0) * c_st_int_2 + c_st_int_1 * (c_t_int_1 / 10) +
(c_st_int_1 * c_t_int_2) - (c_st_int_2 / 10) * c_t_int_2 = 115
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_int_1 = 81 and
c2_t_int_1 = 741 and
c2_st_int_1 = 115 ;
-- dynamic expression
v2_int_1 :=
10 * v_int_1 + v_int_1 * v_int_2 + v_int_1 * v_int_1 -
v_int_2 * c_int_2 ;
v2_t_int_1 :=
(1) * 500 + (v_t_int_1 / 2) * v_t_int_2 + v_t_int_1 * 2 -
v_t_int_2 * v_t_int_2 ;
v2_st_int_1 :=
(-0) * v_st_int_2 + v_st_int_1 * (v_t_int_1 / 10) +
(v_st_int_1 * v_t_int_2) - (v_st_int_2 / 10) * v_t_int_2 ;
dyn_correct := v2_int_1 = 81 and
v2_t_int_1 = 741 and
v2_st_int_1 = 115 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00434 ;
use WORK.STANDARD_TYPES.test_report, WORK.STANDARD_TYPES.print ;
use WORK.ARITHMETIC.ALL ;
entity ENT00434_Test_Bench is
end ENT00434_Test_Bench ;
architecture ARCH00434_Test_Bench of ENT00434_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct, globally_static_correct,
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00434 ( ARCH00434 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00434" ,
"* predefined for integer types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00434_Test_Bench ;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_Bit_Counter.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo che conta i bit per il trasferimento seriale
-- del segnale audio.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Audio_Bit_Counter is
generic(
BIT_COUNTER_INIT: std_logic_vector(4 downto 0) := "11111"
);
port(
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
counting: out std_logic
);
end Audio_Bit_Counter;
architecture behaviour of Audio_Bit_Counter is
signal reset_bit_counter: std_logic;
signal bit_counter: std_logic_vector(4 downto 0);
begin
reset_bit_counter <= left_right_clk_rising_edge or left_right_clk_falling_edge;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
bit_counter <= "00000";
elsif (reset_bit_counter = '1') then
bit_counter <= BIT_COUNTER_INIT;
elsif ((bit_clk_falling_edge = '1') and (bit_counter > "00000")) then
bit_counter <= bit_counter - "00001";
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
counting <= '0';
elsif (reset_bit_counter = '1') then
counting <= '1';
elsif ((bit_clk_falling_edge = '1') and (bit_counter = "00000")) then
counting <= '0';
end if;
end if;
end process;
end behaviour; |
library ieee;
use ieee.std_logic_1164.all;
entity testcase is
port(
data_in : in std_ulogic;
data_out : out std_ulogic
);
end entity testcase;
architecture behaviour of testcase is
begin
comb : process(all)
begin
data_out <= '1' when data_in = '0' else '0';
end process;
end architecture behaviour;
|
architecture RTL of FIFO is
begin
process
begin
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
-- Violations below
FOR_LABEL : for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
end loop;
for index in 4 to 23 loop
for j in 0 to 127 loop
end loop;
end loop;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:04:07 12/09/2018
-- Design Name:
-- Module Name: top - structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
use work.ssg_display_shared_package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ssg_display_top is
port (clk : in std_logic;
rst : in std_logic;
in_switches_p : in std_logic_vector(7 downto 0);
in_buttons_p : in std_logic_vector(3 downto 0);
out_seg_p : out SEG_T;
out_dp_p : out std_logic;
out_digits_en_p : out DIGITS_EN_T;
out_leds_p : out std_logic_vector(7 downto 0)
);
end ssg_display_top;
architecture structural of ssg_display_top is
--
-------------------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------------------
--
--
-- Seven Segment Display Component
--
component ssg_display is
port (clk : in std_logic;
rst : in std_logic;
in_bcds_p : in std_logic_vector(15 downto 0);-- Four BCD numbers that can be displayed by the four 7-segment digits
in_dps_p : in DP_T; -- enable/disable input signals for the decimal point of a digit
out_seg_p : out SEG_T; -- enable output signals for seven led segments(cathode) of currently refreshed digit
out_dp_p : out std_logic; -- enable ouput signal for the decimal point of currently refreshed digit
out_digits_en_p : out DIGITS_EN_T -- enable signals for K=4 digits. only one digit out of K=4 digits is enabled for refresh duration
);
end component ssg_display;
--
-- Declaration of the KCPSM6 component including default values for generics.
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component kcpsm6;
--
-- Program ROM
--
component ssg_program is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component ssg_program;
--
-- Signals for connection of ssg_display and KCPSM6.
--
signal bcds_reg : std_logic_vector(15 downto 0);-- Four BCD numbers that can be displayed by the four 7-segment digits
signal dps_reg : DP_T; -- enable/disable input signals for the decimal point of a digit
signal segs_sig : SEG_T; -- enable output signals for seven led segments(cathode) of currently refreshed digit
signal dp_sig : std_logic; -- enable ouput signal for the decimal point of currently refreshed digit
signal digits_en_sig : DIGITS_EN_T; -- enable signals for K=4 digits. only one digit out of K=4 digits is enabled for refresh duration
--
-- Signals for connection of KCPSM6 and Program Memory.
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
--
-- Some additional signals are required if your system also needs to reset KCPSM6.
--
signal rdl : std_logic;
--
-- When interrupt is to be used then the recommended circuit included below requires
-- the following signal to represent the request made from your system.
--
signal int_request : std_logic;
begin
--
-- Components Instances
--
processor: kcpsm6
generic map ( hwbuild => X"00",
interrupt_vector => X"3FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
program_rom: ssg_program --Name to match your PSM file
generic map( C_FAMILY => "S6", --Family 'S6', 'V6' or '7S'
C_RAM_SIZE_KWORDS => 1, --Program size '1', '2' or '4'
C_JTAG_LOADER_ENABLE => 1) --Include JTAG Loader when set to '1'
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
ssd: ssg_display
port map ( clk => clk,
rst => rst,
in_bcds_p => bcds_reg,
in_dps_p => dps_reg,
out_seg_p => segs_sig,
out_dp_p => dp_sig,
out_digits_en_p => digits_en_sig
);
--
-- In many designs (especially your first) interrupt and sleep are not used.
-- Tie these inputs Low until you need them. Tying 'interrupt' to 'interrupt_ack'
-- preserves both signals for future use and avoids a warning message.
--
kcpsm6_sleep <= '0';
interrupt <= interrupt_ack;
kcpsm6_reset <= rst or rdl;
in_port(7 downto 4) <= (others => '0');
mux_in_ports: process( clk )
begin
if( clk'event and clk='1') then
if( rst = '1' ) then
in_port(3 downto 0) <= (others => '0');
else
case port_id(1 downto 0) is
-- IN_SWITCH_HLFWRD_X_PORT
when "00" => in_port(3 downto 0) <= in_switches_p(3 downto 0);
-- IN_SWITCH_HLFWRD_Y_PORT
when "01" => in_port(3 downto 0) <= in_switches_p(7 downto 4);
-- IN_BUTTON_PORT
when "10" => in_port(3 downto 0) <= in_buttons_p;
-- Others
when others => in_port(3 downto 0) <= (others => '0');
end case;
end if;
end if;
end process mux_in_ports;
decode_out_ports: process(clk)
begin
if( clk'event and clk='1') then
if( rst = '1') then
bcds_reg <= (others => '0');
dps_reg <= (others => DISABLE_DP);
else
if( write_strobe = '1') then
case port_id(1 downto 0) is
-- OUT_NUM_X_PORT
when "00" => bcds_reg(3 downto 0) <= out_port(3 downto 0);
-- OUT_NUM_Y_PORT
when "01" => bcds_reg(7 downto 4) <= out_port(3 downto 0);
-- OUT_SUM_PORT
when "10" => bcds_reg(15 downto 8) <= out_port;
-- OUT_DP_PORT
when "11" => dps_reg <= out_port(3 downto 0);
when others => bcds_reg <= bcds_reg;
dps_reg <= dps_reg;
end case;
end if;
end if;
end if;
end process decode_out_ports;
out_seg_p <= segs_sig;
out_dp_p <= dp_sig;
out_digits_en_p <= digits_en_sig;
out_leds_p <= in_switches_p;
end structural; |
-- $Id: nexys3lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: nexys3lib
-- Description: Nexys 3 components
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
-- 2011-11-25 432 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys3lib is
component nexys3_aif is -- NEXYS 3, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit -- ppcm: ...
);
end component;
component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys3lib;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Problem - UART on the DE1 does not have all pins connected. Need to use...
ENTITY pokey IS
PORT
(
CLK : IN STD_LOGIC;
ENABLE_179 :in std_logic;
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
-- keyboard interface
-- KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
-- KEY_HELD : IN STD_LOGIC;
-- SHIFT_PRESSED : IN STD_LOGIC;
-- BREAK_PRESSED : IN STD_LOGIC;
-- KEY_INTERRUPT : IN STD_LOGIC;
keyboard_scan : out std_logic_vector(5 downto 0);
keyboard_response : in std_logic_vector(1 downto 0);
-- pots - go high as capacitor charges
POT_IN : in std_logic_vector(7 downto 0);
-- sio interface
SIO_IN1 : IN std_logic;
SIO_IN2 : IN std_logic;
SIO_IN3 : IN std_logic;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
IRQ_N_OUT : OUT std_logic;
SIO_OUT1 : OUT std_logic;
SIO_OUT2 : OUT std_logic;
SIO_OUT3 : OUT std_logic;
SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
POT_RESET : out std_logic
);
END pokey;
ARCHITECTURE vhdl OF pokey IS
component synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END component;
component syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
syncreset : in std_logic;
reset_n : in std_logic;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END component;
component pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_noise_filter IS
PORT
(
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END component;
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
shift_pressed : out std_logic;
control_pressed : out std_logic;
break_pressed : out std_logic;
key_held : out std_logic;
keycode : out std_logic_vector(5 downto 0);
other_key_irq : out std_logic
);
end component;
--signal enable_179 : std_logic;
signal enable_64 : std_logic;
signal enable_15 : std_logic;
signal audf0_reg : std_logic_vector(7 downto 0);
signal audc0_reg : std_logic_vector(7 downto 0);
signal audf1_reg : std_logic_vector(7 downto 0);
signal audc1_reg : std_logic_vector(7 downto 0);
signal audf2_reg : std_logic_vector(7 downto 0);
signal audc2_reg : std_logic_vector(7 downto 0);
signal audf3_reg : std_logic_vector(7 downto 0);
signal audc3_reg : std_logic_vector(7 downto 0);
signal audctl_reg : std_logic_vector(7 downto 0);
signal audf0_next : std_logic_vector(7 downto 0);
signal audc0_next : std_logic_vector(7 downto 0);
signal audf1_next : std_logic_vector(7 downto 0);
signal audc1_next : std_logic_vector(7 downto 0);
signal audf2_next : std_logic_vector(7 downto 0);
signal audc2_next : std_logic_vector(7 downto 0);
signal audf3_next : std_logic_vector(7 downto 0);
signal audc3_next : std_logic_vector(7 downto 0);
signal audctl_next : std_logic_vector(7 downto 0);
signal audf0_pulse : std_logic;
signal audf1_pulse : std_logic;
signal audf2_pulse : std_logic;
signal audf3_pulse : std_logic;
signal audf0_reload : std_logic;
signal audf1_reload : std_logic;
signal audf2_reload : std_logic;
signal audf3_reload : std_logic;
signal stimer_write : std_logic;
signal stimer_write_delayed : std_logic;
signal audf0_pulse_noise : std_logic;
signal audf1_pulse_noise : std_logic;
signal audf2_pulse_noise : std_logic;
signal audf3_pulse_noise : std_logic;
signal audf0_enable : std_logic;
signal audf1_enable : std_logic;
signal audf2_enable : std_logic;
signal audf3_enable : std_logic;
signal chan0_output_next : std_logic;
signal chan1_output_next : std_logic;
signal chan2_output_next : std_logic;
signal chan3_output_next : std_logic;
signal chan0_output_reg : std_logic;
signal chan1_output_reg : std_logic;
signal chan2_output_reg : std_logic;
signal chan3_output_reg : std_logic;
signal highpass0_next : std_logic;
signal highpass1_next : std_logic;
signal highpass0_reg : std_logic;
signal highpass1_reg : std_logic;
signal volume_channel_0_next : std_logic_vector(3 downto 0);
signal volume_channel_1_next : std_logic_vector(3 downto 0);
signal volume_channel_2_next : std_logic_vector(3 downto 0);
signal volume_channel_3_next : std_logic_vector(3 downto 0);
signal volume_channel_0_reg : std_logic_vector(3 downto 0);
signal volume_channel_1_reg : std_logic_vector(3 downto 0);
signal volume_channel_2_reg : std_logic_vector(3 downto 0);
signal volume_channel_3_reg : std_logic_vector(3 downto 0);
signal addr_decoded : std_logic_vector(15 downto 0);
signal noise_4 : std_logic;
signal noise_5 : std_logic;
signal noise_large : std_logic;
signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
signal initmode : std_logic;
signal irqen_next : std_logic_vector(7 downto 0);
signal irqen_reg : std_logic_vector(7 downto 0);
signal irqst_next : std_logic_vector(7 downto 0);
signal irqst_reg : std_logic_vector(7 downto 0);
signal irq_n_next : std_logic;
signal irq_n_reg : std_logic; -- for output
-- serial ports!
signal serial_ip_ready_interrupt : std_logic;
signal serial_ip_framing_next : std_logic;
signal serial_ip_framing_reg : std_logic;
signal serial_ip_overrun_next : std_logic;
signal serial_ip_overrun_reg : std_logic;
signal serial_op_needed_interrupt : std_logic;
signal skctl_next : std_logic_vector(7 downto 0);
signal skctl_reg : std_logic_vector(7 downto 0);
signal serin_shift_next : std_logic_vector(9 downto 0);
signal serin_shift_reg : std_logic_vector(9 downto 0);
signal serin_next : std_logic_vector(7 downto 0);
signal serin_reg : std_logic_vector(7 downto 0);
signal serin_bitcount_next : std_logic_vector(3 downto 0);
signal serin_bitcount_reg : std_logic_vector(3 downto 0);
signal sio_in1_reg : std_logic;
signal sio_in2_reg : std_logic;
signal sio_in3_reg : std_logic;
signal sio_in_next : std_logic;
signal sio_in_reg : std_logic;
signal sio_out_next : std_logic;
signal sio_out_reg : std_logic;
signal serial_out_next : std_logic;
signal serial_out_reg : std_logic;
signal serout_shift_next : std_logic_vector(9 downto 0);
signal serout_shift_reg : std_logic_vector(9 downto 0);
signal serout_holding_full_next : std_logic;
signal serout_holding_full_reg : std_logic;
signal serout_holding_next : std_logic_vector(7 downto 0);
signal serout_holding_reg : std_logic_vector(7 downto 0);
signal serout_holding_load : std_logic;
signal serout_bitcount_next : std_logic_vector(3 downto 0);
signal serout_bitcount_reg : std_logic_vector(3 downto 0);
signal serout_active_next : std_logic;
signal serout_active_reg : std_logic;
signal serial_reset : std_logic;
signal serout_sync_reset : std_logic;
signal skrest_write : std_logic;
signal serout_enable : std_logic;
signal serout_enable_delayed : std_logic;
signal serin_enable : std_logic;
signal async_serial_reset : std_logic;
signal waiting_for_start_bit : std_logic;
signal serin_clock_next : std_logic;
signal serin_clock_reg : std_logic;
signal serin_clock_last_next : std_logic;
signal serin_clock_last_reg : std_logic;
signal serout_clock_next : std_logic;
signal serout_clock_reg : std_logic;
signal serout_clock_last_next : std_logic;
signal serout_clock_last_reg : std_logic;
signal twotone_reset : std_logic;
signal twotone_next : std_logic;
signal twotone_reg : std_logic;
signal clock_next : std_logic;
signal clock_reg : std_logic;
signal clock_sync_next : std_logic;
signal clock_sync_reg : std_logic;
signal clock_input : std_logic;
-- keyboard
signal keyboard_overrun_next : std_logic;
signal keyboard_overrun_reg : std_logic;
signal shift_pressed : std_logic;
signal control_pressed : std_logic;
signal break_pressed : std_logic;
signal key_held : std_logic;
signal other_key_irq : std_logic;
signal kbcode : std_logic_vector(5 downto 0);
-- pots
signal pot0_next : std_logic_vector(7 downto 0);
signal pot0_reg : std_logic_vector(7 downto 0);
signal pot1_next : std_logic_vector(7 downto 0);
signal pot1_reg : std_logic_vector(7 downto 0);
signal pot2_next : std_logic_vector(7 downto 0);
signal pot2_reg : std_logic_vector(7 downto 0);
signal pot3_next : std_logic_vector(7 downto 0);
signal pot3_reg : std_logic_vector(7 downto 0);
signal pot4_next : std_logic_vector(7 downto 0);
signal pot4_reg : std_logic_vector(7 downto 0);
signal pot5_next : std_logic_vector(7 downto 0);
signal pot5_reg : std_logic_vector(7 downto 0);
signal pot6_next : std_logic_vector(7 downto 0);
signal pot6_reg : std_logic_vector(7 downto 0);
signal pot7_next : std_logic_vector(7 downto 0);
signal pot7_reg : std_logic_vector(7 downto 0);
signal pot_counter_next : std_logic_vector(7 downto 0);
signal pot_counter_reg : std_logic_vector(7 downto 0);
signal potgo_write : std_logic;
signal pot_reset_next : std_logic;
signal pot_reset_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
audf0_reg <= X"00";
audc0_reg <= X"00";
audf1_reg <= X"00";
audc1_reg <= X"00";
audf2_reg <= X"00";
audc2_reg <= X"00";
audf3_reg <= X"00";
audc3_reg <= X"00";
audctl_reg <= X"00";
irqen_reg <= X"00";
irqst_reg <= X"FF";
irq_n_reg <= '1';
skctl_reg <= X"00";
highpass0_reg <= '0';
highpass1_reg <= '0';
chan0_output_reg <= '0';
chan1_output_reg <= '0';
chan2_output_reg <= '0';
chan3_output_reg <= '0';
volume_channel_0_reg <= (others=>'0');
volume_channel_1_reg <= (others=>'0');
volume_channel_2_reg <= (others=>'0');
volume_channel_3_reg <= (others=>'0');
serin_reg <= (others=>'0');
serin_shift_reg <= (others=>'0');
serin_bitcount_reg <= (others=>'0');
serout_shift_reg <= (others=>'0');
serout_holding_reg <= (others=>'0');
serout_holding_full_reg <= '0';
serout_active_reg <= '0';
sio_out_reg <= '1';
serial_out_reg <= '1';
serial_ip_framing_reg <= '0';
serial_ip_overrun_reg <= '0';
clock_reg <= '0';
clock_sync_reg <= '0';
keyboard_overrun_reg <= '0';
serin_clock_reg <= '0';
serin_clock_last_reg <= '0';
serout_clock_reg <= '0';
serout_clock_last_reg <= '0';
twotone_reg <= '0';
sio_in_reg <= '0';
pot0_reg <= (others=>'0');
pot1_reg <= (others=>'0');
pot2_reg <= (others=>'0');
pot3_reg <= (others=>'0');
pot4_reg <= (others=>'0');
pot5_reg <= (others=>'0');
pot6_reg <= (others=>'0');
pot7_reg <= (others=>'0');
pot_counter_reg <= (others=>'0');
pot_reset_reg <= '1';
elsif (clk'event and clk='1') then
audf0_reg <= audf0_next;
audc0_reg <= audc0_next;
audf1_reg <= audf1_next;
audc1_reg <= audc1_next;
audf2_reg <= audf2_next;
audc2_reg <= audc2_next;
audf3_reg <= audf3_next;
audc3_reg <= audc3_next;
audctl_reg <= audctl_next;
irqen_reg <= irqen_next;
irqst_reg <= irqst_next;
irq_n_reg <= irq_n_next;
skctl_reg <= skctl_next;
highpass0_reg <= highpass0_next;
highpass1_reg <= highpass1_next;
chan0_output_reg <= chan0_output_next;
chan1_output_reg <= chan1_output_next;
chan2_output_reg <= chan2_output_next;
chan3_output_reg <= chan3_output_next;
volume_channel_0_reg<= volume_channel_0_next;
volume_channel_1_reg<= volume_channel_1_next;
volume_channel_2_reg<= volume_channel_2_next;
volume_channel_3_reg<= volume_channel_3_next;
serin_reg <= serin_next;
serin_shift_reg <= serin_shift_next;
serin_bitcount_reg <= serin_bitcount_next;
serout_shift_reg <= serout_shift_next;
serout_bitcount_reg <= serout_bitcount_next;
serout_holding_reg<=serout_holding_next;
serout_holding_full_reg<=serout_holding_full_next;
serout_active_reg <= serout_active_next;
sio_out_reg <= sio_out_next;
serial_out_reg <= serial_out_next;
serial_ip_framing_reg <= serial_ip_framing_next;
serial_ip_overrun_reg <= serial_ip_overrun_next;
clock_reg <= clock_next;
clock_sync_reg <= clock_sync_next;
keyboard_overrun_reg <= keyboard_overrun_next;
serin_clock_reg <= serin_clock_next;
serin_clock_last_reg <= serin_clock_last_next;
serout_clock_reg <= serout_clock_next;
serout_clock_last_reg <= serout_clock_last_next;
twotone_reg <= twotone_next;
sio_in_reg <= sio_in_next;
pot0_reg <= pot0_next;
pot1_reg <= pot1_next;
pot2_reg <= pot2_next;
pot3_reg <= pot3_next;
pot4_reg <= pot4_next;
pot5_reg <= pot5_next;
pot6_reg <= pot6_next;
pot7_reg <= pot7_next;
pot_counter_reg <= pot_counter_next;
pot_reset_reg <= pot_reset_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- clock selection
process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
begin
audf0_enable <= enable_64;
audf1_enable <= enable_64;
audf2_enable <= enable_64;
audf3_enable <= enable_64;
if (audctl_reg(0) = '1') then
audf0_enable <= enable_15;
audf1_enable <= enable_15;
audf2_enable <= enable_15;
audf3_enable <= enable_15;
end if;
if (audctl_reg(6) = '1') then
audf0_enable <= enable_179;
end if;
if (audctl_reg(5) = '1') then
audf2_enable <= enable_179;
end if;
if(audctl_reg(4) = '1') then
audf1_enable <= audf0_pulse;
end if;
if(audctl_reg(3) = '1') then
audf3_enable <= audf2_pulse;
end if;
end process;
-- Instantiate timers
timer0 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
timer1 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
timer2 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
timer3 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);
-- Timer reloading
process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
begin
audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
end process;
-- Writes to registers
process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
begin
audf0_next <= audf0_reg;
audc0_next <= audc0_reg;
audf1_next <= audf1_reg;
audc1_next <= audc1_reg;
audf2_next <= audf2_reg;
audc2_next <= audc2_reg;
audf3_next <= audf3_reg;
audc3_next <= audc3_reg;
audctl_next <= audctl_reg;
irqen_next <= irqen_reg;
skctl_next <= skctl_reg;
stimer_write <= '0';
serout_holding_load <= '0';
serout_holding_next <= serout_holding_reg;
serial_reset <= '0';
skrest_write <= '0';
potgo_write <= '0';
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
audf0_next <= data_in;
end if;
if(addr_decoded(1) = '1') then
audc0_next <= data_in;
end if;
if(addr_decoded(2) = '1') then
audf1_next <= data_in;
end if;
if(addr_decoded(3) = '1') then
audc1_next <= data_in;
end if;
if(addr_decoded(4) = '1') then
audf2_next <= data_in;
end if;
if(addr_decoded(5) = '1') then
audc2_next <= data_in;
end if;
if(addr_decoded(6) = '1') then
audf3_next <= data_in;
end if;
if(addr_decoded(7) = '1') then
audc3_next <= data_in;
end if;
if(addr_decoded(8) = '1') then
audctl_next <= data_in;
end if;
if (addr_decoded(9) = '1') then --STIMER
stimer_write <= '1';
end if;
if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
skrest_write <= '1';
end if;
if (addr_decoded(11) = '1') then -- POTGO - start POT scan
potgo_write <= '1';
end if;
if (addr_decoded(13) = '1') then --SEROUT
serout_holding_next <= data_in;
serout_holding_load <= '1';
end if;
if (addr_decoded(14) = '1') then --IRQEN
irqen_next <= data_in;
end if;
if (addr_decoded(15) = '1') then --SKCTL
skctl_next <= data_in;
if (data_in(6 downto 4)="000") then
serial_reset <= '1';
end if;
end if;
end if;
end process;
-- Read from registers
process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
data_out <= X"FF";
if(addr_decoded(0) = '1') then --POT0
data_out <= pot0_reg;
end if;
if(addr_decoded(1) = '1') then --POT1
data_out <= pot1_reg;
end if;
if(addr_decoded(2) = '1') then --POT2
data_out <= pot2_reg;
end if;
if(addr_decoded(3) = '1') then --POT3
data_out <= pot3_reg;
end if;
if(addr_decoded(4) = '1') then --POT4
data_out <= pot4_reg;
end if;
if(addr_decoded(5) = '1') then --POT5
data_out <= pot5_reg;
end if;
if(addr_decoded(6) = '1') then --POT6
data_out <= pot6_reg;
end if;
if(addr_decoded(7) = '1') then --POT7
data_out <= pot7_reg;
end if;
if(addr_decoded(8) = '1') then --ALLPOT
data_out <= not(pot_in);
end if;
if(addr_decoded(9) = '1') then --KBCODE
data_out <= control_pressed&shift_pressed&kbcode;
end if;
if(addr_decoded(10) = '1') then -- RANDOM
data_out <= RAND_OUT;
end if;
if (addr_decoded(13) = '1') then --SERIN
data_out <= serin_reg;
end if;
if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
data_out <= IRQST_REG;
--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
end if;
if (addr_decoded(15) = '1') then --SKSTAT
data_out <= not(serial_ip_framing_reg)¬(keyboard_overrun_reg)¬(serial_ip_overrun_reg)&sio_in_reg¬(SHIFT_PRESSED)¬(KEY_HELD)&waiting_for_start_bit&"1";
end if;
end process;
-- Fire interrupts
process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
begin
-- clear interrupts
irqst_next <= irqst_reg or not(irqen_reg);
irq_n_next <= '0';
if ((irqst_reg or "0000"¬(irqen_reg(3))&"000") = X"FF") then
irq_n_next <= '1';
end if;
-- set interrupts
if (audf0_pulse = '1') then
irqst_next(0) <= not(irqen_reg(0));
end if;
if (audf1_pulse = '1') then
irqst_next(1) <= not(irqen_reg(1));
end if;
if (audf3_pulse = '1') then
irqst_next(2) <= not(irqen_reg(2));
end if;
if (other_key_irq = '1') then
irqst_next(6) <= not(irqen_reg(6));
end if;
if (break_pressed = '1') then
irqst_next(7) <= not(irqen_reg(7));
end if;
if (serial_ip_ready_interrupt = '1') then
irqst_next(5) <= not(irqen_reg(5));
end if;
irqst_next(3) <= serout_active_reg;
if (serial_op_needed_interrupt = '1') then
irqst_next(4) <= not(irqen_reg(4));
end if;
end process;
-- Instantiate delay for stimer reload_request
stimer_delay : delay_line
generic map (count=>3)
port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
--stimer_write_delayed <= stimer_write;
-- Instantiate audio noise filters
pokey_noise_filter0 : pokey_noise_filter
port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter1 : pokey_noise_filter
port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter2 : pokey_noise_filter
port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter3 : pokey_noise_filter
port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
-- Audio output stage
process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
begin
chan0_output_next <= chan0_output_reg;
chan1_output_next <= chan1_output_reg;
chan2_output_next <= chan2_output_reg;
chan3_output_next <= chan3_output_reg;
if (audf0_pulse_noise = '1') then
chan0_output_next <= not(chan0_output_reg);
end if;
if (audf1_pulse_noise = '1') then
chan1_output_next <= not(chan1_output_reg);
end if;
if (audf2_pulse_noise = '1') then
chan2_output_next <= not(chan2_output_reg);
end if;
if (audf3_pulse_noise = '1') then
chan3_output_next <= not(chan3_output_reg);
end if;
end process;
-- High pass filters
process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
begin
highpass0_next <= highpass0_reg;
highpass1_next <= highpass1_reg;
if (audctl_reg(2) = '1') then
if (audf2_pulse = '1') then
highpass0_next <= chan0_output_reg;
end if;
else
highpass0_next <= '1';
end if;
if (audctl_reg(1) = '1') then
if (audf3_pulse = '1') then
highpass1_next <= chan1_output_reg;
end if;
else
highpass1_next <= '1';
end if;
end process;
-- Instantiate key pokey clocks
-- ~1.79MHz - from 25MHz/14
-- ~64KHz - from 1.79MHz/28
-- ~15KHz - from 1.79MHz/114
--enable_179_div : enable_divider
-- generic map (COUNT=>14)
-- port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
-- resetcount 6/33
enable_64_div : syncreset_enable_divider
generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
enable_15_div : syncreset_enable_divider
generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
-- Instantiate pokey noise circuits (lfsr)
initmode <= skctl_next(1) nor skctl_next(0);
poly_17_19_lfsr : pokey_poly_17_9
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
poly_5_lfsr : pokey_poly_5
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
poly_4_lfsr : pokey_poly_4
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
begin
volume_channel_0_next <= "0000";
volume_channel_1_next <= "0000";
volume_channel_2_next <= "0000";
volume_channel_3_next <= "0000";
if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
volume_channel_0_next <= audc0_reg(3 downto 0);
end if;
if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
volume_channel_1_next <= audc1_reg(3 downto 0);
end if;
if ((chan2_output_reg or audc2_reg(4)) = '1') then
volume_channel_2_next <= audc2_reg(3 downto 0);
end if;
if ((chan3_output_reg or audc3_reg(4)) = '1') then
volume_channel_3_next <= audc3_reg(3 downto 0);
end if;
end process;
-- serial port output
-- urghhh
serout_sync_reset <= serial_reset or stimer_write_delayed;
serout_clock_delay : delay_line
generic map (count=>2)
port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
begin
serout_clock_next <= serout_clock_reg;
serout_clock_last_next <= serout_clock_reg;
serout_shift_next <= serout_shift_reg;
serout_bitcount_next <= serout_bitcount_reg;
serout_holding_full_next <= serout_holding_full_reg;
serout_active_next <= serout_active_reg;
serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
sio_out_next <= serial_out_reg;
-- two tone output
twotone_next <= twotone_reg;
twotone_reset <= '0';
if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
twotone_next <= not(twotone_reg);
twotone_reset <= skctl_reg(3);
end if;
if (skctl_reg(3) = '1') then
sio_out_next <= twotone_reg;
end if;
-- force break
if (skctl_reg(7) = '1') then
sio_out_next <= '0';
end if;
serial_op_needed_interrupt <= '0';
-- generate clock from enable signals
if (serout_enable_delayed = '1') then
serout_clock_next <= not(serout_clock_reg);
end if;
-- output bits over sio
if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then
serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
-- reload
if (serout_bitcount_reg = X"0") then
if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
serout_shift_next <= '1'&serout_holding_reg&'0';
serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
serout_holding_full_next <= '0';
serial_op_needed_interrupt <= '1'; -- more data please!
serout_active_next <= '1';
else
serout_active_next <= '0';
serial_out_next <= '1'; -- remove blip!
end if;
else
serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
end if;
end if;
-- register to load has been written too, update our state to reflect that it is full
if (serout_holding_load = '1') then
serout_holding_full_next <= '1';
end if;
if (serial_reset = '1') then
twotone_next <= '0';
serout_bitcount_next <= (others=>'0');
serout_shift_next <= (others=>'0');
serout_holding_full_next <= '0';
serout_clock_next <= '0';
serout_clock_last_next <= '0';
serout_active_next <= '0';
end if;
end process;
-- serial port input
sio_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);
sio_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);
sio_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);
sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
begin
serin_clock_next <= serin_clock_reg;
serin_clock_last_next <= serin_clock_reg;
serin_shift_next <= serin_shift_reg;
serin_bitcount_next <= serin_bitcount_reg;
serin_next <= serin_reg;
serial_ip_overrun_next <= serial_ip_overrun_reg;
serial_ip_framing_next <= serial_ip_framing_reg;
serial_ip_ready_interrupt <= '0';
async_serial_reset <= '0';
-- generate clock from enable signals
if (serin_enable = '1') then
serin_clock_next <= not(serin_clock_reg);
end if;
-- resync clock on receipt of start bit
if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
async_serial_reset <= '1';
serin_clock_next <= '1';
end if;
-- receive bits into shift reg
if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge
if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then
serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
if (serin_bitcount_reg = X"0") then -- full byte
serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
-- irq to alert new data avilable
serial_ip_ready_interrupt <= '1';
-- flag up overrun
if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
serial_ip_overrun_next <= '1';
end if;
-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
if (sio_in_reg='0') then
serial_ip_framing_next <= '1';
end if;
else
serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
end if;
end if;
end if;
if (skrest_write = '1') then
serial_ip_overrun_next <= '0';
serial_ip_framing_next <= '0';
end if;
if (serial_reset = '1') then
serin_clock_next <= '0';
serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
serin_shift_next <= (others=>'0');
end if;
end process;
-- serial clocks
process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
begin
clock_next <= sio_clock;
clock_sync_next <= clock_reg;
serout_enable <= '0';
serin_enable <= '0';
clock_input <= '1'; -- when output, outputs channel 4
case skctl_reg(6 downto 4) is
when "000" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "001" =>
serin_enable <= audf3_pulse;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "010" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
clock_input <= '0';
when "011" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "100" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= audf3_pulse;
when "101" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "110" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
clock_input <= '0';
when "111" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
when others =>
-- nop
end case;
end process;
-- keyboard overrun (i.e. second key pressed before interrupt cleared)
process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
begin
keyboard_overrun_next <= keyboard_overrun_reg;
if (other_key_irq='1' and irqst_reg(6)='0') then
keyboard_overrun_next <= '1';
end if;
if (skrest_write = '1') then
keyboard_overrun_next <= '0';
end if;
end process;
-- keyboard scan
pokey_keyboard_scanner1 : pokey_keyboard_scanner
port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);
-- POT scan
process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
pot0_next <= pot0_reg;
pot1_next <= pot1_reg;
pot2_next <= pot2_reg;
pot3_next <= pot3_reg;
pot4_next <= pot4_reg;
pot5_next <= pot5_reg;
pot6_next <= pot6_reg;
pot7_next <= pot7_reg;
pot_reset_next <= pot_reset_reg;
pot_counter_next <= pot_counter_reg;
if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
if (pot_counter_reg = X"E4") then
pot_reset_next <= '1'; -- turn on pot dump transistors
end if;
if (pot_reset_reg = '0') then
if (pot_in(0) = '0') then -- pot now high, latch
pot0_next <= pot_counter_reg;
end if;
if (pot_in(1) = '0') then -- pot now high, latch
pot1_next <= pot_counter_reg;
end if;
if (pot_in(2) = '0') then -- pot now high, latch
pot2_next <= pot_counter_reg;
end if;
if (pot_in(3) = '0') then -- pot now high, latch
pot3_next <= pot_counter_reg;
end if;
if (pot_in(4) = '0') then -- pot now high, latch
pot4_next <= pot_counter_reg;
end if;
if (pot_in(5) = '0') then -- pot now high, latch
pot5_next <= pot_counter_reg;
end if;
if (pot_in(6) = '0') then -- pot now high, latch
pot6_next <= pot_counter_reg;
end if;
if (pot_in(7) = '0') then -- pot now high, latch
pot7_next <= pot_counter_reg;
end if;
end if;
end if;
if (potgo_write = '1') then
pot_counter_next <= (others=>'0');
pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
end if;
end process;
-- Outputs
irq_n_out <= irq_n_reg;
CHANNEL_0_OUT <= volume_channel_0_reg;
CHANNEL_1_OUT <= volume_channel_1_reg;
CHANNEL_2_OUT <= volume_channel_2_reg;
CHANNEL_3_OUT <= volume_channel_3_reg;
sio_out1 <= sio_out_reg;
sio_out2 <= sio_out_reg;
sio_out3 <= sio_out_reg;
sio_clock <= audf3_pulse when clock_input='0' else 'Z';
pot_reset <= pot_reset_reg;
END vhdl;
|
entity reg4 is
port ( d0, d1, d2, d3, enable, clock : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_131 is
generic(
NUM_BITS : positive := 131
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_131 is
----------------------------------------------------------------------------------------------------
-- m = 131, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, enA, enB, a_greater_b,a_eq_b: std_logic;
signal A, B, U, V, X2, Y2, toB, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "00" when A(0) = '0' and currentState = CYCLE else
"01" when B(0) = '0' and currentState = CYCLE else
"10" when a_greater_b = '1' and currentState = CYCLE else
"11";
c0 <= '0' when caso = "01" else
'1';
c1 <= '0' when caso = "00" else
'1';
c2 <= '0' when caso = "01" else
'1';
c3 <= '0' when caso = "00" else
'1';
c4 <= '0' when CurrentState = Load1 else
'1';
c5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c6 <= '0' when rst = '1' else
'1';
enA <= '1' when currentState = LOAD1 or caso = "00" or caso = "10" else
'0';
enB <= '1' when caso = "01" or caso = "11" or rst = '1' or currentstate = LOAD1 else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
celda_reg_A: entity celda_a(behave)
generic map(NUM_BITS)
port map( A, B, c0, c1, enA, rst, clk, toB, A);
celda_reg_U: entity celda_U(behave)
generic map(NUM_BITS)
port map(U, V, P, c2, c3, c4, enA, rst, clk, toV, U);
celda_reg_B: entity celda_B(behave)
generic map(NUM_BITS)
port map(toB, P , Y2, c5, c6, enB, clk, B);
celda_reg_V: entity celda_v(behave)
generic map(NUM_BITS)
port map(toV, X2, c5, c6, enB, clk, V);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if rst = '1' then
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
--done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2905.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02905ent IS
END c02s01b01x02p03n01i02905ent;
ARCHITECTURE c02s01b01x02p03n01i02905arch OF c02s01b01x02p03n01i02905ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V2 := S1'quiet;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02905 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02905arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2905.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02905ent IS
END c02s01b01x02p03n01i02905ent;
ARCHITECTURE c02s01b01x02p03n01i02905arch OF c02s01b01x02p03n01i02905ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V2 := S1'quiet;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02905 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02905arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2905.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02905ent IS
END c02s01b01x02p03n01i02905ent;
ARCHITECTURE c02s01b01x02p03n01i02905arch OF c02s01b01x02p03n01i02905ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute QUIET may not be read within a procedure
V2 := S1'quiet;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02905 - The attribute QUIET of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02905arch;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
a <= b;
BLOCK_LABEL : block is
begin
end block;
a <= b;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Filename: ac97_if_pkg.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package ac97_if_pkg is
constant AC97_CMD_LENGTH : integer := 25;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- Write 0x0 to 0x0 (reset registers)
constant RESET_REGISTERS_CMD :
std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"000000";
-- Write 0x808 to 0x2 (master volume 0db gain)
constant MASTER_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"020808";
-- Write 0x808 to 0x4 (headphone vol)
constant HEADPHONE_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"040808";
-- Write 0x8000 to 0xa (mute PC beep)
constant MUTE_PC_BEEP_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"0a8000";
-- Write 0x808 to 0x18 pcmoutvol (amp out line)
constant PCMOUT_VOLUME_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"180808";
-- Write 0x404 to 0x1a record source (line in for left and right)
constant RECORD_SOURCE_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1a0404";
-- Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
constant RECORD_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1c0008";
constant EMPTY_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"000000";
end ac97_if_pkg;
package body ac97_if_pkg is
end ac97_if_pkg;
|
-------------------------------------------------------------------------------
-- Filename: ac97_if_pkg.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package ac97_if_pkg is
constant AC97_CMD_LENGTH : integer := 25;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- Write 0x0 to 0x0 (reset registers)
constant RESET_REGISTERS_CMD :
std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"000000";
-- Write 0x808 to 0x2 (master volume 0db gain)
constant MASTER_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"020808";
-- Write 0x808 to 0x4 (headphone vol)
constant HEADPHONE_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"040808";
-- Write 0x8000 to 0xa (mute PC beep)
constant MUTE_PC_BEEP_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"0a8000";
-- Write 0x808 to 0x18 pcmoutvol (amp out line)
constant PCMOUT_VOLUME_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"180808";
-- Write 0x404 to 0x1a record source (line in for left and right)
constant RECORD_SOURCE_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1a0404";
-- Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
constant RECORD_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1c0008";
constant EMPTY_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"000000";
end ac97_if_pkg;
package body ac97_if_pkg is
end ac97_if_pkg;
|
-------------------------------------------------------------------------------
-- Filename: ac97_if_pkg.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package ac97_if_pkg is
constant AC97_CMD_LENGTH : integer := 25;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- Write 0x0 to 0x0 (reset registers)
constant RESET_REGISTERS_CMD :
std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"000000";
-- Write 0x808 to 0x2 (master volume 0db gain)
constant MASTER_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"020808";
-- Write 0x808 to 0x4 (headphone vol)
constant HEADPHONE_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"040808";
-- Write 0x8000 to 0xa (mute PC beep)
constant MUTE_PC_BEEP_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"0a8000";
-- Write 0x808 to 0x18 pcmoutvol (amp out line)
constant PCMOUT_VOLUME_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"180808";
-- Write 0x404 to 0x1a record source (line in for left and right)
constant RECORD_SOURCE_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1a0404";
-- Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
constant RECORD_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1c0008";
constant EMPTY_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"000000";
end ac97_if_pkg;
package body ac97_if_pkg is
end ac97_if_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ForLoop is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ForLoop;
architecture behaviour of ForLoop is
signal result : std_logic_vector(n downto 0);
begin
gen : for i in 1 to 2 generate
nested : for j in 1 to 2 generate
moreNested : for k in 1 to 2 generate
sum <= i + j + k;
end generate moreNested;
end generate nested;
end generate gen;
end behaviour;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:49 06/12/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/Output_Extender_TB.vhd
-- Project Name: OZ-3_System
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Output_Port_MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Output_Extender_TB IS
END Output_Extender_TB;
ARCHITECTURE behavior OF Output_Extender_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Output_Port_MUX
PORT(
data : IN std_logic_vector(31 downto 0);
sel : IN std_logic_vector(1 downto 0);
output0 : OUT std_logic_vector(31 downto 0);
output1 : OUT std_logic_vector(31 downto 0);
output2 : OUT std_logic_vector(31 downto 0);
output3 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal data : std_logic_vector(31 downto 0) := (others => '0');
signal sel : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal output0 : std_logic_vector(31 downto 0);
signal output1 : std_logic_vector(31 downto 0);
signal output2 : std_logic_vector(31 downto 0);
signal output3 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Output_Port_MUX PORT MAP (
data => data,
sel => sel,
output0 => output0,
output1 => output1,
output2 => output2,
output3 => output3
);
-- Stimulus process
stim_proc: process
begin
sel(0) <= '1';
wait for 640 ns;
sel(1) <= '0';
wait for 1280 ns;
data <= x"00000006";
wait for 640 ns;
sel(0) <= '0';
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:49 06/12/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/Output_Extender_TB.vhd
-- Project Name: OZ-3_System
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Output_Port_MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Output_Extender_TB IS
END Output_Extender_TB;
ARCHITECTURE behavior OF Output_Extender_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Output_Port_MUX
PORT(
data : IN std_logic_vector(31 downto 0);
sel : IN std_logic_vector(1 downto 0);
output0 : OUT std_logic_vector(31 downto 0);
output1 : OUT std_logic_vector(31 downto 0);
output2 : OUT std_logic_vector(31 downto 0);
output3 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal data : std_logic_vector(31 downto 0) := (others => '0');
signal sel : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal output0 : std_logic_vector(31 downto 0);
signal output1 : std_logic_vector(31 downto 0);
signal output2 : std_logic_vector(31 downto 0);
signal output3 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Output_Port_MUX PORT MAP (
data => data,
sel => sel,
output0 => output0,
output1 => output1,
output2 => output2,
output3 => output3
);
-- Stimulus process
stim_proc: process
begin
sel(0) <= '1';
wait for 640 ns;
sel(1) <= '0';
wait for 1280 ns;
data <= x"00000006";
wait for 640 ns;
sel(0) <= '0';
wait;
end process;
END;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNQPHUITBS is
generic ( decode : string := "001";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNQPHUITBS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "001",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNQPHUITBS is
generic ( decode : string := "001";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNQPHUITBS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "001",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNQPHUITBS is
generic ( decode : string := "001";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNQPHUITBS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "001",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNQPHUITBS is
generic ( decode : string := "001";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNQPHUITBS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "001",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
--
-- GPIOs on Zybo (only PL)
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
pbs_i : in std_logic_vector(3 downto 0);
dips_i : in std_logic_vector(3 downto 0);
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o <= pbs_i or dips_i;
end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 4
-- C_READ_WIDTH_A : 4
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 2048
-- C_READ_DEPTH_B : 2048
-- C_ADDRB_WIDTH : 11
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 1
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ENB => ENB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'high downto din'low);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'high downto din'low);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
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Subsets and Splits