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architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode timing statemachine ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 7th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_tctrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_tctrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
---------------------------
-- DMA Timing Controller --
---------------------------
--
--
-- Timing DMA mode transfers
----------------------------------------------
-- T0: cycle time
-- Td: DIOR-/DIOW- asserted pulse width
-- Te: DIOR- data access
-- Tf: DIOR- data hold
-- Tg: DIOR-/DIOW- data setup
-- Th: DIOW- data hold
-- Ti: DMACK to DIOR-/DIOW- setup
-- Tj: DIOR-/DIOW- to DMACK hold
-- Tkr: DIOR- negated pulse width
-- Tkw: DIOW- negated pulse width
-- Tm: CS(1:0) valid to DIOR-/DIOW-
-- Tn: CS(1:0) hold
--
--
-- Transfer sequence
----------------------------------
-- 1) wait for Tm
-- 2) assert DIOR-/DIOW-
-- when write action present data (Timing spec. Tg always honored)
-- output enable is controlled by DMA-direction and DMACK-
-- 3) wait for Td
-- 4) negate DIOR-/DIOW-
-- when read action, latch data
-- 5) wait for Teoc (T0 - Td - Tm) or Tkw, whichever is greater
-- Th, Tj, Tk, Tn always honored
-- 6) start new cycle
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end entity atahost_dma_tctrl;
architecture structural of atahost_dma_tctrl is
component ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end component ro_cnt;
signal Tmdone, Tddone : std_logic;
signal iDIOR, iDIOW : std_logic;
begin
DIOR <= iDIOR; DIOW <= iDIOW;
-- 1) hookup Tm counter
tm_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Tm
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => go,
D => Tm,
done => Tmdone
);
-- 2) set (and reset) DIOR-/DIOW-
T2proc: process(clk, nReset)
begin
if (nReset = '0') then
iDIOR <= '0';
iDIOW <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDIOR <= '0';
iDIOW <= '0';
else
iDIOR <= (not we and Tmdone) or (iDIOR and not Tddone);
iDIOW <= ( we and Tmdone) or (iDIOW and not Tddone);
end if;
end if;
end process T2proc;
-- 3) hookup Td counter
td_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Td
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tmdone,
D => Td,
done => Tddone
);
-- generate data_strobe
gen_dstrb: process(clk)
begin
if (clk'event and clk = '1') then
dstrb <= Tddone; -- capture data at rising edge of DIOR-
end if;
end process gen_dstrb;
-- 4) negate DIOR-/DIOW- when Tddone
-- 5) hookup end_of_cycle counter
eoc_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tddone,
D => Teoc,
done => done
);
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode timing statemachine ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 7th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_tctrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_tctrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
---------------------------
-- DMA Timing Controller --
---------------------------
--
--
-- Timing DMA mode transfers
----------------------------------------------
-- T0: cycle time
-- Td: DIOR-/DIOW- asserted pulse width
-- Te: DIOR- data access
-- Tf: DIOR- data hold
-- Tg: DIOR-/DIOW- data setup
-- Th: DIOW- data hold
-- Ti: DMACK to DIOR-/DIOW- setup
-- Tj: DIOR-/DIOW- to DMACK hold
-- Tkr: DIOR- negated pulse width
-- Tkw: DIOW- negated pulse width
-- Tm: CS(1:0) valid to DIOR-/DIOW-
-- Tn: CS(1:0) hold
--
--
-- Transfer sequence
----------------------------------
-- 1) wait for Tm
-- 2) assert DIOR-/DIOW-
-- when write action present data (Timing spec. Tg always honored)
-- output enable is controlled by DMA-direction and DMACK-
-- 3) wait for Td
-- 4) negate DIOR-/DIOW-
-- when read action, latch data
-- 5) wait for Teoc (T0 - Td - Tm) or Tkw, whichever is greater
-- Th, Tj, Tk, Tn always honored
-- 6) start new cycle
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end entity atahost_dma_tctrl;
architecture structural of atahost_dma_tctrl is
component ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end component ro_cnt;
signal Tmdone, Tddone : std_logic;
signal iDIOR, iDIOW : std_logic;
begin
DIOR <= iDIOR; DIOW <= iDIOW;
-- 1) hookup Tm counter
tm_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Tm
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => go,
D => Tm,
done => Tmdone
);
-- 2) set (and reset) DIOR-/DIOW-
T2proc: process(clk, nReset)
begin
if (nReset = '0') then
iDIOR <= '0';
iDIOW <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDIOR <= '0';
iDIOW <= '0';
else
iDIOR <= (not we and Tmdone) or (iDIOR and not Tddone);
iDIOW <= ( we and Tmdone) or (iDIOW and not Tddone);
end if;
end if;
end process T2proc;
-- 3) hookup Td counter
td_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Td
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tmdone,
D => Td,
done => Tddone
);
-- generate data_strobe
gen_dstrb: process(clk)
begin
if (clk'event and clk = '1') then
dstrb <= Tddone; -- capture data at rising edge of DIOR-
end if;
end process gen_dstrb;
-- 4) negate DIOR-/DIOW- when Tddone
-- 5) hookup end_of_cycle counter
eoc_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tddone,
D => Teoc,
done => done
);
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture slew_limited of opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
v_amplified == gain * v_in;
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture slew_limited of opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
v_amplified == gain * v_in;
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture slew_limited of opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
v_amplified == gain * v_in;
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component will map an address sent to the memory so that
entity memory_read_proxy is
generic(STARTING_X: integer := 0; STARTING_Y: integer := 0; X_LENGTH: integer := 350; Y_LENGTH: integer := 350);
port(
x_in: in std_logic_vector(9 downto 0) := (others => '0');
y_in: in std_logic_vector(9 downto 0) := (others => '0');
memory_value: in std_logic_vector(0 downto 0) := (others => '0');
x_out: out std_logic_vector(9 downto 0) := (others => '0');
y_out: out std_logic_vector(9 downto 0) := (others => '0');
proxy_value: out std_logic_vector(0 downto 0) := (others => '0')
);
end memory_read_proxy;
architecture memory_read_proxy_arq of memory_read_proxy is
signal memory_data : std_logic_vector(0 downto 0) := (others => '0');
begin
process(x_in,y_in)
variable x_in_int : integer := 0;
variable y_in_int : integer := 0;
begin
x_in_int := to_integer(unsigned(x_in));
y_in_int := to_integer(unsigned(y_in));
memory_data <= memory_value;
if(x_in_int >= STARTING_X and
x_in_int <= (STARTING_X + X_LENGTH) and
y_in_int >= STARTING_Y and
y_in_int <= (STARTING_Y + Y_LENGTH)) then
x_out <= std_logic_vector(to_unsigned(x_in_int - STARTING_X,10));
y_out <= std_logic_vector(to_unsigned(y_in_int - STARTING_Y,10));
proxy_value <= memory_data;
else
x_out <= (others => '0');
y_out <= (others => '0');
proxy_value <= (others => '0');
end if;
end process;
end architecture; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_ML605 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 200 MHz
);
port (
ClockIn_200MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_200MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 200.000 0.000 50.0
-- CLK_OUT1 100.000 0.000 50.0
-- CLK_OUT2 125.000 0.000 50.0
-- CLK_OUT3 250.000 0.000 50.0
-- CLK_OUT4 10.000 0.000 50.0
--
architecture rtl of clknet_ClockNetwork_ML605 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 200 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (200 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_10MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_125MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_250MHz : STD_LOGIC;
signal MMCM_Clock_10MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_125MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_250MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_250MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset nor MMCM_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= not MMCM_Locked_d and MMCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
Locked <= MMCM_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "VIRTEX6"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_200MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => MMCM_Clock_10MHz,
O => MMCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => MMCM_Clock_125MHz,
O => MMCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 250 MHz BUFG
BUFG_Clock_250MHz : BUFG
port map (
I => MMCM_Clock_250MHz,
O => MMCM_Clock_250MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCM_ADV
generic map (
CLOCK_HOLD => FALSE,
STARTUP_WAIT => FALSE,
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => FALSE,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 5.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_DIVIDE => 4,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => 0.0,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_200MHz_BUFG,
CLKFBSTOPPED => open,
CLKOUT0 => MMCM_Clock_200MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_100MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_125MHz,
CLKOUT2B => open,
CLKOUT3 => MMCM_Clock_250MHz,
CLKOUT3B => open,
CLKOUT4 => MMCM_Clock_10MHz,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
Control_Clock_200MHz <= Control_Clock_BUFR;
Clock_250MHz <= MMCM_Clock_250MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_125MHz <= MMCM_Clock_125MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
Clock_10MHz <= MMCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncLocked250MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_250MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03186ent IS
END c14s03b00x00p42n01i03186ent;
ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : TEXT open write_mode is "iofile.01";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
WRITELINE (FILEV, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03186arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03186ent IS
END c14s03b00x00p42n01i03186ent;
ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : TEXT open write_mode is "iofile.01";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
WRITELINE (FILEV, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03186arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03186ent IS
END c14s03b00x00p42n01i03186ent;
ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : TEXT open write_mode is "iofile.01";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
WRITELINE (FILEV, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03186arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk_in : in std_ulogic;
clk_vga : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(3 downto 0); -- dm
ddr_dqs : inout std_logic_vector(3 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(3 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(1 downto 0); -- bank address
ddr_dq : inout std_logic_vector(31 downto 0); -- data
ddr_odt : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SVGA
vid_hsync : out std_logic;
vid_vsync : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal vgao : apbvga_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk : std_ulogic;
signal lclk_vga : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of lclk_vga : signal is true;
attribute syn_preserve of lclk_vga : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 125000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_in, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => spartan3, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000, clkmul => 2, clkdiv => 2,
TRFC => CFG_DDR2SP_TRFC,
-- readdly must be 0 for simulation, but 1 for hardware
--pragma translate_off
readdly => 0,
--pragma translate_on
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => CFG_DDR2SP_DATAWIDTH, odten => 0)
port map ( cgo.clklock, rstn, lclk, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk(1 downto 0) <= core_ddr_clk(1 downto 0);
ddr_clkb(1 downto 0) <= core_ddr_clkb(1 downto 0);
ddr_cke <= core_ddr_cke(0);
ddr_csb <= core_ddr_csb(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- There is no PS/2 port
apbo(5) <= apb_none;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
-- MISO is shared with Flash data 0
spii.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, gnd);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- SVGA -------------------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate
clk_vga_pad : clkpad generic map (tech => padtech) port map (clk_vga, lclk_vga);
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000,clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, lclk_vga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_r, vgao.video_out_r(7 downto 4));
video_out_g_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_g, vgao.video_out_g(7 downto 4));
video_out_b_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_b, vgao.video_out_b(7 downto 4));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan3A DSP 1800A board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity Or2 is
port(
a, b: in std_logic;
y: out std_logic
);
end Or2;
architecture Structural of Or2 is
begin
y <= a or b;
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2834.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RETURN is
end RETURN;
ENTITY c13s09b00x00p99n01i02834ent IS
END c13s09b00x00p99n01i02834ent;
ARCHITECTURE c13s09b00x00p99n01i02834arch OF c13s09b00x00p99n01i02834ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02834 - Reserved word RETURN can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02834arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2834.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RETURN is
end RETURN;
ENTITY c13s09b00x00p99n01i02834ent IS
END c13s09b00x00p99n01i02834ent;
ARCHITECTURE c13s09b00x00p99n01i02834arch OF c13s09b00x00p99n01i02834ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02834 - Reserved word RETURN can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02834arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2834.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RETURN is
end RETURN;
ENTITY c13s09b00x00p99n01i02834ent IS
END c13s09b00x00p99n01i02834ent;
ARCHITECTURE c13s09b00x00p99n01i02834arch OF c13s09b00x00p99n01i02834ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02834 - Reserved word RETURN can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02834arch;
|
-------------------------------------------------------------------------------
-- Title : Motor control
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM with deadtime
--
-- Memory Map:
-- Base Address + 0 | W | PWM value
-- Base Address + 0 | R | unused
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
use work.commutation_pkg.all;
entity bldc_motor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
-- Number of bits for the PWM generation (e.g. 12 => 0..4095)
WIDTH : positive := 12;
PRESCALER : positive
);
port (
driver_stage_p : out bldc_driver_stage_type;
hall_p : in hall_sensor_type;
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end bldc_motor_module;
-------------------------------------------------------------------------------
architecture behavioral of bldc_motor_module is
type bldc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
pwm_value : std_logic_vector(WIDTH - 1 downto 0); -- PWM value
sd : std_logic; -- Shutdown
dir : std_logic;
end record;
signal clk_en : std_logic := '1';
signal center : std_logic; -- currently not used
signal pwm : half_bridge_type;
signal r, rin : bldc_motor_module_type := (
data_out => (others => '0'),
pwm_value => (others => '0'),
sd => '1',
dir => '0'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i.addr, bus_i.data(15),
bus_i.data(WIDTH - 1 downto 0), bus_i.re, bus_i.we, r)
variable v : bldc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.pwm_value := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
v.dir := bus_i.data(14);
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
-- Deadtime settings:
-- 50 MHz clock => 20ns per cycle
-- T_DEAD = 20 * 20ns = 400ns
T_DEAD => 20)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => r.pwm_value,
break_p => break_p,
reset => '0',
clk => clk);
commutation_1 : commutation
port map (
driver_stage_p => driver_stage_p,
hall_p => hall_p,
pwm_p => pwm,
dir_p => r.dir,
sd_p => r.sd,
clk => clk);
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Motor control
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM with deadtime
--
-- Memory Map:
-- Base Address + 0 | W | PWM value
-- Base Address + 0 | R | unused
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
use work.commutation_pkg.all;
entity bldc_motor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
-- Number of bits for the PWM generation (e.g. 12 => 0..4095)
WIDTH : positive := 12;
PRESCALER : positive
);
port (
driver_stage_p : out bldc_driver_stage_type;
hall_p : in hall_sensor_type;
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end bldc_motor_module;
-------------------------------------------------------------------------------
architecture behavioral of bldc_motor_module is
type bldc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
pwm_value : std_logic_vector(WIDTH - 1 downto 0); -- PWM value
sd : std_logic; -- Shutdown
dir : std_logic;
end record;
signal clk_en : std_logic := '1';
signal center : std_logic; -- currently not used
signal pwm : half_bridge_type;
signal r, rin : bldc_motor_module_type := (
data_out => (others => '0'),
pwm_value => (others => '0'),
sd => '1',
dir => '0'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i.addr, bus_i.data(15),
bus_i.data(WIDTH - 1 downto 0), bus_i.re, bus_i.we, r)
variable v : bldc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.pwm_value := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
v.dir := bus_i.data(14);
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
-- Deadtime settings:
-- 50 MHz clock => 20ns per cycle
-- T_DEAD = 20 * 20ns = 400ns
T_DEAD => 20)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => r.pwm_value,
break_p => break_p,
reset => '0',
clk => clk);
commutation_1 : commutation
port map (
driver_stage_p => driver_stage_p,
hall_p => hall_p,
pwm_p => pwm,
dir_p => r.dir,
sd_p => r.sd,
clk => clk);
end behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(15); -- Negative
CCR(2) <= '1' when arith(15 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(16) xor arith(15); -- Overflow
CCR(0) <= arith(16); --Carry
RESULT <= arith(15 downto 0);
end Combinational;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reproducer_pkg is
-- Functions
function MINI(LEFT, RIGHT: unsigned) return unsigned;
function MINI(LEFT, RIGHT: integer) return integer;
end reproducer_pkg;
package body reproducer_pkg is
function MINI(LEFT, RIGHT: unsigned) return unsigned is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
function MINI(LEFT, RIGHT: integer) return integer is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
end reproducer_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reproducer_pkg.all;
entity reproducer is
port(
inputA : in unsigned(7 downto 0);
inputB : in unsigned(7 downto 0);
inputC : in integer;
inputD : in integer;
OutputA : out unsigned(7 downto 0);
OutputB : out integer
);
end reproducer;
architecture rtl of reproducer is
begin
OutputA <= minI(inputA, inputB);
OutputB <= minI(inputC, inputD);
end rtl;
|
--------------------------------------------------------------------------------
-- Title : VHDL Support Level Module
-- File : tri_mode_ethernet_mac_0_support.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the support level for the Tri-Mode
-- Ethernet MAC IP. It contains potentially shareable FPGA
-- resources such as clocking, reset and IDELAYCTRL logic.
-- This can be used as-is in a single core design, or adapted
-- for use with multi-core implementations.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block support level
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_support is
port(
gtx_clk : in std_logic;
gtx_clk_out : out std_logic;
gtx_clk90_out : out std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end tri_mode_ethernet_mac_0_support;
architecture wrapper of tri_mode_ethernet_mac_0_support is
------------------------------------------------------------------------------
-- Component declaration for the TEMAC core
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0
port(
gtx_clk : in std_logic;
gtx_clk90 : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Shareable logic component declarations
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support_clocking
port (
clk_in1 : in std_logic;
clk_out1 : out std_logic;
clk_out2 : out std_logic;
reset : in std_logic;
locked : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_support_resets
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic; -- The reset pulse for the IDELAYCTRL.
gtx_clk : in std_logic;
gtx_dcm_locked : in std_logic;
gtx_mmcm_rst_out : out std_logic -- The reset pulse for the MMCM.
);
end component;
-- Internal signals
signal mmcm_out_gtx_clk : std_logic;
signal mmcm_out_gtx_clk90 : std_logic;
signal gtx_mmcm_rst : std_logic;
signal gtx_mmcm_locked : std_logic;
signal idelayctrl_reset : std_logic;
signal idelayctrl_ready : std_logic;
begin
-----------------------------------------------------------------------------
-- Shareable logic
-----------------------------------------------------------------------------
gtx_clk_out <= mmcm_out_gtx_clk;
gtx_clk90_out <= mmcm_out_gtx_clk90;
-- Instantiate the sharable clocking logic
tri_mode_ethernet_mac_support_clocking_i : tri_mode_ethernet_mac_0_support_clocking
port map (
clk_in1 => gtx_clk,
clk_out1 => mmcm_out_gtx_clk,
clk_out2 => mmcm_out_gtx_clk90,
reset => gtx_mmcm_rst,
locked => gtx_mmcm_locked
);
-- Instantiate the sharable reset logic
tri_mode_ethernet_mac_support_resets_i : tri_mode_ethernet_mac_0_support_resets
port map(
glbl_rstn => glbl_rstn,
refclk => refclk,
idelayctrl_ready => idelayctrl_ready,
idelayctrl_reset_out => idelayctrl_reset,
gtx_clk => gtx_clk,
gtx_dcm_locked => gtx_mmcm_locked,
gtx_mmcm_rst_out => gtx_mmcm_rst
);
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
tri_mode_ethernet_mac_idelayctrl_common_i : IDELAYCTRL
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
RDY => idelayctrl_ready,
REFCLK => refclk,
RST => idelayctrl_reset
);
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
tri_mode_ethernet_mac_i : tri_mode_ethernet_mac_0
port map (
gtx_clk => mmcm_out_gtx_clk,
gtx_clk90 => mmcm_out_gtx_clk90,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Receiver Interface
----------------------------
rx_enable => rx_enable,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Transmitter Interface
-------------------------------
tx_enable => tx_enable,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- MAC Control Interface
------------------------
pause_req => pause_req,
pause_val => pause_val,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- RGMII Interface
------------------
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => mac_irq
);
end wrapper;
|
--------------------------------------------------------------------------------
-- Title : VHDL Support Level Module
-- File : tri_mode_ethernet_mac_0_support.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the support level for the Tri-Mode
-- Ethernet MAC IP. It contains potentially shareable FPGA
-- resources such as clocking, reset and IDELAYCTRL logic.
-- This can be used as-is in a single core design, or adapted
-- for use with multi-core implementations.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block support level
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_support is
port(
gtx_clk : in std_logic;
gtx_clk_out : out std_logic;
gtx_clk90_out : out std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end tri_mode_ethernet_mac_0_support;
architecture wrapper of tri_mode_ethernet_mac_0_support is
------------------------------------------------------------------------------
-- Component declaration for the TEMAC core
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0
port(
gtx_clk : in std_logic;
gtx_clk90 : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Shareable logic component declarations
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support_clocking
port (
clk_in1 : in std_logic;
clk_out1 : out std_logic;
clk_out2 : out std_logic;
reset : in std_logic;
locked : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_support_resets
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic; -- The reset pulse for the IDELAYCTRL.
gtx_clk : in std_logic;
gtx_dcm_locked : in std_logic;
gtx_mmcm_rst_out : out std_logic -- The reset pulse for the MMCM.
);
end component;
-- Internal signals
signal mmcm_out_gtx_clk : std_logic;
signal mmcm_out_gtx_clk90 : std_logic;
signal gtx_mmcm_rst : std_logic;
signal gtx_mmcm_locked : std_logic;
signal idelayctrl_reset : std_logic;
signal idelayctrl_ready : std_logic;
begin
-----------------------------------------------------------------------------
-- Shareable logic
-----------------------------------------------------------------------------
gtx_clk_out <= mmcm_out_gtx_clk;
gtx_clk90_out <= mmcm_out_gtx_clk90;
-- Instantiate the sharable clocking logic
tri_mode_ethernet_mac_support_clocking_i : tri_mode_ethernet_mac_0_support_clocking
port map (
clk_in1 => gtx_clk,
clk_out1 => mmcm_out_gtx_clk,
clk_out2 => mmcm_out_gtx_clk90,
reset => gtx_mmcm_rst,
locked => gtx_mmcm_locked
);
-- Instantiate the sharable reset logic
tri_mode_ethernet_mac_support_resets_i : tri_mode_ethernet_mac_0_support_resets
port map(
glbl_rstn => glbl_rstn,
refclk => refclk,
idelayctrl_ready => idelayctrl_ready,
idelayctrl_reset_out => idelayctrl_reset,
gtx_clk => gtx_clk,
gtx_dcm_locked => gtx_mmcm_locked,
gtx_mmcm_rst_out => gtx_mmcm_rst
);
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
tri_mode_ethernet_mac_idelayctrl_common_i : IDELAYCTRL
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
RDY => idelayctrl_ready,
REFCLK => refclk,
RST => idelayctrl_reset
);
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
tri_mode_ethernet_mac_i : tri_mode_ethernet_mac_0
port map (
gtx_clk => mmcm_out_gtx_clk,
gtx_clk90 => mmcm_out_gtx_clk90,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Receiver Interface
----------------------------
rx_enable => rx_enable,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Transmitter Interface
-------------------------------
tx_enable => tx_enable,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- MAC Control Interface
------------------------
pause_req => pause_req,
pause_val => pause_val,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- RGMII Interface
------------------
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => mac_irq
);
end wrapper;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
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conv_std_logic_vector(295,AMPL_WIDTH),
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conv_std_logic_vector(295,AMPL_WIDTH),
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conv_std_logic_vector(296,AMPL_WIDTH),
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conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
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conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
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conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
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conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(423,AMPL_WIDTH),
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conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
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conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
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conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
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conv_std_logic_vector(424,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
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conv_std_logic_vector(429,AMPL_WIDTH),
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conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
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conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
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conv_std_logic_vector(430,AMPL_WIDTH),
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conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(432,AMPL_WIDTH),
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conv_std_logic_vector(435,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
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conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
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conv_std_logic_vector(457,AMPL_WIDTH),
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conv_std_logic_vector(457,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
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conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
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conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
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conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(466,AMPL_WIDTH),
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conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
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conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
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conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
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conv_std_logic_vector(503,AMPL_WIDTH),
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conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
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conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
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conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
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conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
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conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
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conv_std_logic_vector(311,AMPL_WIDTH),
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conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
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conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
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conv_std_logic_vector(313,AMPL_WIDTH),
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conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
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conv_std_logic_vector(313,AMPL_WIDTH),
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conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
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conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
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conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
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conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
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conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
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conv_std_logic_vector(417,AMPL_WIDTH),
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conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
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conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
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conv_std_logic_vector(418,AMPL_WIDTH),
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conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
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conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
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conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
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conv_std_logic_vector(425,AMPL_WIDTH),
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conv_std_logic_vector(426,AMPL_WIDTH),
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conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
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conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
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conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
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conv_std_logic_vector(438,AMPL_WIDTH),
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conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
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conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
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conv_std_logic_vector(440,AMPL_WIDTH),
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conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
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conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
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conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
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conv_std_logic_vector(460,AMPL_WIDTH),
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conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
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conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
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conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
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conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
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conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
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conv_std_logic_vector(480,AMPL_WIDTH),
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conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(483,AMPL_WIDTH),
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conv_std_logic_vector(483,AMPL_WIDTH),
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conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
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conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
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conv_std_logic_vector(484,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
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conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
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conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
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conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
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conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
----------------- half_adder_structrual -----------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder--
entity half_adder_structrual is
port (A, B : in std_logic;
SUM, CARRY : out std_logic
);
end half_adder_structrual;
-- architecture structrual --
architecture structrual of half_adder_structrual is
begin
u1: entity work.and_2 port map(a=>A ,b=>B, carryS=>CARRY);
u2: entity work.xor_2 port map(a=>A, b=>B, sum=>SUM);
end structrual; |
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`protect begin_protected
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`protect end_protected
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_epc:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_epc_v2_0;
USE axi_epc_v2_0.axi_epc;
ENTITY cpu_axi_epc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END cpu_axi_epc_0_0;
ARCHITECTURE cpu_axi_epc_0_0_arch OF cpu_axi_epc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_epc IS
GENERIC (
C_S_AXI_CLK_PERIOD_PS : INTEGER;
C_PRH_CLK_PERIOD_PS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_PERIPHERALS : INTEGER;
C_PRH_MAX_AWIDTH : INTEGER;
C_PRH_MAX_DWIDTH : INTEGER;
C_PRH_MAX_ADWIDTH : INTEGER;
C_PRH_CLK_SUPPORT : INTEGER;
C_PRH0_BASEADDR : STD_LOGIC_VECTOR;
C_PRH0_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH0_FIFO_ACCESS : INTEGER;
C_PRH0_FIFO_OFFSET : INTEGER;
C_PRH0_AWIDTH : INTEGER;
C_PRH0_DWIDTH : INTEGER;
C_PRH0_DWIDTH_MATCH : INTEGER;
C_PRH0_SYNC : INTEGER;
C_PRH0_BUS_MULTIPLEX : INTEGER;
C_PRH0_ADDR_TSU : INTEGER;
C_PRH0_ADDR_TH : INTEGER;
C_PRH0_ADS_WIDTH : INTEGER;
C_PRH0_CSN_TSU : INTEGER;
C_PRH0_CSN_TH : INTEGER;
C_PRH0_WRN_WIDTH : INTEGER;
C_PRH0_WR_CYCLE : INTEGER;
C_PRH0_DATA_TSU : INTEGER;
C_PRH0_DATA_TH : INTEGER;
C_PRH0_RDN_WIDTH : INTEGER;
C_PRH0_RD_CYCLE : INTEGER;
C_PRH0_DATA_TOUT : INTEGER;
C_PRH0_DATA_TINV : INTEGER;
C_PRH0_RDY_TOUT : INTEGER;
C_PRH0_RDY_WIDTH : INTEGER;
C_PRH1_BASEADDR : STD_LOGIC_VECTOR;
C_PRH1_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH1_FIFO_ACCESS : INTEGER;
C_PRH1_FIFO_OFFSET : INTEGER;
C_PRH1_AWIDTH : INTEGER;
C_PRH1_DWIDTH : INTEGER;
C_PRH1_DWIDTH_MATCH : INTEGER;
C_PRH1_SYNC : INTEGER;
C_PRH1_BUS_MULTIPLEX : INTEGER;
C_PRH1_ADDR_TSU : INTEGER;
C_PRH1_ADDR_TH : INTEGER;
C_PRH1_ADS_WIDTH : INTEGER;
C_PRH1_CSN_TSU : INTEGER;
C_PRH1_CSN_TH : INTEGER;
C_PRH1_WRN_WIDTH : INTEGER;
C_PRH1_WR_CYCLE : INTEGER;
C_PRH1_DATA_TSU : INTEGER;
C_PRH1_DATA_TH : INTEGER;
C_PRH1_RDN_WIDTH : INTEGER;
C_PRH1_RD_CYCLE : INTEGER;
C_PRH1_DATA_TOUT : INTEGER;
C_PRH1_DATA_TINV : INTEGER;
C_PRH1_RDY_TOUT : INTEGER;
C_PRH1_RDY_WIDTH : INTEGER;
C_PRH2_BASEADDR : STD_LOGIC_VECTOR;
C_PRH2_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH2_FIFO_ACCESS : INTEGER;
C_PRH2_FIFO_OFFSET : INTEGER;
C_PRH2_AWIDTH : INTEGER;
C_PRH2_DWIDTH : INTEGER;
C_PRH2_DWIDTH_MATCH : INTEGER;
C_PRH2_SYNC : INTEGER;
C_PRH2_BUS_MULTIPLEX : INTEGER;
C_PRH2_ADDR_TSU : INTEGER;
C_PRH2_ADDR_TH : INTEGER;
C_PRH2_ADS_WIDTH : INTEGER;
C_PRH2_CSN_TSU : INTEGER;
C_PRH2_CSN_TH : INTEGER;
C_PRH2_WRN_WIDTH : INTEGER;
C_PRH2_WR_CYCLE : INTEGER;
C_PRH2_DATA_TSU : INTEGER;
C_PRH2_DATA_TH : INTEGER;
C_PRH2_RDN_WIDTH : INTEGER;
C_PRH2_RD_CYCLE : INTEGER;
C_PRH2_DATA_TOUT : INTEGER;
C_PRH2_DATA_TINV : INTEGER;
C_PRH2_RDY_TOUT : INTEGER;
C_PRH2_RDY_WIDTH : INTEGER;
C_PRH3_BASEADDR : STD_LOGIC_VECTOR;
C_PRH3_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH3_FIFO_ACCESS : INTEGER;
C_PRH3_FIFO_OFFSET : INTEGER;
C_PRH3_AWIDTH : INTEGER;
C_PRH3_DWIDTH : INTEGER;
C_PRH3_DWIDTH_MATCH : INTEGER;
C_PRH3_SYNC : INTEGER;
C_PRH3_BUS_MULTIPLEX : INTEGER;
C_PRH3_ADDR_TSU : INTEGER;
C_PRH3_ADDR_TH : INTEGER;
C_PRH3_ADS_WIDTH : INTEGER;
C_PRH3_CSN_TSU : INTEGER;
C_PRH3_CSN_TH : INTEGER;
C_PRH3_WRN_WIDTH : INTEGER;
C_PRH3_WR_CYCLE : INTEGER;
C_PRH3_DATA_TSU : INTEGER;
C_PRH3_DATA_TH : INTEGER;
C_PRH3_RDN_WIDTH : INTEGER;
C_PRH3_RD_CYCLE : INTEGER;
C_PRH3_DATA_TOUT : INTEGER;
C_PRH3_DATA_TINV : INTEGER;
C_PRH3_RDY_TOUT : INTEGER;
C_PRH3_RDY_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END COMPONENT axi_epc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF prh_clk: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CLK";
ATTRIBUTE X_INTERFACE_INFO OF prh_rst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RST";
ATTRIBUTE X_INTERFACE_INFO OF prh_cs_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CS_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_addr: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF prh_ads: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADS";
ATTRIBUTE X_INTERFACE_INFO OF prh_be: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BE";
ATTRIBUTE X_INTERFACE_INFO OF prh_rnw: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF prh_rd_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RD_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_wr_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF WR_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_burst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BURST";
ATTRIBUTE X_INTERFACE_INFO OF prh_rdy: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RDY";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_i: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_I";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_o: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_O";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_t: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_T";
BEGIN
U0 : axi_epc
GENERIC MAP (
C_S_AXI_CLK_PERIOD_PS => 10000,
C_PRH_CLK_PERIOD_PS => 10000,
C_FAMILY => "zynq",
C_INSTANCE => "axi_epc_inst",
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_PERIPHERALS => 1,
C_PRH_MAX_AWIDTH => 32,
C_PRH_MAX_DWIDTH => 32,
C_PRH_MAX_ADWIDTH => 32,
C_PRH_CLK_SUPPORT => 0,
C_PRH0_BASEADDR => X"80600000",
C_PRH0_HIGHADDR => X"8060FFFF",
C_PRH0_FIFO_ACCESS => 0,
C_PRH0_FIFO_OFFSET => 0,
C_PRH0_AWIDTH => 32,
C_PRH0_DWIDTH => 32,
C_PRH0_DWIDTH_MATCH => 0,
C_PRH0_SYNC => 1,
C_PRH0_BUS_MULTIPLEX => 0,
C_PRH0_ADDR_TSU => 0,
C_PRH0_ADDR_TH => 0,
C_PRH0_ADS_WIDTH => 0,
C_PRH0_CSN_TSU => 0,
C_PRH0_CSN_TH => 0,
C_PRH0_WRN_WIDTH => 0,
C_PRH0_WR_CYCLE => 0,
C_PRH0_DATA_TSU => 0,
C_PRH0_DATA_TH => 0,
C_PRH0_RDN_WIDTH => 0,
C_PRH0_RD_CYCLE => 0,
C_PRH0_DATA_TOUT => 0,
C_PRH0_DATA_TINV => 0,
C_PRH0_RDY_TOUT => 0,
C_PRH0_RDY_WIDTH => 100000,
C_PRH1_BASEADDR => X"B000FFFF",
C_PRH1_HIGHADDR => X"BFFFFFFF",
C_PRH1_FIFO_ACCESS => 0,
C_PRH1_FIFO_OFFSET => 0,
C_PRH1_AWIDTH => 32,
C_PRH1_DWIDTH => 32,
C_PRH1_DWIDTH_MATCH => 0,
C_PRH1_SYNC => 0,
C_PRH1_BUS_MULTIPLEX => 0,
C_PRH1_ADDR_TSU => 0,
C_PRH1_ADDR_TH => 0,
C_PRH1_ADS_WIDTH => 0,
C_PRH1_CSN_TSU => 0,
C_PRH1_CSN_TH => 0,
C_PRH1_WRN_WIDTH => 0,
C_PRH1_WR_CYCLE => 0,
C_PRH1_DATA_TSU => 0,
C_PRH1_DATA_TH => 0,
C_PRH1_RDN_WIDTH => 0,
C_PRH1_RD_CYCLE => 0,
C_PRH1_DATA_TOUT => 0,
C_PRH1_DATA_TINV => 0,
C_PRH1_RDY_TOUT => 0,
C_PRH1_RDY_WIDTH => 0,
C_PRH2_BASEADDR => X"C000FFFF",
C_PRH2_HIGHADDR => X"CFFFFFFF",
C_PRH2_FIFO_ACCESS => 0,
C_PRH2_FIFO_OFFSET => 0,
C_PRH2_AWIDTH => 32,
C_PRH2_DWIDTH => 32,
C_PRH2_DWIDTH_MATCH => 0,
C_PRH2_SYNC => 0,
C_PRH2_BUS_MULTIPLEX => 0,
C_PRH2_ADDR_TSU => 0,
C_PRH2_ADDR_TH => 0,
C_PRH2_ADS_WIDTH => 0,
C_PRH2_CSN_TSU => 0,
C_PRH2_CSN_TH => 0,
C_PRH2_WRN_WIDTH => 0,
C_PRH2_WR_CYCLE => 0,
C_PRH2_DATA_TSU => 0,
C_PRH2_DATA_TH => 0,
C_PRH2_RDN_WIDTH => 0,
C_PRH2_RD_CYCLE => 0,
C_PRH2_DATA_TOUT => 0,
C_PRH2_DATA_TINV => 0,
C_PRH2_RDY_TOUT => 0,
C_PRH2_RDY_WIDTH => 0,
C_PRH3_BASEADDR => X"D000FFFF",
C_PRH3_HIGHADDR => X"DFFFFFFF",
C_PRH3_FIFO_ACCESS => 0,
C_PRH3_FIFO_OFFSET => 0,
C_PRH3_AWIDTH => 32,
C_PRH3_DWIDTH => 32,
C_PRH3_DWIDTH_MATCH => 0,
C_PRH3_SYNC => 0,
C_PRH3_BUS_MULTIPLEX => 0,
C_PRH3_ADDR_TSU => 0,
C_PRH3_ADDR_TH => 0,
C_PRH3_ADS_WIDTH => 0,
C_PRH3_CSN_TSU => 0,
C_PRH3_CSN_TH => 0,
C_PRH3_WRN_WIDTH => 0,
C_PRH3_WR_CYCLE => 0,
C_PRH3_DATA_TSU => 0,
C_PRH3_DATA_TH => 0,
C_PRH3_RDN_WIDTH => 0,
C_PRH3_RD_CYCLE => 0,
C_PRH3_DATA_TOUT => 0,
C_PRH3_DATA_TINV => 0,
C_PRH3_RDY_TOUT => 0,
C_PRH3_RDY_WIDTH => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
prh_clk => prh_clk,
prh_rst => prh_rst,
prh_cs_n => prh_cs_n,
prh_addr => prh_addr,
prh_ads => prh_ads,
prh_be => prh_be,
prh_rnw => prh_rnw,
prh_rd_n => prh_rd_n,
prh_wr_n => prh_wr_n,
prh_burst => prh_burst,
prh_rdy => prh_rdy,
prh_data_i => prh_data_i,
prh_data_o => prh_data_o,
prh_data_t => prh_data_t
);
END cpu_axi_epc_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:29:32 10/15/2014
-- Design Name:
-- Module Name: vga_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
gr : out std_logic_vector(2 downto 0);
re : out std_logic_vector(2 downto 0);
bl : out std_logic_vector(1 downto 0)
);
end vga_ctrl;
architecture Behavioral of vga_ctrl is
constant HD : integer := 640; -- h display
constant HF : integer := 16; -- h front porch
constant HB : integer := 48; -- h back porch
constant HR : integer := 96; -- h retrace
constant HT : integer := 799; -- h total
constant VD : integer := 480; -- v display
constant VF : integer := 11; -- v front porch
constant VB : integer := 31; -- v back porch
constant VR : integer := 2; -- v retrace
constant VT : integer := 524; -- v total
signal clk_div_c, clk_div_n : unsigned(1 downto 0); -- mod 4
signal h_count_c, h_count_n, v_count_c, v_count_n : unsigned(9 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
clk_div_c <= (others => '0');
h_count_c <= (others => '0');
v_count_c <= (others => '0');
else
clk_div_c <= clk_div_n;
h_count_c <= h_count_n;
v_count_c <= v_count_n;
end if;
end if;
end process;
clk_div_n <= clk_div_c + 1;
h_proc: process(clk_div_c, h_count_c)
begin
h_count_n <= h_count_c;
if (clk_div_c = "11") then
h_count_n <= h_count_c + 1;
if h_count_c = HT then
h_count_n <= (others => '0');
end if;
end if;
end process;
v_proc: process(clk_div_c, h_count_c, v_count_c)
begin
v_count_n <= v_count_c;
if (clk_div_c = "11" and h_count_c = HT) then
v_count_n <= v_count_c + 1;
if v_count_c = VT then
v_count_n <= (others => '0');
end if;
end if;
end process;
--
end Behavioral; |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(width-1 downto 0);
datab : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
add_sub : in std_logic;
aclr : in std_logic;
cin : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(0-1 downto 0);
datab : in std_logic_vector(0-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(width-1 downto 0);
datab : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
add_sub : in std_logic;
aclr : in std_logic;
cin : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(0-1 downto 0);
datab : in std_logic_vector(0-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(width-1 downto 0);
datab : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
add_sub : in std_logic;
aclr : in std_logic;
cin : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(0-1 downto 0);
datab : in std_logic_vector(0-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic;
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic;
dataa : in std_logic_vector(width-1 downto 0);
datab : in std_logic_vector(width-1 downto 0);
cout : out std_logic;
add_sub : in std_logic;
aclr : in std_logic;
cin : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic;
clock : in std_logic;
dataa : in std_logic_vector(0-1 downto 0);
datab : in std_logic_vector(0-1 downto 0);
ena : in std_logic;
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1876.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01876ent IS
END c07s01b00x00p08n01i01876ent;
ARCHITECTURE c07s01b00x00p08n01i01876arch OF c07s01b00x00p08n01i01876ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := blk; --block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01876 - Block labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01876arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1876.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01876ent IS
END c07s01b00x00p08n01i01876ent;
ARCHITECTURE c07s01b00x00p08n01i01876arch OF c07s01b00x00p08n01i01876ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := blk; --block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01876 - Block labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01876arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1876.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01876ent IS
END c07s01b00x00p08n01i01876ent;
ARCHITECTURE c07s01b00x00p08n01i01876arch OF c07s01b00x00p08n01i01876ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := blk; --block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01876 - Block labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01876arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02064ent IS
END c07s02b04x00p01n02i02064ent;
ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
INTV := INTV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02064ent IS
END c07s02b04x00p01n02i02064ent;
ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
INTV := INTV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02064ent IS
END c07s02b04x00p01n02i02064ent;
ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
INTV := INTV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03147ent_a IS
END c05s02b02x00p08n01i03147ent_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03147"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_b;
--
ENTITY c05s02b02x00p08n01i03147ent IS
END c05s02b02x00p08n01i03147ent;
ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
component c05s02b02x00p08n01i03147ent_c
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03147ent_c;
END c05s02b02x00p08n01i03147arch;
configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
for c05s02b02x00p08n01i03147arch
for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
end for;
end for;
end c05s02b02x00p08n01i03147cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03147ent_a IS
END c05s02b02x00p08n01i03147ent_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03147"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_b;
--
ENTITY c05s02b02x00p08n01i03147ent IS
END c05s02b02x00p08n01i03147ent;
ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
component c05s02b02x00p08n01i03147ent_c
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03147ent_c;
END c05s02b02x00p08n01i03147arch;
configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
for c05s02b02x00p08n01i03147arch
for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
end for;
end for;
end c05s02b02x00p08n01i03147cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03147ent_a IS
END c05s02b02x00p08n01i03147ent_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_a;
ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03147"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03147arch_b;
--
ENTITY c05s02b02x00p08n01i03147ent IS
END c05s02b02x00p08n01i03147ent;
ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
component c05s02b02x00p08n01i03147ent_c
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03147ent_c;
END c05s02b02x00p08n01i03147arch;
configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
for c05s02b02x00p08n01i03147arch
for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
end for;
end for;
end c05s02b02x00p08n01i03147cfg;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: d2prc
-- File: d2prc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc dependable mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library techmap;
use techmap.gencomp.all;
entity d2prc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9; -- true FIFO depth = 2**fifo_depth
crc_block : integer := 10); -- Number of 32-bit words in a CRC-block
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end d2prc;
architecture d2prc_rtl of d2prc is
type icap_state is (IDLE, START, READ_LENGTH, WAIT_AB, WRITE_ICAP, WRITE_ICAP_VERIFY, END_CONFIG, ABORT, ICAP_ERROR_LATENCY);
signal pstate, nstate : icap_state;
type ahb_state is (IDLE_AHB, START_AHB, GRANTED, CHECK_CRC, WAIT_WRITE_END, CHECK_LAST_CRC, BUS_CNTL_ERROR, FIFO_FULL, ICAP_ERROR, CRC_ERROR);
signal present_state, next_state : ahb_state;
-- fifo types
type ififo_type is record
wen : std_ulogic;
waddress : std_logic_vector(fifo_depth downto 0);
waddress_gray : std_logic_vector(fifo_depth downto 0);
idata : std_logic_vector(31 downto 0);
full : std_ulogic;
end record;
type ofifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(fifo_depth downto 0);
raddress_gray : std_logic_vector(fifo_depth downto 0);
odata : std_logic_vector(31 downto 0);
empty : std_ulogic;
end record;
-- cdc control signals for async_dprc
type cdc_async is record
start : std_ulogic;
stop : std_ulogic;
icap_errn : std_ulogic;
icap_end : std_ulogic;
end record;
-- dummy fifo types
type icfifo_type is record
wen : std_ulogic;
waddress : std_logic_vector(4 downto 0);
waddress_gray : std_logic_vector(4 downto 0);
idata : std_logic_vector(0 downto 0);
full : std_ulogic;
end record;
type ocfifo_type is record
ren : std_ulogic;
raddress : std_logic_vector(4 downto 0);
raddress_gray : std_logic_vector(4 downto 0);
odata : std_logic_vector(0 downto 0);
empty : std_ulogic;
end record;
signal fifo_in, regfifo_in : ififo_type;
signal cfifoi, regcfifoi : icfifo_type;
signal fifo_out, regfifo_out : ofifo_type;
signal cfifoo, regcfifoo : ocfifo_type;
signal raddr_sync, waddr_sync : std_logic_vector(fifo_depth downto 0);
signal craddr_sync, cwaddr_sync : std_logic_vector(4 downto 0);
signal cdc_ahb, rcdc_ahb, cdc_icap, rcdc_icap : cdc_async;
type regs_ahb is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
address : std_logic_vector(31 downto 0);
crc_signature : std_logic_vector(31 downto 0);
c_block : std_logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
type regs_icap is record
c_bitstream : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
c_block : std_Logic_vector(integer(ceil(log2(real(crc_block))))-1 downto 0); -- size the counter depending on the actual crc block size
end record;
signal reg, regin : regs_ahb;
signal regicap, reginicap :regs_icap;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= fifo_out.odata;
fifo_in.idata <= dmao.Data;
cfifoi.idata(0) <= cfifoi.wen;
-------------------------------
-- ahb bus clock domain
-------------------------------
ahbcomb: process(raddr_sync, craddr_sync, regfifo_in, regcfifoi, rcdc_ahb, cdc_ahb, reg, present_state, rstn, rstact, apbregi, dmao)
variable vfifo_in : ififo_type;
variable vcfifoi : icfifo_type;
variable vcdc_ahb : cdc_async;
variable regv : regs_ahb;
variable raddr_sync_decoded : std_logic_vector(fifo_depth downto 0);
variable craddr_sync_decoded : std_logic_vector(4 downto 0);
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
rstact <= '0';
vfifo_in.wen := '0';
vcfifoi.wen := '0';
regv := reg;
vcdc_ahb := rcdc_ahb;
vcdc_ahb.start := '0';
vcdc_ahb.stop := '0';
-- initialize fifo signals
vfifo_in.waddress := regfifo_in.waddress;
vfifo_in.full := '0';
vcfifoi.waddress := regcfifoi.waddress;
vcfifoi.full := '0';
-- fifos full generation
gray_decoder(raddr_sync,fifo_depth,raddr_sync_decoded);
if (vfifo_in.waddress(fifo_depth)=raddr_sync_decoded(fifo_depth) and (vfifo_in.waddress(fifo_depth-1 downto 0)-raddr_sync_decoded(fifo_depth-1 downto 0))>(2**fifo_depth-16)) then
vfifo_in.full := '1';
elsif (vfifo_in.waddress(fifo_depth)/= raddr_sync_decoded(fifo_depth) and (raddr_sync_decoded(fifo_depth-1 downto 0)-vfifo_in.waddress(fifo_depth-1 downto 0))<16) then
vfifo_in.full := '1';
end if;
gray_decoder(craddr_sync,4,craddr_sync_decoded);
if (vcfifoi.waddress(4)=craddr_sync_decoded(4) and (vcfifoi.waddress(3 downto 0)-craddr_sync_decoded(3 downto 0))>10) then
vcfifoi.full := '1';
elsif (vcfifoi.waddress(4)/= craddr_sync(4) and (craddr_sync_decoded(3 downto 0)-vcfifoi.waddress(3 downto 0))<10) then
vcfifoi.full := '1';
end if;
case present_state is
when IDLE_AHB =>
if (apbregi.control/=X"00000000") then
next_state <= START_AHB;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- initialize counter
regv.address := apbregi.address;
vcdc_ahb.start := '1'; -- start icap write controller
regv.crc_signature := (others=>'1'); --reset crc_signature
else
next_state <= IDLE_AHB;
end if;
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
when START_AHB =>
if (dmao.Grant and dmao.Ready)='1' then
if (regv.c_block=0) then
next_state <= CHECK_CRC;
else
next_state <= GRANTED;
end if;
else
next_state <= START_AHB;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
vcdc_ahb.start := '1'; -- start icap write controller
when GRANTED =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, request last crc
next_state <= CHECK_LAST_CRC;
elsif ((vfifo_in.full='1') or (vcfifoi.full='1')) then
next_state<=FIFO_FULL;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when CHECK_LAST_CRC =>
if (regv.c_ready=1) and (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
next_state <= WAIT_WRITE_END;
vcfifoi.wen := '1'; -- validate block
end if;
else
next_state <= CHECK_LAST_CRC;
end if;
when CHECK_CRC =>
if (dmao.Ready='1') then -- if CRC word received, check CRC and start downloading another block
if (regv.crc_signature/=dmao.Data) then -- do not write signature in data FIFO
next_state <= CRC_ERROR;
vcdc_ahb.stop := '1';
else
if (regv.c_grant=0) then
next_state <= CHECK_LAST_CRC;
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
vcfifoi.wen := '1'; -- validate block
end if;
regv.c_block := std_logic_vector(to_unsigned(crc_block-1,regv.c_block'length)); -- re-initialize counter
else
next_state <= CHECK_CRC;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
when FIFO_FULL =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif ((regv.c_grant=regv.c_ready) and (vfifo_in.full='0') and (vcfifoi.full='0')) then
next_state <= GRANTED;
else
next_state <= FIFO_FULL;
end if;
when WAIT_WRITE_END =>
if (regv.c_block=0) and (dmao.Ready='1') then
next_state <= CHECK_CRC;
elsif (cdc_ahb.icap_end='1') then
next_state <= IDLE_AHB;
regv.rst_persist := '0';
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
else
next_state <= WAIT_WRITE_END;
end if;
when CRC_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0001";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when BUS_CNTL_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
vcdc_ahb.stop := '1';
regv.rst_persist := '1';
when ICAP_ERROR =>
next_state <= IDLE_AHB;
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
vfifo_in.waddress := (others=>'0');
vcfifoi.waddress := (others=>'0');
regv.rst_persist := '1';
end case;
-- CRC check and fifo write enables
if (dmao.Ready='1') then
if (present_state/=CHECK_CRC) or (present_state=CHECK_LAST_CRC and regv.c_ready>1) then
crc(dmao.Data,reg.crc_signature,regv.crc_signature);
vfifo_in.wen := '1';
end if;
end if;
if (present_state/=IDLE_AHB) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (present_state/=IDLE_AHB) and (present_state/=CHECK_CRC) and (dmao.Ready='1') then
regv.c_block := regv.c_block-1;
end if;
if (present_state/=IDLE_AHB) and (cdc_ahb.icap_errn='0') then
next_state <= ICAP_ERROR;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
vcdc_ahb.stop := '1';
end if;
-- write fifos
if vfifo_in.wen = '1' then
vfifo_in.waddress := vfifo_in.waddress +1;
end if;
if vcfifoi.wen = '1' then
vcfifoi.waddress := vcfifoi.waddress +1;
end if;
gray_encoder(vfifo_in.waddress,vfifo_in.waddress_gray);
gray_encoder(vcfifoi.waddress,vcfifoi.waddress_gray);
-- fifos write address to be latched and synchronized
fifo_in.waddress_gray <= vfifo_in.waddress_gray;
cfifoi.waddress_gray <= vcfifoi.waddress_gray;
fifo_in.waddress <= vfifo_in.waddress;
cfifoi.waddress <= vcfifoi.waddress;
fifo_in.wen <= vfifo_in.wen;
cfifoi.wen <= vcfifoi.wen;
-- update fifo full
fifo_in.full <= vfifo_in.full;
cfifoi.full <= vcfifoi.full;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
cdc_ahb.start <= vcdc_ahb.start;
cdc_ahb.stop <= vcdc_ahb.stop;
regin <= regv;
end process;
ahbreg: process(clkm,rstn)
begin
if rstn='0' then
regfifo_in.waddress <= (others =>'0');
regcfifoi.waddress <= (others =>'0');
regfifo_in.waddress_gray <= (others =>'0');
regcfifoi.waddress_gray <= (others =>'0');
rcdc_ahb.start <= '0';
rcdc_ahb.stop <= '0';
present_state <= IDLE_AHB;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.crc_signature <= (others=>'1');
reg.c_block <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
regfifo_in <= fifo_in;
regcfifoi <= cfifoi;
rcdc_ahb <= cdc_ahb;
present_state <= next_state;
reg <= regin;
end if;
end process;
-------------------------------
-- synchronization registers
-------------------------------
-- input d is already registered in the source clock domain
syn_gen0: for i in 0 to fifo_depth generate -- data fifo addresses
syncreg_inst0: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regfifo_in.waddress_gray(i), q => waddr_sync(i));
syncreg_inst1: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regfifo_out.raddress_gray(i), q => raddr_sync(i));
end generate;
syn_gen01: for i in 0 to 4 generate -- dummy control fifo addresses
syncreg_inst01: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => regcfifoi.waddress_gray(i), q => cwaddr_sync(i));
syncreg_inst11: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => regcfifoo.raddress_gray(i), q => craddr_sync(i));
end generate;
-- CDC control signals
syncreg_inst2: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_errn, q => cdc_ahb.icap_errn);
syncreg_inst3: syncreg generic map (tech => technology, stages => 2)
port map(clk => clkm, d => rcdc_icap.icap_end, q => cdc_ahb.icap_end);
syncreg_inst4: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.start, q => cdc_icap.start);
syncreg_inst5: syncreg generic map (tech => technology, stages => 2)
port map(clk => clk100, d => rcdc_ahb.stop, q => cdc_icap.stop);
-------------------------------
-- icap clock domain
-------------------------------
icapcomb: process(waddr_sync, cwaddr_sync, regfifo_out, fifo_out, regcfifoo, cfifoo, cdc_icap, pstate, regicap, icapo)
variable vfifo_out : ofifo_type;
variable vcfifoo : ocfifo_type;
variable vcdc_icap : cdc_async;
variable vregicap : regs_icap;
begin
icapi.cen <= '1';
icapi.wen <= '1';
vcdc_icap.icap_end := '0';
vcdc_icap.icap_errn := '1';
vregicap := regicap;
-- initialize fifo signals
vfifo_out.raddress := regfifo_out.raddress;
vfifo_out.empty := '0';
vfifo_out.ren := '0';
vcfifoo.raddress := regcfifoo.raddress;
vcfifoo.empty := '0';
vcfifoo.ren := '0';
-- fifos empty generation
gray_encoder(vfifo_out.raddress,vfifo_out.raddress_gray);
if (vfifo_out.raddress_gray=waddr_sync) then
vfifo_out.empty := '1';
end if;
gray_encoder(vcfifoo.raddress,vcfifoo.raddress_gray);
if (vcfifoo.raddress_gray=cwaddr_sync) then
vcfifoo.empty := '1';
end if;
-- fsm
case pstate is
when IDLE =>
if (cdc_icap.start='1') then
nstate <= START;
else
nstate <= IDLE;
end if;
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- initialize counter
when START =>
if (cfifoo.empty='0') then -- read first word of the bitstream & first checked block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= READ_LENGTH;
else
nstate <= START;
end if;
icapi.wen <= '0';
when READ_LENGTH =>
if (vregicap.c_block=0) then
nstate <= WAIT_AB;
else
nstate <= WRITE_ICAP;
end if;
vregicap.c_bitstream := fifo_out.odata(19 downto 0);
vfifo_out.ren := '1';
icapi.wen <= '0';
when WAIT_AB =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (cfifoo.empty='0') then -- download another block
vfifo_out.ren := '1';
vcfifoo.ren := '1';
nstate <= WRITE_ICAP;
else
nstate <= WAIT_AB;
end if;
icapi.wen <= '0';
vregicap.c_block:=std_logic_vector(to_unsigned(crc_block-1,vregicap.c_block'length)); -- reinitialize counter
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when WRITE_ICAP_VERIFY =>
if (vregicap.c_bitstream=1) then
nstate <= ICAP_ERROR_LATENCY;
elsif (vregicap.c_block=0) then
nstate <= WAIT_AB; -- wait for another block
vfifo_out.ren := '1';
elsif (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.ren := '1';
else
nstate <= WRITE_ICAP_VERIFY;
vfifo_out.ren := '1';
end if;
icapi.wen <= '0';
icapi.cen <= not(regfifo_out.ren); --1 cycle latency with respect to fifo_out.ren
when END_CONFIG =>
nstate <= IDLE;
vfifo_out.raddress := (others=>'0');
vcfifoo.raddress := (others=>'0');
vcdc_icap.icap_end := '1';
when ABORT =>
if (vregicap.c_latency=4) then
nstate <= IDLE;
vregicap.c_latency := (others=>'0');
else
nstate <= ABORT;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
vfifo_out.raddress := (others=>'0'); -- reset fifo address
vcfifoo.raddress := (others=>'0');
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_errn:='0'; -- signal icap error to the ahb clock domain
elsif (vregicap.c_latency=4) then
nstate <= END_CONFIG;
vregicap.c_latency := (others=>'0');
vcdc_icap.icap_end := '1';
else
nstate <= ICAP_ERROR_LATENCY;
vregicap.c_latency := vregicap.c_latency+1;
end if;
icapi.wen <= '0';
end case;
if (cdc_icap.stop='1') then
nstate <= ABORT;
vregicap.c_latency := (others=>'0');
vfifo_out.ren := '1';
end if;
-- read fifos
if vfifo_out.ren = '1' then
vfifo_out.raddress := vfifo_out.raddress +1;
end if;
if vcfifoo.ren = '1' then
vcfifoo.raddress := vcfifoo.raddress +1;
end if;
if vfifo_out.ren = '1' then
vregicap.c_bitstream := vregicap.c_bitstream -1; -- because fifo introduces 1-cycle latency on output data
vregicap.c_block := vregicap.c_block-1;
end if;
-- fifos read address to be latched and synchronized
fifo_out.raddress_gray <= vfifo_out.raddress_gray;
cfifoo.raddress_gray <= vcfifoo.raddress_gray;
fifo_out.raddress <= vfifo_out.raddress;
cfifoo.raddress <= vcfifoo.raddress;
-- update fifo empty
fifo_out.empty <= vfifo_out.empty;
cfifoo.empty <= vcfifoo.empty;
fifo_out.ren <= vfifo_out.ren;
cfifoo.ren <= vcfifoo.ren;
cdc_icap.icap_errn <= vcdc_icap.icap_errn;
cdc_icap.icap_end <= vcdc_icap.icap_end;
reginicap <= vregicap;
end process;
icapreg: process(clk100,rstn)
begin
if rstn='0' then
regfifo_out.raddress <= (others =>'0');
regfifo_out.raddress_gray <= (others =>'0');
regfifo_out.ren <= '0';
regcfifoo.raddress <= (others =>'0');
regcfifoo.raddress_gray <= (others =>'0');
regcfifoo.ren <= '0';
regicap.c_bitstream <= (others =>'0');
regicap.c_latency <= (others =>'0');
regicap.c_block <= (others=>'0');
rcdc_icap.start <= '0';
rcdc_icap.stop <= '0';
elsif rising_edge(clk100) then
regfifo_out.raddress <= fifo_out.raddress;
regfifo_out.raddress_gray <= fifo_out.raddress_gray;
regfifo_out.ren <= fifo_out.ren;
regcfifoo.raddress <= cfifoo.raddress;
regcfifoo.raddress_gray <= cfifoo.raddress_gray;
pstate <= nstate;
regicap <= reginicap;
rcdc_icap <= cdc_icap;
end if;
end process;
--Instantiate data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => fifo_depth, dbits => 32, sepclk => 1) -- 2**fifo_depth 32-bit data RAM
port map (clk100, fifo_out.ren, fifo_out.raddress(fifo_depth-1 downto 0), fifo_out.odata, clkm, fifo_in.wen, fifo_in.waddress(fifo_depth-1 downto 0), fifo_in.idata);
end d2prc_rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c04s03b02x00p01n01i00091pkg IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; --unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; --constrained array type
SUBTYPE ust_subchary IS ut_chary; --unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); --constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); --constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
END c04s03b02x00p01n01i00091pkg;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent_a IS
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END c04s03b02x00p01n01i00091ent_a;
ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
BEGIN
PROCESS
BEGIN
--
FOR I IN 1 TO 7
LOOP
ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 7
LOOP
ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN NUL TO ENQ
LOOP
ASSERT ut_chary_prt(I) = INTEGER'LEFT
REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 1 TO 10
LOOP
ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN '0' TO '9'
LOOP
ASSERT cst_digit_prt(I) = INTEGER'LEFT
REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE; END LOOP;
ASSERT rt_date_prt.day = 0 REPORT " rt_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.month = Jan REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.year = 0 REPORT " rt_date_prt.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.day = 0 REPORT "rst_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.month = Jan REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.year = 0 REPORT "rst_date_prt.year not properly intialized" SEVERITY FAILURE;
assert NOT( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***PASSED TEST: c04s03b02x00p01n01i00091"
severity NOTE;
assert ( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
severity ERROR;
wait;
END PROCESS;
END c04s03b02x00p01n01i00091arch_a;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent IS
END c04s03b02x00p01n01i00091ent;
ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
COMPONENT c04s03b02x00p01n01i00091ent_a
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END COMPONENT;
for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
SIGNAL STRING_prt : STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : ct_word;
SIGNAL cst_str10_prt : cst_str10;
SIGNAL cst_digit_prt : cst_digit;
SIGNAL rt_date_prt : rt_date;
SIGNAL rst_date_prt : rst_date;
BEGIN
C : c04s03b02x00p01n01i00091ent_a
PORT MAP ( STRING_prt,
BIT_VECTOR_prt,
ut_chary_prt,
ct_word_prt,
cst_str10_prt,
cst_digit_prt,
rt_date_prt,
rst_date_prt );
END c04s03b02x00p01n01i00091arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c04s03b02x00p01n01i00091pkg IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; --unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; --constrained array type
SUBTYPE ust_subchary IS ut_chary; --unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); --constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); --constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
END c04s03b02x00p01n01i00091pkg;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent_a IS
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END c04s03b02x00p01n01i00091ent_a;
ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
BEGIN
PROCESS
BEGIN
--
FOR I IN 1 TO 7
LOOP
ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 7
LOOP
ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN NUL TO ENQ
LOOP
ASSERT ut_chary_prt(I) = INTEGER'LEFT
REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 1 TO 10
LOOP
ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN '0' TO '9'
LOOP
ASSERT cst_digit_prt(I) = INTEGER'LEFT
REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE; END LOOP;
ASSERT rt_date_prt.day = 0 REPORT " rt_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.month = Jan REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.year = 0 REPORT " rt_date_prt.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.day = 0 REPORT "rst_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.month = Jan REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.year = 0 REPORT "rst_date_prt.year not properly intialized" SEVERITY FAILURE;
assert NOT( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***PASSED TEST: c04s03b02x00p01n01i00091"
severity NOTE;
assert ( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
severity ERROR;
wait;
END PROCESS;
END c04s03b02x00p01n01i00091arch_a;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent IS
END c04s03b02x00p01n01i00091ent;
ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
COMPONENT c04s03b02x00p01n01i00091ent_a
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END COMPONENT;
for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
SIGNAL STRING_prt : STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : ct_word;
SIGNAL cst_str10_prt : cst_str10;
SIGNAL cst_digit_prt : cst_digit;
SIGNAL rt_date_prt : rt_date;
SIGNAL rst_date_prt : rst_date;
BEGIN
C : c04s03b02x00p01n01i00091ent_a
PORT MAP ( STRING_prt,
BIT_VECTOR_prt,
ut_chary_prt,
ct_word_prt,
cst_str10_prt,
cst_digit_prt,
rt_date_prt,
rst_date_prt );
END c04s03b02x00p01n01i00091arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c04s03b02x00p01n01i00091pkg IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; --unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; --constrained array type
SUBTYPE ust_subchary IS ut_chary; --unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); --constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); --constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
END c04s03b02x00p01n01i00091pkg;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent_a IS
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END c04s03b02x00p01n01i00091ent_a;
ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
BEGIN
PROCESS
BEGIN
--
FOR I IN 1 TO 7
LOOP
ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 7
LOOP
ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN NUL TO ENQ
LOOP
ASSERT ut_chary_prt(I) = INTEGER'LEFT
REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 1 TO 10
LOOP
ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN '0' TO '9'
LOOP
ASSERT cst_digit_prt(I) = INTEGER'LEFT
REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE; END LOOP;
ASSERT rt_date_prt.day = 0 REPORT " rt_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.month = Jan REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.year = 0 REPORT " rt_date_prt.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.day = 0 REPORT "rst_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.month = Jan REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.year = 0 REPORT "rst_date_prt.year not properly intialized" SEVERITY FAILURE;
assert NOT( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***PASSED TEST: c04s03b02x00p01n01i00091"
severity NOTE;
assert ( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
severity ERROR;
wait;
END PROCESS;
END c04s03b02x00p01n01i00091arch_a;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent IS
END c04s03b02x00p01n01i00091ent;
ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
COMPONENT c04s03b02x00p01n01i00091ent_a
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END COMPONENT;
for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
SIGNAL STRING_prt : STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : ct_word;
SIGNAL cst_str10_prt : cst_str10;
SIGNAL cst_digit_prt : cst_digit;
SIGNAL rt_date_prt : rt_date;
SIGNAL rst_date_prt : rst_date;
BEGIN
C : c04s03b02x00p01n01i00091ent_a
PORT MAP ( STRING_prt,
BIT_VECTOR_prt,
ut_chary_prt,
ct_word_prt,
cst_str10_prt,
cst_digit_prt,
rt_date_prt,
rst_date_prt );
END c04s03b02x00p01n01i00091arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
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-- of Xilinx, Inc. and is protected under U.S. and
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-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ffd_serie is
generic (
N : natural := 1
);
port (
clock : in std_logic;
reset : in std_logic;
enable: in std_logic;
D : in std_logic;
Q : out std_logic
);
end;
architecture ffd_serie_arq of ffd_serie is
signal aux : std_logic_vector(N downto 0);
begin
aux(0) <= D;
delay_i: for i in 1 to N generate
ffd_delay: entity work.ffd
port map(
clk => clock,
rst => reset,
ena => enable,
d => aux(i-1),
q => aux(i)
);
end generate;
Q <= aux(N);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_cpu_2_crossbar_wrap_pack.all;
entity plasoc_cpu_2_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_cpu_2_crossbar_wrap;
architecture Behavioral of plasoc_cpu_2_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_awready & signal_m_axi_awready & int_m_axi_awready & cpuid_gpio_m_axi_awready & ip_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_wready & signal_m_axi_wready & int_m_axi_wready & cpuid_gpio_m_axi_wready & ip_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bid & signal_m_axi_bid & int_m_axi_bid & cpuid_gpio_m_axi_bid & ip_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bresp & signal_m_axi_bresp & int_m_axi_bresp & cpuid_gpio_m_axi_bresp & ip_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bvalid & signal_m_axi_bvalid & int_m_axi_bvalid & cpuid_gpio_m_axi_bvalid & ip_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_arready & signal_m_axi_arready & int_m_axi_arready & cpuid_gpio_m_axi_arready & ip_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rid & signal_m_axi_rid & int_m_axi_rid & cpuid_gpio_m_axi_rid & ip_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rdata & signal_m_axi_rdata & int_m_axi_rdata & cpuid_gpio_m_axi_rdata & ip_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rresp & signal_m_axi_rresp & int_m_axi_rresp & cpuid_gpio_m_axi_rresp & ip_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rlast & signal_m_axi_rlast & int_m_axi_rlast & cpuid_gpio_m_axi_rlast & ip_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rvalid & signal_m_axi_rvalid & int_m_axi_rvalid & cpuid_gpio_m_axi_rvalid & ip_m_axi_rvalid;
cpu_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cpu_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cpu_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cpu_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cpu_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cpu_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpu_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cpu_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cpu_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
ip_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
signal_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
ip_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
signal_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
ip_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
signal_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
ip_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
cpuid_gpio_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
signal_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
timer_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
ip_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
signal_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
ip_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
signal_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
ip_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
signal_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
ip_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
signal_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
ip_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
cpuid_gpio_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
signal_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
timer_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
ip_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpuid_gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
signal_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
ip_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
cpuid_gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
signal_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
ip_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
cpuid_gpio_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
signal_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
timer_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
ip_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
cpuid_gpio_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
signal_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
timer_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
ip_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
cpuid_gpio_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
signal_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
timer_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
ip_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
signal_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
ip_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
signal_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
ip_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
signal_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
ip_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
cpuid_gpio_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
signal_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
timer_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
ip_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
signal_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
ip_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
signal_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
ip_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
signal_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
ip_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
signal_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
ip_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
cpuid_gpio_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
signal_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
timer_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
ip_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
cpuid_gpio_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
signal_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
timer_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w32_d3_A_shiftReg;
architecture rtl of fifo_w32_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w32_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w32_d3_A is
component fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity logDim is
port(
pwmIn : in std_logic_vector(5 downto 0);
logPwm : out std_logic_vector(7 downto 0)
);
end entity logDim;
architecture RTL of logDim is
type rom_array is array (natural range 0 to 63) of std_logic_vector(7 downto 0);
-- constant array definition to cover the logarithmic caracteristic
constant rom_data : rom_array := (
conv_std_logic_vector(0, 8),
conv_std_logic_vector(1, 8),
conv_std_logic_vector(2, 8),
conv_std_logic_vector(3, 8),
conv_std_logic_vector(4, 8),
conv_std_logic_vector(5, 8),
conv_std_logic_vector(6, 8),
conv_std_logic_vector(7, 8),
conv_std_logic_vector(8, 8),
conv_std_logic_vector(9, 8),
conv_std_logic_vector(10, 8),
conv_std_logic_vector(11, 8),
conv_std_logic_vector(12, 8),
conv_std_logic_vector(13, 8),
conv_std_logic_vector(14, 8),
conv_std_logic_vector(16, 8),
conv_std_logic_vector(18, 8),
conv_std_logic_vector(20, 8),
conv_std_logic_vector(22, 8),
conv_std_logic_vector(25, 8),
conv_std_logic_vector(28, 8),
conv_std_logic_vector(30, 8),
conv_std_logic_vector(33, 8),
conv_std_logic_vector(36, 8),
conv_std_logic_vector(39, 8),
conv_std_logic_vector(42, 8),
conv_std_logic_vector(46, 8),
conv_std_logic_vector(49, 8),
conv_std_logic_vector(53, 8),
conv_std_logic_vector(56, 8),
conv_std_logic_vector(60, 8),
conv_std_logic_vector(64, 8),
conv_std_logic_vector(68, 8),
conv_std_logic_vector(72, 8),
conv_std_logic_vector(77, 8),
conv_std_logic_vector(81, 8),
conv_std_logic_vector(86, 8),
conv_std_logic_vector(90, 8),
conv_std_logic_vector(95, 8),
conv_std_logic_vector(100, 8),
conv_std_logic_vector(105, 8),
conv_std_logic_vector(110, 8),
conv_std_logic_vector(116, 8),
conv_std_logic_vector(121, 8),
conv_std_logic_vector(127, 8),
conv_std_logic_vector(132, 8),
conv_std_logic_vector(138, 8),
conv_std_logic_vector(144, 8),
conv_std_logic_vector(150, 8),
conv_std_logic_vector(156, 8),
conv_std_logic_vector(163, 8),
conv_std_logic_vector(169, 8),
conv_std_logic_vector(176, 8),
conv_std_logic_vector(182, 8),
conv_std_logic_vector(189, 8),
conv_std_logic_vector(196, 8),
conv_std_logic_vector(203, 8),
conv_std_logic_vector(210, 8),
conv_std_logic_vector(218, 8),
conv_std_logic_vector(225, 8),
conv_std_logic_vector(233, 8),
conv_std_logic_vector(240, 8),
conv_std_logic_vector(246, 8),
conv_std_logic_vector(255, 8)
);
begin
-- write output
logPwm <= rom_data(conv_integer(unsigned(pwmIn)));
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2431.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02431ent IS
END c07s03b02x02p01n01i02431ent;
ARCHITECTURE c07s03b02x02p01n01i02431arch OF c07s03b02x02p01n01i02431ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable x : array_three := (1=>2,2=>3,3=>4,4=>6.32,5=>6,6=>7); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02431 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2431.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02431ent IS
END c07s03b02x02p01n01i02431ent;
ARCHITECTURE c07s03b02x02p01n01i02431arch OF c07s03b02x02p01n01i02431ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable x : array_three := (1=>2,2=>3,3=>4,4=>6.32,5=>6,6=>7); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02431 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2431.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02431ent IS
END c07s03b02x02p01n01i02431ent;
ARCHITECTURE c07s03b02x02p01n01i02431arch OF c07s03b02x02p01n01i02431ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable x : array_three := (1=>2,2=>3,3=>4,4=>6.32,5=>6,6=>7); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02431 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02431arch;
|
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: kn_kalman_add.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altfp_add_sub 2012:01:25:21:13:53:SJ cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_h0e;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 29
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_n3g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_n3g;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_n3g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range823w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range847w860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w878w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range865w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range830w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) AND wire_rbarrel_shift_w859w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) AND wire_rbarrel_shift_w878w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) AND wire_rbarrel_shift_w_sbit_w_range865w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0) <= NOT wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range826w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) <= NOT wire_rbarrel_shift_w_sel_w_range849w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) <= NOT wire_rbarrel_shift_w_sel_w_range868w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w864w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 3) & dir_pipe(0) & dir_w(1 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 78) & sbit_piper1d & smux_w(51 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r1d & sel_pipec3r1d & distance(2 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w883w & wire_rbarrel_shift_w864w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w856w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w859w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w878w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range823w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range847w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range865w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range826w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range849w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range868w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range830w <= smux_w(77 DOWNTO 52);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(2));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range830w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_n3g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_3e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --kn_kalman_add_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_6e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero919w920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero921w922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero919w & wire_altpriority_encoder14_w_lg_w_lg_zero921w922w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0) <= wire_altpriority_encoder14_w_lg_zero919w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero921w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero919w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero921w922w(0) <= wire_altpriority_encoder14_w_lg_zero921w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0);
altpriority_encoder14 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_be8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero909w910w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero911w912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero909w & wire_altpriority_encoder12_w_lg_w_lg_zero911w912w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i) <= wire_altpriority_encoder12_w_lg_zero909w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero911w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero909w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero911w912w(i) <= wire_altpriority_encoder12_w_lg_zero911w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i);
END GENERATE loop52;
altpriority_encoder12 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_3v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --kn_kalman_add_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_6v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero944w945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero946w947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero944w & wire_altpriority_encoder18_w_lg_w_lg_zero946w947w);
altpriority_encoder17 : kn_kalman_add_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0) <= wire_altpriority_encoder18_w_lg_zero944w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero946w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero944w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero946w947w(0) <= wire_altpriority_encoder18_w_lg_zero946w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0);
altpriority_encoder18 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_bv7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero935w936w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero937w938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero935w & wire_altpriority_encoder16_w_lg_w_lg_zero937w938w);
altpriority_encoder15 : kn_kalman_add_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i) <= wire_altpriority_encoder16_w_lg_zero935w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero937w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero935w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero937w938w(i) <= wire_altpriority_encoder16_w_lg_zero937w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i);
END GENERATE loop55;
altpriority_encoder16 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_uv8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero900w901w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero902w903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero900w & wire_altpriority_encoder10_w_lg_w_lg_zero902w903w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i) <= wire_altpriority_encoder10_w_lg_zero900w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero902w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero900w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero902w903w(i) <= wire_altpriority_encoder10_w_lg_zero902w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i);
END GENERATE loop58;
altpriority_encoder10 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : kn_kalman_add_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --kn_kalman_add_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ue9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero956w957w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero958w959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero956w & wire_altpriority_encoder20_w_lg_w_lg_zero958w959w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i) <= wire_altpriority_encoder20_w_lg_zero956w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero958w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero956w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero958w959w(i) <= wire_altpriority_encoder20_w_lg_zero958w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i);
END GENERATE loop61;
altpriority_encoder20 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_ou8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero890w891w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero890w & wire_altpriority_encoder8_w_lg_w_lg_zero892w893w);
altpriority_encoder7 : kn_kalman_add_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i) <= wire_altpriority_encoder8_w_lg_zero890w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero892w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero890w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i);
END GENERATE loop64;
altpriority_encoder8 : kn_kalman_add_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_nh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1006w1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1006w1008w(0) <= NOT wire_altpriority_encoder27_w_data_range1006w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1006w1008w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1006w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_qh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0);
altpriority_encoder27 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_vh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero990w991w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero990w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero988w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i);
END GENERATE loop67;
altpriority_encoder25 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ii9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ii9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ii9 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero980w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero980w981w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero980w981w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero980w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero978w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero980w981w(i) <= wire_altpriority_encoder23_w_lg_zero980w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i);
END GENERATE loop70;
altpriority_encoder23 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ii9
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_n28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1040w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1040w1042w(0) <= NOT wire_altpriority_encoder34_w_data_range1040w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1040w1042w);
wire_altpriority_encoder34_w_data_range1040w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_q28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w);
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1035w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w(0) <= wire_altpriority_encoder33_w_lg_zero1035w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0);
altpriority_encoder33 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : kn_kalman_add_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --kn_kalman_add_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_v28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1026w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1026w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1024w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w(i) <= wire_altpriority_encoder31_w_lg_zero1026w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i);
END GENERATE loop73;
altpriority_encoder31 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : kn_kalman_add_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --kn_kalman_add_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_i39 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_i39;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_i39 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1017w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1015w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i);
END GENERATE loop76;
altpriority_encoder29 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : kn_kalman_add_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --kn_kalman_add_altpriority_encoder_i39
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_cna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_cna;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_cna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero966w967w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero968w969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_ii9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_i39
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop77 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w(i) <= NOT tmp_q_wire(i);
END GENERATE loop77;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero968w969w);
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i) <= wire_altpriority_encoder21_w_lg_zero966w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop78;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero968w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop79;
wire_altpriority_encoder21_w_lg_zero966w(0) <= NOT wire_altpriority_encoder21_zero;
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero968w969w(i) <= wire_altpriority_encoder21_w_lg_zero968w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i);
END GENERATE loop80;
altpriority_encoder21 : kn_kalman_add_altpriority_encoder_ii9
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : kn_kalman_add_altpriority_encoder_i39
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_cna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 716
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altfp_add_sub_12j IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add_altfp_add_sub_12j;
ARCHITECTURE RTL OF kn_kalman_add_altfp_add_sub_12j IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL add_sub_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe25 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altbarrel_shift_n3g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_cna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop81 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop90;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop94;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop97 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop97;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop98 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop112;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop113 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop113;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop114 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop117;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop118 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop121;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25;
clk_en <= '1';
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : kn_kalman_add_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : kn_kalman_add_altbarrel_shift_n3g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : kn_kalman_add_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : kn_kalman_add_altpriority_encoder_cna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN add_sub_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN add_sub_dffe25 <= add_sub_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe25 <= both_inputs_are_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe25 <= dataa_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe25 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe25 <= exp_res_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe25 <= infinite_output_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe25 <= input_is_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe25 <= input_is_nan_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe25 <= sticky_bit_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop123;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop124;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop125;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop126;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop127;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop128;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop129;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop130;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --kn_kalman_add_altfp_add_sub_12j
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add;
ARCHITECTURE RTL OF kn_kalman_add IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_add_altfp_add_sub_12j
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_add_altfp_add_sub_12j_component : kn_kalman_add_altfp_add_sub_12j
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add_inst.vhd TRUE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: kn_kalman_add.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altfp_add_sub 2012:01:25:21:13:53:SJ cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_h0e;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 29
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_n3g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_n3g;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_n3g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range823w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range847w860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w878w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range865w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range830w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) AND wire_rbarrel_shift_w859w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) AND wire_rbarrel_shift_w878w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) AND wire_rbarrel_shift_w_sbit_w_range865w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0) <= NOT wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range826w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) <= NOT wire_rbarrel_shift_w_sel_w_range849w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) <= NOT wire_rbarrel_shift_w_sel_w_range868w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w864w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 3) & dir_pipe(0) & dir_w(1 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 78) & sbit_piper1d & smux_w(51 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r1d & sel_pipec3r1d & distance(2 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w883w & wire_rbarrel_shift_w864w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w856w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w859w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w878w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range823w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range847w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range865w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range826w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range849w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range868w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range830w <= smux_w(77 DOWNTO 52);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(2));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range830w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_n3g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_3e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --kn_kalman_add_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_6e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero919w920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero921w922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero919w & wire_altpriority_encoder14_w_lg_w_lg_zero921w922w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0) <= wire_altpriority_encoder14_w_lg_zero919w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero921w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero919w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero921w922w(0) <= wire_altpriority_encoder14_w_lg_zero921w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0);
altpriority_encoder14 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_be8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero909w910w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero911w912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero909w & wire_altpriority_encoder12_w_lg_w_lg_zero911w912w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i) <= wire_altpriority_encoder12_w_lg_zero909w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero911w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero909w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero911w912w(i) <= wire_altpriority_encoder12_w_lg_zero911w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i);
END GENERATE loop52;
altpriority_encoder12 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_3v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --kn_kalman_add_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_6v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero944w945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero946w947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero944w & wire_altpriority_encoder18_w_lg_w_lg_zero946w947w);
altpriority_encoder17 : kn_kalman_add_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0) <= wire_altpriority_encoder18_w_lg_zero944w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero946w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero944w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero946w947w(0) <= wire_altpriority_encoder18_w_lg_zero946w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0);
altpriority_encoder18 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_bv7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero935w936w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero937w938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero935w & wire_altpriority_encoder16_w_lg_w_lg_zero937w938w);
altpriority_encoder15 : kn_kalman_add_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i) <= wire_altpriority_encoder16_w_lg_zero935w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero937w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero935w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero937w938w(i) <= wire_altpriority_encoder16_w_lg_zero937w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i);
END GENERATE loop55;
altpriority_encoder16 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_uv8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero900w901w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero902w903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero900w & wire_altpriority_encoder10_w_lg_w_lg_zero902w903w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i) <= wire_altpriority_encoder10_w_lg_zero900w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero902w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero900w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero902w903w(i) <= wire_altpriority_encoder10_w_lg_zero902w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i);
END GENERATE loop58;
altpriority_encoder10 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : kn_kalman_add_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --kn_kalman_add_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ue9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero956w957w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero958w959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero956w & wire_altpriority_encoder20_w_lg_w_lg_zero958w959w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i) <= wire_altpriority_encoder20_w_lg_zero956w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero958w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero956w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero958w959w(i) <= wire_altpriority_encoder20_w_lg_zero958w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i);
END GENERATE loop61;
altpriority_encoder20 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_ou8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero890w891w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero890w & wire_altpriority_encoder8_w_lg_w_lg_zero892w893w);
altpriority_encoder7 : kn_kalman_add_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i) <= wire_altpriority_encoder8_w_lg_zero890w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero892w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero890w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i);
END GENERATE loop64;
altpriority_encoder8 : kn_kalman_add_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_nh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1006w1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1006w1008w(0) <= NOT wire_altpriority_encoder27_w_data_range1006w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1006w1008w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1006w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_qh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0);
altpriority_encoder27 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_vh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero990w991w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero990w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero988w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i);
END GENERATE loop67;
altpriority_encoder25 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ii9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ii9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ii9 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero980w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero980w981w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero980w981w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero980w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero978w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero980w981w(i) <= wire_altpriority_encoder23_w_lg_zero980w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i);
END GENERATE loop70;
altpriority_encoder23 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ii9
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_n28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1040w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1040w1042w(0) <= NOT wire_altpriority_encoder34_w_data_range1040w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1040w1042w);
wire_altpriority_encoder34_w_data_range1040w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_q28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w);
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1035w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w(0) <= wire_altpriority_encoder33_w_lg_zero1035w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0);
altpriority_encoder33 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : kn_kalman_add_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --kn_kalman_add_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_v28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1026w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1026w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1024w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w(i) <= wire_altpriority_encoder31_w_lg_zero1026w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i);
END GENERATE loop73;
altpriority_encoder31 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : kn_kalman_add_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --kn_kalman_add_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_i39 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_i39;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_i39 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1017w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1015w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i);
END GENERATE loop76;
altpriority_encoder29 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : kn_kalman_add_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --kn_kalman_add_altpriority_encoder_i39
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_cna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_cna;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_cna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero966w967w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero968w969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_ii9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_i39
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop77 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w(i) <= NOT tmp_q_wire(i);
END GENERATE loop77;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero968w969w);
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i) <= wire_altpriority_encoder21_w_lg_zero966w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop78;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero968w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop79;
wire_altpriority_encoder21_w_lg_zero966w(0) <= NOT wire_altpriority_encoder21_zero;
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero968w969w(i) <= wire_altpriority_encoder21_w_lg_zero968w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i);
END GENERATE loop80;
altpriority_encoder21 : kn_kalman_add_altpriority_encoder_ii9
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : kn_kalman_add_altpriority_encoder_i39
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_cna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 716
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altfp_add_sub_12j IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add_altfp_add_sub_12j;
ARCHITECTURE RTL OF kn_kalman_add_altfp_add_sub_12j IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL add_sub_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe25 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altbarrel_shift_n3g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_cna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop81 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop90;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop94;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop97 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop97;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop98 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop112;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop113 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop113;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop114 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop117;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop118 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop121;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25;
clk_en <= '1';
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : kn_kalman_add_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : kn_kalman_add_altbarrel_shift_n3g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : kn_kalman_add_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : kn_kalman_add_altpriority_encoder_cna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN add_sub_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN add_sub_dffe25 <= add_sub_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe25 <= both_inputs_are_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe25 <= dataa_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe25 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe25 <= exp_res_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe25 <= infinite_output_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe25 <= input_is_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe25 <= input_is_nan_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe25 <= sticky_bit_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop123;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop124;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop125;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop126;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop127;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop128;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop129;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop130;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --kn_kalman_add_altfp_add_sub_12j
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add;
ARCHITECTURE RTL OF kn_kalman_add IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_add_altfp_add_sub_12j
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_add_altfp_add_sub_12j_component : kn_kalman_add_altfp_add_sub_12j
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add_inst.vhd TRUE
-- Retrieval info: LIB_FILE: lpm
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_6;
USE blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_6 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_6,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_6,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_m" &
"em_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4000,C_READ_DEPTH_A=4000,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C" &
"_WRITE_DEPTH_B=500,C_READ_DEPTH_B=500,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_D" &
"ISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.4085 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_6
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4000,
C_READ_DEPTH_A => 4000,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 500,
C_READ_DEPTH_B => 500,
C_ADDRB_WIDTH => 9,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.4085 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
|
library verilog;
use verilog.vl_types.all;
entity butterfly_radix4_2nd is
generic(
cos0 : integer := 32767;
cos1 : integer := 32767;
cos2 : integer := 32767;
cos3 : integer := 30273;
cos4 : integer := 23170;
cos5 : integer := 12540;
cos6 : integer := 23170;
cos7 : integer := 0;
cos8 : integer := 42366;
cos9 : integer := 12540;
cos10 : integer := 42366;
cos11 : integer := 35263;
sin0 : integer := 0;
sin1 : integer := 0;
sin2 : integer := 0;
sin3 : integer := 52996;
sin4 : integer := 42366;
sin5 : integer := 35263;
sin6 : integer := 42366;
sin7 : integer := 32769;
sin8 : integer := 42366;
sin9 : integer := 35263;
sin10 : integer := 42366;
sin11 : integer := 12540
);
port(
clk : in vl_logic;
re_0 : in vl_logic_vector(15 downto 0);
re_1 : in vl_logic_vector(15 downto 0);
re_2 : in vl_logic_vector(15 downto 0);
re_3 : in vl_logic_vector(15 downto 0);
re_4 : in vl_logic_vector(15 downto 0);
re_5 : in vl_logic_vector(15 downto 0);
re_6 : in vl_logic_vector(15 downto 0);
re_7 : in vl_logic_vector(15 downto 0);
re_8 : in vl_logic_vector(15 downto 0);
re_9 : in vl_logic_vector(15 downto 0);
re_10 : in vl_logic_vector(15 downto 0);
re_11 : in vl_logic_vector(15 downto 0);
re_12 : in vl_logic_vector(15 downto 0);
re_13 : in vl_logic_vector(15 downto 0);
re_14 : in vl_logic_vector(15 downto 0);
re_15 : in vl_logic_vector(15 downto 0);
im_0 : in vl_logic_vector(15 downto 0);
im_1 : in vl_logic_vector(15 downto 0);
im_2 : in vl_logic_vector(15 downto 0);
im_3 : in vl_logic_vector(15 downto 0);
im_4 : in vl_logic_vector(15 downto 0);
im_5 : in vl_logic_vector(15 downto 0);
im_6 : in vl_logic_vector(15 downto 0);
im_7 : in vl_logic_vector(15 downto 0);
im_8 : in vl_logic_vector(15 downto 0);
im_9 : in vl_logic_vector(15 downto 0);
im_10 : in vl_logic_vector(15 downto 0);
im_11 : in vl_logic_vector(15 downto 0);
im_12 : in vl_logic_vector(15 downto 0);
im_13 : in vl_logic_vector(15 downto 0);
im_14 : in vl_logic_vector(15 downto 0);
im_15 : in vl_logic_vector(15 downto 0);
butterfly_re0 : out vl_logic_vector(15 downto 0);
butterfly_re1 : out vl_logic_vector(15 downto 0);
butterfly_re2 : out vl_logic_vector(15 downto 0);
butterfly_re3 : out vl_logic_vector(15 downto 0);
butterfly_re4 : out vl_logic_vector(15 downto 0);
butterfly_re5 : out vl_logic_vector(15 downto 0);
butterfly_re6 : out vl_logic_vector(15 downto 0);
butterfly_re7 : out vl_logic_vector(15 downto 0);
butterfly_re8 : out vl_logic_vector(15 downto 0);
butterfly_re9 : out vl_logic_vector(15 downto 0);
butterfly_re10 : out vl_logic_vector(15 downto 0);
butterfly_re11 : out vl_logic_vector(15 downto 0);
butterfly_re12 : out vl_logic_vector(15 downto 0);
butterfly_re13 : out vl_logic_vector(15 downto 0);
butterfly_re14 : out vl_logic_vector(15 downto 0);
butterfly_re15 : out vl_logic_vector(15 downto 0);
butterfly_im0 : out vl_logic_vector(15 downto 0);
butterfly_im1 : out vl_logic_vector(15 downto 0);
butterfly_im2 : out vl_logic_vector(15 downto 0);
butterfly_im3 : out vl_logic_vector(15 downto 0);
butterfly_im4 : out vl_logic_vector(15 downto 0);
butterfly_im5 : out vl_logic_vector(15 downto 0);
butterfly_im6 : out vl_logic_vector(15 downto 0);
butterfly_im7 : out vl_logic_vector(15 downto 0);
butterfly_im8 : out vl_logic_vector(15 downto 0);
butterfly_im9 : out vl_logic_vector(15 downto 0);
butterfly_im10 : out vl_logic_vector(15 downto 0);
butterfly_im11 : out vl_logic_vector(15 downto 0);
butterfly_im12 : out vl_logic_vector(15 downto 0);
butterfly_im13 : out vl_logic_vector(15 downto 0);
butterfly_im14 : out vl_logic_vector(15 downto 0);
butterfly_im15 : out vl_logic_vector(15 downto 0)
);
end butterfly_radix4_2nd;
|
library verilog;
use verilog.vl_types.all;
entity butterfly_radix4_2nd is
generic(
cos0 : integer := 32767;
cos1 : integer := 32767;
cos2 : integer := 32767;
cos3 : integer := 30273;
cos4 : integer := 23170;
cos5 : integer := 12540;
cos6 : integer := 23170;
cos7 : integer := 0;
cos8 : integer := 42366;
cos9 : integer := 12540;
cos10 : integer := 42366;
cos11 : integer := 35263;
sin0 : integer := 0;
sin1 : integer := 0;
sin2 : integer := 0;
sin3 : integer := 52996;
sin4 : integer := 42366;
sin5 : integer := 35263;
sin6 : integer := 42366;
sin7 : integer := 32769;
sin8 : integer := 42366;
sin9 : integer := 35263;
sin10 : integer := 42366;
sin11 : integer := 12540
);
port(
clk : in vl_logic;
re_0 : in vl_logic_vector(15 downto 0);
re_1 : in vl_logic_vector(15 downto 0);
re_2 : in vl_logic_vector(15 downto 0);
re_3 : in vl_logic_vector(15 downto 0);
re_4 : in vl_logic_vector(15 downto 0);
re_5 : in vl_logic_vector(15 downto 0);
re_6 : in vl_logic_vector(15 downto 0);
re_7 : in vl_logic_vector(15 downto 0);
re_8 : in vl_logic_vector(15 downto 0);
re_9 : in vl_logic_vector(15 downto 0);
re_10 : in vl_logic_vector(15 downto 0);
re_11 : in vl_logic_vector(15 downto 0);
re_12 : in vl_logic_vector(15 downto 0);
re_13 : in vl_logic_vector(15 downto 0);
re_14 : in vl_logic_vector(15 downto 0);
re_15 : in vl_logic_vector(15 downto 0);
im_0 : in vl_logic_vector(15 downto 0);
im_1 : in vl_logic_vector(15 downto 0);
im_2 : in vl_logic_vector(15 downto 0);
im_3 : in vl_logic_vector(15 downto 0);
im_4 : in vl_logic_vector(15 downto 0);
im_5 : in vl_logic_vector(15 downto 0);
im_6 : in vl_logic_vector(15 downto 0);
im_7 : in vl_logic_vector(15 downto 0);
im_8 : in vl_logic_vector(15 downto 0);
im_9 : in vl_logic_vector(15 downto 0);
im_10 : in vl_logic_vector(15 downto 0);
im_11 : in vl_logic_vector(15 downto 0);
im_12 : in vl_logic_vector(15 downto 0);
im_13 : in vl_logic_vector(15 downto 0);
im_14 : in vl_logic_vector(15 downto 0);
im_15 : in vl_logic_vector(15 downto 0);
butterfly_re0 : out vl_logic_vector(15 downto 0);
butterfly_re1 : out vl_logic_vector(15 downto 0);
butterfly_re2 : out vl_logic_vector(15 downto 0);
butterfly_re3 : out vl_logic_vector(15 downto 0);
butterfly_re4 : out vl_logic_vector(15 downto 0);
butterfly_re5 : out vl_logic_vector(15 downto 0);
butterfly_re6 : out vl_logic_vector(15 downto 0);
butterfly_re7 : out vl_logic_vector(15 downto 0);
butterfly_re8 : out vl_logic_vector(15 downto 0);
butterfly_re9 : out vl_logic_vector(15 downto 0);
butterfly_re10 : out vl_logic_vector(15 downto 0);
butterfly_re11 : out vl_logic_vector(15 downto 0);
butterfly_re12 : out vl_logic_vector(15 downto 0);
butterfly_re13 : out vl_logic_vector(15 downto 0);
butterfly_re14 : out vl_logic_vector(15 downto 0);
butterfly_re15 : out vl_logic_vector(15 downto 0);
butterfly_im0 : out vl_logic_vector(15 downto 0);
butterfly_im1 : out vl_logic_vector(15 downto 0);
butterfly_im2 : out vl_logic_vector(15 downto 0);
butterfly_im3 : out vl_logic_vector(15 downto 0);
butterfly_im4 : out vl_logic_vector(15 downto 0);
butterfly_im5 : out vl_logic_vector(15 downto 0);
butterfly_im6 : out vl_logic_vector(15 downto 0);
butterfly_im7 : out vl_logic_vector(15 downto 0);
butterfly_im8 : out vl_logic_vector(15 downto 0);
butterfly_im9 : out vl_logic_vector(15 downto 0);
butterfly_im10 : out vl_logic_vector(15 downto 0);
butterfly_im11 : out vl_logic_vector(15 downto 0);
butterfly_im12 : out vl_logic_vector(15 downto 0);
butterfly_im13 : out vl_logic_vector(15 downto 0);
butterfly_im14 : out vl_logic_vector(15 downto 0);
butterfly_im15 : out vl_logic_vector(15 downto 0)
);
end butterfly_radix4_2nd;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rstgen is
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, arst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if syncrst = 0 generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if syncrst = 1 generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklock) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rstgen is
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, arst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if syncrst = 0 generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if syncrst = 1 generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklock) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: vram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 7168
-- C_READ_DEPTH_A : 7168
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 7168
-- C_READ_DEPTH_B : 7168
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY vram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END vram_prod;
ARCHITECTURE xilinx OF vram_prod IS
COMPONENT vram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : vram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1 is
port( dataln : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dataOut : out STD_LOGIC);
end Mux2_1;
Architecture BehavProcess of Mux2_1 is
begin
process(sel,dataln)
begin
if(sel="00") then
dataOut <= dataln(0);
elsif(sel="01") then
dataOut <= dataln(1);
elsif(sel="10") then
dataOut <= dataln(2);
else
dataOut <= dataln(3);
end if;
end process;
end BehavProcess;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1 is
port( dataln : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dataOut : out STD_LOGIC);
end Mux2_1;
Architecture BehavProcess of Mux2_1 is
begin
process(sel,dataln)
begin
if(sel="00") then
dataOut <= dataln(0);
elsif(sel="01") then
dataOut <= dataln(1);
elsif(sel="10") then
dataOut <= dataln(2);
else
dataOut <= dataln(3);
end if;
end process;
end BehavProcess;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_sw_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_axi_gpio_sw_0;
ARCHITECTURE system_axi_gpio_sw_0_arch OF system_axi_gpio_sw_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_sw_0_arch : ARCHITECTURE IS "system_axi_gpio_sw_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "system_axi_gpio_sw_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=4,C_ALL_INPUTS=1,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END system_axi_gpio_sw_0_arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_e85aeee534196d83.vhd when simulating
-- the core, cc_cmplr_v3_0_e85aeee534196d83. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_e85aeee534196d83 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_e85aeee534196d83;
ARCHITECTURE cc_cmplr_v3_0_e85aeee534196d83_a OF cc_cmplr_v3_0_e85aeee534196d83 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_e85aeee534196d83
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_e85aeee534196d83 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 61,
c_c2 => 61,
c_c3 => 61,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2240,
c_component_name => "cc_cmplr_v3_0_e85aeee534196d83",
c_diff_delay => 2,
c_family => "virtex6",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 61,
c_i2 => 61,
c_i3 => 61,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 2500,
c_min_rate => 2500,
c_num_channels => 4,
c_num_stages => 3,
c_output_width => 61,
c_rate => 2500,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_e85aeee534196d83
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_e85aeee534196d83_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CartTable is
port(clk: in std_logic;
d: out std_logic_vector(10 downto 0);
c: out std_logic_vector(6 downto 0);
a: in std_logic_vector(6 downto 0));
end CartTable;
architecture arch of CartTable is
type rom_type is array (0 to 127) of std_logic_vector(10 downto 0);
signal rom: rom_type := (
"00000000000",
"00000010000",
"00000100010",
"00001000010",
"00001100010",
"00010000100",
"00011000101",
"00100000011",
"00100100010",
"00101000101",
"00110000000",
"00110010000",
"00110100000",
"00110110000",
"00111000010",
"00111100010",
"01000001000",
"01000101000",
"01001000000",
"01001010000",
"01001100000",
"01001110000",
"01010000101",
"01011000010",
"01011100010",
"01100000010",
"01100100010",
"01101000100",
"01110000000",
"01110010000",
"01110100000",
"01110110000",
"01111000100",
"10000000010",
"10000100010",
"10001000000",
"10001010000",
"10001100010",
"10010000100",
"10011000010",
"10011100010",
"10100000100",
"10101000010",
"10101100010",
"10110000100",
"10111001010",
"10111101010",
"11000001010",
"11000100000",
"11000110000",
"11001000010",
"11001100010",
"11010000010",
"11010100010",
"11011000000",
"11011010000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000",
"00000000000");
signal ra: std_logic_vector(6 downto 0);
begin
process(clk)
begin
if (clk = '1' and clk'event) then
ra <= a;
end if;
end process;
d <= rom(to_integer(unsigned(ra)));
c <= "0110111";
end arch;
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p05n01i02676ent IS
END c13s03b01x00p05n01i02676ent;
ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
constant a234567_10_234567_20_234567a : integer := 2;
constant a234567_10_234567_20_234567b : integer := 7;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***PASSED TEST: c13s03b01x00p05n01i02676"
severity NOTE;
assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p05n01i02676arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p05n01i02676ent IS
END c13s03b01x00p05n01i02676ent;
ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
constant a234567_10_234567_20_234567a : integer := 2;
constant a234567_10_234567_20_234567b : integer := 7;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***PASSED TEST: c13s03b01x00p05n01i02676"
severity NOTE;
assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p05n01i02676arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p05n01i02676ent IS
END c13s03b01x00p05n01i02676ent;
ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
constant a234567_10_234567_20_234567a : integer := 2;
constant a234567_10_234567_20_234567b : integer := 7;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***PASSED TEST: c13s03b01x00p05n01i02676"
severity NOTE;
assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p05n01i02676arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_38 : BOOLEAN;
signal img_0_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_38)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0 <= img_0_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1 <= img_0_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2 <= img_0_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3 <= img_0_cols_V_fu_35_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_38 assign process. --
ap_sig_bdd_38_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_38 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
img_0_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
img_0_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_38 : BOOLEAN;
signal img_0_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_38)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0 <= img_0_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1 <= img_0_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2 <= img_0_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3 <= img_0_cols_V_fu_35_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_38 assign process. --
ap_sig_bdd_38_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_38 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
img_0_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
img_0_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_38 : BOOLEAN;
signal img_0_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_38)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0 <= img_0_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1 <= img_0_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2 <= img_0_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3 <= img_0_cols_V_fu_35_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_38 assign process. --
ap_sig_bdd_38_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_38 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
img_0_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
img_0_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_38 : BOOLEAN;
signal img_0_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2_preg <= img_0_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_38)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_0 <= img_0_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_1 <= img_0_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_2 <= img_0_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_38, img_0_cols_V_fu_35_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_38))) then
ap_return_3 <= img_0_cols_V_fu_35_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_38 assign process. --
ap_sig_bdd_38_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_38 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
img_0_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
img_0_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_115 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_115;
architecture augh of cmp_115 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_115 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_115;
architecture augh of cmp_115 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 300, --631
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
|
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capability of a simulator.
--
--
-- Revision History: For more details, see CoveragePkg_release_notes.pdf
-- Date Version Description
-- 11/2016: 2016.11 Initial revision
-- 12/2016 2016.11a Fixed an issue with attributes
--
--
-- Copyright (c) 2016 by Aldec. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- Modified copies of this source file may be distributed
-- under the terms of the ARTISTIC License as published by
-- The Perl Foundation; either version 2.0 of the License,
-- or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
-- --
--------------------------------------------------------------------------
package VendorCovApiPkg is
subtype VendorCovHandleType is integer;
-- Types for how coverage bins are represented. Matches OSVVM types.
type VendorCovRangeType is record
min: integer;
max: integer;
end record;
type VendorCovRangeArrayType is array ( integer range <> ) of VendorCovRangeType;
-- Create Initial Data Structure for Point/Item Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovPointCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovPointCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CvpCreate";
-- Create Initial Data Structure for Cross Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovCrossCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovCrossCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CrCreate";
-- Sets/Updates the name of the Coverage Model.
-- Should not be called until the data structure is created by VendorCovPointCreate or VendorCovCrossCreate.
-- Replaces name that was set by VendorCovPointCreate or VendorCovCrossCreate.
procedure VendorCovSetName( obj: VendorCovHandleType; name: string );
attribute foreign of VendorCovSetName[ VendorCovHandleType, string ]: procedure is "VHPI systf; cvg_SetCoverName";
-- Add a bin or set of bins to either a Point/Item or Cross Functional Coverage Model
-- Checking for sizing that is different from original sizing already done in OSVVM CoveragePkg
-- It is important to maintain an index that corresponds to the order the bins were entered as
-- that is used when coverage is recorded.
procedure VendorCovBinAdd( obj: VendorCovHandleType; bins: VendorCovRangeArrayType; Action: integer; atleast: integer; name: string );
attribute foreign of VendorCovBinAdd[ VendorCovHandleType, VendorCovRangeArrayType, integer, integer, string ]: procedure is "VHPI systf; cvg_CvpCrBinCreate";
-- Increment the coverage of bin identified by index number.
-- Index ranges from 1 to Number of Bins.
-- Index corresponds to the order the bins were entered (starting from 1)
procedure VendorCovBinInc( obj: VendorCovHandleType; index: integer );
attribute foreign of VendorCovBinInc[ VendorCovHandleType, integer ]: procedure is "VHPI systf; cvg_CvpCrBinIncr";
-- Action (integer):
-- constant COV_COUNT : integer := 1;
-- constant COV_IGNORE : integer := 0;
-- constant COV_ILLEGAL : integer := -1;
end package;
package body VendorCovApiPkg is
-- Replace any existing package body for this package
end package body VendorCovApiPkg ;
|
--
-- File Name: VendorCovApiPkg_Aldec.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: ALDEC VERSION
--
-- Maintainer:
--
-- Package Defines
-- A set of foreign procedures that link OSVVM's CoveragePkg
-- coverage model creation and coverage capture with the
-- built-in capability of a simulator.
--
--
-- Revision History: For more details, see CoveragePkg_release_notes.pdf
-- Date Version Description
-- 11/2016: 2016.11 Initial revision
-- 12/2016 2016.11a Fixed an issue with attributes
--
--
-- Copyright (c) 2016 by Aldec. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- Modified copies of this source file may be distributed
-- under the terms of the ARTISTIC License as published by
-- The Perl Foundation; either version 2.0 of the License,
-- or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
-- --
--------------------------------------------------------------------------
package VendorCovApiPkg is
subtype VendorCovHandleType is integer;
-- Types for how coverage bins are represented. Matches OSVVM types.
type VendorCovRangeType is record
min: integer;
max: integer;
end record;
type VendorCovRangeArrayType is array ( integer range <> ) of VendorCovRangeType;
-- Create Initial Data Structure for Point/Item Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovPointCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovPointCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CvpCreate";
-- Create Initial Data Structure for Cross Functional Coverage Model
-- Sets initial name of the coverage model if available
impure function VendorCovCrossCreate( name: string ) return VendorCovHandleType;
attribute foreign of VendorCovCrossCreate[ string return VendorCovHandleType ]: function is "VHPI systf; cvg_CrCreate";
-- Sets/Updates the name of the Coverage Model.
-- Should not be called until the data structure is created by VendorCovPointCreate or VendorCovCrossCreate.
-- Replaces name that was set by VendorCovPointCreate or VendorCovCrossCreate.
procedure VendorCovSetName( obj: VendorCovHandleType; name: string );
attribute foreign of VendorCovSetName[ VendorCovHandleType, string ]: procedure is "VHPI systf; cvg_SetCoverName";
-- Add a bin or set of bins to either a Point/Item or Cross Functional Coverage Model
-- Checking for sizing that is different from original sizing already done in OSVVM CoveragePkg
-- It is important to maintain an index that corresponds to the order the bins were entered as
-- that is used when coverage is recorded.
procedure VendorCovBinAdd( obj: VendorCovHandleType; bins: VendorCovRangeArrayType; Action: integer; atleast: integer; name: string );
attribute foreign of VendorCovBinAdd[ VendorCovHandleType, VendorCovRangeArrayType, integer, integer, string ]: procedure is "VHPI systf; cvg_CvpCrBinCreate";
-- Increment the coverage of bin identified by index number.
-- Index ranges from 1 to Number of Bins.
-- Index corresponds to the order the bins were entered (starting from 1)
procedure VendorCovBinInc( obj: VendorCovHandleType; index: integer );
attribute foreign of VendorCovBinInc[ VendorCovHandleType, integer ]: procedure is "VHPI systf; cvg_CvpCrBinIncr";
-- Action (integer):
-- constant COV_COUNT : integer := 1;
-- constant COV_IGNORE : integer := 0;
-- constant COV_ILLEGAL : integer := -1;
end package;
package body VendorCovApiPkg is
-- Replace any existing package body for this package
end package body VendorCovApiPkg ;
|
-- A timer test-bed circuit.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.numeric_std.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY g23_HMS_counter IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
load_enable : IN STD_LOGIC;
count_enable: IN STD_LOGIC;
h_set : IN STD_LOGIC_VECTOR(4 downto 0);
m_set : IN STD_LOGIC_VECTOR(5 downto 0);
s_set : IN STD_LOGIC_VECTOR(5 downto 0);
h_inc : IN STD_LOGIC;
m_inc : IN STD_LOGIC;
s_inc : IN STD_LOGIC;
dst : IN STD_LOGIC;
hours : OUT STD_LOGIC_VECTOR(4 downto 0);
minutes : OUT STD_LOGIC_VECTOR(5 downto 0);
seconds : OUT STD_LOGIC_VECTOR(5 downto 0);
end_of_day : OUT STD_LOGIC
);
END g23_HMS_counter;
ARCHITECTURE alpha OF g23_HMS_counter IS
signal h : STD_LOGIC_VECTOR(4 downto 0);
signal m : STD_LOGIC_VECTOR(5 downto 0);
signal s : STD_LOGIC_VECTOR(5 downto 0);
signal h_maxed : STD_LOGIC;
signal m_maxed : STD_LOGIC;
signal s_maxed : STD_LOGIC;
signal earth_clk: STD_LOGIC;
COMPONENT g23_earth_timer
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
end_of_day <= h_maxed AND m_maxed AND s_maxed;
hours <= h;
minutes <= m;
seconds <= s;
h_maxed <= '1' WHEN (h = "10111") ELSE '0';
m_maxed <= '1' WHEN (m = "111011") ELSE '0';
s_maxed <= '1' WHEN (s = "111011") ELSE '0';
seconds_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 60,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 6
)
PORT MAP (
aload => load_enable,
aclr => reset,
clock => clk,
data => s_set,
cnt_en => count_enable OR s_inc,
q => s
);
minutes_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 60,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 6
)
PORT MAP (
aload => load_enable,
aclr => reset,
clock => clk,
data => m_set,
cnt_en => (count_enable AND s_maxed) OR m_inc,
q => m
);
hours_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 24,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 5
)
PORT MAP (
aload => load_enable,
aclr => reset,
clock => clk,
data => h_set,
cnt_en => (count_enable AND m_maxed AND s_maxed) OR h_inc OR dst,
q => h
);
END alpha; |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo PlayRecord.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- FSM per la gestione di Registrazione e Riproduzione Audio.
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity PlayRecord is
generic (
st_start : std_logic_vector(2 downto 0) := "000"; -- Valori di stato della FSM
st_rc_audio_wait : std_logic_vector(2 downto 0) := "001";
st_rc_ram_nextaddr : std_logic_vector(2 downto 0) := "010";
st_rc_ram_wait : std_logic_vector(2 downto 0) := "011";
st_pl_ram_rd : std_logic_vector(2 downto 0) := "100";
st_pl_audio_wait : std_logic_vector(2 downto 0) := "101";
st_pl_ram_nextaddr : std_logic_vector(2 downto 0) := "110";
st_input_check : std_logic_vector(2 downto 0) := "111"
);
port (
CLOCK_50 : in std_logic;
CLOCK_1S : in std_logic;
reset : in std_logic;
ram_addr : out std_logic_vector(21 downto 0);
ram_data_in : out std_logic_vector(15 downto 0);
ram_read : out std_logic;
ram_write : out std_logic;
ram_data_out : in std_logic_vector(15 downto 0);
ram_valid : in std_logic;
ram_waitrq : in std_logic;
audio_out : out std_logic_vector(15 downto 0);
audio_in : in std_logic_vector(15 downto 0);
audio_out_allowed : in std_logic;
audio_in_available : in std_logic;
write_audio_out : out std_logic;
read_audio_in : out std_logic;
play : in std_logic;
rec : in std_logic;
pause : in std_logic;
speed : in std_logic_vector(1 downto 0);
ram_addr_max : in std_logic_vector(21 downto 0);
playLimitReached : inout std_logic;
secondsCounter : inout std_logic_vector(7 downto 0)
);
end PlayRecord;
architecture behaviour OF PlayRecord IS
signal st : std_logic_vector(2 downto 0);
signal streg : std_logic_vector(2 downto 0);
-- Segnali buffer
signal ram_addr_sig : std_logic_vector(21 downto 0);
signal ram_data_in_sig : std_logic_vector(15 downto 0);
signal ram_read_sig : std_logic;
signal ram_write_sig : std_logic;
signal audio_out_sig : std_logic_vector(15 downto 0);
signal write_audio_out_sig : std_logic;
signal read_audio_in_sig : std_logic;
signal secondsIncrement : std_logic_vector(7 downto 0);
begin
secondsIncrement <= "000000" & speed + "00000001"; -- Determina lo step di incremento dei secondi in Play
-- Segnali buffer
ram_addr <= ram_addr_sig;
ram_data_in <= ram_data_in_sig;
ram_read <= ram_read_sig;
ram_write <= ram_write_sig;
audio_out <= audio_out_sig;
write_audio_out <= write_audio_out_sig;
read_audio_in <= read_audio_in_sig;
playLimitReached <= '1' when ram_addr_max <= ram_addr_sig else '0';
process (all)
begin
st <= streg;
---------------------------------------------------------------------------------------------
---------------------------------------------------------------- FSM della fase di Play e Rec
---------------------------------------------------------------------------------------------
case streg is
---------------------------------------------- STATO START
when st_start =>
st <= st_input_check; -- Da start va a input_check
---------------------------------------------- STATO IDLE
when st_input_check =>
if pause = '0' then -- Stato "idle": determina la prossima operazione
if play = '1' then
if playLimitReached = '0' then
st <= st_pl_audio_wait; -- Play
end if;
elsif rec = '1' then
st <= st_rc_audio_wait; -- Rec: attesa segnale audio
else
st <= st_start; -- Ne' Play ne' Rec: non fa nulla
end if;
end if;
---------------------------------------------- GESTIONE REGSTRAZIONE
when st_rc_audio_wait =>
if (audio_in_available = '1') then
st <= st_rc_ram_nextaddr; -- Rec: passa a indirizzo di memoria successivo
end if;
when st_rc_ram_nextaddr =>
st <= st_rc_ram_wait; -- Rec: scrittura in memoria
when st_rc_ram_wait =>
if (ram_waitrq = '0') then
st <= st_input_check; -- Rec: scrittura terminata e ritorno
end if;
---------------------------------------------- GESTIONE RIPRODUZIONE
when st_pl_audio_wait =>
if (audio_out_allowed = '1') then
st <= st_pl_ram_rd; -- Play: leggi da RAM
end if;
when st_pl_ram_rd =>
if (ram_waitrq ='0' and ram_valid = '1') then
st <= st_pl_ram_nextaddr; -- Play: passa a indirizzo di memoria successivo
end if;
when st_pl_ram_nextaddr =>
st <= st_input_check; -- Play: lettura completata e ritorno
end case;
end process;
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (reset = '1') then
streg <= st_input_check;
else
streg <= st;
end if;
end if;
end process;
-- Contatore indirizzo RAM
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (reset = '1') then
ram_addr_sig <= "0000000000000000000000";
else
if (streg = st_start) then
ram_addr_sig <= "0000000000000000000000";
elsif (streg = st_rc_ram_nextaddr) then
ram_addr_sig <= ram_addr_sig + "0000000000000000000001";
elsif streg = st_pl_ram_nextaddr then -- La velocita' fa "saltare" n banchi di RAM
ram_addr_sig <= ram_addr_sig + "0000000000000000000001" + ("00000000000000000000" & speed);
end if;
end if;
end if;
end process;
-- Contatore secondi
process (CLOCK_50, CLOCK_1S)
begin
if rising_edge(CLOCK_1S) then
if (reset = '1') then
secondsCounter <= "00000000";
else
if (streg = st_start) then
secondsCounter <= "00000000";
elsif pause = '0' then
if play = '1' then
if playLimitReached = '0' then -- secondsIncrement dipende dalla velocita'
secondsCounter <= secondsCounter + secondsIncrement;
else
secondsCounter <= "00000000";
end if;
elsif rec = '1' then
secondsCounter <= secondsCounter + "00000001";
else
secondsCounter <= "00000000";
end if;
end if;
end if;
end if;
end process;
-- Controller Audio
read_audio_in_sig <= '1' when ((streg = st_rc_ram_nextaddr) or (streg = st_start and audio_in_available = '1')) else '0';
write_audio_out_sig <= '1' when (st = st_pl_ram_nextaddr) else '0';
-- Connessione con SDRAM
ram_data_in_sig <= audio_in;
audio_out_sig <= ram_data_out;
ram_write_sig <= '1' when (streg = st_rc_ram_wait) else '0';
ram_read_sig <= '1' when (streg = st_pl_ram_rd) else '0';
END behaviour; |
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`protect end_protected
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Subsets and Splits