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-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
widesig_o : out std_ulogic_vector(31 downto 0);
widesig_r_0 : out std_ulogic;
widesig_r_1 : out std_ulogic;
widesig_r_2 : out std_ulogic;
widesig_r_3 : out std_ulogic;
widesig_r_4 : out std_ulogic;
widesig_r_5 : out std_ulogic;
widesig_r_6 : out std_ulogic;
widesig_r_7 : out std_ulogic;
widesig_r_8 : out std_ulogic;
widesig_r_9 : out std_ulogic;
widesig_r_10 : out std_ulogic;
widesig_r_11 : out std_ulogic;
widesig_r_12 : out std_ulogic;
widesig_r_13 : out std_ulogic;
widesig_r_14 : out std_ulogic;
widesig_r_15 : out std_ulogic;
widesig_r_16 : out std_ulogic;
widesig_r_17 : out std_ulogic;
widesig_r_18 : out std_ulogic;
widesig_r_19 : out std_ulogic;
widesig_r_20 : out std_ulogic;
widesig_r_21 : out std_ulogic;
widesig_r_22 : out std_ulogic;
widesig_r_23 : out std_ulogic;
widesig_r_24 : out std_ulogic;
widesig_r_25 : out std_ulogic;
widesig_r_26 : out std_ulogic;
widesig_r_27 : out std_ulogic;
widesig_r_28 : out std_ulogic;
widesig_r_29 : out std_ulogic;
widesig_r_30 : out std_ulogic;
unsplice_a1_no3 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0);
widemerge_a1 : out std_ulogic_vector(31 downto 0);
p_mix_test1_go : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
port_b_1 : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_c_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
video_i : in std_ulogic_vector(3 downto 0);
widesig_i : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal test1 : std_ulogic;
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0);
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0);
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0);
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0);
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0);
signal unsplice_bad_a : std_ulogic_vector(127 downto 0);
signal unsplice_bad_b : std_ulogic_vector(127 downto 0);
-- __I_NODRV_I signal video_i : std_ulogic_vector(3 downto 0);
signal widemerge_a1 : std_ulogic_vector(31 downto 0);
signal widesig : std_ulogic_vector(31 downto 0);
signal widesig_r_0 : std_ulogic;
signal widesig_r_1 : std_ulogic;
signal widesig_r_10 : std_ulogic;
signal widesig_r_11 : std_ulogic;
signal widesig_r_12 : std_ulogic;
signal widesig_r_13 : std_ulogic;
signal widesig_r_14 : std_ulogic;
signal widesig_r_15 : std_ulogic;
signal widesig_r_16 : std_ulogic;
signal widesig_r_17 : std_ulogic;
signal widesig_r_18 : std_ulogic;
signal widesig_r_19 : std_ulogic;
signal widesig_r_2 : std_ulogic;
signal widesig_r_20 : std_ulogic;
signal widesig_r_21 : std_ulogic;
signal widesig_r_22 : std_ulogic;
signal widesig_r_23 : std_ulogic;
signal widesig_r_24 : std_ulogic;
signal widesig_r_25 : std_ulogic;
signal widesig_r_26 : std_ulogic;
signal widesig_r_27 : std_ulogic;
signal widesig_r_28 : std_ulogic;
signal widesig_r_29 : std_ulogic;
signal widesig_r_3 : std_ulogic;
signal widesig_r_30 : std_ulogic;
signal widesig_r_4 : std_ulogic;
signal widesig_r_5 : std_ulogic;
signal widesig_r_6 : std_ulogic;
signal widesig_r_7 : std_ulogic;
signal widesig_r_8 : std_ulogic;
signal widesig_r_9 : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_test1_go => test1, -- Use internally test1
unsplice_a1_no3 => unsplice_a1_no3, -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100, -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100, -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100, -- connect mid 100 bits
unsplice_bad_a => unsplice_bad_a,
unsplice_bad_b => unsplice_bad_b, -- # conflict
widemerge_a1 => widemerge_a1,
widesig_o => widesig,
widesig_r_0 => widesig_r_0,
widesig_r_1 => widesig_r_1,
widesig_r_10 => widesig_r_10,
widesig_r_11 => widesig_r_11,
widesig_r_12 => widesig_r_12,
widesig_r_13 => widesig_r_13,
widesig_r_14 => widesig_r_14,
widesig_r_15 => widesig_r_15,
widesig_r_16 => widesig_r_16,
widesig_r_17 => widesig_r_17,
widesig_r_18 => widesig_r_18,
widesig_r_19 => widesig_r_19,
widesig_r_2 => widesig_r_2,
widesig_r_20 => widesig_r_20,
widesig_r_21 => widesig_r_21,
widesig_r_22 => widesig_r_22,
widesig_r_23 => widesig_r_23,
widesig_r_24 => widesig_r_24,
widesig_r_25 => widesig_r_25,
widesig_r_26 => widesig_r_26,
widesig_r_27 => widesig_r_27,
widesig_r_28 => widesig_r_28,
widesig_r_29 => widesig_r_29,
widesig_r_3 => widesig_r_3,
widesig_r_30 => widesig_r_30,
widesig_r_4 => widesig_r_4,
widesig_r_5 => widesig_r_5,
widesig_r_6 => widesig_r_6,
widesig_r_7 => widesig_r_7,
widesig_r_8 => widesig_r_8,
widesig_r_9 => widesig_r_9
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
port_b_1 => test1 -- Use internally test1
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_unsplice_a1_no3_125_0_gi => unsplice_a1_no3(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_no3_127_127_gi => unsplice_a1_no3(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0), -- # conflict
p_mix_widemerge_a1_31_0_gi => widemerge_a1,
p_mix_widesig_r_0_gi => widesig_r_0,
p_mix_widesig_r_10_gi => widesig_r_10,
p_mix_widesig_r_11_gi => widesig_r_11,
p_mix_widesig_r_12_gi => widesig_r_12,
p_mix_widesig_r_13_gi => widesig_r_13,
p_mix_widesig_r_14_gi => widesig_r_14,
p_mix_widesig_r_15_gi => widesig_r_15,
p_mix_widesig_r_16_gi => widesig_r_16,
p_mix_widesig_r_17_gi => widesig_r_17,
p_mix_widesig_r_18_gi => widesig_r_18,
p_mix_widesig_r_19_gi => widesig_r_19,
p_mix_widesig_r_1_gi => widesig_r_1,
p_mix_widesig_r_20_gi => widesig_r_20,
p_mix_widesig_r_21_gi => widesig_r_21,
p_mix_widesig_r_22_gi => widesig_r_22,
p_mix_widesig_r_23_gi => widesig_r_23,
p_mix_widesig_r_24_gi => widesig_r_24,
p_mix_widesig_r_25_gi => widesig_r_25,
p_mix_widesig_r_26_gi => widesig_r_26,
p_mix_widesig_r_27_gi => widesig_r_27,
p_mix_widesig_r_28_gi => widesig_r_28,
p_mix_widesig_r_29_gi => widesig_r_29,
p_mix_widesig_r_2_gi => widesig_r_2,
p_mix_widesig_r_30_gi => widesig_r_30,
p_mix_widesig_r_3_gi => widesig_r_3,
p_mix_widesig_r_4_gi => widesig_r_4,
p_mix_widesig_r_5_gi => widesig_r_5,
p_mix_widesig_r_6_gi => widesig_r_6,
p_mix_widesig_r_7_gi => widesig_r_7,
p_mix_widesig_r_8_gi => widesig_r_8,
p_mix_widesig_r_9_gi => widesig_r_9,
-- __I_NODRV_I video_i => __nodrv__/video_i,
widesig_i => widesig
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gpio
-- File: gpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 0;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" => readdata(nbits-1 downto 0) := r.din2;
when "001" => readdata(nbits-1 downto 0) := r.dout;
when "010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => null;
when "001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if i > NAHBIRQ-1 then
exit;
end if;
xirq(i) := tmp2(i);
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if rst = '0' then
v.imask := (others => '0'); v.bypass := (others => '0');
if oepol = 1 then v.dir := (others => '0');
else v.dir := (others => '1'); end if;
v.dout := (others => '0');
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then r <= rin; end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gpio
-- File: gpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 0;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" => readdata(nbits-1 downto 0) := r.din2;
when "001" => readdata(nbits-1 downto 0) := r.dout;
when "010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => null;
when "001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when others =>
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if i > NAHBIRQ-1 then
exit;
end if;
xirq(i) := tmp2(i);
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if rst = '0' then
v.imask := (others => '0'); v.bypass := (others => '0');
if oepol = 1 then v.dir := (others => '0');
else v.dir := (others => '1'); end if;
v.dout := (others => '0');
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then r <= rin; end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY busTriState IS
PORT(
clk : in std_logic;
rst : in std_logic;
rw : in std_logic;
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
dq : inout std_logic_vector
);
END busTriState;
ARCHITECTURE main OF busTriState IS
BEGIN
PROCESS(clk, rst)
BEGIN
if (rst ='1') then
dq <= (others => 'Z');
elsif (rising_edge(clk)) then
if (rw = '1') then
dq <= d;
else
dq <= (others => 'Z');
q <= dq;
end if;
end if;
END PROCESS;
END main; |
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 13.2 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_cfa_gamma_cw is
port (
active_video_i: in std_logic;
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(7 downto 0);
vsync_i: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(23 downto 0);
vsync_o: out std_logic
);
end sg_cfa_gamma_cw;
architecture structural of sg_cfa_gamma_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal active_video_i_net: std_logic;
signal active_video_o_net: std_logic;
signal bayer_ctrl_reg_ce: std_logic;
signal ce_1_sg_x3: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x3: signal is "REDUCE";
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x3: std_logic;
signal data_in_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal hblank_i_net: std_logic;
signal hblank_o_net: std_logic;
signal hsync_i_net: std_logic;
signal hsync_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal vblank_i_net: std_logic;
signal vblank_o_net: std_logic;
signal video_data_i_net: std_logic_vector(7 downto 0);
signal video_data_o_net: std_logic_vector(23 downto 0);
signal vsync_i_net: std_logic;
signal vsync_o_net: std_logic;
begin
active_video_i_net <= active_video_i;
clkNet <= clk;
hblank_i_net <= hblank_i;
hsync_i_net <= hsync_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
vblank_i_net <= vblank_i;
video_data_i_net <= video_data_i;
vsync_i_net <= vsync_i;
clkNet_x0 <= xps_clk;
active_video_o <= active_video_o_net;
hblank_o <= hblank_o_net;
hsync_o <= hsync_o_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
vblank_o <= vblank_o_net;
video_data_o <= video_data_o_net;
vsync_o <= vsync_o_net;
bayer_ctrl: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000001000110110100000111100100",
latency => 1
)
port map (
ce => bayer_ctrl_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i => data_in_net,
o => data_out_net
);
bayer_ctrl_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_net,
dout => bayer_ctrl_reg_ce
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_cfa_gamma_x0: entity work.sg_cfa_gamma
port map (
active_video_i => active_video_i_net,
ce_1 => ce_1_sg_x3,
clk_1 => clk_1_sg_x3,
data_out => data_out_net,
dout => data_out_net,
hblank_i => hblank_i_net,
hsync_i => hsync_i_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
vblank_i => vblank_i_net,
video_data_i => video_data_i_net,
vsync_i => vsync_i_net,
active_video_o => active_video_o_net,
data_in => data_in_net,
en => en_net,
hblank_o => hblank_o_net,
hsync_o => hsync_o_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
vblank_o => vblank_o_net,
video_data_o => video_data_o_net,
vsync_o => vsync_o_net
);
end structural;
|
entity tb_issue is
end tb_issue;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_issue is
signal a : boolean;
begin
dut: entity work.issue
port map (a);
process
begin
wait for 1 ns;
assert a severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_64 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_64;
architecture BEHAVIORAL of dcm_32_64 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 64.00 = 32.000 * 24/12
CLKFX_MULTIPLY => 24,
CLKFX_DIVIDE => 12,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 08/07/2015 - 20:07
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MEM IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
MemWrite : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END MEM;
ARCHITECTURE ARC_MEM OF MEM IS
TYPE RAM_TYPE IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL RAM: RAM_TYPE;
SIGNAL ADRESS : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF RESET = '1' THEN
RAM <= ((OTHERS => (OTHERS=>'0')));
ELSIF CLK'EVENT AND CLK = '1' THEN
IF MemWrite = '1' THEN
--MIPS ARMAZEMA EM BYTES OU SEJA 4 EM 4
--POR ISSO PEGA DE 31 A 2, POIS DEVIDO A POSIO DE ORDENAO DO ARRAY SER DE 1 EM 1...
--...SE DESLOCA DOIS PARA DIREITA EX:
-- SW $S0, 4($T0) 1010110100101000 0000000000000100
-- [31-2]
-- 1010110100101000 00000000000001 = 1
-- SW $S0, 8($T0) 1010110100101000 0000000000001000
-- [31-2]
-- 1010110100101000 00000000000010 = 2
RAM(TO_INTEGER (UNSIGNED(ADRESS(31 DOWNTO 2)))) <= IN_B;
END IF;
END IF;
END PROCESS;
OUT_A <= RAM(TO_INTEGER(UNSIGNED(ADRESS(31 DOWNTO 2)))) WHEN MemRead ='1';
--PARA UTILIZAR COM O MARS
ADRESS <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) - X"FFFF0000");
END ARC_MEM;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 08/07/2015 - 20:07
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MEM IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
MemWrite : IN STD_LOGIC;
MemRead : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END MEM;
ARCHITECTURE ARC_MEM OF MEM IS
TYPE RAM_TYPE IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL RAM: RAM_TYPE;
SIGNAL ADRESS : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF RESET = '1' THEN
RAM <= ((OTHERS => (OTHERS=>'0')));
ELSIF CLK'EVENT AND CLK = '1' THEN
IF MemWrite = '1' THEN
--MIPS ARMAZEMA EM BYTES OU SEJA 4 EM 4
--POR ISSO PEGA DE 31 A 2, POIS DEVIDO A POSIO DE ORDENAO DO ARRAY SER DE 1 EM 1...
--...SE DESLOCA DOIS PARA DIREITA EX:
-- SW $S0, 4($T0) 1010110100101000 0000000000000100
-- [31-2]
-- 1010110100101000 00000000000001 = 1
-- SW $S0, 8($T0) 1010110100101000 0000000000001000
-- [31-2]
-- 1010110100101000 00000000000010 = 2
RAM(TO_INTEGER (UNSIGNED(ADRESS(31 DOWNTO 2)))) <= IN_B;
END IF;
END IF;
END PROCESS;
OUT_A <= RAM(TO_INTEGER(UNSIGNED(ADRESS(31 DOWNTO 2)))) WHEN MemRead ='1';
--PARA UTILIZAR COM O MARS
ADRESS <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) - X"FFFF0000");
END ARC_MEM;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the grethaxi device.
--! @details This is Ethernet MAC device with the AMBA AXI inteface
--! and EDCL debugging functionality.
------------------------------------------------------------------------------
--!
--! @page eth_link Ethernet
--!
--! @par Overview
--! The Ethernet Media Access Controller (GRETH) provides an interface between
--! an AMBA-AXI bus and Ethernet network. It supports 10/100 Mbit speed in both
--! full- and half-duplex modes. Integrated EDCL submodule implements hardware
--! decoding of UDP traffic and redirects EDCL request directly on AXI system
--! bus. The AMBA interface consists of an AXI slave
--! interface for configuration and control and an AXI master interface
--! for transmit and receive data. There is one DMA engine for the transmitter
--! and one for receiver. EDCL submodule and both DMA engines share the same
--! AXI master interface.
--!
--! @subsection eth_confgure Configure Host Computer
--! To make development board visible in your local network your should
--! properly specify connection properties. In this chapter I will show how to
--! configure the host computer (Windows 7 or Linux) to communicate with the
--! FPGA hardware over Ethernet.
--!
--! @note <em>If you also want simultaneous Internet access your host computer
--! requires a second Ethernet port. I couldn't find workable
--! configuration via router.</em>
--!
--! @warning I recommend you to make restore point before you start.
--!
--! @section eth_cfgwin Configure Windows Host
--!
--! Let's setup the following network configuration that allows to work with
--! FPGA board and to be connected to Internet. I use different Ethernet
--! ports and different subnets (192.168.0.x and 192.168.1.x accordingly).
--!
--! <img src="pics/eth_common.png" alt="Ethernet config">
--!
--! @par Host IP and subnet definition:
--! -# Open \c cmd console.
--! -# Use \c ipconfig command to determine network settings.</b>
--! @verbatim
--! ipconfig /all
--! @endverbatim
--! -# Find your IP address (in my case it's 192.168.1.4)
--! -# Check and change if needed default IP address of SOC as follow.
--!
--! @par Setup hard-reset FPGA IP address:
--! -# Open in editor <i>rocket_soc.vhd</i>.
--! -# Find place where <i>grethaxi</i> module is instantiated.
--! -# Change generic <b>ipaddrh</b> and <b>ipaddrl</b> parameters so that
--! they belonged another subnet (Default values: C0A8.0033 corresponding
--! to 192.168.0.51) than Internet connection.
--!
--! @par Configure the Ethernet card for your FPGA hardware
--! -# Load pre-built image file into FPGA board (located in
--! <i>./rocket_soc/bit_files/</i> folder) or use your own one.<br>
--! -# Open <b>Network and Sharing Center</b> via Control Panel
--! <img src="pics/eth_win1.png" alt="ControlPanel">
--! -# Click on <b>Local Area Connection 2</b> link
--! <img src="pics/eth_win2.png" alt="ControlPanel">
--! -# Click on <b>Properties</b> to open properties dialog.
--! <img src="pics/eth_win3.png" alt="ControlPanel">
--! -# Disable all network services except <b>Internet Protocol Version 4</b>
--! as shown on figure above.<br>
--! -# Select enabled service and click on <b>Properties</b> button.
--! <img src="pics/eth_win4.png" alt="ControlPanel">
--! -# Specify unique IP as shown above so that FPGA and your Local
--! Connection were placed <b>in the same subnet</b>.<br>
--! -# Leave the subnet mask set to the default value 255.255.255.0.<br>
--! -# Click OK.
--!
--! @par Check connection
--! -# Check presence of the Ethernet activity by blinking LEDs near the
--! Ethernet connector on FPGA board
--! -# Run \c arp command to see arp table entries.
--! @verbatim
--! arp -a -v
--! @endverbatim
--! <img src="pics/eth_check1.png" alt="Check arp">
--! -# MAC supports only ARP and EDCL requests on hardware level and it cannot
--! respond on others without properly installed software. By this reason ping
--! won't work without running OS on FPGA target but it maybe usefull to ping
--! FPGA target so that it can force updating of the ARP table.
--!
--! @section eth_cfglin Configure Linux Host
--!
--! Let's setup the similar network configuration on Linux host.
--! -# Check <b>ipaddrh</b> and <b>ipaddrl</b> values that are hardcoded
--! on top-level of SOC (default values: C0A8.0033 corresponding
--! to 192.168.0.51).
--! -# Set host IP value in the same subnet using the \c ifconfig command.
--! You might need to enter a password to use the \c sudo command.
--! @verbatim
--! % sudo ifconfig eth0 192.168.0.53 netmask 255.255.255.0
--! @endverbatim
--! -# Enter the following command in the shell to check that the changes
--! took effect:
--! @verbatim
--! % ifconfig eth0
--! @endverbatim
--!
--! @section eth_appl Run Application
--!
--! Now your FPGA board is ready to interact with the host computer via Ethernet.
--! You can find detailed information about MAC (GRETH)
--! in [GRLIB IP Core User's Manual](http://gaisler.com/products/grlib/grip.pdf).
--!
--! There you can find:
--! -# DMA Configuration registers description (Rx/Tx Descriptors tables and entries).
--! -# EDCL message format.
--! -# \c GRLIB itself includes C-example that configure MAC Rx/Tx queues
--! and start transmission of the 1500 Mbyte of data to define Bitrate in Mbps.
--!
--! We provide debugger functionality via Ethernet.
--! See @link dbg_link Debugger description @endlink page.
--!
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Ethernet specific declarations.
library rocketlib;
use rocketlib.grethpkg.all;
entity grethaxi is
generic(
xslvindex : integer := 0;
xmstindex : integer := 0;
xmstindex2 : integer := 1;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0135#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in nasti_master_in_type;
msto : out nasti_master_out_type;
mstcfg : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
slvi : in nasti_slave_in_type;
slvo : out nasti_slave_out_type;
slvcfg : out nasti_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end entity;
architecture arch_grethaxi of grethaxi is
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant xslvconfig : nasti_slave_config_type := (
xindex => xslvindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ETHMAC,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
constant xmstconfig : nasti_master_config_type := (
xindex => xmstindex,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_MAC_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xmstindex2,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_EDCL_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of std_logic_vector(15 downto 0);
type registers is record
bank_slv : nasti_slave_bank_type;
ctrl : eth_control_type;
end record;
signal r, rin : registers;
signal imac_cmd : eth_command_type;
signal omac_status : eth_mac_status_type;
signal omac_rdbgdata : std_logic_vector(31 downto 0);
signal omac_tmsto : eth_tx_ahb_in_type;
signal imac_tmsti : eth_tx_ahb_out_type;
signal omac_tmsto2 : eth_tx_ahb_in_type;
signal imac_tmsti2 : eth_tx_ahb_out_type;
signal omac_rmsto : eth_rx_ahb_in_type;
signal imac_rmsti : eth_rx_ahb_out_type;
begin
comb : process(r, ethi, slvi, omac_rdbgdata, omac_status, rst) is
variable v : registers;
variable vcmd : eth_command_type;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata32 : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable val : std_logic_vector(8*CFG_ALIGN_BYTES-1 downto 0);
begin
v := r;
vcmd := eth_command_none;
procedureAxi4(slvi, xslvconfig, r.bank_slv, v.bank_slv);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := r.bank_slv.raddr(n)(17 downto log2(CFG_ALIGN_BYTES));
val := (others => '0');
if (ramdebug = 0) or (raddr_reg(n)(15 downto 14) = "00") then
case raddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
val(13) := r.ctrl.ramdebugen;
end if;
if (edcl /= 0) then
val(31) := '1';
val(30 downto 28) := bufsize;
val(14) := r.ctrl.edcldis;
val(12) := r.ctrl.disableduplex;
end if;
if enable_mdint = 1 then
val(26) := '1';
val(10) := r.ctrl.pstatirqen;
end if;
if multicast = 1 then
val(25) := '1';
val(11) := r.ctrl.mcasten;
end if;
if rmii = 1 then
val(7) := omac_status.speed;
end if;
val(6) := omac_status.reset;
val(5) := r.ctrl.prom;
val(4) := omac_status.full_duplex;
val(3) := r.ctrl.rx_irqen;
val(2) := r.ctrl.tx_irqen;
val(1) := omac_status.rxen;
val(0) := omac_status.txen;
when "0001" => --status/int source reg
val(9) := not (omac_status.edcltx_idle or omac_status.edclrx_idle);
if enable_mdint = 1 then
val(8) := omac_status.phystat;
end if;
val(7) := omac_status.invaddr;
val(6) := omac_status.toosmall;
val(5) := omac_status.txahberr;
val(4) := omac_status.rxahberr;
val(3) := omac_status.tx_int;
val(2) := omac_status.rx_int;
val(1) := omac_status.tx_err;
val(0) := omac_status.rx_err;
when "0010" => --mac addr lsb
val := r.ctrl.mac_addr(31 downto 0);
when "0011" => --mac addr msb/mdio address
val(15 downto 0) := r.ctrl.mac_addr(47 downto 32);
when "0100" => --mdio ctrl/status
val(31 downto 16) := omac_status.mdio.cmd.data;
val(15 downto 11) := r.ctrl.mdio_phyadr;
val(10 downto 6) := omac_status.mdio.cmd.regadr;
val(3) := omac_status.mdio.busy;
val(2) := omac_status.mdio.linkfail;
val(1) := omac_status.mdio.cmd.read;
val(0) := omac_status.mdio.cmd.write;
when "0101" => --tx descriptor
val(31 downto 10) := r.ctrl.txdesc;
val(9 downto 3) := omac_status.txdsel;
when "0110" => --rx descriptor
val(31 downto 10) := r.ctrl.rxdesc;
val(9 downto 3) := omac_status.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
val := r.ctrl.edclip;
end if;
when "1000" =>
if multicast = 1 then
val := r.ctrl.hash(63 downto 32);
end if;
when "1001" =>
if multicast = 1 then
val := r.ctrl.hash(31 downto 0);
end if;
when "1010" =>
if edcl /= 0 then
val(15 downto 0) := r.ctrl.emacaddr(47 downto 32);
end if;
when "1011" =>
if edcl /= 0 then
val := r.ctrl.emacaddr(31 downto 0);
end if;
when others => null;
end case;
elsif raddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
end if;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := val;
end loop;
if slvi.w_valid = '1' and
r.bank_slv.wstate = wtrans and
r.bank_slv.wresp = NASTI_RESP_OKAY then
wdata := slvi.w_data;
wstrb := slvi.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := r.bank_slv.waddr(n)(17 downto 2);
wdata32 := wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
if wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n) /= "0000" then
if (ramdebug = 0) or (waddr_reg(n)(15 downto 14) = "00") then
case waddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
v.ctrl.ramdebugen := wdata32(13);
end if;
if edcl /= 0 then
v.ctrl.edcldis := wdata32(14);
v.ctrl.disableduplex := wdata32(12);
end if;
if multicast = 1 then
v.ctrl.mcasten := wdata32(11);
end if;
if enable_mdint = 1 then
v.ctrl.pstatirqen := wdata32(10);
end if;
if rmii = 1 then
vcmd.set_speed := wdata32(7);
vcmd.clr_speed := not wdata32(7);
end if;
vcmd.set_reset := wdata32(6);
vcmd.clr_reset := not wdata32(6);
v.ctrl.prom := wdata32(5);
vcmd.set_full_duplex := wdata32(4);
vcmd.clr_full_duplex := not wdata32(4);
v.ctrl.rx_irqen := wdata32(3);
v.ctrl.tx_irqen := wdata32(2);
vcmd.set_rxena := wdata32(1);
vcmd.clr_rxena := not wdata32(1);
vcmd.set_txena := wdata32(0);
vcmd.clr_txena := not wdata32(0);
when "0001" => --status/int source reg
if enable_mdint = 1 then
vcmd.clr_status_phystat := wdata32(8);
end if;
vcmd.clr_status_invaddr := wdata32(7);
vcmd.clr_status_toosmall := wdata32(6);
vcmd.clr_status_txahberr := wdata32(5);
vcmd.clr_status_rxahberr := wdata32(4);
vcmd.clr_status_tx_int := wdata32(3);
vcmd.clr_status_rx_int := wdata32(2);
vcmd.clr_status_tx_err := wdata32(1);
vcmd.clr_status_rx_err := wdata32(0);
when "0010" => --mac addr lsb
v.ctrl.mac_addr(31 downto 0) := wdata32(31 downto 0);
when "0011" => --mac addr msb
v.ctrl.mac_addr(47 downto 32) := wdata32(15 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
vcmd.mdio_cmd.valid := not omac_status.mdio.busy;
if omac_status.mdio.busy = '0' then
v.ctrl.mdio_phyadr := wdata32(15 downto 11);
end if;
vcmd.mdio_cmd.data := wdata32(31 downto 16);
vcmd.mdio_cmd.regadr := wdata32(10 downto 6);
vcmd.mdio_cmd.read := wdata32(1);
vcmd.mdio_cmd.write := wdata32(0);
end if;
when "0101" => --tx descriptor
vcmd.set_txdsel := '1';
vcmd.txdsel := wdata32(9 downto 3);
v.ctrl.txdesc := wdata32(31 downto 10);
when "0110" => --rx descriptor
vcmd.set_rxdsel := '1';
vcmd.rxdsel := wdata32(9 downto 3);
v.ctrl.rxdesc := wdata32(31 downto 10);
when "0111" => --edcl ip
if (edcl /= 0) then
v.ctrl.edclip := wdata32;
end if;
when "1000" => --hash msb
if multicast = 1 then
v.ctrl.hash(63 downto 32) := wdata32;
end if;
when "1001" => --hash lsb
if multicast = 1 then
v.ctrl.hash(31 downto 0) := wdata32;
end if;
when "1010" =>
if edcl /= 0 then
v.ctrl.emacaddr(47 downto 32) := wdata32(15 downto 0);
end if;
when "1011" =>
if edcl /= 0 then
v.ctrl.emacaddr(31 downto 0) := wdata32;
end if;
when others => null;
end case;
elsif waddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
end if;
end if;
end loop;
end if;
slvo <= functionAxi4Output(r.bank_slv, rdata);
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if rst = '0' then
v.bank_slv := NASTI_SLAVE_BANK_RESET;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
v.ctrl.pstatirqen := '0';
v.ctrl.mcasten := '0';
v.ctrl.ramdebugen := '0';
if edcl = 3 then
v.ctrl.edcldis := ethi.edcldisable;
elsif edcl /= 0 then
v.ctrl.edcldis := '0';
end if;
v.ctrl.disableduplex := '0';
if phyrstadr /= 32 then
v.ctrl.mdio_phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.ctrl.mdio_phyadr := ethi.phyrstaddr;
end if;
v.ctrl.mac_addr := (others => '0');
v.ctrl.txdesc := (others => '0');
v.ctrl.rxdesc := (others => '0');
v.ctrl.hash := (others => '0');
v.ctrl.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
v.ctrl.emacaddr := conv_std_logic_vector(macaddrh, 24) &
conv_std_logic_vector(macaddrl, 24);
if edcl > 1 then
v.ctrl.edclip(3 downto 0) := ethi.edcladdr;
v.ctrl.emacaddr(3 downto 0) := ethi.edcladdr;
end if;
end if;
rin <= v;
imac_cmd <= vcmd;
end process;
slvcfg <= xslvconfig;
mstcfg <= xmstconfig;
mstcfg2 <= xmstconfig2;
eth64 : grethc64 generic map (
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
) port map (
rst => rst,
clk => clk,
ctrli => r.ctrl,
cmdi => imac_cmd,
statuso => omac_status,
rdbgdatao => omac_rdbgdata,
--irq
irq => irq,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
tx_dv => ethi.tx_dv,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_en => ethi.rx_en,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
testrst => '0',
testen => '0',
testoen => '0',
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed,
tmsto => omac_tmsto,
tmsti => imac_tmsti,
tmsto2 => omac_tmsto2,
tmsti2 => imac_tmsti2,
rmsto => omac_rmsto,
rmsti => imac_rmsti
);
etho.tx_clk <= '0';
etho.gbit <= '0';
--! AXI Master interface providing DMA access
axi0 : eth_axi_mst generic map (
xindex => xmstindex
) port map (
rst,
clk,
msti,
msto,
omac_tmsto,
imac_tmsti,
omac_rmsto,
imac_rmsti
);
edclmst_on : if edclsepahbg = 1 generate
axi1 : eth_axi_mst generic map (
xindex => xmstindex2
) port map (
rst,
clk,
msti,
msto2,
omac_tmsto2,
imac_tmsti2,
eth_rx_in_none,
open
);
end generate;
edclmst_off : if edclsepahbg = 0 generate
msto2 <= nasti_master_out_none;
imac_tmsti2.grant <= '0';
imac_tmsti2.data <= (others => '0');
imac_tmsti2.ready <= '0';
imac_tmsti2.error <= '0';
imac_tmsti2.retry <= '0';
end generate;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the grethaxi device.
--! @details This is Ethernet MAC device with the AMBA AXI inteface
--! and EDCL debugging functionality.
------------------------------------------------------------------------------
--!
--! @page eth_link Ethernet
--!
--! @par Overview
--! The Ethernet Media Access Controller (GRETH) provides an interface between
--! an AMBA-AXI bus and Ethernet network. It supports 10/100 Mbit speed in both
--! full- and half-duplex modes. Integrated EDCL submodule implements hardware
--! decoding of UDP traffic and redirects EDCL request directly on AXI system
--! bus. The AMBA interface consists of an AXI slave
--! interface for configuration and control and an AXI master interface
--! for transmit and receive data. There is one DMA engine for the transmitter
--! and one for receiver. EDCL submodule and both DMA engines share the same
--! AXI master interface.
--!
--! @subsection eth_confgure Configure Host Computer
--! To make development board visible in your local network your should
--! properly specify connection properties. In this chapter I will show how to
--! configure the host computer (Windows 7 or Linux) to communicate with the
--! FPGA hardware over Ethernet.
--!
--! @note <em>If you also want simultaneous Internet access your host computer
--! requires a second Ethernet port. I couldn't find workable
--! configuration via router.</em>
--!
--! @warning I recommend you to make restore point before you start.
--!
--! @section eth_cfgwin Configure Windows Host
--!
--! Let's setup the following network configuration that allows to work with
--! FPGA board and to be connected to Internet. I use different Ethernet
--! ports and different subnets (192.168.0.x and 192.168.1.x accordingly).
--!
--! <img src="pics/eth_common.png" alt="Ethernet config">
--!
--! @par Host IP and subnet definition:
--! -# Open \c cmd console.
--! -# Use \c ipconfig command to determine network settings.</b>
--! @verbatim
--! ipconfig /all
--! @endverbatim
--! -# Find your IP address (in my case it's 192.168.1.4)
--! -# Check and change if needed default IP address of SOC as follow.
--!
--! @par Setup hard-reset FPGA IP address:
--! -# Open in editor <i>rocket_soc.vhd</i>.
--! -# Find place where <i>grethaxi</i> module is instantiated.
--! -# Change generic <b>ipaddrh</b> and <b>ipaddrl</b> parameters so that
--! they belonged another subnet (Default values: C0A8.0033 corresponding
--! to 192.168.0.51) than Internet connection.
--!
--! @par Configure the Ethernet card for your FPGA hardware
--! -# Load pre-built image file into FPGA board (located in
--! <i>./rocket_soc/bit_files/</i> folder) or use your own one.<br>
--! -# Open <b>Network and Sharing Center</b> via Control Panel
--! <img src="pics/eth_win1.png" alt="ControlPanel">
--! -# Click on <b>Local Area Connection 2</b> link
--! <img src="pics/eth_win2.png" alt="ControlPanel">
--! -# Click on <b>Properties</b> to open properties dialog.
--! <img src="pics/eth_win3.png" alt="ControlPanel">
--! -# Disable all network services except <b>Internet Protocol Version 4</b>
--! as shown on figure above.<br>
--! -# Select enabled service and click on <b>Properties</b> button.
--! <img src="pics/eth_win4.png" alt="ControlPanel">
--! -# Specify unique IP as shown above so that FPGA and your Local
--! Connection were placed <b>in the same subnet</b>.<br>
--! -# Leave the subnet mask set to the default value 255.255.255.0.<br>
--! -# Click OK.
--!
--! @par Check connection
--! -# Check presence of the Ethernet activity by blinking LEDs near the
--! Ethernet connector on FPGA board
--! -# Run \c arp command to see arp table entries.
--! @verbatim
--! arp -a -v
--! @endverbatim
--! <img src="pics/eth_check1.png" alt="Check arp">
--! -# MAC supports only ARP and EDCL requests on hardware level and it cannot
--! respond on others without properly installed software. By this reason ping
--! won't work without running OS on FPGA target but it maybe usefull to ping
--! FPGA target so that it can force updating of the ARP table.
--!
--! @section eth_cfglin Configure Linux Host
--!
--! Let's setup the similar network configuration on Linux host.
--! -# Check <b>ipaddrh</b> and <b>ipaddrl</b> values that are hardcoded
--! on top-level of SOC (default values: C0A8.0033 corresponding
--! to 192.168.0.51).
--! -# Set host IP value in the same subnet using the \c ifconfig command.
--! You might need to enter a password to use the \c sudo command.
--! @verbatim
--! % sudo ifconfig eth0 192.168.0.53 netmask 255.255.255.0
--! @endverbatim
--! -# Enter the following command in the shell to check that the changes
--! took effect:
--! @verbatim
--! % ifconfig eth0
--! @endverbatim
--!
--! @section eth_appl Run Application
--!
--! Now your FPGA board is ready to interact with the host computer via Ethernet.
--! You can find detailed information about MAC (GRETH)
--! in [GRLIB IP Core User's Manual](http://gaisler.com/products/grlib/grip.pdf).
--!
--! There you can find:
--! -# DMA Configuration registers description (Rx/Tx Descriptors tables and entries).
--! -# EDCL message format.
--! -# \c GRLIB itself includes C-example that configure MAC Rx/Tx queues
--! and start transmission of the 1500 Mbyte of data to define Bitrate in Mbps.
--!
--! We provide debugger functionality via Ethernet.
--! See @link dbg_link Debugger description @endlink page.
--!
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Ethernet specific declarations.
library rocketlib;
use rocketlib.grethpkg.all;
entity grethaxi is
generic(
xslvindex : integer := 0;
xmstindex : integer := 0;
xmstindex2 : integer := 1;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0135#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in nasti_master_in_type;
msto : out nasti_master_out_type;
mstcfg : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
slvi : in nasti_slave_in_type;
slvo : out nasti_slave_out_type;
slvcfg : out nasti_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end entity;
architecture arch_grethaxi of grethaxi is
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant xslvconfig : nasti_slave_config_type := (
xindex => xslvindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ETHMAC,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
constant xmstconfig : nasti_master_config_type := (
xindex => xmstindex,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_MAC_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xmstindex2,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_EDCL_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of std_logic_vector(15 downto 0);
type registers is record
bank_slv : nasti_slave_bank_type;
ctrl : eth_control_type;
end record;
signal r, rin : registers;
signal imac_cmd : eth_command_type;
signal omac_status : eth_mac_status_type;
signal omac_rdbgdata : std_logic_vector(31 downto 0);
signal omac_tmsto : eth_tx_ahb_in_type;
signal imac_tmsti : eth_tx_ahb_out_type;
signal omac_tmsto2 : eth_tx_ahb_in_type;
signal imac_tmsti2 : eth_tx_ahb_out_type;
signal omac_rmsto : eth_rx_ahb_in_type;
signal imac_rmsti : eth_rx_ahb_out_type;
begin
comb : process(r, ethi, slvi, omac_rdbgdata, omac_status, rst) is
variable v : registers;
variable vcmd : eth_command_type;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata32 : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable val : std_logic_vector(8*CFG_ALIGN_BYTES-1 downto 0);
begin
v := r;
vcmd := eth_command_none;
procedureAxi4(slvi, xslvconfig, r.bank_slv, v.bank_slv);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := r.bank_slv.raddr(n)(17 downto log2(CFG_ALIGN_BYTES));
val := (others => '0');
if (ramdebug = 0) or (raddr_reg(n)(15 downto 14) = "00") then
case raddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
val(13) := r.ctrl.ramdebugen;
end if;
if (edcl /= 0) then
val(31) := '1';
val(30 downto 28) := bufsize;
val(14) := r.ctrl.edcldis;
val(12) := r.ctrl.disableduplex;
end if;
if enable_mdint = 1 then
val(26) := '1';
val(10) := r.ctrl.pstatirqen;
end if;
if multicast = 1 then
val(25) := '1';
val(11) := r.ctrl.mcasten;
end if;
if rmii = 1 then
val(7) := omac_status.speed;
end if;
val(6) := omac_status.reset;
val(5) := r.ctrl.prom;
val(4) := omac_status.full_duplex;
val(3) := r.ctrl.rx_irqen;
val(2) := r.ctrl.tx_irqen;
val(1) := omac_status.rxen;
val(0) := omac_status.txen;
when "0001" => --status/int source reg
val(9) := not (omac_status.edcltx_idle or omac_status.edclrx_idle);
if enable_mdint = 1 then
val(8) := omac_status.phystat;
end if;
val(7) := omac_status.invaddr;
val(6) := omac_status.toosmall;
val(5) := omac_status.txahberr;
val(4) := omac_status.rxahberr;
val(3) := omac_status.tx_int;
val(2) := omac_status.rx_int;
val(1) := omac_status.tx_err;
val(0) := omac_status.rx_err;
when "0010" => --mac addr lsb
val := r.ctrl.mac_addr(31 downto 0);
when "0011" => --mac addr msb/mdio address
val(15 downto 0) := r.ctrl.mac_addr(47 downto 32);
when "0100" => --mdio ctrl/status
val(31 downto 16) := omac_status.mdio.cmd.data;
val(15 downto 11) := r.ctrl.mdio_phyadr;
val(10 downto 6) := omac_status.mdio.cmd.regadr;
val(3) := omac_status.mdio.busy;
val(2) := omac_status.mdio.linkfail;
val(1) := omac_status.mdio.cmd.read;
val(0) := omac_status.mdio.cmd.write;
when "0101" => --tx descriptor
val(31 downto 10) := r.ctrl.txdesc;
val(9 downto 3) := omac_status.txdsel;
when "0110" => --rx descriptor
val(31 downto 10) := r.ctrl.rxdesc;
val(9 downto 3) := omac_status.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
val := r.ctrl.edclip;
end if;
when "1000" =>
if multicast = 1 then
val := r.ctrl.hash(63 downto 32);
end if;
when "1001" =>
if multicast = 1 then
val := r.ctrl.hash(31 downto 0);
end if;
when "1010" =>
if edcl /= 0 then
val(15 downto 0) := r.ctrl.emacaddr(47 downto 32);
end if;
when "1011" =>
if edcl /= 0 then
val := r.ctrl.emacaddr(31 downto 0);
end if;
when others => null;
end case;
elsif raddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
end if;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := val;
end loop;
if slvi.w_valid = '1' and
r.bank_slv.wstate = wtrans and
r.bank_slv.wresp = NASTI_RESP_OKAY then
wdata := slvi.w_data;
wstrb := slvi.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := r.bank_slv.waddr(n)(17 downto 2);
wdata32 := wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
if wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n) /= "0000" then
if (ramdebug = 0) or (waddr_reg(n)(15 downto 14) = "00") then
case waddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
v.ctrl.ramdebugen := wdata32(13);
end if;
if edcl /= 0 then
v.ctrl.edcldis := wdata32(14);
v.ctrl.disableduplex := wdata32(12);
end if;
if multicast = 1 then
v.ctrl.mcasten := wdata32(11);
end if;
if enable_mdint = 1 then
v.ctrl.pstatirqen := wdata32(10);
end if;
if rmii = 1 then
vcmd.set_speed := wdata32(7);
vcmd.clr_speed := not wdata32(7);
end if;
vcmd.set_reset := wdata32(6);
vcmd.clr_reset := not wdata32(6);
v.ctrl.prom := wdata32(5);
vcmd.set_full_duplex := wdata32(4);
vcmd.clr_full_duplex := not wdata32(4);
v.ctrl.rx_irqen := wdata32(3);
v.ctrl.tx_irqen := wdata32(2);
vcmd.set_rxena := wdata32(1);
vcmd.clr_rxena := not wdata32(1);
vcmd.set_txena := wdata32(0);
vcmd.clr_txena := not wdata32(0);
when "0001" => --status/int source reg
if enable_mdint = 1 then
vcmd.clr_status_phystat := wdata32(8);
end if;
vcmd.clr_status_invaddr := wdata32(7);
vcmd.clr_status_toosmall := wdata32(6);
vcmd.clr_status_txahberr := wdata32(5);
vcmd.clr_status_rxahberr := wdata32(4);
vcmd.clr_status_tx_int := wdata32(3);
vcmd.clr_status_rx_int := wdata32(2);
vcmd.clr_status_tx_err := wdata32(1);
vcmd.clr_status_rx_err := wdata32(0);
when "0010" => --mac addr lsb
v.ctrl.mac_addr(31 downto 0) := wdata32(31 downto 0);
when "0011" => --mac addr msb
v.ctrl.mac_addr(47 downto 32) := wdata32(15 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
vcmd.mdio_cmd.valid := not omac_status.mdio.busy;
if omac_status.mdio.busy = '0' then
v.ctrl.mdio_phyadr := wdata32(15 downto 11);
end if;
vcmd.mdio_cmd.data := wdata32(31 downto 16);
vcmd.mdio_cmd.regadr := wdata32(10 downto 6);
vcmd.mdio_cmd.read := wdata32(1);
vcmd.mdio_cmd.write := wdata32(0);
end if;
when "0101" => --tx descriptor
vcmd.set_txdsel := '1';
vcmd.txdsel := wdata32(9 downto 3);
v.ctrl.txdesc := wdata32(31 downto 10);
when "0110" => --rx descriptor
vcmd.set_rxdsel := '1';
vcmd.rxdsel := wdata32(9 downto 3);
v.ctrl.rxdesc := wdata32(31 downto 10);
when "0111" => --edcl ip
if (edcl /= 0) then
v.ctrl.edclip := wdata32;
end if;
when "1000" => --hash msb
if multicast = 1 then
v.ctrl.hash(63 downto 32) := wdata32;
end if;
when "1001" => --hash lsb
if multicast = 1 then
v.ctrl.hash(31 downto 0) := wdata32;
end if;
when "1010" =>
if edcl /= 0 then
v.ctrl.emacaddr(47 downto 32) := wdata32(15 downto 0);
end if;
when "1011" =>
if edcl /= 0 then
v.ctrl.emacaddr(31 downto 0) := wdata32;
end if;
when others => null;
end case;
elsif waddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
end if;
end if;
end loop;
end if;
slvo <= functionAxi4Output(r.bank_slv, rdata);
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if rst = '0' then
v.bank_slv := NASTI_SLAVE_BANK_RESET;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
v.ctrl.pstatirqen := '0';
v.ctrl.mcasten := '0';
v.ctrl.ramdebugen := '0';
if edcl = 3 then
v.ctrl.edcldis := ethi.edcldisable;
elsif edcl /= 0 then
v.ctrl.edcldis := '0';
end if;
v.ctrl.disableduplex := '0';
if phyrstadr /= 32 then
v.ctrl.mdio_phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.ctrl.mdio_phyadr := ethi.phyrstaddr;
end if;
v.ctrl.mac_addr := (others => '0');
v.ctrl.txdesc := (others => '0');
v.ctrl.rxdesc := (others => '0');
v.ctrl.hash := (others => '0');
v.ctrl.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
v.ctrl.emacaddr := conv_std_logic_vector(macaddrh, 24) &
conv_std_logic_vector(macaddrl, 24);
if edcl > 1 then
v.ctrl.edclip(3 downto 0) := ethi.edcladdr;
v.ctrl.emacaddr(3 downto 0) := ethi.edcladdr;
end if;
end if;
rin <= v;
imac_cmd <= vcmd;
end process;
slvcfg <= xslvconfig;
mstcfg <= xmstconfig;
mstcfg2 <= xmstconfig2;
eth64 : grethc64 generic map (
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
) port map (
rst => rst,
clk => clk,
ctrli => r.ctrl,
cmdi => imac_cmd,
statuso => omac_status,
rdbgdatao => omac_rdbgdata,
--irq
irq => irq,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
tx_dv => ethi.tx_dv,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_en => ethi.rx_en,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
testrst => '0',
testen => '0',
testoen => '0',
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed,
tmsto => omac_tmsto,
tmsti => imac_tmsti,
tmsto2 => omac_tmsto2,
tmsti2 => imac_tmsti2,
rmsto => omac_rmsto,
rmsti => imac_rmsti
);
etho.tx_clk <= '0';
etho.gbit <= '0';
--! AXI Master interface providing DMA access
axi0 : eth_axi_mst generic map (
xindex => xmstindex
) port map (
rst,
clk,
msti,
msto,
omac_tmsto,
imac_tmsti,
omac_rmsto,
imac_rmsti
);
edclmst_on : if edclsepahbg = 1 generate
axi1 : eth_axi_mst generic map (
xindex => xmstindex2
) port map (
rst,
clk,
msti,
msto2,
omac_tmsto2,
imac_tmsti2,
eth_rx_in_none,
open
);
end generate;
edclmst_off : if edclsepahbg = 0 generate
msto2 <= nasti_master_out_none;
imac_tmsti2.grant <= '0';
imac_tmsti2.data <= (others => '0');
imac_tmsti2.ready <= '0';
imac_tmsti2.error <= '0';
imac_tmsti2.retry <= '0';
end generate;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
entity repro2 is
end entity;
architecture tb of repro2 is
type tb_cfg_t is record
value : string;
end record tb_cfg_t;
function get_msg return string is
begin
return "goodbye";
end get_msg;
constant tb_cfg: tb_cfg_t := ( value => get_msg );
begin
assert tb_cfg.value > "a";
end tb;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY freqDividerTb IS
END freqDividerTb;
ARCHITECTURE behavior OF freqDividerTb IS
COMPONENT freqDivider
Generic (
divisor : integer
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enable : std_logic := '1';
--Outputs
signal clkDividedBy2 : std_logic;
signal clkDividedBy3 : std_logic;
signal clkDividedBy4 : std_logic;
signal clkDividedBy5 : std_logic;
signal clkDividedBy6 : std_logic;
signal clkDividedBy7 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
clk <= not clk after clk_period;
divBy2: freqDivider
GENERIC MAP (divisor => 2)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy2);
divBy3: freqDivider
GENERIC MAP (divisor => 3)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy3);
divBy4: freqDivider
GENERIC MAP (divisor => 4)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy4);
divBy5: freqDivider
GENERIC MAP (divisor => 5)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy5);
divBy6: freqDivider
GENERIC MAP (divisor => 6)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy6);
divBy7: freqDivider
GENERIC MAP (divisor => 7)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy7);
END;
|
-- Descp. decodes the 3 bit color to the 4 bit needed for the segment_decoder
--
-- entity name: g05_color_decoder
--
-- Version 1.0
-- Author: Felix Dube; felix.dube@mail.mcgill.ca & Auguste Lalande; auguste.lalande@mail.mcgill.ca
-- Date: October 29, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_color_decoder is
port (
color : in std_logic_vector(2 downto 0);
color_code : out std_logic_vector(3 downto 0)
);
end g05_color_decoder;
architecture behavior of g05_color_decoder is
begin
with color select color_code <=
"1010" when "000",
"1011" when "001",
"1100" when "010",
"1101" when "011",
"1110" when "100",
"1111" when "101",
"1010" when others;
end behavior; |
--Package declaration for the above program
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package test_pkg is
function reverse_any_vector (a : in std_logic_vector) return std_logic_vector;
end test_pkg; --end of package.
package body test_pkg is --start of package body
--definition of function
function reverse_any_vector (a : in std_logic_vector)
return std_logic_vector is
variable result : std_logic_vector(a'range);
alias aa : std_logic_vector(a'reverse_range) is a;
begin
for i in aa'range loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
--end function
end test_pkg; --end of the package body
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
entity cut_wrapper_static_all is
port (
clk : in std_logic;
testVector : in std_logic_vector(69 downto 0);
resultVector : out std_logic_vector(40 downto 0));
end entity cut_wrapper_static_all;
architecture behav of cut_wrapper_static_all is
component circuit_under_test is
port (
clk : in std_logic;
rst : in std_logic;
testVector : in std_logic_vector(69 downto 0);
resultVector : out std_logic_vector(40 downto 0);
injectionvector : in std_logic_vector(620 downto 0));
end component circuit_under_test;
signal injectionvector : std_logic_vector(620 downto 0);
signal injectionVector_rev_1 : std_logic_vector(300-1 downto 0);
signal injectionVector_rev_2 : std_logic_vector(321-1 downto 0);
begin -- architecture behav
-- all
--injectionVector_rev_1 <= (others => '1');
--injectionVector_rev_2 <= (others => '1');
-- 30 dB
injectionVector_rev_1 <= ('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','0','1','1','1','1','0','1','1','1','1','0','1','1','1','1','1','0','1','1','1','1','1','1','1','0','0','0','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','0','1','1','1');
injectionVector_rev_2 <= ('0','1','1','0','0','0','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','1','1','1','1','1','1','1','1','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
-- 40 dB
--injectionVector_rev_1 <= ('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','0','0','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1');
--injectionVector_rev_2 <=('0','0','0','0','1','1','1','1','1','1','0','0','1','0','0','0','0','0','0','0','0','1','0','0','1','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','1','1','1','1','1','1','1','1','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
--50 dB
--injectionVector_rev_1 <= ('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','1','1','1','1');
--injectionVector_rev_2 <= ('0','0','0','0','0','0','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','1','1','1','1','1','1','1','1','0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0');
injectionVector <= reverse_any_vector(injectionVector_rev_2) & reverse_any_vector(injectionVector_rev_1);
circuit_under_test_1 : circuit_under_test
port map (
clk => clk,
rst => '0',
testVector => testVector,
resultVector => resultVector,
injectionvector => injectionvector);
end architecture behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
--------------------------------------------------
-- not in book
library ieee; use ieee.numeric_bit.all;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "+"(signed(bv1), signed(bv2)) );
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "-"(signed(bv)) );
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
--------------------------------------------------
-- not in book
library ieee; use ieee.numeric_bit.all;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "+"(signed(bv1), signed(bv2)) );
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "-"(signed(bv)) );
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
--------------------------------------------------
-- not in book
library ieee; use ieee.numeric_bit.all;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "+"(signed(bv1), signed(bv2)) );
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "-"(signed(bv)) );
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
|
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
|
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
|
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
|
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01614ent IS
END c08s12b00x00p01n01i01614ent;
ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
--
-- Nested procedures to test return statement.
--
procedure two ( variable val : inout integer ) is
procedure one ( variable val : out integer ) is
begin
val := 1;
return;
val := 2; -- should never get here
end one;
begin
one(val);
val := val * 2;
return;
val := val * 2; -- should never get here
end two;
BEGIN
TESTING : PROCESS
variable v1 : integer;
BEGIN
two (v1);
assert NOT( v1=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01614"
severity NOTE;
assert ( v1=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p01n01i01614arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01614ent IS
END c08s12b00x00p01n01i01614ent;
ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
--
-- Nested procedures to test return statement.
--
procedure two ( variable val : inout integer ) is
procedure one ( variable val : out integer ) is
begin
val := 1;
return;
val := 2; -- should never get here
end one;
begin
one(val);
val := val * 2;
return;
val := val * 2; -- should never get here
end two;
BEGIN
TESTING : PROCESS
variable v1 : integer;
BEGIN
two (v1);
assert NOT( v1=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01614"
severity NOTE;
assert ( v1=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p01n01i01614arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01614ent IS
END c08s12b00x00p01n01i01614ent;
ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
--
-- Nested procedures to test return statement.
--
procedure two ( variable val : inout integer ) is
procedure one ( variable val : out integer ) is
begin
val := 1;
return;
val := 2; -- should never get here
end one;
begin
one(val);
val := val * 2;
return;
val := val * 2; -- should never get here
end two;
BEGIN
TESTING : PROCESS
variable v1 : integer;
BEGIN
two (v1);
assert NOT( v1=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01614"
severity NOTE;
assert ( v1=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p01n01i01614arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RESPONSE_QUEUE_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end PACKAGE body fifo_pkg;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.2 2005/10/06 11:16:05 wig Exp $
-- $Date: 2005/10/06 11:16:05 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.2 2005/10/06 11:16:05 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_0_0_gi : in std_ulogic; -- __W_SINGLEBITBUS
p_mix_iosel_disp_gi : in std_ulogic_vector(3 downto 0);
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_0, CTS_L_0: out std_logic;
DRTS_L_0, DCTS_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_1, CTS_L_1: out std_logic;
DRTS_L_1, DCTS_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_2, CTS_L_2: out std_logic;
DRTS_L_2, DCTS_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_3, CTS_L_3: out std_logic;
DRTS_L_3, DCTS_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
-- Declaring router component
component router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size : integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(4 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component SHMU is
generic (
router_fault_info_width: integer := 5;
network_size: integer := 2
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet_E_0, healthy_packet_E_0, faulty_packet_S_0, healthy_packet_S_0, faulty_packet_L_0, healthy_packet_L_0: in std_logic;
faulty_packet_W_1, healthy_packet_W_1, faulty_packet_S_1, healthy_packet_S_1, faulty_packet_L_1, healthy_packet_L_1: in std_logic;
faulty_packet_E_2, healthy_packet_E_2, faulty_packet_N_2, healthy_packet_N_2, faulty_packet_L_2, healthy_packet_L_2: in std_logic;
faulty_packet_W_3, healthy_packet_W_3, faulty_packet_N_3, healthy_packet_N_3, faulty_packet_L_3, healthy_packet_L_3: in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal DCTS_N_0, DCTS_E_0, DCTS_w_0, DCTS_S_0: std_logic;
signal DCTS_N_1, DCTS_E_1, DCTS_w_1, DCTS_S_1: std_logic;
signal DCTS_N_2, DCTS_E_2, DCTS_w_2, DCTS_S_2: std_logic;
signal DCTS_N_3, DCTS_E_3, DCTS_w_3, DCTS_S_3: std_logic;
signal DRTS_N_0, DRTS_E_0, DRTS_W_0, DRTS_S_0: std_logic;
signal DRTS_N_1, DRTS_E_1, DRTS_W_1, DRTS_S_1: std_logic;
signal DRTS_N_2, DRTS_E_2, DRTS_W_2, DRTS_S_2: std_logic;
signal DRTS_N_3, DRTS_E_3, DRTS_W_3, DRTS_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal CTS_N_0, CTS_E_0, CTS_w_0, CTS_S_0: std_logic;
signal CTS_N_1, CTS_E_1, CTS_w_1, CTS_S_1: std_logic;
signal CTS_N_2, CTS_E_2, CTS_w_2, CTS_S_2: std_logic;
signal CTS_N_3, CTS_E_3, CTS_w_3, CTS_S_3: std_logic;
signal RTS_N_0, RTS_E_0, RTS_W_0, RTS_S_0: std_logic;
signal RTS_N_1, RTS_E_1, RTS_W_1, RTS_S_1: std_logic;
signal RTS_N_2, RTS_E_2, RTS_W_2, RTS_S_2: std_logic;
signal RTS_N_3, RTS_E_3, RTS_W_3, RTS_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal faulty_packet_N_0, faulty_packet_E_0, faulty_packet_W_0, faulty_packet_S_0, faulty_packet_L_0: std_logic;
signal faulty_packet_N_1, faulty_packet_E_1, faulty_packet_W_1, faulty_packet_S_1, faulty_packet_L_1: std_logic;
signal faulty_packet_N_2, faulty_packet_E_2, faulty_packet_W_2, faulty_packet_S_2, faulty_packet_L_2: std_logic;
signal faulty_packet_N_3, faulty_packet_E_3, faulty_packet_W_3, faulty_packet_S_3, faulty_packet_L_3: std_logic;
signal healthy_packet_N_0, healthy_packet_E_0, healthy_packet_W_0, healthy_packet_S_0, healthy_packet_L_0: std_logic;
signal healthy_packet_N_1, healthy_packet_E_1, healthy_packet_W_1, healthy_packet_S_1, healthy_packet_L_1: std_logic;
signal healthy_packet_N_2, healthy_packet_E_2, healthy_packet_W_2, healthy_packet_S_2, healthy_packet_L_2: std_logic;
signal healthy_packet_N_3, healthy_packet_E_3, healthy_packet_W_3, healthy_packet_S_3, healthy_packet_L_3: std_logic;
begin
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
SHMU_unit: SHMU
generic map(router_fault_info_width => 5,network_size => 2)
port map( reset => reset,
clk => clk,
faulty_packet_E_0 =>faulty_packet_E_0 , healthy_packet_E_0=>healthy_packet_E_0, faulty_packet_S_0 => faulty_packet_S_0, healthy_packet_S_0 => healthy_packet_S_0, faulty_packet_L_0 => faulty_packet_L_0, healthy_packet_L_0 => healthy_packet_L_0,
faulty_packet_W_1 =>faulty_packet_W_1 , healthy_packet_W_1=>healthy_packet_W_1, faulty_packet_S_1 => faulty_packet_S_1, healthy_packet_S_1 => healthy_packet_S_1, faulty_packet_L_1 => faulty_packet_L_1, healthy_packet_L_1 => healthy_packet_L_1,
faulty_packet_E_2 =>faulty_packet_E_2 , healthy_packet_E_2=>healthy_packet_E_2, faulty_packet_N_2 => faulty_packet_N_2, healthy_packet_N_2 => healthy_packet_N_2, faulty_packet_L_2 => faulty_packet_L_2, healthy_packet_L_2 => healthy_packet_L_2,
faulty_packet_W_3 =>faulty_packet_W_3 , healthy_packet_W_3=>healthy_packet_W_3, faulty_packet_N_3 => faulty_packet_N_3, healthy_packet_N_3 => healthy_packet_N_3, faulty_packet_L_3 => faulty_packet_L_3, healthy_packet_L_3 => healthy_packet_L_3
);
-- instantiating the routers
R_0: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>0, Rxy_rst => 60, Cx_rst => 10, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_0, DCTS_E_0, DCTS_W_0, DCTS_S_0, DCTS_L_0,
DRTS_N_0, DRTS_E_0, DRTS_W_0, DRTS_S_0, DRTS_L_0,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
RTS_N_0, RTS_E_0, RTS_W_0, RTS_S_0, RTS_L_0,
CTS_N_0, CTS_E_0, CTS_w_0, CTS_S_0, CTS_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
faulty_packet_N_0, faulty_packet_E_0, faulty_packet_W_0, faulty_packet_S_0, faulty_packet_L_0,
healthy_packet_N_0, healthy_packet_E_0, healthy_packet_W_0, healthy_packet_S_0, healthy_packet_L_0);
R_1: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>1, Rxy_rst => 60, Cx_rst => 12, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_1, DCTS_E_1, DCTS_W_1, DCTS_S_1, DCTS_L_1,
DRTS_N_1, DRTS_E_1, DRTS_W_1, DRTS_S_1, DRTS_L_1,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
RTS_N_1, RTS_E_1, RTS_W_1, RTS_S_1, RTS_L_1,
CTS_N_1, CTS_E_1, CTS_w_1, CTS_S_1, CTS_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
faulty_packet_N_1, faulty_packet_E_1, faulty_packet_W_1, faulty_packet_S_1, faulty_packet_L_1,
healthy_packet_N_1, healthy_packet_E_1, healthy_packet_W_1, healthy_packet_S_1, healthy_packet_L_1);
R_2: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>2, Rxy_rst => 60, Cx_rst => 3, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_2, DCTS_E_2, DCTS_W_2, DCTS_S_2, DCTS_L_2,
DRTS_N_2, DRTS_E_2, DRTS_W_2, DRTS_S_2, DRTS_L_2,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
RTS_N_2, RTS_E_2, RTS_W_2, RTS_S_2, RTS_L_2,
CTS_N_2, CTS_E_2, CTS_w_2, CTS_S_2, CTS_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
faulty_packet_N_2, faulty_packet_E_2, faulty_packet_W_2, faulty_packet_S_2, faulty_packet_L_2,
healthy_packet_N_2, healthy_packet_E_2, healthy_packet_W_2, healthy_packet_S_2, healthy_packet_L_2);
R_3: router_parity generic map (DATA_WIDTH => DATA_WIDTH, current_address=>3, Rxy_rst => 60, Cx_rst => 5, NoC_size=>2)
PORT MAP (reset, clk,
DCTS_N_3, DCTS_E_3, DCTS_W_3, DCTS_S_3, DCTS_L_3,
DRTS_N_3, DRTS_E_3, DRTS_W_3, DRTS_S_3, DRTS_L_3,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
RTS_N_3, RTS_E_3, RTS_W_3, RTS_S_3, RTS_L_3,
CTS_N_3, CTS_E_3, CTS_w_3, CTS_S_3, CTS_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
faulty_packet_N_3, faulty_packet_E_3, faulty_packet_W_3, faulty_packet_S_3, faulty_packet_L_3,
healthy_packet_N_3, healthy_packet_E_3, healthy_packet_W_3, healthy_packet_S_3, healthy_packet_L_3);
-- instantiating the Fault fault_injector
-- vertical FIs
FI_0_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_0,
address => FI_Add_0_2,
sta_0 => sta0_0_2,
sta_1 => sta1_0_2,
data_out => RX_N_2
);
FI_2_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_2,
address => FI_Add_2_0,
sta_0 => sta0_2_0,
sta_1 => sta1_2_0,
data_out => RX_S_0
);
FI_1_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_1,
address => FI_Add_1_3,
sta_0 => sta0_1_3,
sta_1 => sta1_1_3,
data_out => RX_N_3
);
FI_3_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_3,
address => FI_Add_3_1,
sta_0 => sta0_3_1,
sta_1 => sta1_3_1,
data_out => RX_S_1
);
-- horizontal FIs
FI_0_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_0,
address => FI_Add_0_1,
sta_0 => sta0_0_1,
sta_1 => sta1_0_1,
data_out => RX_W_1
);
FI_1_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_1,
address => FI_Add_1_0,
sta_0 => sta0_1_0,
sta_1 => sta1_1_0,
data_out => RX_E_0
);
FI_2_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_2,
address => FI_Add_2_3,
sta_0 => sta0_2_3,
sta_1 => sta1_2_3,
data_out => RX_W_3
);
FI_3_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_3,
address => FI_Add_3_2,
sta_0 => sta0_3_2,
sta_1 => sta1_3_2,
data_out => RX_E_2
);
---------------------------------------------------------------
-- binding the routers together
-- vertical handshakes
-- connecting router: 0 to router: 2 and vice versa
DRTS_N_2 <= RTS_S_0;
DCTS_S_0 <= CTS_N_2;
DRTS_S_0 <= RTS_N_2;
DCTS_N_2 <= CTS_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
DRTS_N_3 <= RTS_S_1;
DCTS_S_1 <= CTS_N_3;
DRTS_S_1 <= RTS_N_3;
DCTS_N_3 <= CTS_S_1;
-------------------
-- horizontal handshakes
-- connecting router: 0 to router: 1 and vice versa
DRTS_E_0 <= RTS_W_1;
DCTS_W_1 <= CTS_E_0;
DRTS_W_1 <= RTS_E_0;
DCTS_E_0 <= CTS_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
DRTS_E_2 <= RTS_W_3;
DCTS_W_3 <= CTS_E_2;
DRTS_W_3 <= RTS_E_2;
DCTS_E_2 <= CTS_W_3;
-------------------
end;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- WISHBONE SLAVE (256 registers)
-- generated with sdk-java for testing purposes
--===========================================================================--
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package package_wbs256 is
type reg_wbs256_t is record
reg0 : std_logic_vector(WB_DW-1 downto 0);
reg1 : std_logic_vector(WB_DW-1 downto 0);
reg2 : std_logic_vector(WB_DW-1 downto 0);
reg3 : std_logic_vector(WB_DW-1 downto 0);
reg4 : std_logic_vector(WB_DW-1 downto 0);
reg5 : std_logic_vector(WB_DW-1 downto 0);
reg6 : std_logic_vector(WB_DW-1 downto 0);
reg7 : std_logic_vector(WB_DW-1 downto 0);
reg8 : std_logic_vector(WB_DW-1 downto 0);
reg9 : std_logic_vector(WB_DW-1 downto 0);
reg10 : std_logic_vector(WB_DW-1 downto 0);
reg11 : std_logic_vector(WB_DW-1 downto 0);
reg12 : std_logic_vector(WB_DW-1 downto 0);
reg13 : std_logic_vector(WB_DW-1 downto 0);
reg14 : std_logic_vector(WB_DW-1 downto 0);
reg15 : std_logic_vector(WB_DW-1 downto 0);
reg16 : std_logic_vector(WB_DW-1 downto 0);
reg17 : std_logic_vector(WB_DW-1 downto 0);
reg18 : std_logic_vector(WB_DW-1 downto 0);
reg19 : std_logic_vector(WB_DW-1 downto 0);
reg20 : std_logic_vector(WB_DW-1 downto 0);
reg21 : std_logic_vector(WB_DW-1 downto 0);
reg22 : std_logic_vector(WB_DW-1 downto 0);
reg23 : std_logic_vector(WB_DW-1 downto 0);
reg24 : std_logic_vector(WB_DW-1 downto 0);
reg25 : std_logic_vector(WB_DW-1 downto 0);
reg26 : std_logic_vector(WB_DW-1 downto 0);
reg27 : std_logic_vector(WB_DW-1 downto 0);
reg28 : std_logic_vector(WB_DW-1 downto 0);
reg29 : std_logic_vector(WB_DW-1 downto 0);
reg30 : std_logic_vector(WB_DW-1 downto 0);
reg31 : std_logic_vector(WB_DW-1 downto 0);
reg32 : std_logic_vector(WB_DW-1 downto 0);
reg33 : std_logic_vector(WB_DW-1 downto 0);
reg34 : std_logic_vector(WB_DW-1 downto 0);
reg35 : std_logic_vector(WB_DW-1 downto 0);
reg36 : std_logic_vector(WB_DW-1 downto 0);
reg37 : std_logic_vector(WB_DW-1 downto 0);
reg38 : std_logic_vector(WB_DW-1 downto 0);
reg39 : std_logic_vector(WB_DW-1 downto 0);
reg40 : std_logic_vector(WB_DW-1 downto 0);
reg41 : std_logic_vector(WB_DW-1 downto 0);
reg42 : std_logic_vector(WB_DW-1 downto 0);
reg43 : std_logic_vector(WB_DW-1 downto 0);
reg44 : std_logic_vector(WB_DW-1 downto 0);
reg45 : std_logic_vector(WB_DW-1 downto 0);
reg46 : std_logic_vector(WB_DW-1 downto 0);
reg47 : std_logic_vector(WB_DW-1 downto 0);
reg48 : std_logic_vector(WB_DW-1 downto 0);
reg49 : std_logic_vector(WB_DW-1 downto 0);
reg50 : std_logic_vector(WB_DW-1 downto 0);
reg51 : std_logic_vector(WB_DW-1 downto 0);
reg52 : std_logic_vector(WB_DW-1 downto 0);
reg53 : std_logic_vector(WB_DW-1 downto 0);
reg54 : std_logic_vector(WB_DW-1 downto 0);
reg55 : std_logic_vector(WB_DW-1 downto 0);
reg56 : std_logic_vector(WB_DW-1 downto 0);
reg57 : std_logic_vector(WB_DW-1 downto 0);
reg58 : std_logic_vector(WB_DW-1 downto 0);
reg59 : std_logic_vector(WB_DW-1 downto 0);
reg60 : std_logic_vector(WB_DW-1 downto 0);
reg61 : std_logic_vector(WB_DW-1 downto 0);
reg62 : std_logic_vector(WB_DW-1 downto 0);
reg63 : std_logic_vector(WB_DW-1 downto 0);
reg64 : std_logic_vector(WB_DW-1 downto 0);
reg65 : std_logic_vector(WB_DW-1 downto 0);
reg66 : std_logic_vector(WB_DW-1 downto 0);
reg67 : std_logic_vector(WB_DW-1 downto 0);
reg68 : std_logic_vector(WB_DW-1 downto 0);
reg69 : std_logic_vector(WB_DW-1 downto 0);
reg70 : std_logic_vector(WB_DW-1 downto 0);
reg71 : std_logic_vector(WB_DW-1 downto 0);
reg72 : std_logic_vector(WB_DW-1 downto 0);
reg73 : std_logic_vector(WB_DW-1 downto 0);
reg74 : std_logic_vector(WB_DW-1 downto 0);
reg75 : std_logic_vector(WB_DW-1 downto 0);
reg76 : std_logic_vector(WB_DW-1 downto 0);
reg77 : std_logic_vector(WB_DW-1 downto 0);
reg78 : std_logic_vector(WB_DW-1 downto 0);
reg79 : std_logic_vector(WB_DW-1 downto 0);
reg80 : std_logic_vector(WB_DW-1 downto 0);
reg81 : std_logic_vector(WB_DW-1 downto 0);
reg82 : std_logic_vector(WB_DW-1 downto 0);
reg83 : std_logic_vector(WB_DW-1 downto 0);
reg84 : std_logic_vector(WB_DW-1 downto 0);
reg85 : std_logic_vector(WB_DW-1 downto 0);
reg86 : std_logic_vector(WB_DW-1 downto 0);
reg87 : std_logic_vector(WB_DW-1 downto 0);
reg88 : std_logic_vector(WB_DW-1 downto 0);
reg89 : std_logic_vector(WB_DW-1 downto 0);
reg90 : std_logic_vector(WB_DW-1 downto 0);
reg91 : std_logic_vector(WB_DW-1 downto 0);
reg92 : std_logic_vector(WB_DW-1 downto 0);
reg93 : std_logic_vector(WB_DW-1 downto 0);
reg94 : std_logic_vector(WB_DW-1 downto 0);
reg95 : std_logic_vector(WB_DW-1 downto 0);
reg96 : std_logic_vector(WB_DW-1 downto 0);
reg97 : std_logic_vector(WB_DW-1 downto 0);
reg98 : std_logic_vector(WB_DW-1 downto 0);
reg99 : std_logic_vector(WB_DW-1 downto 0);
reg100 : std_logic_vector(WB_DW-1 downto 0);
reg101 : std_logic_vector(WB_DW-1 downto 0);
reg102 : std_logic_vector(WB_DW-1 downto 0);
reg103 : std_logic_vector(WB_DW-1 downto 0);
reg104 : std_logic_vector(WB_DW-1 downto 0);
reg105 : std_logic_vector(WB_DW-1 downto 0);
reg106 : std_logic_vector(WB_DW-1 downto 0);
reg107 : std_logic_vector(WB_DW-1 downto 0);
reg108 : std_logic_vector(WB_DW-1 downto 0);
reg109 : std_logic_vector(WB_DW-1 downto 0);
reg110 : std_logic_vector(WB_DW-1 downto 0);
reg111 : std_logic_vector(WB_DW-1 downto 0);
reg112 : std_logic_vector(WB_DW-1 downto 0);
reg113 : std_logic_vector(WB_DW-1 downto 0);
reg114 : std_logic_vector(WB_DW-1 downto 0);
reg115 : std_logic_vector(WB_DW-1 downto 0);
reg116 : std_logic_vector(WB_DW-1 downto 0);
reg117 : std_logic_vector(WB_DW-1 downto 0);
reg118 : std_logic_vector(WB_DW-1 downto 0);
reg119 : std_logic_vector(WB_DW-1 downto 0);
reg120 : std_logic_vector(WB_DW-1 downto 0);
reg121 : std_logic_vector(WB_DW-1 downto 0);
reg122 : std_logic_vector(WB_DW-1 downto 0);
reg123 : std_logic_vector(WB_DW-1 downto 0);
reg124 : std_logic_vector(WB_DW-1 downto 0);
reg125 : std_logic_vector(WB_DW-1 downto 0);
reg126 : std_logic_vector(WB_DW-1 downto 0);
reg127 : std_logic_vector(WB_DW-1 downto 0);
reg128 : std_logic_vector(WB_DW-1 downto 0);
reg129 : std_logic_vector(WB_DW-1 downto 0);
reg130 : std_logic_vector(WB_DW-1 downto 0);
reg131 : std_logic_vector(WB_DW-1 downto 0);
reg132 : std_logic_vector(WB_DW-1 downto 0);
reg133 : std_logic_vector(WB_DW-1 downto 0);
reg134 : std_logic_vector(WB_DW-1 downto 0);
reg135 : std_logic_vector(WB_DW-1 downto 0);
reg136 : std_logic_vector(WB_DW-1 downto 0);
reg137 : std_logic_vector(WB_DW-1 downto 0);
reg138 : std_logic_vector(WB_DW-1 downto 0);
reg139 : std_logic_vector(WB_DW-1 downto 0);
reg140 : std_logic_vector(WB_DW-1 downto 0);
reg141 : std_logic_vector(WB_DW-1 downto 0);
reg142 : std_logic_vector(WB_DW-1 downto 0);
reg143 : std_logic_vector(WB_DW-1 downto 0);
reg144 : std_logic_vector(WB_DW-1 downto 0);
reg145 : std_logic_vector(WB_DW-1 downto 0);
reg146 : std_logic_vector(WB_DW-1 downto 0);
reg147 : std_logic_vector(WB_DW-1 downto 0);
reg148 : std_logic_vector(WB_DW-1 downto 0);
reg149 : std_logic_vector(WB_DW-1 downto 0);
reg150 : std_logic_vector(WB_DW-1 downto 0);
reg151 : std_logic_vector(WB_DW-1 downto 0);
reg152 : std_logic_vector(WB_DW-1 downto 0);
reg153 : std_logic_vector(WB_DW-1 downto 0);
reg154 : std_logic_vector(WB_DW-1 downto 0);
reg155 : std_logic_vector(WB_DW-1 downto 0);
reg156 : std_logic_vector(WB_DW-1 downto 0);
reg157 : std_logic_vector(WB_DW-1 downto 0);
reg158 : std_logic_vector(WB_DW-1 downto 0);
reg159 : std_logic_vector(WB_DW-1 downto 0);
reg160 : std_logic_vector(WB_DW-1 downto 0);
reg161 : std_logic_vector(WB_DW-1 downto 0);
reg162 : std_logic_vector(WB_DW-1 downto 0);
reg163 : std_logic_vector(WB_DW-1 downto 0);
reg164 : std_logic_vector(WB_DW-1 downto 0);
reg165 : std_logic_vector(WB_DW-1 downto 0);
reg166 : std_logic_vector(WB_DW-1 downto 0);
reg167 : std_logic_vector(WB_DW-1 downto 0);
reg168 : std_logic_vector(WB_DW-1 downto 0);
reg169 : std_logic_vector(WB_DW-1 downto 0);
reg170 : std_logic_vector(WB_DW-1 downto 0);
reg171 : std_logic_vector(WB_DW-1 downto 0);
reg172 : std_logic_vector(WB_DW-1 downto 0);
reg173 : std_logic_vector(WB_DW-1 downto 0);
reg174 : std_logic_vector(WB_DW-1 downto 0);
reg175 : std_logic_vector(WB_DW-1 downto 0);
reg176 : std_logic_vector(WB_DW-1 downto 0);
reg177 : std_logic_vector(WB_DW-1 downto 0);
reg178 : std_logic_vector(WB_DW-1 downto 0);
reg179 : std_logic_vector(WB_DW-1 downto 0);
reg180 : std_logic_vector(WB_DW-1 downto 0);
reg181 : std_logic_vector(WB_DW-1 downto 0);
reg182 : std_logic_vector(WB_DW-1 downto 0);
reg183 : std_logic_vector(WB_DW-1 downto 0);
reg184 : std_logic_vector(WB_DW-1 downto 0);
reg185 : std_logic_vector(WB_DW-1 downto 0);
reg186 : std_logic_vector(WB_DW-1 downto 0);
reg187 : std_logic_vector(WB_DW-1 downto 0);
reg188 : std_logic_vector(WB_DW-1 downto 0);
reg189 : std_logic_vector(WB_DW-1 downto 0);
reg190 : std_logic_vector(WB_DW-1 downto 0);
reg191 : std_logic_vector(WB_DW-1 downto 0);
reg192 : std_logic_vector(WB_DW-1 downto 0);
reg193 : std_logic_vector(WB_DW-1 downto 0);
reg194 : std_logic_vector(WB_DW-1 downto 0);
reg195 : std_logic_vector(WB_DW-1 downto 0);
reg196 : std_logic_vector(WB_DW-1 downto 0);
reg197 : std_logic_vector(WB_DW-1 downto 0);
reg198 : std_logic_vector(WB_DW-1 downto 0);
reg199 : std_logic_vector(WB_DW-1 downto 0);
reg200 : std_logic_vector(WB_DW-1 downto 0);
reg201 : std_logic_vector(WB_DW-1 downto 0);
reg202 : std_logic_vector(WB_DW-1 downto 0);
reg203 : std_logic_vector(WB_DW-1 downto 0);
reg204 : std_logic_vector(WB_DW-1 downto 0);
reg205 : std_logic_vector(WB_DW-1 downto 0);
reg206 : std_logic_vector(WB_DW-1 downto 0);
reg207 : std_logic_vector(WB_DW-1 downto 0);
reg208 : std_logic_vector(WB_DW-1 downto 0);
reg209 : std_logic_vector(WB_DW-1 downto 0);
reg210 : std_logic_vector(WB_DW-1 downto 0);
reg211 : std_logic_vector(WB_DW-1 downto 0);
reg212 : std_logic_vector(WB_DW-1 downto 0);
reg213 : std_logic_vector(WB_DW-1 downto 0);
reg214 : std_logic_vector(WB_DW-1 downto 0);
reg215 : std_logic_vector(WB_DW-1 downto 0);
reg216 : std_logic_vector(WB_DW-1 downto 0);
reg217 : std_logic_vector(WB_DW-1 downto 0);
reg218 : std_logic_vector(WB_DW-1 downto 0);
reg219 : std_logic_vector(WB_DW-1 downto 0);
reg220 : std_logic_vector(WB_DW-1 downto 0);
reg221 : std_logic_vector(WB_DW-1 downto 0);
reg222 : std_logic_vector(WB_DW-1 downto 0);
reg223 : std_logic_vector(WB_DW-1 downto 0);
reg224 : std_logic_vector(WB_DW-1 downto 0);
reg225 : std_logic_vector(WB_DW-1 downto 0);
reg226 : std_logic_vector(WB_DW-1 downto 0);
reg227 : std_logic_vector(WB_DW-1 downto 0);
reg228 : std_logic_vector(WB_DW-1 downto 0);
reg229 : std_logic_vector(WB_DW-1 downto 0);
reg230 : std_logic_vector(WB_DW-1 downto 0);
reg231 : std_logic_vector(WB_DW-1 downto 0);
reg232 : std_logic_vector(WB_DW-1 downto 0);
reg233 : std_logic_vector(WB_DW-1 downto 0);
reg234 : std_logic_vector(WB_DW-1 downto 0);
reg235 : std_logic_vector(WB_DW-1 downto 0);
reg236 : std_logic_vector(WB_DW-1 downto 0);
reg237 : std_logic_vector(WB_DW-1 downto 0);
reg238 : std_logic_vector(WB_DW-1 downto 0);
reg239 : std_logic_vector(WB_DW-1 downto 0);
reg240 : std_logic_vector(WB_DW-1 downto 0);
reg241 : std_logic_vector(WB_DW-1 downto 0);
reg242 : std_logic_vector(WB_DW-1 downto 0);
reg243 : std_logic_vector(WB_DW-1 downto 0);
reg244 : std_logic_vector(WB_DW-1 downto 0);
reg245 : std_logic_vector(WB_DW-1 downto 0);
reg246 : std_logic_vector(WB_DW-1 downto 0);
reg247 : std_logic_vector(WB_DW-1 downto 0);
reg248 : std_logic_vector(WB_DW-1 downto 0);
reg249 : std_logic_vector(WB_DW-1 downto 0);
reg250 : std_logic_vector(WB_DW-1 downto 0);
reg251 : std_logic_vector(WB_DW-1 downto 0);
reg252 : std_logic_vector(WB_DW-1 downto 0);
reg253 : std_logic_vector(WB_DW-1 downto 0);
reg254 : std_logic_vector(WB_DW-1 downto 0);
reg255 : std_logic_vector(WB_DW-1 downto 0);
end record;
component wbs256
port (
-- register outputs
reg0_out : out std_logic_vector(WB_DW-1 downto 0);
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0);
reg3_out : out std_logic_vector(WB_DW-1 downto 0);
reg4_out : out std_logic_vector(WB_DW-1 downto 0);
reg5_out : out std_logic_vector(WB_DW-1 downto 0);
reg6_out : out std_logic_vector(WB_DW-1 downto 0);
reg7_out : out std_logic_vector(WB_DW-1 downto 0);
reg8_out : out std_logic_vector(WB_DW-1 downto 0);
reg9_out : out std_logic_vector(WB_DW-1 downto 0);
reg10_out : out std_logic_vector(WB_DW-1 downto 0);
reg11_out : out std_logic_vector(WB_DW-1 downto 0);
reg12_out : out std_logic_vector(WB_DW-1 downto 0);
reg13_out : out std_logic_vector(WB_DW-1 downto 0);
reg14_out : out std_logic_vector(WB_DW-1 downto 0);
reg15_out : out std_logic_vector(WB_DW-1 downto 0);
reg16_out : out std_logic_vector(WB_DW-1 downto 0);
reg17_out : out std_logic_vector(WB_DW-1 downto 0);
reg18_out : out std_logic_vector(WB_DW-1 downto 0);
reg19_out : out std_logic_vector(WB_DW-1 downto 0);
reg20_out : out std_logic_vector(WB_DW-1 downto 0);
reg21_out : out std_logic_vector(WB_DW-1 downto 0);
reg22_out : out std_logic_vector(WB_DW-1 downto 0);
reg23_out : out std_logic_vector(WB_DW-1 downto 0);
reg24_out : out std_logic_vector(WB_DW-1 downto 0);
reg25_out : out std_logic_vector(WB_DW-1 downto 0);
reg26_out : out std_logic_vector(WB_DW-1 downto 0);
reg27_out : out std_logic_vector(WB_DW-1 downto 0);
reg28_out : out std_logic_vector(WB_DW-1 downto 0);
reg29_out : out std_logic_vector(WB_DW-1 downto 0);
reg30_out : out std_logic_vector(WB_DW-1 downto 0);
reg31_out : out std_logic_vector(WB_DW-1 downto 0);
reg32_out : out std_logic_vector(WB_DW-1 downto 0);
reg33_out : out std_logic_vector(WB_DW-1 downto 0);
reg34_out : out std_logic_vector(WB_DW-1 downto 0);
reg35_out : out std_logic_vector(WB_DW-1 downto 0);
reg36_out : out std_logic_vector(WB_DW-1 downto 0);
reg37_out : out std_logic_vector(WB_DW-1 downto 0);
reg38_out : out std_logic_vector(WB_DW-1 downto 0);
reg39_out : out std_logic_vector(WB_DW-1 downto 0);
reg40_out : out std_logic_vector(WB_DW-1 downto 0);
reg41_out : out std_logic_vector(WB_DW-1 downto 0);
reg42_out : out std_logic_vector(WB_DW-1 downto 0);
reg43_out : out std_logic_vector(WB_DW-1 downto 0);
reg44_out : out std_logic_vector(WB_DW-1 downto 0);
reg45_out : out std_logic_vector(WB_DW-1 downto 0);
reg46_out : out std_logic_vector(WB_DW-1 downto 0);
reg47_out : out std_logic_vector(WB_DW-1 downto 0);
reg48_out : out std_logic_vector(WB_DW-1 downto 0);
reg49_out : out std_logic_vector(WB_DW-1 downto 0);
reg50_out : out std_logic_vector(WB_DW-1 downto 0);
reg51_out : out std_logic_vector(WB_DW-1 downto 0);
reg52_out : out std_logic_vector(WB_DW-1 downto 0);
reg53_out : out std_logic_vector(WB_DW-1 downto 0);
reg54_out : out std_logic_vector(WB_DW-1 downto 0);
reg55_out : out std_logic_vector(WB_DW-1 downto 0);
reg56_out : out std_logic_vector(WB_DW-1 downto 0);
reg57_out : out std_logic_vector(WB_DW-1 downto 0);
reg58_out : out std_logic_vector(WB_DW-1 downto 0);
reg59_out : out std_logic_vector(WB_DW-1 downto 0);
reg60_out : out std_logic_vector(WB_DW-1 downto 0);
reg61_out : out std_logic_vector(WB_DW-1 downto 0);
reg62_out : out std_logic_vector(WB_DW-1 downto 0);
reg63_out : out std_logic_vector(WB_DW-1 downto 0);
reg64_out : out std_logic_vector(WB_DW-1 downto 0);
reg65_out : out std_logic_vector(WB_DW-1 downto 0);
reg66_out : out std_logic_vector(WB_DW-1 downto 0);
reg67_out : out std_logic_vector(WB_DW-1 downto 0);
reg68_out : out std_logic_vector(WB_DW-1 downto 0);
reg69_out : out std_logic_vector(WB_DW-1 downto 0);
reg70_out : out std_logic_vector(WB_DW-1 downto 0);
reg71_out : out std_logic_vector(WB_DW-1 downto 0);
reg72_out : out std_logic_vector(WB_DW-1 downto 0);
reg73_out : out std_logic_vector(WB_DW-1 downto 0);
reg74_out : out std_logic_vector(WB_DW-1 downto 0);
reg75_out : out std_logic_vector(WB_DW-1 downto 0);
reg76_out : out std_logic_vector(WB_DW-1 downto 0);
reg77_out : out std_logic_vector(WB_DW-1 downto 0);
reg78_out : out std_logic_vector(WB_DW-1 downto 0);
reg79_out : out std_logic_vector(WB_DW-1 downto 0);
reg80_out : out std_logic_vector(WB_DW-1 downto 0);
reg81_out : out std_logic_vector(WB_DW-1 downto 0);
reg82_out : out std_logic_vector(WB_DW-1 downto 0);
reg83_out : out std_logic_vector(WB_DW-1 downto 0);
reg84_out : out std_logic_vector(WB_DW-1 downto 0);
reg85_out : out std_logic_vector(WB_DW-1 downto 0);
reg86_out : out std_logic_vector(WB_DW-1 downto 0);
reg87_out : out std_logic_vector(WB_DW-1 downto 0);
reg88_out : out std_logic_vector(WB_DW-1 downto 0);
reg89_out : out std_logic_vector(WB_DW-1 downto 0);
reg90_out : out std_logic_vector(WB_DW-1 downto 0);
reg91_out : out std_logic_vector(WB_DW-1 downto 0);
reg92_out : out std_logic_vector(WB_DW-1 downto 0);
reg93_out : out std_logic_vector(WB_DW-1 downto 0);
reg94_out : out std_logic_vector(WB_DW-1 downto 0);
reg95_out : out std_logic_vector(WB_DW-1 downto 0);
reg96_out : out std_logic_vector(WB_DW-1 downto 0);
reg97_out : out std_logic_vector(WB_DW-1 downto 0);
reg98_out : out std_logic_vector(WB_DW-1 downto 0);
reg99_out : out std_logic_vector(WB_DW-1 downto 0);
reg100_out : out std_logic_vector(WB_DW-1 downto 0);
reg101_out : out std_logic_vector(WB_DW-1 downto 0);
reg102_out : out std_logic_vector(WB_DW-1 downto 0);
reg103_out : out std_logic_vector(WB_DW-1 downto 0);
reg104_out : out std_logic_vector(WB_DW-1 downto 0);
reg105_out : out std_logic_vector(WB_DW-1 downto 0);
reg106_out : out std_logic_vector(WB_DW-1 downto 0);
reg107_out : out std_logic_vector(WB_DW-1 downto 0);
reg108_out : out std_logic_vector(WB_DW-1 downto 0);
reg109_out : out std_logic_vector(WB_DW-1 downto 0);
reg110_out : out std_logic_vector(WB_DW-1 downto 0);
reg111_out : out std_logic_vector(WB_DW-1 downto 0);
reg112_out : out std_logic_vector(WB_DW-1 downto 0);
reg113_out : out std_logic_vector(WB_DW-1 downto 0);
reg114_out : out std_logic_vector(WB_DW-1 downto 0);
reg115_out : out std_logic_vector(WB_DW-1 downto 0);
reg116_out : out std_logic_vector(WB_DW-1 downto 0);
reg117_out : out std_logic_vector(WB_DW-1 downto 0);
reg118_out : out std_logic_vector(WB_DW-1 downto 0);
reg119_out : out std_logic_vector(WB_DW-1 downto 0);
reg120_out : out std_logic_vector(WB_DW-1 downto 0);
reg121_out : out std_logic_vector(WB_DW-1 downto 0);
reg122_out : out std_logic_vector(WB_DW-1 downto 0);
reg123_out : out std_logic_vector(WB_DW-1 downto 0);
reg124_out : out std_logic_vector(WB_DW-1 downto 0);
reg125_out : out std_logic_vector(WB_DW-1 downto 0);
reg126_out : out std_logic_vector(WB_DW-1 downto 0);
reg127_out : out std_logic_vector(WB_DW-1 downto 0);
reg128_out : out std_logic_vector(WB_DW-1 downto 0);
reg129_out : out std_logic_vector(WB_DW-1 downto 0);
reg130_out : out std_logic_vector(WB_DW-1 downto 0);
reg131_out : out std_logic_vector(WB_DW-1 downto 0);
reg132_out : out std_logic_vector(WB_DW-1 downto 0);
reg133_out : out std_logic_vector(WB_DW-1 downto 0);
reg134_out : out std_logic_vector(WB_DW-1 downto 0);
reg135_out : out std_logic_vector(WB_DW-1 downto 0);
reg136_out : out std_logic_vector(WB_DW-1 downto 0);
reg137_out : out std_logic_vector(WB_DW-1 downto 0);
reg138_out : out std_logic_vector(WB_DW-1 downto 0);
reg139_out : out std_logic_vector(WB_DW-1 downto 0);
reg140_out : out std_logic_vector(WB_DW-1 downto 0);
reg141_out : out std_logic_vector(WB_DW-1 downto 0);
reg142_out : out std_logic_vector(WB_DW-1 downto 0);
reg143_out : out std_logic_vector(WB_DW-1 downto 0);
reg144_out : out std_logic_vector(WB_DW-1 downto 0);
reg145_out : out std_logic_vector(WB_DW-1 downto 0);
reg146_out : out std_logic_vector(WB_DW-1 downto 0);
reg147_out : out std_logic_vector(WB_DW-1 downto 0);
reg148_out : out std_logic_vector(WB_DW-1 downto 0);
reg149_out : out std_logic_vector(WB_DW-1 downto 0);
reg150_out : out std_logic_vector(WB_DW-1 downto 0);
reg151_out : out std_logic_vector(WB_DW-1 downto 0);
reg152_out : out std_logic_vector(WB_DW-1 downto 0);
reg153_out : out std_logic_vector(WB_DW-1 downto 0);
reg154_out : out std_logic_vector(WB_DW-1 downto 0);
reg155_out : out std_logic_vector(WB_DW-1 downto 0);
reg156_out : out std_logic_vector(WB_DW-1 downto 0);
reg157_out : out std_logic_vector(WB_DW-1 downto 0);
reg158_out : out std_logic_vector(WB_DW-1 downto 0);
reg159_out : out std_logic_vector(WB_DW-1 downto 0);
reg160_out : out std_logic_vector(WB_DW-1 downto 0);
reg161_out : out std_logic_vector(WB_DW-1 downto 0);
reg162_out : out std_logic_vector(WB_DW-1 downto 0);
reg163_out : out std_logic_vector(WB_DW-1 downto 0);
reg164_out : out std_logic_vector(WB_DW-1 downto 0);
reg165_out : out std_logic_vector(WB_DW-1 downto 0);
reg166_out : out std_logic_vector(WB_DW-1 downto 0);
reg167_out : out std_logic_vector(WB_DW-1 downto 0);
reg168_out : out std_logic_vector(WB_DW-1 downto 0);
reg169_out : out std_logic_vector(WB_DW-1 downto 0);
reg170_out : out std_logic_vector(WB_DW-1 downto 0);
reg171_out : out std_logic_vector(WB_DW-1 downto 0);
reg172_out : out std_logic_vector(WB_DW-1 downto 0);
reg173_out : out std_logic_vector(WB_DW-1 downto 0);
reg174_out : out std_logic_vector(WB_DW-1 downto 0);
reg175_out : out std_logic_vector(WB_DW-1 downto 0);
reg176_out : out std_logic_vector(WB_DW-1 downto 0);
reg177_out : out std_logic_vector(WB_DW-1 downto 0);
reg178_out : out std_logic_vector(WB_DW-1 downto 0);
reg179_out : out std_logic_vector(WB_DW-1 downto 0);
reg180_out : out std_logic_vector(WB_DW-1 downto 0);
reg181_out : out std_logic_vector(WB_DW-1 downto 0);
reg182_out : out std_logic_vector(WB_DW-1 downto 0);
reg183_out : out std_logic_vector(WB_DW-1 downto 0);
reg184_out : out std_logic_vector(WB_DW-1 downto 0);
reg185_out : out std_logic_vector(WB_DW-1 downto 0);
reg186_out : out std_logic_vector(WB_DW-1 downto 0);
reg187_out : out std_logic_vector(WB_DW-1 downto 0);
reg188_out : out std_logic_vector(WB_DW-1 downto 0);
reg189_out : out std_logic_vector(WB_DW-1 downto 0);
reg190_out : out std_logic_vector(WB_DW-1 downto 0);
reg191_out : out std_logic_vector(WB_DW-1 downto 0);
reg192_out : out std_logic_vector(WB_DW-1 downto 0);
reg193_out : out std_logic_vector(WB_DW-1 downto 0);
reg194_out : out std_logic_vector(WB_DW-1 downto 0);
reg195_out : out std_logic_vector(WB_DW-1 downto 0);
reg196_out : out std_logic_vector(WB_DW-1 downto 0);
reg197_out : out std_logic_vector(WB_DW-1 downto 0);
reg198_out : out std_logic_vector(WB_DW-1 downto 0);
reg199_out : out std_logic_vector(WB_DW-1 downto 0);
reg200_out : out std_logic_vector(WB_DW-1 downto 0);
reg201_out : out std_logic_vector(WB_DW-1 downto 0);
reg202_out : out std_logic_vector(WB_DW-1 downto 0);
reg203_out : out std_logic_vector(WB_DW-1 downto 0);
reg204_out : out std_logic_vector(WB_DW-1 downto 0);
reg205_out : out std_logic_vector(WB_DW-1 downto 0);
reg206_out : out std_logic_vector(WB_DW-1 downto 0);
reg207_out : out std_logic_vector(WB_DW-1 downto 0);
reg208_out : out std_logic_vector(WB_DW-1 downto 0);
reg209_out : out std_logic_vector(WB_DW-1 downto 0);
reg210_out : out std_logic_vector(WB_DW-1 downto 0);
reg211_out : out std_logic_vector(WB_DW-1 downto 0);
reg212_out : out std_logic_vector(WB_DW-1 downto 0);
reg213_out : out std_logic_vector(WB_DW-1 downto 0);
reg214_out : out std_logic_vector(WB_DW-1 downto 0);
reg215_out : out std_logic_vector(WB_DW-1 downto 0);
reg216_out : out std_logic_vector(WB_DW-1 downto 0);
reg217_out : out std_logic_vector(WB_DW-1 downto 0);
reg218_out : out std_logic_vector(WB_DW-1 downto 0);
reg219_out : out std_logic_vector(WB_DW-1 downto 0);
reg220_out : out std_logic_vector(WB_DW-1 downto 0);
reg221_out : out std_logic_vector(WB_DW-1 downto 0);
reg222_out : out std_logic_vector(WB_DW-1 downto 0);
reg223_out : out std_logic_vector(WB_DW-1 downto 0);
reg224_out : out std_logic_vector(WB_DW-1 downto 0);
reg225_out : out std_logic_vector(WB_DW-1 downto 0);
reg226_out : out std_logic_vector(WB_DW-1 downto 0);
reg227_out : out std_logic_vector(WB_DW-1 downto 0);
reg228_out : out std_logic_vector(WB_DW-1 downto 0);
reg229_out : out std_logic_vector(WB_DW-1 downto 0);
reg230_out : out std_logic_vector(WB_DW-1 downto 0);
reg231_out : out std_logic_vector(WB_DW-1 downto 0);
reg232_out : out std_logic_vector(WB_DW-1 downto 0);
reg233_out : out std_logic_vector(WB_DW-1 downto 0);
reg234_out : out std_logic_vector(WB_DW-1 downto 0);
reg235_out : out std_logic_vector(WB_DW-1 downto 0);
reg236_out : out std_logic_vector(WB_DW-1 downto 0);
reg237_out : out std_logic_vector(WB_DW-1 downto 0);
reg238_out : out std_logic_vector(WB_DW-1 downto 0);
reg239_out : out std_logic_vector(WB_DW-1 downto 0);
reg240_out : out std_logic_vector(WB_DW-1 downto 0);
reg241_out : out std_logic_vector(WB_DW-1 downto 0);
reg242_out : out std_logic_vector(WB_DW-1 downto 0);
reg243_out : out std_logic_vector(WB_DW-1 downto 0);
reg244_out : out std_logic_vector(WB_DW-1 downto 0);
reg245_out : out std_logic_vector(WB_DW-1 downto 0);
reg246_out : out std_logic_vector(WB_DW-1 downto 0);
reg247_out : out std_logic_vector(WB_DW-1 downto 0);
reg248_out : out std_logic_vector(WB_DW-1 downto 0);
reg249_out : out std_logic_vector(WB_DW-1 downto 0);
reg250_out : out std_logic_vector(WB_DW-1 downto 0);
reg251_out : out std_logic_vector(WB_DW-1 downto 0);
reg252_out : out std_logic_vector(WB_DW-1 downto 0);
reg253_out : out std_logic_vector(WB_DW-1 downto 0);
reg254_out : out std_logic_vector(WB_DW-1 downto 0);
reg255_out : out std_logic_vector(WB_DW-1 downto 0);
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.package_wbs256.all;
-------------------------------------------------------------------------------
entity wbs256 is
-------------------------------------------------------------------------------
port (
-- register outputs
reg0_out : out std_logic_vector(WB_DW-1 downto 0);
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0);
reg3_out : out std_logic_vector(WB_DW-1 downto 0);
reg4_out : out std_logic_vector(WB_DW-1 downto 0);
reg5_out : out std_logic_vector(WB_DW-1 downto 0);
reg6_out : out std_logic_vector(WB_DW-1 downto 0);
reg7_out : out std_logic_vector(WB_DW-1 downto 0);
reg8_out : out std_logic_vector(WB_DW-1 downto 0);
reg9_out : out std_logic_vector(WB_DW-1 downto 0);
reg10_out : out std_logic_vector(WB_DW-1 downto 0);
reg11_out : out std_logic_vector(WB_DW-1 downto 0);
reg12_out : out std_logic_vector(WB_DW-1 downto 0);
reg13_out : out std_logic_vector(WB_DW-1 downto 0);
reg14_out : out std_logic_vector(WB_DW-1 downto 0);
reg15_out : out std_logic_vector(WB_DW-1 downto 0);
reg16_out : out std_logic_vector(WB_DW-1 downto 0);
reg17_out : out std_logic_vector(WB_DW-1 downto 0);
reg18_out : out std_logic_vector(WB_DW-1 downto 0);
reg19_out : out std_logic_vector(WB_DW-1 downto 0);
reg20_out : out std_logic_vector(WB_DW-1 downto 0);
reg21_out : out std_logic_vector(WB_DW-1 downto 0);
reg22_out : out std_logic_vector(WB_DW-1 downto 0);
reg23_out : out std_logic_vector(WB_DW-1 downto 0);
reg24_out : out std_logic_vector(WB_DW-1 downto 0);
reg25_out : out std_logic_vector(WB_DW-1 downto 0);
reg26_out : out std_logic_vector(WB_DW-1 downto 0);
reg27_out : out std_logic_vector(WB_DW-1 downto 0);
reg28_out : out std_logic_vector(WB_DW-1 downto 0);
reg29_out : out std_logic_vector(WB_DW-1 downto 0);
reg30_out : out std_logic_vector(WB_DW-1 downto 0);
reg31_out : out std_logic_vector(WB_DW-1 downto 0);
reg32_out : out std_logic_vector(WB_DW-1 downto 0);
reg33_out : out std_logic_vector(WB_DW-1 downto 0);
reg34_out : out std_logic_vector(WB_DW-1 downto 0);
reg35_out : out std_logic_vector(WB_DW-1 downto 0);
reg36_out : out std_logic_vector(WB_DW-1 downto 0);
reg37_out : out std_logic_vector(WB_DW-1 downto 0);
reg38_out : out std_logic_vector(WB_DW-1 downto 0);
reg39_out : out std_logic_vector(WB_DW-1 downto 0);
reg40_out : out std_logic_vector(WB_DW-1 downto 0);
reg41_out : out std_logic_vector(WB_DW-1 downto 0);
reg42_out : out std_logic_vector(WB_DW-1 downto 0);
reg43_out : out std_logic_vector(WB_DW-1 downto 0);
reg44_out : out std_logic_vector(WB_DW-1 downto 0);
reg45_out : out std_logic_vector(WB_DW-1 downto 0);
reg46_out : out std_logic_vector(WB_DW-1 downto 0);
reg47_out : out std_logic_vector(WB_DW-1 downto 0);
reg48_out : out std_logic_vector(WB_DW-1 downto 0);
reg49_out : out std_logic_vector(WB_DW-1 downto 0);
reg50_out : out std_logic_vector(WB_DW-1 downto 0);
reg51_out : out std_logic_vector(WB_DW-1 downto 0);
reg52_out : out std_logic_vector(WB_DW-1 downto 0);
reg53_out : out std_logic_vector(WB_DW-1 downto 0);
reg54_out : out std_logic_vector(WB_DW-1 downto 0);
reg55_out : out std_logic_vector(WB_DW-1 downto 0);
reg56_out : out std_logic_vector(WB_DW-1 downto 0);
reg57_out : out std_logic_vector(WB_DW-1 downto 0);
reg58_out : out std_logic_vector(WB_DW-1 downto 0);
reg59_out : out std_logic_vector(WB_DW-1 downto 0);
reg60_out : out std_logic_vector(WB_DW-1 downto 0);
reg61_out : out std_logic_vector(WB_DW-1 downto 0);
reg62_out : out std_logic_vector(WB_DW-1 downto 0);
reg63_out : out std_logic_vector(WB_DW-1 downto 0);
reg64_out : out std_logic_vector(WB_DW-1 downto 0);
reg65_out : out std_logic_vector(WB_DW-1 downto 0);
reg66_out : out std_logic_vector(WB_DW-1 downto 0);
reg67_out : out std_logic_vector(WB_DW-1 downto 0);
reg68_out : out std_logic_vector(WB_DW-1 downto 0);
reg69_out : out std_logic_vector(WB_DW-1 downto 0);
reg70_out : out std_logic_vector(WB_DW-1 downto 0);
reg71_out : out std_logic_vector(WB_DW-1 downto 0);
reg72_out : out std_logic_vector(WB_DW-1 downto 0);
reg73_out : out std_logic_vector(WB_DW-1 downto 0);
reg74_out : out std_logic_vector(WB_DW-1 downto 0);
reg75_out : out std_logic_vector(WB_DW-1 downto 0);
reg76_out : out std_logic_vector(WB_DW-1 downto 0);
reg77_out : out std_logic_vector(WB_DW-1 downto 0);
reg78_out : out std_logic_vector(WB_DW-1 downto 0);
reg79_out : out std_logic_vector(WB_DW-1 downto 0);
reg80_out : out std_logic_vector(WB_DW-1 downto 0);
reg81_out : out std_logic_vector(WB_DW-1 downto 0);
reg82_out : out std_logic_vector(WB_DW-1 downto 0);
reg83_out : out std_logic_vector(WB_DW-1 downto 0);
reg84_out : out std_logic_vector(WB_DW-1 downto 0);
reg85_out : out std_logic_vector(WB_DW-1 downto 0);
reg86_out : out std_logic_vector(WB_DW-1 downto 0);
reg87_out : out std_logic_vector(WB_DW-1 downto 0);
reg88_out : out std_logic_vector(WB_DW-1 downto 0);
reg89_out : out std_logic_vector(WB_DW-1 downto 0);
reg90_out : out std_logic_vector(WB_DW-1 downto 0);
reg91_out : out std_logic_vector(WB_DW-1 downto 0);
reg92_out : out std_logic_vector(WB_DW-1 downto 0);
reg93_out : out std_logic_vector(WB_DW-1 downto 0);
reg94_out : out std_logic_vector(WB_DW-1 downto 0);
reg95_out : out std_logic_vector(WB_DW-1 downto 0);
reg96_out : out std_logic_vector(WB_DW-1 downto 0);
reg97_out : out std_logic_vector(WB_DW-1 downto 0);
reg98_out : out std_logic_vector(WB_DW-1 downto 0);
reg99_out : out std_logic_vector(WB_DW-1 downto 0);
reg100_out : out std_logic_vector(WB_DW-1 downto 0);
reg101_out : out std_logic_vector(WB_DW-1 downto 0);
reg102_out : out std_logic_vector(WB_DW-1 downto 0);
reg103_out : out std_logic_vector(WB_DW-1 downto 0);
reg104_out : out std_logic_vector(WB_DW-1 downto 0);
reg105_out : out std_logic_vector(WB_DW-1 downto 0);
reg106_out : out std_logic_vector(WB_DW-1 downto 0);
reg107_out : out std_logic_vector(WB_DW-1 downto 0);
reg108_out : out std_logic_vector(WB_DW-1 downto 0);
reg109_out : out std_logic_vector(WB_DW-1 downto 0);
reg110_out : out std_logic_vector(WB_DW-1 downto 0);
reg111_out : out std_logic_vector(WB_DW-1 downto 0);
reg112_out : out std_logic_vector(WB_DW-1 downto 0);
reg113_out : out std_logic_vector(WB_DW-1 downto 0);
reg114_out : out std_logic_vector(WB_DW-1 downto 0);
reg115_out : out std_logic_vector(WB_DW-1 downto 0);
reg116_out : out std_logic_vector(WB_DW-1 downto 0);
reg117_out : out std_logic_vector(WB_DW-1 downto 0);
reg118_out : out std_logic_vector(WB_DW-1 downto 0);
reg119_out : out std_logic_vector(WB_DW-1 downto 0);
reg120_out : out std_logic_vector(WB_DW-1 downto 0);
reg121_out : out std_logic_vector(WB_DW-1 downto 0);
reg122_out : out std_logic_vector(WB_DW-1 downto 0);
reg123_out : out std_logic_vector(WB_DW-1 downto 0);
reg124_out : out std_logic_vector(WB_DW-1 downto 0);
reg125_out : out std_logic_vector(WB_DW-1 downto 0);
reg126_out : out std_logic_vector(WB_DW-1 downto 0);
reg127_out : out std_logic_vector(WB_DW-1 downto 0);
reg128_out : out std_logic_vector(WB_DW-1 downto 0);
reg129_out : out std_logic_vector(WB_DW-1 downto 0);
reg130_out : out std_logic_vector(WB_DW-1 downto 0);
reg131_out : out std_logic_vector(WB_DW-1 downto 0);
reg132_out : out std_logic_vector(WB_DW-1 downto 0);
reg133_out : out std_logic_vector(WB_DW-1 downto 0);
reg134_out : out std_logic_vector(WB_DW-1 downto 0);
reg135_out : out std_logic_vector(WB_DW-1 downto 0);
reg136_out : out std_logic_vector(WB_DW-1 downto 0);
reg137_out : out std_logic_vector(WB_DW-1 downto 0);
reg138_out : out std_logic_vector(WB_DW-1 downto 0);
reg139_out : out std_logic_vector(WB_DW-1 downto 0);
reg140_out : out std_logic_vector(WB_DW-1 downto 0);
reg141_out : out std_logic_vector(WB_DW-1 downto 0);
reg142_out : out std_logic_vector(WB_DW-1 downto 0);
reg143_out : out std_logic_vector(WB_DW-1 downto 0);
reg144_out : out std_logic_vector(WB_DW-1 downto 0);
reg145_out : out std_logic_vector(WB_DW-1 downto 0);
reg146_out : out std_logic_vector(WB_DW-1 downto 0);
reg147_out : out std_logic_vector(WB_DW-1 downto 0);
reg148_out : out std_logic_vector(WB_DW-1 downto 0);
reg149_out : out std_logic_vector(WB_DW-1 downto 0);
reg150_out : out std_logic_vector(WB_DW-1 downto 0);
reg151_out : out std_logic_vector(WB_DW-1 downto 0);
reg152_out : out std_logic_vector(WB_DW-1 downto 0);
reg153_out : out std_logic_vector(WB_DW-1 downto 0);
reg154_out : out std_logic_vector(WB_DW-1 downto 0);
reg155_out : out std_logic_vector(WB_DW-1 downto 0);
reg156_out : out std_logic_vector(WB_DW-1 downto 0);
reg157_out : out std_logic_vector(WB_DW-1 downto 0);
reg158_out : out std_logic_vector(WB_DW-1 downto 0);
reg159_out : out std_logic_vector(WB_DW-1 downto 0);
reg160_out : out std_logic_vector(WB_DW-1 downto 0);
reg161_out : out std_logic_vector(WB_DW-1 downto 0);
reg162_out : out std_logic_vector(WB_DW-1 downto 0);
reg163_out : out std_logic_vector(WB_DW-1 downto 0);
reg164_out : out std_logic_vector(WB_DW-1 downto 0);
reg165_out : out std_logic_vector(WB_DW-1 downto 0);
reg166_out : out std_logic_vector(WB_DW-1 downto 0);
reg167_out : out std_logic_vector(WB_DW-1 downto 0);
reg168_out : out std_logic_vector(WB_DW-1 downto 0);
reg169_out : out std_logic_vector(WB_DW-1 downto 0);
reg170_out : out std_logic_vector(WB_DW-1 downto 0);
reg171_out : out std_logic_vector(WB_DW-1 downto 0);
reg172_out : out std_logic_vector(WB_DW-1 downto 0);
reg173_out : out std_logic_vector(WB_DW-1 downto 0);
reg174_out : out std_logic_vector(WB_DW-1 downto 0);
reg175_out : out std_logic_vector(WB_DW-1 downto 0);
reg176_out : out std_logic_vector(WB_DW-1 downto 0);
reg177_out : out std_logic_vector(WB_DW-1 downto 0);
reg178_out : out std_logic_vector(WB_DW-1 downto 0);
reg179_out : out std_logic_vector(WB_DW-1 downto 0);
reg180_out : out std_logic_vector(WB_DW-1 downto 0);
reg181_out : out std_logic_vector(WB_DW-1 downto 0);
reg182_out : out std_logic_vector(WB_DW-1 downto 0);
reg183_out : out std_logic_vector(WB_DW-1 downto 0);
reg184_out : out std_logic_vector(WB_DW-1 downto 0);
reg185_out : out std_logic_vector(WB_DW-1 downto 0);
reg186_out : out std_logic_vector(WB_DW-1 downto 0);
reg187_out : out std_logic_vector(WB_DW-1 downto 0);
reg188_out : out std_logic_vector(WB_DW-1 downto 0);
reg189_out : out std_logic_vector(WB_DW-1 downto 0);
reg190_out : out std_logic_vector(WB_DW-1 downto 0);
reg191_out : out std_logic_vector(WB_DW-1 downto 0);
reg192_out : out std_logic_vector(WB_DW-1 downto 0);
reg193_out : out std_logic_vector(WB_DW-1 downto 0);
reg194_out : out std_logic_vector(WB_DW-1 downto 0);
reg195_out : out std_logic_vector(WB_DW-1 downto 0);
reg196_out : out std_logic_vector(WB_DW-1 downto 0);
reg197_out : out std_logic_vector(WB_DW-1 downto 0);
reg198_out : out std_logic_vector(WB_DW-1 downto 0);
reg199_out : out std_logic_vector(WB_DW-1 downto 0);
reg200_out : out std_logic_vector(WB_DW-1 downto 0);
reg201_out : out std_logic_vector(WB_DW-1 downto 0);
reg202_out : out std_logic_vector(WB_DW-1 downto 0);
reg203_out : out std_logic_vector(WB_DW-1 downto 0);
reg204_out : out std_logic_vector(WB_DW-1 downto 0);
reg205_out : out std_logic_vector(WB_DW-1 downto 0);
reg206_out : out std_logic_vector(WB_DW-1 downto 0);
reg207_out : out std_logic_vector(WB_DW-1 downto 0);
reg208_out : out std_logic_vector(WB_DW-1 downto 0);
reg209_out : out std_logic_vector(WB_DW-1 downto 0);
reg210_out : out std_logic_vector(WB_DW-1 downto 0);
reg211_out : out std_logic_vector(WB_DW-1 downto 0);
reg212_out : out std_logic_vector(WB_DW-1 downto 0);
reg213_out : out std_logic_vector(WB_DW-1 downto 0);
reg214_out : out std_logic_vector(WB_DW-1 downto 0);
reg215_out : out std_logic_vector(WB_DW-1 downto 0);
reg216_out : out std_logic_vector(WB_DW-1 downto 0);
reg217_out : out std_logic_vector(WB_DW-1 downto 0);
reg218_out : out std_logic_vector(WB_DW-1 downto 0);
reg219_out : out std_logic_vector(WB_DW-1 downto 0);
reg220_out : out std_logic_vector(WB_DW-1 downto 0);
reg221_out : out std_logic_vector(WB_DW-1 downto 0);
reg222_out : out std_logic_vector(WB_DW-1 downto 0);
reg223_out : out std_logic_vector(WB_DW-1 downto 0);
reg224_out : out std_logic_vector(WB_DW-1 downto 0);
reg225_out : out std_logic_vector(WB_DW-1 downto 0);
reg226_out : out std_logic_vector(WB_DW-1 downto 0);
reg227_out : out std_logic_vector(WB_DW-1 downto 0);
reg228_out : out std_logic_vector(WB_DW-1 downto 0);
reg229_out : out std_logic_vector(WB_DW-1 downto 0);
reg230_out : out std_logic_vector(WB_DW-1 downto 0);
reg231_out : out std_logic_vector(WB_DW-1 downto 0);
reg232_out : out std_logic_vector(WB_DW-1 downto 0);
reg233_out : out std_logic_vector(WB_DW-1 downto 0);
reg234_out : out std_logic_vector(WB_DW-1 downto 0);
reg235_out : out std_logic_vector(WB_DW-1 downto 0);
reg236_out : out std_logic_vector(WB_DW-1 downto 0);
reg237_out : out std_logic_vector(WB_DW-1 downto 0);
reg238_out : out std_logic_vector(WB_DW-1 downto 0);
reg239_out : out std_logic_vector(WB_DW-1 downto 0);
reg240_out : out std_logic_vector(WB_DW-1 downto 0);
reg241_out : out std_logic_vector(WB_DW-1 downto 0);
reg242_out : out std_logic_vector(WB_DW-1 downto 0);
reg243_out : out std_logic_vector(WB_DW-1 downto 0);
reg244_out : out std_logic_vector(WB_DW-1 downto 0);
reg245_out : out std_logic_vector(WB_DW-1 downto 0);
reg246_out : out std_logic_vector(WB_DW-1 downto 0);
reg247_out : out std_logic_vector(WB_DW-1 downto 0);
reg248_out : out std_logic_vector(WB_DW-1 downto 0);
reg249_out : out std_logic_vector(WB_DW-1 downto 0);
reg250_out : out std_logic_vector(WB_DW-1 downto 0);
reg251_out : out std_logic_vector(WB_DW-1 downto 0);
reg252_out : out std_logic_vector(WB_DW-1 downto 0);
reg253_out : out std_logic_vector(WB_DW-1 downto 0);
reg254_out : out std_logic_vector(WB_DW-1 downto 0);
reg255_out : out std_logic_vector(WB_DW-1 downto 0);
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end wbs256;
-------------------------------------------------------------------------------
architecture behavioral of wbs256 is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
constant REG0_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"00";
constant REG1_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"01";
constant REG2_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"02";
constant REG3_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"03";
constant REG4_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"04";
constant REG5_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"05";
constant REG6_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"06";
constant REG7_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"07";
constant REG8_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"08";
constant REG9_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"09";
constant REG10_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0A";
constant REG11_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0B";
constant REG12_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0C";
constant REG13_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0D";
constant REG14_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0E";
constant REG15_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0F";
constant REG16_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"10";
constant REG17_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"11";
constant REG18_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"12";
constant REG19_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"13";
constant REG20_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"14";
constant REG21_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"15";
constant REG22_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"16";
constant REG23_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"17";
constant REG24_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"18";
constant REG25_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"19";
constant REG26_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1A";
constant REG27_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1B";
constant REG28_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1C";
constant REG29_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1D";
constant REG30_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1E";
constant REG31_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1F";
constant REG32_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"20";
constant REG33_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"21";
constant REG34_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"22";
constant REG35_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"23";
constant REG36_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"24";
constant REG37_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"25";
constant REG38_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"26";
constant REG39_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"27";
constant REG40_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"28";
constant REG41_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"29";
constant REG42_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2A";
constant REG43_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2B";
constant REG44_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2C";
constant REG45_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2D";
constant REG46_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2E";
constant REG47_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2F";
constant REG48_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"30";
constant REG49_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"31";
constant REG50_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"32";
constant REG51_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"33";
constant REG52_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"34";
constant REG53_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"35";
constant REG54_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"36";
constant REG55_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"37";
constant REG56_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"38";
constant REG57_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"39";
constant REG58_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3A";
constant REG59_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3B";
constant REG60_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3C";
constant REG61_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3D";
constant REG62_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3E";
constant REG63_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3F";
constant REG64_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"40";
constant REG65_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"41";
constant REG66_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"42";
constant REG67_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"43";
constant REG68_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"44";
constant REG69_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"45";
constant REG70_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"46";
constant REG71_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"47";
constant REG72_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"48";
constant REG73_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"49";
constant REG74_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4A";
constant REG75_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4B";
constant REG76_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4C";
constant REG77_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4D";
constant REG78_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4E";
constant REG79_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4F";
constant REG80_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"50";
constant REG81_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"51";
constant REG82_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"52";
constant REG83_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"53";
constant REG84_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"54";
constant REG85_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"55";
constant REG86_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"56";
constant REG87_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"57";
constant REG88_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"58";
constant REG89_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"59";
constant REG90_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5A";
constant REG91_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5B";
constant REG92_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5C";
constant REG93_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5D";
constant REG94_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5E";
constant REG95_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5F";
constant REG96_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"60";
constant REG97_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"61";
constant REG98_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"62";
constant REG99_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"63";
constant REG100_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"64";
constant REG101_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"65";
constant REG102_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"66";
constant REG103_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"67";
constant REG104_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"68";
constant REG105_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"69";
constant REG106_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6A";
constant REG107_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6B";
constant REG108_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6C";
constant REG109_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6D";
constant REG110_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6E";
constant REG111_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6F";
constant REG112_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"70";
constant REG113_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"71";
constant REG114_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"72";
constant REG115_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"73";
constant REG116_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"74";
constant REG117_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"75";
constant REG118_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"76";
constant REG119_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"77";
constant REG120_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"78";
constant REG121_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"79";
constant REG122_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7A";
constant REG123_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7B";
constant REG124_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7C";
constant REG125_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7D";
constant REG126_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7E";
constant REG127_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7F";
constant REG128_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"80";
constant REG129_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"81";
constant REG130_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"82";
constant REG131_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"83";
constant REG132_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"84";
constant REG133_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"85";
constant REG134_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"86";
constant REG135_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"87";
constant REG136_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"88";
constant REG137_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"89";
constant REG138_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8A";
constant REG139_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8B";
constant REG140_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8C";
constant REG141_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8D";
constant REG142_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8E";
constant REG143_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8F";
constant REG144_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"90";
constant REG145_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"91";
constant REG146_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"92";
constant REG147_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"93";
constant REG148_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"94";
constant REG149_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"95";
constant REG150_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"96";
constant REG151_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"97";
constant REG152_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"98";
constant REG153_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"99";
constant REG154_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9A";
constant REG155_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9B";
constant REG156_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9C";
constant REG157_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9D";
constant REG158_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9E";
constant REG159_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9F";
constant REG160_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A0";
constant REG161_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A1";
constant REG162_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A2";
constant REG163_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A3";
constant REG164_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A4";
constant REG165_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A5";
constant REG166_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A6";
constant REG167_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A7";
constant REG168_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A8";
constant REG169_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A9";
constant REG170_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AA";
constant REG171_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AB";
constant REG172_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AC";
constant REG173_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AD";
constant REG174_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AE";
constant REG175_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AF";
constant REG176_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B0";
constant REG177_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B1";
constant REG178_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B2";
constant REG179_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B3";
constant REG180_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B4";
constant REG181_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B5";
constant REG182_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B6";
constant REG183_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B7";
constant REG184_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B8";
constant REG185_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B9";
constant REG186_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BA";
constant REG187_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BB";
constant REG188_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BC";
constant REG189_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BD";
constant REG190_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BE";
constant REG191_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BF";
constant REG192_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C0";
constant REG193_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C1";
constant REG194_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C2";
constant REG195_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C3";
constant REG196_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C4";
constant REG197_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C5";
constant REG198_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C6";
constant REG199_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C7";
constant REG200_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C8";
constant REG201_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C9";
constant REG202_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CA";
constant REG203_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CB";
constant REG204_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CC";
constant REG205_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CD";
constant REG206_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CE";
constant REG207_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CF";
constant REG208_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D0";
constant REG209_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D1";
constant REG210_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D2";
constant REG211_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D3";
constant REG212_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D4";
constant REG213_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D5";
constant REG214_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D6";
constant REG215_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D7";
constant REG216_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D8";
constant REG217_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D9";
constant REG218_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DA";
constant REG219_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DB";
constant REG220_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DC";
constant REG221_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DD";
constant REG222_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DE";
constant REG223_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DF";
constant REG224_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E0";
constant REG225_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E1";
constant REG226_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E2";
constant REG227_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E3";
constant REG228_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E4";
constant REG229_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E5";
constant REG230_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E6";
constant REG231_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E7";
constant REG232_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E8";
constant REG233_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E9";
constant REG234_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EA";
constant REG235_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EB";
constant REG236_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EC";
constant REG237_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"ED";
constant REG238_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EE";
constant REG239_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EF";
constant REG240_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F0";
constant REG241_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F1";
constant REG242_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F2";
constant REG243_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F3";
constant REG244_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F4";
constant REG245_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F5";
constant REG246_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F6";
constant REG247_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F7";
constant REG248_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F8";
constant REG249_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F9";
constant REG250_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FA";
constant REG251_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FB";
constant REG252_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FC";
constant REG253_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FD";
constant REG254_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FE";
constant REG255_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FF";
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : reg_wbs256_t;
signal reg0_adr_match_s, reg1_adr_match_s, reg2_adr_match_s, reg3_adr_match_s, reg4_adr_match_s, reg5_adr_match_s, reg6_adr_match_s, reg7_adr_match_s, reg8_adr_match_s, reg9_adr_match_s, reg10_adr_match_s, reg11_adr_match_s, reg12_adr_match_s, reg13_adr_match_s, reg14_adr_match_s, reg15_adr_match_s, reg16_adr_match_s, reg17_adr_match_s, reg18_adr_match_s, reg19_adr_match_s, reg20_adr_match_s, reg21_adr_match_s, reg22_adr_match_s, reg23_adr_match_s, reg24_adr_match_s, reg25_adr_match_s, reg26_adr_match_s, reg27_adr_match_s, reg28_adr_match_s, reg29_adr_match_s, reg30_adr_match_s, reg31_adr_match_s, reg32_adr_match_s, reg33_adr_match_s, reg34_adr_match_s, reg35_adr_match_s, reg36_adr_match_s, reg37_adr_match_s, reg38_adr_match_s, reg39_adr_match_s, reg40_adr_match_s, reg41_adr_match_s, reg42_adr_match_s, reg43_adr_match_s, reg44_adr_match_s, reg45_adr_match_s, reg46_adr_match_s, reg47_adr_match_s, reg48_adr_match_s, reg49_adr_match_s, reg50_adr_match_s, reg51_adr_match_s, reg52_adr_match_s, reg53_adr_match_s, reg54_adr_match_s, reg55_adr_match_s, reg56_adr_match_s, reg57_adr_match_s, reg58_adr_match_s, reg59_adr_match_s, reg60_adr_match_s, reg61_adr_match_s, reg62_adr_match_s, reg63_adr_match_s, reg64_adr_match_s, reg65_adr_match_s, reg66_adr_match_s, reg67_adr_match_s, reg68_adr_match_s, reg69_adr_match_s, reg70_adr_match_s, reg71_adr_match_s, reg72_adr_match_s, reg73_adr_match_s, reg74_adr_match_s, reg75_adr_match_s, reg76_adr_match_s, reg77_adr_match_s, reg78_adr_match_s, reg79_adr_match_s, reg80_adr_match_s, reg81_adr_match_s, reg82_adr_match_s, reg83_adr_match_s, reg84_adr_match_s, reg85_adr_match_s, reg86_adr_match_s, reg87_adr_match_s, reg88_adr_match_s, reg89_adr_match_s, reg90_adr_match_s, reg91_adr_match_s, reg92_adr_match_s, reg93_adr_match_s, reg94_adr_match_s, reg95_adr_match_s, reg96_adr_match_s, reg97_adr_match_s, reg98_adr_match_s, reg99_adr_match_s, reg100_adr_match_s, reg101_adr_match_s, reg102_adr_match_s, reg103_adr_match_s, reg104_adr_match_s, reg105_adr_match_s, reg106_adr_match_s, reg107_adr_match_s, reg108_adr_match_s, reg109_adr_match_s, reg110_adr_match_s, reg111_adr_match_s, reg112_adr_match_s, reg113_adr_match_s, reg114_adr_match_s, reg115_adr_match_s, reg116_adr_match_s, reg117_adr_match_s, reg118_adr_match_s, reg119_adr_match_s, reg120_adr_match_s, reg121_adr_match_s, reg122_adr_match_s, reg123_adr_match_s, reg124_adr_match_s, reg125_adr_match_s, reg126_adr_match_s, reg127_adr_match_s, reg128_adr_match_s, reg129_adr_match_s, reg130_adr_match_s, reg131_adr_match_s, reg132_adr_match_s, reg133_adr_match_s, reg134_adr_match_s, reg135_adr_match_s, reg136_adr_match_s, reg137_adr_match_s, reg138_adr_match_s, reg139_adr_match_s, reg140_adr_match_s, reg141_adr_match_s, reg142_adr_match_s, reg143_adr_match_s, reg144_adr_match_s, reg145_adr_match_s, reg146_adr_match_s, reg147_adr_match_s, reg148_adr_match_s, reg149_adr_match_s, reg150_adr_match_s, reg151_adr_match_s, reg152_adr_match_s, reg153_adr_match_s, reg154_adr_match_s, reg155_adr_match_s, reg156_adr_match_s, reg157_adr_match_s, reg158_adr_match_s, reg159_adr_match_s, reg160_adr_match_s, reg161_adr_match_s, reg162_adr_match_s, reg163_adr_match_s, reg164_adr_match_s, reg165_adr_match_s, reg166_adr_match_s, reg167_adr_match_s, reg168_adr_match_s, reg169_adr_match_s, reg170_adr_match_s, reg171_adr_match_s, reg172_adr_match_s, reg173_adr_match_s, reg174_adr_match_s, reg175_adr_match_s, reg176_adr_match_s, reg177_adr_match_s, reg178_adr_match_s, reg179_adr_match_s, reg180_adr_match_s, reg181_adr_match_s, reg182_adr_match_s, reg183_adr_match_s, reg184_adr_match_s, reg185_adr_match_s, reg186_adr_match_s, reg187_adr_match_s, reg188_adr_match_s, reg189_adr_match_s, reg190_adr_match_s, reg191_adr_match_s, reg192_adr_match_s, reg193_adr_match_s, reg194_adr_match_s, reg195_adr_match_s, reg196_adr_match_s, reg197_adr_match_s, reg198_adr_match_s, reg199_adr_match_s, reg200_adr_match_s, reg201_adr_match_s, reg202_adr_match_s, reg203_adr_match_s, reg204_adr_match_s, reg205_adr_match_s, reg206_adr_match_s, reg207_adr_match_s, reg208_adr_match_s, reg209_adr_match_s, reg210_adr_match_s, reg211_adr_match_s, reg212_adr_match_s, reg213_adr_match_s, reg214_adr_match_s, reg215_adr_match_s, reg216_adr_match_s, reg217_adr_match_s, reg218_adr_match_s, reg219_adr_match_s, reg220_adr_match_s, reg221_adr_match_s, reg222_adr_match_s, reg223_adr_match_s, reg224_adr_match_s, reg225_adr_match_s, reg226_adr_match_s, reg227_adr_match_s, reg228_adr_match_s, reg229_adr_match_s, reg230_adr_match_s, reg231_adr_match_s, reg232_adr_match_s, reg233_adr_match_s, reg234_adr_match_s, reg235_adr_match_s, reg236_adr_match_s, reg237_adr_match_s, reg238_adr_match_s, reg239_adr_match_s, reg240_adr_match_s, reg241_adr_match_s, reg242_adr_match_s, reg243_adr_match_s, reg244_adr_match_s, reg245_adr_match_s, reg246_adr_match_s, reg247_adr_match_s, reg248_adr_match_s, reg249_adr_match_s, reg250_adr_match_s, reg251_adr_match_s, reg252_adr_match_s, reg253_adr_match_s, reg254_adr_match_s, reg255_adr_match_s : std_logic;
signal reg0_re_s, reg1_re_s, reg2_re_s, reg3_re_s, reg4_re_s, reg5_re_s, reg6_re_s, reg7_re_s, reg8_re_s, reg9_re_s, reg10_re_s, reg11_re_s, reg12_re_s, reg13_re_s, reg14_re_s, reg15_re_s, reg16_re_s, reg17_re_s, reg18_re_s, reg19_re_s, reg20_re_s, reg21_re_s, reg22_re_s, reg23_re_s, reg24_re_s, reg25_re_s, reg26_re_s, reg27_re_s, reg28_re_s, reg29_re_s, reg30_re_s, reg31_re_s, reg32_re_s, reg33_re_s, reg34_re_s, reg35_re_s, reg36_re_s, reg37_re_s, reg38_re_s, reg39_re_s, reg40_re_s, reg41_re_s, reg42_re_s, reg43_re_s, reg44_re_s, reg45_re_s, reg46_re_s, reg47_re_s, reg48_re_s, reg49_re_s, reg50_re_s, reg51_re_s, reg52_re_s, reg53_re_s, reg54_re_s, reg55_re_s, reg56_re_s, reg57_re_s, reg58_re_s, reg59_re_s, reg60_re_s, reg61_re_s, reg62_re_s, reg63_re_s, reg64_re_s, reg65_re_s, reg66_re_s, reg67_re_s, reg68_re_s, reg69_re_s, reg70_re_s, reg71_re_s, reg72_re_s, reg73_re_s, reg74_re_s, reg75_re_s, reg76_re_s, reg77_re_s, reg78_re_s, reg79_re_s, reg80_re_s, reg81_re_s, reg82_re_s, reg83_re_s, reg84_re_s, reg85_re_s, reg86_re_s, reg87_re_s, reg88_re_s, reg89_re_s, reg90_re_s, reg91_re_s, reg92_re_s, reg93_re_s, reg94_re_s, reg95_re_s, reg96_re_s, reg97_re_s, reg98_re_s, reg99_re_s, reg100_re_s, reg101_re_s, reg102_re_s, reg103_re_s, reg104_re_s, reg105_re_s, reg106_re_s, reg107_re_s, reg108_re_s, reg109_re_s, reg110_re_s, reg111_re_s, reg112_re_s, reg113_re_s, reg114_re_s, reg115_re_s, reg116_re_s, reg117_re_s, reg118_re_s, reg119_re_s, reg120_re_s, reg121_re_s, reg122_re_s, reg123_re_s, reg124_re_s, reg125_re_s, reg126_re_s, reg127_re_s, reg128_re_s, reg129_re_s, reg130_re_s, reg131_re_s, reg132_re_s, reg133_re_s, reg134_re_s, reg135_re_s, reg136_re_s, reg137_re_s, reg138_re_s, reg139_re_s, reg140_re_s, reg141_re_s, reg142_re_s, reg143_re_s, reg144_re_s, reg145_re_s, reg146_re_s, reg147_re_s, reg148_re_s, reg149_re_s, reg150_re_s, reg151_re_s, reg152_re_s, reg153_re_s, reg154_re_s, reg155_re_s, reg156_re_s, reg157_re_s, reg158_re_s, reg159_re_s, reg160_re_s, reg161_re_s, reg162_re_s, reg163_re_s, reg164_re_s, reg165_re_s, reg166_re_s, reg167_re_s, reg168_re_s, reg169_re_s, reg170_re_s, reg171_re_s, reg172_re_s, reg173_re_s, reg174_re_s, reg175_re_s, reg176_re_s, reg177_re_s, reg178_re_s, reg179_re_s, reg180_re_s, reg181_re_s, reg182_re_s, reg183_re_s, reg184_re_s, reg185_re_s, reg186_re_s, reg187_re_s, reg188_re_s, reg189_re_s, reg190_re_s, reg191_re_s, reg192_re_s, reg193_re_s, reg194_re_s, reg195_re_s, reg196_re_s, reg197_re_s, reg198_re_s, reg199_re_s, reg200_re_s, reg201_re_s, reg202_re_s, reg203_re_s, reg204_re_s, reg205_re_s, reg206_re_s, reg207_re_s, reg208_re_s, reg209_re_s, reg210_re_s, reg211_re_s, reg212_re_s, reg213_re_s, reg214_re_s, reg215_re_s, reg216_re_s, reg217_re_s, reg218_re_s, reg219_re_s, reg220_re_s, reg221_re_s, reg222_re_s, reg223_re_s, reg224_re_s, reg225_re_s, reg226_re_s, reg227_re_s, reg228_re_s, reg229_re_s, reg230_re_s, reg231_re_s, reg232_re_s, reg233_re_s, reg234_re_s, reg235_re_s, reg236_re_s, reg237_re_s, reg238_re_s, reg239_re_s, reg240_re_s, reg241_re_s, reg242_re_s, reg243_re_s, reg244_re_s, reg245_re_s, reg246_re_s, reg247_re_s, reg248_re_s, reg249_re_s, reg250_re_s, reg251_re_s, reg252_re_s, reg253_re_s, reg254_re_s, reg255_re_s : std_logic;
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
reg0_adr_match_s <= '1' when wbs_in.adr = REG0_ADR else '0';
reg1_adr_match_s <= '1' when wbs_in.adr = REG1_ADR else '0';
reg2_adr_match_s <= '1' when wbs_in.adr = REG2_ADR else '0';
reg3_adr_match_s <= '1' when wbs_in.adr = REG3_ADR else '0';
reg4_adr_match_s <= '1' when wbs_in.adr = REG4_ADR else '0';
reg5_adr_match_s <= '1' when wbs_in.adr = REG5_ADR else '0';
reg6_adr_match_s <= '1' when wbs_in.adr = REG6_ADR else '0';
reg7_adr_match_s <= '1' when wbs_in.adr = REG7_ADR else '0';
reg8_adr_match_s <= '1' when wbs_in.adr = REG8_ADR else '0';
reg9_adr_match_s <= '1' when wbs_in.adr = REG9_ADR else '0';
reg10_adr_match_s <= '1' when wbs_in.adr = REG10_ADR else '0';
reg11_adr_match_s <= '1' when wbs_in.adr = REG11_ADR else '0';
reg12_adr_match_s <= '1' when wbs_in.adr = REG12_ADR else '0';
reg13_adr_match_s <= '1' when wbs_in.adr = REG13_ADR else '0';
reg14_adr_match_s <= '1' when wbs_in.adr = REG14_ADR else '0';
reg15_adr_match_s <= '1' when wbs_in.adr = REG15_ADR else '0';
reg16_adr_match_s <= '1' when wbs_in.adr = REG16_ADR else '0';
reg17_adr_match_s <= '1' when wbs_in.adr = REG17_ADR else '0';
reg18_adr_match_s <= '1' when wbs_in.adr = REG18_ADR else '0';
reg19_adr_match_s <= '1' when wbs_in.adr = REG19_ADR else '0';
reg20_adr_match_s <= '1' when wbs_in.adr = REG20_ADR else '0';
reg21_adr_match_s <= '1' when wbs_in.adr = REG21_ADR else '0';
reg22_adr_match_s <= '1' when wbs_in.adr = REG22_ADR else '0';
reg23_adr_match_s <= '1' when wbs_in.adr = REG23_ADR else '0';
reg24_adr_match_s <= '1' when wbs_in.adr = REG24_ADR else '0';
reg25_adr_match_s <= '1' when wbs_in.adr = REG25_ADR else '0';
reg26_adr_match_s <= '1' when wbs_in.adr = REG26_ADR else '0';
reg27_adr_match_s <= '1' when wbs_in.adr = REG27_ADR else '0';
reg28_adr_match_s <= '1' when wbs_in.adr = REG28_ADR else '0';
reg29_adr_match_s <= '1' when wbs_in.adr = REG29_ADR else '0';
reg30_adr_match_s <= '1' when wbs_in.adr = REG30_ADR else '0';
reg31_adr_match_s <= '1' when wbs_in.adr = REG31_ADR else '0';
reg32_adr_match_s <= '1' when wbs_in.adr = REG32_ADR else '0';
reg33_adr_match_s <= '1' when wbs_in.adr = REG33_ADR else '0';
reg34_adr_match_s <= '1' when wbs_in.adr = REG34_ADR else '0';
reg35_adr_match_s <= '1' when wbs_in.adr = REG35_ADR else '0';
reg36_adr_match_s <= '1' when wbs_in.adr = REG36_ADR else '0';
reg37_adr_match_s <= '1' when wbs_in.adr = REG37_ADR else '0';
reg38_adr_match_s <= '1' when wbs_in.adr = REG38_ADR else '0';
reg39_adr_match_s <= '1' when wbs_in.adr = REG39_ADR else '0';
reg40_adr_match_s <= '1' when wbs_in.adr = REG40_ADR else '0';
reg41_adr_match_s <= '1' when wbs_in.adr = REG41_ADR else '0';
reg42_adr_match_s <= '1' when wbs_in.adr = REG42_ADR else '0';
reg43_adr_match_s <= '1' when wbs_in.adr = REG43_ADR else '0';
reg44_adr_match_s <= '1' when wbs_in.adr = REG44_ADR else '0';
reg45_adr_match_s <= '1' when wbs_in.adr = REG45_ADR else '0';
reg46_adr_match_s <= '1' when wbs_in.adr = REG46_ADR else '0';
reg47_adr_match_s <= '1' when wbs_in.adr = REG47_ADR else '0';
reg48_adr_match_s <= '1' when wbs_in.adr = REG48_ADR else '0';
reg49_adr_match_s <= '1' when wbs_in.adr = REG49_ADR else '0';
reg50_adr_match_s <= '1' when wbs_in.adr = REG50_ADR else '0';
reg51_adr_match_s <= '1' when wbs_in.adr = REG51_ADR else '0';
reg52_adr_match_s <= '1' when wbs_in.adr = REG52_ADR else '0';
reg53_adr_match_s <= '1' when wbs_in.adr = REG53_ADR else '0';
reg54_adr_match_s <= '1' when wbs_in.adr = REG54_ADR else '0';
reg55_adr_match_s <= '1' when wbs_in.adr = REG55_ADR else '0';
reg56_adr_match_s <= '1' when wbs_in.adr = REG56_ADR else '0';
reg57_adr_match_s <= '1' when wbs_in.adr = REG57_ADR else '0';
reg58_adr_match_s <= '1' when wbs_in.adr = REG58_ADR else '0';
reg59_adr_match_s <= '1' when wbs_in.adr = REG59_ADR else '0';
reg60_adr_match_s <= '1' when wbs_in.adr = REG60_ADR else '0';
reg61_adr_match_s <= '1' when wbs_in.adr = REG61_ADR else '0';
reg62_adr_match_s <= '1' when wbs_in.adr = REG62_ADR else '0';
reg63_adr_match_s <= '1' when wbs_in.adr = REG63_ADR else '0';
reg64_adr_match_s <= '1' when wbs_in.adr = REG64_ADR else '0';
reg65_adr_match_s <= '1' when wbs_in.adr = REG65_ADR else '0';
reg66_adr_match_s <= '1' when wbs_in.adr = REG66_ADR else '0';
reg67_adr_match_s <= '1' when wbs_in.adr = REG67_ADR else '0';
reg68_adr_match_s <= '1' when wbs_in.adr = REG68_ADR else '0';
reg69_adr_match_s <= '1' when wbs_in.adr = REG69_ADR else '0';
reg70_adr_match_s <= '1' when wbs_in.adr = REG70_ADR else '0';
reg71_adr_match_s <= '1' when wbs_in.adr = REG71_ADR else '0';
reg72_adr_match_s <= '1' when wbs_in.adr = REG72_ADR else '0';
reg73_adr_match_s <= '1' when wbs_in.adr = REG73_ADR else '0';
reg74_adr_match_s <= '1' when wbs_in.adr = REG74_ADR else '0';
reg75_adr_match_s <= '1' when wbs_in.adr = REG75_ADR else '0';
reg76_adr_match_s <= '1' when wbs_in.adr = REG76_ADR else '0';
reg77_adr_match_s <= '1' when wbs_in.adr = REG77_ADR else '0';
reg78_adr_match_s <= '1' when wbs_in.adr = REG78_ADR else '0';
reg79_adr_match_s <= '1' when wbs_in.adr = REG79_ADR else '0';
reg80_adr_match_s <= '1' when wbs_in.adr = REG80_ADR else '0';
reg81_adr_match_s <= '1' when wbs_in.adr = REG81_ADR else '0';
reg82_adr_match_s <= '1' when wbs_in.adr = REG82_ADR else '0';
reg83_adr_match_s <= '1' when wbs_in.adr = REG83_ADR else '0';
reg84_adr_match_s <= '1' when wbs_in.adr = REG84_ADR else '0';
reg85_adr_match_s <= '1' when wbs_in.adr = REG85_ADR else '0';
reg86_adr_match_s <= '1' when wbs_in.adr = REG86_ADR else '0';
reg87_adr_match_s <= '1' when wbs_in.adr = REG87_ADR else '0';
reg88_adr_match_s <= '1' when wbs_in.adr = REG88_ADR else '0';
reg89_adr_match_s <= '1' when wbs_in.adr = REG89_ADR else '0';
reg90_adr_match_s <= '1' when wbs_in.adr = REG90_ADR else '0';
reg91_adr_match_s <= '1' when wbs_in.adr = REG91_ADR else '0';
reg92_adr_match_s <= '1' when wbs_in.adr = REG92_ADR else '0';
reg93_adr_match_s <= '1' when wbs_in.adr = REG93_ADR else '0';
reg94_adr_match_s <= '1' when wbs_in.adr = REG94_ADR else '0';
reg95_adr_match_s <= '1' when wbs_in.adr = REG95_ADR else '0';
reg96_adr_match_s <= '1' when wbs_in.adr = REG96_ADR else '0';
reg97_adr_match_s <= '1' when wbs_in.adr = REG97_ADR else '0';
reg98_adr_match_s <= '1' when wbs_in.adr = REG98_ADR else '0';
reg99_adr_match_s <= '1' when wbs_in.adr = REG99_ADR else '0';
reg100_adr_match_s <= '1' when wbs_in.adr = REG100_ADR else '0';
reg101_adr_match_s <= '1' when wbs_in.adr = REG101_ADR else '0';
reg102_adr_match_s <= '1' when wbs_in.adr = REG102_ADR else '0';
reg103_adr_match_s <= '1' when wbs_in.adr = REG103_ADR else '0';
reg104_adr_match_s <= '1' when wbs_in.adr = REG104_ADR else '0';
reg105_adr_match_s <= '1' when wbs_in.adr = REG105_ADR else '0';
reg106_adr_match_s <= '1' when wbs_in.adr = REG106_ADR else '0';
reg107_adr_match_s <= '1' when wbs_in.adr = REG107_ADR else '0';
reg108_adr_match_s <= '1' when wbs_in.adr = REG108_ADR else '0';
reg109_adr_match_s <= '1' when wbs_in.adr = REG109_ADR else '0';
reg110_adr_match_s <= '1' when wbs_in.adr = REG110_ADR else '0';
reg111_adr_match_s <= '1' when wbs_in.adr = REG111_ADR else '0';
reg112_adr_match_s <= '1' when wbs_in.adr = REG112_ADR else '0';
reg113_adr_match_s <= '1' when wbs_in.adr = REG113_ADR else '0';
reg114_adr_match_s <= '1' when wbs_in.adr = REG114_ADR else '0';
reg115_adr_match_s <= '1' when wbs_in.adr = REG115_ADR else '0';
reg116_adr_match_s <= '1' when wbs_in.adr = REG116_ADR else '0';
reg117_adr_match_s <= '1' when wbs_in.adr = REG117_ADR else '0';
reg118_adr_match_s <= '1' when wbs_in.adr = REG118_ADR else '0';
reg119_adr_match_s <= '1' when wbs_in.adr = REG119_ADR else '0';
reg120_adr_match_s <= '1' when wbs_in.adr = REG120_ADR else '0';
reg121_adr_match_s <= '1' when wbs_in.adr = REG121_ADR else '0';
reg122_adr_match_s <= '1' when wbs_in.adr = REG122_ADR else '0';
reg123_adr_match_s <= '1' when wbs_in.adr = REG123_ADR else '0';
reg124_adr_match_s <= '1' when wbs_in.adr = REG124_ADR else '0';
reg125_adr_match_s <= '1' when wbs_in.adr = REG125_ADR else '0';
reg126_adr_match_s <= '1' when wbs_in.adr = REG126_ADR else '0';
reg127_adr_match_s <= '1' when wbs_in.adr = REG127_ADR else '0';
reg128_adr_match_s <= '1' when wbs_in.adr = REG128_ADR else '0';
reg129_adr_match_s <= '1' when wbs_in.adr = REG129_ADR else '0';
reg130_adr_match_s <= '1' when wbs_in.adr = REG130_ADR else '0';
reg131_adr_match_s <= '1' when wbs_in.adr = REG131_ADR else '0';
reg132_adr_match_s <= '1' when wbs_in.adr = REG132_ADR else '0';
reg133_adr_match_s <= '1' when wbs_in.adr = REG133_ADR else '0';
reg134_adr_match_s <= '1' when wbs_in.adr = REG134_ADR else '0';
reg135_adr_match_s <= '1' when wbs_in.adr = REG135_ADR else '0';
reg136_adr_match_s <= '1' when wbs_in.adr = REG136_ADR else '0';
reg137_adr_match_s <= '1' when wbs_in.adr = REG137_ADR else '0';
reg138_adr_match_s <= '1' when wbs_in.adr = REG138_ADR else '0';
reg139_adr_match_s <= '1' when wbs_in.adr = REG139_ADR else '0';
reg140_adr_match_s <= '1' when wbs_in.adr = REG140_ADR else '0';
reg141_adr_match_s <= '1' when wbs_in.adr = REG141_ADR else '0';
reg142_adr_match_s <= '1' when wbs_in.adr = REG142_ADR else '0';
reg143_adr_match_s <= '1' when wbs_in.adr = REG143_ADR else '0';
reg144_adr_match_s <= '1' when wbs_in.adr = REG144_ADR else '0';
reg145_adr_match_s <= '1' when wbs_in.adr = REG145_ADR else '0';
reg146_adr_match_s <= '1' when wbs_in.adr = REG146_ADR else '0';
reg147_adr_match_s <= '1' when wbs_in.adr = REG147_ADR else '0';
reg148_adr_match_s <= '1' when wbs_in.adr = REG148_ADR else '0';
reg149_adr_match_s <= '1' when wbs_in.adr = REG149_ADR else '0';
reg150_adr_match_s <= '1' when wbs_in.adr = REG150_ADR else '0';
reg151_adr_match_s <= '1' when wbs_in.adr = REG151_ADR else '0';
reg152_adr_match_s <= '1' when wbs_in.adr = REG152_ADR else '0';
reg153_adr_match_s <= '1' when wbs_in.adr = REG153_ADR else '0';
reg154_adr_match_s <= '1' when wbs_in.adr = REG154_ADR else '0';
reg155_adr_match_s <= '1' when wbs_in.adr = REG155_ADR else '0';
reg156_adr_match_s <= '1' when wbs_in.adr = REG156_ADR else '0';
reg157_adr_match_s <= '1' when wbs_in.adr = REG157_ADR else '0';
reg158_adr_match_s <= '1' when wbs_in.adr = REG158_ADR else '0';
reg159_adr_match_s <= '1' when wbs_in.adr = REG159_ADR else '0';
reg160_adr_match_s <= '1' when wbs_in.adr = REG160_ADR else '0';
reg161_adr_match_s <= '1' when wbs_in.adr = REG161_ADR else '0';
reg162_adr_match_s <= '1' when wbs_in.adr = REG162_ADR else '0';
reg163_adr_match_s <= '1' when wbs_in.adr = REG163_ADR else '0';
reg164_adr_match_s <= '1' when wbs_in.adr = REG164_ADR else '0';
reg165_adr_match_s <= '1' when wbs_in.adr = REG165_ADR else '0';
reg166_adr_match_s <= '1' when wbs_in.adr = REG166_ADR else '0';
reg167_adr_match_s <= '1' when wbs_in.adr = REG167_ADR else '0';
reg168_adr_match_s <= '1' when wbs_in.adr = REG168_ADR else '0';
reg169_adr_match_s <= '1' when wbs_in.adr = REG169_ADR else '0';
reg170_adr_match_s <= '1' when wbs_in.adr = REG170_ADR else '0';
reg171_adr_match_s <= '1' when wbs_in.adr = REG171_ADR else '0';
reg172_adr_match_s <= '1' when wbs_in.adr = REG172_ADR else '0';
reg173_adr_match_s <= '1' when wbs_in.adr = REG173_ADR else '0';
reg174_adr_match_s <= '1' when wbs_in.adr = REG174_ADR else '0';
reg175_adr_match_s <= '1' when wbs_in.adr = REG175_ADR else '0';
reg176_adr_match_s <= '1' when wbs_in.adr = REG176_ADR else '0';
reg177_adr_match_s <= '1' when wbs_in.adr = REG177_ADR else '0';
reg178_adr_match_s <= '1' when wbs_in.adr = REG178_ADR else '0';
reg179_adr_match_s <= '1' when wbs_in.adr = REG179_ADR else '0';
reg180_adr_match_s <= '1' when wbs_in.adr = REG180_ADR else '0';
reg181_adr_match_s <= '1' when wbs_in.adr = REG181_ADR else '0';
reg182_adr_match_s <= '1' when wbs_in.adr = REG182_ADR else '0';
reg183_adr_match_s <= '1' when wbs_in.adr = REG183_ADR else '0';
reg184_adr_match_s <= '1' when wbs_in.adr = REG184_ADR else '0';
reg185_adr_match_s <= '1' when wbs_in.adr = REG185_ADR else '0';
reg186_adr_match_s <= '1' when wbs_in.adr = REG186_ADR else '0';
reg187_adr_match_s <= '1' when wbs_in.adr = REG187_ADR else '0';
reg188_adr_match_s <= '1' when wbs_in.adr = REG188_ADR else '0';
reg189_adr_match_s <= '1' when wbs_in.adr = REG189_ADR else '0';
reg190_adr_match_s <= '1' when wbs_in.adr = REG190_ADR else '0';
reg191_adr_match_s <= '1' when wbs_in.adr = REG191_ADR else '0';
reg192_adr_match_s <= '1' when wbs_in.adr = REG192_ADR else '0';
reg193_adr_match_s <= '1' when wbs_in.adr = REG193_ADR else '0';
reg194_adr_match_s <= '1' when wbs_in.adr = REG194_ADR else '0';
reg195_adr_match_s <= '1' when wbs_in.adr = REG195_ADR else '0';
reg196_adr_match_s <= '1' when wbs_in.adr = REG196_ADR else '0';
reg197_adr_match_s <= '1' when wbs_in.adr = REG197_ADR else '0';
reg198_adr_match_s <= '1' when wbs_in.adr = REG198_ADR else '0';
reg199_adr_match_s <= '1' when wbs_in.adr = REG199_ADR else '0';
reg200_adr_match_s <= '1' when wbs_in.adr = REG200_ADR else '0';
reg201_adr_match_s <= '1' when wbs_in.adr = REG201_ADR else '0';
reg202_adr_match_s <= '1' when wbs_in.adr = REG202_ADR else '0';
reg203_adr_match_s <= '1' when wbs_in.adr = REG203_ADR else '0';
reg204_adr_match_s <= '1' when wbs_in.adr = REG204_ADR else '0';
reg205_adr_match_s <= '1' when wbs_in.adr = REG205_ADR else '0';
reg206_adr_match_s <= '1' when wbs_in.adr = REG206_ADR else '0';
reg207_adr_match_s <= '1' when wbs_in.adr = REG207_ADR else '0';
reg208_adr_match_s <= '1' when wbs_in.adr = REG208_ADR else '0';
reg209_adr_match_s <= '1' when wbs_in.adr = REG209_ADR else '0';
reg210_adr_match_s <= '1' when wbs_in.adr = REG210_ADR else '0';
reg211_adr_match_s <= '1' when wbs_in.adr = REG211_ADR else '0';
reg212_adr_match_s <= '1' when wbs_in.adr = REG212_ADR else '0';
reg213_adr_match_s <= '1' when wbs_in.adr = REG213_ADR else '0';
reg214_adr_match_s <= '1' when wbs_in.adr = REG214_ADR else '0';
reg215_adr_match_s <= '1' when wbs_in.adr = REG215_ADR else '0';
reg216_adr_match_s <= '1' when wbs_in.adr = REG216_ADR else '0';
reg217_adr_match_s <= '1' when wbs_in.adr = REG217_ADR else '0';
reg218_adr_match_s <= '1' when wbs_in.adr = REG218_ADR else '0';
reg219_adr_match_s <= '1' when wbs_in.adr = REG219_ADR else '0';
reg220_adr_match_s <= '1' when wbs_in.adr = REG220_ADR else '0';
reg221_adr_match_s <= '1' when wbs_in.adr = REG221_ADR else '0';
reg222_adr_match_s <= '1' when wbs_in.adr = REG222_ADR else '0';
reg223_adr_match_s <= '1' when wbs_in.adr = REG223_ADR else '0';
reg224_adr_match_s <= '1' when wbs_in.adr = REG224_ADR else '0';
reg225_adr_match_s <= '1' when wbs_in.adr = REG225_ADR else '0';
reg226_adr_match_s <= '1' when wbs_in.adr = REG226_ADR else '0';
reg227_adr_match_s <= '1' when wbs_in.adr = REG227_ADR else '0';
reg228_adr_match_s <= '1' when wbs_in.adr = REG228_ADR else '0';
reg229_adr_match_s <= '1' when wbs_in.adr = REG229_ADR else '0';
reg230_adr_match_s <= '1' when wbs_in.adr = REG230_ADR else '0';
reg231_adr_match_s <= '1' when wbs_in.adr = REG231_ADR else '0';
reg232_adr_match_s <= '1' when wbs_in.adr = REG232_ADR else '0';
reg233_adr_match_s <= '1' when wbs_in.adr = REG233_ADR else '0';
reg234_adr_match_s <= '1' when wbs_in.adr = REG234_ADR else '0';
reg235_adr_match_s <= '1' when wbs_in.adr = REG235_ADR else '0';
reg236_adr_match_s <= '1' when wbs_in.adr = REG236_ADR else '0';
reg237_adr_match_s <= '1' when wbs_in.adr = REG237_ADR else '0';
reg238_adr_match_s <= '1' when wbs_in.adr = REG238_ADR else '0';
reg239_adr_match_s <= '1' when wbs_in.adr = REG239_ADR else '0';
reg240_adr_match_s <= '1' when wbs_in.adr = REG240_ADR else '0';
reg241_adr_match_s <= '1' when wbs_in.adr = REG241_ADR else '0';
reg242_adr_match_s <= '1' when wbs_in.adr = REG242_ADR else '0';
reg243_adr_match_s <= '1' when wbs_in.adr = REG243_ADR else '0';
reg244_adr_match_s <= '1' when wbs_in.adr = REG244_ADR else '0';
reg245_adr_match_s <= '1' when wbs_in.adr = REG245_ADR else '0';
reg246_adr_match_s <= '1' when wbs_in.adr = REG246_ADR else '0';
reg247_adr_match_s <= '1' when wbs_in.adr = REG247_ADR else '0';
reg248_adr_match_s <= '1' when wbs_in.adr = REG248_ADR else '0';
reg249_adr_match_s <= '1' when wbs_in.adr = REG249_ADR else '0';
reg250_adr_match_s <= '1' when wbs_in.adr = REG250_ADR else '0';
reg251_adr_match_s <= '1' when wbs_in.adr = REG251_ADR else '0';
reg252_adr_match_s <= '1' when wbs_in.adr = REG252_ADR else '0';
reg253_adr_match_s <= '1' when wbs_in.adr = REG253_ADR else '0';
reg254_adr_match_s <= '1' when wbs_in.adr = REG254_ADR else '0';
reg255_adr_match_s <= '1' when wbs_in.adr = REG255_ADR else '0';
-- register enable signals
reg0_re_s <= wbs_in.stb AND wbs_in.we AND reg0_adr_match_s;
reg1_re_s <= wbs_in.stb AND wbs_in.we AND reg1_adr_match_s;
reg2_re_s <= wbs_in.stb AND wbs_in.we AND reg2_adr_match_s;
reg3_re_s <= wbs_in.stb AND wbs_in.we AND reg3_adr_match_s;
reg4_re_s <= wbs_in.stb AND wbs_in.we AND reg4_adr_match_s;
reg5_re_s <= wbs_in.stb AND wbs_in.we AND reg5_adr_match_s;
reg6_re_s <= wbs_in.stb AND wbs_in.we AND reg6_adr_match_s;
reg7_re_s <= wbs_in.stb AND wbs_in.we AND reg7_adr_match_s;
reg8_re_s <= wbs_in.stb AND wbs_in.we AND reg8_adr_match_s;
reg9_re_s <= wbs_in.stb AND wbs_in.we AND reg9_adr_match_s;
reg10_re_s <= wbs_in.stb AND wbs_in.we AND reg10_adr_match_s;
reg11_re_s <= wbs_in.stb AND wbs_in.we AND reg11_adr_match_s;
reg12_re_s <= wbs_in.stb AND wbs_in.we AND reg12_adr_match_s;
reg13_re_s <= wbs_in.stb AND wbs_in.we AND reg13_adr_match_s;
reg14_re_s <= wbs_in.stb AND wbs_in.we AND reg14_adr_match_s;
reg15_re_s <= wbs_in.stb AND wbs_in.we AND reg15_adr_match_s;
reg16_re_s <= wbs_in.stb AND wbs_in.we AND reg16_adr_match_s;
reg17_re_s <= wbs_in.stb AND wbs_in.we AND reg17_adr_match_s;
reg18_re_s <= wbs_in.stb AND wbs_in.we AND reg18_adr_match_s;
reg19_re_s <= wbs_in.stb AND wbs_in.we AND reg19_adr_match_s;
reg20_re_s <= wbs_in.stb AND wbs_in.we AND reg20_adr_match_s;
reg21_re_s <= wbs_in.stb AND wbs_in.we AND reg21_adr_match_s;
reg22_re_s <= wbs_in.stb AND wbs_in.we AND reg22_adr_match_s;
reg23_re_s <= wbs_in.stb AND wbs_in.we AND reg23_adr_match_s;
reg24_re_s <= wbs_in.stb AND wbs_in.we AND reg24_adr_match_s;
reg25_re_s <= wbs_in.stb AND wbs_in.we AND reg25_adr_match_s;
reg26_re_s <= wbs_in.stb AND wbs_in.we AND reg26_adr_match_s;
reg27_re_s <= wbs_in.stb AND wbs_in.we AND reg27_adr_match_s;
reg28_re_s <= wbs_in.stb AND wbs_in.we AND reg28_adr_match_s;
reg29_re_s <= wbs_in.stb AND wbs_in.we AND reg29_adr_match_s;
reg30_re_s <= wbs_in.stb AND wbs_in.we AND reg30_adr_match_s;
reg31_re_s <= wbs_in.stb AND wbs_in.we AND reg31_adr_match_s;
reg32_re_s <= wbs_in.stb AND wbs_in.we AND reg32_adr_match_s;
reg33_re_s <= wbs_in.stb AND wbs_in.we AND reg33_adr_match_s;
reg34_re_s <= wbs_in.stb AND wbs_in.we AND reg34_adr_match_s;
reg35_re_s <= wbs_in.stb AND wbs_in.we AND reg35_adr_match_s;
reg36_re_s <= wbs_in.stb AND wbs_in.we AND reg36_adr_match_s;
reg37_re_s <= wbs_in.stb AND wbs_in.we AND reg37_adr_match_s;
reg38_re_s <= wbs_in.stb AND wbs_in.we AND reg38_adr_match_s;
reg39_re_s <= wbs_in.stb AND wbs_in.we AND reg39_adr_match_s;
reg40_re_s <= wbs_in.stb AND wbs_in.we AND reg40_adr_match_s;
reg41_re_s <= wbs_in.stb AND wbs_in.we AND reg41_adr_match_s;
reg42_re_s <= wbs_in.stb AND wbs_in.we AND reg42_adr_match_s;
reg43_re_s <= wbs_in.stb AND wbs_in.we AND reg43_adr_match_s;
reg44_re_s <= wbs_in.stb AND wbs_in.we AND reg44_adr_match_s;
reg45_re_s <= wbs_in.stb AND wbs_in.we AND reg45_adr_match_s;
reg46_re_s <= wbs_in.stb AND wbs_in.we AND reg46_adr_match_s;
reg47_re_s <= wbs_in.stb AND wbs_in.we AND reg47_adr_match_s;
reg48_re_s <= wbs_in.stb AND wbs_in.we AND reg48_adr_match_s;
reg49_re_s <= wbs_in.stb AND wbs_in.we AND reg49_adr_match_s;
reg50_re_s <= wbs_in.stb AND wbs_in.we AND reg50_adr_match_s;
reg51_re_s <= wbs_in.stb AND wbs_in.we AND reg51_adr_match_s;
reg52_re_s <= wbs_in.stb AND wbs_in.we AND reg52_adr_match_s;
reg53_re_s <= wbs_in.stb AND wbs_in.we AND reg53_adr_match_s;
reg54_re_s <= wbs_in.stb AND wbs_in.we AND reg54_adr_match_s;
reg55_re_s <= wbs_in.stb AND wbs_in.we AND reg55_adr_match_s;
reg56_re_s <= wbs_in.stb AND wbs_in.we AND reg56_adr_match_s;
reg57_re_s <= wbs_in.stb AND wbs_in.we AND reg57_adr_match_s;
reg58_re_s <= wbs_in.stb AND wbs_in.we AND reg58_adr_match_s;
reg59_re_s <= wbs_in.stb AND wbs_in.we AND reg59_adr_match_s;
reg60_re_s <= wbs_in.stb AND wbs_in.we AND reg60_adr_match_s;
reg61_re_s <= wbs_in.stb AND wbs_in.we AND reg61_adr_match_s;
reg62_re_s <= wbs_in.stb AND wbs_in.we AND reg62_adr_match_s;
reg63_re_s <= wbs_in.stb AND wbs_in.we AND reg63_adr_match_s;
reg64_re_s <= wbs_in.stb AND wbs_in.we AND reg64_adr_match_s;
reg65_re_s <= wbs_in.stb AND wbs_in.we AND reg65_adr_match_s;
reg66_re_s <= wbs_in.stb AND wbs_in.we AND reg66_adr_match_s;
reg67_re_s <= wbs_in.stb AND wbs_in.we AND reg67_adr_match_s;
reg68_re_s <= wbs_in.stb AND wbs_in.we AND reg68_adr_match_s;
reg69_re_s <= wbs_in.stb AND wbs_in.we AND reg69_adr_match_s;
reg70_re_s <= wbs_in.stb AND wbs_in.we AND reg70_adr_match_s;
reg71_re_s <= wbs_in.stb AND wbs_in.we AND reg71_adr_match_s;
reg72_re_s <= wbs_in.stb AND wbs_in.we AND reg72_adr_match_s;
reg73_re_s <= wbs_in.stb AND wbs_in.we AND reg73_adr_match_s;
reg74_re_s <= wbs_in.stb AND wbs_in.we AND reg74_adr_match_s;
reg75_re_s <= wbs_in.stb AND wbs_in.we AND reg75_adr_match_s;
reg76_re_s <= wbs_in.stb AND wbs_in.we AND reg76_adr_match_s;
reg77_re_s <= wbs_in.stb AND wbs_in.we AND reg77_adr_match_s;
reg78_re_s <= wbs_in.stb AND wbs_in.we AND reg78_adr_match_s;
reg79_re_s <= wbs_in.stb AND wbs_in.we AND reg79_adr_match_s;
reg80_re_s <= wbs_in.stb AND wbs_in.we AND reg80_adr_match_s;
reg81_re_s <= wbs_in.stb AND wbs_in.we AND reg81_adr_match_s;
reg82_re_s <= wbs_in.stb AND wbs_in.we AND reg82_adr_match_s;
reg83_re_s <= wbs_in.stb AND wbs_in.we AND reg83_adr_match_s;
reg84_re_s <= wbs_in.stb AND wbs_in.we AND reg84_adr_match_s;
reg85_re_s <= wbs_in.stb AND wbs_in.we AND reg85_adr_match_s;
reg86_re_s <= wbs_in.stb AND wbs_in.we AND reg86_adr_match_s;
reg87_re_s <= wbs_in.stb AND wbs_in.we AND reg87_adr_match_s;
reg88_re_s <= wbs_in.stb AND wbs_in.we AND reg88_adr_match_s;
reg89_re_s <= wbs_in.stb AND wbs_in.we AND reg89_adr_match_s;
reg90_re_s <= wbs_in.stb AND wbs_in.we AND reg90_adr_match_s;
reg91_re_s <= wbs_in.stb AND wbs_in.we AND reg91_adr_match_s;
reg92_re_s <= wbs_in.stb AND wbs_in.we AND reg92_adr_match_s;
reg93_re_s <= wbs_in.stb AND wbs_in.we AND reg93_adr_match_s;
reg94_re_s <= wbs_in.stb AND wbs_in.we AND reg94_adr_match_s;
reg95_re_s <= wbs_in.stb AND wbs_in.we AND reg95_adr_match_s;
reg96_re_s <= wbs_in.stb AND wbs_in.we AND reg96_adr_match_s;
reg97_re_s <= wbs_in.stb AND wbs_in.we AND reg97_adr_match_s;
reg98_re_s <= wbs_in.stb AND wbs_in.we AND reg98_adr_match_s;
reg99_re_s <= wbs_in.stb AND wbs_in.we AND reg99_adr_match_s;
reg100_re_s <= wbs_in.stb AND wbs_in.we AND reg100_adr_match_s;
reg101_re_s <= wbs_in.stb AND wbs_in.we AND reg101_adr_match_s;
reg102_re_s <= wbs_in.stb AND wbs_in.we AND reg102_adr_match_s;
reg103_re_s <= wbs_in.stb AND wbs_in.we AND reg103_adr_match_s;
reg104_re_s <= wbs_in.stb AND wbs_in.we AND reg104_adr_match_s;
reg105_re_s <= wbs_in.stb AND wbs_in.we AND reg105_adr_match_s;
reg106_re_s <= wbs_in.stb AND wbs_in.we AND reg106_adr_match_s;
reg107_re_s <= wbs_in.stb AND wbs_in.we AND reg107_adr_match_s;
reg108_re_s <= wbs_in.stb AND wbs_in.we AND reg108_adr_match_s;
reg109_re_s <= wbs_in.stb AND wbs_in.we AND reg109_adr_match_s;
reg110_re_s <= wbs_in.stb AND wbs_in.we AND reg110_adr_match_s;
reg111_re_s <= wbs_in.stb AND wbs_in.we AND reg111_adr_match_s;
reg112_re_s <= wbs_in.stb AND wbs_in.we AND reg112_adr_match_s;
reg113_re_s <= wbs_in.stb AND wbs_in.we AND reg113_adr_match_s;
reg114_re_s <= wbs_in.stb AND wbs_in.we AND reg114_adr_match_s;
reg115_re_s <= wbs_in.stb AND wbs_in.we AND reg115_adr_match_s;
reg116_re_s <= wbs_in.stb AND wbs_in.we AND reg116_adr_match_s;
reg117_re_s <= wbs_in.stb AND wbs_in.we AND reg117_adr_match_s;
reg118_re_s <= wbs_in.stb AND wbs_in.we AND reg118_adr_match_s;
reg119_re_s <= wbs_in.stb AND wbs_in.we AND reg119_adr_match_s;
reg120_re_s <= wbs_in.stb AND wbs_in.we AND reg120_adr_match_s;
reg121_re_s <= wbs_in.stb AND wbs_in.we AND reg121_adr_match_s;
reg122_re_s <= wbs_in.stb AND wbs_in.we AND reg122_adr_match_s;
reg123_re_s <= wbs_in.stb AND wbs_in.we AND reg123_adr_match_s;
reg124_re_s <= wbs_in.stb AND wbs_in.we AND reg124_adr_match_s;
reg125_re_s <= wbs_in.stb AND wbs_in.we AND reg125_adr_match_s;
reg126_re_s <= wbs_in.stb AND wbs_in.we AND reg126_adr_match_s;
reg127_re_s <= wbs_in.stb AND wbs_in.we AND reg127_adr_match_s;
reg128_re_s <= wbs_in.stb AND wbs_in.we AND reg128_adr_match_s;
reg129_re_s <= wbs_in.stb AND wbs_in.we AND reg129_adr_match_s;
reg130_re_s <= wbs_in.stb AND wbs_in.we AND reg130_adr_match_s;
reg131_re_s <= wbs_in.stb AND wbs_in.we AND reg131_adr_match_s;
reg132_re_s <= wbs_in.stb AND wbs_in.we AND reg132_adr_match_s;
reg133_re_s <= wbs_in.stb AND wbs_in.we AND reg133_adr_match_s;
reg134_re_s <= wbs_in.stb AND wbs_in.we AND reg134_adr_match_s;
reg135_re_s <= wbs_in.stb AND wbs_in.we AND reg135_adr_match_s;
reg136_re_s <= wbs_in.stb AND wbs_in.we AND reg136_adr_match_s;
reg137_re_s <= wbs_in.stb AND wbs_in.we AND reg137_adr_match_s;
reg138_re_s <= wbs_in.stb AND wbs_in.we AND reg138_adr_match_s;
reg139_re_s <= wbs_in.stb AND wbs_in.we AND reg139_adr_match_s;
reg140_re_s <= wbs_in.stb AND wbs_in.we AND reg140_adr_match_s;
reg141_re_s <= wbs_in.stb AND wbs_in.we AND reg141_adr_match_s;
reg142_re_s <= wbs_in.stb AND wbs_in.we AND reg142_adr_match_s;
reg143_re_s <= wbs_in.stb AND wbs_in.we AND reg143_adr_match_s;
reg144_re_s <= wbs_in.stb AND wbs_in.we AND reg144_adr_match_s;
reg145_re_s <= wbs_in.stb AND wbs_in.we AND reg145_adr_match_s;
reg146_re_s <= wbs_in.stb AND wbs_in.we AND reg146_adr_match_s;
reg147_re_s <= wbs_in.stb AND wbs_in.we AND reg147_adr_match_s;
reg148_re_s <= wbs_in.stb AND wbs_in.we AND reg148_adr_match_s;
reg149_re_s <= wbs_in.stb AND wbs_in.we AND reg149_adr_match_s;
reg150_re_s <= wbs_in.stb AND wbs_in.we AND reg150_adr_match_s;
reg151_re_s <= wbs_in.stb AND wbs_in.we AND reg151_adr_match_s;
reg152_re_s <= wbs_in.stb AND wbs_in.we AND reg152_adr_match_s;
reg153_re_s <= wbs_in.stb AND wbs_in.we AND reg153_adr_match_s;
reg154_re_s <= wbs_in.stb AND wbs_in.we AND reg154_adr_match_s;
reg155_re_s <= wbs_in.stb AND wbs_in.we AND reg155_adr_match_s;
reg156_re_s <= wbs_in.stb AND wbs_in.we AND reg156_adr_match_s;
reg157_re_s <= wbs_in.stb AND wbs_in.we AND reg157_adr_match_s;
reg158_re_s <= wbs_in.stb AND wbs_in.we AND reg158_adr_match_s;
reg159_re_s <= wbs_in.stb AND wbs_in.we AND reg159_adr_match_s;
reg160_re_s <= wbs_in.stb AND wbs_in.we AND reg160_adr_match_s;
reg161_re_s <= wbs_in.stb AND wbs_in.we AND reg161_adr_match_s;
reg162_re_s <= wbs_in.stb AND wbs_in.we AND reg162_adr_match_s;
reg163_re_s <= wbs_in.stb AND wbs_in.we AND reg163_adr_match_s;
reg164_re_s <= wbs_in.stb AND wbs_in.we AND reg164_adr_match_s;
reg165_re_s <= wbs_in.stb AND wbs_in.we AND reg165_adr_match_s;
reg166_re_s <= wbs_in.stb AND wbs_in.we AND reg166_adr_match_s;
reg167_re_s <= wbs_in.stb AND wbs_in.we AND reg167_adr_match_s;
reg168_re_s <= wbs_in.stb AND wbs_in.we AND reg168_adr_match_s;
reg169_re_s <= wbs_in.stb AND wbs_in.we AND reg169_adr_match_s;
reg170_re_s <= wbs_in.stb AND wbs_in.we AND reg170_adr_match_s;
reg171_re_s <= wbs_in.stb AND wbs_in.we AND reg171_adr_match_s;
reg172_re_s <= wbs_in.stb AND wbs_in.we AND reg172_adr_match_s;
reg173_re_s <= wbs_in.stb AND wbs_in.we AND reg173_adr_match_s;
reg174_re_s <= wbs_in.stb AND wbs_in.we AND reg174_adr_match_s;
reg175_re_s <= wbs_in.stb AND wbs_in.we AND reg175_adr_match_s;
reg176_re_s <= wbs_in.stb AND wbs_in.we AND reg176_adr_match_s;
reg177_re_s <= wbs_in.stb AND wbs_in.we AND reg177_adr_match_s;
reg178_re_s <= wbs_in.stb AND wbs_in.we AND reg178_adr_match_s;
reg179_re_s <= wbs_in.stb AND wbs_in.we AND reg179_adr_match_s;
reg180_re_s <= wbs_in.stb AND wbs_in.we AND reg180_adr_match_s;
reg181_re_s <= wbs_in.stb AND wbs_in.we AND reg181_adr_match_s;
reg182_re_s <= wbs_in.stb AND wbs_in.we AND reg182_adr_match_s;
reg183_re_s <= wbs_in.stb AND wbs_in.we AND reg183_adr_match_s;
reg184_re_s <= wbs_in.stb AND wbs_in.we AND reg184_adr_match_s;
reg185_re_s <= wbs_in.stb AND wbs_in.we AND reg185_adr_match_s;
reg186_re_s <= wbs_in.stb AND wbs_in.we AND reg186_adr_match_s;
reg187_re_s <= wbs_in.stb AND wbs_in.we AND reg187_adr_match_s;
reg188_re_s <= wbs_in.stb AND wbs_in.we AND reg188_adr_match_s;
reg189_re_s <= wbs_in.stb AND wbs_in.we AND reg189_adr_match_s;
reg190_re_s <= wbs_in.stb AND wbs_in.we AND reg190_adr_match_s;
reg191_re_s <= wbs_in.stb AND wbs_in.we AND reg191_adr_match_s;
reg192_re_s <= wbs_in.stb AND wbs_in.we AND reg192_adr_match_s;
reg193_re_s <= wbs_in.stb AND wbs_in.we AND reg193_adr_match_s;
reg194_re_s <= wbs_in.stb AND wbs_in.we AND reg194_adr_match_s;
reg195_re_s <= wbs_in.stb AND wbs_in.we AND reg195_adr_match_s;
reg196_re_s <= wbs_in.stb AND wbs_in.we AND reg196_adr_match_s;
reg197_re_s <= wbs_in.stb AND wbs_in.we AND reg197_adr_match_s;
reg198_re_s <= wbs_in.stb AND wbs_in.we AND reg198_adr_match_s;
reg199_re_s <= wbs_in.stb AND wbs_in.we AND reg199_adr_match_s;
reg200_re_s <= wbs_in.stb AND wbs_in.we AND reg200_adr_match_s;
reg201_re_s <= wbs_in.stb AND wbs_in.we AND reg201_adr_match_s;
reg202_re_s <= wbs_in.stb AND wbs_in.we AND reg202_adr_match_s;
reg203_re_s <= wbs_in.stb AND wbs_in.we AND reg203_adr_match_s;
reg204_re_s <= wbs_in.stb AND wbs_in.we AND reg204_adr_match_s;
reg205_re_s <= wbs_in.stb AND wbs_in.we AND reg205_adr_match_s;
reg206_re_s <= wbs_in.stb AND wbs_in.we AND reg206_adr_match_s;
reg207_re_s <= wbs_in.stb AND wbs_in.we AND reg207_adr_match_s;
reg208_re_s <= wbs_in.stb AND wbs_in.we AND reg208_adr_match_s;
reg209_re_s <= wbs_in.stb AND wbs_in.we AND reg209_adr_match_s;
reg210_re_s <= wbs_in.stb AND wbs_in.we AND reg210_adr_match_s;
reg211_re_s <= wbs_in.stb AND wbs_in.we AND reg211_adr_match_s;
reg212_re_s <= wbs_in.stb AND wbs_in.we AND reg212_adr_match_s;
reg213_re_s <= wbs_in.stb AND wbs_in.we AND reg213_adr_match_s;
reg214_re_s <= wbs_in.stb AND wbs_in.we AND reg214_adr_match_s;
reg215_re_s <= wbs_in.stb AND wbs_in.we AND reg215_adr_match_s;
reg216_re_s <= wbs_in.stb AND wbs_in.we AND reg216_adr_match_s;
reg217_re_s <= wbs_in.stb AND wbs_in.we AND reg217_adr_match_s;
reg218_re_s <= wbs_in.stb AND wbs_in.we AND reg218_adr_match_s;
reg219_re_s <= wbs_in.stb AND wbs_in.we AND reg219_adr_match_s;
reg220_re_s <= wbs_in.stb AND wbs_in.we AND reg220_adr_match_s;
reg221_re_s <= wbs_in.stb AND wbs_in.we AND reg221_adr_match_s;
reg222_re_s <= wbs_in.stb AND wbs_in.we AND reg222_adr_match_s;
reg223_re_s <= wbs_in.stb AND wbs_in.we AND reg223_adr_match_s;
reg224_re_s <= wbs_in.stb AND wbs_in.we AND reg224_adr_match_s;
reg225_re_s <= wbs_in.stb AND wbs_in.we AND reg225_adr_match_s;
reg226_re_s <= wbs_in.stb AND wbs_in.we AND reg226_adr_match_s;
reg227_re_s <= wbs_in.stb AND wbs_in.we AND reg227_adr_match_s;
reg228_re_s <= wbs_in.stb AND wbs_in.we AND reg228_adr_match_s;
reg229_re_s <= wbs_in.stb AND wbs_in.we AND reg229_adr_match_s;
reg230_re_s <= wbs_in.stb AND wbs_in.we AND reg230_adr_match_s;
reg231_re_s <= wbs_in.stb AND wbs_in.we AND reg231_adr_match_s;
reg232_re_s <= wbs_in.stb AND wbs_in.we AND reg232_adr_match_s;
reg233_re_s <= wbs_in.stb AND wbs_in.we AND reg233_adr_match_s;
reg234_re_s <= wbs_in.stb AND wbs_in.we AND reg234_adr_match_s;
reg235_re_s <= wbs_in.stb AND wbs_in.we AND reg235_adr_match_s;
reg236_re_s <= wbs_in.stb AND wbs_in.we AND reg236_adr_match_s;
reg237_re_s <= wbs_in.stb AND wbs_in.we AND reg237_adr_match_s;
reg238_re_s <= wbs_in.stb AND wbs_in.we AND reg238_adr_match_s;
reg239_re_s <= wbs_in.stb AND wbs_in.we AND reg239_adr_match_s;
reg240_re_s <= wbs_in.stb AND wbs_in.we AND reg240_adr_match_s;
reg241_re_s <= wbs_in.stb AND wbs_in.we AND reg241_adr_match_s;
reg242_re_s <= wbs_in.stb AND wbs_in.we AND reg242_adr_match_s;
reg243_re_s <= wbs_in.stb AND wbs_in.we AND reg243_adr_match_s;
reg244_re_s <= wbs_in.stb AND wbs_in.we AND reg244_adr_match_s;
reg245_re_s <= wbs_in.stb AND wbs_in.we AND reg245_adr_match_s;
reg246_re_s <= wbs_in.stb AND wbs_in.we AND reg246_adr_match_s;
reg247_re_s <= wbs_in.stb AND wbs_in.we AND reg247_adr_match_s;
reg248_re_s <= wbs_in.stb AND wbs_in.we AND reg248_adr_match_s;
reg249_re_s <= wbs_in.stb AND wbs_in.we AND reg249_adr_match_s;
reg250_re_s <= wbs_in.stb AND wbs_in.we AND reg250_adr_match_s;
reg251_re_s <= wbs_in.stb AND wbs_in.we AND reg251_adr_match_s;
reg252_re_s <= wbs_in.stb AND wbs_in.we AND reg252_adr_match_s;
reg253_re_s <= wbs_in.stb AND wbs_in.we AND reg253_adr_match_s;
reg254_re_s <= wbs_in.stb AND wbs_in.we AND reg254_adr_match_s;
reg255_re_s <= wbs_in.stb AND wbs_in.we AND reg255_adr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
reg_in_s.reg0 <= wbs_in.dat;
reg_in_s.reg1 <= wbs_in.dat;
reg_in_s.reg2 <= wbs_in.dat;
reg_in_s.reg3 <= wbs_in.dat;
reg_in_s.reg4 <= wbs_in.dat;
reg_in_s.reg5 <= wbs_in.dat;
reg_in_s.reg6 <= wbs_in.dat;
reg_in_s.reg7 <= wbs_in.dat;
reg_in_s.reg8 <= wbs_in.dat;
reg_in_s.reg9 <= wbs_in.dat;
reg_in_s.reg10 <= wbs_in.dat;
reg_in_s.reg11 <= wbs_in.dat;
reg_in_s.reg12 <= wbs_in.dat;
reg_in_s.reg13 <= wbs_in.dat;
reg_in_s.reg14 <= wbs_in.dat;
reg_in_s.reg15 <= wbs_in.dat;
reg_in_s.reg16 <= wbs_in.dat;
reg_in_s.reg17 <= wbs_in.dat;
reg_in_s.reg18 <= wbs_in.dat;
reg_in_s.reg19 <= wbs_in.dat;
reg_in_s.reg20 <= wbs_in.dat;
reg_in_s.reg21 <= wbs_in.dat;
reg_in_s.reg22 <= wbs_in.dat;
reg_in_s.reg23 <= wbs_in.dat;
reg_in_s.reg24 <= wbs_in.dat;
reg_in_s.reg25 <= wbs_in.dat;
reg_in_s.reg26 <= wbs_in.dat;
reg_in_s.reg27 <= wbs_in.dat;
reg_in_s.reg28 <= wbs_in.dat;
reg_in_s.reg29 <= wbs_in.dat;
reg_in_s.reg30 <= wbs_in.dat;
reg_in_s.reg31 <= wbs_in.dat;
reg_in_s.reg32 <= wbs_in.dat;
reg_in_s.reg33 <= wbs_in.dat;
reg_in_s.reg34 <= wbs_in.dat;
reg_in_s.reg35 <= wbs_in.dat;
reg_in_s.reg36 <= wbs_in.dat;
reg_in_s.reg37 <= wbs_in.dat;
reg_in_s.reg38 <= wbs_in.dat;
reg_in_s.reg39 <= wbs_in.dat;
reg_in_s.reg40 <= wbs_in.dat;
reg_in_s.reg41 <= wbs_in.dat;
reg_in_s.reg42 <= wbs_in.dat;
reg_in_s.reg43 <= wbs_in.dat;
reg_in_s.reg44 <= wbs_in.dat;
reg_in_s.reg45 <= wbs_in.dat;
reg_in_s.reg46 <= wbs_in.dat;
reg_in_s.reg47 <= wbs_in.dat;
reg_in_s.reg48 <= wbs_in.dat;
reg_in_s.reg49 <= wbs_in.dat;
reg_in_s.reg50 <= wbs_in.dat;
reg_in_s.reg51 <= wbs_in.dat;
reg_in_s.reg52 <= wbs_in.dat;
reg_in_s.reg53 <= wbs_in.dat;
reg_in_s.reg54 <= wbs_in.dat;
reg_in_s.reg55 <= wbs_in.dat;
reg_in_s.reg56 <= wbs_in.dat;
reg_in_s.reg57 <= wbs_in.dat;
reg_in_s.reg58 <= wbs_in.dat;
reg_in_s.reg59 <= wbs_in.dat;
reg_in_s.reg60 <= wbs_in.dat;
reg_in_s.reg61 <= wbs_in.dat;
reg_in_s.reg62 <= wbs_in.dat;
reg_in_s.reg63 <= wbs_in.dat;
reg_in_s.reg64 <= wbs_in.dat;
reg_in_s.reg65 <= wbs_in.dat;
reg_in_s.reg66 <= wbs_in.dat;
reg_in_s.reg67 <= wbs_in.dat;
reg_in_s.reg68 <= wbs_in.dat;
reg_in_s.reg69 <= wbs_in.dat;
reg_in_s.reg70 <= wbs_in.dat;
reg_in_s.reg71 <= wbs_in.dat;
reg_in_s.reg72 <= wbs_in.dat;
reg_in_s.reg73 <= wbs_in.dat;
reg_in_s.reg74 <= wbs_in.dat;
reg_in_s.reg75 <= wbs_in.dat;
reg_in_s.reg76 <= wbs_in.dat;
reg_in_s.reg77 <= wbs_in.dat;
reg_in_s.reg78 <= wbs_in.dat;
reg_in_s.reg79 <= wbs_in.dat;
reg_in_s.reg80 <= wbs_in.dat;
reg_in_s.reg81 <= wbs_in.dat;
reg_in_s.reg82 <= wbs_in.dat;
reg_in_s.reg83 <= wbs_in.dat;
reg_in_s.reg84 <= wbs_in.dat;
reg_in_s.reg85 <= wbs_in.dat;
reg_in_s.reg86 <= wbs_in.dat;
reg_in_s.reg87 <= wbs_in.dat;
reg_in_s.reg88 <= wbs_in.dat;
reg_in_s.reg89 <= wbs_in.dat;
reg_in_s.reg90 <= wbs_in.dat;
reg_in_s.reg91 <= wbs_in.dat;
reg_in_s.reg92 <= wbs_in.dat;
reg_in_s.reg93 <= wbs_in.dat;
reg_in_s.reg94 <= wbs_in.dat;
reg_in_s.reg95 <= wbs_in.dat;
reg_in_s.reg96 <= wbs_in.dat;
reg_in_s.reg97 <= wbs_in.dat;
reg_in_s.reg98 <= wbs_in.dat;
reg_in_s.reg99 <= wbs_in.dat;
reg_in_s.reg100 <= wbs_in.dat;
reg_in_s.reg101 <= wbs_in.dat;
reg_in_s.reg102 <= wbs_in.dat;
reg_in_s.reg103 <= wbs_in.dat;
reg_in_s.reg104 <= wbs_in.dat;
reg_in_s.reg105 <= wbs_in.dat;
reg_in_s.reg106 <= wbs_in.dat;
reg_in_s.reg107 <= wbs_in.dat;
reg_in_s.reg108 <= wbs_in.dat;
reg_in_s.reg109 <= wbs_in.dat;
reg_in_s.reg110 <= wbs_in.dat;
reg_in_s.reg111 <= wbs_in.dat;
reg_in_s.reg112 <= wbs_in.dat;
reg_in_s.reg113 <= wbs_in.dat;
reg_in_s.reg114 <= wbs_in.dat;
reg_in_s.reg115 <= wbs_in.dat;
reg_in_s.reg116 <= wbs_in.dat;
reg_in_s.reg117 <= wbs_in.dat;
reg_in_s.reg118 <= wbs_in.dat;
reg_in_s.reg119 <= wbs_in.dat;
reg_in_s.reg120 <= wbs_in.dat;
reg_in_s.reg121 <= wbs_in.dat;
reg_in_s.reg122 <= wbs_in.dat;
reg_in_s.reg123 <= wbs_in.dat;
reg_in_s.reg124 <= wbs_in.dat;
reg_in_s.reg125 <= wbs_in.dat;
reg_in_s.reg126 <= wbs_in.dat;
reg_in_s.reg127 <= wbs_in.dat;
reg_in_s.reg128 <= wbs_in.dat;
reg_in_s.reg129 <= wbs_in.dat;
reg_in_s.reg130 <= wbs_in.dat;
reg_in_s.reg131 <= wbs_in.dat;
reg_in_s.reg132 <= wbs_in.dat;
reg_in_s.reg133 <= wbs_in.dat;
reg_in_s.reg134 <= wbs_in.dat;
reg_in_s.reg135 <= wbs_in.dat;
reg_in_s.reg136 <= wbs_in.dat;
reg_in_s.reg137 <= wbs_in.dat;
reg_in_s.reg138 <= wbs_in.dat;
reg_in_s.reg139 <= wbs_in.dat;
reg_in_s.reg140 <= wbs_in.dat;
reg_in_s.reg141 <= wbs_in.dat;
reg_in_s.reg142 <= wbs_in.dat;
reg_in_s.reg143 <= wbs_in.dat;
reg_in_s.reg144 <= wbs_in.dat;
reg_in_s.reg145 <= wbs_in.dat;
reg_in_s.reg146 <= wbs_in.dat;
reg_in_s.reg147 <= wbs_in.dat;
reg_in_s.reg148 <= wbs_in.dat;
reg_in_s.reg149 <= wbs_in.dat;
reg_in_s.reg150 <= wbs_in.dat;
reg_in_s.reg151 <= wbs_in.dat;
reg_in_s.reg152 <= wbs_in.dat;
reg_in_s.reg153 <= wbs_in.dat;
reg_in_s.reg154 <= wbs_in.dat;
reg_in_s.reg155 <= wbs_in.dat;
reg_in_s.reg156 <= wbs_in.dat;
reg_in_s.reg157 <= wbs_in.dat;
reg_in_s.reg158 <= wbs_in.dat;
reg_in_s.reg159 <= wbs_in.dat;
reg_in_s.reg160 <= wbs_in.dat;
reg_in_s.reg161 <= wbs_in.dat;
reg_in_s.reg162 <= wbs_in.dat;
reg_in_s.reg163 <= wbs_in.dat;
reg_in_s.reg164 <= wbs_in.dat;
reg_in_s.reg165 <= wbs_in.dat;
reg_in_s.reg166 <= wbs_in.dat;
reg_in_s.reg167 <= wbs_in.dat;
reg_in_s.reg168 <= wbs_in.dat;
reg_in_s.reg169 <= wbs_in.dat;
reg_in_s.reg170 <= wbs_in.dat;
reg_in_s.reg171 <= wbs_in.dat;
reg_in_s.reg172 <= wbs_in.dat;
reg_in_s.reg173 <= wbs_in.dat;
reg_in_s.reg174 <= wbs_in.dat;
reg_in_s.reg175 <= wbs_in.dat;
reg_in_s.reg176 <= wbs_in.dat;
reg_in_s.reg177 <= wbs_in.dat;
reg_in_s.reg178 <= wbs_in.dat;
reg_in_s.reg179 <= wbs_in.dat;
reg_in_s.reg180 <= wbs_in.dat;
reg_in_s.reg181 <= wbs_in.dat;
reg_in_s.reg182 <= wbs_in.dat;
reg_in_s.reg183 <= wbs_in.dat;
reg_in_s.reg184 <= wbs_in.dat;
reg_in_s.reg185 <= wbs_in.dat;
reg_in_s.reg186 <= wbs_in.dat;
reg_in_s.reg187 <= wbs_in.dat;
reg_in_s.reg188 <= wbs_in.dat;
reg_in_s.reg189 <= wbs_in.dat;
reg_in_s.reg190 <= wbs_in.dat;
reg_in_s.reg191 <= wbs_in.dat;
reg_in_s.reg192 <= wbs_in.dat;
reg_in_s.reg193 <= wbs_in.dat;
reg_in_s.reg194 <= wbs_in.dat;
reg_in_s.reg195 <= wbs_in.dat;
reg_in_s.reg196 <= wbs_in.dat;
reg_in_s.reg197 <= wbs_in.dat;
reg_in_s.reg198 <= wbs_in.dat;
reg_in_s.reg199 <= wbs_in.dat;
reg_in_s.reg200 <= wbs_in.dat;
reg_in_s.reg201 <= wbs_in.dat;
reg_in_s.reg202 <= wbs_in.dat;
reg_in_s.reg203 <= wbs_in.dat;
reg_in_s.reg204 <= wbs_in.dat;
reg_in_s.reg205 <= wbs_in.dat;
reg_in_s.reg206 <= wbs_in.dat;
reg_in_s.reg207 <= wbs_in.dat;
reg_in_s.reg208 <= wbs_in.dat;
reg_in_s.reg209 <= wbs_in.dat;
reg_in_s.reg210 <= wbs_in.dat;
reg_in_s.reg211 <= wbs_in.dat;
reg_in_s.reg212 <= wbs_in.dat;
reg_in_s.reg213 <= wbs_in.dat;
reg_in_s.reg214 <= wbs_in.dat;
reg_in_s.reg215 <= wbs_in.dat;
reg_in_s.reg216 <= wbs_in.dat;
reg_in_s.reg217 <= wbs_in.dat;
reg_in_s.reg218 <= wbs_in.dat;
reg_in_s.reg219 <= wbs_in.dat;
reg_in_s.reg220 <= wbs_in.dat;
reg_in_s.reg221 <= wbs_in.dat;
reg_in_s.reg222 <= wbs_in.dat;
reg_in_s.reg223 <= wbs_in.dat;
reg_in_s.reg224 <= wbs_in.dat;
reg_in_s.reg225 <= wbs_in.dat;
reg_in_s.reg226 <= wbs_in.dat;
reg_in_s.reg227 <= wbs_in.dat;
reg_in_s.reg228 <= wbs_in.dat;
reg_in_s.reg229 <= wbs_in.dat;
reg_in_s.reg230 <= wbs_in.dat;
reg_in_s.reg231 <= wbs_in.dat;
reg_in_s.reg232 <= wbs_in.dat;
reg_in_s.reg233 <= wbs_in.dat;
reg_in_s.reg234 <= wbs_in.dat;
reg_in_s.reg235 <= wbs_in.dat;
reg_in_s.reg236 <= wbs_in.dat;
reg_in_s.reg237 <= wbs_in.dat;
reg_in_s.reg238 <= wbs_in.dat;
reg_in_s.reg239 <= wbs_in.dat;
reg_in_s.reg240 <= wbs_in.dat;
reg_in_s.reg241 <= wbs_in.dat;
reg_in_s.reg242 <= wbs_in.dat;
reg_in_s.reg243 <= wbs_in.dat;
reg_in_s.reg244 <= wbs_in.dat;
reg_in_s.reg245 <= wbs_in.dat;
reg_in_s.reg246 <= wbs_in.dat;
reg_in_s.reg247 <= wbs_in.dat;
reg_in_s.reg248 <= wbs_in.dat;
reg_in_s.reg249 <= wbs_in.dat;
reg_in_s.reg250 <= wbs_in.dat;
reg_in_s.reg251 <= wbs_in.dat;
reg_in_s.reg252 <= wbs_in.dat;
reg_in_s.reg253 <= wbs_in.dat;
reg_in_s.reg254 <= wbs_in.dat;
reg_in_s.reg255 <= wbs_in.dat;
-- register output -> wbs_out via demultiplexer
with wbs_in.adr select
wbs_out.dat <= reg_out_s.reg0 when REG0_ADR,
reg_out_s.reg1 when REG1_ADR,
reg_out_s.reg2 when REG2_ADR,
reg_out_s.reg3 when REG3_ADR,
reg_out_s.reg4 when REG4_ADR,
reg_out_s.reg5 when REG5_ADR,
reg_out_s.reg6 when REG6_ADR,
reg_out_s.reg7 when REG7_ADR,
reg_out_s.reg8 when REG8_ADR,
reg_out_s.reg9 when REG9_ADR,
reg_out_s.reg10 when REG10_ADR,
reg_out_s.reg11 when REG11_ADR,
reg_out_s.reg12 when REG12_ADR,
reg_out_s.reg13 when REG13_ADR,
reg_out_s.reg14 when REG14_ADR,
reg_out_s.reg15 when REG15_ADR,
reg_out_s.reg16 when REG16_ADR,
reg_out_s.reg17 when REG17_ADR,
reg_out_s.reg18 when REG18_ADR,
reg_out_s.reg19 when REG19_ADR,
reg_out_s.reg20 when REG20_ADR,
reg_out_s.reg21 when REG21_ADR,
reg_out_s.reg22 when REG22_ADR,
reg_out_s.reg23 when REG23_ADR,
reg_out_s.reg24 when REG24_ADR,
reg_out_s.reg25 when REG25_ADR,
reg_out_s.reg26 when REG26_ADR,
reg_out_s.reg27 when REG27_ADR,
reg_out_s.reg28 when REG28_ADR,
reg_out_s.reg29 when REG29_ADR,
reg_out_s.reg30 when REG30_ADR,
reg_out_s.reg31 when REG31_ADR,
reg_out_s.reg32 when REG32_ADR,
reg_out_s.reg33 when REG33_ADR,
reg_out_s.reg34 when REG34_ADR,
reg_out_s.reg35 when REG35_ADR,
reg_out_s.reg36 when REG36_ADR,
reg_out_s.reg37 when REG37_ADR,
reg_out_s.reg38 when REG38_ADR,
reg_out_s.reg39 when REG39_ADR,
reg_out_s.reg40 when REG40_ADR,
reg_out_s.reg41 when REG41_ADR,
reg_out_s.reg42 when REG42_ADR,
reg_out_s.reg43 when REG43_ADR,
reg_out_s.reg44 when REG44_ADR,
reg_out_s.reg45 when REG45_ADR,
reg_out_s.reg46 when REG46_ADR,
reg_out_s.reg47 when REG47_ADR,
reg_out_s.reg48 when REG48_ADR,
reg_out_s.reg49 when REG49_ADR,
reg_out_s.reg50 when REG50_ADR,
reg_out_s.reg51 when REG51_ADR,
reg_out_s.reg52 when REG52_ADR,
reg_out_s.reg53 when REG53_ADR,
reg_out_s.reg54 when REG54_ADR,
reg_out_s.reg55 when REG55_ADR,
reg_out_s.reg56 when REG56_ADR,
reg_out_s.reg57 when REG57_ADR,
reg_out_s.reg58 when REG58_ADR,
reg_out_s.reg59 when REG59_ADR,
reg_out_s.reg60 when REG60_ADR,
reg_out_s.reg61 when REG61_ADR,
reg_out_s.reg62 when REG62_ADR,
reg_out_s.reg63 when REG63_ADR,
reg_out_s.reg64 when REG64_ADR,
reg_out_s.reg65 when REG65_ADR,
reg_out_s.reg66 when REG66_ADR,
reg_out_s.reg67 when REG67_ADR,
reg_out_s.reg68 when REG68_ADR,
reg_out_s.reg69 when REG69_ADR,
reg_out_s.reg70 when REG70_ADR,
reg_out_s.reg71 when REG71_ADR,
reg_out_s.reg72 when REG72_ADR,
reg_out_s.reg73 when REG73_ADR,
reg_out_s.reg74 when REG74_ADR,
reg_out_s.reg75 when REG75_ADR,
reg_out_s.reg76 when REG76_ADR,
reg_out_s.reg77 when REG77_ADR,
reg_out_s.reg78 when REG78_ADR,
reg_out_s.reg79 when REG79_ADR,
reg_out_s.reg80 when REG80_ADR,
reg_out_s.reg81 when REG81_ADR,
reg_out_s.reg82 when REG82_ADR,
reg_out_s.reg83 when REG83_ADR,
reg_out_s.reg84 when REG84_ADR,
reg_out_s.reg85 when REG85_ADR,
reg_out_s.reg86 when REG86_ADR,
reg_out_s.reg87 when REG87_ADR,
reg_out_s.reg88 when REG88_ADR,
reg_out_s.reg89 when REG89_ADR,
reg_out_s.reg90 when REG90_ADR,
reg_out_s.reg91 when REG91_ADR,
reg_out_s.reg92 when REG92_ADR,
reg_out_s.reg93 when REG93_ADR,
reg_out_s.reg94 when REG94_ADR,
reg_out_s.reg95 when REG95_ADR,
reg_out_s.reg96 when REG96_ADR,
reg_out_s.reg97 when REG97_ADR,
reg_out_s.reg98 when REG98_ADR,
reg_out_s.reg99 when REG99_ADR,
reg_out_s.reg100 when REG100_ADR,
reg_out_s.reg101 when REG101_ADR,
reg_out_s.reg102 when REG102_ADR,
reg_out_s.reg103 when REG103_ADR,
reg_out_s.reg104 when REG104_ADR,
reg_out_s.reg105 when REG105_ADR,
reg_out_s.reg106 when REG106_ADR,
reg_out_s.reg107 when REG107_ADR,
reg_out_s.reg108 when REG108_ADR,
reg_out_s.reg109 when REG109_ADR,
reg_out_s.reg110 when REG110_ADR,
reg_out_s.reg111 when REG111_ADR,
reg_out_s.reg112 when REG112_ADR,
reg_out_s.reg113 when REG113_ADR,
reg_out_s.reg114 when REG114_ADR,
reg_out_s.reg115 when REG115_ADR,
reg_out_s.reg116 when REG116_ADR,
reg_out_s.reg117 when REG117_ADR,
reg_out_s.reg118 when REG118_ADR,
reg_out_s.reg119 when REG119_ADR,
reg_out_s.reg120 when REG120_ADR,
reg_out_s.reg121 when REG121_ADR,
reg_out_s.reg122 when REG122_ADR,
reg_out_s.reg123 when REG123_ADR,
reg_out_s.reg124 when REG124_ADR,
reg_out_s.reg125 when REG125_ADR,
reg_out_s.reg126 when REG126_ADR,
reg_out_s.reg127 when REG127_ADR,
reg_out_s.reg128 when REG128_ADR,
reg_out_s.reg129 when REG129_ADR,
reg_out_s.reg130 when REG130_ADR,
reg_out_s.reg131 when REG131_ADR,
reg_out_s.reg132 when REG132_ADR,
reg_out_s.reg133 when REG133_ADR,
reg_out_s.reg134 when REG134_ADR,
reg_out_s.reg135 when REG135_ADR,
reg_out_s.reg136 when REG136_ADR,
reg_out_s.reg137 when REG137_ADR,
reg_out_s.reg138 when REG138_ADR,
reg_out_s.reg139 when REG139_ADR,
reg_out_s.reg140 when REG140_ADR,
reg_out_s.reg141 when REG141_ADR,
reg_out_s.reg142 when REG142_ADR,
reg_out_s.reg143 when REG143_ADR,
reg_out_s.reg144 when REG144_ADR,
reg_out_s.reg145 when REG145_ADR,
reg_out_s.reg146 when REG146_ADR,
reg_out_s.reg147 when REG147_ADR,
reg_out_s.reg148 when REG148_ADR,
reg_out_s.reg149 when REG149_ADR,
reg_out_s.reg150 when REG150_ADR,
reg_out_s.reg151 when REG151_ADR,
reg_out_s.reg152 when REG152_ADR,
reg_out_s.reg153 when REG153_ADR,
reg_out_s.reg154 when REG154_ADR,
reg_out_s.reg155 when REG155_ADR,
reg_out_s.reg156 when REG156_ADR,
reg_out_s.reg157 when REG157_ADR,
reg_out_s.reg158 when REG158_ADR,
reg_out_s.reg159 when REG159_ADR,
reg_out_s.reg160 when REG160_ADR,
reg_out_s.reg161 when REG161_ADR,
reg_out_s.reg162 when REG162_ADR,
reg_out_s.reg163 when REG163_ADR,
reg_out_s.reg164 when REG164_ADR,
reg_out_s.reg165 when REG165_ADR,
reg_out_s.reg166 when REG166_ADR,
reg_out_s.reg167 when REG167_ADR,
reg_out_s.reg168 when REG168_ADR,
reg_out_s.reg169 when REG169_ADR,
reg_out_s.reg170 when REG170_ADR,
reg_out_s.reg171 when REG171_ADR,
reg_out_s.reg172 when REG172_ADR,
reg_out_s.reg173 when REG173_ADR,
reg_out_s.reg174 when REG174_ADR,
reg_out_s.reg175 when REG175_ADR,
reg_out_s.reg176 when REG176_ADR,
reg_out_s.reg177 when REG177_ADR,
reg_out_s.reg178 when REG178_ADR,
reg_out_s.reg179 when REG179_ADR,
reg_out_s.reg180 when REG180_ADR,
reg_out_s.reg181 when REG181_ADR,
reg_out_s.reg182 when REG182_ADR,
reg_out_s.reg183 when REG183_ADR,
reg_out_s.reg184 when REG184_ADR,
reg_out_s.reg185 when REG185_ADR,
reg_out_s.reg186 when REG186_ADR,
reg_out_s.reg187 when REG187_ADR,
reg_out_s.reg188 when REG188_ADR,
reg_out_s.reg189 when REG189_ADR,
reg_out_s.reg190 when REG190_ADR,
reg_out_s.reg191 when REG191_ADR,
reg_out_s.reg192 when REG192_ADR,
reg_out_s.reg193 when REG193_ADR,
reg_out_s.reg194 when REG194_ADR,
reg_out_s.reg195 when REG195_ADR,
reg_out_s.reg196 when REG196_ADR,
reg_out_s.reg197 when REG197_ADR,
reg_out_s.reg198 when REG198_ADR,
reg_out_s.reg199 when REG199_ADR,
reg_out_s.reg200 when REG200_ADR,
reg_out_s.reg201 when REG201_ADR,
reg_out_s.reg202 when REG202_ADR,
reg_out_s.reg203 when REG203_ADR,
reg_out_s.reg204 when REG204_ADR,
reg_out_s.reg205 when REG205_ADR,
reg_out_s.reg206 when REG206_ADR,
reg_out_s.reg207 when REG207_ADR,
reg_out_s.reg208 when REG208_ADR,
reg_out_s.reg209 when REG209_ADR,
reg_out_s.reg210 when REG210_ADR,
reg_out_s.reg211 when REG211_ADR,
reg_out_s.reg212 when REG212_ADR,
reg_out_s.reg213 when REG213_ADR,
reg_out_s.reg214 when REG214_ADR,
reg_out_s.reg215 when REG215_ADR,
reg_out_s.reg216 when REG216_ADR,
reg_out_s.reg217 when REG217_ADR,
reg_out_s.reg218 when REG218_ADR,
reg_out_s.reg219 when REG219_ADR,
reg_out_s.reg220 when REG220_ADR,
reg_out_s.reg221 when REG221_ADR,
reg_out_s.reg222 when REG222_ADR,
reg_out_s.reg223 when REG223_ADR,
reg_out_s.reg224 when REG224_ADR,
reg_out_s.reg225 when REG225_ADR,
reg_out_s.reg226 when REG226_ADR,
reg_out_s.reg227 when REG227_ADR,
reg_out_s.reg228 when REG228_ADR,
reg_out_s.reg229 when REG229_ADR,
reg_out_s.reg230 when REG230_ADR,
reg_out_s.reg231 when REG231_ADR,
reg_out_s.reg232 when REG232_ADR,
reg_out_s.reg233 when REG233_ADR,
reg_out_s.reg234 when REG234_ADR,
reg_out_s.reg235 when REG235_ADR,
reg_out_s.reg236 when REG236_ADR,
reg_out_s.reg237 when REG237_ADR,
reg_out_s.reg238 when REG238_ADR,
reg_out_s.reg239 when REG239_ADR,
reg_out_s.reg240 when REG240_ADR,
reg_out_s.reg241 when REG241_ADR,
reg_out_s.reg242 when REG242_ADR,
reg_out_s.reg243 when REG243_ADR,
reg_out_s.reg244 when REG244_ADR,
reg_out_s.reg245 when REG245_ADR,
reg_out_s.reg246 when REG246_ADR,
reg_out_s.reg247 when REG247_ADR,
reg_out_s.reg248 when REG248_ADR,
reg_out_s.reg249 when REG249_ADR,
reg_out_s.reg250 when REG250_ADR,
reg_out_s.reg251 when REG251_ADR,
reg_out_s.reg252 when REG252_ADR,
reg_out_s.reg253 when REG253_ADR,
reg_out_s.reg254 when REG254_ADR,
reg_out_s.reg255 when REG255_ADR,
(others => '-') when others;
-- register outputs -> non-wishbone outputs
reg0_out <= reg_out_s.reg0;
reg1_out <= reg_out_s.reg1;
reg2_out <= reg_out_s.reg2;
reg3_out <= reg_out_s.reg3;
reg4_out <= reg_out_s.reg4;
reg5_out <= reg_out_s.reg5;
reg6_out <= reg_out_s.reg6;
reg7_out <= reg_out_s.reg7;
reg8_out <= reg_out_s.reg8;
reg9_out <= reg_out_s.reg9;
reg10_out <= reg_out_s.reg10;
reg11_out <= reg_out_s.reg11;
reg12_out <= reg_out_s.reg12;
reg13_out <= reg_out_s.reg13;
reg14_out <= reg_out_s.reg14;
reg15_out <= reg_out_s.reg15;
reg16_out <= reg_out_s.reg16;
reg17_out <= reg_out_s.reg17;
reg18_out <= reg_out_s.reg18;
reg19_out <= reg_out_s.reg19;
reg20_out <= reg_out_s.reg20;
reg21_out <= reg_out_s.reg21;
reg22_out <= reg_out_s.reg22;
reg23_out <= reg_out_s.reg23;
reg24_out <= reg_out_s.reg24;
reg25_out <= reg_out_s.reg25;
reg26_out <= reg_out_s.reg26;
reg27_out <= reg_out_s.reg27;
reg28_out <= reg_out_s.reg28;
reg29_out <= reg_out_s.reg29;
reg30_out <= reg_out_s.reg30;
reg31_out <= reg_out_s.reg31;
reg32_out <= reg_out_s.reg32;
reg33_out <= reg_out_s.reg33;
reg34_out <= reg_out_s.reg34;
reg35_out <= reg_out_s.reg35;
reg36_out <= reg_out_s.reg36;
reg37_out <= reg_out_s.reg37;
reg38_out <= reg_out_s.reg38;
reg39_out <= reg_out_s.reg39;
reg40_out <= reg_out_s.reg40;
reg41_out <= reg_out_s.reg41;
reg42_out <= reg_out_s.reg42;
reg43_out <= reg_out_s.reg43;
reg44_out <= reg_out_s.reg44;
reg45_out <= reg_out_s.reg45;
reg46_out <= reg_out_s.reg46;
reg47_out <= reg_out_s.reg47;
reg48_out <= reg_out_s.reg48;
reg49_out <= reg_out_s.reg49;
reg50_out <= reg_out_s.reg50;
reg51_out <= reg_out_s.reg51;
reg52_out <= reg_out_s.reg52;
reg53_out <= reg_out_s.reg53;
reg54_out <= reg_out_s.reg54;
reg55_out <= reg_out_s.reg55;
reg56_out <= reg_out_s.reg56;
reg57_out <= reg_out_s.reg57;
reg58_out <= reg_out_s.reg58;
reg59_out <= reg_out_s.reg59;
reg60_out <= reg_out_s.reg60;
reg61_out <= reg_out_s.reg61;
reg62_out <= reg_out_s.reg62;
reg63_out <= reg_out_s.reg63;
reg64_out <= reg_out_s.reg64;
reg65_out <= reg_out_s.reg65;
reg66_out <= reg_out_s.reg66;
reg67_out <= reg_out_s.reg67;
reg68_out <= reg_out_s.reg68;
reg69_out <= reg_out_s.reg69;
reg70_out <= reg_out_s.reg70;
reg71_out <= reg_out_s.reg71;
reg72_out <= reg_out_s.reg72;
reg73_out <= reg_out_s.reg73;
reg74_out <= reg_out_s.reg74;
reg75_out <= reg_out_s.reg75;
reg76_out <= reg_out_s.reg76;
reg77_out <= reg_out_s.reg77;
reg78_out <= reg_out_s.reg78;
reg79_out <= reg_out_s.reg79;
reg80_out <= reg_out_s.reg80;
reg81_out <= reg_out_s.reg81;
reg82_out <= reg_out_s.reg82;
reg83_out <= reg_out_s.reg83;
reg84_out <= reg_out_s.reg84;
reg85_out <= reg_out_s.reg85;
reg86_out <= reg_out_s.reg86;
reg87_out <= reg_out_s.reg87;
reg88_out <= reg_out_s.reg88;
reg89_out <= reg_out_s.reg89;
reg90_out <= reg_out_s.reg90;
reg91_out <= reg_out_s.reg91;
reg92_out <= reg_out_s.reg92;
reg93_out <= reg_out_s.reg93;
reg94_out <= reg_out_s.reg94;
reg95_out <= reg_out_s.reg95;
reg96_out <= reg_out_s.reg96;
reg97_out <= reg_out_s.reg97;
reg98_out <= reg_out_s.reg98;
reg99_out <= reg_out_s.reg99;
reg100_out <= reg_out_s.reg100;
reg101_out <= reg_out_s.reg101;
reg102_out <= reg_out_s.reg102;
reg103_out <= reg_out_s.reg103;
reg104_out <= reg_out_s.reg104;
reg105_out <= reg_out_s.reg105;
reg106_out <= reg_out_s.reg106;
reg107_out <= reg_out_s.reg107;
reg108_out <= reg_out_s.reg108;
reg109_out <= reg_out_s.reg109;
reg110_out <= reg_out_s.reg110;
reg111_out <= reg_out_s.reg111;
reg112_out <= reg_out_s.reg112;
reg113_out <= reg_out_s.reg113;
reg114_out <= reg_out_s.reg114;
reg115_out <= reg_out_s.reg115;
reg116_out <= reg_out_s.reg116;
reg117_out <= reg_out_s.reg117;
reg118_out <= reg_out_s.reg118;
reg119_out <= reg_out_s.reg119;
reg120_out <= reg_out_s.reg120;
reg121_out <= reg_out_s.reg121;
reg122_out <= reg_out_s.reg122;
reg123_out <= reg_out_s.reg123;
reg124_out <= reg_out_s.reg124;
reg125_out <= reg_out_s.reg125;
reg126_out <= reg_out_s.reg126;
reg127_out <= reg_out_s.reg127;
reg128_out <= reg_out_s.reg128;
reg129_out <= reg_out_s.reg129;
reg130_out <= reg_out_s.reg130;
reg131_out <= reg_out_s.reg131;
reg132_out <= reg_out_s.reg132;
reg133_out <= reg_out_s.reg133;
reg134_out <= reg_out_s.reg134;
reg135_out <= reg_out_s.reg135;
reg136_out <= reg_out_s.reg136;
reg137_out <= reg_out_s.reg137;
reg138_out <= reg_out_s.reg138;
reg139_out <= reg_out_s.reg139;
reg140_out <= reg_out_s.reg140;
reg141_out <= reg_out_s.reg141;
reg142_out <= reg_out_s.reg142;
reg143_out <= reg_out_s.reg143;
reg144_out <= reg_out_s.reg144;
reg145_out <= reg_out_s.reg145;
reg146_out <= reg_out_s.reg146;
reg147_out <= reg_out_s.reg147;
reg148_out <= reg_out_s.reg148;
reg149_out <= reg_out_s.reg149;
reg150_out <= reg_out_s.reg150;
reg151_out <= reg_out_s.reg151;
reg152_out <= reg_out_s.reg152;
reg153_out <= reg_out_s.reg153;
reg154_out <= reg_out_s.reg154;
reg155_out <= reg_out_s.reg155;
reg156_out <= reg_out_s.reg156;
reg157_out <= reg_out_s.reg157;
reg158_out <= reg_out_s.reg158;
reg159_out <= reg_out_s.reg159;
reg160_out <= reg_out_s.reg160;
reg161_out <= reg_out_s.reg161;
reg162_out <= reg_out_s.reg162;
reg163_out <= reg_out_s.reg163;
reg164_out <= reg_out_s.reg164;
reg165_out <= reg_out_s.reg165;
reg166_out <= reg_out_s.reg166;
reg167_out <= reg_out_s.reg167;
reg168_out <= reg_out_s.reg168;
reg169_out <= reg_out_s.reg169;
reg170_out <= reg_out_s.reg170;
reg171_out <= reg_out_s.reg171;
reg172_out <= reg_out_s.reg172;
reg173_out <= reg_out_s.reg173;
reg174_out <= reg_out_s.reg174;
reg175_out <= reg_out_s.reg175;
reg176_out <= reg_out_s.reg176;
reg177_out <= reg_out_s.reg177;
reg178_out <= reg_out_s.reg178;
reg179_out <= reg_out_s.reg179;
reg180_out <= reg_out_s.reg180;
reg181_out <= reg_out_s.reg181;
reg182_out <= reg_out_s.reg182;
reg183_out <= reg_out_s.reg183;
reg184_out <= reg_out_s.reg184;
reg185_out <= reg_out_s.reg185;
reg186_out <= reg_out_s.reg186;
reg187_out <= reg_out_s.reg187;
reg188_out <= reg_out_s.reg188;
reg189_out <= reg_out_s.reg189;
reg190_out <= reg_out_s.reg190;
reg191_out <= reg_out_s.reg191;
reg192_out <= reg_out_s.reg192;
reg193_out <= reg_out_s.reg193;
reg194_out <= reg_out_s.reg194;
reg195_out <= reg_out_s.reg195;
reg196_out <= reg_out_s.reg196;
reg197_out <= reg_out_s.reg197;
reg198_out <= reg_out_s.reg198;
reg199_out <= reg_out_s.reg199;
reg200_out <= reg_out_s.reg200;
reg201_out <= reg_out_s.reg201;
reg202_out <= reg_out_s.reg202;
reg203_out <= reg_out_s.reg203;
reg204_out <= reg_out_s.reg204;
reg205_out <= reg_out_s.reg205;
reg206_out <= reg_out_s.reg206;
reg207_out <= reg_out_s.reg207;
reg208_out <= reg_out_s.reg208;
reg209_out <= reg_out_s.reg209;
reg210_out <= reg_out_s.reg210;
reg211_out <= reg_out_s.reg211;
reg212_out <= reg_out_s.reg212;
reg213_out <= reg_out_s.reg213;
reg214_out <= reg_out_s.reg214;
reg215_out <= reg_out_s.reg215;
reg216_out <= reg_out_s.reg216;
reg217_out <= reg_out_s.reg217;
reg218_out <= reg_out_s.reg218;
reg219_out <= reg_out_s.reg219;
reg220_out <= reg_out_s.reg220;
reg221_out <= reg_out_s.reg221;
reg222_out <= reg_out_s.reg222;
reg223_out <= reg_out_s.reg223;
reg224_out <= reg_out_s.reg224;
reg225_out <= reg_out_s.reg225;
reg226_out <= reg_out_s.reg226;
reg227_out <= reg_out_s.reg227;
reg228_out <= reg_out_s.reg228;
reg229_out <= reg_out_s.reg229;
reg230_out <= reg_out_s.reg230;
reg231_out <= reg_out_s.reg231;
reg232_out <= reg_out_s.reg232;
reg233_out <= reg_out_s.reg233;
reg234_out <= reg_out_s.reg234;
reg235_out <= reg_out_s.reg235;
reg236_out <= reg_out_s.reg236;
reg237_out <= reg_out_s.reg237;
reg238_out <= reg_out_s.reg238;
reg239_out <= reg_out_s.reg239;
reg240_out <= reg_out_s.reg240;
reg241_out <= reg_out_s.reg241;
reg242_out <= reg_out_s.reg242;
reg243_out <= reg_out_s.reg243;
reg244_out <= reg_out_s.reg244;
reg245_out <= reg_out_s.reg245;
reg246_out <= reg_out_s.reg246;
reg247_out <= reg_out_s.reg247;
reg248_out <= reg_out_s.reg248;
reg249_out <= reg_out_s.reg249;
reg250_out <= reg_out_s.reg250;
reg251_out <= reg_out_s.reg251;
reg252_out <= reg_out_s.reg252;
reg253_out <= reg_out_s.reg253;
reg254_out <= reg_out_s.reg254;
reg255_out <= reg_out_s.reg255;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- reset all registers
if (wbs_in.rst = '1') then
reg_out_s.reg0 <= (others => '0');
reg_out_s.reg1 <= (others => '0');
reg_out_s.reg2 <= (others => '0');
reg_out_s.reg3 <= (others => '0');
reg_out_s.reg4 <= (others => '0');
reg_out_s.reg5 <= (others => '0');
reg_out_s.reg6 <= (others => '0');
reg_out_s.reg7 <= (others => '0');
reg_out_s.reg8 <= (others => '0');
reg_out_s.reg9 <= (others => '0');
reg_out_s.reg10 <= (others => '0');
reg_out_s.reg11 <= (others => '0');
reg_out_s.reg12 <= (others => '0');
reg_out_s.reg13 <= (others => '0');
reg_out_s.reg14 <= (others => '0');
reg_out_s.reg15 <= (others => '0');
reg_out_s.reg16 <= (others => '0');
reg_out_s.reg17 <= (others => '0');
reg_out_s.reg18 <= (others => '0');
reg_out_s.reg19 <= (others => '0');
reg_out_s.reg20 <= (others => '0');
reg_out_s.reg21 <= (others => '0');
reg_out_s.reg22 <= (others => '0');
reg_out_s.reg23 <= (others => '0');
reg_out_s.reg24 <= (others => '0');
reg_out_s.reg25 <= (others => '0');
reg_out_s.reg26 <= (others => '0');
reg_out_s.reg27 <= (others => '0');
reg_out_s.reg28 <= (others => '0');
reg_out_s.reg29 <= (others => '0');
reg_out_s.reg30 <= (others => '0');
reg_out_s.reg31 <= (others => '0');
reg_out_s.reg32 <= (others => '0');
reg_out_s.reg33 <= (others => '0');
reg_out_s.reg34 <= (others => '0');
reg_out_s.reg35 <= (others => '0');
reg_out_s.reg36 <= (others => '0');
reg_out_s.reg37 <= (others => '0');
reg_out_s.reg38 <= (others => '0');
reg_out_s.reg39 <= (others => '0');
reg_out_s.reg40 <= (others => '0');
reg_out_s.reg41 <= (others => '0');
reg_out_s.reg42 <= (others => '0');
reg_out_s.reg43 <= (others => '0');
reg_out_s.reg44 <= (others => '0');
reg_out_s.reg45 <= (others => '0');
reg_out_s.reg46 <= (others => '0');
reg_out_s.reg47 <= (others => '0');
reg_out_s.reg48 <= (others => '0');
reg_out_s.reg49 <= (others => '0');
reg_out_s.reg50 <= (others => '0');
reg_out_s.reg51 <= (others => '0');
reg_out_s.reg52 <= (others => '0');
reg_out_s.reg53 <= (others => '0');
reg_out_s.reg54 <= (others => '0');
reg_out_s.reg55 <= (others => '0');
reg_out_s.reg56 <= (others => '0');
reg_out_s.reg57 <= (others => '0');
reg_out_s.reg58 <= (others => '0');
reg_out_s.reg59 <= (others => '0');
reg_out_s.reg60 <= (others => '0');
reg_out_s.reg61 <= (others => '0');
reg_out_s.reg62 <= (others => '0');
reg_out_s.reg63 <= (others => '0');
reg_out_s.reg64 <= (others => '0');
reg_out_s.reg65 <= (others => '0');
reg_out_s.reg66 <= (others => '0');
reg_out_s.reg67 <= (others => '0');
reg_out_s.reg68 <= (others => '0');
reg_out_s.reg69 <= (others => '0');
reg_out_s.reg70 <= (others => '0');
reg_out_s.reg71 <= (others => '0');
reg_out_s.reg72 <= (others => '0');
reg_out_s.reg73 <= (others => '0');
reg_out_s.reg74 <= (others => '0');
reg_out_s.reg75 <= (others => '0');
reg_out_s.reg76 <= (others => '0');
reg_out_s.reg77 <= (others => '0');
reg_out_s.reg78 <= (others => '0');
reg_out_s.reg79 <= (others => '0');
reg_out_s.reg80 <= (others => '0');
reg_out_s.reg81 <= (others => '0');
reg_out_s.reg82 <= (others => '0');
reg_out_s.reg83 <= (others => '0');
reg_out_s.reg84 <= (others => '0');
reg_out_s.reg85 <= (others => '0');
reg_out_s.reg86 <= (others => '0');
reg_out_s.reg87 <= (others => '0');
reg_out_s.reg88 <= (others => '0');
reg_out_s.reg89 <= (others => '0');
reg_out_s.reg90 <= (others => '0');
reg_out_s.reg91 <= (others => '0');
reg_out_s.reg92 <= (others => '0');
reg_out_s.reg93 <= (others => '0');
reg_out_s.reg94 <= (others => '0');
reg_out_s.reg95 <= (others => '0');
reg_out_s.reg96 <= (others => '0');
reg_out_s.reg97 <= (others => '0');
reg_out_s.reg98 <= (others => '0');
reg_out_s.reg99 <= (others => '0');
reg_out_s.reg100 <= (others => '0');
reg_out_s.reg101 <= (others => '0');
reg_out_s.reg102 <= (others => '0');
reg_out_s.reg103 <= (others => '0');
reg_out_s.reg104 <= (others => '0');
reg_out_s.reg105 <= (others => '0');
reg_out_s.reg106 <= (others => '0');
reg_out_s.reg107 <= (others => '0');
reg_out_s.reg108 <= (others => '0');
reg_out_s.reg109 <= (others => '0');
reg_out_s.reg110 <= (others => '0');
reg_out_s.reg111 <= (others => '0');
reg_out_s.reg112 <= (others => '0');
reg_out_s.reg113 <= (others => '0');
reg_out_s.reg114 <= (others => '0');
reg_out_s.reg115 <= (others => '0');
reg_out_s.reg116 <= (others => '0');
reg_out_s.reg117 <= (others => '0');
reg_out_s.reg118 <= (others => '0');
reg_out_s.reg119 <= (others => '0');
reg_out_s.reg120 <= (others => '0');
reg_out_s.reg121 <= (others => '0');
reg_out_s.reg122 <= (others => '0');
reg_out_s.reg123 <= (others => '0');
reg_out_s.reg124 <= (others => '0');
reg_out_s.reg125 <= (others => '0');
reg_out_s.reg126 <= (others => '0');
reg_out_s.reg127 <= (others => '0');
reg_out_s.reg128 <= (others => '0');
reg_out_s.reg129 <= (others => '0');
reg_out_s.reg130 <= (others => '0');
reg_out_s.reg131 <= (others => '0');
reg_out_s.reg132 <= (others => '0');
reg_out_s.reg133 <= (others => '0');
reg_out_s.reg134 <= (others => '0');
reg_out_s.reg135 <= (others => '0');
reg_out_s.reg136 <= (others => '0');
reg_out_s.reg137 <= (others => '0');
reg_out_s.reg138 <= (others => '0');
reg_out_s.reg139 <= (others => '0');
reg_out_s.reg140 <= (others => '0');
reg_out_s.reg141 <= (others => '0');
reg_out_s.reg142 <= (others => '0');
reg_out_s.reg143 <= (others => '0');
reg_out_s.reg144 <= (others => '0');
reg_out_s.reg145 <= (others => '0');
reg_out_s.reg146 <= (others => '0');
reg_out_s.reg147 <= (others => '0');
reg_out_s.reg148 <= (others => '0');
reg_out_s.reg149 <= (others => '0');
reg_out_s.reg150 <= (others => '0');
reg_out_s.reg151 <= (others => '0');
reg_out_s.reg152 <= (others => '0');
reg_out_s.reg153 <= (others => '0');
reg_out_s.reg154 <= (others => '0');
reg_out_s.reg155 <= (others => '0');
reg_out_s.reg156 <= (others => '0');
reg_out_s.reg157 <= (others => '0');
reg_out_s.reg158 <= (others => '0');
reg_out_s.reg159 <= (others => '0');
reg_out_s.reg160 <= (others => '0');
reg_out_s.reg161 <= (others => '0');
reg_out_s.reg162 <= (others => '0');
reg_out_s.reg163 <= (others => '0');
reg_out_s.reg164 <= (others => '0');
reg_out_s.reg165 <= (others => '0');
reg_out_s.reg166 <= (others => '0');
reg_out_s.reg167 <= (others => '0');
reg_out_s.reg168 <= (others => '0');
reg_out_s.reg169 <= (others => '0');
reg_out_s.reg170 <= (others => '0');
reg_out_s.reg171 <= (others => '0');
reg_out_s.reg172 <= (others => '0');
reg_out_s.reg173 <= (others => '0');
reg_out_s.reg174 <= (others => '0');
reg_out_s.reg175 <= (others => '0');
reg_out_s.reg176 <= (others => '0');
reg_out_s.reg177 <= (others => '0');
reg_out_s.reg178 <= (others => '0');
reg_out_s.reg179 <= (others => '0');
reg_out_s.reg180 <= (others => '0');
reg_out_s.reg181 <= (others => '0');
reg_out_s.reg182 <= (others => '0');
reg_out_s.reg183 <= (others => '0');
reg_out_s.reg184 <= (others => '0');
reg_out_s.reg185 <= (others => '0');
reg_out_s.reg186 <= (others => '0');
reg_out_s.reg187 <= (others => '0');
reg_out_s.reg188 <= (others => '0');
reg_out_s.reg189 <= (others => '0');
reg_out_s.reg190 <= (others => '0');
reg_out_s.reg191 <= (others => '0');
reg_out_s.reg192 <= (others => '0');
reg_out_s.reg193 <= (others => '0');
reg_out_s.reg194 <= (others => '0');
reg_out_s.reg195 <= (others => '0');
reg_out_s.reg196 <= (others => '0');
reg_out_s.reg197 <= (others => '0');
reg_out_s.reg198 <= (others => '0');
reg_out_s.reg199 <= (others => '0');
reg_out_s.reg200 <= (others => '0');
reg_out_s.reg201 <= (others => '0');
reg_out_s.reg202 <= (others => '0');
reg_out_s.reg203 <= (others => '0');
reg_out_s.reg204 <= (others => '0');
reg_out_s.reg205 <= (others => '0');
reg_out_s.reg206 <= (others => '0');
reg_out_s.reg207 <= (others => '0');
reg_out_s.reg208 <= (others => '0');
reg_out_s.reg209 <= (others => '0');
reg_out_s.reg210 <= (others => '0');
reg_out_s.reg211 <= (others => '0');
reg_out_s.reg212 <= (others => '0');
reg_out_s.reg213 <= (others => '0');
reg_out_s.reg214 <= (others => '0');
reg_out_s.reg215 <= (others => '0');
reg_out_s.reg216 <= (others => '0');
reg_out_s.reg217 <= (others => '0');
reg_out_s.reg218 <= (others => '0');
reg_out_s.reg219 <= (others => '0');
reg_out_s.reg220 <= (others => '0');
reg_out_s.reg221 <= (others => '0');
reg_out_s.reg222 <= (others => '0');
reg_out_s.reg223 <= (others => '0');
reg_out_s.reg224 <= (others => '0');
reg_out_s.reg225 <= (others => '0');
reg_out_s.reg226 <= (others => '0');
reg_out_s.reg227 <= (others => '0');
reg_out_s.reg228 <= (others => '0');
reg_out_s.reg229 <= (others => '0');
reg_out_s.reg230 <= (others => '0');
reg_out_s.reg231 <= (others => '0');
reg_out_s.reg232 <= (others => '0');
reg_out_s.reg233 <= (others => '0');
reg_out_s.reg234 <= (others => '0');
reg_out_s.reg235 <= (others => '0');
reg_out_s.reg236 <= (others => '0');
reg_out_s.reg237 <= (others => '0');
reg_out_s.reg238 <= (others => '0');
reg_out_s.reg239 <= (others => '0');
reg_out_s.reg240 <= (others => '0');
reg_out_s.reg241 <= (others => '0');
reg_out_s.reg242 <= (others => '0');
reg_out_s.reg243 <= (others => '0');
reg_out_s.reg244 <= (others => '0');
reg_out_s.reg245 <= (others => '0');
reg_out_s.reg246 <= (others => '0');
reg_out_s.reg247 <= (others => '0');
reg_out_s.reg248 <= (others => '0');
reg_out_s.reg249 <= (others => '0');
reg_out_s.reg250 <= (others => '0');
reg_out_s.reg251 <= (others => '0');
reg_out_s.reg252 <= (others => '0');
reg_out_s.reg253 <= (others => '0');
reg_out_s.reg254 <= (others => '0');
reg_out_s.reg255 <= (others => '0');
-- store reg0
elsif(reg0_re_s = '1') then
reg_out_s.reg0 <= reg_in_s.reg0;
-- store reg1
elsif(reg1_re_s = '1') then
reg_out_s.reg1 <= reg_in_s.reg1;
-- store reg2
elsif(reg2_re_s = '1') then
reg_out_s.reg2 <= reg_in_s.reg2;
-- store reg3
elsif(reg3_re_s = '1') then
reg_out_s.reg3 <= reg_in_s.reg3;
-- store reg4
elsif(reg4_re_s = '1') then
reg_out_s.reg4 <= reg_in_s.reg4;
-- store reg5
elsif(reg5_re_s = '1') then
reg_out_s.reg5 <= reg_in_s.reg5;
-- store reg6
elsif(reg6_re_s = '1') then
reg_out_s.reg6 <= reg_in_s.reg6;
-- store reg7
elsif(reg7_re_s = '1') then
reg_out_s.reg7 <= reg_in_s.reg7;
-- store reg8
elsif(reg8_re_s = '1') then
reg_out_s.reg8 <= reg_in_s.reg8;
-- store reg9
elsif(reg9_re_s = '1') then
reg_out_s.reg9 <= reg_in_s.reg9;
-- store reg10
elsif(reg10_re_s = '1') then
reg_out_s.reg10 <= reg_in_s.reg10;
-- store reg11
elsif(reg11_re_s = '1') then
reg_out_s.reg11 <= reg_in_s.reg11;
-- store reg12
elsif(reg12_re_s = '1') then
reg_out_s.reg12 <= reg_in_s.reg12;
-- store reg13
elsif(reg13_re_s = '1') then
reg_out_s.reg13 <= reg_in_s.reg13;
-- store reg14
elsif(reg14_re_s = '1') then
reg_out_s.reg14 <= reg_in_s.reg14;
-- store reg15
elsif(reg15_re_s = '1') then
reg_out_s.reg15 <= reg_in_s.reg15;
-- store reg16
elsif(reg16_re_s = '1') then
reg_out_s.reg16 <= reg_in_s.reg16;
-- store reg17
elsif(reg17_re_s = '1') then
reg_out_s.reg17 <= reg_in_s.reg17;
-- store reg18
elsif(reg18_re_s = '1') then
reg_out_s.reg18 <= reg_in_s.reg18;
-- store reg19
elsif(reg19_re_s = '1') then
reg_out_s.reg19 <= reg_in_s.reg19;
-- store reg20
elsif(reg20_re_s = '1') then
reg_out_s.reg20 <= reg_in_s.reg20;
-- store reg21
elsif(reg21_re_s = '1') then
reg_out_s.reg21 <= reg_in_s.reg21;
-- store reg22
elsif(reg22_re_s = '1') then
reg_out_s.reg22 <= reg_in_s.reg22;
-- store reg23
elsif(reg23_re_s = '1') then
reg_out_s.reg23 <= reg_in_s.reg23;
-- store reg24
elsif(reg24_re_s = '1') then
reg_out_s.reg24 <= reg_in_s.reg24;
-- store reg25
elsif(reg25_re_s = '1') then
reg_out_s.reg25 <= reg_in_s.reg25;
-- store reg26
elsif(reg26_re_s = '1') then
reg_out_s.reg26 <= reg_in_s.reg26;
-- store reg27
elsif(reg27_re_s = '1') then
reg_out_s.reg27 <= reg_in_s.reg27;
-- store reg28
elsif(reg28_re_s = '1') then
reg_out_s.reg28 <= reg_in_s.reg28;
-- store reg29
elsif(reg29_re_s = '1') then
reg_out_s.reg29 <= reg_in_s.reg29;
-- store reg30
elsif(reg30_re_s = '1') then
reg_out_s.reg30 <= reg_in_s.reg30;
-- store reg31
elsif(reg31_re_s = '1') then
reg_out_s.reg31 <= reg_in_s.reg31;
-- store reg32
elsif(reg32_re_s = '1') then
reg_out_s.reg32 <= reg_in_s.reg32;
-- store reg33
elsif(reg33_re_s = '1') then
reg_out_s.reg33 <= reg_in_s.reg33;
-- store reg34
elsif(reg34_re_s = '1') then
reg_out_s.reg34 <= reg_in_s.reg34;
-- store reg35
elsif(reg35_re_s = '1') then
reg_out_s.reg35 <= reg_in_s.reg35;
-- store reg36
elsif(reg36_re_s = '1') then
reg_out_s.reg36 <= reg_in_s.reg36;
-- store reg37
elsif(reg37_re_s = '1') then
reg_out_s.reg37 <= reg_in_s.reg37;
-- store reg38
elsif(reg38_re_s = '1') then
reg_out_s.reg38 <= reg_in_s.reg38;
-- store reg39
elsif(reg39_re_s = '1') then
reg_out_s.reg39 <= reg_in_s.reg39;
-- store reg40
elsif(reg40_re_s = '1') then
reg_out_s.reg40 <= reg_in_s.reg40;
-- store reg41
elsif(reg41_re_s = '1') then
reg_out_s.reg41 <= reg_in_s.reg41;
-- store reg42
elsif(reg42_re_s = '1') then
reg_out_s.reg42 <= reg_in_s.reg42;
-- store reg43
elsif(reg43_re_s = '1') then
reg_out_s.reg43 <= reg_in_s.reg43;
-- store reg44
elsif(reg44_re_s = '1') then
reg_out_s.reg44 <= reg_in_s.reg44;
-- store reg45
elsif(reg45_re_s = '1') then
reg_out_s.reg45 <= reg_in_s.reg45;
-- store reg46
elsif(reg46_re_s = '1') then
reg_out_s.reg46 <= reg_in_s.reg46;
-- store reg47
elsif(reg47_re_s = '1') then
reg_out_s.reg47 <= reg_in_s.reg47;
-- store reg48
elsif(reg48_re_s = '1') then
reg_out_s.reg48 <= reg_in_s.reg48;
-- store reg49
elsif(reg49_re_s = '1') then
reg_out_s.reg49 <= reg_in_s.reg49;
-- store reg50
elsif(reg50_re_s = '1') then
reg_out_s.reg50 <= reg_in_s.reg50;
-- store reg51
elsif(reg51_re_s = '1') then
reg_out_s.reg51 <= reg_in_s.reg51;
-- store reg52
elsif(reg52_re_s = '1') then
reg_out_s.reg52 <= reg_in_s.reg52;
-- store reg53
elsif(reg53_re_s = '1') then
reg_out_s.reg53 <= reg_in_s.reg53;
-- store reg54
elsif(reg54_re_s = '1') then
reg_out_s.reg54 <= reg_in_s.reg54;
-- store reg55
elsif(reg55_re_s = '1') then
reg_out_s.reg55 <= reg_in_s.reg55;
-- store reg56
elsif(reg56_re_s = '1') then
reg_out_s.reg56 <= reg_in_s.reg56;
-- store reg57
elsif(reg57_re_s = '1') then
reg_out_s.reg57 <= reg_in_s.reg57;
-- store reg58
elsif(reg58_re_s = '1') then
reg_out_s.reg58 <= reg_in_s.reg58;
-- store reg59
elsif(reg59_re_s = '1') then
reg_out_s.reg59 <= reg_in_s.reg59;
-- store reg60
elsif(reg60_re_s = '1') then
reg_out_s.reg60 <= reg_in_s.reg60;
-- store reg61
elsif(reg61_re_s = '1') then
reg_out_s.reg61 <= reg_in_s.reg61;
-- store reg62
elsif(reg62_re_s = '1') then
reg_out_s.reg62 <= reg_in_s.reg62;
-- store reg63
elsif(reg63_re_s = '1') then
reg_out_s.reg63 <= reg_in_s.reg63;
-- store reg64
elsif(reg64_re_s = '1') then
reg_out_s.reg64 <= reg_in_s.reg64;
-- store reg65
elsif(reg65_re_s = '1') then
reg_out_s.reg65 <= reg_in_s.reg65;
-- store reg66
elsif(reg66_re_s = '1') then
reg_out_s.reg66 <= reg_in_s.reg66;
-- store reg67
elsif(reg67_re_s = '1') then
reg_out_s.reg67 <= reg_in_s.reg67;
-- store reg68
elsif(reg68_re_s = '1') then
reg_out_s.reg68 <= reg_in_s.reg68;
-- store reg69
elsif(reg69_re_s = '1') then
reg_out_s.reg69 <= reg_in_s.reg69;
-- store reg70
elsif(reg70_re_s = '1') then
reg_out_s.reg70 <= reg_in_s.reg70;
-- store reg71
elsif(reg71_re_s = '1') then
reg_out_s.reg71 <= reg_in_s.reg71;
-- store reg72
elsif(reg72_re_s = '1') then
reg_out_s.reg72 <= reg_in_s.reg72;
-- store reg73
elsif(reg73_re_s = '1') then
reg_out_s.reg73 <= reg_in_s.reg73;
-- store reg74
elsif(reg74_re_s = '1') then
reg_out_s.reg74 <= reg_in_s.reg74;
-- store reg75
elsif(reg75_re_s = '1') then
reg_out_s.reg75 <= reg_in_s.reg75;
-- store reg76
elsif(reg76_re_s = '1') then
reg_out_s.reg76 <= reg_in_s.reg76;
-- store reg77
elsif(reg77_re_s = '1') then
reg_out_s.reg77 <= reg_in_s.reg77;
-- store reg78
elsif(reg78_re_s = '1') then
reg_out_s.reg78 <= reg_in_s.reg78;
-- store reg79
elsif(reg79_re_s = '1') then
reg_out_s.reg79 <= reg_in_s.reg79;
-- store reg80
elsif(reg80_re_s = '1') then
reg_out_s.reg80 <= reg_in_s.reg80;
-- store reg81
elsif(reg81_re_s = '1') then
reg_out_s.reg81 <= reg_in_s.reg81;
-- store reg82
elsif(reg82_re_s = '1') then
reg_out_s.reg82 <= reg_in_s.reg82;
-- store reg83
elsif(reg83_re_s = '1') then
reg_out_s.reg83 <= reg_in_s.reg83;
-- store reg84
elsif(reg84_re_s = '1') then
reg_out_s.reg84 <= reg_in_s.reg84;
-- store reg85
elsif(reg85_re_s = '1') then
reg_out_s.reg85 <= reg_in_s.reg85;
-- store reg86
elsif(reg86_re_s = '1') then
reg_out_s.reg86 <= reg_in_s.reg86;
-- store reg87
elsif(reg87_re_s = '1') then
reg_out_s.reg87 <= reg_in_s.reg87;
-- store reg88
elsif(reg88_re_s = '1') then
reg_out_s.reg88 <= reg_in_s.reg88;
-- store reg89
elsif(reg89_re_s = '1') then
reg_out_s.reg89 <= reg_in_s.reg89;
-- store reg90
elsif(reg90_re_s = '1') then
reg_out_s.reg90 <= reg_in_s.reg90;
-- store reg91
elsif(reg91_re_s = '1') then
reg_out_s.reg91 <= reg_in_s.reg91;
-- store reg92
elsif(reg92_re_s = '1') then
reg_out_s.reg92 <= reg_in_s.reg92;
-- store reg93
elsif(reg93_re_s = '1') then
reg_out_s.reg93 <= reg_in_s.reg93;
-- store reg94
elsif(reg94_re_s = '1') then
reg_out_s.reg94 <= reg_in_s.reg94;
-- store reg95
elsif(reg95_re_s = '1') then
reg_out_s.reg95 <= reg_in_s.reg95;
-- store reg96
elsif(reg96_re_s = '1') then
reg_out_s.reg96 <= reg_in_s.reg96;
-- store reg97
elsif(reg97_re_s = '1') then
reg_out_s.reg97 <= reg_in_s.reg97;
-- store reg98
elsif(reg98_re_s = '1') then
reg_out_s.reg98 <= reg_in_s.reg98;
-- store reg99
elsif(reg99_re_s = '1') then
reg_out_s.reg99 <= reg_in_s.reg99;
-- store reg100
elsif(reg100_re_s = '1') then
reg_out_s.reg100 <= reg_in_s.reg100;
-- store reg101
elsif(reg101_re_s = '1') then
reg_out_s.reg101 <= reg_in_s.reg101;
-- store reg102
elsif(reg102_re_s = '1') then
reg_out_s.reg102 <= reg_in_s.reg102;
-- store reg103
elsif(reg103_re_s = '1') then
reg_out_s.reg103 <= reg_in_s.reg103;
-- store reg104
elsif(reg104_re_s = '1') then
reg_out_s.reg104 <= reg_in_s.reg104;
-- store reg105
elsif(reg105_re_s = '1') then
reg_out_s.reg105 <= reg_in_s.reg105;
-- store reg106
elsif(reg106_re_s = '1') then
reg_out_s.reg106 <= reg_in_s.reg106;
-- store reg107
elsif(reg107_re_s = '1') then
reg_out_s.reg107 <= reg_in_s.reg107;
-- store reg108
elsif(reg108_re_s = '1') then
reg_out_s.reg108 <= reg_in_s.reg108;
-- store reg109
elsif(reg109_re_s = '1') then
reg_out_s.reg109 <= reg_in_s.reg109;
-- store reg110
elsif(reg110_re_s = '1') then
reg_out_s.reg110 <= reg_in_s.reg110;
-- store reg111
elsif(reg111_re_s = '1') then
reg_out_s.reg111 <= reg_in_s.reg111;
-- store reg112
elsif(reg112_re_s = '1') then
reg_out_s.reg112 <= reg_in_s.reg112;
-- store reg113
elsif(reg113_re_s = '1') then
reg_out_s.reg113 <= reg_in_s.reg113;
-- store reg114
elsif(reg114_re_s = '1') then
reg_out_s.reg114 <= reg_in_s.reg114;
-- store reg115
elsif(reg115_re_s = '1') then
reg_out_s.reg115 <= reg_in_s.reg115;
-- store reg116
elsif(reg116_re_s = '1') then
reg_out_s.reg116 <= reg_in_s.reg116;
-- store reg117
elsif(reg117_re_s = '1') then
reg_out_s.reg117 <= reg_in_s.reg117;
-- store reg118
elsif(reg118_re_s = '1') then
reg_out_s.reg118 <= reg_in_s.reg118;
-- store reg119
elsif(reg119_re_s = '1') then
reg_out_s.reg119 <= reg_in_s.reg119;
-- store reg120
elsif(reg120_re_s = '1') then
reg_out_s.reg120 <= reg_in_s.reg120;
-- store reg121
elsif(reg121_re_s = '1') then
reg_out_s.reg121 <= reg_in_s.reg121;
-- store reg122
elsif(reg122_re_s = '1') then
reg_out_s.reg122 <= reg_in_s.reg122;
-- store reg123
elsif(reg123_re_s = '1') then
reg_out_s.reg123 <= reg_in_s.reg123;
-- store reg124
elsif(reg124_re_s = '1') then
reg_out_s.reg124 <= reg_in_s.reg124;
-- store reg125
elsif(reg125_re_s = '1') then
reg_out_s.reg125 <= reg_in_s.reg125;
-- store reg126
elsif(reg126_re_s = '1') then
reg_out_s.reg126 <= reg_in_s.reg126;
-- store reg127
elsif(reg127_re_s = '1') then
reg_out_s.reg127 <= reg_in_s.reg127;
-- store reg128
elsif(reg128_re_s = '1') then
reg_out_s.reg128 <= reg_in_s.reg128;
-- store reg129
elsif(reg129_re_s = '1') then
reg_out_s.reg129 <= reg_in_s.reg129;
-- store reg130
elsif(reg130_re_s = '1') then
reg_out_s.reg130 <= reg_in_s.reg130;
-- store reg131
elsif(reg131_re_s = '1') then
reg_out_s.reg131 <= reg_in_s.reg131;
-- store reg132
elsif(reg132_re_s = '1') then
reg_out_s.reg132 <= reg_in_s.reg132;
-- store reg133
elsif(reg133_re_s = '1') then
reg_out_s.reg133 <= reg_in_s.reg133;
-- store reg134
elsif(reg134_re_s = '1') then
reg_out_s.reg134 <= reg_in_s.reg134;
-- store reg135
elsif(reg135_re_s = '1') then
reg_out_s.reg135 <= reg_in_s.reg135;
-- store reg136
elsif(reg136_re_s = '1') then
reg_out_s.reg136 <= reg_in_s.reg136;
-- store reg137
elsif(reg137_re_s = '1') then
reg_out_s.reg137 <= reg_in_s.reg137;
-- store reg138
elsif(reg138_re_s = '1') then
reg_out_s.reg138 <= reg_in_s.reg138;
-- store reg139
elsif(reg139_re_s = '1') then
reg_out_s.reg139 <= reg_in_s.reg139;
-- store reg140
elsif(reg140_re_s = '1') then
reg_out_s.reg140 <= reg_in_s.reg140;
-- store reg141
elsif(reg141_re_s = '1') then
reg_out_s.reg141 <= reg_in_s.reg141;
-- store reg142
elsif(reg142_re_s = '1') then
reg_out_s.reg142 <= reg_in_s.reg142;
-- store reg143
elsif(reg143_re_s = '1') then
reg_out_s.reg143 <= reg_in_s.reg143;
-- store reg144
elsif(reg144_re_s = '1') then
reg_out_s.reg144 <= reg_in_s.reg144;
-- store reg145
elsif(reg145_re_s = '1') then
reg_out_s.reg145 <= reg_in_s.reg145;
-- store reg146
elsif(reg146_re_s = '1') then
reg_out_s.reg146 <= reg_in_s.reg146;
-- store reg147
elsif(reg147_re_s = '1') then
reg_out_s.reg147 <= reg_in_s.reg147;
-- store reg148
elsif(reg148_re_s = '1') then
reg_out_s.reg148 <= reg_in_s.reg148;
-- store reg149
elsif(reg149_re_s = '1') then
reg_out_s.reg149 <= reg_in_s.reg149;
-- store reg150
elsif(reg150_re_s = '1') then
reg_out_s.reg150 <= reg_in_s.reg150;
-- store reg151
elsif(reg151_re_s = '1') then
reg_out_s.reg151 <= reg_in_s.reg151;
-- store reg152
elsif(reg152_re_s = '1') then
reg_out_s.reg152 <= reg_in_s.reg152;
-- store reg153
elsif(reg153_re_s = '1') then
reg_out_s.reg153 <= reg_in_s.reg153;
-- store reg154
elsif(reg154_re_s = '1') then
reg_out_s.reg154 <= reg_in_s.reg154;
-- store reg155
elsif(reg155_re_s = '1') then
reg_out_s.reg155 <= reg_in_s.reg155;
-- store reg156
elsif(reg156_re_s = '1') then
reg_out_s.reg156 <= reg_in_s.reg156;
-- store reg157
elsif(reg157_re_s = '1') then
reg_out_s.reg157 <= reg_in_s.reg157;
-- store reg158
elsif(reg158_re_s = '1') then
reg_out_s.reg158 <= reg_in_s.reg158;
-- store reg159
elsif(reg159_re_s = '1') then
reg_out_s.reg159 <= reg_in_s.reg159;
-- store reg160
elsif(reg160_re_s = '1') then
reg_out_s.reg160 <= reg_in_s.reg160;
-- store reg161
elsif(reg161_re_s = '1') then
reg_out_s.reg161 <= reg_in_s.reg161;
-- store reg162
elsif(reg162_re_s = '1') then
reg_out_s.reg162 <= reg_in_s.reg162;
-- store reg163
elsif(reg163_re_s = '1') then
reg_out_s.reg163 <= reg_in_s.reg163;
-- store reg164
elsif(reg164_re_s = '1') then
reg_out_s.reg164 <= reg_in_s.reg164;
-- store reg165
elsif(reg165_re_s = '1') then
reg_out_s.reg165 <= reg_in_s.reg165;
-- store reg166
elsif(reg166_re_s = '1') then
reg_out_s.reg166 <= reg_in_s.reg166;
-- store reg167
elsif(reg167_re_s = '1') then
reg_out_s.reg167 <= reg_in_s.reg167;
-- store reg168
elsif(reg168_re_s = '1') then
reg_out_s.reg168 <= reg_in_s.reg168;
-- store reg169
elsif(reg169_re_s = '1') then
reg_out_s.reg169 <= reg_in_s.reg169;
-- store reg170
elsif(reg170_re_s = '1') then
reg_out_s.reg170 <= reg_in_s.reg170;
-- store reg171
elsif(reg171_re_s = '1') then
reg_out_s.reg171 <= reg_in_s.reg171;
-- store reg172
elsif(reg172_re_s = '1') then
reg_out_s.reg172 <= reg_in_s.reg172;
-- store reg173
elsif(reg173_re_s = '1') then
reg_out_s.reg173 <= reg_in_s.reg173;
-- store reg174
elsif(reg174_re_s = '1') then
reg_out_s.reg174 <= reg_in_s.reg174;
-- store reg175
elsif(reg175_re_s = '1') then
reg_out_s.reg175 <= reg_in_s.reg175;
-- store reg176
elsif(reg176_re_s = '1') then
reg_out_s.reg176 <= reg_in_s.reg176;
-- store reg177
elsif(reg177_re_s = '1') then
reg_out_s.reg177 <= reg_in_s.reg177;
-- store reg178
elsif(reg178_re_s = '1') then
reg_out_s.reg178 <= reg_in_s.reg178;
-- store reg179
elsif(reg179_re_s = '1') then
reg_out_s.reg179 <= reg_in_s.reg179;
-- store reg180
elsif(reg180_re_s = '1') then
reg_out_s.reg180 <= reg_in_s.reg180;
-- store reg181
elsif(reg181_re_s = '1') then
reg_out_s.reg181 <= reg_in_s.reg181;
-- store reg182
elsif(reg182_re_s = '1') then
reg_out_s.reg182 <= reg_in_s.reg182;
-- store reg183
elsif(reg183_re_s = '1') then
reg_out_s.reg183 <= reg_in_s.reg183;
-- store reg184
elsif(reg184_re_s = '1') then
reg_out_s.reg184 <= reg_in_s.reg184;
-- store reg185
elsif(reg185_re_s = '1') then
reg_out_s.reg185 <= reg_in_s.reg185;
-- store reg186
elsif(reg186_re_s = '1') then
reg_out_s.reg186 <= reg_in_s.reg186;
-- store reg187
elsif(reg187_re_s = '1') then
reg_out_s.reg187 <= reg_in_s.reg187;
-- store reg188
elsif(reg188_re_s = '1') then
reg_out_s.reg188 <= reg_in_s.reg188;
-- store reg189
elsif(reg189_re_s = '1') then
reg_out_s.reg189 <= reg_in_s.reg189;
-- store reg190
elsif(reg190_re_s = '1') then
reg_out_s.reg190 <= reg_in_s.reg190;
-- store reg191
elsif(reg191_re_s = '1') then
reg_out_s.reg191 <= reg_in_s.reg191;
-- store reg192
elsif(reg192_re_s = '1') then
reg_out_s.reg192 <= reg_in_s.reg192;
-- store reg193
elsif(reg193_re_s = '1') then
reg_out_s.reg193 <= reg_in_s.reg193;
-- store reg194
elsif(reg194_re_s = '1') then
reg_out_s.reg194 <= reg_in_s.reg194;
-- store reg195
elsif(reg195_re_s = '1') then
reg_out_s.reg195 <= reg_in_s.reg195;
-- store reg196
elsif(reg196_re_s = '1') then
reg_out_s.reg196 <= reg_in_s.reg196;
-- store reg197
elsif(reg197_re_s = '1') then
reg_out_s.reg197 <= reg_in_s.reg197;
-- store reg198
elsif(reg198_re_s = '1') then
reg_out_s.reg198 <= reg_in_s.reg198;
-- store reg199
elsif(reg199_re_s = '1') then
reg_out_s.reg199 <= reg_in_s.reg199;
-- store reg200
elsif(reg200_re_s = '1') then
reg_out_s.reg200 <= reg_in_s.reg200;
-- store reg201
elsif(reg201_re_s = '1') then
reg_out_s.reg201 <= reg_in_s.reg201;
-- store reg202
elsif(reg202_re_s = '1') then
reg_out_s.reg202 <= reg_in_s.reg202;
-- store reg203
elsif(reg203_re_s = '1') then
reg_out_s.reg203 <= reg_in_s.reg203;
-- store reg204
elsif(reg204_re_s = '1') then
reg_out_s.reg204 <= reg_in_s.reg204;
-- store reg205
elsif(reg205_re_s = '1') then
reg_out_s.reg205 <= reg_in_s.reg205;
-- store reg206
elsif(reg206_re_s = '1') then
reg_out_s.reg206 <= reg_in_s.reg206;
-- store reg207
elsif(reg207_re_s = '1') then
reg_out_s.reg207 <= reg_in_s.reg207;
-- store reg208
elsif(reg208_re_s = '1') then
reg_out_s.reg208 <= reg_in_s.reg208;
-- store reg209
elsif(reg209_re_s = '1') then
reg_out_s.reg209 <= reg_in_s.reg209;
-- store reg210
elsif(reg210_re_s = '1') then
reg_out_s.reg210 <= reg_in_s.reg210;
-- store reg211
elsif(reg211_re_s = '1') then
reg_out_s.reg211 <= reg_in_s.reg211;
-- store reg212
elsif(reg212_re_s = '1') then
reg_out_s.reg212 <= reg_in_s.reg212;
-- store reg213
elsif(reg213_re_s = '1') then
reg_out_s.reg213 <= reg_in_s.reg213;
-- store reg214
elsif(reg214_re_s = '1') then
reg_out_s.reg214 <= reg_in_s.reg214;
-- store reg215
elsif(reg215_re_s = '1') then
reg_out_s.reg215 <= reg_in_s.reg215;
-- store reg216
elsif(reg216_re_s = '1') then
reg_out_s.reg216 <= reg_in_s.reg216;
-- store reg217
elsif(reg217_re_s = '1') then
reg_out_s.reg217 <= reg_in_s.reg217;
-- store reg218
elsif(reg218_re_s = '1') then
reg_out_s.reg218 <= reg_in_s.reg218;
-- store reg219
elsif(reg219_re_s = '1') then
reg_out_s.reg219 <= reg_in_s.reg219;
-- store reg220
elsif(reg220_re_s = '1') then
reg_out_s.reg220 <= reg_in_s.reg220;
-- store reg221
elsif(reg221_re_s = '1') then
reg_out_s.reg221 <= reg_in_s.reg221;
-- store reg222
elsif(reg222_re_s = '1') then
reg_out_s.reg222 <= reg_in_s.reg222;
-- store reg223
elsif(reg223_re_s = '1') then
reg_out_s.reg223 <= reg_in_s.reg223;
-- store reg224
elsif(reg224_re_s = '1') then
reg_out_s.reg224 <= reg_in_s.reg224;
-- store reg225
elsif(reg225_re_s = '1') then
reg_out_s.reg225 <= reg_in_s.reg225;
-- store reg226
elsif(reg226_re_s = '1') then
reg_out_s.reg226 <= reg_in_s.reg226;
-- store reg227
elsif(reg227_re_s = '1') then
reg_out_s.reg227 <= reg_in_s.reg227;
-- store reg228
elsif(reg228_re_s = '1') then
reg_out_s.reg228 <= reg_in_s.reg228;
-- store reg229
elsif(reg229_re_s = '1') then
reg_out_s.reg229 <= reg_in_s.reg229;
-- store reg230
elsif(reg230_re_s = '1') then
reg_out_s.reg230 <= reg_in_s.reg230;
-- store reg231
elsif(reg231_re_s = '1') then
reg_out_s.reg231 <= reg_in_s.reg231;
-- store reg232
elsif(reg232_re_s = '1') then
reg_out_s.reg232 <= reg_in_s.reg232;
-- store reg233
elsif(reg233_re_s = '1') then
reg_out_s.reg233 <= reg_in_s.reg233;
-- store reg234
elsif(reg234_re_s = '1') then
reg_out_s.reg234 <= reg_in_s.reg234;
-- store reg235
elsif(reg235_re_s = '1') then
reg_out_s.reg235 <= reg_in_s.reg235;
-- store reg236
elsif(reg236_re_s = '1') then
reg_out_s.reg236 <= reg_in_s.reg236;
-- store reg237
elsif(reg237_re_s = '1') then
reg_out_s.reg237 <= reg_in_s.reg237;
-- store reg238
elsif(reg238_re_s = '1') then
reg_out_s.reg238 <= reg_in_s.reg238;
-- store reg239
elsif(reg239_re_s = '1') then
reg_out_s.reg239 <= reg_in_s.reg239;
-- store reg240
elsif(reg240_re_s = '1') then
reg_out_s.reg240 <= reg_in_s.reg240;
-- store reg241
elsif(reg241_re_s = '1') then
reg_out_s.reg241 <= reg_in_s.reg241;
-- store reg242
elsif(reg242_re_s = '1') then
reg_out_s.reg242 <= reg_in_s.reg242;
-- store reg243
elsif(reg243_re_s = '1') then
reg_out_s.reg243 <= reg_in_s.reg243;
-- store reg244
elsif(reg244_re_s = '1') then
reg_out_s.reg244 <= reg_in_s.reg244;
-- store reg245
elsif(reg245_re_s = '1') then
reg_out_s.reg245 <= reg_in_s.reg245;
-- store reg246
elsif(reg246_re_s = '1') then
reg_out_s.reg246 <= reg_in_s.reg246;
-- store reg247
elsif(reg247_re_s = '1') then
reg_out_s.reg247 <= reg_in_s.reg247;
-- store reg248
elsif(reg248_re_s = '1') then
reg_out_s.reg248 <= reg_in_s.reg248;
-- store reg249
elsif(reg249_re_s = '1') then
reg_out_s.reg249 <= reg_in_s.reg249;
-- store reg250
elsif(reg250_re_s = '1') then
reg_out_s.reg250 <= reg_in_s.reg250;
-- store reg251
elsif(reg251_re_s = '1') then
reg_out_s.reg251 <= reg_in_s.reg251;
-- store reg252
elsif(reg252_re_s = '1') then
reg_out_s.reg252 <= reg_in_s.reg252;
-- store reg253
elsif(reg253_re_s = '1') then
reg_out_s.reg253 <= reg_in_s.reg253;
-- store reg254
elsif(reg254_re_s = '1') then
reg_out_s.reg254 <= reg_in_s.reg254;
-- store reg255
elsif(reg255_re_s = '1') then
reg_out_s.reg255 <= reg_in_s.reg255;
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
type t_int1 is range 0 to 100 ;
subtype st_int1 is t_int1 range 8 to 60 ;
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr2_range1 is integer range 1 to 10 ;
subtype t_arr2_range2 is boolean range false to true ;
subtype t_arr1_range1 is integer range 1 to 10 ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
type t_rec1 is record
f1 : integer range 0 to 1000 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
subtype st_rec1 is t_rec1 ;
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
subtype st_rec2 is t_rec2 ;
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
begin
main: process
type t_new_int1 is range -10 to 10;
type t_new_int2 is range -10 to 10;
variable a : t_new_int1 := 0;
variable b : t_new_int2 := 0;
begin
-- should fail
-- b:=a;
report "Process in the architecture of the entity.";
wait;
end process;
end;
|
--------------------------------------------------------------------------------
-- Entity: usb_tracer
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_tracer is
port (
clock : in std_logic;
reset : in std_logic;
usb_data : in std_logic_vector(7 downto 0);
usb_valid : in std_logic;
usb_rxcmd : in std_logic;
stream_out : out std_logic_vector(31 downto 0);
stream_valid: out std_logic );
end entity;
architecture arch of usb_tracer is
signal counter : unsigned(27 downto 0);
signal raw_rd : std_logic;
signal raw_wr : std_logic;
signal raw_valid : std_logic;
signal raw_in : std_logic_vector(37 downto 0);
signal raw_in : std_logic_vector(37 downto 0);
signal enc16 : std_logic_vector(15 downto 0);
signal enc16_push : std_logic;
type t_state is (idle, ext1, format1, format3a, format3b);
signal state, next_state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
raw_wr <= '0';
if usb_valid = '1' then
raw_in <= '0' & usb_rxcmd & usb_data & std_logic_vector(counter);
raw_wr <= '1';
counter <= to_unsigned(1, counter'length);
elsif counter = X"FFFFFFF" then
raw_in <= "10" & X"00" & std_logic_vector(counter);
raw_wr <= '1';
counter <= to_unsigned(1, counter'length);
else
counter <= counter + 1;
end if;
if reset = '1' then
counter <= (others => '0');
end if;
end if;
end process;
i_raw_fifo: entity work.sync_fifo
generic map(
g_depth => 15,
g_data_width => 38,
g_threshold => 8,
g_storage => "auto",
g_fall_through => true
)
port map(
clock => clock,
reset => reset,
rd_en => raw_rd,
wr_en => raw_wr,
din => raw_in,
dout => raw_out,
flush => '0',
valid => raw_valid
);
p_encode: process(raw_out, raw_valid, state)
begin
next_state <= state;
enc16 <= (others => 'X');
enc16_push <= '0';
raw_rd <= '0';
case state is
when idle =>
if raw_valid = '1' then
if raw_out(37 downto 36) = "10" then
enc16 <= X"3FFF";
enc16_push <= '1';
raw_rd <= '1';
next_state <= ext1;
elsif raw_out(27 downto 4) = X"000000" then -- Format 0 feasible
enc16 <= '1' & raw_out(36) & "00" & raw_out(3 downto 0) & raw_out(35 downto 28);
enc16_push <= '1';
raw_rd <= '1';
elsif raw_out(27 downto 20) = X"000" then -- Format 1 or 2 are feasible
enc16 <= '1' & raw_out(36) & "01" & raw_out(3 downto 0) & raw_out(11 downto 4);
enc16_push <= '1';
next_state <= format1;
else
enc16 <= '1' & raw_out(36) & "11" & raw_out(3 downto 0) & raw_out(11 downto 4);
enc16_push <= '1';
next_state <= format3a;
end if;
end if;
when ext1 =>
enc16 <= X"FFFF";
enc16_push <= '1';
next_state <= idle;
when format1 =>
enc16 <= raw_out(35 downto 28) & raw_out(19 downto 12);
enc16_push <= '1';
raw_rd <= '1';
next_state <= idle;
when format3a =>
enc16 <= raw_out(19 downto 12) & raw_out(27 downto 20);
enc16_push <= '1';
next_state <= format3b;
when format3b =>
enc16 <= X"00" & raw_out(35 downto 28);
enc16_push <= '1';
raw_rd <= '1';
next_state <= idle;
when others =>
null;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
state <= next_state;
stream_valid <= '0';
if enc16_push = '1' then
if toggle = '0' then
stream_out(15 downto 0) <= enc16;
toggle <= '1';
else
stream_out(31 downto 16) <= enc16;
stream_valid <= '1';
toggle <= '0';
end if;
end if;
if reset = '1' then
state <= idle;
toggle <= '0';
stream_out <= (others => '0');
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block4
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_6_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_6_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_14_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_14_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_11_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_12_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_12_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_11_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block4 IS
-- Signals
SIGNAL twdlXdin_6_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_6_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_14_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_14_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_11_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_11_im_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_12_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_12_im_tmp : signed(17 DOWNTO 0); -- sfix18
BEGIN
twdlXdin_6_re_signed <= signed(twdlXdin_6_re);
twdlXdin_6_im_signed <= signed(twdlXdin_6_im);
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_6_re_signed,
twdlXdin_6_im_signed, twdlXdin_14_re_signed, twdlXdin_14_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_6_re_signed, 19) + resize(twdlXdin_14_re_signed, 19);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_6_re_signed, 19) - resize(twdlXdin_14_re_signed, 19);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_6_im_signed, 19) + resize(twdlXdin_14_im_signed, 19);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_6_im_signed, 19) - resize(twdlXdin_14_im_signed, 19);
END IF;
dout_11_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(17 DOWNTO 0);
dout_11_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(17 DOWNTO 0);
dout_12_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(17 DOWNTO 0);
dout_12_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(17 DOWNTO 0);
dout_11_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re <= std_logic_vector(dout_12_re_tmp);
dout_12_im <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_b is
port (
q : in std_logic_vector(31 downto 0);
A : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
clock : in std_logic;
B : out std_logic_vector(31 downto 0)
);
end k_ukf_b;
architecture struct of k_ukf_b is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_div IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => q,
datab => A,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => k,
datab => T,
result => Z2);
M3 : k_ukf_div port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => B);
end struct; |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
entity phz_calc is
end entity phz_calc;
architecture behavioral of phz_calc is
function to_string (inp: sfixed) return string is
variable image_str: string (1 to inp'length + 1);
variable j: integer range 1 to image_str'length + 1;
begin
j := 1;
for i in inp'range loop
if i = -1 then
image_str(j) := '.';
j := j + 1;
end if;
image_str(j) := character'VALUE(std_ulogic'IMAGE(inp(i)));
j := j + 1;
end loop;
return image_str;
end function;
begin
process
variable z: sfixed (3 downto -3);
begin
z := to_sfixed(3.2,3,-3);
report "z = " & to_string (z);
wait;
end process;
end architecture behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3084.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b03x00p02n01i03084ent IS
END c12s06b03x00p02n01i03084ent;
ARCHITECTURE c12s06b03x00p02n01i03084arch OF c12s06b03x00p02n01i03084ent IS
signal S1 : BIT;
BEGIN
S1 <= transport '1' after 5 ns,
'0' after 15 ns;
A : block(S1 = '1')
begin
process
begin
wait on GUARD;
if GUARD then
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
else
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
end if;
end process;
end block A;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert FALSE
report "***PASSED TEST: c12s06b03x00p02n01i03084 - This test needs manual check to see other two PASS assertion note."
severity NOTE;
wait;
END PROCESS TESTING;
END c12s06b03x00p02n01i03084arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3084.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b03x00p02n01i03084ent IS
END c12s06b03x00p02n01i03084ent;
ARCHITECTURE c12s06b03x00p02n01i03084arch OF c12s06b03x00p02n01i03084ent IS
signal S1 : BIT;
BEGIN
S1 <= transport '1' after 5 ns,
'0' after 15 ns;
A : block(S1 = '1')
begin
process
begin
wait on GUARD;
if GUARD then
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
else
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
end if;
end process;
end block A;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert FALSE
report "***PASSED TEST: c12s06b03x00p02n01i03084 - This test needs manual check to see other two PASS assertion note."
severity NOTE;
wait;
END PROCESS TESTING;
END c12s06b03x00p02n01i03084arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3084.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b03x00p02n01i03084ent IS
END c12s06b03x00p02n01i03084ent;
ARCHITECTURE c12s06b03x00p02n01i03084arch OF c12s06b03x00p02n01i03084ent IS
signal S1 : BIT;
BEGIN
S1 <= transport '1' after 5 ns,
'0' after 15 ns;
A : block(S1 = '1')
begin
process
begin
wait on GUARD;
if GUARD then
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
else
assert false
report "No failure; Changes on signal S1 have modified the GUARD signal"
severity NOTE;
end if;
end process;
end block A;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert FALSE
report "***PASSED TEST: c12s06b03x00p02n01i03084 - This test needs manual check to see other two PASS assertion note."
severity NOTE;
wait;
END PROCESS TESTING;
END c12s06b03x00p02n01i03084arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(15 DOWNTO 0) <= WRITE_ADDR(15 DOWNTO 0);
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(15 DOWNTO 0) <= WRITE_ADDR(15 DOWNTO 0);
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Wrapper module for the user design top level file. This module can be
-- instantiated in the system and interconnect as shown in example design
-- (example_top module).
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end entity ddr;
architecture arch_ddr of ddr is
-- Start of IP top component
component ddr_mig
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr_mig;
-- End of IP top component
begin
-- Start of IP top instance
u_ddr_mig : ddr_mig
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_ref_req => app_ref_req,
app_zq_req => app_zq_req,
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of IP top instance
end architecture arch_ddr;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc704.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00704ent IS
END c03s04b01x00p23n01i00704ent;
ARCHITECTURE c03s04b01x00p23n01i00704arch OF c03s04b01x00p23n01i00704ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
type FT is file of BIT_VECTOR5;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.57";
-- Declare a variable.
constant CON : BIT_VECTOR5 := B"10101";
variable VAR : BIT_VECTOR5 := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00704 - The output file will tested by test file s010436.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00704arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc704.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00704ent IS
END c03s04b01x00p23n01i00704ent;
ARCHITECTURE c03s04b01x00p23n01i00704arch OF c03s04b01x00p23n01i00704ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
type FT is file of BIT_VECTOR5;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.57";
-- Declare a variable.
constant CON : BIT_VECTOR5 := B"10101";
variable VAR : BIT_VECTOR5 := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00704 - The output file will tested by test file s010436.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00704arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc704.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00704ent IS
END c03s04b01x00p23n01i00704ent;
ARCHITECTURE c03s04b01x00p23n01i00704arch OF c03s04b01x00p23n01i00704ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
type FT is file of BIT_VECTOR5;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.57";
-- Declare a variable.
constant CON : BIT_VECTOR5 := B"10101";
variable VAR : BIT_VECTOR5 := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00704 - The output file will tested by test file s010436.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00704arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:57:43 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_RegFile - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The register file for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_RegFile is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
ld_val: in STD_LOGIC;
ALUB_out : in STD_LOGIC;
src1_addr : in STD_LOGIC_VECTOR(2 downto 0);
src2_addr : in STD_LOGIC_VECTOR(2 downto 0);
dest_addr : in STD_LOGIC_VECTOR(2 downto 0);
data_to_load : in STD_LOGIC_VECTOR(15 downto 0);
to_ALUA_out : out STD_LOGIC_VECTOR(15 downto 0);
to_ALUB_out : out STD_LOGIC_VECTOR(15 downto 0);
data_collection_1 : out STD_LOGIC_VECTOR(15 downto 0)); --
end TestCPU1_RegFile;
architecture Behavioral of TestCPU1_RegFile is
begin
RegFile: process (clock, reset, ALUB_out, src1_addr, src2_addr) is
type reg_array is array (7 downto 0) of
STD_LOGIC_VECTOR(15 downto 0);
variable reg_file: reg_array := (others => b"0000000000000000");
begin
if falling_edge(clock) then
if reset = '1' then
reg_file := (others => b"0000000000000000");
elsif ((ld_val = '1') and (dest_addr /= b"000")) then
reg_file(conv_integer(unsigned(dest_addr))) := data_to_load;
end if;
end if;
if ALUB_out = '0' then
to_ALUB_out <= x"0000";
else
to_ALUB_out <= reg_file(conv_integer(unsigned(src2_addr)));
end if;
to_ALUA_out <= reg_file(conv_integer(unsigned(src1_addr)));
data_collection_1 <= reg_file(1);
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.usb1_ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.usb1_ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
CONSTANT rd_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
CONSTANT rd_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
CONSTANT rd_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emddis : out std_logic;
epwrdwn : out std_ulogic;
ereset : out std_ulogic;
esleep : out std_ulogic;
epause : out std_ulogic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk : std_ulogic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET), CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED,
CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp0 : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_GRPCI2_MASTER = 0 generate ahbso(4) <= ahbs_none; end generate;
nop2 : if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
apbo(4) <= apb_none; apbo(5) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech, netlist => CFG_SPW_NETLIST,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
ports => 1, dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
--===========================================================================--
-- --
-- ps2_keyboard.vhd - Synthesizable PS/2 Keyboard Interface --
-- --
--===========================================================================--
--
-- File name : ps2_keyboard.vhd
--
-- Purpose : Implements a PS/2 Keyboard Interface
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Author : Original Verilog version by John Clayton
-- Converted to VHDL by John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description :
--
-- This is a state-machine driven serial-to-parallel and parallel-to-serial
-- interface to the ps2 style keyboard interface. The details of the operation
-- of the keyboard interface were obtained from the following website:
--
-- http://www.beyondlogic.org/keyboard/keybrd.htm
--
-- Some aspects of the keyboard interface are not implemented (e.g, parity
-- checking for the receive side, and recognition of the various commands
-- which the keyboard sends out, such as "power on selt test passed," "Error"
-- and "Resend.") However, if the user wishes to recognize these reply
-- messages, the scan code output can always be used to extend functionality
-- as desired.
--
-- Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
-- The rx interface provides separate indicator flags for these two conditions
-- with every valid character scan code which it provides. The shift keys are
-- also trapped by the interface, in order to provide correct uppercase ASCII
-- characters at the ascii output, although the scan codes for the shift keys
-- are still provided at the scan code output. So, the left/right ALT keys
-- can be differentiated by the presence of the rx_entended signal, while the
-- left/right shift keys are differentiable by the different scan codes
-- received.
--
-- The interface to the ps2 keyboard uses ps2_clk clock rates of
-- 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
-- machine runs should be at least twice the rate of the ps2_clk, so that the
-- states can accurately follow the clock signal itself. Four times
-- oversampling is better. Say 200kHz at least. The upper limit for clocking
-- the state machine will undoubtedly be determined by delays in the logic
-- which decodes the scan codes into ASCII equivalents. The maximum speed
-- will be most likely many megahertz, depending upon target technology.
-- In order to run the state machine extremely fast, synchronizing flip-flops
-- have been added to the ps2_clk and ps2_data inputs of the state machine.
-- This avoids poor performance related to slow transitions of the inputs.
--
-- Because this is a bi-directional interface, while reading from the keyboard
-- the ps2_clk and ps2_data lines are used as inputs. While writing to the
-- keyboard, however (which may be done at any time. If writing interrupts a
-- read from the keyboard, the keyboard will buffer up its data, and send
-- it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
-- and pullup resistors are used to bring the lines high again, by setting
-- the drivers to high impedance state.
--
-- The tx interface, for writing to the keyboard, does not provide any special
-- pre-processing. It simply transmits the 8-bit command value to the
-- keyboard.
--
-- Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
-- whether they be internal to an FPGA I/O pad, or externally placed.
-- If internal pullups are used, they may be fairly weak, causing bounces
-- due to crosstalk, etc. There is a "debounce timer" implemented in order
-- to eliminate erroneous state transitions which would occur based on bounce.
--
-- Parameters are provided in order to configure and appropriately size the
-- counter of a 60 microsecond timer used in the transmitter, depending on
-- the clock frequency used. The 60 microsecond period is guaranteed to be
-- more than one period of the ps2_clk_s signal.
--
-- Also, a smaller 5 microsecond timer has been included for "debounce".
-- This is used because, with internal pullups on the ps2_clk and ps2_data
-- lines, there is some bouncing around which occurs
--
-- A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
-- from producing scan codes (along with their "undefined" ASCII equivalents)
-- at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
-- key status will only be reported by rx_shift_on. No ascii or scan
-- codes will be reported for the shift keys. This is useful for those who
-- wish to use the ASCII data stream, and who don't want to have to "filter
-- out" the shift key codes.
--
-- Copyright (C) 2001 - 2010 John Clayton and John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Author: John Clayton
-- 2001-04-30 copied this file from lcd_2.v (pared down).
-- 2001-05-24 changed the first module from "ps2_keyboard_receiver"
-- to "ps2_keyboard_interface"
-- 2001-05-29 Added input synchronizing flip-flops. Changed state
-- encoding (m1) for good operation after part config.
-- 2001-05-31 Added low drive strength and slow transitions to ps2_clk
-- and ps2_data in the constraints file. Added the signal
-- "tx_shifting_done" as distinguished from "rx_shifting_done."
-- Debugged the transmitter portion in the lab.
-- 2001-06-01 Added horizontal tab to the ascii output.
-- 2001-06-01 Added parameter TRAP_SHIFT_KEYS.
-- 2001-06-05 Debugged the "debounce" timer functionality.
-- Used 60usec timer as a "watchdog" timeout during
-- receive from the keyboard. This means that a keyboard
-- can now be "hot plugged" into the interface, without
-- messing up the bit_count, since the bit_count is reset
-- to zero during periods of inactivity anyway. This was
-- difficult to debug. I ended up using the logic analyzer,
-- and had to scratch my head quite a bit.
-- 2001-06-06 Removed extra comments before the input synchronizing
-- flip-flops. Used the correct parameter to size the
-- 5usec_timer_count. Changed the name of this file from
-- ps2.v to ps2_keyboard.v
-- 2001-06/06 Removed "&& q[7:0]" in output_strobe logic. Removed extra
-- commented out "else" condition in the shift register and
-- bit counter.
-- 2001-06-07 Changed default values for 60usec timer parameters so that
-- they correspond to 60usec for a 49.152MHz clock.
--
-- Author: John Kent
--2001-02-10 Converted to VHDL
-- 2004-09-11 Added ctrl key
-- Changed undefined key codes to x"ff"
-- Reversed clock polarity
-- 2004-10-18 Added ctrl keys to ASCII ROM
-- Added CAPS Lock toggle.
-- 2007-02-06 Added Generic Clock parameter
-- 2010-05-31 Revised header, added GPL
-- 2010-06-17 Change some signal names for consistancy
-- 2010-10-24 Rearranged code to prevent shift key outputting characters
--
--
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
entity ps2_keyboard is
generic (
CLK_FREQ_MHZ : integer
);
port(
clk : in std_logic;
reset : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_read : in std_logic;
rx_data_ready : out std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_on : out std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_data_empty : out std_logic;
tx_error : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end ps2_keyboard;
-------------------------------------------------------------------------------
-- Architecture for ps2 keyboard interface
-------------------------------------------------------------------------------
architecture rtl of ps2_keyboard is
-----------------------------------------------------------------------------
constant TOTAL_BITS : integer := 11;
constant EXTEND_CODE : integer := 16#E0#;
constant RELEASE_CODE : integer := 16#F0#;
constant LEFT_SHIFT : integer := 16#12#;
constant RIGHT_SHIFT : integer := 16#59#;
constant CTRL_CODE : integer := 16#14#;
constant LEFT_ALT : integer := 16#11#;
constant CAPS_CODE : integer := 16#58#;
constant SCROLL_LOCK : integer := 16#7E#;
constant NUM_LOCK : integer := 16#77#;
-- constants
-- The timer value can be up to (2^bits) inclusive.
-- Values for 49.152 MHz clock
--constant TIMER_60USEC_VALUE_PP : integer := 2950; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 186; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
-- Values for 12.5 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 750; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 10; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 62; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 6; -- Number of bits needed for timer
-- Values for 25 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 1500; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 11; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 125; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 7; -- Number of bits needed for timer
-- Values for generic Clock up to 50 MHz
constant TIMER_60USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 60; -- Number of clock cycles for 60usec.
constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
constant TIMER_5USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 5; -- Number of clock cycles for debounce
constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Default: No shift key trap.
-- State encodings, provided as constants
-- for flexibility to the one instantiating the module.
-- In general, the default values need not be changed.
-- State "m1_rx_clk_l" has been chosen on purpose. Since the input
-- synchronizing flip-flops initially contain zero, it takes one clk
-- for them to update to reflect the actual (idle = high) status of
-- the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
-- allows the state machine to transition to m1_rx_clk_h when the true
-- values of the input signals become present at the outputs of the
-- synchronizing flip-flops. This initial transition is harmless, and it
-- eliminates the need for a "reset" pulse before the interface can operate.
type m1_type is ( m1_rx_clk_h, m1_rx_clk_l,
m1_tx_wait_clk_h, m1_tx_force_clk_l,
m1_tx_clk_h, m1_tx_clk_l,
m1_tx_wait_keyboard_ack, m1_tx_done_recovery,
m1_tx_error, m1_tx_rising_edge_marker,
m1_tx_first_wait_clk_h, m1_tx_first_wait_clk_l, m1_tx_reset_timer,
m1_rx_falling_edge_marker, m1_rx_rising_edge_marker );
-- Internal signal declarations
signal timer_60usec_done : std_logic;
signal timer_5usec_done : std_logic;
signal extended : std_logic;
signal released : std_logic;
signal shift_key_on : std_logic;
signal ctrl_key_on : std_logic;
signal caps_key_on : std_logic;
-- NOTE: These two signals used to be one. They
-- were split into two signals because of
-- shift key trapping. With shift key
-- trapping, no event is generated externally,
-- but the "hold" data must still be cleared
-- anyway regardless, in preparation for the
-- next scan codes.
signal rx_output_event : std_logic; -- Used only to clear: hold_released, hold_extended
signal rx_output_strobe : std_logic; -- Used to produce the actual output.
signal tx_parity_bit : std_logic;
signal rx_shifting_done : std_logic;
signal tx_shifting_done : std_logic;
signal shift_key_plus_code: std_logic_vector(8 downto 0);
signal q : std_logic_vector(TOTAL_BITS-1 downto 0);
signal m1_state : m1_type;
signal m1_next_state : m1_type;
signal bit_count : std_logic_vector(3 downto 0);
signal enable_timer_60usec: std_logic;
signal enable_timer_5usec : std_logic;
signal timer_60usec_count : std_logic_vector(TIMER_60USEC_BITS_PP-1 downto 0);
signal timer_5usec_count : std_logic_vector(TIMER_5USEC_BITS_PP-1 downto 0);
signal ascii : std_logic_vector(7 downto 0); -- "REG" type only because a case statement is used.
signal left_shift_key : std_logic;
signal right_shift_key : std_logic;
signal hold_extended : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal hold_released : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal ps2_clk_s : std_logic; -- Synchronous version of this input
signal ps2_data_s : std_logic; -- Synchronous version of this input
signal ps2_clk_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal ps2_data_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal tx_data_empty_o : std_logic;
--
-- key lookup table
--
component keymap_rom
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
begin
my_key_map : keymap_rom
Port map (
clk => clk,
rst => reset,
cs => '1',
rw => '1',
addr => shift_key_plus_code,
data_in => "00000000",
data_out => ascii
);
----------------------------------------------------------------------------
-- Module code
-- assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
-- assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
--
ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z )
begin
if( ps2_clk_hi_z = '1' ) then
ps2_clk <= 'Z';
else
ps2_clk <= '0';
end if;
if( ps2_data_hi_z = '1' ) then
ps2_data <= 'Z';
else
ps2_data <= '0';
end if;
end process;
-- Input "synchronizing" logic -- synchronizes the inputs to the state
-- machine clock, thus avoiding errors related to
-- spurious state machine transitions.
ps2_synch : process(clk, ps2_clk, ps2_data)
begin
if clk'event and clk='0' then
ps2_clk_s <= ps2_clk;
ps2_data_s <= ps2_data;
end if;
end process;
-- State register
m1_state_register : process( clk, reset, m1_state )
begin
if clk'event and clk='0' then
if (reset = '1') then
m1_state <= m1_rx_clk_h;
else
m1_state <= m1_next_state;
end if;
end if;
end process;
m1_state_logic : process( m1_state, q,
tx_shifting_done, tx_write,
ps2_clk_s, ps2_data_s,
timer_60usec_done, timer_5usec_done )
begin
-- Output signals default to this value, unless changed in a state condition.
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
case (m1_state) is
--
-- receive clock transitions
--
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
end if;
when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;
when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;
--
-- write to keyboard (Tx)
--
when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;
when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;
when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
-- This state must be included because the device might possibly
-- delay for up to 10 milliseconds before beginning its clock pulses.
-- During that waiting time, we cannot drive the data (q[0]) because it
-- is possibly 1, which would cause the keyboard to abort its receive
-- and the expected clocks would then never be generated.
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;
when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;
when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;
when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;
when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;
when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
end if;
when m1_tx_error =>
tx_error <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error;
end if;
when others =>
m1_next_state <= m1_rx_clk_h;
end case;
end process;
--
-- This is the bit counter
--
bit_counter: process(clk, reset, m1_state, bit_count )
begin
if clk'event and clk = '0' then
if ( reset = '1' ) or ( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done.
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and
( m1_state = m1_rx_clk_h ) and
( ps2_clk_s = '1' ) then
bit_count <= "0000"; -- rx watchdog timer reset
elsif ( m1_state = m1_rx_falling_edge_marker ) or -- increment for rx
(m1_state = m1_tx_rising_edge_marker) then -- increment for tx
bit_count <= bit_count + 1;
end if;
end if;
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;
if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
end process;
assign: process( bit_count, tx_write, m1_state, tx_data_empty_o, m1_state )
begin
--
-- This is the signal which enables loading of the shift register.
-- It also indicates "ack" to the device writing to the transmitter.
--
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_data_empty_o <= '1';
else
tx_data_empty_o <= '0';
end if;
tx_data_empty <= tx_data_empty_o;
end process;
-- This is the shift register
q_shift : process(clk, tx_data_empty_o, tx_parity_bit, tx_data,
m1_state, q, ps2_data_s, rx_shifting_done )
begin
--
-- This is the ODD parity bit for the transmitted word.
-- assign tx_parity_bit = ~^tx_data;
--
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor
tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );
if clk'event and clk='0' then
if (reset = '1') then
q <= (others=>'0');
elsif (tx_data_empty_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
end process;
--
-- This is the 60usec timer counter
--
timer60usec: process(clk, enable_timer_60usec, timer_60usec_count)
begin
if clk'event and clk = '0' then
if (enable_timer_60usec = '0') then
timer_60usec_count <= (others => '0');
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;
if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
end process;
--
-- This is the 5usec timer counter
--
timer5usec : process(clk, enable_timer_5usec, timer_5usec_count )
begin
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= (others => '0');
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
end process;
--
-- Create the signals which indicate special scan codes received.
-- These are the "unlatched versions."
--
extend_release_decode : process( q, rx_shifting_done, extended, released )
begin
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
else
rx_output_event <= '0';
end if;
end process;
--
-- Store the special scan code status bits
-- Not the final output, but an intermediate storage place,
-- until the entire set of output data can be assembled.
--
special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended, released )
begin
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
end process;
--
-- convert scan code to ascii code
--
scan_to_ascii : process( shift_key_on, caps_key_on, q )
begin
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);
end process;
--
-- These bits contain the status of the two shift keys
--
left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and (rx_shifting_done = '1') then
left_shift_key <= not hold_released;
end if;
end if;
end process;
right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and (rx_shifting_done = '1') then
right_shift_key <= not hold_released;
end if;
end if;
end process;
shift_proc : process( left_shift_key, right_shift_key, shift_key_on, caps_key_on, q )
begin
shift_key_on <= left_shift_key or right_shift_key;
rx_shift_on <= shift_key_on;
end process;
--
-- Control keys
--
ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and (rx_shifting_done = '1') then
ctrl_key_on <= not hold_released;
end if;
end if;
end process;
--
-- Caps lock
--
caps_proc : process(clk, reset, q, rx_shifting_done, hold_released, caps_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and (rx_shifting_done = '1') then
if (hold_released = '0') then
caps_key_on <= not caps_key_on;
end if;
end if;
end if;
end process;
--
-- Output the special scan code flags, the scan code and the ascii
--
special_scan_proc : process(clk, reset, rx_output_strobe,
hold_extended, hold_released,
ascii, ctrl_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
rx_data <= (others=>'0');
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
if ctrl_key_on = '1' then
rx_data <= ascii and x"1f";
else
rx_data <= ascii;
end if;
end if;
end if;
end process;
--
-- Store the final rx output data only when all extend and release codes
-- are received and the next (actual key) scan code is also ready.
-- (the presence of rx_extended or rx_released refers to the
-- the current latest scan code received, not the previously latched flags.)
--
rx_output_proc : process( clk, reset,
rx_shifting_done, rx_output_strobe,
extended, released,
hold_extended, hold_released,
q, ascii, rx_read )
begin
if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and (rx_output_strobe = '0') and
(extended = '0') and (released = '0') and
(hold_released = '0' ) and
(ascii /= "00000000" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
end process;
--
-- This part translates the scan code into an ASCII value...
-- Only the ASCII codes which I considered important have been included.
-- if you want more, just add the appropriate case statement lines...
-- (You will need to know the keyboard scan codes you wish to assign.)
-- The entries are listed in ascending order of ASCII value.
--
--shift_map : process( shift_key_plus_code )
--begin
-- case shift_key_plus_code is
-- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"00d" => ascii <= x"09"; -- Horizontal Tab
-- when x"10d" => ascii <= x"09"; -- Horizontal Tab
-- when x"05a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"15a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"076" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"176" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"029" => ascii <= x"20"; -- Space
-- when x"129" => ascii <= x"20"; -- Space
-- when x"116" => ascii <= x"21"; -- !
-- when x"152" => ascii <= x"22"; -- "
-- when x"126" => ascii <= x"23"; -- #
-- when x"125" => ascii <= x"24"; -- $
-- when x"12e" => ascii <= x"25"; --
-- when x"13d" => ascii <= x"26"; --
-- when x"052" => ascii <= x"27"; --
-- when x"146" => ascii <= x"28"; --
-- when x"145" => ascii <= x"29"; --
-- when x"13e" => ascii <= x"2a"; -- *
-- when x"155" => ascii <= x"2b"; -- +
-- when x"041" => ascii <= x"2c"; -- ,
-- when x"04e" => ascii <= x"2d"; -- -
-- when x"049" => ascii <= x"2e"; -- .
-- when x"04a" => ascii <= x"2f"; -- /
-- when x"045" => ascii <= x"30"; -- 0
-- when x"016" => ascii <= x"31"; -- 1
-- when x"01e" => ascii <= x"32"; -- 2
-- when x"026" => ascii <= x"33"; -- 3
-- when x"025" => ascii <= x"34"; -- 4
-- when x"02e" => ascii <= x"35"; -- 5
-- when x"036" => ascii <= x"36"; -- 6
-- when x"03d" => ascii <= x"37"; -- 7
-- when x"03e" => ascii <= x"38"; -- 8
-- when x"046" => ascii <= x"39"; -- 9
-- when x"14c" => ascii <= x"3a"; -- :
-- when x"04c" => ascii <= x"3b"; -- ;
-- when x"141" => ascii <= x"3c"; -- <
-- when x"055" => ascii <= x"3d"; -- =
-- when x"149" => ascii <= x"3e"; -- >
-- when x"14a" => ascii <= x"3f"; -- ?
-- when x"11e" => ascii <= x"40"; -- @
-- when x"11c" => ascii <= x"41"; -- A
-- when x"132" => ascii <= x"42"; -- B
-- when x"121" => ascii <= x"43"; -- C
-- when x"123" => ascii <= x"44"; -- D
-- when x"124" => ascii <= x"45"; -- E
-- when x"12b" => ascii <= x"46"; -- F
-- when x"134" => ascii <= x"47"; -- G
-- when x"133" => ascii <= x"48"; -- H
-- when x"143" => ascii <= x"49"; -- I
-- when x"13b" => ascii <= x"4a"; -- J
-- when x"142" => ascii <= x"4b"; -- K
-- when x"14b" => ascii <= x"4c"; -- L
-- when x"13a" => ascii <= x"4d"; -- M
-- when x"131" => ascii <= x"4e"; -- N
-- when x"144" => ascii <= x"4f"; -- O
-- when x"14d" => ascii <= x"50"; -- P
-- when x"115" => ascii <= x"51"; -- Q
-- when x"12d" => ascii <= x"52"; -- R
-- when x"11b" => ascii <= x"53"; -- S
-- when x"12c" => ascii <= x"54"; -- T
-- when x"13c" => ascii <= x"55"; -- U
-- when x"12a" => ascii <= x"56"; -- V
-- when x"11d" => ascii <= x"57"; -- W
-- when x"122" => ascii <= x"58"; -- X
-- when x"135" => ascii <= x"59"; -- Y
-- when x"11a" => ascii <= x"5a"; -- Z
-- when x"054" => ascii <= x"5b"; -- [
-- when x"05d" => ascii <= x"5c"; -- \
-- when x"05b" => ascii <= x"5d"; -- ]
-- when x"136" => ascii <= x"5e"; -- ^
-- when x"14e" => ascii <= x"5f"; -- _
-- when x"00e" => ascii <= x"60"; -- `
-- when x"01c" => ascii <= x"61"; -- a
-- when x"032" => ascii <= x"62"; -- b
-- when x"021" => ascii <= x"63"; -- c
-- when x"023" => ascii <= x"64"; -- d
-- when x"024" => ascii <= x"65"; -- e
-- when x"02b" => ascii <= x"66"; -- f
-- when x"034" => ascii <= x"67"; -- g
-- when x"033" => ascii <= x"68"; -- h
-- when x"043" => ascii <= x"69"; -- i
-- when x"03b" => ascii <= x"6a"; -- j
-- when x"042" => ascii <= x"6b"; -- k
-- when x"04b" => ascii <= x"6c"; -- l
-- when x"03a" => ascii <= x"6d"; -- m
-- when x"031" => ascii <= x"6e"; -- n
-- when x"044" => ascii <= x"6f"; -- o
-- when x"04d" => ascii <= x"70"; -- p
-- when x"015" => ascii <= x"71"; -- q
-- when x"02d" => ascii <= x"72"; -- r
-- when x"01b" => ascii <= x"73"; -- s
-- when x"02c" => ascii <= x"74"; -- t
-- when x"03c" => ascii <= x"75"; -- u
-- when x"02a" => ascii <= x"76"; -- v
-- when x"01d" => ascii <= x"77"; -- w
-- when x"022" => ascii <= x"78"; -- x
-- when x"035" => ascii <= x"79"; -- y
-- when x"01a" => ascii <= x"7a"; -- z
-- when x"154" => ascii <= x"7b"; -- {
-- when x"15d" => ascii <= x"7c"; -- |
-- when x"15b" => ascii <= x"7d"; -- }
-- when x"10e" => ascii <= x"7e"; -- ~
-- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when others => ascii <= x"00"; -- 0xff used for unlisted characters.
-- end case;
--end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 8;
axi_slave_amount : integer := 2;
axi_master_base_address : std_logic_vector := X"44a5000044a4000044a3000044a2000044a1000044a000000100000000000000";
axi_master_high_address : std_logic_vector := X"44a5ffff44a4ffff44a3ffff44a2ffff44a1ffff44a0ffff0103ffff0000ffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
cdma_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_awlen : in std_logic_vector(7 downto 0);
cdma_s_axi_awsize : in std_logic_vector(2 downto 0);
cdma_s_axi_awburst : in std_logic_vector(1 downto 0);
cdma_s_axi_awlock : in std_logic;
cdma_s_axi_awcache : in std_logic_vector(3 downto 0);
cdma_s_axi_awprot : in std_logic_vector(2 downto 0);
cdma_s_axi_awqos : in std_logic_vector(3 downto 0);
cdma_s_axi_awregion : in std_logic_vector(3 downto 0);
cdma_s_axi_awvalid : in std_logic;
cdma_s_axi_awready : out std_logic;
cdma_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cdma_s_axi_wlast : in std_logic;
cdma_s_axi_wvalid : in std_logic;
cdma_s_axi_wready : out std_logic;
cdma_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_bresp : out std_logic_vector(1 downto 0);
cdma_s_axi_bvalid : out std_logic;
cdma_s_axi_bready : in std_logic;
cdma_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_arlen : in std_logic_vector(7 downto 0);
cdma_s_axi_arsize : in std_logic_vector(2 downto 0);
cdma_s_axi_arburst : in std_logic_vector(1 downto 0);
cdma_s_axi_arlock : in std_logic;
cdma_s_axi_arcache : in std_logic_vector(3 downto 0);
cdma_s_axi_arprot : in std_logic_vector(2 downto 0);
cdma_s_axi_arqos : in std_logic_vector(3 downto 0);
cdma_s_axi_arregion : in std_logic_vector(3 downto 0);
cdma_s_axi_arvalid : in std_logic;
cdma_s_axi_arready : out std_logic;
cdma_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_rresp : out std_logic_vector(1 downto 0);
cdma_s_axi_rlast : out std_logic;
cdma_s_axi_rvalid : out std_logic;
cdma_s_axi_rready : in std_logic;
bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_awlen : out std_logic_vector(7 downto 0);
bram_m_axi_awsize : out std_logic_vector(2 downto 0);
bram_m_axi_awburst : out std_logic_vector(1 downto 0);
bram_m_axi_awlock : out std_logic;
bram_m_axi_awcache : out std_logic_vector(3 downto 0);
bram_m_axi_awprot : out std_logic_vector(2 downto 0);
bram_m_axi_awqos : out std_logic_vector(3 downto 0);
bram_m_axi_awregion : out std_logic_vector(3 downto 0);
bram_m_axi_awvalid : out std_logic;
bram_m_axi_awready : in std_logic;
bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
bram_m_axi_wlast : out std_logic;
bram_m_axi_wvalid : out std_logic;
bram_m_axi_wready : in std_logic;
bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_bresp : in std_logic_vector(1 downto 0);
bram_m_axi_bvalid : in std_logic;
bram_m_axi_bready : out std_logic;
bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_arlen : out std_logic_vector(7 downto 0);
bram_m_axi_arsize : out std_logic_vector(2 downto 0);
bram_m_axi_arburst : out std_logic_vector(1 downto 0);
bram_m_axi_arlock : out std_logic;
bram_m_axi_arcache : out std_logic_vector(3 downto 0);
bram_m_axi_arprot : out std_logic_vector(2 downto 0);
bram_m_axi_arqos : out std_logic_vector(3 downto 0);
bram_m_axi_arregion : out std_logic_vector(3 downto 0);
bram_m_axi_arvalid : out std_logic;
bram_m_axi_arready : in std_logic;
bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_rresp : in std_logic_vector(1 downto 0);
bram_m_axi_rlast : in std_logic;
bram_m_axi_rvalid : in std_logic;
bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
cdma_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_awlen : out std_logic_vector(7 downto 0);
cdma_m_axi_awsize : out std_logic_vector(2 downto 0);
cdma_m_axi_awburst : out std_logic_vector(1 downto 0);
cdma_m_axi_awlock : out std_logic;
cdma_m_axi_awcache : out std_logic_vector(3 downto 0);
cdma_m_axi_awprot : out std_logic_vector(2 downto 0);
cdma_m_axi_awqos : out std_logic_vector(3 downto 0);
cdma_m_axi_awregion : out std_logic_vector(3 downto 0);
cdma_m_axi_awvalid : out std_logic;
cdma_m_axi_awready : in std_logic;
cdma_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cdma_m_axi_wlast : out std_logic;
cdma_m_axi_wvalid : out std_logic;
cdma_m_axi_wready : in std_logic;
cdma_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_m_axi_bvalid : in std_logic;
cdma_m_axi_bready : out std_logic;
cdma_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_arlen : out std_logic_vector(7 downto 0);
cdma_m_axi_arsize : out std_logic_vector(2 downto 0);
cdma_m_axi_arburst : out std_logic_vector(1 downto 0);
cdma_m_axi_arlock : out std_logic;
cdma_m_axi_arcache : out std_logic_vector(3 downto 0);
cdma_m_axi_arprot : out std_logic_vector(2 downto 0);
cdma_m_axi_arqos : out std_logic_vector(3 downto 0);
cdma_m_axi_arregion : out std_logic_vector(3 downto 0);
cdma_m_axi_arvalid : out std_logic;
cdma_m_axi_arready : in std_logic;
cdma_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_rresp : in std_logic_vector(1 downto 0);
cdma_m_axi_rlast : in std_logic;
cdma_m_axi_rvalid : in std_logic;
cdma_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
timer_extra_0_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_awlock : out std_logic;
timer_extra_0_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awvalid : out std_logic;
timer_extra_0_m_axi_awready : in std_logic;
timer_extra_0_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_extra_0_m_axi_wlast : out std_logic;
timer_extra_0_m_axi_wvalid : out std_logic;
timer_extra_0_m_axi_wready : in std_logic;
timer_extra_0_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_bvalid : in std_logic;
timer_extra_0_m_axi_bready : out std_logic;
timer_extra_0_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_arlock : out std_logic;
timer_extra_0_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arvalid : out std_logic;
timer_extra_0_m_axi_arready : in std_logic;
timer_extra_0_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_rlast : in std_logic;
timer_extra_0_m_axi_rvalid : in std_logic;
timer_extra_0_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_0_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 8;
axi_slave_amount : integer := 2;
axi_master_base_address : std_logic_vector := X"44a5000044a4000044a3000044a2000044a1000044a000000100000000000000";
axi_master_high_address : std_logic_vector := X"44a5ffff44a4ffff44a3ffff44a2ffff44a1ffff44a0ffff0103ffff0000ffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
cdma_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_awlen : in std_logic_vector(7 downto 0);
cdma_s_axi_awsize : in std_logic_vector(2 downto 0);
cdma_s_axi_awburst : in std_logic_vector(1 downto 0);
cdma_s_axi_awlock : in std_logic;
cdma_s_axi_awcache : in std_logic_vector(3 downto 0);
cdma_s_axi_awprot : in std_logic_vector(2 downto 0);
cdma_s_axi_awqos : in std_logic_vector(3 downto 0);
cdma_s_axi_awregion : in std_logic_vector(3 downto 0);
cdma_s_axi_awvalid : in std_logic;
cdma_s_axi_awready : out std_logic;
cdma_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cdma_s_axi_wlast : in std_logic;
cdma_s_axi_wvalid : in std_logic;
cdma_s_axi_wready : out std_logic;
cdma_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_bresp : out std_logic_vector(1 downto 0);
cdma_s_axi_bvalid : out std_logic;
cdma_s_axi_bready : in std_logic;
cdma_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_arlen : in std_logic_vector(7 downto 0);
cdma_s_axi_arsize : in std_logic_vector(2 downto 0);
cdma_s_axi_arburst : in std_logic_vector(1 downto 0);
cdma_s_axi_arlock : in std_logic;
cdma_s_axi_arcache : in std_logic_vector(3 downto 0);
cdma_s_axi_arprot : in std_logic_vector(2 downto 0);
cdma_s_axi_arqos : in std_logic_vector(3 downto 0);
cdma_s_axi_arregion : in std_logic_vector(3 downto 0);
cdma_s_axi_arvalid : in std_logic;
cdma_s_axi_arready : out std_logic;
cdma_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_rresp : out std_logic_vector(1 downto 0);
cdma_s_axi_rlast : out std_logic;
cdma_s_axi_rvalid : out std_logic;
cdma_s_axi_rready : in std_logic;
bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_awlen : out std_logic_vector(7 downto 0);
bram_m_axi_awsize : out std_logic_vector(2 downto 0);
bram_m_axi_awburst : out std_logic_vector(1 downto 0);
bram_m_axi_awlock : out std_logic;
bram_m_axi_awcache : out std_logic_vector(3 downto 0);
bram_m_axi_awprot : out std_logic_vector(2 downto 0);
bram_m_axi_awqos : out std_logic_vector(3 downto 0);
bram_m_axi_awregion : out std_logic_vector(3 downto 0);
bram_m_axi_awvalid : out std_logic;
bram_m_axi_awready : in std_logic;
bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
bram_m_axi_wlast : out std_logic;
bram_m_axi_wvalid : out std_logic;
bram_m_axi_wready : in std_logic;
bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_bresp : in std_logic_vector(1 downto 0);
bram_m_axi_bvalid : in std_logic;
bram_m_axi_bready : out std_logic;
bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_arlen : out std_logic_vector(7 downto 0);
bram_m_axi_arsize : out std_logic_vector(2 downto 0);
bram_m_axi_arburst : out std_logic_vector(1 downto 0);
bram_m_axi_arlock : out std_logic;
bram_m_axi_arcache : out std_logic_vector(3 downto 0);
bram_m_axi_arprot : out std_logic_vector(2 downto 0);
bram_m_axi_arqos : out std_logic_vector(3 downto 0);
bram_m_axi_arregion : out std_logic_vector(3 downto 0);
bram_m_axi_arvalid : out std_logic;
bram_m_axi_arready : in std_logic;
bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_rresp : in std_logic_vector(1 downto 0);
bram_m_axi_rlast : in std_logic;
bram_m_axi_rvalid : in std_logic;
bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
cdma_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_awlen : out std_logic_vector(7 downto 0);
cdma_m_axi_awsize : out std_logic_vector(2 downto 0);
cdma_m_axi_awburst : out std_logic_vector(1 downto 0);
cdma_m_axi_awlock : out std_logic;
cdma_m_axi_awcache : out std_logic_vector(3 downto 0);
cdma_m_axi_awprot : out std_logic_vector(2 downto 0);
cdma_m_axi_awqos : out std_logic_vector(3 downto 0);
cdma_m_axi_awregion : out std_logic_vector(3 downto 0);
cdma_m_axi_awvalid : out std_logic;
cdma_m_axi_awready : in std_logic;
cdma_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cdma_m_axi_wlast : out std_logic;
cdma_m_axi_wvalid : out std_logic;
cdma_m_axi_wready : in std_logic;
cdma_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_m_axi_bvalid : in std_logic;
cdma_m_axi_bready : out std_logic;
cdma_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_arlen : out std_logic_vector(7 downto 0);
cdma_m_axi_arsize : out std_logic_vector(2 downto 0);
cdma_m_axi_arburst : out std_logic_vector(1 downto 0);
cdma_m_axi_arlock : out std_logic;
cdma_m_axi_arcache : out std_logic_vector(3 downto 0);
cdma_m_axi_arprot : out std_logic_vector(2 downto 0);
cdma_m_axi_arqos : out std_logic_vector(3 downto 0);
cdma_m_axi_arregion : out std_logic_vector(3 downto 0);
cdma_m_axi_arvalid : out std_logic;
cdma_m_axi_arready : in std_logic;
cdma_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_rresp : in std_logic_vector(1 downto 0);
cdma_m_axi_rlast : in std_logic;
cdma_m_axi_rvalid : in std_logic;
cdma_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
timer_extra_0_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_awlock : out std_logic;
timer_extra_0_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awvalid : out std_logic;
timer_extra_0_m_axi_awready : in std_logic;
timer_extra_0_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_extra_0_m_axi_wlast : out std_logic;
timer_extra_0_m_axi_wvalid : out std_logic;
timer_extra_0_m_axi_wready : in std_logic;
timer_extra_0_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_bvalid : in std_logic;
timer_extra_0_m_axi_bready : out std_logic;
timer_extra_0_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_arlock : out std_logic;
timer_extra_0_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arvalid : out std_logic;
timer_extra_0_m_axi_arready : in std_logic;
timer_extra_0_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_rlast : in std_logic;
timer_extra_0_m_axi_rvalid : in std_logic;
timer_extra_0_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_0_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
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|
`protect begin_protected
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`protect end_protected
|
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
|
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_minimal is
generic (runner_cfg : string);
end entity;
architecture tb of tb_minimal is
begin
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("testcase_1") then
report "Hello from testcase_1";
elsif run("testcase_2") then
report "Hello from testcase_2";
end if;
end loop;
test_runner_cleanup(runner);
end process;
end architecture;
|
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_minimal is
generic (runner_cfg : string);
end entity;
architecture tb of tb_minimal is
begin
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("testcase_1") then
report "Hello from testcase_1";
elsif run("testcase_2") then
report "Hello from testcase_2";
end if;
end loop;
test_runner_cleanup(runner);
end process;
end architecture;
|
-- Automatically generated: write_netlist -wrapapp -vhdl -module reconflogic-wrapmax6682mean.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MyReconfigLogic is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end MyReconfigLogic;
architecture WrapMAX6682Mean of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgMode_o : out std_logic;
CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgDataOut_o : out std_logic;
CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0)
);
end component;
component MAX6682Mean
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PauseCounterPreset_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component ParamIntf
generic (
WrAddrWidth : integer range 1 to 15 := 4;
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end component;
component ParamOutReg
generic (
Width : integer := 16
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
ParamWrData_i : in std_logic_vector(Width-1 downto 0);
Param_o : out std_logic_vector(Width-1 downto 0)
);
end component;
signal PauseCounterPreset_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetH_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_s : std_logic_vector(15 downto 0);
signal SensorValue_s : std_logic_vector(15 downto 0);
signal Threshold_s : std_logic_vector(15 downto 0);
signal CfgClk_s : std_logic_vector(0 downto 0);
signal CfgMode_s : std_logic;
signal CfgShift_s : std_logic_vector(0 downto 0);
signal CfgDataOut_s : std_logic;
signal CfgDataIn_s : std_logic_vector(0 downto 0);
signal ParamWrAddr_s : std_logic_vector(2 downto 0);
signal ParamWrData_s : std_logic_vector(15 downto 0);
signal ParamWr_s : std_logic;
signal ParamRdAddr_s : std_logic_vector(0 downto 0);
signal ParamRdData_s : std_logic_vector(15 downto 0);
type Params_t is array(0 to 1) of std_logic_vector(15 downto 0);
signal Params_s : Params_t;
signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0);
signal ParamI2C_Divider800Enable_s : std_logic;
signal ParamI2C_ErrAckParamEnable_s : std_logic;
signal ParamPauseCounterPresetEnable_s : std_logic;
signal ParamPeriodCounterPresetHEnable_s : std_logic;
signal ParamPeriodCounterPresetLEnable_s : std_logic;
signal ParamThresholdEnable_s : std_logic;
begin
-- Configuration Interface
CfgIntf_0: CfgIntf
generic map (
BaseAddr => 16#0180#,
NumCfgs => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => CfgIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
CfgClk_o => CfgClk_s,
CfgMode_o => CfgMode_s,
CfgShift_o => CfgShift_s,
CfgDataOut_o => CfgDataOut_s,
CfgDataIn_i => CfgDataIn_s
);
-- Parameterization Interface: 6 write addresses, 2 read addresses
ParamIntf_0: ParamIntf
generic map (
BaseAddr => 16#0188#,
WrAddrWidth => 3,
RdAddrWidth => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => ParamIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
ParamWrAddr_o => ParamWrAddr_s,
ParamWrData_o => ParamWrData_s,
ParamWr_o => ParamWr_s,
ParamRdAddr_o => ParamRdAddr_s,
ParamRdData_i => ParamRdData_s
);
MAX6682Mean_0: MAX6682Mean
port map (
MAX6682CS_n_o => Outputs_o(0),
CpuIntr_o => ReconfModuleIRQs_o(0),
SPI_Data_o => SPI_DataIn_o,
SPI_Data_i => SPI_DataOut_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Transmission_i => SPI_Transmission_i,
SPI_Write_o => SPI_Write_o,
Enable_i => ReconfModuleIn_i(0),
Clk_i => Clk_i,
Reset_n_i => Reset_n_i,
PauseCounterPreset_i => PauseCounterPreset_s,
PeriodCounterPresetH_i => PeriodCounterPresetH_s,
PeriodCounterPresetL_i => PeriodCounterPresetL_s,
SensorValue_o => SensorValue_s,
Threshold_i => Threshold_s
);
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReadCount_o <= "0000";
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
Outputs_o(1) <= '0';
Outputs_o(2) <= '0';
Outputs_o(3) <= '0';
Outputs_o(4) <= '0';
Outputs_o(5) <= '0';
Outputs_o(6) <= '0';
Outputs_o(7) <= '0';
ReconfModuleIRQs_o(1) <= '0';
ReconfModuleIRQs_o(2) <= '0';
ReconfModuleIRQs_o(3) <= '0';
ReconfModuleIRQs_o(4) <= '0';
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_LSBFE_o <= '0';
SPI_SPPR_SPR_o <= "00000000";
ReconfModuleOut_o(0) <= '0';
ReconfModuleOut_o(1) <= '0';
ReconfModuleOut_o(2) <= '0';
ReconfModuleOut_o(3) <= '0';
ReconfModuleOut_o(4) <= '0';
ReconfModuleOut_o(5) <= '0';
ReconfModuleOut_o(6) <= '0';
ReconfModuleOut_o(7) <= '0';
-- just a fixed value for the config interface
CfgDataIn_s <= "0";
-- Param read address decoder
-- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
-- hope that the synthesis optimizes the MUX
-- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
-- 0 to n.", even during param write cycles, because ParamRdAddr has the
-- source as ParamWrAddr. Use the parameter "-noindexcheck" during
-- compilation ("vcom"). Simulation works fine then, but ModelSim generates
-- numerous "INTERNAL ERROR"s to stdout, which seem harmless.
ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s)));
ParamOutReg_I2C_Divider800: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_Divider800_o,
Enable_i => ParamI2C_Divider800Enable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_I2C_ErrAckParam: ParamOutReg
generic map (
Width => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_ErrAckParam_s,
Enable_i => ParamI2C_ErrAckParamEnable_s,
ParamWrData_i => ParamWrData_s(0 downto 0)
);
ParamOutReg_PauseCounterPreset: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PauseCounterPreset_s,
Enable_i => ParamPauseCounterPresetEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetH_s,
Enable_i => ParamPeriodCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetL_s,
Enable_i => ParamPeriodCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_Threshold: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => Threshold_s,
Enable_i => ParamThresholdEnable_s,
ParamWrData_i => ParamWrData_s
);
I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0);
-- Address $00
Params_s(0) <= "00000000" & I2C_Errors_i;
-- Address $01
Params_s(1) <= SensorValue_s;
-- Address $00
ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else
'0';
-- Address $01
ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else
'0';
-- Address $02
ParamPauseCounterPresetEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else
'0';
-- Address $03
ParamPeriodCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else
'0';
-- Address $04
ParamPeriodCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else
'0';
-- Address $05
ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "101" else
'0';
end WrapMAX6682Mean;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tri_intersect is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TID : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
outs_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of tri_intersect is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"tri_intersect,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=121,HLS_SYN_TPT=none,HLS_SYN_MEM=32,HLS_SYN_DSP=127,HLS_SYN_FF=16912,HLS_SYN_LUT=22657}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (37 downto 0) := "00000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (37 downto 0) := "00000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (37 downto 0) := "00000000100000000000000000000000000000";
constant ap_ST_pp0_stg0_fsm_30 : STD_LOGIC_VECTOR (37 downto 0) := "00000001000000000000000000000000000000";
constant ap_ST_st115_fsm_31 : STD_LOGIC_VECTOR (37 downto 0) := "00000010000000000000000000000000000000";
constant ap_ST_st116_fsm_32 : STD_LOGIC_VECTOR (37 downto 0) := "00000100000000000000000000000000000000";
constant ap_ST_st117_fsm_33 : STD_LOGIC_VECTOR (37 downto 0) := "00001000000000000000000000000000000000";
constant ap_ST_st118_fsm_34 : STD_LOGIC_VECTOR (37 downto 0) := "00010000000000000000000000000000000000";
constant ap_ST_st119_fsm_35 : STD_LOGIC_VECTOR (37 downto 0) := "00100000000000000000000000000000000000";
constant ap_ST_st120_fsm_36 : STD_LOGIC_VECTOR (37 downto 0) := "01000000000000000000000000000000000000";
constant ap_ST_st121_fsm_37 : STD_LOGIC_VECTOR (37 downto 0) := "10000000000000000000000000000000000000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_3F800000 : STD_LOGIC_VECTOR (31 downto 0) := "00111111100000000000000000000000";
constant ap_const_lv32_1E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111100000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv32_200 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000000000";
constant ap_const_lv32_21F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000011111";
constant ap_const_lv32_220 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000100000";
constant ap_const_lv32_23F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000111111";
constant ap_const_lv576_lc_1 : STD_LOGIC_VECTOR (575 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal i1_reg_238 : STD_LOGIC_VECTOR (1 downto 0);
signal reg_489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_75 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_86 : BOOLEAN;
signal reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_96 : BOOLEAN;
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_104 : BOOLEAN;
signal reg_497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_122 : BOOLEAN;
signal reg_501 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_132 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_140 : BOOLEAN;
signal reg_505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_150 : BOOLEAN;
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal reg_509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_168 : BOOLEAN;
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal reg_513 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_186 : BOOLEAN;
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_194 : BOOLEAN;
signal reg_517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_212 : BOOLEAN;
signal reg_521 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_222 : BOOLEAN;
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal reg_525 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_240 : BOOLEAN;
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_248 : BOOLEAN;
signal reg_529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_258 : BOOLEAN;
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_266 : BOOLEAN;
signal reg_533 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_284 : BOOLEAN;
signal reg_537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_302 : BOOLEAN;
signal reg_541 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_312 : BOOLEAN;
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_320 : BOOLEAN;
signal reg_545 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st116_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_331 : BOOLEAN;
signal ap_sig_ioackin_outs_TREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st119_fsm_35 : STD_LOGIC;
signal ap_sig_bdd_342 : BOOLEAN;
signal reg_549 : STD_LOGIC_VECTOR (31 downto 0);
signal data_array_addr_gep_fu_208_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_addr_reg_1095 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_355 : BOOLEAN;
signal data_array_addr_1_gep_fu_220_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_addr_1_reg_1100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_365 : BOOLEAN;
signal ins_keep_V_val_reg_1105 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_strb_V_val_reg_1110 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_user_V_val_reg_1115 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_last_V_val_reg_1120 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_id_V_val_reg_1125 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_dest_V_val_reg_1130 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_1135 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_387 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it36 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it37 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it38 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it39 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it40 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it41 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it42 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it43 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it44 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it45 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it46 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it47 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it48 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it49 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it50 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it51 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it52 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it53 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it54 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it55 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it56 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it57 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it58 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it59 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it60 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it61 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it62 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it63 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it64 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it65 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it66 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it67 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it68 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it69 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it70 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it71 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it72 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it73 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it74 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it75 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it76 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it77 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it78 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it79 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it80 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it81 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it82 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it83 : STD_LOGIC := '0';
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_797_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal data_array_addr_2_reg_1144 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_q0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_load_2_reg_1150 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_3_fu_808_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_reg_1155 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_new_reg_1160 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_new_reg_1165 : STD_LOGIC_VECTOR (31 downto 0);
signal v1x_assign_new_reg_1170 : STD_LOGIC_VECTOR (31 downto 0);
signal v1y_assign_new_reg_1175 : STD_LOGIC_VECTOR (31 downto 0);
signal v1z_assign_new_reg_1180 : STD_LOGIC_VECTOR (31 downto 0);
signal v2x_assign_new_reg_1185 : STD_LOGIC_VECTOR (31 downto 0);
signal v2y_assign_new_reg_1190 : STD_LOGIC_VECTOR (31 downto 0);
signal v2z_assign_new_reg_1195 : STD_LOGIC_VECTOR (31 downto 0);
signal rdx_assign_new_reg_1200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdy_assign_new_reg_1205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdz_assign_new_reg_1210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rex_assign_new_reg_1215 : STD_LOGIC_VECTOR (31 downto 0);
signal rey_assign_new_reg_1220 : STD_LOGIC_VECTOR (31 downto 0);
signal rez_assign_new_reg_1225 : STD_LOGIC_VECTOR (31 downto 0);
signal v0x_assign4_fu_952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_fu_958_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_fu_964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal a_reg_1296 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal b_reg_1303 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_reg_1310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal d_reg_1317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal e_reg_1324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal f_reg_1331 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_reg_1338 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_1345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal l_reg_1352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal g_fu_1006_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal g_reg_1359 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal h_fu_1010_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal h_reg_1366 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_fu_1014_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_1373 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_reg_1380 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_41_reg_1385 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_i_reg_1390 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_i_reg_1395 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_i_reg_1400 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_i_reg_1405 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_i_reg_1410 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_i_reg_1415 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_reg_1420 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_i_reg_1426 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_i_reg_1432 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_i_reg_1437 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_i_reg_1442 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_i_reg_1448 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_i_reg_1454 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_i_reg_1459 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_reg_1464 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_i_reg_1469 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_i_reg_1474 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_reg_1479 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_i_reg_1484 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_i_reg_1489 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_i_reg_1494 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_i_reg_1499 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_i_reg_1504 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_i_reg_1510 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_i_reg_1516 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_i_reg_1521 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_i_reg_1526 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_i_reg_1531 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_i_reg_1536 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_i_reg_1541 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_i_reg_1546 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_i_reg_1551 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal m_reg_1556 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_i_reg_1561 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_i_reg_1566 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_i_reg_1571 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal im_reg_1576 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_fu_1022_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_reg_1583 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_addr_1174175_part_set_fu_1054_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal beta_addr_1174175_part_set_reg_1593 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address0 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_ce0 : STD_LOGIC;
signal data_array_we0 : STD_LOGIC;
signal data_array_d0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address1 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_ce1 : STD_LOGIC;
signal data_array_we1 : STD_LOGIC;
signal data_array_d1 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_q1 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_s_fu_803_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal t_load_fu_1065_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_fu_1070_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st117_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_1866 : BOOLEAN;
signal beta_load_fu_1075_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st118_fsm_34 : STD_LOGIC;
signal ap_sig_bdd_1874 : BOOLEAN;
signal t_load_s_fu_1080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_s_fu_1085_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st120_fsm_36 : STD_LOGIC;
signal ap_sig_bdd_1883 : BOOLEAN;
signal beta_load_s_fu_1090_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st121_fsm_37 : STD_LOGIC;
signal ap_sig_bdd_1891 : BOOLEAN;
signal ap_reg_ioackin_outs_TREADY : STD_LOGIC := '0';
signal rez_addr149150_part_set_fu_647_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_1146147_part_set_fu_778_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st115_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_1948 : BOOLEAN;
signal grp_fu_250_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_14_toint_fu_609_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_13_toint_fu_605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_12_toint_fu_601_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_11_toint_fu_597_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_10_toint_fu_593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_9_toint_fu_589_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_8_toint_fu_585_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_7_toint_fu_581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_6_toint_fu_577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_5_toint_fu_573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_4_toint_fu_569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_3_toint_fu_565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_2_toint_fu_561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_1_toint_fu_557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_toint_fu_553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_613_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_29_toint_fu_740_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_28_toint_fu_712_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_27_toint_fu_708_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_26_toint_fu_704_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_25_toint_fu_700_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_24_toint_fu_696_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_23_toint_fu_692_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_22_toint_fu_688_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_21_toint_fu_684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_20_toint_fu_680_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_19_toint_fu_676_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_18_toint_fu_672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_17_toint_fu_668_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_16_toint_fu_664_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_15_toint_fu_660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_744_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal tmp_61_to_int_i_fu_1019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_write_assign_toint_fu_1040_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_write_assign_toint_fu_1036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal t_write_assign_toint_fu_1032_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_1044_p4 : STD_LOGIC_VECTOR (95 downto 0);
signal grp_fu_459_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_ce : STD_LOGIC;
signal grp_fu_254_ce : STD_LOGIC;
signal grp_fu_258_ce : STD_LOGIC;
signal grp_fu_262_ce : STD_LOGIC;
signal grp_fu_266_ce : STD_LOGIC;
signal grp_fu_270_ce : STD_LOGIC;
signal grp_fu_274_ce : STD_LOGIC;
signal grp_fu_278_ce : STD_LOGIC;
signal grp_fu_282_ce : STD_LOGIC;
signal grp_fu_286_ce : STD_LOGIC;
signal grp_fu_290_ce : STD_LOGIC;
signal grp_fu_294_ce : STD_LOGIC;
signal grp_fu_298_ce : STD_LOGIC;
signal grp_fu_302_ce : STD_LOGIC;
signal grp_fu_306_ce : STD_LOGIC;
signal grp_fu_310_ce : STD_LOGIC;
signal grp_fu_314_ce : STD_LOGIC;
signal grp_fu_318_ce : STD_LOGIC;
signal grp_fu_322_ce : STD_LOGIC;
signal grp_fu_326_ce : STD_LOGIC;
signal grp_fu_330_ce : STD_LOGIC;
signal grp_fu_334_ce : STD_LOGIC;
signal grp_fu_338_ce : STD_LOGIC;
signal grp_fu_342_ce : STD_LOGIC;
signal grp_fu_346_ce : STD_LOGIC;
signal grp_fu_350_ce : STD_LOGIC;
signal grp_fu_354_ce : STD_LOGIC;
signal grp_fu_358_ce : STD_LOGIC;
signal grp_fu_362_ce : STD_LOGIC;
signal grp_fu_366_ce : STD_LOGIC;
signal grp_fu_370_ce : STD_LOGIC;
signal grp_fu_374_ce : STD_LOGIC;
signal grp_fu_378_ce : STD_LOGIC;
signal grp_fu_382_ce : STD_LOGIC;
signal grp_fu_386_ce : STD_LOGIC;
signal grp_fu_390_ce : STD_LOGIC;
signal grp_fu_394_ce : STD_LOGIC;
signal grp_fu_398_ce : STD_LOGIC;
signal grp_fu_402_ce : STD_LOGIC;
signal grp_fu_406_ce : STD_LOGIC;
signal grp_fu_410_ce : STD_LOGIC;
signal grp_fu_414_ce : STD_LOGIC;
signal grp_fu_418_ce : STD_LOGIC;
signal grp_fu_422_ce : STD_LOGIC;
signal grp_fu_426_ce : STD_LOGIC;
signal grp_fu_430_ce : STD_LOGIC;
signal grp_fu_434_ce : STD_LOGIC;
signal grp_fu_438_ce : STD_LOGIC;
signal grp_fu_442_ce : STD_LOGIC;
signal grp_fu_446_ce : STD_LOGIC;
signal grp_fu_450_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (37 downto 0);
component tri_intersect_fsub_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fadd_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fmul_32ns_32ns_32_5_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fdiv_32ns_32ns_32_30 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_data_array IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (0 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (575 downto 0);
q0 : OUT STD_LOGIC_VECTOR (575 downto 0);
address1 : IN STD_LOGIC_VECTOR (0 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (575 downto 0);
q1 : OUT STD_LOGIC_VECTOR (575 downto 0) );
end component;
begin
data_array_U : component tri_intersect_data_array
generic map (
DataWidth => 576,
AddressRange => 2,
AddressWidth => 1)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => data_array_address0,
ce0 => data_array_ce0,
we0 => data_array_we0,
d0 => data_array_d0,
q0 => data_array_q0,
address1 => data_array_address1,
ce1 => data_array_ce1,
we1 => data_array_we1,
d1 => data_array_d1,
q1 => data_array_q1);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U0 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_250_p0,
din1 => grp_fu_250_p1,
ce => grp_fu_250_ce,
dout => grp_fu_250_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U1 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_254_p0,
din1 => grp_fu_254_p1,
ce => grp_fu_254_ce,
dout => grp_fu_254_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U2 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_258_p0,
din1 => grp_fu_258_p1,
ce => grp_fu_258_ce,
dout => grp_fu_258_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U3 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_262_p0,
din1 => grp_fu_262_p1,
ce => grp_fu_262_ce,
dout => grp_fu_262_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U4 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_266_p0,
din1 => grp_fu_266_p1,
ce => grp_fu_266_ce,
dout => grp_fu_266_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U5 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_270_p0,
din1 => grp_fu_270_p1,
ce => grp_fu_270_ce,
dout => grp_fu_270_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U6 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_274_p0,
din1 => grp_fu_274_p1,
ce => grp_fu_274_ce,
dout => grp_fu_274_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U7 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_278_p0,
din1 => grp_fu_278_p1,
ce => grp_fu_278_ce,
dout => grp_fu_278_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U8 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_282_p0,
din1 => grp_fu_282_p1,
ce => grp_fu_282_ce,
dout => grp_fu_282_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U9 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_286_p0,
din1 => grp_fu_286_p1,
ce => grp_fu_286_ce,
dout => grp_fu_286_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U10 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_290_p0,
din1 => grp_fu_290_p1,
ce => grp_fu_290_ce,
dout => grp_fu_290_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U11 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_294_p0,
din1 => grp_fu_294_p1,
ce => grp_fu_294_ce,
dout => grp_fu_294_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U12 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_298_p0,
din1 => grp_fu_298_p1,
ce => grp_fu_298_ce,
dout => grp_fu_298_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U13 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_302_p0,
din1 => grp_fu_302_p1,
ce => grp_fu_302_ce,
dout => grp_fu_302_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U14 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_306_p0,
din1 => grp_fu_306_p1,
ce => grp_fu_306_ce,
dout => grp_fu_306_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U15 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_310_p0,
din1 => grp_fu_310_p1,
ce => grp_fu_310_ce,
dout => grp_fu_310_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U16 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_314_p0,
din1 => grp_fu_314_p1,
ce => grp_fu_314_ce,
dout => grp_fu_314_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U17 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_318_p0,
din1 => grp_fu_318_p1,
ce => grp_fu_318_ce,
dout => grp_fu_318_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U18 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_322_p0,
din1 => grp_fu_322_p1,
ce => grp_fu_322_ce,
dout => grp_fu_322_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U19 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_326_p0,
din1 => grp_fu_326_p1,
ce => grp_fu_326_ce,
dout => grp_fu_326_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U20 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_330_p0,
din1 => grp_fu_330_p1,
ce => grp_fu_330_ce,
dout => grp_fu_330_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U21 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_334_p0,
din1 => grp_fu_334_p1,
ce => grp_fu_334_ce,
dout => grp_fu_334_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U22 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_338_p0,
din1 => grp_fu_338_p1,
ce => grp_fu_338_ce,
dout => grp_fu_338_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U23 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_342_p0,
din1 => grp_fu_342_p1,
ce => grp_fu_342_ce,
dout => grp_fu_342_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U24 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_346_p0,
din1 => grp_fu_346_p1,
ce => grp_fu_346_ce,
dout => grp_fu_346_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U25 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_350_p0,
din1 => grp_fu_350_p1,
ce => grp_fu_350_ce,
dout => grp_fu_350_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U26 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_354_p0,
din1 => grp_fu_354_p1,
ce => grp_fu_354_ce,
dout => grp_fu_354_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U27 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_358_p0,
din1 => grp_fu_358_p1,
ce => grp_fu_358_ce,
dout => grp_fu_358_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U28 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_362_p0,
din1 => grp_fu_362_p1,
ce => grp_fu_362_ce,
dout => grp_fu_362_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U29 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_366_p0,
din1 => grp_fu_366_p1,
ce => grp_fu_366_ce,
dout => grp_fu_366_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U30 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_370_p0,
din1 => grp_fu_370_p1,
ce => grp_fu_370_ce,
dout => grp_fu_370_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U31 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_374_p0,
din1 => grp_fu_374_p1,
ce => grp_fu_374_ce,
dout => grp_fu_374_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U32 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_378_p0,
din1 => grp_fu_378_p1,
ce => grp_fu_378_ce,
dout => grp_fu_378_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U33 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_382_p0,
din1 => grp_fu_382_p1,
ce => grp_fu_382_ce,
dout => grp_fu_382_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U34 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_386_p0,
din1 => grp_fu_386_p1,
ce => grp_fu_386_ce,
dout => grp_fu_386_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U35 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_390_p0,
din1 => grp_fu_390_p1,
ce => grp_fu_390_ce,
dout => grp_fu_390_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U36 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_394_p0,
din1 => grp_fu_394_p1,
ce => grp_fu_394_ce,
dout => grp_fu_394_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U37 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_398_p0,
din1 => grp_fu_398_p1,
ce => grp_fu_398_ce,
dout => grp_fu_398_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U38 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_402_p0,
din1 => grp_fu_402_p1,
ce => grp_fu_402_ce,
dout => grp_fu_402_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U39 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_406_p0,
din1 => grp_fu_406_p1,
ce => grp_fu_406_ce,
dout => grp_fu_406_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U40 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_410_p0,
din1 => grp_fu_410_p1,
ce => grp_fu_410_ce,
dout => grp_fu_410_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U41 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_414_p0,
din1 => grp_fu_414_p1,
ce => grp_fu_414_ce,
dout => grp_fu_414_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U42 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_418_p0,
din1 => grp_fu_418_p1,
ce => grp_fu_418_ce,
dout => grp_fu_418_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U43 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_422_p0,
din1 => grp_fu_422_p1,
ce => grp_fu_422_ce,
dout => grp_fu_422_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U44 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_426_p0,
din1 => grp_fu_426_p1,
ce => grp_fu_426_ce,
dout => grp_fu_426_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U45 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_430_p0,
din1 => grp_fu_430_p1,
ce => grp_fu_430_ce,
dout => grp_fu_430_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U46 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_434_p0,
din1 => grp_fu_434_p1,
ce => grp_fu_434_ce,
dout => grp_fu_434_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U47 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_438_p0,
din1 => grp_fu_438_p1,
ce => grp_fu_438_ce,
dout => grp_fu_438_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U48 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_442_p0,
din1 => grp_fu_442_p1,
ce => grp_fu_442_ce,
dout => grp_fu_442_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U49 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_446_p0,
din1 => grp_fu_446_p1,
ce => grp_fu_446_ce,
dout => grp_fu_446_p2);
tri_intersect_fdiv_32ns_32ns_32_30_U50 : component tri_intersect_fdiv_32ns_32ns_32_30
generic map (
ID => 1,
NUM_STAGE => 30,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_450_p0,
din1 => grp_fu_450_p1,
ce => grp_fu_450_ce,
dout => grp_fu_450_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_outs_TREADY assign process. --
ap_reg_ioackin_outs_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37) and (ap_const_logic_1 = outs_TREADY)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and not((exitcond2_fu_791_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it36 assign process. --
ap_reg_ppiten_pp0_it36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it37 assign process. --
ap_reg_ppiten_pp0_it37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it38 assign process. --
ap_reg_ppiten_pp0_it38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it39 assign process. --
ap_reg_ppiten_pp0_it39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it40 assign process. --
ap_reg_ppiten_pp0_it40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it41 assign process. --
ap_reg_ppiten_pp0_it41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it42 assign process. --
ap_reg_ppiten_pp0_it42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it43 assign process. --
ap_reg_ppiten_pp0_it43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it44 assign process. --
ap_reg_ppiten_pp0_it44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it45 assign process. --
ap_reg_ppiten_pp0_it45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it46 assign process. --
ap_reg_ppiten_pp0_it46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it47 assign process. --
ap_reg_ppiten_pp0_it47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it48 assign process. --
ap_reg_ppiten_pp0_it48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it49 assign process. --
ap_reg_ppiten_pp0_it49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it50 assign process. --
ap_reg_ppiten_pp0_it50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it51 assign process. --
ap_reg_ppiten_pp0_it51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it52 assign process. --
ap_reg_ppiten_pp0_it52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it53 assign process. --
ap_reg_ppiten_pp0_it53_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it54 assign process. --
ap_reg_ppiten_pp0_it54_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it55 assign process. --
ap_reg_ppiten_pp0_it55_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it56 assign process. --
ap_reg_ppiten_pp0_it56_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it57 assign process. --
ap_reg_ppiten_pp0_it57_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it58 assign process. --
ap_reg_ppiten_pp0_it58_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it59 assign process. --
ap_reg_ppiten_pp0_it59_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it60 assign process. --
ap_reg_ppiten_pp0_it60_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it61 assign process. --
ap_reg_ppiten_pp0_it61_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it62 assign process. --
ap_reg_ppiten_pp0_it62_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it63 assign process. --
ap_reg_ppiten_pp0_it63_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it64 assign process. --
ap_reg_ppiten_pp0_it64_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it65 assign process. --
ap_reg_ppiten_pp0_it65_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it66 assign process. --
ap_reg_ppiten_pp0_it66_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it67 assign process. --
ap_reg_ppiten_pp0_it67_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it68 assign process. --
ap_reg_ppiten_pp0_it68_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it69 assign process. --
ap_reg_ppiten_pp0_it69_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it70 assign process. --
ap_reg_ppiten_pp0_it70_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it71 assign process. --
ap_reg_ppiten_pp0_it71_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it72 assign process. --
ap_reg_ppiten_pp0_it72_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it73 assign process. --
ap_reg_ppiten_pp0_it73_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it74 assign process. --
ap_reg_ppiten_pp0_it74_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it75 assign process. --
ap_reg_ppiten_pp0_it75_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it76 assign process. --
ap_reg_ppiten_pp0_it76_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it77 assign process. --
ap_reg_ppiten_pp0_it77_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it78 assign process. --
ap_reg_ppiten_pp0_it78_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it78 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it78 <= ap_reg_ppiten_pp0_it77;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it79 assign process. --
ap_reg_ppiten_pp0_it79_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it79 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it79 <= ap_reg_ppiten_pp0_it78;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it80 assign process. --
ap_reg_ppiten_pp0_it80_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it80 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it80 <= ap_reg_ppiten_pp0_it79;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it81 assign process. --
ap_reg_ppiten_pp0_it81_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it81 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it81 <= ap_reg_ppiten_pp0_it80;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it82 assign process. --
ap_reg_ppiten_pp0_it82_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it82 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it82 <= ap_reg_ppiten_pp0_it81;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it83 assign process. --
ap_reg_ppiten_pp0_it83_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it83 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it83 <= ap_reg_ppiten_pp0_it82;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end process;
-- i1_reg_238 assign process. --
i1_reg_238_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
i1_reg_238 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
i1_reg_238 <= i_fu_797_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 = ap_const_lv1_0)) then
a_reg_1296 <= grp_fu_250_p2;
b_reg_1303 <= grp_fu_254_p2;
c_reg_1310 <= grp_fu_258_p2;
d_reg_1317 <= grp_fu_262_p2;
e_reg_1324 <= grp_fu_266_p2;
f_reg_1331 <= grp_fu_270_p2;
j_reg_1338 <= grp_fu_274_p2;
k_reg_1345 <= grp_fu_278_p2;
l_reg_1352 <= grp_fu_282_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_true = ap_true)) then
ap_reg_ppstg_a_reg_1296_pp0_it11 <= a_reg_1296;
ap_reg_ppstg_a_reg_1296_pp0_it12 <= ap_reg_ppstg_a_reg_1296_pp0_it11;
ap_reg_ppstg_a_reg_1296_pp0_it13 <= ap_reg_ppstg_a_reg_1296_pp0_it12;
ap_reg_ppstg_a_reg_1296_pp0_it14 <= ap_reg_ppstg_a_reg_1296_pp0_it13;
ap_reg_ppstg_a_reg_1296_pp0_it15 <= ap_reg_ppstg_a_reg_1296_pp0_it14;
ap_reg_ppstg_a_reg_1296_pp0_it16 <= ap_reg_ppstg_a_reg_1296_pp0_it15;
ap_reg_ppstg_a_reg_1296_pp0_it17 <= ap_reg_ppstg_a_reg_1296_pp0_it16;
ap_reg_ppstg_a_reg_1296_pp0_it18 <= ap_reg_ppstg_a_reg_1296_pp0_it17;
ap_reg_ppstg_a_reg_1296_pp0_it19 <= ap_reg_ppstg_a_reg_1296_pp0_it18;
ap_reg_ppstg_a_reg_1296_pp0_it20 <= ap_reg_ppstg_a_reg_1296_pp0_it19;
ap_reg_ppstg_a_reg_1296_pp0_it21 <= ap_reg_ppstg_a_reg_1296_pp0_it20;
ap_reg_ppstg_a_reg_1296_pp0_it22 <= ap_reg_ppstg_a_reg_1296_pp0_it21;
ap_reg_ppstg_a_reg_1296_pp0_it23 <= ap_reg_ppstg_a_reg_1296_pp0_it22;
ap_reg_ppstg_a_reg_1296_pp0_it24 <= ap_reg_ppstg_a_reg_1296_pp0_it23;
ap_reg_ppstg_b_reg_1303_pp0_it11 <= b_reg_1303;
ap_reg_ppstg_b_reg_1303_pp0_it12 <= ap_reg_ppstg_b_reg_1303_pp0_it11;
ap_reg_ppstg_b_reg_1303_pp0_it13 <= ap_reg_ppstg_b_reg_1303_pp0_it12;
ap_reg_ppstg_b_reg_1303_pp0_it14 <= ap_reg_ppstg_b_reg_1303_pp0_it13;
ap_reg_ppstg_b_reg_1303_pp0_it15 <= ap_reg_ppstg_b_reg_1303_pp0_it14;
ap_reg_ppstg_b_reg_1303_pp0_it16 <= ap_reg_ppstg_b_reg_1303_pp0_it15;
ap_reg_ppstg_b_reg_1303_pp0_it17 <= ap_reg_ppstg_b_reg_1303_pp0_it16;
ap_reg_ppstg_b_reg_1303_pp0_it18 <= ap_reg_ppstg_b_reg_1303_pp0_it17;
ap_reg_ppstg_b_reg_1303_pp0_it19 <= ap_reg_ppstg_b_reg_1303_pp0_it18;
ap_reg_ppstg_b_reg_1303_pp0_it20 <= ap_reg_ppstg_b_reg_1303_pp0_it19;
ap_reg_ppstg_b_reg_1303_pp0_it21 <= ap_reg_ppstg_b_reg_1303_pp0_it20;
ap_reg_ppstg_b_reg_1303_pp0_it22 <= ap_reg_ppstg_b_reg_1303_pp0_it21;
ap_reg_ppstg_b_reg_1303_pp0_it23 <= ap_reg_ppstg_b_reg_1303_pp0_it22;
ap_reg_ppstg_b_reg_1303_pp0_it24 <= ap_reg_ppstg_b_reg_1303_pp0_it23;
ap_reg_ppstg_c_reg_1310_pp0_it11 <= c_reg_1310;
ap_reg_ppstg_c_reg_1310_pp0_it12 <= ap_reg_ppstg_c_reg_1310_pp0_it11;
ap_reg_ppstg_c_reg_1310_pp0_it13 <= ap_reg_ppstg_c_reg_1310_pp0_it12;
ap_reg_ppstg_c_reg_1310_pp0_it14 <= ap_reg_ppstg_c_reg_1310_pp0_it13;
ap_reg_ppstg_c_reg_1310_pp0_it15 <= ap_reg_ppstg_c_reg_1310_pp0_it14;
ap_reg_ppstg_c_reg_1310_pp0_it16 <= ap_reg_ppstg_c_reg_1310_pp0_it15;
ap_reg_ppstg_c_reg_1310_pp0_it17 <= ap_reg_ppstg_c_reg_1310_pp0_it16;
ap_reg_ppstg_c_reg_1310_pp0_it18 <= ap_reg_ppstg_c_reg_1310_pp0_it17;
ap_reg_ppstg_c_reg_1310_pp0_it19 <= ap_reg_ppstg_c_reg_1310_pp0_it18;
ap_reg_ppstg_c_reg_1310_pp0_it20 <= ap_reg_ppstg_c_reg_1310_pp0_it19;
ap_reg_ppstg_c_reg_1310_pp0_it21 <= ap_reg_ppstg_c_reg_1310_pp0_it20;
ap_reg_ppstg_c_reg_1310_pp0_it22 <= ap_reg_ppstg_c_reg_1310_pp0_it21;
ap_reg_ppstg_c_reg_1310_pp0_it23 <= ap_reg_ppstg_c_reg_1310_pp0_it22;
ap_reg_ppstg_c_reg_1310_pp0_it24 <= ap_reg_ppstg_c_reg_1310_pp0_it23;
ap_reg_ppstg_c_reg_1310_pp0_it25 <= ap_reg_ppstg_c_reg_1310_pp0_it24;
ap_reg_ppstg_c_reg_1310_pp0_it26 <= ap_reg_ppstg_c_reg_1310_pp0_it25;
ap_reg_ppstg_c_reg_1310_pp0_it27 <= ap_reg_ppstg_c_reg_1310_pp0_it26;
ap_reg_ppstg_c_reg_1310_pp0_it28 <= ap_reg_ppstg_c_reg_1310_pp0_it27;
ap_reg_ppstg_c_reg_1310_pp0_it29 <= ap_reg_ppstg_c_reg_1310_pp0_it28;
ap_reg_ppstg_c_reg_1310_pp0_it30 <= ap_reg_ppstg_c_reg_1310_pp0_it29;
ap_reg_ppstg_c_reg_1310_pp0_it31 <= ap_reg_ppstg_c_reg_1310_pp0_it30;
ap_reg_ppstg_c_reg_1310_pp0_it32 <= ap_reg_ppstg_c_reg_1310_pp0_it31;
ap_reg_ppstg_c_reg_1310_pp0_it33 <= ap_reg_ppstg_c_reg_1310_pp0_it32;
ap_reg_ppstg_d_reg_1317_pp0_it11 <= d_reg_1317;
ap_reg_ppstg_d_reg_1317_pp0_it12 <= ap_reg_ppstg_d_reg_1317_pp0_it11;
ap_reg_ppstg_d_reg_1317_pp0_it13 <= ap_reg_ppstg_d_reg_1317_pp0_it12;
ap_reg_ppstg_d_reg_1317_pp0_it14 <= ap_reg_ppstg_d_reg_1317_pp0_it13;
ap_reg_ppstg_d_reg_1317_pp0_it15 <= ap_reg_ppstg_d_reg_1317_pp0_it14;
ap_reg_ppstg_d_reg_1317_pp0_it16 <= ap_reg_ppstg_d_reg_1317_pp0_it15;
ap_reg_ppstg_d_reg_1317_pp0_it17 <= ap_reg_ppstg_d_reg_1317_pp0_it16;
ap_reg_ppstg_d_reg_1317_pp0_it18 <= ap_reg_ppstg_d_reg_1317_pp0_it17;
ap_reg_ppstg_d_reg_1317_pp0_it19 <= ap_reg_ppstg_d_reg_1317_pp0_it18;
ap_reg_ppstg_d_reg_1317_pp0_it20 <= ap_reg_ppstg_d_reg_1317_pp0_it19;
ap_reg_ppstg_d_reg_1317_pp0_it21 <= ap_reg_ppstg_d_reg_1317_pp0_it20;
ap_reg_ppstg_d_reg_1317_pp0_it22 <= ap_reg_ppstg_d_reg_1317_pp0_it21;
ap_reg_ppstg_d_reg_1317_pp0_it23 <= ap_reg_ppstg_d_reg_1317_pp0_it22;
ap_reg_ppstg_d_reg_1317_pp0_it24 <= ap_reg_ppstg_d_reg_1317_pp0_it23;
ap_reg_ppstg_d_reg_1317_pp0_it25 <= ap_reg_ppstg_d_reg_1317_pp0_it24;
ap_reg_ppstg_d_reg_1317_pp0_it26 <= ap_reg_ppstg_d_reg_1317_pp0_it25;
ap_reg_ppstg_d_reg_1317_pp0_it27 <= ap_reg_ppstg_d_reg_1317_pp0_it26;
ap_reg_ppstg_d_reg_1317_pp0_it28 <= ap_reg_ppstg_d_reg_1317_pp0_it27;
ap_reg_ppstg_d_reg_1317_pp0_it29 <= ap_reg_ppstg_d_reg_1317_pp0_it28;
ap_reg_ppstg_d_reg_1317_pp0_it30 <= ap_reg_ppstg_d_reg_1317_pp0_it29;
ap_reg_ppstg_d_reg_1317_pp0_it31 <= ap_reg_ppstg_d_reg_1317_pp0_it30;
ap_reg_ppstg_d_reg_1317_pp0_it32 <= ap_reg_ppstg_d_reg_1317_pp0_it31;
ap_reg_ppstg_d_reg_1317_pp0_it33 <= ap_reg_ppstg_d_reg_1317_pp0_it32;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2 <= data_array_load_2_reg_1150;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8;
ap_reg_ppstg_e_reg_1324_pp0_it11 <= e_reg_1324;
ap_reg_ppstg_e_reg_1324_pp0_it12 <= ap_reg_ppstg_e_reg_1324_pp0_it11;
ap_reg_ppstg_e_reg_1324_pp0_it13 <= ap_reg_ppstg_e_reg_1324_pp0_it12;
ap_reg_ppstg_e_reg_1324_pp0_it14 <= ap_reg_ppstg_e_reg_1324_pp0_it13;
ap_reg_ppstg_e_reg_1324_pp0_it15 <= ap_reg_ppstg_e_reg_1324_pp0_it14;
ap_reg_ppstg_e_reg_1324_pp0_it16 <= ap_reg_ppstg_e_reg_1324_pp0_it15;
ap_reg_ppstg_e_reg_1324_pp0_it17 <= ap_reg_ppstg_e_reg_1324_pp0_it16;
ap_reg_ppstg_e_reg_1324_pp0_it18 <= ap_reg_ppstg_e_reg_1324_pp0_it17;
ap_reg_ppstg_e_reg_1324_pp0_it19 <= ap_reg_ppstg_e_reg_1324_pp0_it18;
ap_reg_ppstg_e_reg_1324_pp0_it20 <= ap_reg_ppstg_e_reg_1324_pp0_it19;
ap_reg_ppstg_e_reg_1324_pp0_it21 <= ap_reg_ppstg_e_reg_1324_pp0_it20;
ap_reg_ppstg_e_reg_1324_pp0_it22 <= ap_reg_ppstg_e_reg_1324_pp0_it21;
ap_reg_ppstg_e_reg_1324_pp0_it23 <= ap_reg_ppstg_e_reg_1324_pp0_it22;
ap_reg_ppstg_e_reg_1324_pp0_it24 <= ap_reg_ppstg_e_reg_1324_pp0_it23;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it9;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it11 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it10;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it12 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it11;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it13 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it12;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it13;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it15 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it14;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it16 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it15;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it17 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it16;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it18 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it17;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it19 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it18;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it1;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it20 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it19;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it21 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it20;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it22 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it21;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it22;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it24 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it23;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it25 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it24;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it26 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it25;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it27 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it26;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it27;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it29 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it28;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it3 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it2;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it30 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it29;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it31 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it30;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it31;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it33 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it32;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it34 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it33;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it35 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it34;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it36 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it35;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it36;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it38 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it37;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it39 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it38;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it4 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it3;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it40 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it39;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it41 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it40;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it42 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it41;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it43 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it42;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it44 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it43;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it45 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it44;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it45;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it47 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it46;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it48 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it47;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it49 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it48;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it5 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it4;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it50 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it49;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it51 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it50;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it52 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it51;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it53 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it52;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it54 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it53;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it55 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it54;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it56 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it55;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it57 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it56;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it58 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it57;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it59 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it58;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it6 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it5;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it60 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it59;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it61 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it60;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it62 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it61;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it63 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it62;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it64 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it63;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it65 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it64;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it66 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it65;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it67 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it66;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it68 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it67;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it69 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it68;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it7 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it6;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it70 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it69;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it71 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it70;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it72 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it71;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it73 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it72;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it74 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it73;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it75 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it74;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it75;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it77 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it76;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it78 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it77;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it79 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it78;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it8 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it7;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it80 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it79;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it80;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it81;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it8;
ap_reg_ppstg_f_reg_1331_pp0_it11 <= f_reg_1331;
ap_reg_ppstg_f_reg_1331_pp0_it12 <= ap_reg_ppstg_f_reg_1331_pp0_it11;
ap_reg_ppstg_f_reg_1331_pp0_it13 <= ap_reg_ppstg_f_reg_1331_pp0_it12;
ap_reg_ppstg_f_reg_1331_pp0_it14 <= ap_reg_ppstg_f_reg_1331_pp0_it13;
ap_reg_ppstg_f_reg_1331_pp0_it15 <= ap_reg_ppstg_f_reg_1331_pp0_it14;
ap_reg_ppstg_f_reg_1331_pp0_it16 <= ap_reg_ppstg_f_reg_1331_pp0_it15;
ap_reg_ppstg_f_reg_1331_pp0_it17 <= ap_reg_ppstg_f_reg_1331_pp0_it16;
ap_reg_ppstg_f_reg_1331_pp0_it18 <= ap_reg_ppstg_f_reg_1331_pp0_it17;
ap_reg_ppstg_f_reg_1331_pp0_it19 <= ap_reg_ppstg_f_reg_1331_pp0_it18;
ap_reg_ppstg_f_reg_1331_pp0_it20 <= ap_reg_ppstg_f_reg_1331_pp0_it19;
ap_reg_ppstg_f_reg_1331_pp0_it21 <= ap_reg_ppstg_f_reg_1331_pp0_it20;
ap_reg_ppstg_f_reg_1331_pp0_it22 <= ap_reg_ppstg_f_reg_1331_pp0_it21;
ap_reg_ppstg_f_reg_1331_pp0_it23 <= ap_reg_ppstg_f_reg_1331_pp0_it22;
ap_reg_ppstg_f_reg_1331_pp0_it24 <= ap_reg_ppstg_f_reg_1331_pp0_it23;
ap_reg_ppstg_g_reg_1359_pp0_it12 <= g_reg_1359;
ap_reg_ppstg_g_reg_1359_pp0_it13 <= ap_reg_ppstg_g_reg_1359_pp0_it12;
ap_reg_ppstg_g_reg_1359_pp0_it14 <= ap_reg_ppstg_g_reg_1359_pp0_it13;
ap_reg_ppstg_g_reg_1359_pp0_it15 <= ap_reg_ppstg_g_reg_1359_pp0_it14;
ap_reg_ppstg_g_reg_1359_pp0_it16 <= ap_reg_ppstg_g_reg_1359_pp0_it15;
ap_reg_ppstg_g_reg_1359_pp0_it17 <= ap_reg_ppstg_g_reg_1359_pp0_it16;
ap_reg_ppstg_g_reg_1359_pp0_it18 <= ap_reg_ppstg_g_reg_1359_pp0_it17;
ap_reg_ppstg_g_reg_1359_pp0_it19 <= ap_reg_ppstg_g_reg_1359_pp0_it18;
ap_reg_ppstg_g_reg_1359_pp0_it20 <= ap_reg_ppstg_g_reg_1359_pp0_it19;
ap_reg_ppstg_g_reg_1359_pp0_it21 <= ap_reg_ppstg_g_reg_1359_pp0_it20;
ap_reg_ppstg_g_reg_1359_pp0_it22 <= ap_reg_ppstg_g_reg_1359_pp0_it21;
ap_reg_ppstg_g_reg_1359_pp0_it23 <= ap_reg_ppstg_g_reg_1359_pp0_it22;
ap_reg_ppstg_g_reg_1359_pp0_it24 <= ap_reg_ppstg_g_reg_1359_pp0_it23;
ap_reg_ppstg_g_reg_1359_pp0_it25 <= ap_reg_ppstg_g_reg_1359_pp0_it24;
ap_reg_ppstg_g_reg_1359_pp0_it26 <= ap_reg_ppstg_g_reg_1359_pp0_it25;
ap_reg_ppstg_g_reg_1359_pp0_it27 <= ap_reg_ppstg_g_reg_1359_pp0_it26;
ap_reg_ppstg_g_reg_1359_pp0_it28 <= ap_reg_ppstg_g_reg_1359_pp0_it27;
ap_reg_ppstg_g_reg_1359_pp0_it29 <= ap_reg_ppstg_g_reg_1359_pp0_it28;
ap_reg_ppstg_g_reg_1359_pp0_it30 <= ap_reg_ppstg_g_reg_1359_pp0_it29;
ap_reg_ppstg_g_reg_1359_pp0_it31 <= ap_reg_ppstg_g_reg_1359_pp0_it30;
ap_reg_ppstg_g_reg_1359_pp0_it32 <= ap_reg_ppstg_g_reg_1359_pp0_it31;
ap_reg_ppstg_g_reg_1359_pp0_it33 <= ap_reg_ppstg_g_reg_1359_pp0_it32;
ap_reg_ppstg_h_reg_1366_pp0_it12 <= h_reg_1366;
ap_reg_ppstg_h_reg_1366_pp0_it13 <= ap_reg_ppstg_h_reg_1366_pp0_it12;
ap_reg_ppstg_h_reg_1366_pp0_it14 <= ap_reg_ppstg_h_reg_1366_pp0_it13;
ap_reg_ppstg_h_reg_1366_pp0_it15 <= ap_reg_ppstg_h_reg_1366_pp0_it14;
ap_reg_ppstg_h_reg_1366_pp0_it16 <= ap_reg_ppstg_h_reg_1366_pp0_it15;
ap_reg_ppstg_h_reg_1366_pp0_it17 <= ap_reg_ppstg_h_reg_1366_pp0_it16;
ap_reg_ppstg_h_reg_1366_pp0_it18 <= ap_reg_ppstg_h_reg_1366_pp0_it17;
ap_reg_ppstg_h_reg_1366_pp0_it19 <= ap_reg_ppstg_h_reg_1366_pp0_it18;
ap_reg_ppstg_h_reg_1366_pp0_it20 <= ap_reg_ppstg_h_reg_1366_pp0_it19;
ap_reg_ppstg_h_reg_1366_pp0_it21 <= ap_reg_ppstg_h_reg_1366_pp0_it20;
ap_reg_ppstg_h_reg_1366_pp0_it22 <= ap_reg_ppstg_h_reg_1366_pp0_it21;
ap_reg_ppstg_h_reg_1366_pp0_it23 <= ap_reg_ppstg_h_reg_1366_pp0_it22;
ap_reg_ppstg_h_reg_1366_pp0_it24 <= ap_reg_ppstg_h_reg_1366_pp0_it23;
ap_reg_ppstg_i_1_reg_1373_pp0_it12 <= i_1_reg_1373;
ap_reg_ppstg_i_1_reg_1373_pp0_it13 <= ap_reg_ppstg_i_1_reg_1373_pp0_it12;
ap_reg_ppstg_i_1_reg_1373_pp0_it14 <= ap_reg_ppstg_i_1_reg_1373_pp0_it13;
ap_reg_ppstg_i_1_reg_1373_pp0_it15 <= ap_reg_ppstg_i_1_reg_1373_pp0_it14;
ap_reg_ppstg_i_1_reg_1373_pp0_it16 <= ap_reg_ppstg_i_1_reg_1373_pp0_it15;
ap_reg_ppstg_i_1_reg_1373_pp0_it17 <= ap_reg_ppstg_i_1_reg_1373_pp0_it16;
ap_reg_ppstg_i_1_reg_1373_pp0_it18 <= ap_reg_ppstg_i_1_reg_1373_pp0_it17;
ap_reg_ppstg_i_1_reg_1373_pp0_it19 <= ap_reg_ppstg_i_1_reg_1373_pp0_it18;
ap_reg_ppstg_i_1_reg_1373_pp0_it20 <= ap_reg_ppstg_i_1_reg_1373_pp0_it19;
ap_reg_ppstg_i_1_reg_1373_pp0_it21 <= ap_reg_ppstg_i_1_reg_1373_pp0_it20;
ap_reg_ppstg_i_1_reg_1373_pp0_it22 <= ap_reg_ppstg_i_1_reg_1373_pp0_it21;
ap_reg_ppstg_i_1_reg_1373_pp0_it23 <= ap_reg_ppstg_i_1_reg_1373_pp0_it22;
ap_reg_ppstg_i_1_reg_1373_pp0_it24 <= ap_reg_ppstg_i_1_reg_1373_pp0_it23;
ap_reg_ppstg_j_reg_1338_pp0_it11 <= j_reg_1338;
ap_reg_ppstg_j_reg_1338_pp0_it12 <= ap_reg_ppstg_j_reg_1338_pp0_it11;
ap_reg_ppstg_j_reg_1338_pp0_it13 <= ap_reg_ppstg_j_reg_1338_pp0_it12;
ap_reg_ppstg_j_reg_1338_pp0_it14 <= ap_reg_ppstg_j_reg_1338_pp0_it13;
ap_reg_ppstg_j_reg_1338_pp0_it15 <= ap_reg_ppstg_j_reg_1338_pp0_it14;
ap_reg_ppstg_j_reg_1338_pp0_it16 <= ap_reg_ppstg_j_reg_1338_pp0_it15;
ap_reg_ppstg_j_reg_1338_pp0_it17 <= ap_reg_ppstg_j_reg_1338_pp0_it16;
ap_reg_ppstg_j_reg_1338_pp0_it18 <= ap_reg_ppstg_j_reg_1338_pp0_it17;
ap_reg_ppstg_j_reg_1338_pp0_it19 <= ap_reg_ppstg_j_reg_1338_pp0_it18;
ap_reg_ppstg_j_reg_1338_pp0_it20 <= ap_reg_ppstg_j_reg_1338_pp0_it19;
ap_reg_ppstg_j_reg_1338_pp0_it21 <= ap_reg_ppstg_j_reg_1338_pp0_it20;
ap_reg_ppstg_j_reg_1338_pp0_it22 <= ap_reg_ppstg_j_reg_1338_pp0_it21;
ap_reg_ppstg_j_reg_1338_pp0_it23 <= ap_reg_ppstg_j_reg_1338_pp0_it22;
ap_reg_ppstg_j_reg_1338_pp0_it24 <= ap_reg_ppstg_j_reg_1338_pp0_it23;
ap_reg_ppstg_k_reg_1345_pp0_it11 <= k_reg_1345;
ap_reg_ppstg_k_reg_1345_pp0_it12 <= ap_reg_ppstg_k_reg_1345_pp0_it11;
ap_reg_ppstg_k_reg_1345_pp0_it13 <= ap_reg_ppstg_k_reg_1345_pp0_it12;
ap_reg_ppstg_k_reg_1345_pp0_it14 <= ap_reg_ppstg_k_reg_1345_pp0_it13;
ap_reg_ppstg_k_reg_1345_pp0_it15 <= ap_reg_ppstg_k_reg_1345_pp0_it14;
ap_reg_ppstg_k_reg_1345_pp0_it16 <= ap_reg_ppstg_k_reg_1345_pp0_it15;
ap_reg_ppstg_k_reg_1345_pp0_it17 <= ap_reg_ppstg_k_reg_1345_pp0_it16;
ap_reg_ppstg_k_reg_1345_pp0_it18 <= ap_reg_ppstg_k_reg_1345_pp0_it17;
ap_reg_ppstg_k_reg_1345_pp0_it19 <= ap_reg_ppstg_k_reg_1345_pp0_it18;
ap_reg_ppstg_k_reg_1345_pp0_it20 <= ap_reg_ppstg_k_reg_1345_pp0_it19;
ap_reg_ppstg_k_reg_1345_pp0_it21 <= ap_reg_ppstg_k_reg_1345_pp0_it20;
ap_reg_ppstg_k_reg_1345_pp0_it22 <= ap_reg_ppstg_k_reg_1345_pp0_it21;
ap_reg_ppstg_k_reg_1345_pp0_it23 <= ap_reg_ppstg_k_reg_1345_pp0_it22;
ap_reg_ppstg_k_reg_1345_pp0_it24 <= ap_reg_ppstg_k_reg_1345_pp0_it23;
ap_reg_ppstg_l_reg_1352_pp0_it11 <= l_reg_1352;
ap_reg_ppstg_l_reg_1352_pp0_it12 <= ap_reg_ppstg_l_reg_1352_pp0_it11;
ap_reg_ppstg_l_reg_1352_pp0_it13 <= ap_reg_ppstg_l_reg_1352_pp0_it12;
ap_reg_ppstg_l_reg_1352_pp0_it14 <= ap_reg_ppstg_l_reg_1352_pp0_it13;
ap_reg_ppstg_l_reg_1352_pp0_it15 <= ap_reg_ppstg_l_reg_1352_pp0_it14;
ap_reg_ppstg_l_reg_1352_pp0_it16 <= ap_reg_ppstg_l_reg_1352_pp0_it15;
ap_reg_ppstg_l_reg_1352_pp0_it17 <= ap_reg_ppstg_l_reg_1352_pp0_it16;
ap_reg_ppstg_l_reg_1352_pp0_it18 <= ap_reg_ppstg_l_reg_1352_pp0_it17;
ap_reg_ppstg_l_reg_1352_pp0_it19 <= ap_reg_ppstg_l_reg_1352_pp0_it18;
ap_reg_ppstg_l_reg_1352_pp0_it20 <= ap_reg_ppstg_l_reg_1352_pp0_it19;
ap_reg_ppstg_l_reg_1352_pp0_it21 <= ap_reg_ppstg_l_reg_1352_pp0_it20;
ap_reg_ppstg_l_reg_1352_pp0_it22 <= ap_reg_ppstg_l_reg_1352_pp0_it21;
ap_reg_ppstg_l_reg_1352_pp0_it23 <= ap_reg_ppstg_l_reg_1352_pp0_it22;
ap_reg_ppstg_l_reg_1352_pp0_it24 <= ap_reg_ppstg_l_reg_1352_pp0_it23;
ap_reg_ppstg_l_reg_1352_pp0_it25 <= ap_reg_ppstg_l_reg_1352_pp0_it24;
ap_reg_ppstg_l_reg_1352_pp0_it26 <= ap_reg_ppstg_l_reg_1352_pp0_it25;
ap_reg_ppstg_l_reg_1352_pp0_it27 <= ap_reg_ppstg_l_reg_1352_pp0_it26;
ap_reg_ppstg_l_reg_1352_pp0_it28 <= ap_reg_ppstg_l_reg_1352_pp0_it27;
ap_reg_ppstg_l_reg_1352_pp0_it29 <= ap_reg_ppstg_l_reg_1352_pp0_it28;
ap_reg_ppstg_l_reg_1352_pp0_it30 <= ap_reg_ppstg_l_reg_1352_pp0_it29;
ap_reg_ppstg_l_reg_1352_pp0_it31 <= ap_reg_ppstg_l_reg_1352_pp0_it30;
ap_reg_ppstg_l_reg_1352_pp0_it32 <= ap_reg_ppstg_l_reg_1352_pp0_it31;
ap_reg_ppstg_l_reg_1352_pp0_it33 <= ap_reg_ppstg_l_reg_1352_pp0_it32;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2 <= rdx_assign_new_reg_1200;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2 <= rdy_assign_new_reg_1205;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2 <= rdz_assign_new_reg_1210;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48 <= tmp_25_i_reg_1561;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48 <= tmp_31_i_reg_1566;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48 <= tmp_36_i_reg_1571;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30)) then
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1 <= data_array_addr_2_reg_1144;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it1 <= exitcond2_reg_1135;
exitcond2_reg_1135 <= exitcond2_fu_791_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 = ap_const_lv1_0)) then
beta_addr_1174175_part_set_reg_1593 <= beta_addr_1174175_part_set_fu_1054_p5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
data_array_addr_2_reg_1144 <= tmp_s_fu_803_p1(1 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_reg_1135 = ap_const_lv1_0))) then
data_array_load_2_reg_1150 <= data_array_q0;
rdx_assign_new_reg_1200 <= data_array_q0(319 downto 288);
rdy_assign_new_reg_1205 <= data_array_q0(351 downto 320);
rdz_assign_new_reg_1210 <= data_array_q0(383 downto 352);
rex_assign_new_reg_1215 <= data_array_q0(415 downto 384);
rey_assign_new_reg_1220 <= data_array_q0(447 downto 416);
rez_assign_new_reg_1225 <= data_array_q0(479 downto 448);
tmp_3_reg_1155 <= tmp_3_fu_808_p1;
v0y_assign_new_reg_1160 <= data_array_q0(63 downto 32);
v0z_assign_new_reg_1165 <= data_array_q0(95 downto 64);
v1x_assign_new_reg_1170 <= data_array_q0(127 downto 96);
v1y_assign_new_reg_1175 <= data_array_q0(159 downto 128);
v1z_assign_new_reg_1180 <= data_array_q0(191 downto 160);
v2x_assign_new_reg_1185 <= data_array_q0(223 downto 192);
v2y_assign_new_reg_1190 <= data_array_q0(255 downto 224);
v2z_assign_new_reg_1195 <= data_array_q0(287 downto 256);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 = ap_const_lv1_0)) then
g_reg_1359 <= g_fu_1006_p1;
h_reg_1366 <= h_fu_1010_p1;
i_1_reg_1373 <= i_1_fu_1014_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 = ap_const_lv1_0)) then
im_reg_1576 <= grp_fu_450_p2;
tmp_61_neg_i_reg_1583 <= tmp_61_neg_i_fu_1022_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ins_dest_V_val_reg_1130 <= ins_TDEST;
ins_id_V_val_reg_1125 <= ins_TID;
ins_keep_V_val_reg_1105 <= ins_TKEEP;
ins_last_V_val_reg_1120 <= ins_TLAST;
ins_strb_V_val_reg_1110 <= ins_TSTRB;
ins_user_V_val_reg_1115 <= ins_TUSER;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 = ap_const_lv1_0)) then
m_reg_1556 <= grp_fu_326_p2;
tmp_25_i_reg_1561 <= grp_fu_330_p2;
tmp_31_i_reg_1566 <= grp_fu_334_p2;
tmp_36_i_reg_1571 <= grp_fu_338_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)))) then
reg_489 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)))) then
reg_493 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)))) then
reg_497 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)))) then
reg_501 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)))) then
reg_505 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)))) then
reg_509 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)))) then
reg_513 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)))) then
reg_517 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)))) then
reg_521 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)))) then
reg_525 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)))) then
reg_529 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)))) then
reg_533 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)))) then
reg_537 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)))) then
reg_541 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)))) then
reg_545 <= data_array_q1(543 downto 512);
reg_549 <= data_array_q1(575 downto 544);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 = ap_const_lv1_0)) then
tmp_10_i_reg_1504 <= grp_fu_302_p2;
tmp_23_i_reg_1510 <= grp_fu_306_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 = ap_const_lv1_0)) then
tmp_11_i_reg_1521 <= grp_fu_422_p2;
tmp_20_i_reg_1526 <= grp_fu_314_p2;
tmp_24_i_reg_1531 <= grp_fu_426_p2;
tmp_29_i_reg_1536 <= grp_fu_318_p2;
tmp_30_i_reg_1541 <= grp_fu_430_p2;
tmp_34_i_reg_1546 <= grp_fu_322_p2;
tmp_35_i_reg_1551 <= grp_fu_434_p2;
tmp_7_i_reg_1516 <= grp_fu_310_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 = ap_const_lv1_0)) then
tmp_12_i_reg_1400 <= grp_fu_358_p2;
tmp_13_i_reg_1405 <= grp_fu_362_p2;
tmp_16_i_reg_1410 <= grp_fu_366_p2;
tmp_17_i_reg_1415 <= grp_fu_370_p2;
tmp_3_i_reg_1390 <= grp_fu_350_p2;
tmp_4_i_reg_1395 <= grp_fu_354_p2;
tmp_i_41_reg_1385 <= grp_fu_346_p2;
tmp_i_reg_1380 <= grp_fu_342_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 = ap_const_lv1_0)) then
tmp_14_i_reg_1442 <= grp_fu_294_p2;
tmp_18_i_reg_1448 <= grp_fu_298_p2;
tmp_1_i_reg_1420 <= grp_fu_286_p2;
tmp_21_i_reg_1454 <= grp_fu_382_p2;
tmp_22_i_reg_1459 <= grp_fu_386_p2;
tmp_5_i_reg_1426 <= grp_fu_290_p2;
tmp_8_i_reg_1432 <= grp_fu_374_p2;
tmp_9_i_reg_1437 <= grp_fu_378_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 = ap_const_lv1_0)) then
tmp_15_i_reg_1474 <= grp_fu_398_p2;
tmp_19_i_reg_1479 <= grp_fu_402_p2;
tmp_27_i_reg_1484 <= grp_fu_406_p2;
tmp_28_i_reg_1489 <= grp_fu_410_p2;
tmp_2_i_reg_1464 <= grp_fu_390_p2;
tmp_32_i_reg_1494 <= grp_fu_414_p2;
tmp_33_i_reg_1499 <= grp_fu_418_p2;
tmp_6_i_reg_1469 <= grp_fu_394_p2;
end if;
end if;
end process;
data_array_addr_reg_1095(0) <= '0';
data_array_addr_1_reg_1100(0) <= '1';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ins_TVALID, ap_CS_fsm, ap_sig_ioackin_outs_TREADY, exitcond2_fu_791_p2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it82, ap_reg_ppiten_pp0_it83)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st8_fsm_7 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st10_fsm_9 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
else
ap_NS_fsm <= ap_ST_st10_fsm_9;
end if;
when ap_ST_st11_fsm_10 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st12_fsm_11 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st15_fsm_14 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st16_fsm_15;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st16_fsm_15 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st16_fsm_15;
end if;
when ap_ST_st17_fsm_16 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st18_fsm_17 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st19_fsm_18;
end if;
when ap_ST_st20_fsm_19 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st22_fsm_21;
else
ap_NS_fsm <= ap_ST_st21_fsm_20;
end if;
when ap_ST_st22_fsm_21 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st24_fsm_23;
end if;
when ap_ST_st25_fsm_24 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st26_fsm_25;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st26_fsm_25 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st27_fsm_26;
else
ap_NS_fsm <= ap_ST_st26_fsm_25;
end if;
when ap_ST_st27_fsm_26 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st28_fsm_27;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st28_fsm_27 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
else
ap_NS_fsm <= ap_ST_st28_fsm_27;
end if;
when ap_ST_st29_fsm_28 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st29_fsm_28;
end if;
when ap_ST_st30_fsm_29 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_30;
else
ap_NS_fsm <= ap_ST_st30_fsm_29;
end if;
when ap_ST_pp0_stg0_fsm_30 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it82)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_30;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st115_fsm_31;
else
ap_NS_fsm <= ap_ST_st115_fsm_31;
end if;
when ap_ST_st115_fsm_31 =>
ap_NS_fsm <= ap_ST_st116_fsm_32;
when ap_ST_st116_fsm_32 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st117_fsm_33;
else
ap_NS_fsm <= ap_ST_st116_fsm_32;
end if;
when ap_ST_st117_fsm_33 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st118_fsm_34;
else
ap_NS_fsm <= ap_ST_st117_fsm_33;
end if;
when ap_ST_st118_fsm_34 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st119_fsm_35;
else
ap_NS_fsm <= ap_ST_st118_fsm_34;
end if;
when ap_ST_st119_fsm_35 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st120_fsm_36;
else
ap_NS_fsm <= ap_ST_st119_fsm_35;
end if;
when ap_ST_st120_fsm_36 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st121_fsm_37;
else
ap_NS_fsm <= ap_ST_st120_fsm_36;
end if;
when ap_ST_st121_fsm_37 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st121_fsm_37;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_104 assign process. --
ap_sig_bdd_104_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_104 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_122 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_132 assign process. --
ap_sig_bdd_132_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_132 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_140 assign process. --
ap_sig_bdd_140_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_140 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_150 assign process. --
ap_sig_bdd_150_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_150 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_168 assign process. --
ap_sig_bdd_168_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_168 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_186 assign process. --
ap_sig_bdd_186_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_186 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_1866 assign process. --
ap_sig_bdd_1866_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1866 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_1874 assign process. --
ap_sig_bdd_1874_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1874 <= (ap_const_lv1_1 = ap_CS_fsm(34 downto 34));
end process;
-- ap_sig_bdd_1883 assign process. --
ap_sig_bdd_1883_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1883 <= (ap_const_lv1_1 = ap_CS_fsm(36 downto 36));
end process;
-- ap_sig_bdd_1891 assign process. --
ap_sig_bdd_1891_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1891 <= (ap_const_lv1_1 = ap_CS_fsm(37 downto 37));
end process;
-- ap_sig_bdd_194 assign process. --
ap_sig_bdd_194_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_194 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_1948 assign process. --
ap_sig_bdd_1948_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1948 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_204 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_212 assign process. --
ap_sig_bdd_212_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_212 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_222 assign process. --
ap_sig_bdd_222_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_222 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_240 assign process. --
ap_sig_bdd_240_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_240 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_248 assign process. --
ap_sig_bdd_248_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_248 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_258 assign process. --
ap_sig_bdd_258_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_258 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_266 assign process. --
ap_sig_bdd_266_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_266 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_284 assign process. --
ap_sig_bdd_284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_284 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_302 assign process. --
ap_sig_bdd_302_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_302 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_312 assign process. --
ap_sig_bdd_312_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_312 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_320 assign process. --
ap_sig_bdd_320_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_320 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_331 assign process. --
ap_sig_bdd_331_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_331 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_342 assign process. --
ap_sig_bdd_342_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_342 <= (ap_const_lv1_1 = ap_CS_fsm(35 downto 35));
end process;
-- ap_sig_bdd_355 assign process. --
ap_sig_bdd_355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_365 assign process. --
ap_sig_bdd_365_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_365 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_387 assign process. --
ap_sig_bdd_387_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_387 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_75 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_86 assign process. --
ap_sig_bdd_86_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_86 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_96 assign process. --
ap_sig_bdd_96_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_96 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_30 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_30_assign_proc : process(ap_sig_bdd_387)
begin
if (ap_sig_bdd_387) then
ap_sig_cseq_ST_pp0_stg0_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_240)
begin
if (ap_sig_bdd_240) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_31 assign process. --
ap_sig_cseq_ST_st115_fsm_31_assign_proc : process(ap_sig_bdd_1948)
begin
if (ap_sig_bdd_1948) then
ap_sig_cseq_ST_st115_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st116_fsm_32 assign process. --
ap_sig_cseq_ST_st116_fsm_32_assign_proc : process(ap_sig_bdd_331)
begin
if (ap_sig_bdd_331) then
ap_sig_cseq_ST_st116_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_33 assign process. --
ap_sig_cseq_ST_st117_fsm_33_assign_proc : process(ap_sig_bdd_1866)
begin
if (ap_sig_bdd_1866) then
ap_sig_cseq_ST_st117_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_34 assign process. --
ap_sig_cseq_ST_st118_fsm_34_assign_proc : process(ap_sig_bdd_1874)
begin
if (ap_sig_bdd_1874) then
ap_sig_cseq_ST_st118_fsm_34 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_34 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_35 assign process. --
ap_sig_cseq_ST_st119_fsm_35_assign_proc : process(ap_sig_bdd_342)
begin
if (ap_sig_bdd_342) then
ap_sig_cseq_ST_st119_fsm_35 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_35 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_258)
begin
if (ap_sig_bdd_258) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_36 assign process. --
ap_sig_cseq_ST_st120_fsm_36_assign_proc : process(ap_sig_bdd_1883)
begin
if (ap_sig_bdd_1883) then
ap_sig_cseq_ST_st120_fsm_36 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_36 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_37 assign process. --
ap_sig_cseq_ST_st121_fsm_37_assign_proc : process(ap_sig_bdd_1891)
begin
if (ap_sig_bdd_1891) then
ap_sig_cseq_ST_st121_fsm_37 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_37 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_312)
begin
if (ap_sig_bdd_312) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_355)
begin
if (ap_sig_bdd_355) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_86)
begin
if (ap_sig_bdd_86) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_122)
begin
if (ap_sig_bdd_122) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_140)
begin
if (ap_sig_bdd_140) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_75)
begin
if (ap_sig_bdd_75) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_194)
begin
if (ap_sig_bdd_194) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_212)
begin
if (ap_sig_bdd_212) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_248)
begin
if (ap_sig_bdd_248) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_266)
begin
if (ap_sig_bdd_266) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_284)
begin
if (ap_sig_bdd_284) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_302)
begin
if (ap_sig_bdd_302) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_320)
begin
if (ap_sig_bdd_320) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_96)
begin
if (ap_sig_bdd_96) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_365)
begin
if (ap_sig_bdd_365) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_132)
begin
if (ap_sig_bdd_132) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_150)
begin
if (ap_sig_bdd_150) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_168)
begin
if (ap_sig_bdd_168) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_186)
begin
if (ap_sig_bdd_186) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_204)
begin
if (ap_sig_bdd_204) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_222)
begin
if (ap_sig_bdd_222) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_outs_TREADY assign process. --
ap_sig_ioackin_outs_TREADY_assign_proc : process(outs_TREADY, ap_reg_ioackin_outs_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) then
ap_sig_ioackin_outs_TREADY <= outs_TREADY;
else
ap_sig_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end process;
beta_addr_1174175_part_set_fu_1054_p5 <= (tmp_2_fu_1044_p4 & ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81(479 downto 0));
beta_load_fu_1075_p1 <= reg_549;
beta_load_s_fu_1090_p1 <= reg_549;
beta_write_assign_toint_fu_1040_p1 <= grp_fu_446_p2;
data_array_addr_1_gep_fu_220_p3 <= ap_const_lv64_1(1 - 1 downto 0);
data_array_addr_gep_fu_208_p3 <= ap_const_lv64_0(1 - 1 downto 0);
-- data_array_address0 assign process. --
data_array_address0_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_pp0_stg0_fsm_30, ap_reg_ppiten_pp0_it0, tmp_s_fu_803_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
data_array_address0 <= ap_const_lv64_1(1 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
data_array_address0 <= ap_const_lv64_0(1 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
data_array_address0 <= tmp_s_fu_803_p1(1 - 1 downto 0);
else
data_array_address0 <= "X";
end if;
end process;
-- data_array_address1 assign process. --
data_array_address1_assign_proc : process(data_array_addr_reg_1095, data_array_addr_1_reg_1100, ap_reg_ppiten_pp0_it83, ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st115_fsm_31)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it83)) then
data_array_address1 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) then
data_array_address1 <= data_array_addr_1_reg_1100;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_31)) then
data_array_address1 <= data_array_addr_reg_1095;
else
data_array_address1 <= "X";
end if;
end process;
-- data_array_ce0 assign process. --
data_array_ce0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_pp0_stg0_fsm_30, ap_reg_ppiten_pp0_it0)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
data_array_ce0 <= ap_const_logic_1;
else
data_array_ce0 <= ap_const_logic_0;
end if;
end process;
-- data_array_ce1 assign process. --
data_array_ce1_assign_proc : process(ap_sig_ioackin_outs_TREADY, ap_reg_ppiten_pp0_it83, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st115_fsm_31)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_31))) then
data_array_ce1 <= ap_const_logic_1;
else
data_array_ce1 <= ap_const_logic_0;
end if;
end process;
-- data_array_d0 assign process. --
data_array_d0_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, rez_addr149150_part_set_fu_647_p5, rez_addr_1146147_part_set_fu_778_p5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
data_array_d0 <= rez_addr_1146147_part_set_fu_778_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
data_array_d0 <= rez_addr149150_part_set_fu_647_p5;
else
data_array_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
data_array_d1 <= beta_addr_1174175_part_set_reg_1593;
-- data_array_we0 assign process. --
data_array_we0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)))) then
data_array_we0 <= ap_const_logic_1;
else
data_array_we0 <= ap_const_logic_0;
end if;
end process;
-- data_array_we1 assign process. --
data_array_we1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_reg_ppstg_exitcond2_reg_1135_pp0_it82)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and (ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 = ap_const_lv1_0)))) then
data_array_we1 <= ap_const_logic_1;
else
data_array_we1 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_791_p2 <= "1" when (i1_reg_238 = ap_const_lv2_2) else "0";
g_fu_1006_p1 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10;
gamma_load_fu_1070_p1 <= reg_545;
gamma_load_s_fu_1085_p1 <= reg_545;
gamma_write_assign_toint_fu_1036_p1 <= grp_fu_442_p2;
grp_fu_250_ce <= ap_const_logic_1;
grp_fu_250_p0 <= v0x_assign4_fu_952_p1;
grp_fu_250_p1 <= v1x_assign_new_reg_1170;
grp_fu_254_ce <= ap_const_logic_1;
grp_fu_254_p0 <= v0y_assign_fu_958_p1;
grp_fu_254_p1 <= v1y_assign_new_reg_1175;
grp_fu_258_ce <= ap_const_logic_1;
grp_fu_258_p0 <= v0z_assign_fu_964_p1;
grp_fu_258_p1 <= v1z_assign_new_reg_1180;
grp_fu_262_ce <= ap_const_logic_1;
grp_fu_262_p0 <= v0x_assign4_fu_952_p1;
grp_fu_262_p1 <= v2x_assign_new_reg_1185;
grp_fu_266_ce <= ap_const_logic_1;
grp_fu_266_p0 <= v0y_assign_fu_958_p1;
grp_fu_266_p1 <= v2y_assign_new_reg_1190;
grp_fu_270_ce <= ap_const_logic_1;
grp_fu_270_p0 <= v0z_assign_fu_964_p1;
grp_fu_270_p1 <= v2z_assign_new_reg_1195;
grp_fu_274_ce <= ap_const_logic_1;
grp_fu_274_p0 <= v0x_assign4_fu_952_p1;
grp_fu_274_p1 <= rex_assign_new_reg_1215;
grp_fu_278_ce <= ap_const_logic_1;
grp_fu_278_p0 <= v0y_assign_fu_958_p1;
grp_fu_278_p1 <= rey_assign_new_reg_1220;
grp_fu_282_ce <= ap_const_logic_1;
grp_fu_282_p0 <= v0z_assign_fu_964_p1;
grp_fu_282_p1 <= rez_assign_new_reg_1225;
grp_fu_286_ce <= ap_const_logic_1;
grp_fu_286_p0 <= tmp_i_reg_1380;
grp_fu_286_p1 <= tmp_i_41_reg_1385;
grp_fu_290_ce <= ap_const_logic_1;
grp_fu_290_p0 <= tmp_3_i_reg_1390;
grp_fu_290_p1 <= tmp_4_i_reg_1395;
grp_fu_294_ce <= ap_const_logic_1;
grp_fu_294_p0 <= tmp_12_i_reg_1400;
grp_fu_294_p1 <= tmp_13_i_reg_1405;
grp_fu_298_ce <= ap_const_logic_1;
grp_fu_298_p0 <= tmp_16_i_reg_1410;
grp_fu_298_p1 <= tmp_17_i_reg_1415;
grp_fu_302_ce <= ap_const_logic_1;
grp_fu_302_p0 <= tmp_8_i_reg_1432;
grp_fu_302_p1 <= tmp_9_i_reg_1437;
grp_fu_306_ce <= ap_const_logic_1;
grp_fu_306_p0 <= tmp_21_i_reg_1454;
grp_fu_306_p1 <= tmp_22_i_reg_1459;
grp_fu_310_ce <= ap_const_logic_1;
grp_fu_310_p0 <= tmp_2_i_reg_1464;
grp_fu_310_p1 <= tmp_6_i_reg_1469;
grp_fu_314_ce <= ap_const_logic_1;
grp_fu_314_p0 <= tmp_15_i_reg_1474;
grp_fu_314_p1 <= tmp_19_i_reg_1479;
grp_fu_318_ce <= ap_const_logic_1;
grp_fu_318_p0 <= tmp_27_i_reg_1484;
grp_fu_318_p1 <= tmp_28_i_reg_1489;
grp_fu_322_ce <= ap_const_logic_1;
grp_fu_322_p0 <= tmp_32_i_reg_1494;
grp_fu_322_p1 <= tmp_33_i_reg_1499;
grp_fu_326_ce <= ap_const_logic_1;
grp_fu_326_p0 <= tmp_7_i_reg_1516;
grp_fu_326_p1 <= tmp_11_i_reg_1521;
grp_fu_330_ce <= ap_const_logic_1;
grp_fu_330_p0 <= tmp_20_i_reg_1526;
grp_fu_330_p1 <= tmp_24_i_reg_1531;
grp_fu_334_ce <= ap_const_logic_1;
grp_fu_334_p0 <= tmp_29_i_reg_1536;
grp_fu_334_p1 <= tmp_30_i_reg_1541;
grp_fu_338_ce <= ap_const_logic_1;
grp_fu_338_p0 <= tmp_34_i_reg_1546;
grp_fu_338_p1 <= tmp_35_i_reg_1551;
grp_fu_342_ce <= ap_const_logic_1;
grp_fu_342_p0 <= e_reg_1324;
grp_fu_342_p1 <= i_1_fu_1014_p1;
grp_fu_346_ce <= ap_const_logic_1;
grp_fu_346_p0 <= f_reg_1331;
grp_fu_346_p1 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10;
grp_fu_350_ce <= ap_const_logic_1;
grp_fu_350_p0 <= f_reg_1331;
grp_fu_350_p1 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10;
grp_fu_354_ce <= ap_const_logic_1;
grp_fu_354_p0 <= d_reg_1317;
grp_fu_354_p1 <= i_1_fu_1014_p1;
grp_fu_358_ce <= ap_const_logic_1;
grp_fu_358_p0 <= a_reg_1296;
grp_fu_358_p1 <= k_reg_1345;
grp_fu_362_ce <= ap_const_logic_1;
grp_fu_362_p0 <= j_reg_1338;
grp_fu_362_p1 <= b_reg_1303;
grp_fu_366_ce <= ap_const_logic_1;
grp_fu_366_p0 <= j_reg_1338;
grp_fu_366_p1 <= c_reg_1310;
grp_fu_370_ce <= ap_const_logic_1;
grp_fu_370_p0 <= a_reg_1296;
grp_fu_370_p1 <= l_reg_1352;
grp_fu_374_ce <= ap_const_logic_1;
grp_fu_374_p0 <= ap_reg_ppstg_d_reg_1317_pp0_it19;
grp_fu_374_p1 <= ap_reg_ppstg_h_reg_1366_pp0_it19;
grp_fu_378_ce <= ap_const_logic_1;
grp_fu_378_p0 <= ap_reg_ppstg_e_reg_1324_pp0_it19;
grp_fu_378_p1 <= ap_reg_ppstg_g_reg_1359_pp0_it19;
grp_fu_382_ce <= ap_const_logic_1;
grp_fu_382_p0 <= ap_reg_ppstg_b_reg_1303_pp0_it19;
grp_fu_382_p1 <= ap_reg_ppstg_l_reg_1352_pp0_it19;
grp_fu_386_ce <= ap_const_logic_1;
grp_fu_386_p0 <= ap_reg_ppstg_k_reg_1345_pp0_it19;
grp_fu_386_p1 <= ap_reg_ppstg_c_reg_1310_pp0_it19;
grp_fu_390_ce <= ap_const_logic_1;
grp_fu_390_p0 <= ap_reg_ppstg_a_reg_1296_pp0_it24;
grp_fu_390_p1 <= tmp_1_i_reg_1420;
grp_fu_394_ce <= ap_const_logic_1;
grp_fu_394_p0 <= ap_reg_ppstg_b_reg_1303_pp0_it24;
grp_fu_394_p1 <= tmp_5_i_reg_1426;
grp_fu_398_ce <= ap_const_logic_1;
grp_fu_398_p0 <= ap_reg_ppstg_f_reg_1331_pp0_it24;
grp_fu_398_p1 <= tmp_14_i_reg_1442;
grp_fu_402_ce <= ap_const_logic_1;
grp_fu_402_p0 <= ap_reg_ppstg_e_reg_1324_pp0_it24;
grp_fu_402_p1 <= tmp_18_i_reg_1448;
grp_fu_406_ce <= ap_const_logic_1;
grp_fu_406_p0 <= tmp_14_i_reg_1442;
grp_fu_406_p1 <= ap_reg_ppstg_i_1_reg_1373_pp0_it24;
grp_fu_410_ce <= ap_const_logic_1;
grp_fu_410_p0 <= tmp_18_i_reg_1448;
grp_fu_410_p1 <= ap_reg_ppstg_h_reg_1366_pp0_it24;
grp_fu_414_ce <= ap_const_logic_1;
grp_fu_414_p0 <= ap_reg_ppstg_j_reg_1338_pp0_it24;
grp_fu_414_p1 <= tmp_1_i_reg_1420;
grp_fu_418_ce <= ap_const_logic_1;
grp_fu_418_p0 <= ap_reg_ppstg_k_reg_1345_pp0_it24;
grp_fu_418_p1 <= tmp_5_i_reg_1426;
grp_fu_422_ce <= ap_const_logic_1;
grp_fu_422_p0 <= ap_reg_ppstg_c_reg_1310_pp0_it33;
grp_fu_422_p1 <= tmp_10_i_reg_1504;
grp_fu_426_ce <= ap_const_logic_1;
grp_fu_426_p0 <= ap_reg_ppstg_d_reg_1317_pp0_it33;
grp_fu_426_p1 <= tmp_23_i_reg_1510;
grp_fu_430_ce <= ap_const_logic_1;
grp_fu_430_p0 <= tmp_23_i_reg_1510;
grp_fu_430_p1 <= ap_reg_ppstg_g_reg_1359_pp0_it33;
grp_fu_434_ce <= ap_const_logic_1;
grp_fu_434_p0 <= ap_reg_ppstg_l_reg_1352_pp0_it33;
grp_fu_434_p1 <= tmp_10_i_reg_1504;
grp_fu_438_ce <= ap_const_logic_1;
grp_fu_438_p0 <= tmp_61_neg_i_reg_1583;
grp_fu_438_p1 <= im_reg_1576;
grp_fu_442_ce <= ap_const_logic_1;
grp_fu_442_p0 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77;
grp_fu_442_p1 <= im_reg_1576;
grp_fu_446_ce <= ap_const_logic_1;
grp_fu_446_p0 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77;
grp_fu_446_p1 <= im_reg_1576;
grp_fu_450_ce <= ap_const_logic_1;
grp_fu_450_p0 <= ap_const_lv32_3F800000;
grp_fu_450_p1 <= m_reg_1556;
grp_fu_459_p4 <= data_array_q1(511 downto 480);
h_fu_1010_p1 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10;
i_1_fu_1014_p1 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10;
i_fu_797_p2 <= std_logic_vector(unsigned(i1_reg_238) + unsigned(ap_const_lv2_1));
-- ins_TREADY assign process. --
ins_TREADY_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)))) then
ins_TREADY <= ap_const_logic_1;
else
ins_TREADY <= ap_const_logic_0;
end if;
end process;
ins_data_tmp_load_10_toint_fu_593_p1 <= reg_529;
ins_data_tmp_load_11_toint_fu_597_p1 <= reg_533;
ins_data_tmp_load_12_toint_fu_601_p1 <= reg_537;
ins_data_tmp_load_13_toint_fu_605_p1 <= reg_541;
ins_data_tmp_load_14_toint_fu_609_p1 <= ins_TDATA;
ins_data_tmp_load_15_toint_fu_660_p1 <= reg_489;
ins_data_tmp_load_16_toint_fu_664_p1 <= reg_493;
ins_data_tmp_load_17_toint_fu_668_p1 <= reg_497;
ins_data_tmp_load_18_toint_fu_672_p1 <= reg_501;
ins_data_tmp_load_19_toint_fu_676_p1 <= reg_505;
ins_data_tmp_load_1_toint_fu_557_p1 <= reg_493;
ins_data_tmp_load_20_toint_fu_680_p1 <= reg_509;
ins_data_tmp_load_21_toint_fu_684_p1 <= reg_513;
ins_data_tmp_load_22_toint_fu_688_p1 <= reg_517;
ins_data_tmp_load_23_toint_fu_692_p1 <= reg_521;
ins_data_tmp_load_24_toint_fu_696_p1 <= reg_525;
ins_data_tmp_load_25_toint_fu_700_p1 <= reg_529;
ins_data_tmp_load_26_toint_fu_704_p1 <= reg_533;
ins_data_tmp_load_27_toint_fu_708_p1 <= reg_537;
ins_data_tmp_load_28_toint_fu_712_p1 <= reg_541;
ins_data_tmp_load_29_toint_fu_740_p1 <= ins_TDATA;
ins_data_tmp_load_2_toint_fu_561_p1 <= reg_497;
ins_data_tmp_load_3_toint_fu_565_p1 <= reg_501;
ins_data_tmp_load_4_toint_fu_569_p1 <= reg_505;
ins_data_tmp_load_5_toint_fu_573_p1 <= reg_509;
ins_data_tmp_load_6_toint_fu_577_p1 <= reg_513;
ins_data_tmp_load_7_toint_fu_581_p1 <= reg_517;
ins_data_tmp_load_8_toint_fu_585_p1 <= reg_521;
ins_data_tmp_load_9_toint_fu_589_p1 <= reg_525;
ins_data_tmp_load_toint_fu_553_p1 <= reg_489;
-- outs_TDATA assign process. --
outs_TDATA_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, t_load_fu_1065_p1, gamma_load_fu_1070_p1, ap_sig_cseq_ST_st117_fsm_33, beta_load_fu_1075_p1, ap_sig_cseq_ST_st118_fsm_34, t_load_s_fu_1080_p1, gamma_load_s_fu_1085_p1, ap_sig_cseq_ST_st120_fsm_36, beta_load_s_fu_1090_p1, ap_sig_cseq_ST_st121_fsm_37)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)) then
outs_TDATA <= beta_load_s_fu_1090_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36)) then
outs_TDATA <= gamma_load_s_fu_1085_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)) then
outs_TDATA <= t_load_s_fu_1080_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) then
outs_TDATA <= beta_load_fu_1075_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33)) then
outs_TDATA <= gamma_load_fu_1070_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32)) then
outs_TDATA <= t_load_fu_1065_p1;
else
outs_TDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
outs_TDEST <= ins_dest_V_val_reg_1130;
outs_TID <= ins_id_V_val_reg_1125;
outs_TKEEP <= ins_keep_V_val_reg_1105;
-- outs_TLAST assign process. --
outs_TLAST_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, ins_last_V_val_reg_1120, ap_sig_cseq_ST_st117_fsm_33, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st120_fsm_36, ap_sig_cseq_ST_st121_fsm_37)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)) then
outs_TLAST <= ins_last_V_val_reg_1120;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) or (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36))) then
outs_TLAST <= ap_const_lv1_0;
else
outs_TLAST <= "X";
end if;
end process;
outs_TSTRB <= ins_strb_V_val_reg_1110;
outs_TUSER <= ins_user_V_val_reg_1115;
-- outs_TVALID assign process. --
outs_TVALID_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, ap_sig_cseq_ST_st117_fsm_33, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st120_fsm_36, ap_sig_cseq_ST_st121_fsm_37, ap_reg_ioackin_outs_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)))) then
outs_TVALID <= ap_const_logic_1;
else
outs_TVALID <= ap_const_logic_0;
end if;
end process;
rez_addr149150_part_set_fu_647_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_fu_613_p16);
rez_addr_1146147_part_set_fu_778_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_1_fu_744_p16);
t_load_fu_1065_p1 <= grp_fu_459_p4;
t_load_s_fu_1080_p1 <= grp_fu_459_p4;
t_write_assign_toint_fu_1032_p1 <= grp_fu_438_p2;
tmp_1_fu_744_p16 <= ((((((((((((((ins_data_tmp_load_29_toint_fu_740_p1 & ins_data_tmp_load_28_toint_fu_712_p1) & ins_data_tmp_load_27_toint_fu_708_p1) & ins_data_tmp_load_26_toint_fu_704_p1) & ins_data_tmp_load_25_toint_fu_700_p1) & ins_data_tmp_load_24_toint_fu_696_p1) & ins_data_tmp_load_23_toint_fu_692_p1) & ins_data_tmp_load_22_toint_fu_688_p1) & ins_data_tmp_load_21_toint_fu_684_p1) & ins_data_tmp_load_20_toint_fu_680_p1) & ins_data_tmp_load_19_toint_fu_676_p1) & ins_data_tmp_load_18_toint_fu_672_p1) & ins_data_tmp_load_17_toint_fu_668_p1) & ins_data_tmp_load_16_toint_fu_664_p1) & ins_data_tmp_load_15_toint_fu_660_p1);
tmp_2_fu_1044_p4 <= ((beta_write_assign_toint_fu_1040_p1 & gamma_write_assign_toint_fu_1036_p1) & t_write_assign_toint_fu_1032_p1);
tmp_3_fu_808_p1 <= data_array_q0(32 - 1 downto 0);
tmp_61_neg_i_fu_1022_p2 <= (tmp_61_to_int_i_fu_1019_p1 xor ap_const_lv32_80000000);
tmp_61_to_int_i_fu_1019_p1 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76;
tmp_fu_613_p16 <= ((((((((((((((ins_data_tmp_load_14_toint_fu_609_p1 & ins_data_tmp_load_13_toint_fu_605_p1) & ins_data_tmp_load_12_toint_fu_601_p1) & ins_data_tmp_load_11_toint_fu_597_p1) & ins_data_tmp_load_10_toint_fu_593_p1) & ins_data_tmp_load_9_toint_fu_589_p1) & ins_data_tmp_load_8_toint_fu_585_p1) & ins_data_tmp_load_7_toint_fu_581_p1) & ins_data_tmp_load_6_toint_fu_577_p1) & ins_data_tmp_load_5_toint_fu_573_p1) & ins_data_tmp_load_4_toint_fu_569_p1) & ins_data_tmp_load_3_toint_fu_565_p1) & ins_data_tmp_load_2_toint_fu_561_p1) & ins_data_tmp_load_1_toint_fu_557_p1) & ins_data_tmp_load_toint_fu_553_p1);
tmp_s_fu_803_p1 <= std_logic_vector(resize(unsigned(i1_reg_238),64));
v0x_assign4_fu_952_p1 <= tmp_3_reg_1155;
v0y_assign_fu_958_p1 <= v0y_assign_new_reg_1160;
v0z_assign_fu_964_p1 <= v0z_assign_new_reg_1165;
end behav;
|
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 )
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 )
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 )
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n
);
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02011ent IS
END c07s02b02x00p10n01i02011ent;
ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
TYPE int_vector is array (integer range <>) of INTEGER;
SUBTYPE int_8 is int_vector(0 to 7);
SUBTYPE int_4 is int_vector(0 to 3);
BEGIN
TESTING: PROCESS
CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE target_1 : boolean;
VARIABLE target_2 : boolean;
VARIABLE target_3 : boolean;
VARIABLE target_4 : boolean;
BEGIN
target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
wait for 5 ns;
assert NOT( target_1 and
target_2 and
target_3 and
target_4 )
report "***PASSED TEST: c07s02b02x00p10n01i02011"
severity NOTE;
assert ( target_1 and
target_2 and
target_3 and
target_4 )
report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02011ent IS
END c07s02b02x00p10n01i02011ent;
ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
TYPE int_vector is array (integer range <>) of INTEGER;
SUBTYPE int_8 is int_vector(0 to 7);
SUBTYPE int_4 is int_vector(0 to 3);
BEGIN
TESTING: PROCESS
CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE target_1 : boolean;
VARIABLE target_2 : boolean;
VARIABLE target_3 : boolean;
VARIABLE target_4 : boolean;
BEGIN
target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
wait for 5 ns;
assert NOT( target_1 and
target_2 and
target_3 and
target_4 )
report "***PASSED TEST: c07s02b02x00p10n01i02011"
severity NOTE;
assert ( target_1 and
target_2 and
target_3 and
target_4 )
report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02011ent IS
END c07s02b02x00p10n01i02011ent;
ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
TYPE int_vector is array (integer range <>) of INTEGER;
SUBTYPE int_8 is int_vector(0 to 7);
SUBTYPE int_4 is int_vector(0 to 3);
BEGIN
TESTING: PROCESS
CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE target_1 : boolean;
VARIABLE target_2 : boolean;
VARIABLE target_3 : boolean;
VARIABLE target_4 : boolean;
BEGIN
target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
wait for 5 ns;
assert NOT( target_1 and
target_2 and
target_3 and
target_4 )
report "***PASSED TEST: c07s02b02x00p10n01i02011"
severity NOTE;
assert ( target_1 and
target_2 and
target_3 and
target_4 )
report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02011arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen) and slew = 0
else 'X' when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else 'Z';
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_iopad port map (pad, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
x0 : dare_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength, filter)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en, o(j), cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol, filter)
port map (pad(j), i(j), en(j), o(j), cfgi);
end generate;
end;
|
entity logical2 is
end entity;
architecture test of logical2 is
signal x : bit;
signal one : bit := '1';
signal zero : bit := '0';
signal vec : bit_vector(0 to 1) := ('0', '1');
begin
process is
variable v : boolean := true;
begin
x <= '0';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = zero;
assert (x or zero) = zero;
assert (x or one) = one;
assert (x xor zero) = zero;
assert (x xor one) = one;
assert (x xnor zero) = one;
assert (x xnor one) = zero;
assert (x nand zero) = one;
assert (x nand one) = one;
assert (x nor zero) = one;
assert (x nor one) = zero;
x <= '1';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = one;
assert (x or zero) = one;
assert (x or one) = one;
assert (x xor zero) = one;
assert (x xor one) = zero;
assert (x xnor zero) = zero;
assert (x xnor one) = one;
assert (x nand zero) = one;
assert (x nand one) = zero;
assert (x nor zero) = zero;
assert (x nor one) = zero;
v := v and v; assert v;
v := v or v; assert v;
v := v nand v; assert not v;
v := v nor v; assert v;
v := v xor v; assert not v;
v := v xnor v; assert v;
v := v xnor v; assert v;
-- This tests short circuiting
x <= '0';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = zero;
assert (x or vec(0)) = zero;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = zero;
assert (x xor vec(1)) = one;
assert (x xnor vec(0)) = one;
assert (x xnor vec(1)) = zero;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = one;
assert (x nor vec(0)) = one;
assert (x nor vec(1)) = zero;
x <= '1';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = one;
assert (x or vec(0)) = one;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = one;
assert (x xor vec(1)) = zero;
assert (x xnor vec(0)) = zero;
assert (x xnor vec(1)) = one;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = zero;
assert (x nor vec(0)) = zero;
assert (x nor vec(1)) = zero;
wait;
end process;
end architecture;
|
architecture RTL of ENT is
BEGIN
end RTL;
architecture RTL of ENT is
BEGIN
end rtl;
architecture RTL of ENT is
BEGIN
end Rtl;
architecture RTL of ENT is
BEGIN
end;
architecture RTL of ENT is
BEGIN
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue3 is
end issue3;
architecture beh of issue3 is
type t_rec is
record
elem : std_logic_vector (3 downto 0);
end record;
begin
assert t_rec'(elem => 4b"0") = t_rec'(elem => 3b"0");
end architecture beh;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:13:41 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/bram/bram_funcsim.vhdl
-- Design : bram
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bramblk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bramblk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end bramblk_mem_gen_prim_wrapper;
architecture STRUCTURE of bramblk_mem_gen_prim_wrapper is
signal \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => '1',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bramblk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bramblk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bramblk_mem_gen_prim_width;
architecture STRUCTURE of bramblk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.bramblk_mem_gen_prim_wrapper
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bramblk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bramblk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bramblk_mem_gen_generic_cstr;
architecture STRUCTURE of bramblk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bramblk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bramblk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bramblk_mem_gen_top : entity is "blk_mem_gen_top";
end bramblk_mem_gen_top;
architecture STRUCTURE of bramblk_mem_gen_top is
begin
\valid.cstr\: entity work.bramblk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bramblk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bramblk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end bramblk_mem_gen_v8_2_synth;
architecture STRUCTURE of bramblk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.bramblk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bramblk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "bram.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 2048;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 2048;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 11;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 2048;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 11;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \bramblk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 5.11005 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \bramblk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \bramblk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \bramblk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bramblk_mem_gen_v8_2_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram : entity is "bram,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of bram : entity is "bram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.11005 mW}";
end bram;
architecture STRUCTURE of bram is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 5.11005 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\bramblk_mem_gen_v8_2__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(15 downto 0) => dina(15 downto 0),
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(15 downto 0) => NLW_U0_douta_UNCONNECTED(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_16
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_16
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_16 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : OUT std_logic
);
END TWDLROM_3_16;
ARCHITECTURE rtl OF TWDLROM_3_16 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_16_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_16_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_16_re_tmp <= twdlIn_re;
twdl_3_16_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_16_re <= std_logic_vector(twdl_3_16_re_tmp);
twdl_3_16_im <= std_logic_vector(twdl_3_16_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_16_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_16_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
package order1 is
type t is (A, B, C);
type t_vec is array (natural range <>) of t;
end package;
package order1 is
type t is (C, B, A); -- Redefine t
type t_vec is array (1 to 2) of t;
constant x : boolean := t_vec'(A, A) < t_vec'(C, C); -- Should not fold!
end package;
|
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_bpm2_with_dcc_rtm is
generic (
-- Number of RTM SFP GTs
g_NUM_SFPS : integer := 4;
-- Start index of the RTM SFP GTs
g_SFP_START_ID : integer := 4;
-- Number of P2P GTs
g_NUM_P2P_GTS : integer := 8;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc1_adc_clk_div_rst_p_o : out std_logic;
fmc1_adc_clk_div_rst_n_o : out std_logic;
fmc1_adc_ext_rst_n_o : out std_logic;
fmc1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc1_adc_clk0_p_i : in std_logic := '0';
fmc1_adc_clk0_n_i : in std_logic := '0';
fmc1_adc_clk1_p_i : in std_logic := '0';
fmc1_adc_clk1_n_i : in std_logic := '0';
fmc1_adc_clk2_p_i : in std_logic := '0';
fmc1_adc_clk2_n_i : in std_logic := '0';
fmc1_adc_clk3_p_i : in std_logic := '0';
fmc1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc1_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc1_prsnt_i : in std_logic;
--fmc1_pg_m2c_i : in std_logic;
--fmc1_clk_dir_i : in std_logic;
-- Trigger
fmc1_trig_dir_o : out std_logic;
fmc1_trig_term_o : out std_logic;
fmc1_trig_val_p_b : inout std_logic;
fmc1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc1_adc_spi_clk_o : out std_logic;
fmc1_adc_spi_mosi_o : out std_logic;
fmc1_adc_spi_miso_i : in std_logic;
fmc1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc1_si571_scl_pad_b : inout std_logic;
fmc1_si571_sda_pad_b : inout std_logic;
fmc1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc1_spi_ad9510_cs_o : out std_logic;
fmc1_spi_ad9510_sclk_o : out std_logic;
fmc1_spi_ad9510_mosi_o : out std_logic;
fmc1_spi_ad9510_miso_i : in std_logic;
fmc1_pll_function_o : out std_logic;
fmc1_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc1_fpga_clk_p_i : in std_logic;
fmc1_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc1_amc7823_spi_cs_o : out std_logic;
fmc1_amc7823_spi_sclk_o : out std_logic;
fmc1_amc7823_spi_mosi_o : out std_logic;
fmc1_amc7823_spi_miso_i : in std_logic;
fmc1_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc2_adc_clk_div_rst_p_o : out std_logic;
fmc2_adc_clk_div_rst_n_o : out std_logic;
fmc2_adc_ext_rst_n_o : out std_logic;
fmc2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc2_adc_clk0_p_i : in std_logic := '0';
fmc2_adc_clk0_n_i : in std_logic := '0';
fmc2_adc_clk1_p_i : in std_logic := '0';
fmc2_adc_clk1_n_i : in std_logic := '0';
fmc2_adc_clk2_p_i : in std_logic := '0';
fmc2_adc_clk2_n_i : in std_logic := '0';
fmc2_adc_clk3_p_i : in std_logic := '0';
fmc2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc2_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc2_prsnt_i : in std_logic;
--fmc2_pg_m2c_i : in std_logic;
--fmc2_clk_dir_i : in std_logic;
-- Trigger
fmc2_trig_dir_o : out std_logic;
fmc2_trig_term_o : out std_logic;
fmc2_trig_val_p_b : inout std_logic;
fmc2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc2_adc_spi_clk_o : out std_logic;
fmc2_adc_spi_mosi_o : out std_logic;
fmc2_adc_spi_miso_i : in std_logic;
fmc2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc2_si571_scl_pad_b : inout std_logic;
fmc2_si571_sda_pad_b : inout std_logic;
fmc2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc2_spi_ad9510_cs_o : out std_logic;
fmc2_spi_ad9510_sclk_o : out std_logic;
fmc2_spi_ad9510_mosi_o : out std_logic;
fmc2_spi_ad9510_miso_i : in std_logic;
fmc2_pll_function_o : out std_logic;
fmc2_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc2_fpga_clk_p_i : in std_logic;
fmc2_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc2_amc7823_spi_cs_o : out std_logic;
fmc2_amc7823_spi_sclk_o : out std_logic;
fmc2_amc7823_spi_mosi_o : out std_logic;
fmc2_amc7823_spi_miso_i : in std_logic;
fmc2_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic;
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
rtm_sfp_rx_p_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '0');
rtm_sfp_rx_n_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '1');
rtm_sfp_tx_p_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
rtm_sfp_tx_n_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b : inout std_logic;
rtm_sda_b : inout std_logic;
-- Si570 oscillator output enable
rtm_si570_oe_o : out std_logic;
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to
-- AFC
--rtm_rtm_sync_clk_p_o : out std_logic;
--rtm_rtm_sync_clk_n_o : out std_logic;
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
rtm_clk_in_sel_o : out std_logic;
-- FPGA clocks from CDCLVD1212
rtm_fpga_clk1_p_i : in std_logic := '0';
rtm_fpga_clk1_n_i : in std_logic := '0';
rtm_fpga_clk2_p_i : in std_logic := '0';
rtm_fpga_clk2_n_i : in std_logic := '0';
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
-- The PISO chips are organized like this:
--
-- Parallel load
rtm_sfp_status_reg_pl_o : out std_logic;
-- Clock N
rtm_sfp_status_reg_clk_n_o : out std_logic;
-- Serial output
rtm_sfp_status_reg_out_i : in std_logic := '0';
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
-- The SIPO chips are organized like this:
--
-- Strobe
rtm_sfp_ctl_str_n_o : out std_logic;
-- Data input
rtm_sfp_ctl_din_n_o : out std_logic;
-- Parallel output enable
rtm_sfp_ctl_oe_n_o : out std_logic;
-- External clock from RTM to FPGA
rtm_ext_clk_p_i : in std_logic := '0';
rtm_ext_clk_n_i : in std_logic := '0'
);
end dbe_bpm2_with_dcc_rtm;
architecture rtl of dbe_bpm2_with_dcc_rtm is
begin
cmp_dbe_bpm_gen : entity work.dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMC250M",
g_WITH_RTM_SFP => true,
g_NUM_SFPS => g_NUM_SFPS,
g_SFP_START_ID => g_SFP_START_ID,
g_WITH_RTM_SFP_FOFB_DCC => true,
g_NUM_P2P_GTS => g_NUM_P2P_GTS,
g_P2P_GT_START_ID => g_P2P_GT_START_ID,
g_WITH_P2P_FOFB_DCC => true
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i => p2p_gt_rx_p_i,
p2p_gt_rx_n_i => p2p_gt_rx_n_i,
p2p_gt_tx_p_o => p2p_gt_tx_p_o,
p2p_gt_tx_n_o => p2p_gt_tx_n_o,
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o => fmc1_adc_clk_div_rst_p_o,
fmc250_1_adc_clk_div_rst_n_o => fmc1_adc_clk_div_rst_n_o,
fmc250_1_adc_ext_rst_n_o => fmc1_adc_ext_rst_n_o,
fmc250_1_adc_sleep_o => fmc1_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i => fmc1_adc_clk0_p_i,
fmc250_1_adc_clk0_n_i => fmc1_adc_clk0_n_i,
fmc250_1_adc_clk1_p_i => fmc1_adc_clk1_p_i,
fmc250_1_adc_clk1_n_i => fmc1_adc_clk1_n_i,
fmc250_1_adc_clk2_p_i => fmc1_adc_clk2_p_i,
fmc250_1_adc_clk2_n_i => fmc1_adc_clk2_n_i,
fmc250_1_adc_clk3_p_i => fmc1_adc_clk3_p_i,
fmc250_1_adc_clk3_n_i => fmc1_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i => fmc1_adc_data_ch0_p_i,
fmc250_1_adc_data_ch0_n_i => fmc1_adc_data_ch0_n_i,
fmc250_1_adc_data_ch1_p_i => fmc1_adc_data_ch1_p_i,
fmc250_1_adc_data_ch1_n_i => fmc1_adc_data_ch1_n_i,
fmc250_1_adc_data_ch2_p_i => fmc1_adc_data_ch2_p_i,
fmc250_1_adc_data_ch2_n_i => fmc1_adc_data_ch2_n_i,
fmc250_1_adc_data_ch3_p_i => fmc1_adc_data_ch3_p_i,
fmc250_1_adc_data_ch3_n_i => fmc1_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o => fmc1_trig_dir_o,
fmc250_1_trig_term_o => fmc1_trig_term_o,
fmc250_1_trig_val_p_b => fmc1_trig_val_p_b,
fmc250_1_trig_val_n_b => fmc1_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o => fmc1_adc_spi_clk_o,
fmc250_1_adc_spi_mosi_o => fmc1_adc_spi_mosi_o,
fmc250_1_adc_spi_miso_i => fmc1_adc_spi_miso_i,
fmc250_1_adc_spi_cs_adc0_n_o => fmc1_adc_spi_cs_adc0_n_o,
fmc250_1_adc_spi_cs_adc1_n_o => fmc1_adc_spi_cs_adc1_n_o,
fmc250_1_adc_spi_cs_adc2_n_o => fmc1_adc_spi_cs_adc2_n_o,
fmc250_1_adc_spi_cs_adc3_n_o => fmc1_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_1_si571_scl_pad_b => fmc1_si571_scl_pad_b,
fmc250_1_si571_sda_pad_b => fmc1_si571_sda_pad_b,
fmc250_1_si571_oe_o => fmc1_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o => fmc1_spi_ad9510_cs_o,
fmc250_1_spi_ad9510_sclk_o => fmc1_spi_ad9510_sclk_o,
fmc250_1_spi_ad9510_mosi_o => fmc1_spi_ad9510_mosi_o,
fmc250_1_spi_ad9510_miso_i => fmc1_spi_ad9510_miso_i,
fmc250_1_pll_function_o => fmc1_pll_function_o,
fmc250_1_pll_status_i => fmc1_pll_status_i,
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i => fmc1_fpga_clk_p_i,
fmc250_1_fpga_clk_n_i => fmc1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o => fmc1_clk_sel_o,
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o => fmc1_amc7823_spi_cs_o,
fmc250_1_amc7823_spi_sclk_o => fmc1_amc7823_spi_sclk_o,
fmc250_1_amc7823_spi_mosi_o => fmc1_amc7823_spi_mosi_o,
fmc250_1_amc7823_spi_miso_i => fmc1_amc7823_spi_miso_i,
fmc250_1_amc7823_davn_i => fmc1_amc7823_davn_i,
-- FMC LEDs
fmc250_1_led1_o => fmc1_led1_o,
fmc250_1_led2_o => fmc1_led2_o,
fmc250_1_led3_o => fmc1_led3_o,
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o => fmc2_adc_clk_div_rst_p_o,
fmc250_2_adc_clk_div_rst_n_o => fmc2_adc_clk_div_rst_n_o,
fmc250_2_adc_ext_rst_n_o => fmc2_adc_ext_rst_n_o,
fmc250_2_adc_sleep_o => fmc2_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i => fmc2_adc_clk0_p_i,
fmc250_2_adc_clk0_n_i => fmc2_adc_clk0_n_i,
fmc250_2_adc_clk1_p_i => fmc2_adc_clk1_p_i,
fmc250_2_adc_clk1_n_i => fmc2_adc_clk1_n_i,
fmc250_2_adc_clk2_p_i => fmc2_adc_clk2_p_i,
fmc250_2_adc_clk2_n_i => fmc2_adc_clk2_n_i,
fmc250_2_adc_clk3_p_i => fmc2_adc_clk3_p_i,
fmc250_2_adc_clk3_n_i => fmc2_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i => fmc2_adc_data_ch0_p_i,
fmc250_2_adc_data_ch0_n_i => fmc2_adc_data_ch0_n_i,
fmc250_2_adc_data_ch1_p_i => fmc2_adc_data_ch1_p_i,
fmc250_2_adc_data_ch1_n_i => fmc2_adc_data_ch1_n_i,
fmc250_2_adc_data_ch2_p_i => fmc2_adc_data_ch2_p_i,
fmc250_2_adc_data_ch2_n_i => fmc2_adc_data_ch2_n_i,
fmc250_2_adc_data_ch3_p_i => fmc2_adc_data_ch3_p_i,
fmc250_2_adc_data_ch3_n_i => fmc2_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o => fmc2_trig_dir_o,
fmc250_2_trig_term_o => fmc2_trig_term_o,
fmc250_2_trig_val_p_b => fmc2_trig_val_p_b,
fmc250_2_trig_val_n_b => fmc2_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o => fmc2_adc_spi_clk_o,
fmc250_2_adc_spi_mosi_o => fmc2_adc_spi_mosi_o,
fmc250_2_adc_spi_miso_i => fmc2_adc_spi_miso_i,
fmc250_2_adc_spi_cs_adc0_n_o => fmc2_adc_spi_cs_adc0_n_o,
fmc250_2_adc_spi_cs_adc1_n_o => fmc2_adc_spi_cs_adc1_n_o,
fmc250_2_adc_spi_cs_adc2_n_o => fmc2_adc_spi_cs_adc2_n_o,
fmc250_2_adc_spi_cs_adc3_n_o => fmc2_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_2_si571_scl_pad_b => fmc2_si571_scl_pad_b,
fmc250_2_si571_sda_pad_b => fmc2_si571_sda_pad_b,
fmc250_2_si571_oe_o => fmc2_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o => fmc2_spi_ad9510_cs_o,
fmc250_2_spi_ad9510_sclk_o => fmc2_spi_ad9510_sclk_o,
fmc250_2_spi_ad9510_mosi_o => fmc2_spi_ad9510_mosi_o,
fmc250_2_spi_ad9510_miso_i => fmc2_spi_ad9510_miso_i,
fmc250_2_pll_function_o => fmc2_pll_function_o,
fmc250_2_pll_status_i => fmc2_pll_status_i,
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i => fmc2_fpga_clk_p_i,
fmc250_2_fpga_clk_n_i => fmc2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o => fmc2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o => fmc2_amc7823_spi_cs_o,
fmc250_2_amc7823_spi_sclk_o => fmc2_amc7823_spi_sclk_o,
fmc250_2_amc7823_spi_mosi_o => fmc2_amc7823_spi_mosi_o,
fmc250_2_amc7823_spi_miso_i => fmc2_amc7823_spi_miso_i,
fmc250_2_amc7823_davn_i => fmc2_amc7823_davn_i,
-- FMC LEDs
fmc250_2_led1_o => fmc2_led1_o,
fmc250_2_led2_o => fmc2_led2_o,
fmc250_2_led3_o => fmc2_led3_o,
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
rtm_sfp_rx_p_i => rtm_sfp_rx_p_i,
rtm_sfp_rx_n_i => rtm_sfp_rx_n_i,
rtm_sfp_tx_p_o => rtm_sfp_tx_p_o,
rtm_sfp_tx_n_o => rtm_sfp_tx_n_o,
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b => rtm_scl_b,
rtm_sda_b => rtm_sda_b,
-- Si570 oscillator output enable
rtm_si570_oe_o => rtm_si570_oe_o,
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected to FPGA
-- rtm_sync_clk_p_o => rtm_sync_clk_p_o,
-- rtm_sync_clk_n_o => rtm_sync_clk_n_o,
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
rtm_clk_in_sel_o => rtm_clk_in_sel_o,
-- FPGA clocks from CDCLVD1212
rtm_fpga_clk1_p_i => rtm_fpga_clk1_p_i,
rtm_fpga_clk1_n_i => rtm_fpga_clk1_n_i,
rtm_fpga_clk2_p_i => rtm_fpga_clk2_p_i,
rtm_fpga_clk2_n_i => rtm_fpga_clk2_n_i,
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
--
-- Parallel load
rtm_sfp_status_reg_pl_o => rtm_sfp_status_reg_pl_o,
-- Clock N
rtm_sfp_status_reg_clk_n_o => rtm_sfp_status_reg_clk_n_o,
-- Serial output
rtm_sfp_status_reg_out_i => rtm_sfp_status_reg_out_i,
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
--
-- Strobe
rtm_sfp_ctl_str_n_o => rtm_sfp_ctl_str_n_o,
-- Data input
rtm_sfp_ctl_din_n_o => rtm_sfp_ctl_din_n_o,
-- Parallel output enable
rtm_sfp_ctl_oe_n_o => rtm_sfp_ctl_oe_n_o,
-- External clock from RTM to FPGA
rtm_ext_clk_p_i => rtm_ext_clk_p_i,
rtm_ext_clk_n_i => rtm_ext_clk_n_i
);
end rtl;
|
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2
-- File: grpci2.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dftlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2 is
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH; -- For trace buffers
oepol : integer := 0;
hmindex : integer := 0;
hdmindex : integer := 0;
hsindex : integer := 0;
haddr : integer := 0;
hmask : integer := 0;
ioaddr : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
irq : integer := 0;
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram...
hostrst : integer range 0 to 2 := 0; -- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
tbpindex : integer := 0;
tbpaddr : integer := 0;
tbpmask : integer := 16#F00#;
netlist : integer range 0 to 1 := 0; -- Use PHY netlist
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#;
iotest : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
dirq : in std_logic_vector(3 downto 0);
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbdmi : in ahb_mst_in_type;
ahbdmo : out ahb_mst_out_type;
ptarst : out std_logic;
tbapbi : in apb_slv_in_type := apb_slv_in_none;
tbapbo : out apb_slv_out_type;
debugo : out std_logic_vector(debug*255 downto 0)
);
end;
architecture rtl of grpci2 is
-- PHY =>
signal phyi : grpci2_phy_in_type;
signal phyo : grpci2_phy_out_type;
signal sig_m_request, sig_m_mabort, sig_t_abort, sig_t_ready, sig_t_retry : std_logic;
signal sig_pr_conf_comm_serren, sig_pr_conf_comm_perren : std_logic;
signal sig_soft_rst : std_logic_vector(2 downto 0);
-- PHY <=
constant PT_DEPTH : integer := 5 + log2(tracebuffer/32);
constant HIOMASK : integer := 16#E00# - 16#200#*conv_integer(conv_std_logic(tracebuffer/=0));
constant MST_ACC_CNT : integer := fifo_count - 1;
constant RAM_LATENCY : integer := 1 + ram_raw_latency(memtech); -- Delay FIFO readout one extra write clock cycle for some technologies
type pci_bars_type is array (0 to 5) of std_logic_vector(31 downto 0);
constant pci_bars_none : pci_bars_type := (others => (others => '0'));
type pci_config_space_type is record
bar : pci_bars_type;
comm : pci_config_command_type;
stat : pci_config_status_type;
ltimer : std_logic_vector(7 downto 0);
iline : std_logic_vector(7 downto 0);
pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar
bar_mask : pci_bars_type; -- PCI bar mask (bar size)
cfg_map : std_logic_vector(31 downto 0);-- Map extended PCI configuration space to AHB address
end record;
constant pci_config_space_none : pci_config_space_type := (pci_bars_none, pci_config_command_none, pci_config_status_none, (others => '0'), (others => '0'), pci_bars_none, pci_bars_none, (others => '0'));
type pci_config_space_multi_type is array (0 to multifunc) of pci_config_space_type;
type pci_fifo_out_type is record
data : std_logic_vector(31 downto 0);
err : std_logic_vector(3 downto 0);
end record;
constant pci_fifo_out_none : pci_fifo_out_type := ((others => '0'), (others => '0'));
type pci_fifo_in_type is record
en : std_logic; -- Read/write enable for fifo
addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
data : std_logic_vector(31 downto 0); -- Fifo input data
end record;
constant pci_fifo_in_none : pci_fifo_in_type := ('0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'));
type pci_g_acc_trans_type is record
pending : std_logic; -- Access pending (valid)
addr : std_logic_vector(31 downto 0); -- Access start address
acctype : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
accmode : std_logic_vector(2 downto 0); -- Access mode (use cancel, use length, burst)
size : std_logic_vector(2 downto 0); -- Access size
offset : std_logic_vector(1 downto 0); -- Access byte offset
index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
length : std_logic_vector(15 downto 0); -- Access length
func : std_logic_vector(2 downto 0); -- The master belongs to this PCI function
--
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
end record;
constant pci_g_acc_trans_none : pci_g_acc_trans_type := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), 0, (others => '0'), (others => '0'), (others => '0'), '0');
type pci_g_acc_status_trans_type is record
done : std_logic; -- Access done
status : std_logic_vector(3 downto 0); -- Access status
count : std_logic_vector(15 downto 0);-- Access transfer count
end record;
constant pci_g_acc_status_trans_none : pci_g_acc_status_trans_type := ('0', (others => '0'), (others => '0'));
type pci_g_acc_status_trans_multi_type is array (0 to 1) of pci_g_acc_status_trans_type;
constant pci_g_acc_status_trans_multi_none : pci_g_acc_status_trans_multi_type := (others => pci_g_acc_status_trans_none);
type pci_g_fifo_trans_type is record
pending : std_logic_vector(2 downto 0); -- FIFO pending (valid)
start : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO start address (first valid data)
stop : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO stop address (last valid data)
firstf : std_logic; -- First FIFO
lastf : std_logic; -- Last FIFO
status : std_logic_vector(3 downto 0); -- Error status
--
last_cbe : std_logic_vector(3 downto 0); -- Byte enable of last data
end record;
constant pci_g_fifo_trans_none : pci_g_fifo_trans_type := ((others => '0'), zero32(FIFO_DEPTH-1 downto 0), zero32(FIFO_DEPTH-1 downto 0), '0', '0', (others => '0'), (others => '0'));
type pci_g_acc_trans_multi_type is array (0 to 1) of pci_g_acc_trans_type;
constant pci_g_acc_trans_multi_none : pci_g_acc_trans_multi_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_type is array (0 to 3) of pci_g_acc_trans_type;
constant pci_g_acc_trans_vector_none : pci_g_acc_trans_vector_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_multi_type is array (0 to 1) of pci_g_acc_trans_vector_type;
constant pci_g_acc_trans_vector_multi_none : pci_g_acc_trans_vector_multi_type := (others => pci_g_acc_trans_vector_none);
type pci_g_fifo_trans_vector_type is array (0 to FIFO_COUNT-1) of pci_g_fifo_trans_type;
constant pci_g_fifo_trans_vector_none: pci_g_fifo_trans_vector_type := (others => pci_g_fifo_trans_none);
type pci_g_fifo_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_trans_vector_type;
constant pci_g_fifo_trans_vector_multi_none : pci_g_fifo_trans_vector_multi_type := (others => pci_g_fifo_trans_vector_none);
subtype pci_g_fifo_ack_trans_vector_type is std_logic_vector(FIFO_COUNT-1 downto 0);
constant pci_g_fifo_ack_trans_vector_none : pci_g_fifo_ack_trans_vector_type := (others => '0');
type pci_g_fifo_ack_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_ack_trans_vector_type;
constant pci_g_fifo_ack_trans_vector_multi_none : pci_g_fifo_ack_trans_vector_multi_type := (others => pci_g_fifo_ack_trans_vector_none);
type pci_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cmd : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
active : std_logic_vector(1 downto 0); -- [1]: access has data to transfer, [0]: access active
done : std_logic_vector(2 downto 0); -- [2]: access terminated by error, [1]:(PCI master write: all pending fifos acked), [0]: access done
status : std_logic_vector(2 downto 0); -- Error status
first : std_logic; -- First data in access
func : integer range 0 to multifunc; -- PCI function accessed
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector(FIFO_DEPTH-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
end record;
constant pci_master_acc_none : pci_master_acc_type := ('0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', 0, 0, zero32(FIFO_DEPTH-1 downto 0), '0', '0');
type pci_master_acc_multi_type is array (0 to 1) of pci_master_acc_type;
constant pci_master_acc_multi_none : pci_master_acc_multi_type := (pci_master_acc_none, pci_master_acc_none);
constant acc_sel_ahb : integer := 0;
constant acc_sel_dma : integer := 1;
type ahb_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cbe : std_logic_vector(3 downto 0); -- Access byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
acctype : std_logic_vector(3 downto 0); --
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
burst : std_logic; -- Same as accmode(0);
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
fifo_wdata : std_logic_vector(31 downto 0);
end record;
constant ahb_master_acc_none : ahb_master_acc_type := ('0', (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'), '0', 0, (others => '0'), '0', '0', (others => '0'));
type pci_fifo_type is record
index : integer range 0 to FIFO_COUNT-1;-- FIFO index
ctrl : pci_fifo_in_type; -- FIFO RAM control signal
end record;
constant pci_fifo_none : pci_fifo_type := (0, pci_fifo_in_none);
type pci_access_type is record
addr : std_logic_vector(31 downto 0); -- Access address
ready : std_logic; -- Data ready
pending : std_logic; -- Access saved and pending
read : std_logic; -- Target read / write access
burst : std_logic; -- Burst access
retry : std_logic; -- Access terminated with retry
acc_type: std_logic_vector(1 downto 0); -- Access type: 00: memory, 10: configuration space, 11: mapping registers, 01: ext conf space mapped to AHB
bar : std_logic_vector(5 downto 0); -- PCI bar accessed
func : integer range 0 to multifunc; -- PCI function accessed
match : std_logic; -- Access matching pending access
continue: std_logic; -- Burst may continue
newacc : std_logic; -- New access, discard old data
oldburst: std_logic; -- When "new access" store last burst
impcfgreg: std_logic; -- Indicates if the current Configuration Space register is implemented
end record;
constant pci_access_none : pci_access_type := ((others => '0'), '0', '0', '0', '0', '0', (others => '0'), (others => '0'), 0, '0', '0', '0', '0', '1');
type pci_access_vector_type is array (0 to 1) of pci_access_type;
constant pci_access_vector_none : pci_access_vector_type := (others => pci_access_none);
type pci_target_type is record
state : pci_target_state_type;
fstate : pci_target_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
atp : pci_fifo_type; -- AMBA to PCI FIFO
pta : pci_fifo_type; -- PCI to AMBA FIFO
addr : std_logic_vector(31 downto 0);-- Used as FIFO address during write
cur_acc : pci_access_vector_type; -- Current PCI access
lcount : std_logic_vector(2 downto 0); -- Target latency counter 8 clocks (initial latency should 16 clocks)
preload : std_logic; -- Preload the internal FIFO
preload_count : std_logic_vector(1 downto 0); -- Counter used when preloading the internal FIFO
stop : std_logic;
stoped : std_logic;
hold : std_logic_vector(0 downto 0);
hold_fifo : std_logic;
hold_reset : std_logic;
hold_write : std_logic;
first : std_logic_vector(1 downto 0); -- Used to mark first fifo. bit[1]: first fifo in transfer, bit[0]: first word in fifo
conf_addr : std_logic_vector(3 downto 0);
first_word : std_logic; -- Indicate first word in access
diswithout : std_logic; -- Disconnect without data
addr_perr : std_logic; -- Address Parity Error detected
abort : std_logic; -- Target abort
retry : std_logic;
discard : std_logic;
accbuf : pci_g_acc_trans_vector_type; -- PCI target to AHB master access buffer
blen : std_logic_vector(15 downto 0);-- PCI target burst length boundary
blenmask : std_logic_vector(15 downto 0);-- PCI target burst length boundary mask
saverfifo : std_logic; -- Save prefetched FIFO until next PCI access in case of target termination (disconnect without data)
discardtimeren : std_logic; -- Enable/Disable discard timer
discardtimer : std_logic_vector(15 downto 0);-- Discard prefetched data after 2^15 PCI clock cycles
end record;
constant pci_target_none : pci_target_type := (
pt_idle, ptf_idle, pci_core_fifo_vector_none, pci_fifo_none, pci_fifo_none,
(others => '0'), pci_access_vector_none, (others => '0'), '0', (others => '0'), '0', '0',
(others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', pci_g_acc_trans_vector_none, (others => '0'),
(others => '0'), '0', '0', (others => '0'));
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
abort : std_logic_vector(1 downto 0); -- Master/Target abort [0]: master or target abort; [1]: 1 = target abort, 0 = master abort
ltimer : std_logic_vector(7 downto 0); -- PCI master latency timer
framedel : std_logic; -- Delayed frame
devsel_tout : std_logic_vector(2 downto 0); -- Devsel time out conter;
devsel_asserted : std_logic; -- Devsel asserted;
addr : std_logic_vector(31 downto 0);-- PCI state address
cbe_data : std_logic_vector(3 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
hold : std_logic_vector(1 downto 0); -- Hold transfer due to no available fifo
hold_fifo : std_logic; -- Hold FIFO due to no available fifo
done_fifo : std_logic; -- No more FIFO Available
done_trans : std_logic; -- No more data in FIFO (transfer done)
term : std_logic_vector(1 downto 0); -- Terminate transfer
done : std_logic; -- Transfer done
first : std_logic_vector(1 downto 0); -- First word in current access
last : std_logic_vector(1 downto 0); -- Last word in transfer
preload : std_logic;
preload_count : std_logic_vector(1 downto 0);
afull : std_logic; -- FIFO almost full on read
afullcnt : std_logic_vector(1 downto 0); -- Counter for the three last word in FIFO on read
burst : std_logic; -- Read burst access => signle accecc or preload
perren : std_logic_vector(1 downto 0); -- bit[0]: Drive output enable for Parity error, bit[1] delayed bit[0]
detectperr : std_logic_vector(1 downto 0); -- bit[2] = 1: Detect Parity error on write
twist : std_logic; -- On for PCI configuration space access, otherwise = pr.pta_trans.ca_twist
first_word : std_logic; -- Indicate first word in access
waitonstop : std_logic;
acc : pci_master_acc_multi_type; -- DMA/AHB slave => PCI master accesses
acc_sel : integer range 0 to 1; -- Active access, 0 = AHB slave; 1 = DMA
acc_cnt : integer range 0 to MST_ACC_CNT; -- Access transfer count (FIFO), for switching DMA/AHB-slave
acc_switch : std_logic; -- Access switching DMA/AHB-slave
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wdata : std_logic_vector(31 downto 0);
fifo_switch : std_logic;
end record;
constant pci_master_none : pci_master_type := (
pm_idle, pmf_idle, pci_core_fifo_vector_none, (others => '0'), (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
'0', '0', (others => '0'), '0', (others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', '0', pci_master_acc_multi_none,
0, 0, '0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'), '0');
type pci_trace_to_apb_trans_type is record
enable : std_logic;
armed : std_logic;
wrap : std_logic;
taddr : std_logic_vector(PT_DEPTH-1 downto 0);
start_ack : std_logic;
stop_ack : std_logic;
--
dbg_ad : std_logic_vector(31 downto 0);
dbg_sig : std_logic_vector(16 downto 0);
dbg_cur_ad : std_logic_vector(31 downto 0);
dbg_cur_acc : std_logic_vector(8 downto 0);
end record;
constant pci_trace_to_apb_trans_none : pci_trace_to_apb_trans_type := ('0', '0', '0', zero32(PT_DEPTH-1 downto 0), '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type apb_to_pci_trace_trans_type is record
start : std_logic;
stop : std_logic;
mode : std_logic_vector(3 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
ad : std_logic_vector(31 downto 0);
admask : std_logic_vector(31 downto 0);
sig : std_logic_vector(16 downto 0);
sigmask : std_logic_vector(16 downto 0);
end record;
constant apb_to_pci_trace_trans_none : apb_to_pci_trace_trans_type := ('0', '0', (others => '0'), zero32(PT_DEPTH-1 downto 0),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type pci_trace_type is record
addr : std_logic_vector(PT_DEPTH-1 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
end record;
constant pci_trace_none : pci_trace_type := (zero32(PT_DEPTH-1 downto 0), zero32(PT_DEPTH-1 downto 0), (others => '0'));
type pci_msd_acc_cancel_acc_multi_type is array (0 to 1) of std_logic_vector(2 downto 0);
type pci_to_ahb_trans_type is record
-- PCI target <=> AHB master
tm_acc : pci_g_acc_trans_type; -- AHB master access (read/write) [PCI target]
tm_acc_cancel : std_logic; -- Cancel access [PCI target]
tm_acc_done_ack : std_logic; -- Ack access done [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- PCI target => AHB master FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- AHB master => PCI target FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc_ack : std_logic_vector(0 to 1); -- PCI master access ack [AHB/DMA]
--msd_acc_cancel_ack : std_logic_vector(0 to 1); -- Cancel access ack [AHB/DMA]
msd_acc_cancel_ack : pci_msd_acc_cancel_acc_multi_type; -- Cancel access ack [AHB/DMA]
msd_acc_done : pci_g_acc_status_trans_multi_type; -- Access status [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO ack
-- PCI config space <=> AHB
ca_host : std_logic;
ca_pcimsten : std_logic_vector(0 to multifunc);
ca_twist : std_logic; -- 1: byte twisting litle (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
-- PCI system
pa_serr : std_logic;
pa_discardtout: std_logic;
rst_ack : std_logic_vector(2 downto 0);
end record;
type ahb_to_pci_trans_type is record
-- PCI target <=> AHB master
tm_acc_ack : std_logic; -- AHB master access ack [PCI target]
tm_acc_cancel_ack : std_logic_vector(2 downto 0); -- Cancel access ack [PCI target]
tm_acc_done : pci_g_acc_status_trans_type; -- Access status [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- AHB master => PCI target FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- PCI target => AHB master FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc : pci_g_acc_trans_multi_type; -- PCI master access (read/write) [AHB/DMA]
msd_acc_cancel : std_logic_vector(1 downto 0); -- Cancel access [AHB/DMA]
msd_acc_done_ack : std_logic_vector(1 downto 0); -- Ack access done [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO ack
-- PCI system
pa_serr_rst : std_logic;
pa_discardtout_rst: std_logic;
rst : std_logic_vector(2 downto 0);
mstswdis : std_logic;
end record;
type pci_sync_type is array (1 to 2) of ahb_to_pci_trans_type;
type ahb_sync_type is array (1 to 2) of pci_to_ahb_trans_type;
type pci_trace_sync_type is array (1 to 2) of apb_to_pci_trace_trans_type;
type apb_sync_type is array (1 to 2) of pci_trace_to_apb_trans_type;
type ahb_to_pci_map_type is array (0 to 15) of std_logic_vector(31 downto 0);
constant ahb_to_pci_map_none : ahb_to_pci_map_type := (others => (others => '0'));
-- Calculate AADDR_WIDTH for HMASK
function calc_aaddr_width(di : in integer) return integer is
variable bits : integer;
begin
if di = 16#800# then bits := 31;
elsif di = 16#c00# then bits := 30;
elsif di = 16#e00# then bits := 29;
elsif di = 16#f00# then bits := 28;
elsif di = 16#f80# then bits := 27;
elsif di = 16#fc0# then bits := 26;
elsif di = 16#fe0# then bits := 25;
elsif di = 16#ff0# then bits := 24;
elsif di = 16#ff8# then bits := 23;
elsif di = 16#ffc# then bits := 22;
elsif di = 16#ffe# then bits := 21;
elsif di = 16#fff# then bits := 20;
else bits := 4; end if;
return bits;
end function;
constant AADDR_WIDTH : integer := calc_aaddr_width(hmask);
type pci_reg_type is record
conf : pci_config_space_multi_type;-- Configuration Space
po : pci_reg_out_type; -- PCI output signals
m : pci_master_type; -- PCI Master
t : pci_target_type; -- PCI Target
pta_trans : pci_to_ahb_trans_type;-- Signals between PCI clock domain and AHB clock domain (need synchronisation)
sync : pci_sync_type;
pt : pci_trace_type;
ptta_trans: pci_trace_to_apb_trans_type;
pt_sync : pci_trace_sync_type;
pciinten : std_logic_vector(3 downto 0); -- Drives output enable for INTA..D
pci66 : std_logic_vector(1 downto 0);
debug : std_logic_vector(31 downto 0);
end record;
subtype AHB_FIFO_BITS is natural range FIFO_DEPTH + 1 downto 2;
type amba_master_state_type is (am_idle, am_read, am_write, am_error);
type amba_master_type is record
state : amba_master_state_type;
first : std_logic_vector(2 downto 0); -- First data in access (mark starting fifo)
done : std_logic_vector(2 downto 0);
stop : std_logic;
dmai0 : dma_ahb_in_type;
dma_hold : std_logic;
active : std_logic;
retry : std_logic;
retry_blen: std_logic_vector(15 downto 0);
retry_size: std_logic_vector(1 downto 0);
retry_offset: std_logic_vector(1 downto 0);
acc : ahb_master_acc_type; -- PCI target => AHB master accesses
hold : std_logic_vector(2 downto 0);
last : std_logic_vector(2 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
blen : std_logic_vector(15 downto 0);
end record;
constant amba_master_none : amba_master_type := (
am_idle, (others => '0'), (others => '0'), '0', dma_ahb_in_none, '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), ahb_master_acc_none, (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type amba_slave_state_type is (as_idle, as_checkpcimst, as_read, as_write, as_pcitrace);
type amba_slave_type is record
state : amba_slave_state_type;
atp : pci_fifo_type;
pta : pci_fifo_type;
hready : std_logic;
hwrite : std_logic;
hsel : std_logic;
hmbsel : std_logic_vector(0 to 2);
hresp : std_logic_vector(1 downto 0);
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
hburst : std_logic;
haddr : std_logic_vector(31 downto 0);
retry : std_logic;
first : std_logic; -- First access in transfer
firstf : std_logic; -- First fifo
pending : std_logic_vector(1 downto 0);
addr : std_logic_vector(31 downto 0);
offset : std_logic_vector(1 downto 0);
master : std_logic_vector(3 downto 0);
write : std_logic;
oneword : std_logic;
burst : std_logic;
config : std_logic;
io : std_logic;
size : std_logic_vector(2 downto 0);
start : std_logic;
hrdata : std_logic_vector(31 downto 0);
continue : std_logic;
discard : std_logic;
atp_map : ahb_to_pci_map_type;
io_map : std_logic_vector(31 downto 16);
cfg_bus : std_logic_vector(23 downto 16);
cfg_status: std_logic_vector(1 downto 0);
io_cfg_burst : std_logic_vector(1 downto 0); -- Alow burst on PCI IO / CONF
erren : std_logic; -- Enables AHB error response for Master/Target abort
parerren : std_logic; -- Enables AHB error response for PAR error
accbuf : pci_g_acc_trans_vector_type; -- AHB slave to PCI master access buffer
blen : std_logic_vector(7 downto 0); -- AHB slave prefetch burst length
blenmask : std_logic_vector(15 downto 0); -- AHB slave prefetch length AHB master mask
done_fifo : std_logic_vector(1 downto 0);
tb_ren : std_logic; -- PCI trace buffer read enable
fakehost : std_logic; -- Fake device in system slot (HOST)
stoppciacc: std_logic;
end record;
constant amba_slave_none : amba_slave_type := (
as_idle, pci_fifo_none, pci_fifo_none, '1', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', (others => '0'), '0', '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
(others => '0'), '0', (others => '0'), '0', '0', ahb_to_pci_map_none, (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', '0', pci_g_acc_trans_vector_none,
(others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
type irq_reg_type is record
device_mask : std_logic_vector(3 downto 0);
device_force : std_logic;
host_mask : std_logic_vector(3 downto 0);
host_status : std_logic_vector(3 downto 0);
host_pirq_vl : std_logic_vector(3 downto 0);
host_pirq_l : std_logic;
access_en : std_logic; -- Enables IRQ for Master/Target abort and PAR error
access_status: std_logic_vector(2 downto 0);
access_pirq : std_logic;
access_pirq_l: std_logic;
system_en : std_logic; -- Enables IRQ for System error
system_status: std_logic_vector(1 downto 0);
system_pirq : std_logic;
system_pirq_l: std_logic;
dma_pirq_l : std_logic;
irqen : std_logic;
end record;
constant irq_reg_none : irq_reg_type := (
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
'0', '0', (others => '0'), '0', '0', '0', (others => '0'), '0', '0', '0', '0');
type dma_state_type is (dma_idle, dma_read_desc, dma_next_channel, dma_write_status, dma_read, dma_write, dma_error);
type dma_desc_type is record
en : std_logic;
irqen : std_logic;
write : std_logic;
tw : std_logic;
desctype: std_logic_vector(1 downto 0);
cio : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
ch : std_logic_vector(31 downto 0);
nextch : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
nextdesc: std_logic_vector(31 downto 0);
cnt : std_logic_vector(15 downto 0);
emptych : std_logic;
chcnt : std_logic_vector(2 downto 0);
paddr : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
acctype : std_logic_vector(3 downto 0);
chid : std_logic_vector(2 downto 0);
end record;
constant dma_desc_none : dma_desc_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type dma_reg_type is record
state : dma_state_type;
dmai1 : dma_ahb_in_type;
desc : dma_desc_type;
dtp : pci_fifo_type;
ptd : pci_fifo_type;
rcnt : std_logic_vector(1 downto 0);
en : std_logic;
err : std_logic_vector(2 downto 0);
errlen : std_logic_vector(15 downto 0);
numch : std_logic_vector(2 downto 0);
dma_hold : std_logic_vector(2 downto 0);
dma_last : std_logic_vector(2 downto 0);
newfifo : std_logic;
active : std_logic;
done : std_logic_vector(1 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
first : std_logic_vector(2 downto 0);
retry : std_logic;
retry_len : std_logic_vector(15 downto 0);
addr : std_logic_vector(31 downto 0);
irq : std_logic;
irqen : std_logic;
irqstatus : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
errstatus : std_logic_vector(4 downto 0); -- DMA error status
irqch : std_logic_vector(7 downto 0); -- DMA Channel irq status
running : std_logic; -- DMA is running
end record;
constant dma_reg_none : dma_reg_type := (
dma_idle, dma_ahb_in_none, dma_desc_none, pci_fifo_none, pci_fifo_none,
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', (others => '0'), zero32(AHB_FIFO_BITS),
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type amba_reg_type is record
m : amba_master_type;
atp_trans : ahb_to_pci_trans_type;
sync : ahb_sync_type;
s : amba_slave_type;
irq : irq_reg_type;
dma : dma_reg_type;
atpt_trans: apb_to_pci_trace_trans_type;
apb_sync : apb_sync_type;
apb_pt_stat : std_logic_vector(31 downto 0);
apb_pr_conf_0_pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar (read only)
debug : std_logic_vector(31 downto 0);
debug_pr : std_logic_vector(31 downto 0);
debuga : std_logic_vector(31 downto 0);
end record;
constant REVISION : amba_version_type := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
-- APB DEBUG
constant tbpconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2_TB, 0, REVISION, 0),
1 => apb_iobar(tbpaddr, tbpmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, HIOMASK),
others => zero32);
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
signal pr, prin : pci_reg_type;
signal pi, piin : pci_in_type; -- Registered PCI signals.
signal pcirstout : std_logic; -- PCI reset
signal pciasyncrst, pciasyncrst_comb : std_logic; -- PCI asynchronous reset
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal pciinten,pciinten_pad : std_logic_vector(3 downto 0);
signal pcisig : std_logic_vector(16 downto 0);
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pr_pta_trans_gated : pci_to_ahb_trans_type; -- PCI Target => AHB Master pending gated with pcirst
signal tm_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal ms_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal tm_fifoo_pta : pci_fifo_out_type;
signal ms_fifoo_pta : pci_fifo_out_type;
signal md_fifoo_dtp : pci_fifo_out_type; -- DMA FIFO output data
signal md_fifoo_ptd : pci_fifo_out_type;
signal pt_fifoo_ad : pci_fifo_out_type; -- PCI trace output data
signal pt_fifoo_sig : pci_fifo_out_type;
-- Scan test support
signal scanen : std_logic;
signal testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
signal scan_prin_t_atp_ctrl_en : std_logic;
signal scan_ar_m_acc_fifo_wen : std_logic;
signal scan_arin_m_acc_fifo_ren : std_logic;
signal scan_pr_t_pta_ctrl_en : std_logic;
signal scan_prin_m_acc_acc_sel_ahb_fifo_ren : std_logic;
signal scan_ar_s_atp_ctrl_en : std_logic;
signal scan_arin_s_pta_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_ahb_fifo_wen : std_logic;
signal scan_prin_m_acc_acc_sel_dma_fifo_ren : std_logic;
signal scan_ar_dma_dtp_ctrl_en : std_logic;
signal scan_arin_dma_ptd_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_dma_fifo_wen : std_logic;
signal scan_tb_ren : std_logic;
signal scan_pr_ptta_trans_enable : std_logic;
signal tb_addr : std_logic_vector(31 downto 0); -- Trace Buffer address
signal tb_ren : std_logic; -- Trace Buffer read enable
signal ar, arin : amba_reg_type;
signal dmao0, dmao1 : dma_ahb_out_type;
signal disabled_dmai : dma_ahb_in_type;
signal ahbmo_con : ahb_mst_out_type; -- Connect AHB-master to ahbmo
signal lpcim_rst, lpcit_rst, lpci_rst: std_ulogic;
signal lahbm_rst, lahbs_rst, lahb_rst: std_ulogic;
signal iotmdin: std_logic_vector(45 downto 0);
signal iotmdout: std_logic_vector(44 downto 0);
signal iotmact, iotmoe: std_ulogic;
attribute sync_set_reset of lpcim_rst : signal is "true";
attribute sync_set_reset of lpcit_rst : signal is "true";
attribute sync_set_reset of lpci_rst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
--attribute sync_set_reset of rst : signal is "true";
attribute sync_set_reset of lahbm_rst : signal is "true";
attribute sync_set_reset of lahbs_rst : signal is "true";
attribute sync_set_reset of lahb_rst : signal is "true";
type bar_size_type is array (0 to 5) of integer range 0 to 31;
constant func0_bar_size : bar_size_type := (bar0, bar1, bar2, bar3, bar4, bar5);
constant func1_bar_size : bar_size_type := (mf1_bar0, mf1_bar1, mf1_bar2, mf1_bar3, mf1_bar4, mf1_bar5);
constant none_bar_size : bar_size_type := (0, 0, 0, 0, 0, 0);
type bar_size_vector_type is array (0 to 7) of bar_size_type;
constant bar_size : bar_size_vector_type := (func0_bar_size, func1_bar_size, none_bar_size, none_bar_size,
none_bar_size, none_bar_size, none_bar_size, none_bar_size);
constant func0_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(bartype,16);
constant func1_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(mf1_bartype,16);
constant func0_bar_prefetch : std_logic_vector(5 downto 0) := func0_bar_type(5 downto 0);
constant func1_bar_prefetch : std_logic_vector(5 downto 0) := func1_bar_type(5 downto 0);
type bar_prefetch_vector_type is array (0 to 7) of std_logic_vector(5 downto 0);
constant bar_prefetch : bar_prefetch_vector_type := (func0_bar_prefetch, func1_bar_prefetch, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
constant func0_bar_io : std_logic_vector(5 downto 0) := func0_bar_type(13 downto 8);
constant func1_bar_io : std_logic_vector(5 downto 0) := func1_bar_type(13 downto 8);
constant bar_io : bar_prefetch_vector_type := (func0_bar_io, func1_bar_io, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type conf_int_vector_type is array (0 to 7) of integer;
constant deviceid_vector : conf_int_vector_type := (deviceid, mf1_deviceid, 0, 0, 0, 0, 0, 0);
constant classcode_vector : conf_int_vector_type := (classcode, mf1_classcode, 0, 0, 0, 0, 0, 0);
constant revisionid_vector : conf_int_vector_type := (revisionid, mf1_revisionid, 0, 0, 0, 0, 0, 0);
constant cap_pointer_vector : conf_int_vector_type := (cap_pointer, mf1_cap_pointer, 0, 0, 0, 0, 0, 0);
constant ext_cap_pointer_vector : conf_int_vector_type := (ext_cap_pointer, mf1_ext_cap_pointer, 0, 0, 0, 0, 0, 0);
constant extcfg_vector : conf_int_vector_type := (extcfg, mf1_extcfg, 0, 0, 0, 0, 0, 0);
type conf_vector16_vector_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant masters_vector : conf_vector16_vector_type := (conv_std_logic_vector(masters, 16), conv_std_logic_vector(mf1_masters, 16),
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
constant deviceirq_vector : conf_int_vector_type := (1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq,
1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq);
type default_bar_map_type is array (0 to 7) of pci_bars_type;
constant default_bar_map : default_bar_map_type := ((conv_std_logic_vector(bar0_map, 24)&x"00", conv_std_logic_vector(bar1_map, 24)&x"00",
conv_std_logic_vector(bar2_map, 24)&x"00", conv_std_logic_vector(bar3_map, 24)&x"00",
conv_std_logic_vector(bar4_map, 24)&x"00", conv_std_logic_vector(bar5_map, 24)&x"00"),
(conv_std_logic_vector(mf1_bar0_map, 24)&x"00", conv_std_logic_vector(mf1_bar1_map, 24)&x"00",
conv_std_logic_vector(mf1_bar2_map, 24)&x"00", conv_std_logic_vector(mf1_bar3_map, 24)&x"00",
conv_std_logic_vector(mf1_bar4_map, 24)&x"00", conv_std_logic_vector(mf1_bar5_map, 24)&x"00"),
pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none);
function blenmask_size(barminsize : in integer)
return integer is
variable res : integer;
begin
res := 16;
if barminsize < 16 then res := barminsize; end if;
return (res - 1);
end function;
function set_pta_addr(paddr : in std_logic_vector(31 downto 0);
pta_map : in pci_bars_type;
bar : in std_logic_vector(5 downto 0);
bar_mask: in pci_bars_type;
barminsize : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := paddr;
for i in 0 to 5 loop
if bar(i) = '1' then
res(31 downto barminsize) := (pta_map(i)(31 downto barminsize) and bar_mask(i)(31 downto barminsize)) or
(paddr(31 downto barminsize) and not bar_mask(i)(31 downto barminsize));
end if;
end loop;
return res;
end function;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
function set_cbe_from_size_addr(size : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(1 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(3 downto 0);
begin
if twist = '1' then
if size = "000" then -- byte
case addr is
when "11" => res := "0111";
when "10" => res := "1011";
when "01" => res := "1101";
when others => res := "1110";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "0011";
when others => res := "1100";
end case;
else
res := "0000";
end if;
else
if size = "000" then -- byte
case addr is
when "11" => res := "1110";
when "10" => res := "1101";
when "01" => res := "1011";
when others => res := "0111";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "1100";
when others => res := "0011";
end case;
else
res := "0000";
end if;
end if;
return res;
end function;
function set_atp_addr(haddr : in std_logic_vector(31 downto 0);
atp_map : in ahb_to_pci_map_type;
hmaster : in std_logic_vector(3 downto 0);
size : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer;
begin
i := conv_integer(hmaster);
res := haddr;
if AADDR_WIDTH /= 4 then
res(31 downto size) := atp_map(i)(31 downto size);
end if;
return res;
end function;
function set_pci_conf_addr(addr : in std_logic_vector(31 downto 0);
cfg_bus : in std_logic_vector(23 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer range 0 to 21;
begin
res := (others => '0');
i := conv_integer(addr(15 downto 11));
if cfg_bus = zero32(23 downto 16) then -- Type 0 config
if i /= 0 then
res(10 + i) := '1';
end if;
res(10 downto 2) := addr(10 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '0'; -- Type
else -- Type 1 config
res(23 downto 16) := cfg_bus;
res(15 downto 2) := addr(15 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '1'; -- Type
end if;
return res;
end function;
function set_pci_io_addr(addr : in std_logic_vector(31 downto 0);
io_map : in std_logic_vector(31 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := io_map & addr(15 downto 0);
return res;
end function;
function set_pci_io_byte_addr(addr : in std_logic_vector(1 downto 0);
size : in std_logic_vector(2 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then
res := addr;
else
if size = "010" then
res := "00";
elsif size = "001" then
case addr is
when "00" => res := "10";
when others => res := "00";
end case;
else
case addr is
when "00" => res := "11";
when "01" => res := "10";
when "10" => res := "01";
when "11" => res := "00";
when others => res := "00";
end case;
end if;
end if;
return res;
end function;
begin
-- PHY =>
pciphy0 : grpci2_phy_wrapper
generic map(tech => memtech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotmdout,
iotdin => iotmdin
);
phyi.pciasyncrst <= pciasyncrst;
phyi.pcisoftrst <= sig_soft_rst;
phyi.pcirstout <= pcirstout;
phyi.pciinten <= pciinten_pad;
phyi.m_request <= sig_m_request;
phyi.m_mabort <= sig_m_mabort;
phyi.pr_m_fstate <= pr.m.fstate;
phyi.pr_m_cfifo <= pr.m.cfifo;
phyi.pv_m_cfifo <= prin.m.cfifo;
phyi.pr_m_addr <= pr.m.addr;
phyi.pr_m_cbe_data <= pr.m.cbe_data;
phyi.pr_m_cbe_cmd <= pr.m.cbe_cmd;
phyi.pr_m_first <= pr.m.first(1 downto 0);
phyi.pv_m_term <= prin.m.term(1 downto 0);
phyi.pr_m_ltimer <= pr.m.ltimer;
phyi.pr_m_burst <= pr.m.burst;
phyi.pr_m_abort <= pr.m.abort(0 downto 0);
phyi.pr_m_perren <= pr.m.perren(0 downto 0);
phyi.pr_m_done_fifo <= pr.m.done_fifo;
phyi.t_abort <= sig_t_abort;
phyi.t_ready <= sig_t_ready;
phyi.t_retry <= sig_t_retry;
phyi.pr_t_state <= pr.t.state;
phyi.pv_t_state <= prin.t.state;
phyi.pr_t_fstate <= pr.t.fstate;
phyi.pr_t_cfifo <= pr.t.cfifo;
phyi.pv_t_diswithout <= prin.t.diswithout;
phyi.pr_t_stoped <= pr.t.stoped;
phyi.pr_t_lcount <= pr.t.lcount;
phyi.pr_t_first_word <= pr.t.first_word;
phyi.pr_t_cur_acc_0_read <= pr.t.cur_acc(0).read;
phyi.pv_t_hold_write <= prin.t.hold_write;
phyi.pv_t_hold_reset <= prin.t.hold_reset;
phyi.pr_conf_comm_perren <= sig_pr_conf_comm_perren;
phyi.pr_conf_comm_serren <= sig_pr_conf_comm_serren; -- SERR# only asserted for address parity error
phyi.testen <= ahbsi.testen when scantest=1 else '0';
phyi.testoen <= ahbsi.testoen;
phyi.testrst <= ahbsi.testrst;
pcirst <= (others => phyo.pcirsto(0));
pi <= phyo.pio;
po <= phyo.poo;
-- PHY <=
disabled_dmai <= ('0', '0', (others => '0'), (others => '0'), (others => '0'), '0', '0');
scanen <= (ahbsi.testen and ahbsi.scanen) when (scantest = 1) else '0';
testin <= ahbsi.testen & "0" & ahbsi.testin(TESTIN_WIDTH-3 downto 0);
pciasyncrst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else pcii.rst;
pciasyncrst_comb <= pcii.rst; -- Version used in comb logic, don't mux in testrst
hostrst2 : if hostrst = 2 generate
pcirstout <= rst and not ar.atp_trans.rst(2);
end generate;
hostrst1 : if hostrst = 1 generate
pcirstout <= rst and not ar.atp_trans.rst(2) when pcii.host = '0' else '1';
end generate;
hostrst0 : if hostrst = 0 generate
pcirstout <= '1';
end generate;
-- Propagate PCI reset to AMBA for peripheral devices
ptarst <= pcii.rst when pcii.host = '1' and hostrst /= 2 else '1';
-- PCI trace signal
pcisig <= pi.cbe &
pi.frame & pi.irdy & pi.trdy & pi.stop &
pi.devsel & pi.par & pi.perr & pi.serr &
pi.idsel & pr.po.req & pi.gnt & pi.lock &
pi.rst; -- & "000";
pcomb : process(pr, pi, pcirst(0), pcii, ar.atp_trans, tm_fifoo_atp, ms_fifoo_atp, md_fifoo_dtp, pcirstout, pciinten, pcisig, ar.atpt_trans,
phyo, pciasyncrst_comb, lpcim_rst, lpcit_rst, lpci_rst, iotmact)
variable pv : pci_reg_type;
variable atp_trans : ahb_to_pci_trans_type;
variable pci : pci_in_type;
variable t_hit : std_logic; -- Target bar address match
variable t_chit : std_logic; -- Target configuration space hit
variable t_bar : std_logic_vector(5 downto 0); -- PCI bar with hit
variable t_func : integer range 0 to multifunc;
variable t_ready : std_logic; -- Backend ready to send/receive data
variable t_abort : std_logic; -- Stop PCI access
variable t_retry : std_logic; -- Stop PCI access
variable t_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable t_cad : std_logic_vector(31 downto 0); -- Data from PCI Configuration Space Header
variable conf_func : integer range 0 to 7;
variable all_func_serren : std_logic;
variable t_acc_type : std_logic_vector(1 downto 0);
variable t_acc_impcfgreg: std_logic;
variable t_acc_burst: std_logic;
variable t_acc_read : std_logic;
variable tm_acc_pending : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_acc_done : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
-- PCI master
variable m_request : std_logic;
variable m_ready : std_logic;
variable m_mabort : std_logic; -- Master abort
variable m_tabort : std_logic; -- Target abort
variable m_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable m_func : integer range 0 to multifunc;
variable acc : pci_master_acc_type;
variable accdone : std_logic; -- Renamed to be synthesized with XST
variable acc_cancel : std_logic;
variable acc_switch : std_logic;
variable fifo : pci_g_fifo_trans_vector_type;
variable fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable msd_acc : pci_g_acc_trans_multi_type;
variable ms_acc_pending : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable md_acc_pending : std_logic;
variable md_acc_done : std_logic;
variable md_acc_cancel : std_logic;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- PCI trace
variable pt_start : std_logic;
variable pt_stop : std_logic;
variable atpt_trans : apb_to_pci_trace_trans_type;
variable pt_setup : apb_to_pci_trace_trans_type;
constant z : std_logic_vector(48 downto 0) := (others => '0');
-- Soft reset
variable pci_target_rst : std_logic;
variable pci_master_rst : std_logic;
variable pci_hard_rst : std_logic;
begin
-- --------------------------------------------------------------------------------
-- Global defaults
-- --------------------------------------------------------------------------------
-- Defaults
pv := pr;
pv.pta_trans.ca_host := pcii.host;
pv.pci66(0) := pcii.pci66; pv.pci66(1) := pr.pci66(0);
-- FIFO and PCI<=>AHB sync
pv.sync(1) := ar.atp_trans; pv.sync(2) := pr.sync(1);
if nsync = 0 then atp_trans := ar.atp_trans;
else atp_trans := pr.sync(nsync); end if;
-- PCI soft reset
pv.pta_trans.rst_ack(0) := atp_trans.rst(0);
pv.pta_trans.rst_ack(1) := atp_trans.rst(1);
pci_target_rst := not pr.pta_trans.rst_ack(0) and (pr.pta_trans.rst_ack(0) xor atp_trans.rst(0));
pci_master_rst := not pr.pta_trans.rst_ack(1) and (pr.pta_trans.rst_ack(1) xor atp_trans.rst(1));
pci_hard_rst := atp_trans.rst(2);
pci := phyo.pciv;
if (pr.po.perr = '0' -- Parity Error detected
and (pr.m.perren /= "00")) then -- During master read
pv.conf(pr.m.acc(pr.m.acc_sel).func).stat.dpe := '1';
end if;
if (pr.po.perr = '0' -- Parity Error detected
and ((pr.t.state = pt_s_data or pr.t.state = pt_turn_ar) and pr.t.cur_acc(0).read = '0')) -- Write to target
or (pr.t.addr_perr = '1') then -- Parity Error in Address phase
pv.conf(pr.t.cur_acc(0).func).stat.dpe := '1';
end if;
-- Signaled System Error
for j in 0 to multifunc loop
if pr.conf(j).comm.perren = '1' and pr.conf(j).comm.serren = '1' and pr.po.serren = oeon then
pv.conf(j).stat.sse := '1';
end if;
end loop;
-- SERR to AHB
if atp_trans.pa_serr_rst = '1' then
pv.pta_trans.pa_serr := '1';
elsif pi.serr = '0' then
pv.pta_trans.pa_serr := '0';
end if;
-- --------------------------------------------------------------------------------
-- PCI master defaults
-- --------------------------------------------------------------------------------
-- Default
m_request := '0';
m_ready := '0';
m_ready := '1';
pv.m.fifo_switch := '0';
pv.m.acc(0).fifo_ren := '0'; -- read enable [AHB]
pv.m.acc(0).fifo_wen := '0'; -- write enable [AHB]
pv.m.acc(1).fifo_ren := '0'; -- read enable [DMA]
pv.m.acc(1).fifo_wen := '0'; -- write enable [DMA]
pv.m.fifo_wdata := byte_twist(pi.ad, pr.m.twist);
pv.m.framedel := pr.po.frame;
ms_acc_pending := atp_trans.msd_acc(0).pending xor pr.pta_trans.msd_acc_ack(0);
ms_acc_done := atp_trans.msd_acc_done_ack(0) xor pr.pta_trans.msd_acc_done(0).done;
ms_acc_cancel := atp_trans.msd_acc_cancel(0) xor pr.pta_trans.msd_acc_cancel_ack(0)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(0)(1) := pr.pta_trans.msd_acc_cancel_ack(0)(0);
pv.pta_trans.msd_acc_cancel_ack(0)(2) := pr.pta_trans.msd_acc_cancel_ack(0)(1);
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := atp_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (pr.pta_trans.msd_fifo(0)(i).pending(0) xor atp_trans.msd_fifo_ack(0)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(0)(i).pending(1) := pr.pta_trans.msd_fifo(0)(i).pending(0);
pv.pta_trans.msd_fifo(0)(i).pending(2) := pr.pta_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := ar.atp_trans.msd_fifo(0);
msd_acc(0) := ar.atp_trans.msd_acc(0);
md_acc_pending := atp_trans.msd_acc(1).pending xor pr.pta_trans.msd_acc_ack(1);
md_acc_done := atp_trans.msd_acc_done_ack(1) xor pr.pta_trans.msd_acc_done(1).done;
md_acc_cancel := atp_trans.msd_acc_cancel(1) xor pr.pta_trans.msd_acc_cancel_ack(1)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(1)(1) := pr.pta_trans.msd_acc_cancel_ack(1)(0);
pv.pta_trans.msd_acc_cancel_ack(1)(2) := pr.pta_trans.msd_acc_cancel_ack(1)(1);
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := atp_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (pr.pta_trans.msd_fifo(1)(i).pending(0) xor atp_trans.msd_fifo_ack(1)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(1)(i).pending(1) := pr.pta_trans.msd_fifo(1)(i).pending(0);
pv.pta_trans.msd_fifo(1)(i).pending(2) := pr.pta_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := ar.atp_trans.msd_fifo(1);
msd_acc(1) := ar.atp_trans.msd_acc(1);
-- PCI master function
m_func := pr.m.acc(pr.m.acc_sel).func;
-- --------------------------------------------------------------------------------
-- PCI master core
-- --------------------------------------------------------------------------------
if master /= 0 or dma /= 0 then -- PCI master enabled
-- First
if pr.m.state = pm_idle or pr.m.state = pm_turn_ar or pr.m.state = pm_dr_bus then
pv.m.first(0) := '1';
else
pv.m.first(0) := '0';
end if;
pv.m.first(1) := pr.m.first(0);
-- Master Data Parity Error
if pr.m.state = pm_m_data then
if pr.m.fstate = pmf_read then
pv.m.perren(0) := '1';
elsif pr.m.fstate = pmf_fifo then
pv.m.detectperr(0) := '1';
end if;
else
pv.m.perren(0) := '0';
pv.m.detectperr(0) := '0';
end if;
pv.m.perren(1) := pr.m.perren(0);
pv.m.detectperr(1) := pr.m.detectperr(0);
if pr.conf(m_func).comm.perren = '1' and -- Parity error response bit[6] = 1
((pr.m.perren /= "00" and pr.po.perr = '0') -- Parity error is signaled by master on read
or (pr.m.detectperr(1) = '1' and pci.perr = '0')) then-- Parity error is signaled by target on write
pv.conf(m_func).stat.mdpe := '1';
pv.m.acc(pr.m.acc_sel).status(0) := '1';
end if;
-- PCI master latency timer
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.ltimer := pr.conf(m_func).ltimer;
elsif pr.m.ltimer /= x"00" and pr.po.frame = '0' then
pv.m.ltimer := pr.m.ltimer - 1;
end if;
-- Devsel time out counter (and master abort signaling)
if pci.devsel = '0' then pv.m.devsel_asserted := '1'; end if;
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.devsel_tout := "100";
pv.m.devsel_asserted := '0';
elsif pr.m.devsel_asserted = '1' then
pv.m.devsel_tout := "100";
elsif pr.m.devsel_tout /= "000" then
pv.m.devsel_tout := pr.m.devsel_tout - 1;
end if;
if (pr.m.devsel_tout = "000" and pr.m.devsel_asserted = '0') and pi.devsel = '1' and pr.m.state = pm_m_data then m_mabort := '1'; pv.conf(m_func).stat.rma := '1'; else m_mabort := '0'; end if; -- Master abort -- delayed mabort one cycle (to reduce pci.devsel timing path)
if pi.devsel = '1' and pi.stop = '0' and pr.m.state = pm_s_tar then m_tabort := '1'; pv.conf(m_func).stat.rta := '1'; else m_tabort := '0'; end if; -- Target abort
if (pr.m.state = pm_m_data and m_mabort = '1') or (pr.m.state = pm_s_tar and m_tabort = '1') then
pv.m.abort(0) := '1';
pv.m.abort(1) := m_tabort;
elsif pr.m.state = pm_s_tar or pr.m.state = pm_idle or pr.m.state = pm_dr_bus then
pv.m.abort := (others => '0');
end if;
if pr.m.abort(0) = '1' then pv.m.abort(0) := '0'; end if;
-- Access acknowledge and arbitration [AHB/DMA]
for i in 0 to 1*dma loop
if ((ms_acc_pending = '1' and i = acc_sel_ahb) or (md_acc_pending = '1' and i = acc_sel_dma)) and pr.m.acc(i).pending = '0' then
pv.pta_trans.msd_acc_ack(i) := atp_trans.msd_acc(i).pending;
pv.m.acc(i).pending := '1';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).done := (others => '0');
pv.m.acc(i).status := (others => '0');
pv.m.acc(i).first := '1';
pv.m.acc(i).addr := msd_acc(i).addr(31 downto 2) & "00";
pv.m.acc(i).func := conv_integer(msd_acc(i).func);
pv.m.acc(i).cmd := msd_acc(i).acctype;
pv.m.acc(i).mode := msd_acc(i).accmode;
pv.m.acc(i).fifo_index := msd_acc(i).index;
if msd_acc(i).acctype(0) = '1' then
pv.m.acc(i).length := (others => '0');
else
pv.m.acc(i).length := msd_acc(i).length;
end if;
if msd_acc(i).acctype = CONF_READ or msd_acc(i).acctype = CONF_WRITE then -- Config
if i = acc_sel_ahb then pv.m.acc(i).endianess := '1'; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr := msd_acc(i).addr; -- PCI CONF address set in AHB slave
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), '1'); -- Set CBE depending on AHB size and address
elsif msd_acc(i).acctype = IO_READ or msd_acc(i).acctype = IO_WRITE then -- IO
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr(1 downto 0) := set_pci_io_byte_addr(msd_acc(i).offset(1 downto 0), msd_acc(i).size, pr.pta_trans.ca_twist); -- PCI IO used byte address
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
else -- Mem
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '1' then -- Status pending
if pr.m.acc(i).done(2 downto 1) = "10" then
if (i = acc_sel_ahb and ms_fifo_pending(pr.m.acc(i).fifo_index) = '1') or (i = acc_sel_dma and md_fifo_pending(pr.m.acc(i).fifo_index) = '1') then
if pr.m.acc(i).fifo_index /= FIFO_COUNT-1 then pv.m.acc(i).fifo_index := pr.m.acc(i).fifo_index + 1;
else pv.m.acc(i).fifo_index := 0; end if;
pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index) := not pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index);
if (i = acc_sel_ahb and ms_fifo(pr.m.acc(i).fifo_index).lastf = '1') or (i = acc_sel_dma and md_fifo(pr.m.acc(i).fifo_index).lastf = '1') then
pv.m.acc(i).done(1) := '1';
end if;
end if;
elsif ((ms_acc_done = '0' and i = acc_sel_ahb) or (md_acc_done = '0' and i = acc_sel_dma)) then
pv.pta_trans.msd_acc_done(i).done := not pr.pta_trans.msd_acc_done(i).done;
pv.pta_trans.msd_acc_done(i).status(2 downto 0) := pr.m.acc(i).status;
if pr.m.acc(i).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(i).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(i).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(i).count := pr.m.acc(i).length;
pv.m.acc(i).pending := '0';
end if;
end if;
-- Access canceled
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active = "10" and pr.m.acc(i).cmd(0) = '0' then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(i).done(0) := '1';
pv.m.acc(i).active(1) := '0';
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '0' then -- Status pending
if pr.m.acc(i).done(1 downto 0) = "01" then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(pr.m.acc_sel).done(1) := '1';
for j in 0 to FIFO_COUNT-1 loop
if (i = acc_sel_ahb and ms_fifo_empty(j) = '0') or (i = acc_sel_dma and md_fifo_empty(j) = '0') then
pv.pta_trans.msd_fifo(i)(j).pending(0) := not pr.pta_trans.msd_fifo(i)(j).pending(0);
else
pv.pta_trans.msd_fifo(i)(j).pending(0) := pr.pta_trans.msd_fifo(i)(j).pending(0);
end if;
end loop;
end if;
else
pv.pta_trans.msd_acc_cancel_ack(i)(0) := atp_trans.msd_acc_cancel(i);
pv.m.acc(i).pending := '0';
end if;
end if;
end loop;
-- control access switching
if atp_trans.mstswdis = '0' then
if (pr.m.acc_sel = acc_sel_dma and pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
or
(pr.m.acc_sel = acc_sel_ahb and pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
then
if pr.m.acc_cnt = MST_ACC_CNT then
pv.m.acc_switch := '1';
end if;
end if;
else
pv.m.acc_switch := '0';
end if;
acc_switch := pv.m.acc_switch;
if ((pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ms_acc_cancel = '0' and pr.m.acc(1).active(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
and not (pr.m.acc_switch = '1' and pr.m.acc_sel = acc_sel_ahb))
or pr.m.acc(0).active(0) = '1' then
acc := pr.m.acc(0);
accdone := ms_acc_done;
acc_cancel := ms_acc_cancel;
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := ms_fifo_pending;
fifo_empty := ms_fifo_empty;
fifo := ms_fifo;
if pr.m.acc_sel = acc_sel_dma then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
elsif (pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and md_acc_cancel = '0' and pr.m.acc(0).active(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
or pr.m.acc(1).active(0) = '1' then
acc := pr.m.acc(1);
accdone := md_acc_done;
acc_cancel := md_acc_cancel;
pv.m.acc_sel := acc_sel_dma;
fifo_pending := md_fifo_pending;
fifo_empty := md_fifo_empty;
fifo := md_fifo;
if pr.m.acc_sel = acc_sel_ahb then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
else
acc := pci_master_acc_none;
accdone := '0';
acc_cancel := '0';
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := (others => '0');
fifo_empty := (others => '0');
fifo := ms_fifo;
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
if acc.fifo_index /= FIFO_COUNT-1 then fifo_nindex := (acc.fifo_index + 1);
else fifo_nindex := 0; end if;
-- FIFO state machine
case pr.m.fstate is
when pmf_idle =>
pv.m.waitonstop := '0';
pv.m.done := '0';
pv.m.done_fifo := '0';
pv.m.done_trans := '0';
pv.m.term := (others => '0');
pv.m.preload := '0';
pv.m.preload_count := (others => '0');
pv.m.afull := '0';
pv.m.afullcnt := (others => '0');
if acc.pending = '1' then
pv.m.addr := acc.addr;
pv.m.twist := acc.endianess;
pv.m.cbe_cmd := acc.cmd;
pv.m.cbe_data := acc.cbe;
pv.m.burst := acc.mode(0);
pv.m.acc_cnt := 0;
if acc.cmd(0) = '1' then -- Write access
pv.m.fstate := pmf_fifo;
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & fifo(acc.fifo_index).start; -- Set fifo start address
else -- Read access
pv.m.fstate := pmf_read;
end if;
pv.m.acc(pv.m.acc_sel).active := "11";
end if;
when pmf_fifo =>
pv.m.acc(pr.m.acc_sel).fifo_ren := fifo_pending(acc.fifo_index);
if pr.m.term = "00" and pr.m.last(0) = '0' and pr.m.done = '0' and (pr.m.cfifo(0).valid = '1' or pr.m.hold(0) = '1')
and m_mabort = '0' and pr.m.abort(0) = '0' then -- request bus if not: latency timer count out; last data phase; transfer done
m_request := '1';
end if;
if (fifo_pending(acc.fifo_index) = '1') and pr.m.done = '0' then -- preload data
pv.m.preload := '1';
pv.m.hold_fifo := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or pr.m.preload = '1' or (pr.m.abort(0)) = '1' then
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.preload = '1' then
if pr.m.cfifo(0).valid = '0' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.cfifo(0).valid = '1' and pr.m.cfifo(1).valid = '0' then
pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
end if;
end if;
if pr.m.acc(0).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(ms_fifoo_atp.data, acc.endianess); -- shifting in data from backend fifo
elsif pr.m.acc(1).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(md_fifoo_dtp.data, acc.endianess); -- shifting in data from DMA fifo
end if;
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
if pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = fifo(acc.fifo_index).stop then -- Mark last word
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DAM/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo_ack(pr.m.acc_sel)(acc.fifo_index) := fifo(acc.fifo_index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
pv.m.fifo_addr := conv_std_logic_vector(fifo_nindex, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- New fifo address (should be ok with [index & zero] or & fifo(fifo_nindex).start)
if fifo_pending(fifo_nindex) = '0' or acc_switch = '1' then -- If no fifo pending => idle
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
if fifo(acc.fifo_index).lastf = '1' then -- Last fifo, transfer is done
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
pv.m.done_trans := '1';
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
pv.m.fifo_addr(FIFO_DEPTH-1 downto 0) := pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
pv.m.cfifo(2).stlast := '0';
if fifo_pending(acc.fifo_index) = '1' and pr.m.done_fifo = '0' then -- Adding valid data to CFIFO
pv.m.cfifo(2).valid := '1';
else
pv.m.cfifo(2).valid := '0';
pv.m.cfifo(2).last := '0';
pv.m.cfifo(2).stlast := '0';
pv.m.cfifo(2).hold := '0';
end if;
end if;
if (pv.m.cfifo(0).valid = '1' and pv.m.cfifo(1).valid = '1' and pv.m.cfifo(2).valid = '1')
or (pv.m.cfifo(0).valid = '1' and pr.m.done_fifo = '1' and not (pv.m.cfifo(1).valid = '0' and pv.m.cfifo(2).valid = '1')) then
pv.m.preload := '0';
if pr.m.cfifo(0).hold = '1' and pv.m.cfifo(1).valid = '1' then pv.m.cfifo(0).hold := '0'; end if;
if pr.m.cfifo(1).hold = '1' and pv.m.cfifo(2).valid = '1' then pv.m.cfifo(1).hold := '0'; end if;
end if;
if pr.m.abort(0) = '1' then -- Empty core FIFO on master/target abort
for i in 0 to 2 loop
pv.m.cfifo(i).valid := '0';
end loop;
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' and pr.m.abort(0) = '0' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length + 1;
end if;
if pr.m.last(1) = '1' or pr.m.abort(0) = '1' then pv.m.done := '1'; end if; -- Last data phase is done => transfer done
-- Signal ERROR to AHB
if pr.m.abort(0) = '1' then
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- Error
pv.m.acc(pr.m.acc_sel).status(2 downto 1) := (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort); -- Error type: Master abort, Target abort, (PAR error)
end if;
end if;
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.term := (others => '0'); m_request := '0';
end if;
if pr.m.done = '1' then
pv.m.fstate := pmf_idle;
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if pr.m.done_trans = '1' or acc.done(2) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
pv.m.acc(pr.m.acc_sel).done(0) := '1';
if pr.m.done_trans = '1' then pv.m.acc(pr.m.acc_sel).done(1) := '1'; end if;
if accdone = '0' and pr.m.done_trans = '1' then
pv.pta_trans.msd_acc_done(pr.m.acc_sel).done := not pr.pta_trans.msd_acc_done(pr.m.acc_sel).done;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(2 downto 0) := pv.m.acc(pr.m.acc_sel).status; -- use pv.. (par error detection)
if pr.m.acc(pr.m.acc_sel).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).count := pr.m.acc(pr.m.acc_sel).length;
pv.m.acc(pr.m.acc_sel).pending := '0';
end if;
end if;
end if;
if pi.stop = '0' and pr.m.state /= pm_idle then m_request := '0'; end if; -- Second deasserted req cycle
when pmf_read =>
if pr.m.term(0) = '0' and m_mabort = '0' and pr.m.abort(0) = '0' and (pi.stop = '1' or pr.m.first(0) = '1') and pr.m.waitonstop = '0' then -- request bus if not: latency timer count out; no empty fifo to fill
m_request := '1'; -- request should be deasserted earlier
end if;
if pr.m.burst = '0' then -- Single access, only one data phase
if pr.po.frame = '0' then
pv.m.term(0) := '1';
elsif (pi.trdy and not pi.stop) = '1' then -- retry
pv.m.term := (others => '0');
end if;
end if;
if (pi.irdy or pi.trdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar)then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length - 1;
end if;
if pr.m.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) or pr.m.burst = '0' or (acc.mode(1) = '1' and acc.length = x"0000") then
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DMA/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
if (acc.mode(1) = '1' and acc.length = x"0000") or pr.m.burst = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '0';
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := (others => '0');
end if;
pv.m.acc(pr.m.acc_sel).fifo_wen := '1';
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & pr.m.addr(AHB_FIFO_BITS);
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pv.m.fifo_addr(FIFO_DEPTH-1 downto 0);
if ((fifo_empty(fifo_nindex) = '0' or acc_switch = '1') and pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 3), FIFO_DEPTH)) -- terminate access when 3 words left to store in FIFO or 3 word left i transfer
or (acc.mode(1) = '1' and acc.length = x"0002") then
pv.m.term(0) := '1';
pv.m.afull := '1'; -- almost full
pv.m.afullcnt := "00"; -- reset full counter
end if;
if pr.m.afull = '1' then -- when transfer is terminated, count data phases (1 - 3)
if pr.m.afullcnt = "01" then
pv.m.afullcnt := (others => '0');
pv.m.afull := '0';
else
pv.m.afullcnt := pr.m.afullcnt + 1;
end if;
end if;
end if;
if (pr.m.afull = '1' and pr.m.afullcnt = "01" and pr.m.first(0) = '1' and pr.m.state = pm_addr)
or (pr.m.afull = '1' and pr.m.afullcnt = "00" and pr.m.state = pm_m_data) -- terminate first or second data phase depending on space left in fifo
or (acc.mode(1) = '1' and ((acc.length = x"0000" and pr.m.state = pm_addr) or (acc.length = x"0001" and pr.m.state = pm_m_data)))then pv.m.term(0) := '1'; end if; -- DMA 1 or 2 word to complete transfer
if pr.m.term(0) = '1' and fifo_empty(acc.fifo_index) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus) then
pv.m.term := (others => '0'); -- Start new access when a fifo becomes empty
end if;
if pr.m.state = pm_s_tar and fifo_empty(acc.fifo_index) = '1' and pv.m.fifo_switch = '0' then pv.m.term(0) := '0'; end if; -- If disconnected, rerequest the bus if fifo is available (but not if fifo switch)
if (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar) and pi.irdy = '0' and (pi.trdy = '0' or (pi.stop = '0' and pi.devsel = '1')) then pv.m.first_word := '0'; end if;
if (acc.done(0) = '1' and (pv.m.first_word = '0' or acc.done(2) = '1'))
or ((pr.m.acc_switch = '1' or fifo_empty(acc.fifo_index) = '0') and pr.m.fifo_switch = '1') then -- Transfer read is done (or no empty fifo), cancelled or access arbitration
m_request := '0';
pv.m.term(0) := '1';
if ((pi.frame and pi.irdy) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus)) then
pv.m.fstate := pmf_idle;
pv.m.term := (others => '0');
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if acc.done(0) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
if acc.mode(2) = '0' or acc.mode(0) = '0' then
pv.m.acc(pr.m.acc_sel).pending := '0';
pv.m.acc(pr.m.acc_sel).done(1) := '1';
else
pv.m.acc(pr.m.acc_sel).done(1) := '0';
end if;
end if;
end if;
end if;
-- Access canceled
if acc_cancel = '1' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
end if;
-- Access aborted by PCI error
if pr.m.abort(0) = '1' and pr.m.acc(pr.m.acc_sel).done(2) = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- error
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := '0' & (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort) & '0'; -- Error type: Master abort, Target abort, (PAR error)
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pr.m.addr(AHB_FIFO_BITS);
end if;
-- Set PAR error status
if pr.m.fifo_switch = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(conv_integer(pr.m.fifo_addr(pr.m.fifo_addr'left downto FIFO_DEPTH))).status(0) := pv.m.acc(pr.m.acc_sel).status(0);
pv.m.acc(pr.m.acc_sel).status(0) := '0';
end if;
when others =>
end case;
-- New (Master state machine is moed to PHY)
if pr.m.state = pm_addr then pv.m.first_word := '1'; end if;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- PCI target defaults
-- --------------------------------------------------------------------------------
-- Defaults
t_hit := '0'; t_chit := '0';
pv.t.cur_acc(0).newacc := '0';
pv.t.hold_reset := '1';
t_cad := (others => '0');
pv.t.first_word := '0';
t_ready := '0'; t_retry := '0';
t_abort := pr.t.stop;
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
t_acc_impcfgreg := '1';
-- FIFO (Block RAM enable(read)/write)
pv.t.atp.ctrl.en := '0'; -- read enable
pv.t.pta.ctrl.en := '0'; -- write enable
pv.t.pta.ctrl.data := byte_twist(pi.ad, pr.pta_trans.ca_twist);
tm_acc_pending := pr.pta_trans.tm_acc.pending xor atp_trans.tm_acc_ack;
tm_acc_cancel := pr.pta_trans.tm_acc_cancel xor atp_trans.tm_acc_cancel_ack(RAM_LATENCY);
tm_acc_done := pr.pta_trans.tm_acc_done_ack xor atp_trans.tm_acc_done.done;
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := atp_trans.tm_fifo(i).pending(RAM_LATENCY) xor pr.pta_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (pr.pta_trans.tm_fifo(i).pending(0) xor atp_trans.tm_fifo_ack(i));
pv.pta_trans.tm_fifo(i).pending(1) := pr.pta_trans.tm_fifo(i).pending(0);
pv.pta_trans.tm_fifo(i).pending(2) := pr.pta_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := ar.atp_trans.tm_fifo;
accbufindex := 0;
-- Not used
if tm_acc_done = '1' then
pv.pta_trans.tm_acc_done_ack := atp_trans.tm_acc_done.done;
end if;
-- --------------------------------------------------------------------------------
-- PCI target core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Target latency counter
if pv.t.state = pt_s_data and pr.po.trdy = '1' and pr.t.lcount /= "111" then
pv.t.lcount := pr.t.lcount + 1;
elsif pr.po.trdy = '0' then
pv.t.lcount := (others => '0');
end if;
-- select next fifo
if pr.t.cur_acc(0).read = '1' then
if pr.t.atp.index /= FIFO_COUNT-1 then t_index := (pr.t.atp.index + 1);
else t_index := 0; end if;
else
if pr.t.pta.index /= FIFO_COUNT-1 then t_index := (pr.t.pta.index + 1);
else t_index := 0; end if;
end if;
-- PCI BAR address matching
t_bar := (others => '0'); t_func := 0;
for j in 0 to multifunc loop
for i in 0 to 5 loop
if (pi.ad(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) =
(pr.conf(j).bar(i)(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) and
pr.conf(j).bar_mask(i)(31) = '1' then
if pr.conf(j).bar_mask(i)(0) = '0' and (pi.cbe = MEM_READ or pi.cbe = MEM_R_MULT or pi.cbe = MEM_R_LINE
or pi.cbe = MEM_WRITE or pi.cbe = MEM_W_INV) then
t_hit := pr.conf(j).comm.memen; -- Only hit if memory access is enabled
t_bar(i) := '1';
t_func := j;
elsif pr.conf(j).bar_mask(i)(0) = '1' and (pi.cbe = IO_READ or pi.cbe = IO_WRITE) then
t_hit := pr.conf(j).comm.ioen; -- Only hit if io access is enabled
t_bar(i) := '1';
t_func := j;
end if;
end if;
end loop;
end loop;
-- Configuration hit when IDSEL or self config (AD[31:11]=0 => no IDSEL) and in host slot
if ((pi.idsel = '1' or (pi.ad(31 downto 11) = zero32(31 downto 11) and pi.host = '0')) -- IDSEL asserted
and (pi.cbe = CONF_READ or pi.cbe = CONF_WRITE)) and pi.ad(1 downto 0) = "00" -- Command = config read or write, Type = 0
and pi.ad(10 downto 8) <= conv_std_logic_vector(multifunc, 3) then -- Respond to implemented function
t_chit := '1';
end if;
-- Read prefetch discard timer
if atp_trans.pa_discardtout_rst = '1' then
pv.pta_trans.pa_discardtout := '0';
end if;
if pr.t.cur_acc(0).pending = '1' and pr.t.discardtimeren = '1' then
if pr.t.discardtimer = x"0000" then
if pr.t.state = pt_idle then
pv.pta_trans.pa_discardtout := '1';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.discardtimer := pr.t.discardtimer - 1;
end if;
end if;
-- Access buffer
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '1' then
pv.pta_trans.tm_acc := pr.t.accbuf(0);
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
pv.t.accbuf(0) := pr.t.accbuf(1);
pv.t.accbuf(1) := pr.t.accbuf(2);
pv.t.accbuf(2) := pr.t.accbuf(3);
pv.t.accbuf(3).pending := '0';
end if;
pv.pciinten := (others => oeoff);
for i in 0 to 3 loop
if i <= multifunc then
pv.conf(i).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(i).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
else
pv.conf(0).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(0).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
end if;
end loop;
if multiint = 0 then
if oeoff = '1' then
pciinten_pad(0) <= andv(pr.pciinten);
else
pciinten_pad(0) <= orv(pr.pciinten);
end if;
pciinten_pad(3 downto 1) <= (others => oeoff);
else
pciinten_pad <= pr.pciinten;
end if;
-- PCI Configuration Space Header
conf_func := 0;
if conv_integer(pr.t.cur_acc(0).addr(10 downto 8)) <= multifunc then
conf_func := conv_integer(pr.t.cur_acc(0).addr(10 downto 8));
end if;
-- read
if pr.t.cur_acc(0).impcfgreg = '1' then
if pr.t.cur_acc(0).acc_type(0) = '0' then
case pr.t.conf_addr is
when "0000" => -- Device and Vendor ID
t_cad := conv_std_logic_vector(deviceid_vector(conf_func),16) & conv_std_logic_vector(vendorid,16);
when "0001" => -- Status and Command
t_cad := pr.conf(conf_func).stat.dpe & pr.conf(conf_func).stat.sse & pr.conf(conf_func).stat.rma & pr.conf(conf_func).stat.rta &
pr.conf(conf_func).stat.sta & "01" & pr.conf(conf_func).stat.mdpe & "00"& pr.pci66(1) &
"1"& pr.conf(conf_func).stat.intsta &"000" &
"00000" & pr.conf(conf_func).comm.intdis & "0" & pr.conf(conf_func).comm.serren & "0" & pr.conf(conf_func).comm.perren & "0" &
pr.conf(conf_func).comm.mwien & "0" & pr.conf(conf_func).comm.msten & pr.conf(conf_func).comm.memen & pr.conf(conf_func).comm.ioen;
when "0010" => -- Class Code and Revision ID
t_cad := conv_std_logic_vector(classcode_vector(conf_func),24) & conv_std_logic_vector(revisionid_vector(conf_func),8);
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
t_cad := "00000000" & conv_std_logic(multifunc /= 0) & "0000000" & pr.conf(conf_func).ltimer & "00000000";
when "0100" => -- BAR0
t_cad := pr.conf(conf_func).bar(0);
--t_cad(3) := bar_prefetch(0);
t_cad(3) := pr.conf(conf_func).bar_mask(0)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(0)(0);
when "0101" => -- BAR1
t_cad := pr.conf(conf_func).bar(1);
--t_cad(3) := bar_prefetch(1);
t_cad(3) := pr.conf(conf_func).bar_mask(1)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(1)(0);
when "0110" => -- BAR2
t_cad := pr.conf(conf_func).bar(2);
--t_cad(3) := bar_prefetch(2);
t_cad(3) := pr.conf(conf_func).bar_mask(2)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(2)(0);
when "0111" => -- BAR3
t_cad := pr.conf(conf_func).bar(3);
--t_cad(3) := bar_prefetch(3);
t_cad(3) := pr.conf(conf_func).bar_mask(3)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(3)(0);
when "1000" => -- BAR4
t_cad := pr.conf(conf_func).bar(4);
--t_cad(3) := bar_prefetch(4);
t_cad(3) := pr.conf(conf_func).bar_mask(4)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(4)(0);
when "1001" => -- BAR5
t_cad := pr.conf(conf_func).bar(5);
--t_cad(3) := bar_prefetch(5);
t_cad(3) := pr.conf(conf_func).bar_mask(5)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(5)(0);
when "1010" => -- Cardbus CIS Pointer
t_cad := (others => '0');
when "1011" => -- Subsystem ID and Subsystem Vendor ID
t_cad := (others => '0');
when "1100" => -- Expansion ROM Base Address
t_cad := (others => '0');
when "1101" => -- Reserved and Capabillities Pointer
t_cad := (others => '0');
t_cad(7 downto 0) := conv_std_logic_vector(cap_pointer_vector(conf_func), 8);
when "1110" => -- Reserved
t_cad := (others => '0');
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
t_cad := x"00" & x"00" & (x"0"&"0"&conv_std_logic_vector(deviceirq_vector(conf_func), 3)) & pr.conf(conf_func).iline;
when others =>
t_cad := (others => '0');
end case;
else -- Mapping register
case pr.t.conf_addr is
when "0000" =>
t_cad := x"0040" & conv_std_logic_vector(ext_cap_pointer_vector(conf_func), 8) & x"09";
when "0001" =>
t_cad := pr.conf(conf_func).pta_map(0);
when "0010" =>
t_cad := pr.conf(conf_func).pta_map(1);
when "0011" =>
t_cad := pr.conf(conf_func).pta_map(2);
when "0100" =>
t_cad := pr.conf(conf_func).pta_map(3);
when "0101" =>
t_cad := pr.conf(conf_func).pta_map(4);
when "0110" =>
t_cad := pr.conf(conf_func).pta_map(5);
when "0111" =>
t_cad := pr.conf(conf_func).cfg_map;
when "1000" =>
t_cad := conv_std_logic_vector(iobase, 12) & x"0000"&"00"&pr.t.discardtimeren&pr.pta_trans.ca_twist; -- AHB IO base address (used to find P&P information) and byte twisting
when "1001" =>
t_cad := pr.conf(conf_func).bar_mask(0);
when "1010" =>
t_cad := pr.conf(conf_func).bar_mask(1);
when "1011" =>
t_cad := pr.conf(conf_func).bar_mask(2);
when "1100" =>
t_cad := pr.conf(conf_func).bar_mask(3);
when "1101" =>
t_cad := pr.conf(conf_func).bar_mask(4);
when "1110" =>
t_cad := pr.conf(conf_func).bar_mask(5);
when "1111" =>
t_cad := pr.t.saverfifo & "000" & x"000" & pr.t.blenmask; -- Burst lenght boundary mask
when others =>
t_cad := (others => '0');
end case;
end if;
end if;
-- write
if (pi.irdy or pi.trdy) = '0' and pr.t.cur_acc(0).acc_type(1) = '1' and pr.t.cur_acc(0).impcfgreg = '1' and
pr.t.cur_acc(0).read = '0' and pr.t.fstate = ptf_cwrite then
-- Support for all CBE combinations
if pi.cbe(3) = '0' then t_cad(31 downto 24) := pi.ad(31 downto 24); end if;
if pi.cbe(2) = '0' then t_cad(23 downto 16) := pi.ad(23 downto 16); end if;
if pi.cbe(1) = '0' then t_cad(15 downto 8) := pi.ad(15 downto 8); end if;
if pi.cbe(0) = '0' then t_cad( 7 downto 0) := pi.ad( 7 downto 0); end if;
if pr.t.cur_acc(0).acc_type(0) = '0'then
case pr.t.conf_addr is
--when "0000" => -- Device and Vendor ID
when "0001" => -- Status and Command
-- Command register
pv.conf(conf_func).comm.ioen := t_cad(0);
pv.conf(conf_func).comm.memen := t_cad(1);
if MASTER = 1 then
pv.conf(conf_func).comm.msten := t_cad(2);
pv.pta_trans.ca_pcimsten(conf_func) := pv.conf(conf_func).comm.msten;
end if;
pv.conf(conf_func).comm.mwien := t_cad(4);
pv.conf(conf_func).comm.perren := t_cad(6);
pv.conf(conf_func).comm.serren := t_cad(8);
pv.conf(conf_func).comm.intdis := t_cad(10);
-- Status register, sticky bits
pv.conf(conf_func).stat.mdpe := pr.conf(conf_func).stat.mdpe and not t_cad(24);
pv.conf(conf_func).stat.sta := pr.conf(conf_func).stat.sta and not t_cad(27);
pv.conf(conf_func).stat.rta := pr.conf(conf_func).stat.rta and not t_cad(28);
pv.conf(conf_func).stat.rma := pr.conf(conf_func).stat.rma and not t_cad(29);
pv.conf(conf_func).stat.sse := pr.conf(conf_func).stat.sse and not t_cad(30);
pv.conf(conf_func).stat.dpe := pr.conf(conf_func).stat.dpe and not t_cad(31);
--when "0010" => -- Class Code and Revision ID
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
pv.conf(conf_func).ltimer := t_cad(15 downto 8);
when "0100" => -- BAR0
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).bar(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" => -- BAR1
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).bar(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" => -- BAR2
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).bar(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" => -- BAR3
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).bar(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1000" => -- BAR4
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).bar(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1001" => -- BAR5
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).bar(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
--when "1010" => -- Cardbus CIS Pointer
--when "1011" => -- Subsystem ID and Subsystem Vendor ID
--when "1100" => -- Expansion ROM Base Address
--when "1101" => -- Reserved and Capabillities Pointer
--when "1110" => -- Reserved
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
pv.conf(conf_func).iline := t_cad(7 downto 0);
when others =>
end case;
else -- Mapping registers
case pr.t.conf_addr is
when "0001" =>
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).pta_map(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0010" =>
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).pta_map(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0011" =>
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).pta_map(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0100" =>
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).pta_map(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" =>
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).pta_map(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" =>
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).pta_map(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" =>
pv.conf(conf_func).cfg_map(31 downto 8) := t_cad(31 downto 8);
when "1000" =>
pv.t.discardtimeren := t_cad(1);
pv.pta_trans.ca_twist := t_cad(0);
when "1001" =>
if bar_size(conf_func)(0) /= 0 then
pv.conf(conf_func).bar_mask(0)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(0)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(0)(0) := t_cad(0);
end if;
when "1010" =>
if bar_size(conf_func)(1) /= 0 then
pv.conf(conf_func).bar_mask(1)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(1)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(1)(0) := t_cad(0);
end if;
when "1011" =>
if bar_size(conf_func)(2) /= 0 then
pv.conf(conf_func).bar_mask(2)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(2)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(2)(0) := t_cad(0);
end if;
when "1100" =>
if bar_size(conf_func)(3) /= 0 then
pv.conf(conf_func).bar_mask(3)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(3)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(3)(0) := t_cad(0);
end if;
when "1101" =>
if bar_size(conf_func)(4) /= 0 then
pv.conf(conf_func).bar_mask(4)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(4)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(4)(0) := t_cad(0);
end if;
when "1110" =>
if bar_size(conf_func)(5) /= 0 then
pv.conf(conf_func).bar_mask(5)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(5)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(5)(0) := t_cad(0);
end if;
when "1111" =>
pv.t.blenmask(blenmask_size(barminsize) downto FIFO_DEPTH) := t_cad(blenmask_size(barminsize) downto FIFO_DEPTH);
pv.t.saverfifo := t_cad(31);
when others =>
end case;
end if;
end if;
-- FIFO State machine
case pr.t.fstate is
when ptf_idle =>
pv.t.first := (others => '1');
pv.t.preload := '0';
pv.t.preload_count := (others => '0');
pv.t.diswithout := '0';
if pr.t.cur_acc(0).pending = '1' then
if pr.t.cur_acc(0).read = '1' then -- Memory and Config read
pv.t.fstate := ptf_fifo;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pr.t.atp.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
else
if pr.t.cur_acc(0).acc_type(1) = '1' then -- Config write
pv.t.fstate := ptf_cwrite;
pv.t.conf_addr := pr.t.cur_acc(0).addr(5 downto 2);
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' then -- Memory write
-- Burst length (only burst up to this boundary)
pv.t.blen := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.fstate := ptf_write;
t_ready := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
else
t_retry := '1';
pv.t.fstate := ptf_idle;
pv.t.cur_acc(0).pending := '0';
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' and -- Access to AHB
( (pr.t.cur_acc(0).read = '1') -- Read
or (pr.t.cur_acc(0).read = '0' and tm_fifo_empty(pr.t.pta.index) = '1')) then -- Write
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '0' then
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.pta_trans.tm_acc.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.pta_trans.tm_acc.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.pta_trans.tm_acc.acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.pta_trans.tm_acc.accmode := "00" & pr.t.cur_acc(0).burst;
pv.pta_trans.tm_acc.size := (others => '0'); -- not used
pv.pta_trans.tm_acc.offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.pta_trans.tm_acc.index := pr.t.atp.index;
else pv.pta_trans.tm_acc.index := pr.t.pta.index; end if;
pv.pta_trans.tm_acc.length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.pta_trans.tm_acc.cbe := pi.cbe;
pv.pta_trans.tm_acc.endianess := pr.pta_trans.ca_twist;
else
accbufindex := 0;
for i in 3 downto 0 loop
if pv.t.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
pv.t.accbuf(accbufindex).pending := '1';
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.accbuf(accbufindex).addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.accbuf(accbufindex).addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.t.accbuf(accbufindex).acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.t.accbuf(accbufindex).accmode := "00" & pr.t.cur_acc(0).burst;
pv.t.accbuf(accbufindex).size := (others => '0'); -- not used
pv.t.accbuf(accbufindex).offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.t.accbuf(accbufindex).index := pr.t.atp.index;
else pv.t.accbuf(accbufindex).index := pr.t.pta.index; end if;
pv.t.accbuf(accbufindex).length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.accbuf(accbufindex).cbe := pi.cbe;
pv.t.accbuf(accbufindex).endianess := pr.pta_trans.ca_twist;
end if;
end if;
end if;
when ptf_fifo =>
pv.t.atp.ctrl.en := tm_fifo_pending(pr.t.atp.index);
if (pr.t.hold(0) = '0' or pr.t.first_word = '1') and pr.t.cfifo(0).valid = '1' then
t_ready := '1';
end if;
if pr.t.cur_acc(0).newacc = '1' or
(tm_acc_cancel = '1' and pr.t.cur_acc(0).acc_type(1) = '0') or
pr.t.cur_acc(0).read = '0' then
t_ready := '0';
end if;
if (tm_acc_cancel = '0' and tm_fifo_pending(pr.t.atp.index) = '1') or pr.t.preload = '1' or pr.t.cur_acc(0).acc_type(1) = '1' then -- FIFO pending or Config access
pv.t.preload := '1';
if pr.t.preload = '0' then pv.t.hold_fifo := '0'; end if;
end if;
if ((pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data) or pr.t.preload = '1' then
if (pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
pv.t.cur_acc(0).addr := pr.t.cur_acc(0).addr + 4;
elsif pr.t.preload = '1' then
if pr.t.cfifo(0).valid = '0' then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
elsif pr.t.cfifo(0).valid = '1' and pr.t.cfifo(1).valid = '0' then
pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
pv.t.cfifo(2).data := byte_twist(tm_fifoo_atp.data, pr.pta_trans.ca_twist); -- shifting in data from backend fifo
else
pv.t.cfifo(2).data := t_cad; -- Configuration access
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
if tm_fifo_pending(pr.t.atp.index) = '1' then
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and pr.t.hold_fifo = '0' then -- Mark last word
pv.t.atp.index := t_index;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- Reset backend fifo address
pv.pta_trans.tm_fifo_ack(pr.t.atp.index) := tm_fifo(pr.t.atp.index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
if tm_fifo_pending(t_index) = '1' then
pv.t.cfifo(2).hold := '0';
else
pv.t.cfifo(2).hold := '1';
pv.t.hold_fifo := '1';
-- Disconnect on last fifo
if tm_fifo(pr.t.atp.index).lastf = '1' then pv.t.cfifo(2).stlast := '1'; end if;
-- Disable fifo read
pv.t.atp.ctrl.en := '0';
end if;
else
pv.t.cfifo(2).hold := '0';
if pr.t.hold_fifo = '0' then
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and tm_fifo(pr.t.atp.index).status /= "0000" then
pv.t.cfifo(2).err := '1';
else
pv.t.cfifo(2).err := '0';
end if;
end if;
else -- Configuration access
if pr.t.conf_addr = "1110" then
pv.t.cfifo(2).stlast := '1';
else
pv.t.cfifo(2).stlast := '0';
end if;
if pr.t.conf_addr = "1111" then
pv.t.cfifo(2).hold := '1';
if pr.t.preload_count = "00" then pv.t.cfifo(2).stlast := '1'; end if;
else
pv.t.cfifo(2).hold := '0';
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
pv.t.cfifo(2).err := '0';
end if;
if (tm_fifo_pending(pr.t.atp.index) = '1' or pr.t.cur_acc(0).acc_type(1) = '1') and pr.t.hold_fifo = '0' then
pv.t.cfifo(2).valid := '1';
else
pv.t.cfifo(2).valid := '0';
end if;
end if;
if (pv.t.cfifo(0).valid = '1' and pv.t.cfifo(1).valid = '1' and pv.t.cfifo(2).valid = '1')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).valid = '0')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1') then
pv.t.preload := '0';
if pr.t.preload = '1' or (pr.t.hold_fifo = '1' and pv.t.hold_fifo = '0') then
pv.t.hold_reset := '0';
if pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1' then pv.t.cfifo(0).hold := '0'; end if;
if pr.t.cfifo(1).hold = '1' and pv.t.cfifo(2).valid = '1' then pv.t.cfifo(1).hold := '0'; end if;
if pr.t.cfifo(2).hold = '1' and tm_fifo_pending(pr.t.atp.index) = '1' then pv.t.cfifo(2).hold := '0'; end if;
end if;
end if;
if (pr.t.state = pt_turn_ar and pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).continue = '0')
or (pr.t.cur_acc(0).newacc = '1')
or ((pr.t.abort = '1' or pr.t.diswithout = '1') and (pr.t.state = pt_backoff or pr.t.state = pt_turn_ar))
then
if pr.t.cur_acc(0).burst = '1' and pr.t.abort = '0' then
if pr.t.cur_acc(0).acc_type(1) = '0' or pr.t.cur_acc(0).read = '0' or pr.t.cur_acc(0).pending = '0' then
pv.t.fstate := ptf_idle;
end if;
else
pv.t.fstate := ptf_idle;
if pr.t.abort = '1' then pv.t.cur_acc(0).pending := '0'; end if;
if pr.t.cur_acc(0).burst = '1' then pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel; end if;
end if;
pv.t.hold_reset := '0';
for i in 0 to 2 loop
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).err := '0';
end loop;
if (pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).burst = '1') or
(pr.t.cur_acc(0).newacc = '1' and pr.t.cur_acc(0).oldburst = '1') then
pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel;
end if;
end if;
when ptf_cwrite =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
if pr.t.conf_addr /= "1111" then -- Config access
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
end if;
when ptf_write =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' and pr.t.hold_write = '0' then
t_ready := '1';
pv.t.hold_reset := '0';
end if;
if (pr.t.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) and pr.t.first(0) = '1' and
(tm_fifo_empty(t_index) = '0' or pr.t.blen = x"0000")) or
((pi.trdy or pi.irdy) = '0' and pr.t.blen = x"0001") or
pr.t.cur_acc(0).burst = '0' then
pv.t.diswithout := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
pv.t.pta.ctrl.en := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.addr(AHB_FIFO_BITS);
if pi.cbe /= ones32(3 downto 0) or pr.t.first(0) = '1' then
pv.t.first(0) := '0';
pv.pta_trans.tm_fifo(pr.t.pta.index).stop := pr.t.addr(AHB_FIFO_BITS);
pv.pta_trans.tm_fifo(pr.t.pta.index).last_cbe := pi.cbe;
end if;
if pr.t.first(0) = '1' then -- First data in this fifo
pv.pta_trans.tm_fifo(pr.t.pta.index).start := pr.t.addr(AHB_FIFO_BITS);
end if;
pv.t.addr := pr.t.addr + 4; -- inc backend fifo address
if pr.t.blen /= zero32(15 downto 0) then
pv.t.blen := pr.t.blen - 1;
end if;
if pr.t.addr(AHB_FIFO_BITS) /= ones32(FIFO_DEPTH-1 downto 0) and pi.frame = '0' and pr.t.diswithout = '0' and pi.stop = '1' then
if pr.t.addr(AHB_FIFO_BITS) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 1), FIFO_DEPTH) then
if tm_fifo_empty(t_index) = '0' then
pv.t.hold_write := '1';
t_ready := '0';
pv.t.diswithout := '1';
end if;
end if;
else
pv.t.first(0) := '1';
pv.t.first(1) := '0';
pv.t.hold_write := '0';
pv.t.pta.index := t_index;
pv.pta_trans.tm_fifo(pr.t.pta.index).pending(0) := not pr.pta_trans.tm_fifo(pr.t.pta.index).pending(0);
pv.pta_trans.tm_fifo(pr.t.pta.index).status := (others => '0');
if pr.t.first(1) = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '1';
else pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '0'; end if;
if pi.frame = '1' or pr.t.diswithout = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '1'; -- Mark last fifo
else pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '0'; end if;
end if;
end if;
when others =>
end case;
-- PCI State machine
case pr.t.state is
when pt_idle => -- The bus is in idle state
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad
and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when pt_b_busy => -- Wait for the current transaction to complete and bus return
-- to idle sate
if (pi.frame and pi.irdy) = '1' then
pv.t.state := pt_idle;
end if;
when pt_s_data => -- Target is transfering data
if (pi.frame and not pi.irdy and ( not pi.trdy or not pi.stop)) = '1' then
pv.t.state := pt_turn_ar;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pi.trdy = '1' and pi.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
elsif (not pi.frame and not pi.stop) = '1' then
pv.t.state := pt_backoff;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pr.t.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
end if;
if (not pi.irdy and not pi.trdy) = '1' then pv.t.cur_acc(0).pending := '0'; end if; -- Data transfered, reset pending
-- can maybe be optimized
if ((pr.t.cfifo(0).valid = '0' or pr.t.cur_acc(0).match = '0') and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).read = '1') or
pr.t.retry = '1' then t_retry := '1'; pv.t.retry := '1'; end if;
-- CFIFO valid again after FIFO switch (First word in continued access), to reassert trdy
if pr.t.fstate = ptf_fifo and pr.t.preload = '1' and pr.t.first_word = '0' and
pr.t.cfifo(0).valid = '0' and pr.t.cfifo(1).valid = '1' then
pv.t.first_word := '1';
end if;
-- When FIFO is saved until next access (disconnect without data)
-- the first_word signal needs to be set one extra cycle to be valid the cycle before
-- FIFO state-machine moves to FIFO write state
if pr.t.fstate = ptf_fifo and pr.t.first_word = '1' and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).newacc = '1' and
pr.t.cur_acc(0).read = '0' then
if pr.t.saverfifo = '1' then
pv.t.first_word := '1';
end if;
end if;
when pt_backoff => -- STOP# is asserted, waiting on deasserted FRAME#
if pi.frame = '1' then
pv.t.state := pt_turn_ar;
end if;
when pt_turn_ar => -- Deassert active signals before tri-state
-- from idle
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '1' then
pv.t.state := pt_idle;
elsif pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when others =>
end case;
if pr.t.fstate = ptf_idle then pv.t.hold_reset := '0'; end if;
if pr.po.stop = '0' then pv.t.stoped := '1'; end if;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- PCI trace
-- --------------------------------------------------------------------------------
-- sync
pv.pt_sync(1) := ar.atpt_trans; pv.pt_sync(2) := pr.pt_sync(1);
if nsync = 0 then atpt_trans := ar.atpt_trans;
else atpt_trans := pr.pt_sync(nsync); end if;
pt_setup := ar.atpt_trans;
pv.ptta_trans.start_ack := atpt_trans.start;
pv.ptta_trans.stop_ack := atpt_trans.stop;
pt_start := not pr.ptta_trans.start_ack and (pr.ptta_trans.start_ack xor atpt_trans.start);
pt_stop := not pr.ptta_trans.stop_ack and (pr.ptta_trans.stop_ack xor atpt_trans.stop);
if tracebuffer /= 0 then -- PCI trace buffer enabled
if pr.ptta_trans.enable = '1' then -- PCI tracing
pv.pt.addr := pr.pt.addr + 1;
if pr.ptta_trans.armed = '1' then -- Check for match
if ((((pi.ad & pcisig) xor (pt_setup.ad & pt_setup.sig)) and (pt_setup.admask & pt_setup.sigmask)) = z) then
if pr.pt.tcount = x"00" then
pv.ptta_trans.armed := '0'; -- Start saving trace
pv.ptta_trans.taddr := pr.pt.addr;
else pv.pt.tcount := pr.pt.tcount - 1; end if;
end if;
if pr.pt.addr = pr.ptta_trans.taddr then pv.ptta_trans.wrap := '1'; end if;
else
if pr.pt.count = zero32(PT_DEPTH-1 downto 0) then pv.ptta_trans.enable := '0'; -- Trace done
else pv.pt.count := pr.pt.count - 1; end if;
end if;
end if;
if pt_stop = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '0';
if pr.ptta_trans.enable = '1' then
pv.ptta_trans.taddr := pr.pt.addr;
end if;
end if;
if pt_start = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '1';
pv.ptta_trans.armed := '1';
pv.ptta_trans.wrap := '0';
pv.pt.count := pt_setup.count;
pv.pt.tcount := pt_setup.tcount;
end if;
--
pv.ptta_trans.dbg_ad := pi.ad;
pv.ptta_trans.dbg_sig := pcisig;
pv.ptta_trans.dbg_cur_ad := pr.t.cur_acc(0).addr;
pv.ptta_trans.dbg_cur_acc := pr.t.cur_acc(0).oldburst &
pr.t.cur_acc(0).acc_type &
pr.t.cur_acc(0).read &
pr.t.cur_acc(0).continue &
pr.t.cur_acc(0).burst &
pr.t.cur_acc(0).newacc &
pr.t.cur_acc(0).match &
pr.t.cur_acc(0).pending;
end if; -- PCI trace buffer enabled
-- --------------------------------------------------------------------------------
-- PCI debug
-- --------------------------------------------------------------------------------
--[31:30] ms_fifo_pending
--[29:28] ms_fifo_empty
--[37:36] tm_fifo_pending
--[25:24] tm_fifo_empty
--[ :23] ms_acc_pending;
--[ :22] ms_acc_cancel;
--[ :21] ms_acc_done;
--[ :20] md_acc_pending;
--[ :19] md_acc_cancel;
--[ :18] md_acc_done;
--[ :17] tm_acc_pending;
--[ :16] tm_acc_cancel;
--[ :15] tm_acc_done;
--[14:12] t.state
--[11: 8] t.fstate
--[ 7: 4] m.state
--[ 3: 0] m.fstate
pv.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
pv.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
pv.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
pv.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
pv.debug( 23) := ms_acc_pending;
pv.debug( 22) := ms_acc_cancel;
pv.debug( 21) := ms_acc_done;
pv.debug( 20) := md_acc_pending;
pv.debug( 19) := md_acc_cancel;
pv.debug( 18) := md_acc_done;
pv.debug( 17) := tm_acc_pending;
pv.debug( 16) := tm_acc_cancel;
pv.debug( 15) := tm_acc_done;
case pr.t.state is
when pt_idle => pv.debug(14 downto 12) := "000";
when pt_b_busy => pv.debug(14 downto 12) := "001";
when pt_s_data => pv.debug(14 downto 12) := "010";
when pt_backoff => pv.debug(14 downto 12) := "011";
when pt_turn_ar => pv.debug(14 downto 12) := "100";
when others => pv.debug(14 downto 12) := "111";
end case;
case pr.t.fstate is
when ptf_idle => pv.debug(11 downto 8) := "0000";
when ptf_fifo => pv.debug(11 downto 8) := "0001";
when ptf_cwrite => pv.debug(11 downto 8) := "0010";
when ptf_write => pv.debug(11 downto 8) := "0011";
when others => pv.debug(11 downto 8) := "1111";
end case;
case pr.m.state is
when pm_idle => pv.debug(7 downto 4) := "0000";
when pm_addr => pv.debug(7 downto 4) := "0001";
when pm_m_data => pv.debug(7 downto 4) := "0010";
when pm_turn_ar => pv.debug(7 downto 4) := "0011";
when pm_s_tar => pv.debug(7 downto 4) := "0100";
when pm_dr_bus => pv.debug(7 downto 4) := "0101";
when others => pv.debug(7 downto 4) := "1111";
end case;
case pr.m.fstate is
when pmf_idle => pv.debug(3 downto 0) := "0000";
when pmf_fifo => pv.debug(3 downto 0) := "0001";
when pmf_read => pv.debug(3 downto 0) := "0010";
when others => pv.debug(3 downto 0) := "1111";
end case;
debugo <= (others => '0');
-- --------------------------------------------------------------------------------
-- PCI reset
-- --------------------------------------------------------------------------------
-- PCI master
lpcim_rst <= pcirst(0) and not pci_master_rst and not pci_hard_rst;
if lpcim_rst = '0' then
-- state
pv.m.fstate := pmf_idle;
for i in 0 to 2 loop
pv.m.cfifo(i).last := '0';
pv.m.cfifo(i).stlast := '0';
pv.m.cfifo(i).hold := '0';
pv.m.cfifo(i).valid := '0';
pv.m.cfifo(i).err := '0';
end loop;
-- core
pv.m.devsel_asserted := '1';
pv.m.abort := (others => '0');
pv.m.hold := (others => '0');
pv.m.hold_fifo := '0';
pv.m.term := (others => '0');
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
for i in 0 to 1 loop
pv.m.acc(i).pending := '0';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).fifo_index := 0;
end loop;
pv.m.fifo_addr := (others => '0');
pv.m.addr := (others => '0'); -- X-prop fix
-- trans
for i in 0 to 1 loop
pv.pta_trans.msd_acc_ack(i) := '0';
pv.pta_trans.msd_acc_cancel_ack(i) := (others => '0');
pv.pta_trans.msd_acc_done(i).done := '0';
for j in 0 to FIFO_COUNT-1 loop
pv.pta_trans.msd_fifo(i)(j).pending := (others => '0');
end loop;
pv.pta_trans.msd_fifo_ack(i) := (others => '0');
end loop;
end if;
-- PCI target
lpcit_rst <= pcirst(0) and not pci_target_rst and not pci_hard_rst;
if lpcit_rst = '0' then
-- state
pv.t.fstate := ptf_idle;
for i in 0 to 2 loop
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).err := '0';
end loop;
pv.t.cfifo(0).data := (others => '0'); -- X-prop fix
pv.t.cfifo(1).data := (others => '0'); -- X-prop fix
pv.t.atp.ctrl.addr := (others => '0'); -- X-prop fix
pv.t.cur_acc(0).addr(31) := '0'; -- X-prop fix
-- core
pv.t.discardtimeren := '1';
pv.t.hold := (others => '0');
pv.t.hold_fifo := '0';
pv.t.stop := '0';
pv.t.addr_perr := '0';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).continue := '0';
pv.t.cur_acc(0).read := '0';
pv.t.cur_acc(0).impcfgreg := '1';
pv.t.atp.index := 0;
pv.t.pta.index := 0;
pv.t.blenmask := (others => '0');
pv.t.blenmask(blenmask_size(barminsize) downto 0) := (others => '1');
pv.t.saverfifo := '0';
for i in 0 to 3 loop
pv.t.accbuf(i).pending := '0';
end loop;
-- trans
for i in 0 to FIFO_COUNT-1 loop
pv.pta_trans.tm_fifo(i).pending := (others => '0');
end loop;
pv.pta_trans.tm_fifo_ack := (others => '0');
pv.pta_trans.tm_acc.pending := '0';
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
end if;
-- PCI reset
lpci_rst <= pcirst(0) and not pci_hard_rst;
if lpci_rst = '0' then
-- Master state
pv.m.state := pm_idle;
-- Target state
pv.t.state := pt_idle;
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
-- PCI system
pv.pta_trans.pa_serr := '1';
pv.pta_trans.pa_discardtout := '0';
-- Configuration space
for j in 0 to multifunc loop
pv.conf(j).comm.ioen := '0';
pv.conf(j).comm.memen := '0';
pv.conf(j).comm.msten := '0';
pv.conf(j).comm.mwien := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
pv.conf(j).comm.intdis := '0';
pv.conf(j).stat.intsta := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.sta := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
--pv.conf.clsize := (others => '0');
pv.conf(j).ltimer := (others => '0');
pv.conf(j).iline := (others => '0');
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
pv.conf(j).pta_map(i) := default_bar_map(j)(i);
pv.conf(j).bar_mask(i) := (others => '0');
pv.conf(j).bar_mask(i)(31 downto bar_size(j)(i)) := ones32(31 downto bar_size(j)(i));
pv.conf(j).bar_mask(i)(3) := bar_prefetch(j)(i);
pv.conf(j).bar_mask(i)(0) := bar_io(j)(i);
if bar_size(j)(i) <= 1 then pv.conf(j).bar_mask(i) := (others => '0'); end if;
end loop;
pv.conf(j).cfg_map := conv_std_logic_vector(extcfg_vector(j),28) & "0000";
end loop;
pv.pta_trans.ca_pcimsten := (others => '0');
pv.pta_trans.ca_twist := conv_std_logic_vector(conv_endian, 1)(0);
-- PCI trace
pv.ptta_trans.enable := '0';
pv.ptta_trans.armed := '0';
pv.ptta_trans.start_ack := '0';
pv.ptta_trans.stop_ack := '0';
pv.pt.addr := (others => '0');
end if;
if pcirst(0) = '0' then
pv.pta_trans.rst_ack := (others => '0');
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
pv.t := pci_target_none;
pv.pta_trans.tm_acc := pci_g_acc_trans_none;
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
pv.pta_trans.tm_fifo := pci_g_fifo_trans_vector_none;
pv.pta_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
pv.po.trdy := '1'; pv.po.trdyen := oeoff; pv.po.stop := '1'; pv.po.stopen := oeoff;
pv.po.devsel := '1'; pv.po.devsel := oeoff;
for j in 0 to multifunc loop
pv.conf(j).comm.memen := '0';
pv.conf(j).stat.sta := '0';
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
end loop;
if master /= 0 and confspace = 0 then -- No Configuration Space but PCI master => master enabled
pv.conf(j).comm.msten := '1'; pv.pta_trans.ca_pcimsten := (others => '1');
end if;
end loop;
end if;
if master = 0 and dma = 0 then -- PCI master disabled
pv.m := pci_master_none;
pv.pta_trans.msd_acc_ack(0) := '0';
pv.pta_trans.msd_acc_cancel_ack(0) := (others => '0');
pv.pta_trans.msd_acc_done(0) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
pv.po.irdy := '1'; pv.po.irdyen := oeoff; pv.po.frame := '1'; pv.po.frameen := oeoff;
pv.po.req := '1'; pv.po.reqen := oeoff;
pv.po.cbe := (others => '0'); pv.po.cbeen := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).comm.msten := '0'; pv.pta_trans.ca_pcimsten := (others => '0');
pv.conf(j).comm.mwien := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
end loop;
end if;
if dma = 0 then -- DMA disabled
pv.m.acc(1) := pci_master_acc_none;
pv.pta_trans.msd_acc_ack(1) := '0';
pv.pta_trans.msd_acc_cancel_ack(1) := (others => '0');
pv.pta_trans.msd_acc_done(1) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
pv.pt := pci_trace_none;
pv.ptta_trans := pci_trace_to_apb_trans_none;
end if;
if dma = 0 and master = 0 and target = 0 then
pv.po.par := '1'; pv.po.paren := oeoff; pv.po.perr := '1'; pv.po.perren := oeoff;
pv.po.serren := oeoff; pv.po.inten := oeoff; pv.po.vinten := (others => oeoff);
pv.po.ad := (others => '0'); pv.po.aden := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
end loop;
end if;
-- --------------
prin <= pv;
-- PHY =>
sig_m_request <= m_request;
sig_m_mabort <= m_mabort;
sig_t_abort <= t_abort;
sig_t_ready <= t_ready;
sig_t_retry <= t_retry;
sig_soft_rst <= pci_hard_rst & pci_master_rst & pci_target_rst;
all_func_serren := '0';
for j in 0 to multifunc loop
all_func_serren := all_func_serren or pr.conf(j).comm.serren;
end loop;
sig_pr_conf_comm_serren <= all_func_serren;
if pr.m.perren /= "00" then
sig_pr_conf_comm_perren <= pr.conf(pr.m.acc(pr.m.acc_sel).func).comm.perren;
else
sig_pr_conf_comm_perren <= pr.conf(pr.t.cur_acc(0).func).comm.perren;
end if;
-- PHY <=
-- Gate PCI target => AHB master pending with pcirst
pr_pta_trans_gated <= pr.pta_trans;
pr_pta_trans_gated.tm_acc.pending <= pr.pta_trans.tm_acc.pending and pciasyncrst_comb;
end process;
acomb : process(ar, rst, pr_pta_trans_gated, dmao0, dmao1, tm_fifoo_pta, ms_fifoo_pta, md_fifoo_ptd, ahbsi, apbi, dirq, pcii.int, pt_fifoo_ad, pt_fifoo_sig, pr.ptta_trans, pcisig, lahbm_rst, lahbs_rst, lahb_rst, iotmact)
variable av : amba_reg_type;
variable pta_trans: pci_to_ahb_trans_type;
variable first : std_logic;
variable tm_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable tm_acc : pci_g_acc_trans_type;
variable tm_acc_pending : std_logic;
variable tm_acc_done : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
-- AHB slave
variable slv_access : std_logic;
variable tb_access : std_logic;
variable ms_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable blen : std_logic_vector(15 downto 0);
variable ms_acc_pending : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_done_status : pci_g_acc_status_trans_type;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
variable ms_func : std_logic_vector(2 downto 0);
variable ms_vifunc : integer range 0 to multifunc;
-- APB slave
variable apbaddr : std_logic_vector(6 downto 2);
variable prdata : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable c_blenmask_update : std_logic;
variable ptta_trans : pci_trace_to_apb_trans_type;
variable pt_status : pci_trace_to_apb_trans_type;
-- DMA
variable md_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable md_acc_pending : std_logic;
variable md_acc_cancel : std_logic;
variable md_acc_done : std_logic;
variable md_acc_done_status : pci_g_acc_status_trans_type;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- Soft reset
variable pci_master_rst : std_logic;
variable pci_target_rst : std_logic;
variable pci_hard_rst : std_logic;
-- APB DEBUG
variable tbapbaddr : std_logic_vector(6 downto 2);
variable tbprdata : std_logic_vector(31 downto 0);
variable tbpirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- --------------------------------------------------------------------------------
-- AHB global defaults
-- --------------------------------------------------------------------------------
-- defaults
av := ar;
av.irq.access_pirq := '0';
av.irq.system_pirq := '0';
-- FIFO and AHB<=>PCI sync
av.sync(1) := pr_pta_trans_gated; av.sync(2) := ar.sync(1);
if nsync = 0 then pta_trans := pr_pta_trans_gated;
else pta_trans := ar.sync(nsync); end if;
-- PCI trace <=> APB sync
av.apb_sync(1) := pr.ptta_trans; av.apb_sync(2) := ar.apb_sync(1);
if nsync = 0 then ptta_trans := pr.ptta_trans;
else ptta_trans := ar.apb_sync(nsync); end if;
pt_status := pr.ptta_trans;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans.start := '0'; av.atpt_trans.stop := '0'; av.atpt_trans.mode := (others => '0');
av.atpt_trans.count := (others => '0'); av.atpt_trans.tcount := (others => '0');
av.atpt_trans.ad := (others => '0'); av.atpt_trans.admask := (others => '0');
av.atpt_trans.sig := (others => '0'); av.atpt_trans.sigmask := (others => '0');
else
if ptta_trans.start_ack = '1' then av.atpt_trans.start := '0'; end if;
if ptta_trans.stop_ack = '1' then av.atpt_trans.stop := '0'; end if;
end if;
-- Soft reset
if pta_trans.rst_ack(0) = '1' then av.atp_trans.rst(0) := '0'; end if; -- PCI-target/AHB-master reset
if pta_trans.rst_ack(1) = '1' then av.atp_trans.rst(1) := '0'; end if; -- PCI-master/AHB-slave reset
pci_target_rst := pta_trans.rst_ack(0) or ar.atp_trans.rst(0);
pci_master_rst := pta_trans.rst_ack(1) or ar.atp_trans.rst(1);
pci_hard_rst := ar.atp_trans.rst(2);
-- --------------------------------------------------------------------------------
-- AHB master defaults
-- --------------------------------------------------------------------------------
-- FIFO enable(read)/write
av.m.acc.fifo_ren := '0';
av.m.acc.fifo_wen := '0';
av.m.acc.fifo_wdata := dmao0.data;
av.m.dmai0.noreq := '0';
tm_acc_pending := pta_trans.tm_acc.pending xor ar.atp_trans.tm_acc_ack;
tm_acc_done := pta_trans.tm_acc_done_ack xor ar.atp_trans.tm_acc_done.done;
tm_acc_cancel := pta_trans.tm_acc_cancel xor ar.atp_trans.tm_acc_cancel_ack(0);
-- Stop_ack also needs to be delayed when pending is delayed
av.atp_trans.tm_acc_cancel_ack(1) := ar.atp_trans.tm_acc_cancel_ack(0);
av.atp_trans.tm_acc_cancel_ack(2) := ar.atp_trans.tm_acc_cancel_ack(1);
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := pta_trans.tm_fifo(i).pending(RAM_LATENCY) xor ar.atp_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (ar.atp_trans.tm_fifo(i).pending(0) xor pta_trans.tm_fifo_ack(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
av.atp_trans.tm_fifo(i).pending(1) := ar.atp_trans.tm_fifo(i).pending(0);
av.atp_trans.tm_fifo(i).pending(2) := ar.atp_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := pr_pta_trans_gated.tm_fifo;
tm_acc := pr_pta_trans_gated.tm_acc;
-- --------------------------------------------------------------------------------
-- AHB master core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Select next fifo
if ar.m.acc.fifo_index /= FIFO_COUNT-1 then tm_nindex := ar.m.acc.fifo_index + 1;
else tm_nindex := 0; end if;
-- latch PCI target access
if tm_acc_pending = '1' and ar.m.acc.pending = '0' then
av.atp_trans.tm_acc_ack := pta_trans.tm_acc.pending;
av.m.acc.pending := '1';
av.m.acc.addr := tm_acc.addr;
av.m.acc.mode := tm_acc.accmode;
av.m.acc.burst := tm_acc.accmode(0);
av.m.acc.cbe := tm_acc.cbe;
av.m.acc.endianess := tm_acc.endianess;
av.m.acc.length := tm_acc.length;
av.m.acc.fifo_index := tm_acc.index;
av.m.acc.acctype := tm_acc.acctype;
end if;
-- AHB master state machine
case ar.m.state is
when am_idle =>
av.m.done := (others => '0');
av.m.stop := '0';
av.m.dmai0.req := '0';
av.m.dmai0.burst := '1';
av.m.dma_hold := '0';
av.m.active := '0';
av.m.retry := '0';
if ar.m.acc.pending = '1' then
av.m.dmai0.addr := ar.m.acc.addr;
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
-- Burst length (only burst up to this boundary)
av.m.blen := ar.m.acc.length;
if ar.m.acc.acctype(0) = '1' then -- Write
av.m.state := am_write;
av.m.first := "010";
av.m.hold := (others => '1');
elsif ar.m.acc.acctype(0) = '0' then -- Read
av.m.state := am_read;
av.m.first := "001";
av.m.hold := (others => '0');
av.m.dmai0.write := '0';
av.m.dmai0.req := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.acc.addr(AHB_FIFO_BITS); -- Set fifo start address
av.m.faddr := av.m.acc.addr(AHB_FIFO_BITS);
if ar.m.acc.burst = '0' then
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0'; -- sinlge access
else
av.m.dmai0.size := "10";
av.m.dmai0.addr(1 downto 0) := "00";
end if;
end if;
end if;
if tm_acc_cancel = '1' then
av.atp_trans.tm_acc_cancel_ack(0) := pta_trans.tm_acc_cancel;
end if;
when am_read =>
if tm_fifo_empty(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.done(0) = '0' and ar.m.active = '0' then
av.m.dmai0.req := '1';
av.m.hold := (others => '0');
end if;
if tm_acc_cancel = '1' then
av.m.done(2) := '1';
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
if ar.m.blen /= zero32(15 downto 0) then
av.m.blen := ar.m.blen - 1;
end if;
if ar.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if tm_fifo_empty(tm_nindex) = '0' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' or ar.m.blen = zero32(15 downto 0) then
av.m.dmai0.req := '0';
av.m.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.m.retry := '0';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
if ar.m.retry = '1' then
av.m.blen := ar.m.retry_blen;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
--av.m.blen := ar.m.blen + 1;
av.m.done(1) := '0';
-- Retry save & restore
av.m.retry := '1';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
av.m.blen := ar.m.retry_blen;
end if;
if dmao0.ready = '1' then
if dmao0.grant = '0' then av.m.active := '0'; end if;
if ar.m.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.m.done(1) = '0' then
av.m.faddr(AHB_FIFO_BITS) := ar.m.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.m.faddr(AHB_FIFO_BITS) := (others => '0');
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
end if;
if ar.m.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.m.done(0) := '1';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '0';
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status := (others => '0'); -- Not used
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).last_cbe := (others => '0'); -- Not used
end if;
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
av.m.done(0) := '1';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status(0) := '1'; -- AHB error
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
end if;
-- to deassert req on last address phase
if av.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) then av.m.dmai0.noreq := '1'; end if;
if ar.m.done(2) = '1' and ar.m.active = '0' and dmao0.grant = '0' then
av.m.dmai0.req := '0';
av.m.done := (others => '1');
end if;
if ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if ar.m.done(2) = '1' then
for i in 0 to FIFO_COUNT-1 loop
if tm_fifo_empty(i) = '0' then
av.atp_trans.tm_fifo(i).pending(0) := not ar.atp_trans.tm_fifo(i).pending(0);
else
av.atp_trans.tm_fifo(i).pending(0) := ar.atp_trans.tm_fifo(i).pending(0);
end if;
end loop;
end if;
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
end if;
when am_write =>
av.m.acc.fifo_ren := tm_fifo_pending(ar.m.acc.fifo_index);
av.m.dmai0.write := '1';
av.m.first(0) := '0';
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.active = '0' and ar.m.done(0) = '0' and ar.m.first(2) = '0' then
av.m.first(0) := '1';
av.m.first(2) := '1';
av.m.hold := "000";
av.m.last := "000";
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
av.m.faddr := tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
if ar.m.first(1) = '1' then
av.m.first(1) := '0';
end if;
-- Last access is non-word or first/last is no-data
if tm_fifo(ar.m.acc.fifo_index).start = tm_fifo(ar.m.acc.fifo_index).stop then
if ar.m.acc.cbe = ones32(3 downto 0) then
av.m.done(0) := '1';
av.m.first(0) := '0';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
elsif tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
elsif ar.m.acc.cbe = ones32(3 downto 0) then
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
av.m.faddr := (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
end if;
end if;
if ar.m.first(0) = '1' then -- Latch first word in fifo
av.m.dmai0.req := '1';
if ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) /= tm_fifo(ar.m.acc.fifo_index).stop then
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.last(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).status /= "0000" then
av.m.done(0) := '1';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
end if;
end if;
av.m.dmai0.data := tm_fifoo_pta.data;
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.faddr := ar.m.faddr + 1;
av.m.retry := '0';
if (ar.m.active = '1' and ar.m.faddr = tm_fifo(ar.m.acc.fifo_index).stop) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
if (ar.m.active = '1' and (tm_fifo_pending(tm_nindex) = '0' or tm_fifo(ar.m.acc.fifo_index).lastf = '1')) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then av.m.last(0) := '1'; end if;
end if;
if tm_fifo_pending(tm_nindex) = '1' then
if tm_fifo(tm_nindex).start = tm_fifo(tm_nindex).stop and tm_fifo(tm_nindex).last_cbe = ones32(3 downto 0) then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
end if;
end if;
-- Last access is non-word
if av.m.faddr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop and tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
elsif (tm_fifo(ar.m.acc.fifo_index).lastf = '0' and tm_fifo_pending(tm_nindex) = '1' and
av.m.faddr(AHB_FIFO_BITS) = zero32(AHB_FIFO_BITS) and tm_fifo(tm_nindex).stop = zero32(AHB_FIFO_BITS) and
tm_fifo(tm_nindex).last_cbe /= ar.m.acc.cbe) then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(tm_nindex).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(tm_nindex).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
if ar.m.retry = '1' then
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
av.m.faddr := ar.m.faddr - 1;
av.m.retry := '1';
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
if dmao0.ready = '1' then
av.m.first(2) := '0';
if dmao0.grant = '0' and ar.m.dmai0.req = '0' then av.m.active := '0'; end if;
if ar.m.hold(1 downto 0) = "00" then
av.m.dmai0.data := tm_fifoo_pta.data;
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) = tm_fifo(ar.m.acc.fifo_index).stop and
ar.m.hold(1 downto 0) /= "11" and ar.m.done(0) = '0' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.acc.fifo_addr := conv_std_logic_vector(av.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(tm_nindex).start; -- Set fifo start address
if tm_fifo_pending(tm_nindex) = '0' or ar.m.hold(0) = '1' then
av.m.hold(1) := '1';
end if;
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' or ar.m.last(1 downto 0) /= "00" then -- Transfer done
av.m.done(0) := '1';
end if;
end if;
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
if ar.m.done(0) = '0' then
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.done(0) := '1';
else
av.m.state := am_error;
end if;
end if;
end if;
if ar.m.done(0) = '1' and ar.m.active = '0' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
if av.m.dmai0.addr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop or ar.m.done(0) = '1' then av.m.dmai0.noreq := '1'; end if; -- to deassert req on last address phase
when am_error =>
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.done(0) = '0' then
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.done(0) := '1';
end if;
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
if ar.m.done(0) = '1' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
when others =>
end case;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- AHB slave defaults
-- --------------------------------------------------------------------------------
-- Default
av.s.hready := '1'; slv_access := '0'; tb_access := '0'; av.s.hresp := HRESP_OKAY;
av.s.retry := '0';
av.s.atp.ctrl.en := '0';
av.s.atp.ctrl.data := ahbreadword(ahbsi.hwdata);
av.s.pta.ctrl.en := '0';
av.s.stoppciacc := '0';
ms_acc_pending := ar.atp_trans.msd_acc(0).pending xor pta_trans.msd_acc_ack(0);
ms_acc_cancel := ar.atp_trans.msd_acc_cancel(0) xor pta_trans.msd_acc_cancel_ack(0)(RAM_LATENCY);
ms_acc_done := ar.atp_trans.msd_acc_done_ack(0) xor pta_trans.msd_acc_done(0).done;
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := pta_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (ar.atp_trans.msd_fifo(0)(i).pending(0) xor pta_trans.msd_fifo_ack(0)(i));
av.atp_trans.msd_fifo(0)(i).pending(1) := ar.atp_trans.msd_fifo(0)(i).pending(0);
av.atp_trans.msd_fifo(0)(i).pending(2) := ar.atp_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := pr_pta_trans_gated.msd_fifo(0);
ms_acc_done_status := pr_pta_trans_gated.msd_acc_done(0);
accbufindex := 0;
-- PCI function number
ms_func := ar.s.atp_map(conv_integer(ar.s.hmaster))(2 downto 0);
ms_vifunc := conv_integer(ar.s.atp_map(conv_integer(av.s.hmaster))(2 downto 0));
if multifunc = 0 then ms_func := (others => '0'); ms_vifunc := 0; end if;
-- --------------------------------------------------------------------------------
-- AHB slave core
-- --------------------------------------------------------------------------------
if master /= 0 then -- PCI master enabled
if ms_acc_done = '1' then -- Handle PCI error on AHB to PCI write
av.atp_trans.msd_acc_done_ack(0) := pta_trans.msd_acc_done(0).done;
if ms_acc_done_status.status(3) = '1' then -- PCI configuration access done
av.s.cfg_status(1) := '1';
if ms_acc_done_status.status(2 downto 0) /= "000" then av.s.cfg_status(0) := '1'; end if;
else
if ar.irq.access_en = '1' and ms_acc_done_status.status(2 downto 0) /= "000" then av.irq.access_pirq := '1'; end if;
av.irq.access_status := ar.irq.access_status or ms_acc_done_status.status(2 downto 0);
end if;
end if;
-- Select next fifo
if ar.s.state = as_write then
if ar.s.atp.index /= FIFO_COUNT-1 then ms_index := ar.s.atp.index + 1;
else ms_index := 0; end if;
else
if ar.s.pta.index /= FIFO_COUNT-1 then ms_index := ar.s.pta.index + 1;
else ms_index := 0; end if;
end if;
-- Access buffer
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '1' then
av.atp_trans.msd_acc(0) := ar.s.accbuf(0);
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.s.accbuf(0) := ar.s.accbuf(1);
av.s.accbuf(1) := ar.s.accbuf(2);
av.s.accbuf(2) := ar.s.accbuf(3);
av.s.accbuf(3).pending := '0';
end if;
-- Set prefetch burst length
blen := x"00" & ar.s.blen;
-- AHB access latchning
if (ahbsi.hready and ahbsi.hsel(hsindex) and ahbsi.htrans(1)) = '1' then
slv_access := '1';
av.s.haddr := ahbsi.haddr; av.s.hwrite := ahbsi.hwrite;
av.s.hsel := ahbsi.hsel(hsindex); av.s.hmbsel := ahbsi.hmbsel(0 to 2);
av.s.htrans := ahbsi.htrans; av.s.hsize := ahbsi.hsize;
av.s.hburst := ahbsi.hburst(0);
av.s.hmaster := ahbsi.hmaster;
end if;
-- PCI trace buffer access
if tracebuffer /= 0 then
if (ahbsi.hsel(hsindex) and ahbsi.hmbsel(1) and ahbsi.haddr(17) and ahbsi.htrans(1)) = '1' then
tb_access := '1';
end if;
end if;
-- Second retry/error cycle
if ar.s.retry = '1' then
if ar.s.hresp = HRESP_ERROR then
av.s.hresp := HRESP_ERROR;
else
av.s.hresp := HRESP_RETRY;
if ar.s.pending = "00" and ar.s.hwrite = '0' and ar.s.start = '0' and ar.s.stoppciacc = '0' then
av.s.pending := "01";
av.s.addr := ar.s.haddr;
av.s.write := ar.s.hwrite;
av.s.master := ar.s.hmaster;
av.s.burst := ar.s.hburst;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
-- Change to sigle access on PCI IO and PCI CONF
if ar.s.io_cfg_burst(0) = '0' and av.s.config = '1' then av.s.burst := '0'; end if;
if ar.s.io_cfg_burst(1) = '0' and av.s.io = '1' then av.s.burst := '0'; end if;
-- Use blen if less than 1k limit and AHB-master is unmasked, else use 1k limit
if (not av.s.addr(9 downto 2)) < ar.s.blen(7 downto 0) or ar.s.blenmask(conv_integer(av.s.master)) = '0' then blen(7 downto 0) := (not av.s.addr(9 downto 2)); end if;
if ar.s.continue = '0' then
if ar.s.hmbsel(0) = '0' then -- config access and io access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_READ;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_READ;
else
if av.s.burst = '1' then av.atp_trans.msd_acc(0).acctype := MEM_R_MULT;
else av.atp_trans.msd_acc(0).acctype := MEM_READ; end if;
end if;
av.atp_trans.msd_acc(0).accmode := av.s.burst & '1' & av.s.burst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.pta.index;
av.atp_trans.msd_acc(0).length := blen;
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_READ;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_READ;
else
if av.s.burst = '1' then av.s.accbuf(accbufindex).acctype := MEM_R_MULT;
else av.s.accbuf(accbufindex).acctype := MEM_READ; end if;
end if;
av.s.accbuf(accbufindex).accmode := av.s.burst & '1' & av.s.burst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.pta.index;
av.s.accbuf(accbufindex).length := blen;
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and ar.s.pending = "01" and ar.s.discard = '0' then
av.s.done_fifo := (others => '0');
av.s.pending := "10";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
elsif ar.s.pending = "10" then
av.s.pending := "11";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
av.s.hrdata := ms_fifoo_pta.data;
if ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.oneword := '1';
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
else av.s.oneword := '0'; end if;
end if;
-- FIFO read enable
av.s.pta.ctrl.en := ms_fifo_pending(ar.s.pta.index);
-- Discard unused fifo data
if ar.s.discard = '1' then
if ms_acc_cancel = '0' then
-- moved to PCI master
av.s.discard := '0';
end if;
end if;
-- AHB slave state machine
case ar.s.state is
when as_idle =>
av.s.continue := '0';
av.s.first := '1';
av.s.firstf := '1';
av.s.tb_ren := '0';
if slv_access = '1' then
if tb_access = '1' then -- PCI trace
av.s.hready := '0';
av.s.state := as_pcitrace;
av.s.tb_ren := '1';
else
if av.s.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' and
pta_trans.ca_pcimsten(ms_vifunc) = '1' and (pci_hard_rst or pci_master_rst) = '0' then -- Write
av.s.state := as_write;
elsif ar.s.pending(1) = '1' and ar.s.master = ahbsi.hmaster and
(pci_hard_rst or pci_master_rst) = '0' then -- Read
if (ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop) or -- Master/Target abort
(ms_fifo(ar.s.pta.index).status(0) = '1') then -- PAR error
if ar.s.config = '1' then -- Master/target abort during PCI config access
av.s.state := as_read;
av.s.cfg_status := "11";
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.burst = '1' then
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
av.s.discard := '1';
else
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
end if;
av.s.pending := (others => '0');
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
end if;
else
if ar.s.config = '1' then av.s.cfg_status(1) := '1'; end if;
av.s.state := as_read;
end if;
elsif ms_fifo_empty(ar.s.atp.index) = '1' and pta_trans.ca_pcimsten(ms_vifunc) = '0' and
(pci_hard_rst or pci_master_rst) = '0' then
av.s.state := as_checkpcimst;
av.s.hready := '0';
elsif (pci_hard_rst or pci_master_rst) = '1' then -- Error during reset
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
else -- Retry
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
end if;
end if;
end if;
when as_checkpcimst =>
if ar.s.hmbsel(0) = '0' and ar.s.haddr(16) = '1' and
((ar.s.haddr(15 downto 11) = zero32(15 downto 11) and pta_trans.ca_host = '0') or ar.s.fakehost = '1') then
if ar.s.hwrite = '1' then
av.s.state := as_write;
else
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
else
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
when as_read =>
av.s.pending := (others => '0');
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ms_fifo_pending(ar.s.pta.index) = '1' then
if ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop or ar.s.burst = '0' or ar.s.oneword = '1' then
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
end if;
end if;
av.s.hrdata := ms_fifoo_pta.data;
av.s.pta.ctrl.addr := conv_std_logic_vector(av.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' then -- new write access
av.s.state := as_write;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and
((ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and -- Master/Target abort
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop) or
(ms_fifo(ar.s.pta.index).status(0) = '1')) then -- PAR error
if ar.s.config = '1' then -- No AHB error for PCI Config Space
av.s.cfg_status := "11";
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
end if;
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
elsif (ahbsi.hwrite = '0' and ar.s.done_fifo(0) = '1') or ar.s.burst = '0' or ar.s.oneword = '1' then -- no pending fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.stoppciacc := not pta_trans.ca_pcimsten(ms_vifunc);
if ar.s.burst = '1' and ahbsi.htrans(0) = '1' then
if ar.s.done_fifo(1) = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
else
av.s.continue := '1'; -- Only for continuing bursts
end if;
end if;
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
when as_write =>
av.s.first := '0';
if ar.s.first = '1' then -- Store fifo start address
if ar.s.hmbsel(0) = '0' then -- mem/io/config access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
av.s.offset := ar.s.haddr(1 downto 0);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_WRITE;
else av.atp_trans.msd_acc(0).acctype := MEM_WRITE; end if;
av.atp_trans.msd_acc(0).accmode := "00" & ar.s.hburst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.atp.index;
av.atp_trans.msd_acc(0).length := (others => '0'); -- not used
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_WRITE;
else av.s.accbuf(accbufindex).acctype := MEM_WRITE; end if;
av.s.accbuf(accbufindex).accmode := "00" & ar.s.hburst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.atp.index;
av.s.accbuf(accbufindex).length := (others => '0'); -- not used
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ahbsi.htrans(0) = '0' then
av.s.firstf := '0';
av.s.atp.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0) := not ar.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0);
if ar.s.firstf = '1' then
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := av.s.addr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '1';
else
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := (others => '0');
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '0';
end if;
av.atp_trans.msd_fifo(0)(ar.s.atp.index).stop := ar.s.haddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).lastf := not ahbsi.htrans(0) or not ms_fifo_empty(ms_index);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(0)(ar.s.atp.index).last_cbe := (others => '0'); -- Not used
end if;
av.s.atp.ctrl.en := '1';
av.s.atp.ctrl.addr := conv_std_logic_vector(ar.s.atp.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ms_index) = '1' then -- new write access
av.s.first := '1';
av.s.firstf := '1';
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
end if;
if ahbsi.hwrite = '1' and ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) and ms_fifo_empty(ms_index) = '0' then -- no empty fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
end if;
end if;
when as_pcitrace =>
if ar.s.hready = '1' then
if tb_access = '1' then
av.s.hready := '0';
av.s.tb_ren := '1';
else
av.s.state := as_idle;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
av.s.hready := '0';
av.s.retry := '1';
av.s.hresp := HRESP_RETRY;
end if;
end if;
else
av.s.tb_ren := '0';
if ar.s.tb_ren = '0' then
av.s.hready := '1';
if ar.s.haddr(16) = '0' then
av.s.hrdata := pt_fifoo_ad.data;
else
av.s.hrdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
av.s.hready := '0';
end if;
end if;
when others =>
end case;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- DMA defaults
-- --------------------------------------------------------------------------------
av.dma.irq := '0';
-- FIFO enable(read)/write
av.dma.ptd.ctrl.en := '0';
av.dma.dtp.ctrl.en := '0';
av.dma.dtp.ctrl.data := dmao1.data;
av.dma.dmai1.noreq := '0';
av.dma.desc.addr(3 downto 0) := (others => '0');
md_acc_pending := ar.atp_trans.msd_acc(1).pending xor pta_trans.msd_acc_ack(1);
md_acc_cancel := ar.atp_trans.msd_acc_cancel(1) xor pta_trans.msd_acc_cancel_ack(1)(RAM_LATENCY);
md_acc_done := ar.atp_trans.msd_acc_done_ack(1) xor pta_trans.msd_acc_done(1).done;
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := pta_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (ar.atp_trans.msd_fifo(1)(i).pending(0) xor pta_trans.msd_fifo_ack(1)(i));
av.atp_trans.msd_fifo(1)(i).pending(1) := ar.atp_trans.msd_fifo(1)(i).pending(0);
av.atp_trans.msd_fifo(1)(i).pending(2) := ar.atp_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := pr_pta_trans_gated.msd_fifo(1);
md_acc_done_status := pr_pta_trans_gated.msd_acc_done(1);
-- --------------------------------------------------------------------------------
-- DMA core
-- --------------------------------------------------------------------------------
if dma /= 0 then -- DMA enabled
-- Select next fifo
if ar.dma.state = dma_read then
if ar.dma.dtp.index /= FIFO_COUNT-1 then md_index := ar.dma.dtp.index + 1;
else md_index := 0; end if;
else
if ar.dma.ptd.index /= FIFO_COUNT-1 then md_index := ar.dma.ptd.index + 1;
else md_index := 0; end if;
end if;
case ar.dma.state is
when dma_idle =>
av.dma.err := (others => '0');
av.dma.running := '0';
av.dma.dmai1.req := '0';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.desc.chcnt := ar.dma.numch;
if ar.dma.errstatus /= "00000" then
av.dma.en := '0';
elsif ar.dma.en = '1' then
av.dma.state := dma_read_desc;
av.dma.rcnt := (others => '0');
av.dma.dmai1.req := '1';
av.dma.dmai1.size := "10";
av.dma.running := '1';
end if;
when dma_read_desc =>
av.dma.active := '0';
av.dma.dma_hold := (others => '0');
av.dma.done := (others => '0');
av.dma.first(0) := '1';
av.dma.retry := '0';
if ar.dma.rcnt = "11" and ar.dma.desc.desctype /= "01"
and (ar.dma.desc.emptych = '0' or ar.dma.desc.chcnt = "000") then av.dma.dmai1.req := '0';
else av.dma.dmai1.req := '1'; end if;
av.dma.dmai1.burst := '1';
if dmao1.grant = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.dmai1.addr(3 downto 2) = "11" then
if ar.dma.desc.desctype = "01" then
av.dma.dmai1.addr := dmao1.data;
elsif ar.dma.desc.emptych = '1' then
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
if ar.dma.desc.chcnt = "000" then
av.dma.dmai1.req := '0';
end if;
else
av.dma.dmai1.req := '0';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
end if;
if av.dma.dmai1.addr(3 downto 2) = "11" then av.dma.dmai1.noreq := '1'; end if;
if dmao1.ready = '1' then
av.dma.err := (others => '0');
av.dma.rcnt := ar.dma.rcnt + 1;
case ar.dma.rcnt is
when "00" => -- Ctrl
av.dma.desc.en := dmao1.data(31);
av.dma.desc.irqen := dmao1.data(30);
av.dma.desc.write := dmao1.data(29);
av.dma.desc.tw := dmao1.data(28);
av.dma.desc.cio := dmao1.data(27 downto 26);
av.dma.desc.acctype := dmao1.data(25 downto 22);
av.dma.desc.desctype := dmao1.data(21 downto 20);
-- dmao1.data(19) = err
av.dma.desc.len := dmao1.data(15 downto 0);
when "01" => -- PCI address / Next DMA CH
if ar.dma.desc.desctype = "01" then
av.dma.desc.ch := ar.dma.desc.addr;
av.dma.desc.nextch := dmao1.data;
av.dma.desc.cnt := ar.dma.desc.len;
av.dma.desc.chid := ar.dma.desc.acctype(2 downto 0);
av.dma.desc.emptych := '1';
else
if ar.dma.desc.en = '1' then
av.dma.desc.emptych := '0';
end if;
av.dma.desc.paddr := dmao1.data;
end if;
when "10" => -- AHB address / Next desc
if ar.dma.desc.desctype = "01" then
av.dma.desc.addr := dmao1.data;
else
av.dma.desc.aaddr := dmao1.data;
end if;
when "11" => -- Next desc / ----
if ar.dma.desc.en = '1' then
if ar.dma.desc.desctype = "00" then
av.dma.desc.chcnt := ar.dma.numch;
av.dma.desc.nextdesc := dmao1.data;
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.dma.state := dma_read;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.addr := ar.dma.desc.aaddr;
if ar.dma.desc.len /= x"0000" then av.dma.dmai1.burst := '1';
else av.dma.dmai1.burst := '0'; end if;
av.dma.dmai1.size := "10"; -- 32-bit access -- add support for unaligned accesses
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.desc.aaddr(AHB_FIFO_BITS); -- Set fifo start address
av.dma.faddr := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
else -- PCI read => AHB write
av.dma.state := dma_write;
av.dma.first := "010";
av.dma.dma_hold := "111";
av.dma.addr := ar.dma.desc.aaddr;
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
end if;
-- Setup access [Read and Write]
av.atp_trans.msd_acc(1).pending := not ar.atp_trans.msd_acc(1).pending;
av.atp_trans.msd_acc(1).addr := ar.dma.desc.paddr;
av.atp_trans.msd_acc(1).func := "000"; -- DMA uses PCI function 0
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.atp_trans.msd_acc(1).index := ar.dma.dtp.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_WRITE;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_WRITE;
else -- PCI Memory access
av.atp_trans.msd_acc(1).acctype := MEM_WRITE;
end if;
else
av.atp_trans.msd_acc(1).index := ar.dma.ptd.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_READ;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_READ;
else -- PCI Memory access
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).acctype := MEM_R_MULT;
else
av.atp_trans.msd_acc(1).acctype := MEM_READ;
end if;
end if;
end if;
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).accmode := "011";
else
av.atp_trans.msd_acc(1).accmode := "010";
end if;
av.atp_trans.msd_acc(1).size := "010"; -- add size support
av.atp_trans.msd_acc(1).offset := ar.dma.desc.paddr(1 downto 0);
av.atp_trans.msd_acc(1).length := ar.dma.desc.len;
av.atp_trans.msd_acc(1).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(1).endianess := av.dma.desc.tw;
end if;
else
if ar.dma.desc.emptych = '0' then
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else
if ar.dma.desc.chcnt = "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
else
av.dma.desc.chcnt := ar.dma.desc.chcnt - 1;
end if;
end if;
end if;
when others =>
end case;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_next_channel =>
if dmao1.grant = '1' then
av.dma.dmai1.req := '0';
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
end if;
if dmao1.ready = '1' then
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
end if;
when dma_write_status =>
if dmao1.grant = '1' then
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
else
av.dma.dmai1.req := '0';
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
end if;
if dmao1.ready = '1' then
if ar.dma.err /= "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
else
if ar.dma.desc.irqen = '1' then
av.dma.irq := '1';
av.dma.irqstatus(1) := '1';
av.dma.irqch(conv_integer(ar.dma.desc.chid)) := '1';
end if;
if ar.dma.en = '0' then -- DMA disabled
av.dma.state := dma_idle;
av.dma.desc.addr := ar.dma.desc.nextdesc;
else
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else -- Next Desc
if ar.dma.desc.cnt /= x"0000" then
av.dma.desc.cnt := av.dma.desc.cnt - 1;
end if;
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextdesc;
av.dma.dmai1.addr := ar.dma.desc.nextdesc;
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_read => -- AHB read => PCI write
if md_fifo_empty(ar.dma.dtp.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.done(0) = '0' and ar.dma.active = '0' then
av.dma.dmai1.req := '1';
av.dma.dma_hold(1 downto 0) := "00";
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.len /= ar.dma.desc.len then
av.dma.len := ar.dma.len + 1;
end if;
if ar.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.dma.len = ar.dma.desc.len then
if md_fifo_empty(md_index) = '0' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
if ar.dma.len = ar.dma.desc.len then
av.dma.dmai1.req := '0';
av.dma.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.dma.retry := '0';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
if ar.dma.retry = '1' then
av.dma.len := ar.dma.retry_len;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
--av.dma.len := ar.dma.len - 1;
av.dma.done(1) := '0';
-- Retry save & restore
av.dma.retry := '1';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
av.dma.len := ar.dma.retry_len;
end if;
if dmao1.ready = '1' then
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' then av.dma.active := '0'; end if;
if ar.dma.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.dma.done(1) = '0' then -- Store data in fifo
av.dma.faddr(AHB_FIFO_BITS) := ar.dma.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.dma.faddr(AHB_FIFO_BITS) := (others => '0');
av.dma.dtp.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
end if;
if ar.dma.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.dma.done(0) := '1';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '0';
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).last_cbe := (others => '0'); -- Not used
end if;
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
elsif dmao1.error = '1' then
av.dma.active := '0';
av.dma.dmai1.req := '0';
av.dma.done(0) := '1';
av.dma.err(0) := '1';
av.dma.dtp.index := md_index; -- Go to next fifo
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or av.dma.len = ar.dma.desc.len then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
if ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
if md_acc_done = '1' then
av.atp_trans.msd_acc_done_ack(1) := not ar.atp_trans.msd_acc_done_ack(1);
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
av.dma.errstatus(1) := '1';
elsif md_acc_done_status.status /= "0000" then
av.dma.err(2) := '1';
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := md_acc_done_status.count;
av.dma.errstatus(4 downto 2) := md_acc_done_status.status(2 downto 0);
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
end if;
when dma_write => -- PCI read => AHB write
av.dma.ptd.ctrl.en := md_fifo_pending(ar.dma.ptd.index);
av.dma.dmai1.write := '1';
av.dma.first(0) := '0';
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.active = '0' and ar.dma.done(0) = '0' and ar.dma.first(2) = '0' then
av.dma.first(0) := '1';
av.dma.first(2) := '1';
av.dma.dma_hold := "000";
av.dma.dma_last := "000";
av.dma.newfifo := '0';
av.dma.ptd.ctrl.addr := conv_std_logic_vector(ar.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
av.dma.faddr := md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
if ar.dma.first(1) = '1' then
av.dma.first(1) := '0';
av.dma.dmai1.addr := ar.dma.addr;
av.dma.dmai1.size := "10";
av.dma.dmai1.addr(1 downto 0) := "00";
end if;
end if;
if ar.dma.first(0) = '1' then -- Latch first word in fifo
av.dma.dmai1.req := '1';
if ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) /= md_fifo(ar.dma.ptd.index).stop then
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.dma.dma_hold(0) := '1';
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.dma_last(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.done(0) := '1';
av.dma.dmai1.req := '0';
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
av.dma.dmai1.data := md_fifoo_ptd.data;
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.newfifo := '0';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
av.dma.faddr := ar.dma.faddr + 1;
if (ar.dma.active = '1' and ar.dma.faddr = md_fifo(ar.dma.ptd.index).stop) or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
if (ar.dma.active = '1' and md_fifo_pending(md_index) = '0') or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
av.dma.faddr := ar.dma.faddr - 1;
end if;
if dmao1.ready = '1' then
av.dma.first(2) := '0';
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' and ar.dma.dmai1.req = '0' then av.dma.active := '0'; end if;
if ar.dma.dma_hold(1 downto 0) = "00" then
av.dma.dmai1.data := md_fifoo_ptd.data;
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) = md_fifo(ar.dma.ptd.index).stop and
ar.dma.dma_hold(1 downto 0) /= "11" and ar.dma.done(0) = '0' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.ptd.ctrl.addr := conv_std_logic_vector(av.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(md_index).start; -- Set fifo start address
if md_fifo_pending(md_index) = '0' or ar.dma.dma_hold(0) = '1' then
av.dma.dma_hold(1) := '1';
end if;
if md_fifo(ar.dma.ptd.index).lastf = '1' or ar.dma.dma_last(1 downto 0) /= "00" then -- Transfer done
av.dma.done(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.err(0) := '1';
av.dma.errstatus(1) := '1';
av.dma.active := '0';
av.dma.dmai1.req := '0';
if ar.dma.done(0) = '0' then
if md_fifo_pending(ar.dma.ptd.index) = '1' and md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.done(0) := '1';
else
av.dma.state := dma_error;
end if;
end if;
end if;
if ar.dma.done(0) = '1' and ar.dma.active = '0' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = md_fifo(ar.dma.ptd.index).stop or ar.dma.done(0) = '1' then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
when dma_error => -- Wait for last fifo
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.done(0) = '0' then
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.done(0) := '1';
end if;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
end if;
if ar.dma.done(0) = '1' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
when others =>
end case;
end if; -- DMA enabled
-- --------------------------------------------------------------------------------
-- IRQ
-- --------------------------------------------------------------------------------
pirq := (others => '0');
-- PCI device driving PCI INTA
if deviceirq = 1 then
pciinten(0) <= oeoff xor (ar.irq.device_mask(0) and (ar.irq.device_force or dirq(0)));
pciinten(1) <= oeoff xor (ar.irq.device_mask(1) and (ar.irq.device_force or dirq(1)));
pciinten(2) <= oeoff xor (ar.irq.device_mask(2) and (ar.irq.device_force or dirq(2)));
pciinten(3) <= oeoff xor (ar.irq.device_mask(3) and (ar.irq.device_force or dirq(3)));
else
av.irq.device_mask := (others => '0');
av.irq.device_force := '0';
pciinten <= (others => oeoff);
end if;
-- PCI host sampling PCI INTA..D
if hostirq = 1 then
av.irq.host_pirq_vl := (pcii.int(3) or not ar.irq.host_mask(3))
& (pcii.int(2) or not ar.irq.host_mask(2))
& (pcii.int(1) or not ar.irq.host_mask(1))
& (pcii.int(0) or not ar.irq.host_mask(0));
av.irq.host_pirq_l := not ( av.irq.host_pirq_vl(0) and av.irq.host_pirq_vl(1)
and av.irq.host_pirq_vl(2) and av.irq.host_pirq_vl(3));
av.irq.host_status := pcii.int(3)
& pcii.int(2)
& pcii.int(1)
& pcii.int(0);
else
av.irq.host_mask := (others => '0');
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl:= (others => '0');
av.irq.host_pirq_l := '0';
end if;
-- System error irq (SERR)
if pta_trans.pa_serr = '1' and ar.atp_trans.pa_serr_rst = '1' then
av.irq.system_status(0) := '0';
av.atp_trans.pa_serr_rst := '0';
elsif pta_trans.pa_serr = '0' then
av.irq.system_status(0) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(0) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- System error irq (Discard time out)
if pta_trans.pa_discardtout = '0' and ar.atp_trans.pa_discardtout_rst = '1' then
av.irq.system_status(1) := '0';
av.atp_trans.pa_discardtout_rst := '0';
elsif pta_trans.pa_discardtout = '1' then
av.irq.system_status(1) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(1) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- Level IRQ
av.irq.system_pirq_l := ar.irq.system_en and orv(ar.irq.system_status);
av.irq.access_pirq_l := ar.irq.access_en and orv(ar.irq.access_status);
av.irq.dma_pirq_l := ar.dma.irqen and orv(ar.dma.irqstatus);
if irqmode = 0 then -- PCI INTA..D, Error irq and DMA irq on the same interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l; -- All level irq
elsif irqmode = 1 then -- PCI INTA..D and Error irq on the same interrupt. DMA irq no next interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := (ar.dma.irqen and ar.dma.irq);
elsif irqmode = 2 then -- PCI INTA..D on separate interrupt, Error irq and DMA irq on first interrupt
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
else --if irqmode = 3 then -- PCI INTA..D on separate interrupt, Error irq on first interrupt, DMA irq on interrupt after PCI INTD
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
pirq(irq+4) := (ar.dma.irqen and ar.dma.irq);
end if;
-- --------------------------------------------------------------------------------
-- APB Slave
-- --------------------------------------------------------------------------------
av.apb_pt_stat := zero32(15 downto PT_DEPTH) & pt_status.taddr
& pt_status.armed & ptta_trans.enable & pt_status.wrap & "0"
& conv_std_logic_vector(PT_DEPTH, 8)
& "00" & ar.atpt_trans.stop & ar.atpt_trans.start;
av.debug_pr := pr.debug;
av.apb_pr_conf_0_pta_map := pr.conf(0).pta_map;
prdata := (others => '0');
apbaddr := apbi.paddr(6 downto 2);
if iotest/=0 and iotmact='0' then av.debuga(5 downto 0) := "000000"; end if;
if (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(7) = '0' then -- PCI core and DMA
case apbaddr is
when "00000" => -- 0x00 Control
prdata(31 downto 29) := ar.atp_trans.rst(2 downto 0);
prdata( 28) := '0';
prdata( 27) := ar.irq.system_en;
prdata( 26) := ar.s.parerren;
prdata( 25) := ar.s.erren;
prdata( 24) := ar.irq.access_en;
prdata(23 downto 16) := ar.s.cfg_bus;
prdata(15 downto 12) := (others => '0'); -- RESERVED
prdata( 11) := ar.atp_trans.mstswdis;
prdata(10 downto 9) := ar.s.io_cfg_burst;
prdata( 8) := ar.irq.device_force;
prdata( 7 downto 4) := ar.irq.device_mask;
prdata( 3 downto 0) := ar.irq.host_mask;
if apbi.pwrite = '1' then
av.atp_trans.rst(2) := apbi.pwdata(31);
av.atp_trans.rst(1 downto 0) := ar.atp_trans.rst(1 downto 0) or apbi.pwdata(30 downto 29);
av.irq.system_en := apbi.pwdata( 27);
av.s.parerren := apbi.pwdata( 26);
av.s.erren := apbi.pwdata( 25);
av.irq.access_en := apbi.pwdata( 24);
av.s.cfg_bus := apbi.pwdata(23 downto 16);
-- := apbi.pwdata(15 downto 12);
av.atp_trans.mstswdis:= apbi.pwdata( 11);
av.s.io_cfg_burst := apbi.pwdata(10 downto 9);
av.irq.device_force := apbi.pwdata( 8);
av.irq.device_mask := apbi.pwdata( 7 downto 4);
av.irq.host_mask := apbi.pwdata( 3 downto 0);
end if;
when "00001" => -- 0x04 Status
prdata(31) := (pta_trans.ca_host and not ar.s.fakehost);
prdata(30) := conv_std_logic(master/=0);
prdata(29) := conv_std_logic(target/=0);
prdata(28) := conv_std_logic(dma/=0);
prdata(27) := conv_std_logic(deviceirq/=0);
prdata(26) := conv_std_logic(hostirq/=0);
prdata(25 downto 24) := conv_std_logic_vector(irqmode, 2);
prdata(23) := conv_std_logic(tracebuffer/=0);
prdata(22 downto 22) := (others => '0'); -- RESERVED
prdata( 21) := ar.s.fakehost;
prdata(20 downto 19) := ar.s.cfg_status;
prdata(18 downto 17) := ar.irq.system_status;
prdata(16 downto 12) := ar.dma.irqstatus & ar.irq.access_status;
prdata(11 downto 8) := ar.irq.host_status;
prdata( 7 downto 5) := (others => '0');-- conv_std_logic_vector(dma_fifo_depth, 2);
prdata( 4 downto 2) := conv_std_logic_vector(fifo_depth, 3);
prdata( 1 downto 0) := conv_std_logic_vector(fifo_count, 2);
if apbi.pwrite = '1' then
av.s.fakehost := ar.s.fakehost xor apbi.pwdata(21);
av.s.cfg_status(0) := ar.s.cfg_status(0) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.s.cfg_status(1) := ar.s.cfg_status(1) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.atp_trans.pa_discardtout_rst := ar.atp_trans.pa_discardtout_rst or apbi.pwdata(18);
av.atp_trans.pa_serr_rst := ar.atp_trans.pa_serr_rst or apbi.pwdata(17);
av.dma.irqstatus := ar.dma.irqstatus and not apbi.pwdata(16 downto 15);
av.irq.access_status := ar.irq.access_status and not apbi.pwdata(14 downto 12);
end if;
when "00010" => -- 0x08 AHB slave burst lenght and AHB-master mask
if apbi.pwrite = '1' then
av.s.blen := apbi.pwdata(7 downto 0);
av.s.blenmask := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.blenmask & zero32(15 downto 8) & ar.s.blen;
when "00011" => -- 0x0c AHB to PCI IO map
if apbi.pwrite = '1' then
av.s.io_map := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.io_map & zero32(15 downto 0);
when "00100" => -- 0x10 DMA Control
if apbi.pwrite = '1' then
av.dma.irqch := ar.dma.irqch and not apbi.pwdata(19 downto 12);
av.dma.errstatus := ar.dma.errstatus and not apbi.pwdata(11 downto 7);
if apbi.pwdata(31) = '1' then -- Safety guard for update of control fields
av.dma.numch := apbi.pwdata(6 downto 4);
av.dma.irqen := apbi.pwdata(1);
end if;
av.dma.en := (ar.dma.en and not apbi.pwdata(2)) or apbi.pwdata(0); -- bit[2] = disable/stop bit[0] = enable/start
end if;
prdata(31) := '1';
prdata(30 downto 0) := (others => '0');
prdata(19 downto 12) := ar.dma.irqch;
prdata(11 downto 7) := ar.dma.errstatus;
prdata(6 downto 4) := ar.dma.numch;
prdata(3) := ar.dma.running;
prdata(2) := '0';
prdata(1) := ar.dma.irqen;
prdata(0) := ar.dma.en;
when "00101" => -- 0x14 DMA Data desc
if apbi.pwrite = '1' then
av.dma.desc.addr(31 downto 4) := apbi.pwdata(31 downto 4);
end if;
prdata(31 downto 0) := ar.dma.desc.addr;
when "00110" => -- 0x18 DMA Channel desc
prdata(31 downto 0) := ar.dma.desc.ch;
when "00111" => -- 0x1c Reserved
prdata(31 downto 0) := ar.debuga;
if apbi.pwrite = '1' then
av.debuga := apbi.pwdata;
end if;
when "01000" => -- 0x20 PCI BAR0 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(0);
when "01001" => -- 0x24 PCI BAR1 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(1);
when "01010" => -- 0x28 PCI BAR2 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(2);
when "01011" => -- 0x2c PCI BAR3 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(3);
when "01100" => -- 0x30 PCI BAR4 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(4);
when "01101" => -- 0x34 PCI BAR5 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(5);
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug_pr;
when "10000" => -- 0x40 AHB master00 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(0)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(0)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(0);
when "10001" => -- 0x44 AHB master01 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(1)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(1)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(1);
when "10010" => -- 0x48 AHB master02 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(2)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(2)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(2);
when "10011" => -- 0x4c AHB master03 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(3)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(3)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(3);
when "10100" => -- 0x50 AHB master04 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(4)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(4)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(4);
when "10101" => -- 0x54 AHB master05 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(5)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(5)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(5);
when "10110" => -- 0x58 AHB master06 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(6)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(6)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(6);
when "10111" => -- 0x5c AHB master07 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(7)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(7)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(7);
when "11000" => -- 0x60 AHB master08 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(8)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(8)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(8);
when "11001" => -- 0x64 AHB master09 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(9)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(9)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(9);
when "11010" => -- 0x68 AHB master10 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(10)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(10)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(10);
when "11011" => -- 0x6c AHB master11 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(11)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(11)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(11);
when "11100" => -- 0x70 AHB master12 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(12)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(12)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(12);
when "11101" => -- 0x74 AHB master13 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(13)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(13)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(13);
when "11110" => -- 0x78 AHB master14 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(14)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(14)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(14);
when "11111" => -- 0x7c AHB master15 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(15)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(15)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(15);
when others =>
prdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case apbaddr is
when "00000" => -- 0x80 PCI trace control & status
if apbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or apbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or apbi.pwdata(1);
end if;
prdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if apbi.pwrite = '1' then
av.atpt_trans.mode := apbi.pwdata(27 downto 24);
av.atpt_trans.tcount := apbi.pwdata(23 downto 16);
av.atpt_trans.count := apbi.pwdata(PT_DEPTH-1 downto 0);
end if;
prdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if apbi.pwrite = '1' then
av.atpt_trans.ad := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if apbi.pwrite = '1' then
av.atpt_trans.admask := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if apbi.pwrite = '1' then
av.atpt_trans.sig := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if apbi.pwrite = '1' then
av.atpt_trans.sigmask := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
prdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
prdata(19 downto 0) := ptta_trans.dbg_sig & "000";
prdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
prdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
prdata(31 downto 8) := (others => '0');
prdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
prdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
apbo.pirq <= pirq;
apbo.prdata <= prdata;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-- --------------------------------------------------------------------------------
-- APB DEBUG Slave
-- --------------------------------------------------------------------------------
tb_ren <= ar.s.tb_ren;
tb_addr <= ar.s.haddr;
tbpirq := (others => '0');
tbprdata := (others => '0');
tbapbaddr := tbapbi.paddr(6 downto 2);
if tbapben = 1 then
if (tbapbi.psel(tbpindex) and tbapbi.paddr(17)) = '1' then
tb_ren <= '1'; tb_addr <= tbapbi.paddr;
end if;
if (tbapbi.psel(tbpindex) and tbapbi.penable) = '1' then
if tbapbi.paddr(17) = '1' then
if tbapbi.paddr(16) = '0' then
tbprdata := pt_fifoo_ad.data;
else
tbprdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
if tbapbi.paddr(7) = '0' then -- PCI core and DMA
case tbapbaddr is
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug_pr;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case tbapbaddr is
when "00000" => -- 0x80 PCI trace control & status
if tbapbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or tbapbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or tbapbi.pwdata(1);
end if;
tbprdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if tbapbi.pwrite = '1' then
av.atpt_trans.mode := tbapbi.pwdata(27 downto 24);
av.atpt_trans.tcount := tbapbi.pwdata(23 downto 16);
av.atpt_trans.count := tbapbi.pwdata(PT_DEPTH-1 downto 0);
end if;
tbprdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.ad := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if tbapbi.pwrite = '1' then
av.atpt_trans.admask := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.sig := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if tbapbi.pwrite = '1' then
av.atpt_trans.sigmask := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
tbprdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
tbprdata(19 downto 0) := ptta_trans.dbg_sig & "000";
tbprdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
tbprdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
tbprdata(31 downto 8) := (others => '0');
tbprdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
end if;
tbapbo.pirq <= tbpirq;
tbapbo.prdata <= tbprdata;
tbapbo.pconfig <= tbpconfig;
tbapbo.pindex <= tbpindex;
else
tbapbo <= apb_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB global signal assignments
-- --------------------------------------------------------------------------------
ahbso.hready <= ar.s.hready;
ahbso.hresp <= ar.s.hresp;
ahbso.hrdata <= ahbdrivedata(ar.s.hrdata);
ahbso.hindex <= hsindex;
ahbso.hconfig <= hconfig;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
if master = 0 then
ahbso <= ahbs_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB debug
-- --------------------------------------------------------------------------------
--[31:30] s_pending
--[29:28] s_empty
--[27:26] tm_pending
--[25:24] tm_empty
--[ :23] ms_acc_pending
--[ :22] ms_acc_cancel
--[ :21] ms_acc_done
--[ :20] tm_acc_pending
--[ :19] tm_acc_cancel
--[ :18] tm_acc_done
--[ :17] md_acc_pending
--[ :16] md_acc_cancel
--[ :15] md_acc_done
--[ :14] ..
--[13:12] dma_done
--[11:10] s_pending
--[ 9: 7] m_done
--[ 6: 4] dma.state
--[ 3: 2] m.state
--[ 1: 0] s.state
av.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
av.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
av.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
av.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
av.debug( 23) := ms_acc_pending;
av.debug( 22) := ms_acc_cancel;
av.debug( 21) := ms_acc_done;
av.debug( 20) := tm_acc_pending;
av.debug( 19) := tm_acc_cancel;
av.debug( 18) := tm_acc_done;
av.debug( 17) := md_acc_pending;
av.debug( 16) := md_acc_cancel;
av.debug( 15) := md_acc_done;
av.debug( 14) := '0';
av.debug(13 downto 12) := ar.dma.done;
av.debug(11 downto 10) := ar.s.pending;
av.debug( 9 downto 7) := ar.m.done;
case ar.dma.state is
when dma_idle => av.debug(6 downto 4) := "000";
when dma_read_desc => av.debug(6 downto 4) := "001";
when dma_next_channel => av.debug(6 downto 4) := "010";
when dma_write_status => av.debug(6 downto 4) := "011";
when dma_read => av.debug(6 downto 4) := "100";
when dma_write => av.debug(6 downto 4) := "101";
when dma_error => av.debug(6 downto 4) := "110";
end case;
case ar.m.state is
when am_idle => av.debug(3 downto 2) := "00";
when am_read => av.debug(3 downto 2) := "01";
when am_write => av.debug(3 downto 2) := "10";
when am_error => av.debug(3 downto 2) := "11";
when others => av.debug(3 downto 2) := "00";
end case;
case ar.s.state is
when as_idle => av.debug(1 downto 0) := "00";
when as_checkpcimst => av.debug(1 downto 0) := "01";
when as_read => av.debug(1 downto 0) := "10";
when as_write => av.debug(1 downto 0) := "11";
when others => av.debug(1 downto 0) := "00";
end case;
-- --------------------------------------------------------------------------------
-- AHB reset
-- --------------------------------------------------------------------------------
-- AHB master
lahbm_rst <= rst and not pci_target_rst and not pci_hard_rst;
if lahbm_rst = '0' then
av.m.state := am_idle;
av.m.acc.fifo_index := 0;
av.m.acc.pending := '0';
av.m.retry := '0';
av.m.dmai0.addr := (others => '0');
av.atp_trans.mstswdis := '0';
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done.done := '0';
for i in 0 to FIFO_COUNT-1 loop
av.atp_trans.tm_fifo(i).pending := (others => '0');
end loop;
av.atp_trans.tm_fifo_ack := (others => '0');
end if;
-- AHB slave
lahbs_rst <= rst and not pci_master_rst and not pci_hard_rst;
if lahbs_rst = '0' then
av.s.state := as_idle;
av.s.atp.index := 0;
av.s.pta.index := 0;
av.s.pending := (others => '0');
av.s.discard := '0';
av.s.start := '0';
av.s.cfg_bus := (others => '0');
av.s.cfg_status := (others => '0');
av.s.parerren := '0';
av.s.erren := '0';
av.s.blen := (others => '1');
av.s.blenmask := (others => '0');
av.s.io_cfg_burst := (others => '0');
av.s.fakehost := '0';
for i in 0 to 3 loop
av.s.accbuf(i).pending := '0';
end loop;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(0)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(0) := (others => '0');
av.atp_trans.msd_acc(0).pending := '0';
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
for i in 0 to 15 loop
if multifunc = 0 then
av.s.atp_map(i)(2 downto 0) := "000";
else
for j in 0 to multifunc loop
if masters_vector(j)(i) = '1' then
av.s.atp_map(i)(2 downto 0) := conv_std_logic_vector(j, 3);
end if;
end loop;
end if;
end loop;
end if;
-- DMA
if lahbs_rst = '0' then
av.dma.state := dma_idle;
av.dma.en := '0';
av.dma.irq := '0';
av.dma.irqen := '0';
av.dma.irqstatus := (others => '0');
av.dma.errstatus := (others => '0');
av.dma.irqch := (others => '0');
av.dma.desc.chid := (others => '0');
av.dma.dtp.index := 0;
av.dma.ptd.index := 0;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(1)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(1) := (others => '0');
av.atp_trans.msd_acc(1).pending := '0';
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
end if;
-- AHB reset
lahb_rst <= rst and not pci_hard_rst;
if lahb_rst = '0' then
if deviceirq = 1 then
av.irq.device_mask := conv_std_logic_vector(deviceirqmask, 4);
av.irq.device_force := '0';
end if;
if hostirq = 1 then
av.irq.host_mask := conv_std_logic_vector(hostirqmask, 4);
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl := (others => '0');
end if;
av.irq.irqen := '0';
av.irq.access_en := '0';
av.irq.access_status := (others => '0');
av.irq.system_en := '0';
av.irq.system_status := (others => '0');
av.atp_trans.pa_serr_rst := '0';
av.atp_trans.pa_discardtout_rst := '0';
-- APB (PCI trace)
av.atpt_trans.start := '0';
av.atpt_trans.stop := '1';
-- Soft reset
av.atp_trans.rst(1 downto 0) := (others => '0');
end if;
if rst = '0' then
-- Hard reset
av.atp_trans.rst(2) := '0';
if iotest /= 0 then
av.debuga(5 downto 0) := "000000";
end if;
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
av.m := amba_master_none;
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done := pci_g_acc_status_trans_none;
av.atp_trans.tm_fifo := pci_g_fifo_trans_vector_none;
av.atp_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
end if;
if master = 0 then -- PCI master disabled
av.s := amba_slave_none;
av.atp_trans.msd_acc(0) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
av.atp_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
end if;
if dma = 0 then -- DMA disabled
av.dma := dma_reg_none;
av.atp_trans.msd_acc(1) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
av.atp_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans := apb_to_pci_trace_trans_none;
end if;
-- --------------
arin <= av;
end process;
preg : process(pciclk, phyo)
begin
if rising_edge(pciclk) then
pr <= prin;
end if;
-- PHY =>
pr.po <= phyo.pr_po;
pr.m.state <= phyo.pr_m_state;
pr.m.last <= phyo.pr_m_last;
pr.m.hold <= phyo.pr_m_hold;
pr.m.term <= phyo.pr_m_term;
pr.t.hold <= phyo.pr_t_hold;
pr.t.stop <= phyo.pr_t_stop;
pr.t.abort <= phyo.pr_t_abort;
pr.t.diswithout <= phyo.pr_t_diswithout;
pr.t.addr_perr <= phyo.pr_t_addr_perr;
-- PHY <=
end process;
areg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
-- AHB master
target_ahbm0 : if target /= 0 generate
ahbm0 : grpci2_ahb_mst generic map (hindex => hmindex, devid => GAISLER_GRPCI2, version => REVISION)
port map (rst, clk, ahbmi, ahbmo_con, ar.m.dmai0, dmao0, disabled_dmai, open);
ahbmo <= ahbmo_con;
end generate;
no_target_ahbm0 : if target = 0 generate
ahbmo <= ahbm_none;
end generate;
dma_ahbm0 : if dma /= 0 generate
ahbm1 : grpci2_ahb_mst generic map (hindex => hdmindex, devid => GAISLER_GRPCI2_DMA, version => REVISION)
port map (rst, clk, ahbdmi, ahbdmo, ar.dma.dmai1, dmao1, disabled_dmai, open);
end generate;
no_dma_ahbm0 : if dma = 0 generate
ahbdmo <= ahbm_none;
end generate;
target_fifo0 : if target /= 0 generate
scan_prin_t_atp_ctrl_en <= (prin.t.atp.ctrl.en and not scanen);
scan_ar_m_acc_fifo_wen <= (ar.m.acc.fifo_wen and not scanen);
scan_arin_m_acc_fifo_ren <= (arin.m.acc.fifo_ren and not scanen);
scan_pr_t_pta_ctrl_en <= (pr.t.pta.ctrl.en and not scanen);
ft0 : if ft /= 0 generate
-- AHB master to PCI target FIFO
atp_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
tm_fifoo_atp.err, testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
tm_fifoo_pta.err, testin
);
-- AHB master to PCI target FIFO
end generate;
noft0 : if ft = 0 generate
atp_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
testin
);
end generate;
end generate;
master_fifo0 : if master /= 0 generate
scan_prin_m_acc_acc_sel_ahb_fifo_ren <= (prin.m.acc(acc_sel_ahb).fifo_ren and not scanen);
scan_ar_s_atp_ctrl_en <= (ar.s.atp.ctrl.en and not scanen);
scan_arin_s_pta_ctrl_en <= (arin.s.pta.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_ahb_fifo_wen <= (pr.m.acc(acc_sel_ahb).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
ms_fifoo_atp.err
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
ms_fifoo_pta.err
);
end generate;
noft0 : if ft = 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
testin
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
dma_fifo0 : if dma /= 0 generate
scan_prin_m_acc_acc_sel_dma_fifo_ren <= (prin.m.acc(acc_sel_dma).fifo_ren and not scanen);
scan_ar_dma_dtp_ctrl_en <= (ar.dma.dtp.ctrl.en and not scanen);
scan_arin_dma_ptd_ctrl_en <= (arin.dma.ptd.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_dma_fifo_wen <= (pr.m.acc(acc_sel_dma).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
md_fifoo_dtp.err, testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
md_fifoo_dtp.err, testin
);
end generate;
noft0 : if ft = 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
-- PCI trace
trace_fifo0 : if tracebuffer /= 0 generate
scan_tb_ren <= (tb_ren and not scanen);
scan_pr_ptta_trans_enable <= (pr.ptta_trans.enable and not scanen);
pt_fifo0 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_ad.data,
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pi.ad,
testin
);
pt_fifoo_ad.err <= (others => '0');
pt_fifo1 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 17, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_sig.data(16 downto 0),
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pcisig,
testin
);
pt_fifoo_sig.err <= (others => '0');
end generate;
-- IO test module
iotgen : if iotest /= 0 generate
iotm : synciotest
generic map (ninputs => 2, noutputs => 1, nbidir => 44)
port map (
clk => pciclk,
rstn => pcii.rst,
datain => iotmdin,
dataout => iotmdout,
tmode => ar.debuga(5 downto 0),
tmodeact => iotmact,
tmodeoe => iotmoe
);
end generate;
iotngen : if iotest = 0 generate
iotmdout <= (others => '0');
iotmact <= '0';
iotmoe <= '0';
end generate;
--pragma translate_off
bootmsg : report_version
generic map ("grpci2" & tost(hmindex) &
": 32-bit PCI/AHB bridge rev, " & tost(REVISION) &
", " & tost(2**FIFO_DEPTH) & "-word FIFOs" & ", PCI trace: " & tost(((2**PT_DEPTH)*conv_integer(conv_std_logic(tracebuffer/=0)))));
--pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out word; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end MMU;
architecture Behavioral of MMU is
-- Components
component ram_controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
write, read: in STD_LOGIC;
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(63 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end component;
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
component SPIFlashModule is
port(clk, reset, io_flash_en, io_flash_write, io_read_id: in std_logic;
io_quad_io: in std_logic_vector(3 downto 0);
io_flash_addr: in std_logic_vector(23 downto 0);
io_flash_data_in: in std_logic_vector(31 downto 0);
io_flash_data_out: out std_logic_vector(31 downto 0);
io_state_to_cpu: out std_logic_vector(11 downto 0);
io_sck_gate, io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: out std_logic);
end component;
constant ROM_period : integer := 150;
type instsmem is array(0 to 100) of word;
signal instr_mem: instsmem := (others => (others => '0'));
signal ROM_mem: instsmem := (
0 => x"00001137",
1 => x"8071011b",
2 => x"01411113",
3 => x"0040006f",
4 => x"01300793",
5 => x"01b79793",
6 => x"00100713",
7 => x"00e79023",
8 => x"098017b7",
9 => x"00000697",
10 => x"09468693",
11 => x"02100713",
12 => x"00479793",
13 => x"00100593",
14 => x"0047c603",
15 => x"0ff67613",
16 => x"fe060ce3",
17 => x"00e781a3",
18 => x"00b782a3",
19 => x"00168693",
20 => x"0006c703",
21 => x"fe0712e3",
22 => x"09801737",
23 => x"01300513",
24 => x"00100693",
25 => x"00471713",
26 => x"00100593",
27 => x"01b51513",
28 => x"00174783",
29 => x"0ff7f793",
30 => x"fe078ce3",
31 => x"00074603",
32 => x"0016869b",
33 => x"03069693",
34 => x"00b70123",
35 => x"0306d693",
36 => x"0ff67613",
37 => x"00d51023",
38 => x"00474783",
39 => x"0ff7f793",
40 => x"fe078ce3",
41 => x"00c701a3",
42 => x"00b702a3",
43 => x"fc5ff06f",
46 => x"45212121",
47 => x"204F4843",
48 => x"56524553",
49 => x"45522121",
50 => x"0000A021",
others => (others => '0'));
-- SPI signals
signal io_flash_en: std_logic;
signal io_flash_write: std_logic;
signal io_quad_io: std_logic_vector(3 downto 0);
signal io_flash_addr: std_logic_vector(23 downto 0);
signal io_flash_data_in: std_logic_vector(31 downto 0);
signal io_flash_data_out: std_logic_vector(31 downto 0);
signal io_read_id: std_logic;
signal io_state_to_cpu: std_logic_vector(11 downto 0);
signal io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: std_logic;
signal io_srl, io_cr : std_logic_vector(7 downto 0);
signal io_sckgate: std_logic;
signal io_rst: std_logic;
type MMU_state is (idle, loading, storing, fetching, decode_state,page_walk,loading_ram_page_walk, loading_ram, loading_rom, done_uart_rx, done_uart_tx, storing_ram);
signal curr_state: MMU_state := idle;
signal next_state: MMU_state := idle;
signal paused_state : MMU_state := idle; --Bit of a misnomer, this is
signal LED_reg: std_logic_vector(15 downto 0);
-- RAM signals
signal w_en: std_logic := '0';
signal RAM_en, ROM_en: std_logic := '0';
type RAM_state is (idle, read_low, read_low_mid, read_upper_mid, read_upper,write_low, write_low_mid, write_upper_mid, write_upper, done);
signal RAM_curr_state : RAM_state := idle;
signal RAM_next_state : RAM_state := idle;
signal RAM_masks: std_logic_vector(7 downto 0);
signal RAM_timeout_counter: integer:= 0;
signal RAM_data_in: std_logic_vector(15 downto 0);
signal RAM_data_out: std_logic_vector(15 downto 0);
signal RAM_address_in: std_logic_vector(26 downto 0);
signal RAM_lb, RAM_ub: std_logic := '1';
signal s_RAM_data_out: doubleword := (others => '0'); -- The register holding the ram doubleword
signal ROM_done, RAM_done: std_logic := '0';
signal BRAM_toggle : std_logic_vector(1 downto 0) := "00";
--32 Bits acceses for ROM, either, too slow
type ROM_state is (idle, reading_lower, reading_higher, done);
signal ROM_curr_state : ROM_state := idle;
signal ROM_next_state : ROM_state := idle;
signal gated_clk: std_logic := '0';
signal s_ROM_data_out: doubleword := (others => '0'); --Register holding the rom doubleword
signal ROM_address_in : std_logic_vector(23 downto 0);
signal s_ROM_done: std_logic;
-- UART out data signal, for reading UART registers
signal ROM_Counter: integer := 0;
signal UART_out: STD_LOGIC_VECTOR(7 downto 0);
signal UART_toggle : std_logic := '0';
signal SATP_mode: std_logic_vector(63 downto 0) := (others => '0');
signal SATP_PPN: std_logic_vector(63 downto 0) := (others => '0');
signal s_internal_data : std_logic_vector(63 downto 0);
signal s_internal_address: doubleword;
signal clk_100, clk_200, clk_25, locked: std_logic;
signal page_address_in: doubleword := (others => '0');
signal uart_data_in, uart_data_out: std_logic_vector(7 downto 0);
signal uart_data_available, uart_ready: std_logic;
signal uart_reset_read, uart_send: std_logic;
signal UART_data: doubleword;
signal m_timer: integer := 0;
Type PAGE_WALK_STATE is (idle,level_i_read, level_i_decode, done);
signal PAGE_WALK_next_state, PAGE_WALK_current_state: PAGE_WALK_STATE := idle;
signal s_page_walk,page_walk_request_read, page_walk_done: std_logic := '0';
signal page_walk_address_out, page_address_final: doubleword;
signal Intermitent_Address_In: doubleword;
signal addr_in_latch: doubleword;
-- Debugging
signal s_debugging_out: std_logic_vector(5 downto 0);
signal qd: std_logic_vector(3 downto 0);
signal gated_clock, clock_gate: std_logic;
signal io_sck_gate: std_logic;
begin
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => clk_100,
clk_200MHz_o => clk_200,
clk_25MHz_o => clk_25,
locked => locked
);
myRAMController: ram_controller port map
(
clk_200 => clk_200,
clk_100 => clk_100,
rst => rst,
data_in => RAM_data_in,
data_out => RAM_data_out,
mask_lb => RAM_lb,
mask_ub => RAM_ub,
done => RAM_done,
write => w_en,
read => RAM_en,
contr_addr_in => RAM_address_in,
ddr2_addr => ddr2_addr ,
ddr2_ba => ddr2_ba ,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p ,
ddr2_ck_n => ddr2_ck_n ,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
--myROMController: ROM_controller_SPI port map(clk_25 => clk_25, rst => io_rst, read =>io_flash_en,
-- address_in => ROM_address_in, data_out => io_flash_data_out,
-- si_i =>io_SI, wp => io_WP, si_t => io_tri_si, wp_t => io_tri_wp,
-- cs_n => io_cs, qd => qd, done =>s_ROM_done);
myROMController: SPIFlashModule port map(
clk => clk_25, reset => io_rst, io_flash_en => io_flash_en, io_flash_write => io_flash_write, io_read_id => io_read_id,
io_quad_io => qd, io_flash_addr => ROM_address_in, io_flash_data_in => io_flash_data_in,
io_flash_data_out => io_flash_data_out, io_state_to_cpu => io_state_to_cpu,
io_sck_gate => io_sckgate, io_SI => io_SI, io_WP => io_WP, io_tri_si => io_tri_si, io_tri_wp => io_tri_wp, io_cs => io_cs,
io_ready => io_ready);
cs_n <= io_cs;
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => CLK,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
MMU_FSM: process(clk, rst)
-- variable s_internal_address: doubleword := (others => '0'); --Realized Physical Address
-- variable paused_state: MMU_state; -- When we find the mode from SATP, we resume from the state saved here
begin
if rst = '1' then
--curr_state <= idle;
-- ROM_curr_state <= idle;
RAM_curr_state <= idle;
PAGE_WALK_current_state <= idle;
m_timer <= 0;
instr_out <= (others => '0');
error <= (others => '0');
io_flash_write <= '0';
io_read_id <= '0';
next_state <= idle;
busy <= '0';
BRAM_toggle <= "11";
LED <= (others => '0');
UART_data <= (others => '0');
data_out <= (others => '0');
elsif(rising_edge(clk)) then
--curr_state <= next_state;
RAM_curr_state <= RAM_next_state;
-- ROM_curr_state <= ROM_next_state;
PAGE_WALK_current_state <= PAGE_WALK_next_state;
m_timer <= m_timer + 1;
busy <= '1';
--next_state <= curr_state;
case next_state is
-- Idling by like the leech you are MMU arent U
when idle =>
busy <= '1';
UART_toggle <= '0';
s_debugging_out <= "000000";
--s_internal_address <= addr_in;
uart_reset_read <= '0';
uart_send <= '0';
if(load = '1') then
next_state <= decode_state;
paused_state <= loading;
ROM_curr_state <= idle;
s_internal_address <= addr_in;
elsif(store = '1') then
next_state <= decode_state;
paused_state <= storing;
s_internal_address <= addr_in;
elsif(ready_instr = '1') then
next_state <= decode_state;
s_internal_address <= addr_instr;
paused_state <= fetching;
else
busy <= '0';
end if;
-- Figure out what state are we at
when decode_state =>
s_debugging_out <= "000001";
case satp_mode(3 downto 0) is
when x"0" => -- No translation is assumed
next_state <= paused_state;
when others =>
next_state <= page_walk; --SV39 is assumed whenever anything else is written, no SV48 shenanigans
end case;
-- Walk the thing blue page walk line
when page_walk =>
s_debugging_out <= "000010";
s_page_walk <= '1'; --We enable the page walk process
if(page_walk_done = '1') then --Page walk is done
s_internal_address <= page_walk_address_out; -- We assign the newly discovered address
next_state <= paused_state; --Resume wherever we left off matey
elsif(page_walk_request_read = '1') then
RAM_en <= '1';
end if;
-- Intermediate fetching state, just check if there is any misalignment errors
when fetching =>
busy <= '1';
s_debugging_out <= "000011";
--Fetches have to be aligned
if(unsigned(s_internal_address) mod 4 > 0) then
error(4) <= '1'; -- Misaligned error, geback geback
next_state <= idle;
elsif( s_internal_address(31 downto 16) = x"0000" ) then
next_state <= idle;
instr_out <= instr_mem(to_integer(unsigned(addr_instr(31 downto 0)))/4);
else
--s_internal_address <= std_logic_vector(unsigned(addr_instr)/2);
next_state <= loading; --Loading instructions from elsewhere
end if;
-- Loading states
when loading =>
s_debugging_out <= "000100";
if(s_internal_address(31 downto 16) = x"0000" ) then --BRAM
next_state <= idle; --Instruction already goes out here, so no need to do anything,
-- We do this to preserve the instr_out port, even though it's really not necesary.
elsif(s_internal_address(31 downto 16) = x"9801") then --UART Registers
next_state <= idle; -- By default go to idle
UART_toggle <= '1';
case s_internal_address(3 downto 0) is
when X"0" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_in;
when X"1" => data_out <= zero_word & zero_word(31 downto 1) & uart_data_available;
when X"2" => data_out <= zero_word & zero_word(31 downto 1) & uart_reset_read;
when X"3" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_out;
when X"4" => data_out <= zero_word & zero_word(31 downto 1) & uart_ready;
when X"5" => data_out <= zero_word & zero_word(31 downto 1) & uart_send;
when others => NULL;
end case;
elsif(s_internal_address(31 downto 24) = x"98") then --LEDS Registers
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock Register
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"9") then --ROM
if(paused_state = fetching) then
instr_out <= ROM_mem(to_integer(unsigned(addr_instr(23 downto 0)))/4);
else
case alignment is
when "0000" =>
when "0001" => --Load byte
if(unsigned(s_internal_address(23 downto 0)) mod 4 = 0) then
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 1) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(15 downto 8);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 2) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(23 downto 16);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 3) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(31 downto 24);
end if;
when "0010" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when "0100" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when "1000" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when others =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
end case;
--data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
ROM_curr_state <= done;
end if;
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= loading_ram;
-- ROM_counter <= 0;
else
next_state <= idle;
end if;
-- Special load cases
when loading_rom =>
s_debugging_out <= "000101";
ROM_en <= '1';
if(ROM_counter > (2 * ROM_period)) then
ROM_en <= '0';
if(paused_state = fetching) then
instr_out <= s_ROM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
when loading_ram =>
s_debugging_out <= "000110";
RAM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= s_RAM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
-- Stores and such
when storing =>
s_debugging_out <= "000111";
next_state <= idle; -- By default go back
if(addr_in(31 downto 16) = x"9801") then --UART
case addr_in(3 downto 0) is
when X"0" => NULL; -- Nothing here really, why would you write to buffer in?
when X"1" => NULL; -- Why?
when X"2" => uart_reset_read <= '1';
next_state <= done_uart_rx;
when X"3" => uart_data_out <= data_in(7 downto 0);
when X"4" => NULL; -- No no no write
when X"5" => uart_send <= '1'; -- Assuming if you are writing is to send something
next_state <= done_uart_tx; -- After writing to this register we reset it automatically
when others => UART_data <= (others => '0');
end case;
elsif(addr_in(31 downto 24) = x"98") then --LEDS
LED <= data_in(15 downto 0) OR data_in(31 downto 16);
next_state <= idle;
elsif(addr_in(31 downto 24) = x"97") then --m_clock
next_state <= idle;
-- elsif(addr_in(31 downto 28) = x"9") then --ROM
-- next_state <= idle; --Can't write to ROM, I mean you could, but hwhy? Don't write to ROM
elsif(addr_in(31 downto 28) = x"8") then --RAM
next_state <= storing_ram;
end if;
-- Special stores section
when storing_ram =>
s_debugging_out <= "001000";
w_en <= '1';
if(RAM_done = '1') then
w_en <= '0';
next_state <= idle;
end if;
-- Special done states, to reset whatever needs to be reset
when done_uart_tx =>
uart_send <= '0';
if(uart_ready = '0') then
next_state <= done_uart_tx;
else
next_state <= idle;
end if;
when done_uart_rx =>
uart_reset_read <= '0';
next_state <= idle;
when others =>
end case;
end if;
end process;
-- Walk the page
PAGE_WALK_FSM: process(clk, rst, s_page_walk)
variable level: Integer := 0;
begin
if(rst = '1') then
elsif(rising_edge(clk)) then
PAGE_WALK_next_state <= PAGE_WALK_current_state;
case PAGE_WALK_current_state is
when idle =>
if(s_page_walk = '1') then
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & addr_in(31 downto 22) & "00";--SATP PPN will give us the root page table location
PAGE_WALK_next_state <= level_i_read;
level := 0; --Start at level 0
end if;
when level_i_read =>
if(level < 3) then
page_walk_request_read <= '1';
if(RAM_done = '1') then
level := level + 1;
PAGE_WALK_next_state <= level_i_decode;
end if;
else
--Raise exception here
--More levels than 3
PAGE_WALK_next_state <= done;
end if;
when level_i_decode =>
PAGE_WALK_next_state <= idle;
if(s_RAM_data_out(0) = '0') then --Invalid PTE Raise the roof
NULL;
elsif(s_RAM_data_out(1) = '0' and s_RAM_data_out(7) = '1') then -- Not Valid and Dirty
NULL;
elsif(s_RAM_data_out(1) = '1' or s_RAM_data_out(3) = '1') then --So far this address is final
-- Check if the PTE is in user mode and we are in user mode
if(mode = "00" and s_RAM_data_out(4) = '1') then
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
-- If the PTE U bit is '0' and we are in Supervisor mode, it's still good
-- We leave this separate in case other actions need to happen in S mode
elsif(mode = "01" and s_RAM_data_out(4) = '0') then
-- If PTE A is 0 or PTE D is 0 and we are storing, then we could raise an exception
-- or set the bits to 1 ourselves
if(s_RAM_data_out(6) = '0' or (paused_state = storing and s_RAM_data_out(7) = '0')) then
-- Raise exception
end if;
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
else
page_walk_next_state <= idle;
--Raise exception when the user has no permission to access this PTE
end if;
page_walk_done <= '1';
else -- We still have to dig deeper m8
page_walk_next_state <= level_i_read;
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & s_internal_address(31 downto 22) & "00";
end if;
when done =>
PAGE_WALK_next_state <= idle;
end case;
end if;
end process;
--busy <= '0' when curr_state = idle else '1';
-- Z high impedance
dq(0) <= 'Z' when io_tri_si = '1' else io_SI;
dq(1) <= 'Z';
dq(2) <= 'Z' when io_tri_wp = '1' else io_WP;
dq(3) <= 'Z';
qd(0) <= dq(0) when io_tri_si = '1' else 'Z';
qd(1) <= dq(1);
qd(2) <= dq(2) when io_tri_wp = '1' else 'Z';
qd(3) <= dq(3);
gated_clock <= '0' when gated_clk = '1' else not(clk_25);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 10.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => gated_clock, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);
-- ROM SPI Clock Generation
ROM_CLK: process(clk_25, rst) begin
if(rst = '1') then
gated_clk <= '1';
elsif(rising_edge(clk_25)) then
if (io_cs = '0') then
gated_clk <= '0';
else
gated_clk <= '1';
end if;
end if;
end process;
---- ROM State Machine
---- To enable rom set ROM_en high
---- Will wait for 600 cycles and give back a 64 bit word
--ROM_FSM: process(clk,rst)
-- begin
-- if(rst = '1') then
-- io_rst <= '1';
-- ROM_next_state <= idle;
-- elsif(rising_edge(clk)) then
-- ROM_next_state <= ROM_curr_state;
-- case ROM_curr_state is
-- when idle =>
-- ROM_next_state <= idle;
-- ROM_counter <= 0;
-- io_rst <= '0';
-- if(ROM_en = '1') then
-- ROM_done <= '0';
-- --io_rst <= '0';
-- ROM_address_in <= s_internal_address(23 downto 0); --24 Bits in
-- ROM_next_state <= reading_lower;
-- end if;
-- when reading_lower =>
-- ROM_next_state <= reading_lower;
-- io_flash_en <= '1';
-- ROM_counter <= ROM_counter + 1; -- Wait a good amount of time to let the device react
-- if(ROM_counter > ROM_period) then
-- s_ROM_data_out(31 downto 0) <= io_flash_data_out;
-- ROM_next_state <= reading_higher;
-- ROM_address_in <= std_logic_vector(unsigned(s_internal_address(23 downto 0)) + 4); --24 Bits in
-- end if;
-- when reading_higher =>
-- ROM_next_state <= reading_higher;
-- ROM_counter <= ROM_counter + 1; -- Wait a good amount of time to let the device react
-- if(ROM_counter > ROM_period * 2) then
-- s_ROM_data_out(63 downto 32) <= io_flash_data_out;
-- ROM_next_state <= done;
-- end if;
-- when done =>
-- ROM_done <= '1';
-- if(ROM_en <= '0') then
-- ROM_next_state <= idle;
-- end if;
-- io_rst <= '1';
-- end case;
-- end if;
--end process;
-- RAM State Machine
-- For reading from RAM, the ideal waiting time is of 230 ns
-- For writing into RAM, the ideal waiting time is of 270 ns
-- To make things easier we use 300 ns for both cases.
RAM_FSM: process(clk, RAM_en, w_en)
variable RAM_counter :integer := 0;
begin
if(rising_edge(clk)) then
if(RAM_curr_state /= idle) then
RAM_counter := RAM_counter + 1;
else
RAM_counter := 0;
end if;
RAM_next_state <= RAM_curr_state;
-- Forget about it
-- If for whatever reason we take long than
-- 1200 cycles, timeout and throw some error
if(RAM_timeout_counter >= 1200) then
RAM_next_state <= idle;
else
case RAM_curr_state is
-- Idle state, read before write
when idle =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_en = '1') then
RAM_next_state <= read_low;
elsif(w_en = '1') then
RAM_next_state <= write_low;
end if;
-- Load States
when read_low =>
if(RAM_counter > 30) then
s_RAM_data_out(15 downto 0) <= RAM_data_out;
RAM_next_state <= read_low_mid;
RAM_counter := 0;
end if;
when read_low_mid =>
if(RAM_counter > 30) then --Valid Data
s_RAM_data_out(31 downto 16) <= RAM_data_out;
RAM_next_state <= read_upper_mid;
RAM_counter := 0;
end if;
when read_upper_mid =>
if(RAM_counter > 30) then
s_RAM_data_out(47 downto 32) <= RAM_data_out;
RAM_next_state <= read_upper;
RAM_counter := 0;
end if;
when read_upper =>
if(RAM_counter > 30) then
s_RAM_data_out(63 downto 48) <= RAM_data_out;
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- Store States (LSB first)
-- Bytes 1 and 2
when write_low =>
--Alignment 0001 means Byte-wise access
if(alignment(0) = '1') then
RAM_ub <= '0'; --Disable the upper byte from controller
end if;
if(RAM_counter > 30) then
if(alignment(0) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_low_mid;
end if;
RAM_counter := 0;
-- Alignment 0100 means Upper Word access
elsif(alignment(2) = '1') then
RAM_counter := 0;
RAM_next_state <= write_upper_mid;
end if;
-- Byte 3 and 4
when write_low_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then --Valid Data
-- Alignment 0010 is Lower Word access
if(alignment(1) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_upper_mid;
RAM_counter := 0;
end if;
end if;
-- Bytes 5 and 6
when write_upper_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= write_upper;
RAM_counter := 0;
end if;
when write_upper =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- We are done here
when others =>
RAM_next_state <= idle;
end case;
end if;
end if;
end process;
-- Latches the last obtained datas (dati, datum? datae?)
--LAST_OBTAINED_DATA: process(clk,rst, UART_toggle) begin
-- if(rst = '1') then
-- data_out <= (others => '0');
-- elsif(rising_edge(clk)) then
-- if(RAM_curr_state = done) then
-- data_out <= s_RAM_data_out;
-- elsif(ROM_curr_state = done) then
-- data_out <= s_ROM_data_out;
-- elsif(UART_toggle = '1') then
-- data_out(7 downto 0) <= UART_data(7 downto 0);
-- data_out(63 downto 8) <= (others => '0');
-- end if;
-- end if;
--end process;
-- Muxes for addresses and data
-- Intermitent address is internal RAM address, whenever we need to use the RAM
-- to access something else, we will make use of this intermitent_address_in signal
Intermitent_Address_In <= addr_in when s_page_walk = '0' else page_address_in;
s_internal_data <= data_in; --For the moment this is right
-- Might change this to sequential logic if needed, I don't think it necessary
RAM_address_in <= std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 0) when RAM_curr_state = idle or RAM_curr_state = read_low or RAM_curr_state = write_low else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 2) when RAM_curr_state = read_low_mid or RAM_curr_state = write_low_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 4) when RAM_curr_state = read_upper_mid or RAM_curr_state = write_upper_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 6) when RAM_curr_state = read_upper or RAM_curr_state = write_upper
else (others => '0');
RAM_data_in <= s_internal_data(15 downto 0 ) when RAM_curr_state = idle or RAM_curr_state = write_low else
s_internal_data(31 downto 16) when RAM_curr_state = write_low_mid else
s_internal_data(47 downto 32) when RAM_curr_state = write_upper_mid else
s_internal_data(63 downto 48) when RAM_curr_state = write_upper else
(others => '0');
-- The CSR telling us where the page table start
SATP_mode(3 downto 0) <= satp(63 downto 60);
SATP_PPN(43 downto 0) <= satp(43 downto 0);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if rising_edge(clock) then
if rising_edge(clock) then
A <= '0';
end if;
end if;
end process;
end behv;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if rising_edge(clock) then
if rising_edge(clock) then
A <= '0';
end if;
end if;
end process;
end behv;
|
-- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop - syn
-- Description: simple stand-alone tester for fx2lib components
--
-- Dependencies: comlib/byte2word
-- comlib/word2byte
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop is -- tester for fx2lib components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end tst_fx2loop;
architecture syn of tst_fx2loop is
type regs_type is record
rxdata : slv16; -- next rx word
txdata : slv16; -- next tx word
tx2data : slv16; -- next tx2 word
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- tx2data
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- tx2cnt
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RXWDATA : slv16 := (others=>'0');
signal RXWVAL : slbit := '0';
signal RXWHOLD : slbit := '0';
signal RXODD : slbit := '0';
signal TXWDATA : slv16 := (others=>'0');
signal TXWENA : slbit := '0';
signal TXWBUSY : slbit := '0';
signal TXODD : slbit := '0';
signal TX2WDATA : slv16 := (others=>'0');
signal TX2WENA : slbit := '0';
signal TX2WBUSY : slbit := '0';
signal TX2ODD : slbit := '0';
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
signal TXENA_L : slbit := '0'; -- local copy of out port signal
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
begin
CNTL_RESET_L <= '0'; -- so far unused
RXB2W : byte2word
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => RXDATA,
ENA => RXVAL,
BUSY => RXHOLD_L,
DO => RXWDATA,
VAL => RXWVAL,
HOLD => RXWHOLD,
ODD => RXODD
);
TX1W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TXWDATA,
ENA => TXWENA,
BUSY => TXWBUSY,
DO => TXDATA,
VAL => TXENA_L,
HOLD => TXBUSY,
ODD => TXODD
);
TX2W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TX2WDATA,
ENA => TX2WENA,
BUSY => TX2WBUSY,
DO => TX2DATA,
VAL => TX2ENA_L,
HOLD => TX2BUSY,
ODD => TX2ODD
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY,
RXHOLD_L, TXBUSY, TX2BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxwhold : slbit := '1';
variable itxwena : slbit := '0';
variable itxwdata : slv16 := (others=>'0');
variable itx2wena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irxwhold := '1';
itxwena := '0';
itxwdata := RXWDATA;
itx2wena := '0';
if HIO_CNTL.throttle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXWVAL='1' and r.rxthrottle='0' then
irxwhold := '0';
if RXWDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := slv(unsigned(RXWDATA) + 1);
end if;
when c_mode_txblast =>
itxwdata := r.txdata;
if TXWBUSY = '0' then
itxwena := '1';
n.txdata := slv(unsigned(r.txdata) + 1);
end if;
irxwhold := '0';
when c_mode_loop =>
itxwdata := RXWDATA;
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
irxwhold := '0';
itxwena := '1';
end if;
when others => null;
end case;
if HIO_CNTL.tx2blast = '1' then
if TX2WBUSY = '0' then
itx2wena := '1';
n.tx2data := slv(unsigned(r.tx2data) + 1);
end if;
end if;
if RXWVAL='1' and irxwhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxwena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
if itx2wena = '1' then
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
end if;
N_REGS <= n;
RXWHOLD <= irxwhold;
TXWENA <= itxwena;
TXWDATA <= itxwdata;
TX2WENA <= itx2wena;
TX2WDATA <= r.tx2data;
HIO_STAT.rxhold <= RXHOLD_L;
HIO_STAT.txbusy <= TXBUSY;
HIO_STAT.tx2busy <= TX2BUSY;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.tx2cnt <= r.tx2cnt;
end process proc_next;
RXHOLD <= RXHOLD_L;
TXENA <= TXENA_L;
TX2ENA <= TX2ENA_L;
end syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
-- We run off a 50mhz clock, transferring 1 byte every 4 cycles. This gives
-- up to 12.5MB/s transfer rate, to achieve the maximum rate we need to use
-- 'turbo' mode that ignores the FT2232H async strobes.
-- xmit strobes data in [subject to dead time] on clocks that are a multiple
-- of 4.
-- tx_overrun is asserted if xmit does not write a block. It is cleared on the
-- next successful xmit. In turbo mode, we have no idea if the write succeeds.
-- Instead tx_overrun outputs a LFSR which may be used to synchronise streams.
entity usbio is
generic (packet_bytes : integer);
port (usbd_in : in unsigned8;
usbd_out : out unsigned8;
usb_oe_n : out std_logic := '1';
usb_nRXF : in std_logic;
usb_nTXE : in std_logic;
usb_nRD : out std_logic := '1';
usb_nWR : out std_logic := '1';
usb_SIWU : out std_logic := '1';
read_ok : in std_logic := '1';
byte_in : out unsigned8;
byte_in_strobe : out std_logic;
packet : in unsigned(packet_bytes * 8 - 1 downto 0);
xmit : in std_logic; -- toggle to xmit.
last : in std_logic; -- strobe for highest number channel.
xmit_channel : in unsigned2;
xmit_length : in integer range 0 to packet_bytes;
low_latency, turbo : in std_logic;
tx_overrun : out std_logic;
clk : in std_logic);
end usbio;
architecture usbio of usbio is
type state_t is (state_idle, state_write, state_write2, state_read,
state_read2, state_pause);
signal state : state_t := state_idle;
signal xmit_prev : std_logic;
signal xmit_buffer : unsigned(packet_bytes * 8 - 1 downto 0);
signal xmit_buffered : std_logic := '0';
signal xmit_buffer_length : integer range 0 to packet_bytes;
signal xmit_queue : unsigned(packet_bytes * 8 - 1 downto 0);
signal xmit_channel_counter : unsigned2 := "00";
signal to_xmit : integer range 0 to packet_bytes := 0;
-- In turbo mode the overrun flags get replaced by an LFSR generated
-- pattern. Poly is 0x100802041.
signal lfsr : std_logic_vector(31 downto 0) := x"00000001";
begin
usbd_out <= xmit_queue(7 downto 0);
process
variable rx_available : boolean;
variable tx_available : boolean;
begin
wait until rising_edge(clk);
usb_nRD <= '1';
usb_nWR <= '1';
usb_oe_n <= '1';
state <= state_idle;
byte_in_strobe <= '0';
if state /= state_pause then
usb_SIWU <= '1';
end if;
-- If we're in state idle, decide what to do next. Prefer reads over
-- writes. The read handshake ensures that a write will get out
-- anyway.
rx_available := usb_nRXF = '0' and read_ok = '1';
tx_available := (usb_nTXE = '0' or turbo = '1') and to_xmit /= 0;
if state = state_idle then
if rx_available then
state <= state_read;
usb_nRD <= '0';
elsif tx_available then
state <= state_write;
usb_oe_n <= '0';
end if;
end if;
if state = state_write then
usb_oe_n <= '0';
usb_nWR <= '0';
state <= state_write2;
to_xmit <= to_xmit - 1;
end if;
if state = state_write2 then
usb_nWR <= '0';
state <= state_pause;
xmit_queue(packet_bytes * 8 - 9 downto 0)
<= xmit_queue(packet_bytes * 8 - 1 downto 8);
xmit_queue(packet_bytes * 8 - 1 downto packet_bytes * 8 - 8)
<= "XXXXXXXX";
if to_xmit = 0 and xmit_buffered = '0' and low_latency = '1' then
usb_SIWU <= '0';
end if;
end if;
if state = state_read then
usb_nRD <= '0';
state <= state_read2;
end if;
if state = state_read2 then
byte_in <= usbd_in;
byte_in_strobe <= '1';
state <= state_pause;
end if;
if xmit_buffered = '1' and to_xmit = 0 then
to_xmit <= xmit_buffer_length;
xmit_buffered <= '0';
xmit_queue <= xmit_buffer;
end if;
xmit_prev <= xmit;
if xmit /= xmit_prev and xmit_channel = xmit_channel_counter
then
xmit_buffered <= '1';
xmit_buffer <= packet;
xmit_buffer_length <= xmit_length;
lfsr <= lfsr(30 downto 0) & (
lfsr(31) xor lfsr(22) xor lfsr(12) xor lfsr(5));
if turbo = '1' then
tx_overrun <= lfsr(0);
else
tx_overrun <= xmit_buffered and b2s(to_xmit /= 0);
end if;
end if;
if xmit /= xmit_prev then
if last = '1' then
xmit_channel_counter <= "00";
else
xmit_channel_counter <= xmit_channel_counter + 1;
end if;
end if;
end process;
end usbio;
|
Subsets and Splits