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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Module Name: transceiver_clocking - Behavioral
--
-- Description: Input buffers for the GTX reference clock
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity transceiver_clocking is
Port ( refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtrefclk0 : out STD_LOGIC;
gtrefclk1 : out STD_LOGIC);
end transceiver_clocking;
architecture Behavioral of transceiver_clocking is
signal buffered_clk0 : std_logic;
signal buffered_clk1 : std_logic;
begin
i_buff0: IBUFDS_GTE2 port map (
I => refclk0_p,
IB => refclk0_n,
CEB => '0',
O => gtrefclk0
);
i_buff1: IBUFDS_GTE2 port map (
I => refclk1_p,
IB => refclk1_n,
CEB => '0',
O => gtrefclk1
);
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
--function log2(i : integer) return integer;
function Header_gen(network_size_x, source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
-- gen_bit_reversed_packet needs fixing !!!
--procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
-- finish_time: in time; signal clk: in std_logic;
-- signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
-- signal port_in: out std_logic_vector);
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(network_size_x, source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
variable source_x, source_y, destination_x, destination_y: integer;
begin
-- We only need network_size_x for calculation of X and Y coordinates of a node!
source_x := source mod network_size_x;
source_y := source / network_size_x;
destination_x := destination mod network_size_x;
destination_y := destination / network_size_x;
Header_flit := Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)) &
XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(network_size_x, source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node_x, source_node_y, destination_node_x, destination_node_y, source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
source_node_y := to_integer(unsigned(port_in(28 downto 22)));
source_node_x := to_integer(unsigned(port_in(21 downto 15)));
destination_node_y := to_integer(unsigned(port_in(14 downto 8)));
destination_node_x := to_integer(unsigned(port_in(7 downto 1)));
-- We only needs network_size_x for computing the node ID (convert from (X,Y) coordinate to Node ID)!
source_node := (source_node_y * network_size_x) + source_node_x;
destination_node := (destination_node_y * network_size_x) + destination_node_x;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hash_array_pkg.all;
entity brutus_top is
generic (
M : integer := 2
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component md5_demux
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component md5_mux
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(M-1 downto 0); --
o_mux_sel : out unsigned(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_demux, s_len_demux_md5_0, s_len_demux_md5_1 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_demux, s_string1_demux_md5_0, s_string1_demux_md5_1 : unsigned(31 downto 0);
signal s_string2_pp_demux, s_string2_demux_md5_0, s_string2_demux_md5_1 : unsigned(31 downto 0);
signal hm0_0, hm1_0, hm2_0, hm3_0 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hm0_1, hm1_1, hm2_1, hm3_1 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hc0_0, hc1_0, hc2_0, hc3_0 : unsigned(31 downto 0); -- hashes from mux to comp
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_demux_start, demux_md5_start_0, demux_md5_start_1 : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
--signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
signal s_ctrl_demux_sel, s_ctrl_mux_sel : unsigned(M-1 downto 0);
signal temp_hash_0, temp_hash_1 : unsigned(127 downto 0);
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_demux_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => s_ctrl_demux_sel,
o_mux_sel => s_ctrl_mux_sel
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => hc0_0,
i_hash_1 => hc1_0,
i_hash_2 => hc2_0,
i_hash_3 => hc3_0,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_demux,
o_data_1 => s_string2_pp_demux,
o_length => s_len_pp_demux
);
demux_inst: md5_demux
generic map (
N => M
)
port map (
i_md5_indata.start => ctrl_demux_start,
i_md5_indata.data_0 => s_string1_pp_demux,
i_md5_indata.data_1 => s_string2_pp_demux,
i_md5_indata.len => s_len_pp_demux,
i_select => s_ctrl_demux_sel,
o_md5_indata_0.start => demux_md5_start_0,
o_md5_indata_0.data_0 => s_string1_demux_md5_0,
o_md5_indata_0.data_1 => s_string2_demux_md5_0,
o_md5_indata_0.len => s_len_demux_md5_0,
o_md5_indata_1.start => demux_md5_start_1,
o_md5_indata_1.data_0 => s_string1_demux_md5_1,
o_md5_indata_1.data_1 => s_string2_demux_md5_1,
o_md5_indata_1.len => s_len_demux_md5_1
);
MD5_inst_0: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_0,
i_data_0 => s_string1_demux_md5_0,
i_data_1 => s_string2_demux_md5_0,
i_length => s_len_demux_md5_0,
o_done => md5_ctrl_done, -- only first md5 connected to controller
o_hash_0 => hm0_0, --o_hash(31 downto 0),
o_hash_1 => hm1_0, --o_hash(63 downto 32),
o_hash_2 => hm2_0, --o_hash(95 downto 64),
o_hash_3 => hm3_0 --o_hash(127 downto 96)
);
MD5_inst_1: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_1,
i_data_0 => s_string1_demux_md5_1,
i_data_1 => s_string2_demux_md5_1,
i_length => s_len_demux_md5_1,
o_done => open,
o_hash_0 => hm0_1, --o_hash(31 downto 0),
o_hash_1 => hm1_1, --o_hash(63 downto 32),
o_hash_2 => hm2_1, --o_hash(95 downto 64),
o_hash_3 => hm3_1 --o_hash(127 downto 96)
);
temp_hash_0 <= hm0_0 & hm1_0 & hm2_0 & hm3_0;
temp_hash_1 <= hm0_1 & hm1_1 & hm2_1 & hm3_1;
mux_inst: md5_mux
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_hash_0 => temp_hash_0,
i_hash_1 => temp_hash_1,
i_select => s_ctrl_mux_sel,
o_hash_0 => hc0_0,
o_hash_1 => hc1_0,
o_hash_2 => hc2_0,
o_hash_3 => hc3_0
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 09/22/2014
-- Design Name:
-- Module Name: brutus_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.hash_array_pkg.all;
entity brutus_top is
generic (
M : integer := 2
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
o_pw_found : out std_logic;
o_passwd : out std_logic_vector(47 downto 0)
);
end brutus_top;
architecture Behavioral of brutus_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component md5_demux
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component md5_mux
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
component comp
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end component;
component controller
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out unsigned(M-1 downto 0); --
o_mux_sel : out unsigned(M-1 downto 0) -- select signals to DEMUX/MUX
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_demux, s_len_demux_md5_0, s_len_demux_md5_1 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_demux, s_string1_demux_md5_0, s_string1_demux_md5_1 : unsigned(31 downto 0);
signal s_string2_pp_demux, s_string2_demux_md5_0, s_string2_demux_md5_1 : unsigned(31 downto 0);
signal hm0_0, hm1_0, hm2_0, hm3_0 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hm0_1, hm1_1, hm2_1, hm3_1 : unsigned(31 downto 0); -- hashes from md5 to mux
signal hc0_0, hc1_0, hc2_0, hc3_0 : unsigned(31 downto 0); -- hashes from mux to comp
signal comp_ctrl_eq, sg_ctrl_done, md5_ctrl_done : std_logic;
signal sg_ctrl_string : std_logic_vector(47 downto 0);
signal ctrl_comp_hash : std_logic_vector(127 downto 0);
signal ctrl_sg_comp_start : std_logic; -- start signal to sg and comp
signal ctrl_demux_start, demux_md5_start_0, demux_md5_start_1 : std_logic; -- start signal to MD5 cores
signal ctrl_sg_halt : std_logic; -- halt signal to sg
--signal ctrl_demux_sel, ctrl_mux_sel : std_logic_vector(M-1 downto 0); -- mux/demux selectors
signal s_ctrl_demux_sel, s_ctrl_mux_sel : unsigned(M-1 downto 0);
signal temp_hash_0, temp_hash_1 : unsigned(127 downto 0);
begin
controller_inst: controller
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
i_comp_eq => comp_ctrl_eq,
i_sg_done => sg_ctrl_done,
i_sg_string => sg_ctrl_string,
i_md5_done => md5_ctrl_done,
o_passwd_hash => ctrl_comp_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd,
o_start_sg_comp => ctrl_sg_comp_start,
o_start_md5 => ctrl_demux_start,
o_halt_sg => ctrl_sg_halt,
o_demux_sel => s_ctrl_demux_sel,
o_mux_sel => s_ctrl_mux_sel
);
comp_inst: comp
port map (
clk => clk,
rstn => rstn,
i_cmp_hash => i_fsl_hash,
i_hash_0 => hc0_0,
i_hash_1 => hc1_0,
i_hash_2 => hc2_0,
i_hash_3 => hc3_0,
i_start => ctrl_sg_comp_start,
o_equal => comp_ctrl_eq
);
sg_ctrl_string <= s_string_sg_pp; -- string goes both to pp and controller
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => ctrl_sg_comp_start,
i_halt => ctrl_sg_halt,
o_done => sg_ctrl_done,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_demux,
o_data_1 => s_string2_pp_demux,
o_length => s_len_pp_demux
);
demux_inst: md5_demux
generic map (
N => M
)
port map (
i_md5_indata.start => ctrl_demux_start,
i_md5_indata.data_0 => s_string1_pp_demux,
i_md5_indata.data_1 => s_string2_pp_demux,
i_md5_indata.len => s_len_pp_demux,
i_select => s_ctrl_demux_sel,
o_md5_indata_0.start => demux_md5_start_0,
o_md5_indata_0.data_0 => s_string1_demux_md5_0,
o_md5_indata_0.data_1 => s_string2_demux_md5_0,
o_md5_indata_0.len => s_len_demux_md5_0,
o_md5_indata_1.start => demux_md5_start_1,
o_md5_indata_1.data_0 => s_string1_demux_md5_1,
o_md5_indata_1.data_1 => s_string2_demux_md5_1,
o_md5_indata_1.len => s_len_demux_md5_1
);
MD5_inst_0: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_0,
i_data_0 => s_string1_demux_md5_0,
i_data_1 => s_string2_demux_md5_0,
i_length => s_len_demux_md5_0,
o_done => md5_ctrl_done, -- only first md5 connected to controller
o_hash_0 => hm0_0, --o_hash(31 downto 0),
o_hash_1 => hm1_0, --o_hash(63 downto 32),
o_hash_2 => hm2_0, --o_hash(95 downto 64),
o_hash_3 => hm3_0 --o_hash(127 downto 96)
);
MD5_inst_1: MD5
port map (
clk => clk,
rstn => rstn,
i_start => demux_md5_start_1,
i_data_0 => s_string1_demux_md5_1,
i_data_1 => s_string2_demux_md5_1,
i_length => s_len_demux_md5_1,
o_done => open,
o_hash_0 => hm0_1, --o_hash(31 downto 0),
o_hash_1 => hm1_1, --o_hash(63 downto 32),
o_hash_2 => hm2_1, --o_hash(95 downto 64),
o_hash_3 => hm3_1 --o_hash(127 downto 96)
);
temp_hash_0 <= hm0_0 & hm1_0 & hm2_0 & hm3_0;
temp_hash_1 <= hm0_1 & hm1_1 & hm2_1 & hm3_1;
mux_inst: md5_mux
generic map (
N => M
)
port map (
clk => clk,
rstn => rstn,
i_hash_0 => temp_hash_0,
i_hash_1 => temp_hash_1,
i_select => s_ctrl_mux_sel,
o_hash_0 => hc0_0,
o_hash_1 => hc1_0,
o_hash_2 => hc2_0,
o_hash_3 => hc3_0
);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruction_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruction_Memory_tb_ARCH OF Instruction_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruction_Memory_synth_inst:ENTITY work.Instruction_Memory_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: axi2ahb
-- File: axi2ahb.vhd
-- Author: Martin George
--
-- AXI/AHB bridge allowing Altera HPS to access LEON3 bus.
-- AHB master interface currently only supports OKAY response from slave.
-- AXI slave only supports incrementing bursts of length 1-16 transfers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
Entity axi2ahb is
generic(
hindex : integer := 0;
idsize : integer := 6;
lensize : integer := 4;
fifo_depth : integer := 16
);
port(
ahb_clk : in std_logic;
axi_clk : in std_logic;
resetn : in std_logic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
s_axi_araddr : in std_logic_vector ( 31 downto 0 );
s_axi_arburst : in std_logic_vector ( 1 downto 0 );
s_axi_arcache : in std_logic_vector ( 3 downto 0 );
s_axi_arid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_arlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_arlock : in std_logic_vector (1 downto 0);
s_axi_arprot : in std_logic_vector ( 2 downto 0 );
s_axi_arqos : in std_logic_vector ( 3 downto 0 );
s_axi_arready : out std_logic;
s_axi_arsize : in std_logic_vector ( 2 downto 0 );
s_axi_arvalid : in std_logic;
s_axi_awaddr : in std_logic_vector ( 31 downto 0 );
s_axi_awburst : in std_logic_vector ( 1 downto 0 );
s_axi_awcache : in std_logic_vector ( 3 downto 0 );
s_axi_awid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_awlen : in std_logic_vector ( lensize-1 downto 0 );
s_axi_awlock : in std_logic_vector (1 downto 0);
s_axi_awprot : in std_logic_vector ( 2 downto 0 );
s_axi_awqos : in std_logic_vector ( 3 downto 0 );
s_axi_awready : out std_logic;
s_axi_awsize : in std_logic_vector ( 2 downto 0 );
s_axi_awvalid : in std_logic;
s_axi_bid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector ( 1 downto 0 );
s_axi_bvalid : out std_logic;
s_axi_rdata : out std_logic_vector ( 31 downto 0 );
s_axi_rid : out std_logic_vector ( idsize-1 downto 0 );
s_axi_rlast : out std_logic;
s_axi_rready : in std_logic;
s_axi_rresp : out std_logic_vector ( 1 downto 0 );
s_axi_rvalid : out std_logic;
s_axi_wdata : in std_logic_vector ( 31 downto 0 );
s_axi_wid : in std_logic_vector ( idsize-1 downto 0 );
s_axi_wlast : in std_logic;
s_axi_wready : out std_logic;
s_axi_wstrb : in std_logic_vector ( 3 downto 0 );
s_axi_wvalid : in std_logic
);
end;
architecture rtl of axi2ahb is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AXI2AHB, 0, 0, 0),
others => zero32);
type axi_w_state_type is (w_start, w_wait, w_data_fifo, w_ahb, w_done);
type axi_r_state_type is (r_start, r_wait, r_data_fifo, r_done);
type ahb_rw_state_type is (idle, w_req, w_first_addr, w_data_addr, w_done, r_req,
r_first_addr, r_data_addr, r_done);
type fifo is array (fifo_depth-1 downto 0) of std_logic_vector(31 downto 0);
type ahb_record is record
--States--
ahb_rw_state : ahb_rw_state_type;
--Outputs--
hwrite : std_logic;
hbusreq : std_logic;
hlock : std_logic;
hsize : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hwaddr : std_logic_vector(9 downto 0);
hraddr : std_logic_vector(9 downto 0);
hburst : std_logic_vector(2 downto 0);
inc_sel : std_logic_vector(2 downto 0);
--FIFO signals--
rfifo : fifo;
rfifo_w_ptr : integer range 0 to fifo_depth-1;
wfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
ahb_haddr_stop : std_logic;
ahb_w_en_ack : std_logic;
ahb_r_done : std_logic;
ahb_w_done : std_logic;
addr_incr : integer range 0 to 15;
end record;
type axi_record is record
--States--
axi_w_state : axi_w_state_type;
axi_r_state : axi_r_state_type;
--Outputs--
arready : std_logic;
awready : std_logic;
bvalid : std_logic;
rdata : std_logic_vector ( 31 downto 0 );
rlast : std_logic;
rvalid : std_logic;
wready : std_logic;
--FIFO signals--
wfifo : fifo;
wfifo_w_ptr : integer range 0 to fifo_depth-1;
rfifo_r_ptr : integer range 0 to fifo_depth-1;
--Control signals--
--Write--
awaddr : std_logic_vector(31 downto 0);
awburst : std_logic_vector(1 downto 0);
awlen : std_logic_vector(lensize-1 downto 0);
awsize : std_logic_vector(2 downto 0);
awid : std_logic_vector(idsize-1 downto 0);
--Read--
arid : std_logic_vector(idsize-1 downto 0);
araddr : std_logic_vector(31 downto 0);
arburst : std_logic_vector(1 downto 0);
arlen : std_logic_vector(lensize-1 downto 0);
arsize : std_logic_vector(2 downto 0);
--AHB--
ahb_r_en : std_logic;
ahb_w_en : std_logic;
end record;
signal h, hin : ahb_record;
signal x, xin : axi_record;
begin
comb: process(resetn, ahbi, x, h, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arid, s_axi_arlen, s_axi_arlock,
s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid,
s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awid,
s_axi_awlen, s_axi_awlock, s_axi_awprot, s_axi_awqos,
s_axi_awsize, s_axi_awvalid, s_axi_bready, s_axi_rready,
s_axi_wdata, s_axi_wid, s_axi_wlast, s_axi_wstrb, s_axi_wvalid)
variable vx : axi_record;
variable vh : ahb_record;
begin
vx := x;
vh := h;
-- AXI WRITE STATES
case x.axi_w_state is
when w_start =>
vx.awready := '1';
vx.wready := '0';
vx.ahb_w_en := '0';
vx.bvalid := '0';
if s_axi_awvalid = '1' then
vx.axi_w_state := w_wait;
vx.awready := '0';
vx.awlen := s_axi_awlen;
vx.awburst := s_axi_awburst;
vx.awsize := s_axi_awsize;
vx.awaddr := s_axi_awaddr;
vx.awid := s_axi_awid;
end if;
when w_wait =>
vx.awready := '0';
if h.ahb_w_done = '1' then
vx.wfifo_w_ptr := 0;
vx.axi_w_state := w_data_fifo;
end if;
when w_data_fifo =>
vx.awready := '0';
vx.wfifo_w_ptr := x.wfifo_w_ptr;
vx.wready := '0';
if s_axi_wvalid = '1' then
vx.wready := '1';
if s_axi_wlast = '1' then
vx.axi_w_state := w_ahb;
else
vx.wfifo_w_ptr := x.wfifo_w_ptr + 1;
end if;
end if;
when w_ahb =>
vx.wready := '0';
vx.ahb_w_en := '1';
if h.ahb_w_en_ack = '1' then
vx.ahb_w_en := '0';
vx.bvalid := '1';
vx.axi_w_state := w_done;
end if;
when w_done =>
if s_axi_bready = '1' then
vx.bvalid := '0';
vx.axi_w_state := w_start;
else
end if;
end case;
-- AXI READ STATES
case x.axi_r_state is
when r_start =>
vx.arready := '1';
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
if s_axi_arvalid = '1' then
vx.arready := '0';
vx.ahb_r_en := '1';
vx.arlen := s_axi_arlen;
vx.arburst := s_axi_arburst;
vx.arsize := s_axi_arsize;
vx.araddr := s_axi_araddr;
vx.arid := s_axi_arid;
vx.axi_r_state := r_wait;
end if;
when r_wait =>
vx.arready := '0';
if h.ahb_r_done = '1' then
vx.ahb_r_en := '0';
vx.axi_r_state := r_data_fifo;
end if;
when r_data_fifo =>
vx.rdata := h.rfifo(x.rfifo_r_ptr);
vx.rvalid := '1';
vx.rfifo_r_ptr := x.rfifo_r_ptr;
-- if x.rfifo_r_ptr = conv_integer(x.arlen) then
if x.rfifo_r_ptr = h.rfifo_w_ptr then
vx.rlast := '1';
vx.axi_r_state := r_done;
elsif s_axi_rready = '1' then
vx.rfifo_r_ptr := x.rfifo_r_ptr + 1;
end if;
when r_done =>
vx.rvalid := '1';
if s_axi_rready = '1' then
vx.rvalid := '0';
vx.rfifo_r_ptr := 0;
vx.rlast := '0';
vx.axi_r_state := r_start;
else
end if;
end case;
-- AHB READ/WRITE STATES
case h.ahb_rw_state is
when idle =>
vh.ahb_w_en_ack := '0';
vh.ahb_r_done := '0';
vh.htrans := "00";
if x.ahb_w_en = '1' then
vh.ahb_w_done := '0';
vh.ahb_rw_state := w_req;
vh.hsize := x.awsize;
vh.inc_sel := x.awsize;
elsif x.ahb_r_en = '1' then
vh.ahb_r_done := '0';
vh.ahb_rw_state := r_req;
vh.hsize := "010";
vh.inc_sel := x.arsize;
else
end if;
-- WRITE STATES
when w_req =>
vh.ahb_w_en_ack := '1';
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '1';
if conv_integer(x.awlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := w_first_addr;
else
end if;
when w_first_addr =>
vh.htrans := "10";
vh.hwaddr := x.awaddr(9 downto 0);
vh.haddr := x.awaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not x.awaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not x.awaddr(1);
when others =>
end case;
vh.ahb_rw_state := w_data_addr;
when w_data_addr =>
vh.htrans := "11";
vh.hwdata := x.wfifo(h.wfifo_r_ptr);
if h.wfifo_r_ptr = x.wfifo_w_ptr then
vh.htrans := "00";
vh.ahb_rw_state := w_done;
elsif ahbi.hready = '1' then
vh.hwaddr := h.hwaddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hwaddr;
case h.hsize is
when "000" =>
vh.haddr(1 downto 0) := not vh.hwaddr(1 downto 0);
when "001" =>
vh.haddr(1) := not vh.hwaddr(1);
when others =>
end case;
vh.wfifo_r_ptr := h.wfifo_r_ptr + 1;
end if;
when w_done =>
if ahbi.hready = '1' then
vh.ahb_haddr_stop := '0';
vh.htrans := "00";
vh.wfifo_r_ptr := 0;
vh.ahb_w_en_ack := '0';
vh.ahb_w_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vh.ahb_rw_state := idle;
else
end if;
-- READ STATES
when r_req =>
vh.rfifo_w_ptr := 0;
vh.hbusreq := '1';
vh.hlock := '1';
vh.hwrite := '0';
if conv_integer(x.arlen) /= 0 then
vh.hburst := "001";
else
vh.hburst := "000";
end if;
if (ahbi.hgrant(hindex) and ahbi.hready) = '1' then
vh.ahb_rw_state := r_first_addr;
vh.htrans := "10";
vh.haddr := x.araddr;
vh.hraddr := x.araddr(9 downto 0);
else
end if;
when r_first_addr =>
if ahbi.hready = '1' then
if h.rfifo_w_ptr /= conv_integer(x.arlen) then
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
vh.ahb_rw_state := r_data_addr;
end if;
when r_data_addr =>
if ahbi.hready = '1' then
vh.rfifo(h.rfifo_w_ptr) := ahbi.hrdata;
if h.rfifo_w_ptr = conv_integer(x.arlen) then
vh.htrans := "00";
vh.ahb_rw_state := r_done;
else
vh.htrans := "11";
vh.rfifo_w_ptr := h.rfifo_w_ptr + 1;
vh.hraddr := h.hraddr + h.addr_incr;
vh.haddr(9 downto 0) := vh.hraddr(9 downto 2) & "00";
end if;
else
end if;
when r_done =>
vh.htrans := "00";
vh.ahb_r_done := '1';
vh.hbusreq := '0';
vh.hlock := '0';
vx.ahb_r_en := '0';
vh.ahb_rw_state := idle;
end case;
-- WDATA muxing
if (s_axi_wvalid and h.ahb_w_done) = '1' then
case s_axi_wstrb is
when "0001" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0)
& s_axi_wdata(7 downto 0);
when "0010" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8)
& s_axi_wdata(15 downto 8);
when "0100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16)
& s_axi_wdata(23 downto 16);
when "1000" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24)
& s_axi_wdata(31 downto 24);
when "0011" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(15 downto 0)
& s_axi_wdata(15 downto 0);
when "1100" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata(31 downto 16)
& s_axi_wdata(31 downto 16);
when "1111" =>
vx.wfifo(x.wfifo_w_ptr) := s_axi_wdata;
when others =>
end case;
end if;
-- HADDR increment
case h.inc_sel is
when "000" =>
vh.addr_incr := 1;
when "001" =>
vh.addr_incr := 2;
when others =>
vh.addr_incr := 4;
end case;
if resetn = '0' then
vx.axi_w_state := w_start;
vx.axi_r_state := r_start;
vh.ahb_rw_state := idle;
vh.rfifo := (others => (others => '0'));
vx.wfifo := (others => (others => '0'));
vh.hbusreq := '0';
vh.hlock := '0';
vh.hwdata := (others => '0');
vh.haddr := (others => '0');
vx.awlen := (others => '0');
vx.awburst := (others => '0');
vx.awsize := (others => '0');
vx.awaddr := (others => '0');
vx.awid := (others => '0');
vx.wready := '0';
vx.arready := '0';
vx.awready := '0';
vx.rdata := (others => '0');
vx.araddr := (others => '0');
vx.arburst := (others => '0');
vx.arlen := (others => '0');
vx.arid := (others => '0');
vx.bvalid := '0';
vx.rlast := '0';
vx.rvalid := '0';
vx.wready := '0';
vh.ahb_r_done := '0';
vx.ahb_r_en := '0';
vx.ahb_w_en := '0';
vh.hwrite := '0';
vh.hsize := (others => '0');
vh.ahb_w_done := '1';
vx.arsize := (others => '0');
vh.hburst := (others => '0');
end if;
xin <= vx;
hin <= vh;
end process;
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ahbo.hirq <= (others => '0');
ahbo.haddr <= h.haddr;
ahbo.htrans <= h.htrans;
ahbo.hprot <= "0011";
ahbo.hburst <= h.hburst;
ahbo.hbusreq <= h.hbusreq;
ahbo.hwrite <= h.hwrite;
ahbo.hwdata <= h.hwdata;
ahbo.hlock <= h.hlock;
ahbo.hsize <= h.hsize;
s_axi_bid <= x.awid;
s_axi_rid <= x.arid;
s_axi_arready <= x.arready;
s_axi_awready <= x.awready;
s_axi_bresp <= "00";
s_axi_bvalid <= x.bvalid;
s_axi_rdata <= x.rdata;
s_axi_rlast <= x.rlast;
s_axi_rresp <= "00";
s_axi_rvalid <= x.rvalid;
s_axi_wready <= x.wready;
--AXI synchronous--
axi_sync: process(axi_clk)
begin
if rising_edge(axi_clk) then
x <= xin;
end if;
end process;
--AHB synchronous--
ahb_sync: process(ahb_clk)
begin
if rising_edge(ahb_clk) then
h <= hin;
end if;
end process;
end;
|
-- #############################################################################
-- DE0_Nano_SoC_LT24_top_level.vhd
-- ===============================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_LT24_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_LT24_ADC_BUSY : in std_logic;
GPIO_0_LT24_ADC_CS_N : out std_logic;
GPIO_0_LT24_ADC_DCLK : out std_logic;
GPIO_0_LT24_ADC_DIN : out std_logic;
GPIO_0_LT24_ADC_DOUT : in std_logic;
GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_LT24_top_level;
architecture rtl of DE0_Nano_SoC_LT24_top_level is
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover always (s_write -> not(s_read));
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.graphics_types_pkg.all;
use work.colors_pkg.all;
use work.sprites_pkg.all;
use std.textio.all;
use std.env.all;
entity sprites_engine_tb is
end;
architecture testbench of sprites_engine_tb is
signal clock, reset: std_logic := '0';
signal raster_position: point_type;
signal sprite_pixel: palette_color_type;
signal sprite_pixel_is_valid: boolean;
procedure wait_clock_cycles(cycles_count: integer) is
begin
for i in 1 to cycles_count loop
wait until clock'event and clock = '1';
end loop;
end;
constant TOP_LEFT_SQUARE_BITMAP: paletted_bitmap_type := (
(1, 1, 1, 1, 1, 1, 1, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 2, 2, 2, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 1, 1, 1, 1, 1, 1, 1)
);
constant BOTTOM_RIGHT_TRIANGLE_BITMAP: paletted_bitmap_type := (
(1, 1, 1, 1, 1, 1, 1, 1),
(1, 0, 0, 0, 0, 0, 0, 1),
(1, 0, 0, 0, 0, 0, 2, 1),
(1, 0, 0, 0, 0, 2, 2, 1),
(1, 0, 0, 2, 2, 2, 2, 1),
(1, 0, 2, 2, 2, 2, 2, 1),
(1, 2, 2, 2, 2, 2, 2, 1),
(1, 1, 1, 1, 1, 1, 1, 1)
);
constant SPRITES: sprites_array_type := (
(x => 1, y => 1, bitmap => TOP_LEFT_SQUARE_BITMAP, enabled => true),
(x => 1, y => 1, bitmap => BOTTOM_RIGHT_TRIANGLE_BITMAP, enabled => true)
);
constant SPRITES_COORDINATES: point_array_type(SPRITES'range) := (
(0, 0),
(16, 0)
);
constant SPRITES_COLLISION_QUERY: sprite_collision_query_type := ( (0,1), (0,1) );
signal sprite_collisions_results: bool_vector(SPRITES_COLLISION_QUERY'range);
begin
uut: entity work.sprites_engine
generic map (
SPRITES_INITIAL_VALUES => (
(x => 1, y => 1, bitmap => TOP_LEFT_SQUARE_BITMAP, enabled => true),
(x => 5, y => 5, bitmap => BOTTOM_RIGHT_TRIANGLE_BITMAP, enabled => true)
),
SPRITES_COLLISION_QUERY => ( (0,1), (0,1) )
)
port map(
clock => clock,
reset => reset,
raster_position => raster_position,
sprites_coordinates => SPRITES_COORDINATES,
sprite_pixel => sprite_pixel,
sprite_pixel_is_valid => sprite_pixel_is_valid,
sprite_collisions_results => sprite_collisions_results,
sprites_enabled => (others => true)
);
clock <= not clock after 10 ns;
process
variable row: line;
begin
report "starting...";
reset <= '1';
wait_clock_cycles(2);
reset <= '0';
for y in 0 to 15 loop
for x in 0 to 15 loop
raster_position <= (x, y);
wait_clock_cycles(1);
write(row, sprite_pixel, field => 2);
end loop;
writeline(output, row);
end loop;
finish;
end process;
end; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00983ent IS
END c06s03b00x00p06n01i00983ent;
ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
function foo return integer is
begin
return 120;
end;
function foo return real is
begin
return 12.0;
end;
BEGIN
C := B1.all;
B1.all := B2.all;
assert NOT( C.a=0 and C.b=0 )
report "***PASSED TEST: c06s03b00x00p06n01i00983"
severity NOTE;
assert ( C.a=0 and C.b=0 )
report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00983arch;
|
entity foo is end;
architecture bar of foo is
shared variable INDEX: INTEGER range 0 to 99 := 0;
shared variable COUNT: POSITIVE;
shared variable MEMORY: BIT_MATRIX (0 to 7, 0 to 1023);
begin end;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-- file : BIST_addsub.vhdl
-- version : jeu. nov. 4 00:49:28 CET 2010
-- this file implements a combinatorial unit, injects a fault and compares
-- the result with a reference unit.
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BIST_addsub is
end BIST_addsub;
architecture BIST of BIST_addsub is
signal result, clk, reset : std_ulogic;
signal operandes : std_ulogic_vector(66 downto 1);
signal result_dut, result_ref : std_ulogic_vector(33 downto 1);
begin
-- the test vector generator
lfsr : entity work.lfsr4
generic map(size => 66)
port map (
clk => clk,
reset => reset,
lfsr => operandes);
-- operandes(1) : add/substract
-- operandes(2) : carry in
-- operandes(34 downto 3) : substractend
-- operandes(66 downto 35) : addend
-- reference add/sub unit
reference: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
-- A-B = A+(-B) = A+(not B + 1) :
if (operandes(1) = '1') then
substractend := not substractend;
end if;
-- calcule l'addition avec les retenues
res := unsigned(addend) + unsigned(substractend);
-- écrit la retenue sortante mais pas entrante
result_ref <= std_ulogic_vector(res(34 downto 2));
end process;
-- add/sub with a fault
faulty: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
if (operandes(1) = '1') then
substractend := not substractend;
end if;
res := unsigned(addend) + unsigned(substractend);
-- fault injection :
if (operandes(34 downto 28) = "0110110") then
res(33) := '1';
end if;
result_dut <= std_ulogic_vector(res(34 downto 2));
end process;
process
function sulv2txt(s : std_ulogic_vector) return string is
variable t : string(s'range);
variable u : string(3 downto 1);
begin
for i in s'range loop
u := std_ulogic'image(s(i));
t(i) := u(2);
end loop;
return t;
end sulv2txt;
variable r : std_ulogic_vector(33 downto 1);
begin
clk <= '0';
reset <= '1';
wait for 1 ns;
reset <= '0';
for i in 1 to 100000 loop
clk <= '1'; wait for 1 ns;
clk <= '0'; wait for 1 ns;
r := result_ref xor result_dut;
if (r /= (33 downto 1=>'0')) then
report integer'image(i) & " : " & sulv2txt(operandes) & " - " & sulv2txt(r);
end if;
end loop;
wait;
end process;
end BIST;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:13 10/09/2015
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
-- Definicion del multiplexor
with Sel select
Tiempo <= DecHor when "00",
UniHor when "01",
DecMin when "10",
UniMin when others;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Testbench for the T410 system toplevel.
--
-- $Id: tb_t410-c.vhd,v 1.1 2006-06-11 22:19:32 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_t410_behav_c0 of tb_t410 is
for behav
for t410_b: t410
use configuration work.t410_struct_c0;
end for;
for tb_elems_b: tb_elems
use configuration work.tb_elems_behav_c0;
end for;
end for;
end tb_t410_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY ZynqDesign_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END ZynqDesign_rst_processing_system7_0_100M_0;
ARCHITECTURE ZynqDesign_rst_processing_system7_0_100M_0_arch OF ZynqDesign_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END ZynqDesign_rst_processing_system7_0_100M_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2004/04/06 11:19:53 wig Exp $
-- $Date: 2004/04/06 11:19:53 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 11:19:53 wig
-- Adding result/autoopen
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ab : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb2.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb2 is
end entity Task4_ent_tb2;
architecture Task4_arch_tb2 of Task4_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 14
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb2;
configuration Task4_cfg_tb2 of Task4_ent_tb2 is
for Task4_arch_tb2
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb2;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4_TB\Task4_tb2.vhd
-- Generated : 10/18/14 16:15:19
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task4.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task4_ent_tb2 is
end entity Task4_ent_tb2;
architecture Task4_arch_tb2 of Task4_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task4 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task4;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task4
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
-- Test length 14
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task4_arch_tb2;
configuration Task4_cfg_tb2 of Task4_ent_tb2 is
for Task4_arch_tb2
for UUT : Task4 use entity work.Task4(Beh);
end for;
end for;
end Task4_cfg_tb2;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package inline_02;
package body inline_02 is
-- code from book
constant max_buffer_size : positive := 4096;
-- end code from book
end package body inline_02;
|
library ieee;
use ieee.std_logic_1164.all;
entity ic4021 is
port (d : in std_logic_vector(7 downto 0);
pl : in std_logic;
ds : in std_logic;
cp : in std_logic;
q5 : out std_logic;
q6 : out std_logic;
q7 : out std_logic);
end ic4021;
architecture behavior of ic4021 is
signal shift_reg: std_logic_vector(7 downto 0) := "00000000";
begin
process (d, pl, cp)
begin
if pl = '1' then
shift_reg <= d;
elsif cp'event and cp = '1' then
shift_reg(7 downto 1) <= shift_reg(6 downto 0);
shift_reg(0) <= ds;
end if;
end process;
q5 <= shift_reg(5);
q6 <= shift_reg(6);
q7 <= shift_reg(7);
end behavior;
|
------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
constant C_LINE_LEN_MATRIX : integer := 64;
-- Use the following line for testing purposes.
--constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
|
------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
constant C_LINE_LEN_MATRIX : integer := 64;
-- Use the following line for testing purposes.
--constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
|
--
-- File Name: AlertLog_Demo_Global.vhd
-- Design Unit Name: AlertLog_Demo_Global
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description:
-- Demo showing use of the global counter in AlertLogPkg
--
-- Developed for:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Refining tests
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;
library osvvm ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.AlertLogPkg.all ;
entity AlertLog_Demo_Global is
end AlertLog_Demo_Global ;
architecture hierarchy of AlertLog_Demo_Global is
signal Clk : std_logic := '0';
begin
Clk <= not Clk after 10 ns ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Testbench_1 : block
begin
TbP0 : process
variable ClkNum : integer := 0 ;
begin
wait until Clk = '1' ;
ClkNum := ClkNum + 1 ;
print(LF & "Clock Number " & to_string(ClkNum)) ;
end process TbP0 ;
------------------------------------------------------------
TbP1 : process
begin
-- Uncomment this line to use a log file rather than OUTPUT
-- TranscriptOpen("./Demo_Global.txt") ;
-- Uncomment this line and the simulation will stop after 15 errors
-- SetAlertStopCount(ERROR, 15) ;
SetAlertLogName("AlertLog_Demo_Global") ;
wait for 0 ns ; -- make sure all processes have elaborated
SetLogEnable(DEBUG, TRUE) ; -- Enable DEBUG Messages for all levels of the hierarchy
-- Uncomment this line to justify alert and log reports
-- SetAlertLogJustify ;
for i in 1 to 5 loop
wait until Clk = '1' ;
if i = 4 then SetLogEnable(DEBUG, FALSE) ; end if ; -- DEBUG Mode OFF
wait for 1 ns ;
Alert("Tb.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("Tb.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait until Clk = '1' ;
wait until Clk = '1' ;
wait for 1 ns ;
ReportAlerts ;
print("") ;
-- Report Alerts with expected errors expressed as a negative ExternalErrors value
ReportAlerts(Name => "AlertLog_Demo_Hierarchy with expected errors", ExternalErrors => -(FAILURE => 0, ERROR => 20, WARNING => 15)) ;
TranscriptClose ;
print(LF & "The following is brought to you by std.env.stop:") ;
std.env.stop ;
wait ;
end process TbP1 ;
------------------------------------------------------------
TbP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 2 ns ;
Alert("Tb.P2.E alert " & to_string(i) & " of 5", ERROR) ;
-- example of a log that is not enabled, so it does not print
Log ("Tb.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait until Clk = '1' ;
wait for 2 ns ;
-- Uncomment this line to and the simulation will stop here
-- Alert("Tb.P2.F Message 1 of 1", FAILURE) ;
wait ;
end process TbP2 ;
------------------------------------------------------------
TbP3 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 3 ns ;
Alert("Tb.P3.W alert " & to_string(i) & " of 5", WARNING) ;
end loop ;
wait ;
end process TbP3 ;
end block Testbench_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Cpu_1 : block
begin
------------------------------------------------------------
CpuP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 5 ns ;
Alert("Cpu.P1.E Message " & to_string(i) & " of 5", ERROR) ;
Log ("Cpu.P1.D log " & to_string(i) & " of 5", DEBUG) ;
Log ("Cpu.P1.F log " & to_string(i) & " of 5", FINAL) ; -- enabled by Uart_1
end loop ;
wait ;
end process CpuP1 ;
------------------------------------------------------------
CpuP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 6 ns ;
Alert("Cpu.P2.W Message " & to_string(i) & " of 5", WARNING) ;
Log ("Cpu.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait ;
end process CpuP2 ;
end block Cpu_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Uart_1 : block
begin
-- Enable FINAL logs for every level
-- Note it is expected that most control of alerts will occur only in the testbench block
-- Note that this also turns on FINAL messages for CPU - see hierarchy for better control
SetLogEnable(FINAL, TRUE) ; -- Runs once at initialization time
------------------------------------------------------------
UartP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 10 ns ;
Alert("Uart.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("UART.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait ;
end process UartP1 ;
------------------------------------------------------------
UartP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 11 ns ;
Alert("Uart.P2.W alert " & to_string(i) & " of 5", WARNING) ;
-- Info not enabled
Log ("UART.P2.I log " & to_string(i) & " of 5", INFO) ;
Log ("UART.P2.F log " & to_string(i) & " of 5", FINAL) ;
end loop ;
wait ;
end process UartP2 ;
end block Uart_1 ;
end hierarchy ; |
--
-- File Name: AlertLog_Demo_Global.vhd
-- Design Unit Name: AlertLog_Demo_Global
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description:
-- Demo showing use of the global counter in AlertLogPkg
--
-- Developed for:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Refining tests
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;
library osvvm ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.AlertLogPkg.all ;
entity AlertLog_Demo_Global is
end AlertLog_Demo_Global ;
architecture hierarchy of AlertLog_Demo_Global is
signal Clk : std_logic := '0';
begin
Clk <= not Clk after 10 ns ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Testbench_1 : block
begin
TbP0 : process
variable ClkNum : integer := 0 ;
begin
wait until Clk = '1' ;
ClkNum := ClkNum + 1 ;
print(LF & "Clock Number " & to_string(ClkNum)) ;
end process TbP0 ;
------------------------------------------------------------
TbP1 : process
begin
-- Uncomment this line to use a log file rather than OUTPUT
-- TranscriptOpen("./Demo_Global.txt") ;
-- Uncomment this line and the simulation will stop after 15 errors
-- SetAlertStopCount(ERROR, 15) ;
SetAlertLogName("AlertLog_Demo_Global") ;
wait for 0 ns ; -- make sure all processes have elaborated
SetLogEnable(DEBUG, TRUE) ; -- Enable DEBUG Messages for all levels of the hierarchy
-- Uncomment this line to justify alert and log reports
-- SetAlertLogJustify ;
for i in 1 to 5 loop
wait until Clk = '1' ;
if i = 4 then SetLogEnable(DEBUG, FALSE) ; end if ; -- DEBUG Mode OFF
wait for 1 ns ;
Alert("Tb.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("Tb.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait until Clk = '1' ;
wait until Clk = '1' ;
wait for 1 ns ;
ReportAlerts ;
print("") ;
-- Report Alerts with expected errors expressed as a negative ExternalErrors value
ReportAlerts(Name => "AlertLog_Demo_Hierarchy with expected errors", ExternalErrors => -(FAILURE => 0, ERROR => 20, WARNING => 15)) ;
TranscriptClose ;
print(LF & "The following is brought to you by std.env.stop:") ;
std.env.stop ;
wait ;
end process TbP1 ;
------------------------------------------------------------
TbP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 2 ns ;
Alert("Tb.P2.E alert " & to_string(i) & " of 5", ERROR) ;
-- example of a log that is not enabled, so it does not print
Log ("Tb.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait until Clk = '1' ;
wait for 2 ns ;
-- Uncomment this line to and the simulation will stop here
-- Alert("Tb.P2.F Message 1 of 1", FAILURE) ;
wait ;
end process TbP2 ;
------------------------------------------------------------
TbP3 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 3 ns ;
Alert("Tb.P3.W alert " & to_string(i) & " of 5", WARNING) ;
end loop ;
wait ;
end process TbP3 ;
end block Testbench_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Cpu_1 : block
begin
------------------------------------------------------------
CpuP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 5 ns ;
Alert("Cpu.P1.E Message " & to_string(i) & " of 5", ERROR) ;
Log ("Cpu.P1.D log " & to_string(i) & " of 5", DEBUG) ;
Log ("Cpu.P1.F log " & to_string(i) & " of 5", FINAL) ; -- enabled by Uart_1
end loop ;
wait ;
end process CpuP1 ;
------------------------------------------------------------
CpuP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 6 ns ;
Alert("Cpu.P2.W Message " & to_string(i) & " of 5", WARNING) ;
Log ("Cpu.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait ;
end process CpuP2 ;
end block Cpu_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Uart_1 : block
begin
-- Enable FINAL logs for every level
-- Note it is expected that most control of alerts will occur only in the testbench block
-- Note that this also turns on FINAL messages for CPU - see hierarchy for better control
SetLogEnable(FINAL, TRUE) ; -- Runs once at initialization time
------------------------------------------------------------
UartP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 10 ns ;
Alert("Uart.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("UART.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait ;
end process UartP1 ;
------------------------------------------------------------
UartP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 11 ns ;
Alert("Uart.P2.W alert " & to_string(i) & " of 5", WARNING) ;
-- Info not enabled
Log ("UART.P2.I log " & to_string(i) & " of 5", INFO) ;
Log ("UART.P2.F log " & to_string(i) & " of 5", FINAL) ;
end loop ;
wait ;
end process UartP2 ;
end block Uart_1 ;
end hierarchy ; |
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: aux_interface - Behavioral
--
-- Description: The low-level interface to the DisplayPort AUX channel.
--
-- This encapsulates a small RX and TX FIFO. To use place all the words you want
-- to send into the TX fifo, and then monitor 'busy' and 'timeout'. Any received
-- data will be in the RX FIFO.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity aux_interface is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0);
------------------------------
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic;
------------------------------
tx_wr_en : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_full : out std_logic;
------------------------------
rx_rd_en : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_empty : out std_logic;
------------------------------
busy : out std_logic := '0';
timeout : out std_logic := '0'
);
end aux_interface;
architecture arch of aux_interface is
type a_small_buffer is array (0 to 31) of std_logic_vector(7 downto 0);
------------------------------------------
-- A small fifo to send data from
------------------------------------------
type t_tx_state is (tx_idle, tx_sync, tx_start, tx_send_data, tx_stop, tx_flush, tx_waiting);
signal tx_state : t_tx_state := tx_idle;
signal tx_fifo : a_small_buffer;
signal tx_rd_ptr : unsigned(4 downto 0) := (others => '0');
signal tx_wr_ptr : unsigned(4 downto 0) := (others => '0');
signal tx_wr_ptr_plus_1 : unsigned(4 downto 0) := (others => '0');
signal timeout_count : unsigned(15 downto 0) := (others => '0');
signal tx_empty : std_logic := '0';
signal tx_full_i : std_logic := '0';
signal tx_rd_data : std_logic_vector(7 downto 0) := (others => '0');
signal tx_rd_en : std_logic := '0';
signal snoop : std_logic := '0';
signal serial_data : std_logic := '0';
signal tristate : std_logic := '0';
signal bit_counter : unsigned(7 downto 0) := (others => '0');
constant bit_counter_max : unsigned(7 downto 0) := to_unsigned(49, 8);
signal data_sr : std_logic_vector(15 downto 0);
signal busy_sr : std_logic_vector(15 downto 0);
type t_rx_state is (rx_waiting, rx_receiving_data, rx_done);
signal rx_state : t_rx_state := rx_waiting;
signal rx_fifo : a_small_buffer;
signal rx_wr_ptr : unsigned(4 downto 0) := (others => '0');
signal rx_wr_ptr_plus_1 : unsigned(4 downto 0) := (others => '0');
signal rx_rd_ptr : unsigned(4 downto 0) := (others => '0');
signal rx_reset : std_logic;
signal rx_empty_i : std_logic := '0';
signal rx_full : std_logic := '0';
signal rx_wr_data : std_logic_vector(7 downto 0) := (others => '0');
signal rx_wr_en : std_logic := '0';
signal rx_count : unsigned(5 downto 0) := (others => '0');
signal rx_buffer : std_logic_vector(15 downto 0) := (others => '0');
signal rx_bits : std_logic_vector(15 downto 0) := (others => '0');
signal rx_a_bit : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_synced : std_logic := '0';
signal rx_meta : std_logic := '0';
signal rx_raw : std_logic := '0';
signal rx_finished : std_logic := '0';
signal rx_holdoff : std_logic_vector(9 downto 0) :=(others => '0');
begin
debug_pmod(3 downto 0) <= "000" & snoop;
----------------------------------------------
-- Async logic for the FIFO state and pointers
----------------------------------------------
rx_wr_ptr_plus_1 <= rx_wr_ptr+1;
tx_wr_ptr_plus_1 <= tx_wr_ptr+1;
rx_empty_i <= '1' when rx_wr_ptr = rx_rd_ptr else '0';
rx_full <= '1' when rx_wr_ptr_plus_1 = rx_rd_ptr else '0';
tx_empty <= '1' when tx_wr_ptr = tx_rd_ptr else '0';
tx_full_i <= '1' when tx_wr_ptr_plus_1 = tx_rd_ptr else '0';
rx_empty <= rx_empty_i;
tx_full <= tx_full_i;
busy <= '0' when tx_empty = '1' and tx_state = tx_idle else '1';
clk_proc: process(clk)
begin
if rising_edge(clk) then
----------------------------------
-- Defaults, overwritten as needed
----------------------------------
tx_rd_en <= '0';
rx_reset <= '0';
timeout <= '0';
-----------------------------------
-- Is it time to send the next bit?
-----------------------------------
if bit_counter = bit_counter_max then
bit_counter <= (others => '0');
serial_data <= data_sr(data_sr'high);
tristate <= not busy_sr(busy_sr'high);
data_sr <= data_sr(data_sr'high-1 downto 0) & '0';
busy_sr <= busy_sr(busy_sr'high-1 downto 0) & '0';
---------------------------------------------------
-- Logic to signal the RX module ignore the data we
-- are actually sending for 10 cycles. This is save
-- as the sync pattern is quite long.
-------------------------------------------
if tx_state = tx_waiting then
rx_holdoff <= rx_holdoff(rx_holdoff'high-1 downto 0) & '0';
else
rx_holdoff <= (others => '1');
end if;
--------------------------------------------------
-- Debug signals that are presented to the outside
--------------------------------------------------
case tx_state is
when tx_idle => debug_pmod(7 downto 4) <= x"0";
when tx_sync => debug_pmod(7 downto 4) <= x"1";
when tx_start => debug_pmod(7 downto 4) <= x"2";
when tx_send_data => debug_pmod(7 downto 4) <= x"3";
when tx_stop => debug_pmod(7 downto 4) <= x"4";
when tx_flush => debug_pmod(7 downto 4) <= x"5";
when tx_waiting => debug_pmod(7 downto 4) <= x"6";
when others => debug_pmod(7 downto 4) <= x"A";
end case;
-------------------------------------
-- What to do with with the FSM state
-------------------------------------
if busy_sr(busy_sr'high-1) = '0' then
case tx_state is
when tx_idle =>
if tx_empty = '0' then
data_sr <= "0101010101010101";
busy_sr <= "1111111111111111";
tx_state <= tx_sync;
end if;
when tx_sync =>
data_sr <= "0101010101010101";
busy_sr <= "1111111111111111";
tx_state <= tx_start;
when tx_start =>
-----------------------------------------------------
-- Just send the start pattern.
--
-- The TX fifo must have something in it to get here.
-----------------------------------------------------
data_sr <= "1111000000000000";
busy_sr <= "1111111100000000";
tx_state <= tx_send_data;
rx_reset <= '1';
tx_rd_en <= '1';
when tx_send_data =>
data_sr <= tx_rd_data(7) & not tx_rd_data(7) & tx_rd_data(6) & not tx_rd_data(6)
& tx_rd_data(5) & not tx_rd_data(5) & tx_rd_data(4) & not tx_rd_data(4)
& tx_rd_data(3) & not tx_rd_data(3) & tx_rd_data(2) & not tx_rd_data(2)
& tx_rd_data(1) & not tx_rd_data(1) & tx_rd_data(0) & not tx_rd_data(0);
busy_sr <= "1111111111111111";
if tx_empty = '1' then
-- Send this word, and follow it up with a STOP
tx_state <= tx_stop;
else
-- Send this word, and also read the next one from the FIFO
tx_rd_en <= '1';
end if;
when tx_stop =>
------------------------
-- Send the STOP pattern
------------------------
data_sr <= "1111000000000000";
busy_sr <= "1111111100000000";
tx_state <= tx_flush;
when tx_flush =>
---------------------------------------------
-- Just wait here until we are no longer busy
---------------------------------------------
tx_state <= tx_waiting;
when others => NULL;
end case;
end if;
else
------------------------------------
-- Not time yet to send the next bit
------------------------------------
bit_counter <= bit_counter + 1;
end if;
-----------------------------------------------
-- How the RX process indicates that we are now
-- free to send another transaction
-----------------------------------------------
if tx_state = tx_waiting and rx_finished = '1' then
tx_state <= tx_idle;
end if;
---------------------------------------------
-- Managing the TX FIFO
-- As soon as a word appears in the FIFO it
-- is sent. As it takes 8us to send a byte, the
-- FIFO can be filled quicker than data is sent,
-- ensuring we don't have underrun the TX FIFO
-- and send a short message.
---------------------------------------------
if tx_full_i = '0' and tx_wr_en = '1' then
tx_fifo(to_integer(tx_wr_ptr)) <= tx_data;
tx_wr_ptr <= tx_wr_ptr+1;
end if;
if tx_empty = '0' and tx_rd_en = '1' then
tx_rd_data <= tx_fifo(to_integer(tx_rd_ptr));
tx_rd_ptr <= tx_rd_ptr + 1;
end if;
--------------------------------------------------
-- Managing the RX FIFO
--
-- The contents of the FIFO is reset during the TX
-- of a new transaction. Pointer updates are
-- seperated from the data read / writes to allow
-- the reset to work.
--------------------------------------------------
if rx_full = '0' and rx_wr_en = '1' then
rx_fifo(to_integer(rx_wr_ptr)) <= rx_wr_data;
end if;
if rx_empty_i = '0' and rx_rd_en = '1' then
rx_data <= rx_fifo(to_integer(rx_rd_ptr));
end if;
if rx_reset = '1' then
rx_wr_ptr <= rx_rd_ptr;
else
if rx_full = '0' and rx_wr_en = '1' then
rx_wr_ptr <= rx_wr_ptr+1;
end if;
if rx_empty_i = '0' and rx_rd_en = '1' then
rx_rd_ptr <= rx_rd_ptr + 1;
end if;
end if;
------------------------------------------
-- Manage the timeout. If it is
-- waiting for a reply for over 400us then
-- signal a timeout to the upper FSM.
------------------------------------------
if bit_counter = bit_counter_max then
if tx_state = tx_waiting and tx_state = tx_waiting then
if timeout_count = 39999 then
tx_state <= tx_idle;
timeout <= '1';
else
timeout_count <= timeout_count + 1;
end if;
else
timeout_count <= (others => '0');
end if;
end if;
end if;
end process;
i_IOBUFDS_0 : IOBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => rx_raw,
IO => dp_tx_aux_p,
IOB => dp_tx_aux_n,
I => serial_data,
T => tristate
);
rx_proc: process(clk)
begin
if rising_edge(clk) then
rx_wr_en <= '0';
rx_finished <= '0';
----------------------------------
-- Is it time to sample a new half-bit?
----------------------------------
if rx_count = 49 then
rx_a_bit <= '1';
rx_buffer <= rx_buffer(rx_buffer'high-1 downto 0) & rx_synced;
rx_bits <= rx_bits(rx_bits'high-1 downto 0) & '1';
rx_count <= (others => '0');
else
rx_count <= rx_count+1;
rx_a_bit <= '0';
end if;
----------------------------------------
-- Have we just sampled a new half-bit?
----------------------------------------
if rx_a_bit = '1' then
case rx_state is
when rx_waiting =>
-----------------------------------------------------
-- Are we seeing the end of the SYNC/START sequence?
-----------------------------------------------------
if rx_buffer = "0101010111110000" then
rx_bits <= (others => '0');
if rx_holdoff(rx_holdoff'high) = '0' then
--------------------------------------
-- Yes, switch to receiving bits, but,
-- but only if the TX modules hasn't
-- transmitted for a short while....
--------------------------------------
rx_state <= rx_receiving_data;
end if;
end if;
when rx_receiving_data =>
---------------------------------------------------------
-- Have we just received the 16th half-bit of the a byte?
---------------------------------------------------------
if rx_bits(rx_bits'high) = '1' then
rx_bits <= (others => '0');
------------------------------------------------
-- Are we missing transistions that are required
-- for valid data bytes?
--
-- Or in other words, is this an error or (more
-- usually) the STOP pattern?
-------------------------------------------------
if rx_buffer(15) = rx_buffer(14) or rx_buffer(13) = rx_buffer(12) or
rx_buffer(11) = rx_buffer(10) or rx_buffer( 9) = rx_buffer( 8) or
rx_buffer( 7) = rx_buffer( 6) or rx_buffer( 5) = rx_buffer( 4) or
rx_buffer( 3) = rx_buffer( 2) or rx_buffer( 1) = rx_buffer( 0) then
----------------------------------------------------------
-- Yes, We finished receiving data, or truncate any errors
----------------------------------------------------------
rx_state <= rx_waiting;
if rx_holdoff(rx_holdoff'high) = '0' then
rx_finished <= '1';
end if;
else
---------------------------------------------------
-- Looks like a valid byte, so write it to the FIFO
----------------------------------------------------
rx_wr_data <= rx_buffer(15) & rx_buffer(13) & rx_buffer(11) & rx_buffer(9)
& rx_buffer( 7) & rx_buffer( 5) & rx_buffer( 3) & rx_buffer(1);
rx_wr_en <= '1';
end if;
end if;
when rx_done =>
null; -- waiting to be reset (so I ignore noise!)
when others =>
rx_state <= rx_waiting;
end case;
end if;
-------------------------------------------------
-- Detect the change on the AUX line, and
-- make sure we sample the data mid-way through
-- the half-bit (e.g 0.25us, 0.75us, 1.25 us...)
-- from when the last transition was seen.
------------------------------------------------
if rx_synced /= rx_last then
rx_count <= to_unsigned(25, 6);
end if;
-------------------------------------------------
-- The transmitted resets the RX FSM when it is
-- sending a request. This is a counter measure
-- against line noise when neigher end is driving
-- the link.
-------------------------------------------------
if rx_reset = '1' then
rx_state <= rx_waiting;
end if;
rx_last <= rx_synced;
----------------------------
-- Synchronise the RX signal
----------------------------
rx_synced <= rx_meta;
snoop <= rx_meta;
--------------------------------------------------------
-- This is done to convert Zs or Xs in simulations to 0s
--------------------------------------------------------
if rx_raw = '1' then
rx_meta <= '1';
else
rx_meta <= '0';
end if;
end if;
end process;
-- Stub off the unused inputs
i_IOBUFDS_1 : IOBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => open,
IO => dp_rx_aux_p,
IOB => dp_rx_aux_n,
I => '0',
T => '1'
);
end architecture; |
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
|
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
|
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 800x600
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0110010000"; -- 400
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0100101100"; -- 300
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "1100011111"; -- 799
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "1001010111"; -- 599
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 800x600
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0110010000"; -- 400
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0100101100"; -- 300
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "1100011111"; -- 799
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "1001010111"; -- 599
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: BLOCK_WORD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.centralRouter_package.all;
use work.all;
--! counts block words, inserts block header
entity BLOCK_WORD_COUNTER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0
);
port (
CLK : in std_logic;
RESET : in std_logic;
RESTART : in std_logic;
BW_RDY : in std_logic; -- Block Word Ready Enable
-------------
EOB_MARK : out std_logic; -- End Of Block flag to send the trailer
BLOCK_HEADER_OUT : out std_logic_vector(15 downto 0); --> sending block header
BLOCK_HEADER_OUT_RDY : out std_logic; --> sending block header
-------------
BLOCK_COUNT_RDY : out std_logic
);
end BLOCK_WORD_COUNTER;
architecture Behavioral of BLOCK_WORD_COUNTER is
signal count_sig : std_logic_vector (9 downto 0) := (others => '0');
signal seq_num : std_logic_vector (4 downto 0) := (others => '0');
signal SOB_MARK, SOB_MARK0, seqCNTcase, seqCNTtrig, EOB_MARK_sig : std_logic;
signal SOB_MARK1, blockCountRdy : std_logic := '0';
signal BLOCK_HEADER : std_logic_vector(31 downto 0);
-- two first words are always sent in the beginning of a block transmittion
constant count_offset : std_logic_vector (9 downto 0) := "0000000001";
begin
ce: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' or RESTART = '1' then
blockCountRdy <= '0';
elsif SOB_MARK1 = '1' then
blockCountRdy <= '1';
end if;
end if;
end process;
--
BLOCK_COUNT_RDY <= blockCountRdy;
--------------------------------------------------------------
-- counting block words, data partition
--------------------------------------------------------------
counter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
count_sig <= (others => '0');
else
if EOB_MARK_sig = '1' or RESTART = '1' then
count_sig <= count_offset;
elsif BW_RDY = '1' then
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- End Of Block trigger out for the
-- sub-chunk data manager to insert a trailer
--------------------------------------------------------------
EOB_MARK_sig <= '1' when (count_sig = BLOCK_WORDn) else '0'; -- there is one more space left, for the trailer
EOB_MARK <= EOB_MARK_sig; -- to output
--------------------------------------------------------------
-- Block Sequence counter, 5 bit
--------------------------------------------------------------
seqCNTcase <= EOB_MARK_sig or RESTART;
seqCNTtrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>2,pw=>1) port map(CLK, seqCNTcase, seqCNTtrig);
--
scounter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
seq_num <= (others => '0');
else
if seqCNTtrig = '1' then
seq_num <= seq_num + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- Start Of Block Mark to insert block header
--------------------------------------------------------------
SOB_MARK <= '1' when (count_sig = count_offset) else '0';
--------------------------------------------------------------
-- Start Of Block produces 2 triggers
-- to send 2 words, as header is 32bit
--------------------------------------------------------------
SOB_MARK0_PULSE: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(CLK, SOB_MARK, SOB_MARK0); -- FIFO WE to send word0
SOB_MARK1_PULSE: process(CLK)
begin
if rising_edge(CLK) then
SOB_MARK1 <= SOB_MARK0; -- FIFO WE to send word1
end if;
end process;
--
-- [0xABCD_16] [[block_counter_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & seq_num & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
out_sel: process(CLK)
begin
if rising_edge(CLK) then
if SOB_MARK0 = '1' then
BLOCK_HEADER_OUT <= BLOCK_HEADER(31 downto 16);
else
BLOCK_HEADER_OUT <= BLOCK_HEADER(15 downto 0);
end if;
end if;
end process;
--
BLOCK_HEADER_OUT_RDY <= SOB_MARK0 or SOB_MARK1;
--
end Behavioral; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: BLOCK_WORD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.centralRouter_package.all;
use work.all;
--! counts block words, inserts block header
entity BLOCK_WORD_COUNTER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0
);
port (
CLK : in std_logic;
RESET : in std_logic;
RESTART : in std_logic;
BW_RDY : in std_logic; -- Block Word Ready Enable
-------------
EOB_MARK : out std_logic; -- End Of Block flag to send the trailer
BLOCK_HEADER_OUT : out std_logic_vector(15 downto 0); --> sending block header
BLOCK_HEADER_OUT_RDY : out std_logic; --> sending block header
-------------
BLOCK_COUNT_RDY : out std_logic
);
end BLOCK_WORD_COUNTER;
architecture Behavioral of BLOCK_WORD_COUNTER is
signal count_sig : std_logic_vector (9 downto 0) := (others => '0');
signal seq_num : std_logic_vector (4 downto 0) := (others => '0');
signal SOB_MARK, SOB_MARK0, seqCNTcase, seqCNTtrig, EOB_MARK_sig : std_logic;
signal SOB_MARK1, blockCountRdy : std_logic := '0';
signal BLOCK_HEADER : std_logic_vector(31 downto 0);
-- two first words are always sent in the beginning of a block transmittion
constant count_offset : std_logic_vector (9 downto 0) := "0000000001";
begin
ce: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' or RESTART = '1' then
blockCountRdy <= '0';
elsif SOB_MARK1 = '1' then
blockCountRdy <= '1';
end if;
end if;
end process;
--
BLOCK_COUNT_RDY <= blockCountRdy;
--------------------------------------------------------------
-- counting block words, data partition
--------------------------------------------------------------
counter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
count_sig <= (others => '0');
else
if EOB_MARK_sig = '1' or RESTART = '1' then
count_sig <= count_offset;
elsif BW_RDY = '1' then
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- End Of Block trigger out for the
-- sub-chunk data manager to insert a trailer
--------------------------------------------------------------
EOB_MARK_sig <= '1' when (count_sig = BLOCK_WORDn) else '0'; -- there is one more space left, for the trailer
EOB_MARK <= EOB_MARK_sig; -- to output
--------------------------------------------------------------
-- Block Sequence counter, 5 bit
--------------------------------------------------------------
seqCNTcase <= EOB_MARK_sig or RESTART;
seqCNTtrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>2,pw=>1) port map(CLK, seqCNTcase, seqCNTtrig);
--
scounter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
seq_num <= (others => '0');
else
if seqCNTtrig = '1' then
seq_num <= seq_num + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- Start Of Block Mark to insert block header
--------------------------------------------------------------
SOB_MARK <= '1' when (count_sig = count_offset) else '0';
--------------------------------------------------------------
-- Start Of Block produces 2 triggers
-- to send 2 words, as header is 32bit
--------------------------------------------------------------
SOB_MARK0_PULSE: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(CLK, SOB_MARK, SOB_MARK0); -- FIFO WE to send word0
SOB_MARK1_PULSE: process(CLK)
begin
if rising_edge(CLK) then
SOB_MARK1 <= SOB_MARK0; -- FIFO WE to send word1
end if;
end process;
--
-- [0xABCD_16] [[block_counter_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & seq_num & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
out_sel: process(CLK)
begin
if rising_edge(CLK) then
if SOB_MARK0 = '1' then
BLOCK_HEADER_OUT <= BLOCK_HEADER(31 downto 16);
else
BLOCK_HEADER_OUT <= BLOCK_HEADER(15 downto 0);
end if;
end if;
end process;
--
BLOCK_HEADER_OUT_RDY <= SOB_MARK0 or SOB_MARK1;
--
end Behavioral; |
-- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:35:41 03/04/2015
-- Design Name:
-- Module Name: FETCH_TOPLEVEL - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
use IEEE.NUMERIC_STD.ALL;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity FETCH is
Port ( CLK : in STD_LOGIC;
DATAIN : in STD_LOGIC_VECTOR( 15 downto 0);
INST_ENB : IN STD_LOGIC;
INST_OUT : out STD_LOGIC_VECTOR( 15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR(9 downto 0);
WE : in STD_LOGIC);
end FETCH;
architecture Structural of FETCH is
signal instruction : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal PC : STD_LOGIC_VECTOR (9 downto 0) := (OTHERS => '0');
signal INC : STD_LOGIC_VECTOR (9 downto 0) := (OTHERS => '0');
begin
U1: entity work.INST_REG
port map( CLK => CLK,
INST_ENB => INST_ENB,
INST => instruction,
INST_OUT => INST_OUT);
U2: entity work.INST_MEM
port map( CLKA => CLK,
WEA(0)=> WE,
ADDRA => PC, -- (9 DOWNTO 0)
DINA => DATAIN, -- (15 DOWNTO 0)
CLKB => CLK,
ADDRB => PC, -- (9 DOWNTO 0)
DOUTB => instruction);
INC <= (PC + "0000000001");
U3: entity work.ProgramCounter
port map ( CLK => CLK,
NEW_PC => INC,
PC_OUT => PC);
PC_OUT <= PC;
end Structural;
|
-- VHDL SD card interface
-- by Steven J. Merrifield, June 2008
-- Reads and writes a single block of data, and also writes continuous data
-- Tested on Xilinx Spartan 3 hardware, using Transcend and SanDisk Ultra II cards
-- Read states are derived from the Apple II emulator by Stephen Edwards
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sd_controller is
port (
cs : out std_logic;
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
rd : in std_logic;
wr : in std_logic;
dm_in : in std_logic; -- data mode, 0 = write continuously, 1 = write single block
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
clk : in std_logic -- twice the SPI clk
);
end sd_controller;
architecture rtl of sd_controller is
type states is (
RST,
INIT,
CMD0,
CMD55,
CMD41,
POLL_CMD,
IDLE, -- wait for read or write pulse
READ_BLOCK,
READ_BLOCK_WAIT,
READ_BLOCK_DATA,
READ_BLOCK_CRC,
SEND_CMD,
RECEIVE_BYTE_WAIT,
RECEIVE_BYTE,
WRITE_BLOCK_CMD,
WRITE_BLOCK_INIT, -- initialise write command
WRITE_BLOCK_DATA, -- loop through all data bytes
WRITE_BLOCK_BYTE, -- send one byte
WRITE_BLOCK_WAIT -- wait until not busy
);
-- one start byte, plus 512 bytes of data, plus two FF end bytes (CRC)
constant WRITE_DATA_SIZE : integer := 515;
signal state, return_state : states;
signal sclk_sig : std_logic := '0';
signal cmd_out : std_logic_vector(55 downto 0);
signal recv_data : std_logic_vector(7 downto 0);
signal address : std_logic_vector(31 downto 0);
signal cmd_mode : std_logic := '1';
signal data_mode : std_logic := '1';
signal response_mode : std_logic := '1';
signal data_sig : std_logic_vector(7 downto 0) := x"00";
begin
process(clk,reset)
variable byte_counter : integer range 0 to WRITE_DATA_SIZE;
variable bit_counter : integer range 0 to 160;
begin
data_mode <= dm_in;
if rising_edge(clk) then
if (reset='1') then
state <= RST;
sclk_sig <= '0';
else
case state is
when RST =>
sclk_sig <= '0';
cmd_out <= (others => '1');
address <= x"00000000";
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
bit_counter := 160;
cs <= '1';
state <= INIT;
when INIT => -- CS=1, send 80 clocks, CS=0
if (bit_counter = 0) then
cs <= '0';
state <= CMD0;
else
bit_counter := bit_counter - 1;
sclk_sig <= not sclk_sig;
end if;
when CMD0 =>
cmd_out <= x"FF400000000095";
bit_counter := 55;
return_state <= CMD55;
state <= SEND_CMD;
when CMD55 =>
cmd_out <= x"FF770000000001"; -- 55d OR 40h = 77h
bit_counter := 55;
return_state <= CMD41;
state <= SEND_CMD;
when CMD41 =>
cmd_out <= x"FF690000000001"; -- 41d OR 40h = 69h
bit_counter := 55;
return_state <= POLL_CMD;
state <= SEND_CMD;
when POLL_CMD =>
if (recv_data(0) = '0') then
state <= IDLE;
else
state <= CMD55;
end if;
when IDLE =>
if (rd = '1') then
state <= READ_BLOCK;
elsif (wr='1') then
state <= WRITE_BLOCK_CMD;
else
state <= IDLE;
end if;
when READ_BLOCK =>
cmd_out <= x"FF" & x"51" & address & x"FF";
bit_counter := 55;
return_state <= READ_BLOCK_WAIT;
state <= SEND_CMD;
when READ_BLOCK_WAIT =>
if (sclk_sig='1' and miso='0') then
state <= READ_BLOCK_DATA;
byte_counter := 511;
bit_counter := 7;
return_state <= READ_BLOCK_DATA;
state <= RECEIVE_BYTE;
end if;
sclk_sig <= not sclk_sig;
when READ_BLOCK_DATA =>
if (byte_counter = 0) then
bit_counter := 7;
return_state <= READ_BLOCK_CRC;
state <= RECEIVE_BYTE;
else
byte_counter := byte_counter - 1;
return_state <= READ_BLOCK_DATA;
bit_counter := 7;
state <= RECEIVE_BYTE;
end if;
when READ_BLOCK_CRC =>
bit_counter := 7;
return_state <= IDLE;
address <= std_logic_vector(unsigned(address) + x"200");
state <= RECEIVE_BYTE;
when SEND_CMD =>
if (sclk_sig = '1') then
if (bit_counter = 0) then
state <= RECEIVE_BYTE_WAIT;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when RECEIVE_BYTE_WAIT =>
if (sclk_sig = '1') then
if (miso = '0') then
recv_data <= (others => '0');
if (response_mode='0') then
bit_counter := 3; -- already read bits 7..4
else
bit_counter := 6; -- already read bit 7
end if;
state <= RECEIVE_BYTE;
end if;
end if;
sclk_sig <= not sclk_sig;
when RECEIVE_BYTE =>
if (sclk_sig = '1') then
recv_data <= recv_data(6 downto 0) & miso;
if (bit_counter = 0) then
state <= return_state;
dout <= recv_data(6 downto 0) & miso;
else
bit_counter := bit_counter - 1;
end if;
end if;
sclk_sig <= not sclk_sig;
when WRITE_BLOCK_CMD =>
cmd_mode <= '1';
if (data_mode = '0') then
cmd_out <= x"FF" & x"59" & address & x"FF"; -- continuous
else
cmd_out <= x"FF" & x"58" & address & x"FF"; -- single block
end if;
bit_counter := 55;
return_state <= WRITE_BLOCK_INIT;
state <= SEND_CMD;
when WRITE_BLOCK_INIT =>
cmd_mode <= '0';
byte_counter := WRITE_DATA_SIZE;
state <= WRITE_BLOCK_DATA;
when WRITE_BLOCK_DATA =>
if byte_counter = 0 then
state <= RECEIVE_BYTE_WAIT;
return_state <= WRITE_BLOCK_WAIT;
response_mode <= '0';
else
if ((byte_counter = 2) or (byte_counter = 1)) then
data_sig <= x"FF"; -- two CRC bytes
elsif byte_counter = WRITE_DATA_SIZE then
if (data_mode='0') then
data_sig <= x"FC"; -- start byte, multiple blocks
else
data_sig <= x"FE"; -- start byte, single block
end if;
else
-- just a counter, get real data here
data_sig <= std_logic_vector(to_unsigned(byte_counter,8));
end if;
bit_counter := 7;
state <= WRITE_BLOCK_BYTE;
byte_counter := byte_counter - 1;
end if;
when WRITE_BLOCK_BYTE =>
if (sclk_sig = '1') then
if bit_counter=0 then
state <= WRITE_BLOCK_DATA;
else
data_sig <= data_sig(6 downto 0) & '1';
bit_counter := bit_counter - 1;
end if;
end if;
sclk_sig <= not sclk_sig;
when WRITE_BLOCK_WAIT =>
response_mode <= '1';
if sclk_sig='1' then
if MISO='1' then
if (data_mode='0') then
state <= WRITE_BLOCK_INIT;
else
address <= std_logic_vector(unsigned(address) + x"200");
state <= IDLE;
end if;
end if;
end if;
sclk_sig <= not sclk_sig;
when others => state <= IDLE;
end case;
end if;
end if;
end process;
sclk <= sclk_sig;
mosi <= cmd_out(55) when cmd_mode='1' else data_sig(7);
end rtl;
|
---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmProgRam
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity zcpsmProgRam is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
reset: in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 );
soft_rst : out std_logic;
prog_we : in std_logic;
prog_clk: in std_logic;
prog_addr : in std_logic_vector( AWIDTH-1 downto 0 );
prog_din : in std_logic_vector( 17 downto 0 )
);
end zcpsmProgRam;
architecture syn of zcpsmProgRam is
type RamType is array( 0 to (2**AWIDTH-1) ) of bit_vector( 17 downto 0 );
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile(PROG);
signal soft_rst_i : std_logic;
signal ones : std_logic_vector( 31 downto 0 );
begin
soft_rst <= soft_rst_i;
ones <= ( others=>'0' );
process( clk, reset )
begin
if reset='1' then
dout <= ( others=>'0' );
elsif clk'event and clk = '1' then
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
program : process (prog_clk)
begin
if prog_clk'event and prog_clk = '1' then
if prog_we = '1' then
RAM(conv_integer(prog_addr)) <= to_bitvector(prog_din);
end if;
end if;
end process;
soft_reset : process( prog_clk, reset )
begin
if reset='1' then
soft_rst_i <= '0';
elsif prog_clk'event and prog_clk = '1' then
if prog_we = '1' and prog_addr = ones( AWIDTH-1 downto 0 ) then
soft_rst_i <= prog_din(0);
end if;
end if;
end process;
end syn;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayMux is
Port (entrada: in STD_LOGIC_VECTOR (15 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output_h: out STD_LOGIC_VECTOR (7 downto 0);
current_display: out STD_LOGIC_VECTOR (3 downto 0);
clk_1k: out STD_LOGIC);
end SevenSegmentDisplayMux;
architecture Behavioral of SevenSegmentDisplayMux is
type STD_LOGIC_ARRAY_4 is array (3 downto 0) of STD_LOGIC_VECTOR (7 downto 0);
signal display : STD_LOGIC_ARRAY_4;
signal cont : INTEGER range 0 to 3 := 0;
signal disp_sel : STD_LOGIC_VECTOR (3 downto 0) := "1110";
signal clk_1k_sgn : STD_LOGIC := '0';
signal clock_1k : INTEGER range 0 to 26000 :=0;
begin
clock_div : process (reset, clock)
begin
if reset = '1' then
clock_1k <= 0;
elsif clock'event and clock ='1' then
if(clock_1k > 25000) then
clk_1k_sgn <= not clk_1k_sgn;
clock_1k <= 0;
else
clock_1k <= clock_1k +1;
end if;
else
clock_1k <= clock_1k;
end if;
end process;
process(clk_1k_sgn, reset)
begin
if reset = '1' then
disp_sel <= "1110";
cont <= 0;
elsif clk_1k_sgn'event and clk_1k_sgn = '1' then
disp_sel(3 downto 1) <= disp_sel(2 downto 0);
disp_sel(0) <= disp_sel(3);
cont <= cont +1;
else
disp_sel <= disp_sel;
cont <= cont;
end if;
end process;
current_display <= disp_sel;
laco_for : for i in 0 to 3 generate
display1 : entity work.SevenSegmentDisplayDriver
port map (entrada((i+1)*4 -1 downto i*4),
clock,
reset,
display(i));
output_h <= display(cont REM 4);
end generate;
clk_1k <= clk_1k_sgn;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:28 11/16/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/MIPS32_948282/myMux2X1_tb_948282.vhd
-- Project Name: MIPS32_948282
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: myMux2X1_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY myMux2X1_tb_948282 IS
END myMux2X1_tb_948282;
ARCHITECTURE behavior OF myMux2X1_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT myMux2X1_948282
PORT(
A : IN std_logic_vector(4 downto 0);
B : IN std_logic_vector(4 downto 0);
Op : IN std_logic;
result : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(4 downto 0) := (others => '0');
signal B : std_logic_vector(4 downto 0) := (others => '0');
signal Op : std_logic := '0';
--Outputs
signal result : std_logic_vector(4 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: myMux2X1_948282 PORT MAP (
A => A,
B => B,
Op => Op,
result => result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
A<="10000";
B<="00000";
Op<='1';
wait for 20 ns;
A<="10000";
B<="00000";
Op<='0';
wait for 20 ns;
A<="10110";
B<="00010";
Op<='1';
wait for 20 ns;
A<="10110";
B<="00010";
Op<='1';
wait for 20 ns;
A<="11000";
B<="01100";
Op<='1';
wait;
end process;
END;
|
-------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project : Loa
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
package adc_ad7266_pkg is
-- The Analog Device AD7266 is a 12-Bit ADC with 12 single ended or 6 differential
-- channels
type adc_ad7266_values_type is array (natural range <>) of std_logic_vector(11 downto 0);
type adc_ad7266_spi_out_type is record
cs_n : std_logic;
sck : std_logic;
a : std_logic_vector(2 downto 0);
sgl_diff : std_logic;
end record;
type adc_ad7266_spi_in_type is record
d_a : std_logic;
d_b : std_logic;
end record;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component adc_ad7266_single_ended
generic (
DELAY : natural);
port (
-- signals to and from real hardware
adc_out : out adc_ad7266_spi_out_type;
adc_in : in adc_ad7266_spi_in_type;
-- signals to and from other logic in FPGA
start_p : in std_logic;
adc_mode_p : in std_logic;
channel_p : in std_logic_vector(2 downto 0);
value_a_p : out std_logic_vector(11 downto 0);
value_b_p : out std_logic_vector(11 downto 0);
done_p : out std_logic;
clk : in std_logic);
end component;
component adc_ad7266_single_ended_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive);
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
adc_values_o : out adc_ad7266_values_type(11 downto 0);
clk : in std_logic);
end component;
end adc_ad7266_pkg;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project : Loa
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
package adc_ad7266_pkg is
-- The Analog Device AD7266 is a 12-Bit ADC with 12 single ended or 6 differential
-- channels
type adc_ad7266_values_type is array (natural range <>) of std_logic_vector(11 downto 0);
type adc_ad7266_spi_out_type is record
cs_n : std_logic;
sck : std_logic;
a : std_logic_vector(2 downto 0);
sgl_diff : std_logic;
end record;
type adc_ad7266_spi_in_type is record
d_a : std_logic;
d_b : std_logic;
end record;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component adc_ad7266_single_ended
generic (
DELAY : natural);
port (
-- signals to and from real hardware
adc_out : out adc_ad7266_spi_out_type;
adc_in : in adc_ad7266_spi_in_type;
-- signals to and from other logic in FPGA
start_p : in std_logic;
adc_mode_p : in std_logic;
channel_p : in std_logic_vector(2 downto 0);
value_a_p : out std_logic_vector(11 downto 0);
value_b_p : out std_logic_vector(11 downto 0);
done_p : out std_logic;
clk : in std_logic);
end component;
component adc_ad7266_single_ended_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive);
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
adc_values_o : out adc_ad7266_values_type(11 downto 0);
clk : in std_logic);
end component;
end adc_ad7266_pkg;
-------------------------------------------------------------------------------
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- $Id: mdm_core.vhd,v 1.1.2.2 2010/11/30 08:14:03 stefana Exp $
-------------------------------------------------------------------------------
-- mdm_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_core.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision$
-- Date: $Date$
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity MDM_Core is
generic (
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8
);
port (
-- Global signals
Config_Reset : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
-- External Trace Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG Signals
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM_Core;
library IEEE;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_1;
use mdm_v3_1.all;
architecture IMP of MDM_CORE is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant C_DRCK_FREQ_HZ : integer := 30000000;
constant C_CLOCK_BITS : integer := log2(C_S_AXI_ACLK_FREQ_HZ / C_DRCK_FREQ_HZ);
component JTAG_CONTROL
generic (
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXIS_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3)
);
end component JTAG_CONTROL;
-- Returns the minimum value of the two parameters
function IntMin (a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
signal config_reset_i : std_logic;
signal clear_Ext_BRK : std_logic;
signal enable_interrupts : std_logic;
signal read_RX_FIFO : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal tx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal write_TX_FIFO : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal xfer_Ack : std_logic;
signal mdm_Dbus_i : std_logic_vector(0 to 31); -- Check!
signal mdm_CS : std_logic; -- Valid address in a address phase
signal mdm_CS_1 : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_2 : std_logic;
signal mdm_CS_3 : std_logic;
signal valid_access : std_logic; -- Active during the address phase (2 clock cycles)
signal valid_access_1 : std_logic; -- Will be a 1 clock delayed valid_access signal
signal valid_access_2 : std_logic; -- Active only 1 clock cycle
signal reading : std_logic; -- Valid reading access
signal valid_access_2_reading : std_logic; -- signal to drive out data bus on a read access
signal sl_rdDAck_i : std_logic;
signal sl_wrDAck_i : std_logic;
signal TDI : std_logic;
signal RESET : std_logic;
signal SHIFT : std_logic;
signal CAPTURE : std_logic;
signal TDO : std_logic;
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal Dbg_Clk : std_logic;
signal Dbg_TDI : std_logic;
signal Dbg_TDO : std_logic;
signal Dbg_Reg_En : std_logic_vector(0 to 7);
signal Dbg_Capture : std_logic;
signal Dbg_Shift : std_logic;
signal Dbg_Update : std_logic;
signal Debug_Rst_i : std_logic;
subtype Reg_En_TYPE is std_logic_vector(0 to 7);
type Reg_EN_ARRAY is array(0 to 31) of Reg_En_TYPE;
signal Dbg_TDO_I : std_logic_vector(0 to 31);
signal Dbg_Reg_En_I : Reg_EN_ARRAY;
signal Dbg_Rst_I : std_logic_vector(0 to 31);
signal PORT_Selector : std_logic_vector(3 downto 0) := (others => '0');
signal PORT_Selector_1 : std_logic_vector(3 downto 0) := (others => '0');
signal TDI_Shifter : std_logic_vector(3 downto 0) := (others => '0');
signal Sl_rdDBus_int : std_logic_vector(0 to 31);
signal bus_clk : std_logic;
signal bus_rst : std_logic;
signal uart_ip2bus_rdack : std_logic;
signal uart_ip2bus_wrack : std_logic;
signal uart_ip2bus_error : std_logic;
signal uart_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_ip2bus_rdack : std_logic;
signal dbgreg_ip2bus_wrack : std_logic;
signal dbgreg_ip2bus_error : std_logic;
signal dbgreg_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_access_lock : std_logic;
signal dbgreg_force_lock : std_logic;
signal dbgreg_unlocked : std_logic;
signal jtag_access_lock : std_logic;
signal jtag_force_lock : std_logic;
signal jtag_axis_overrun : std_logic;
signal jtag_clear_overrun : std_logic;
-----------------------------------------------------------------------------
-- Register mapping
-----------------------------------------------------------------------------
-- Magic string "01000010" + "00000000" + No of Jtag peripheral units "0010"
-- + MDM Version no "00000110"
--
-- MDM Versions table:
-- 0,1,2,3: Not used
-- 4: opb_mdm v3
-- 5: mdm v1
-- 6: mdm v2
constant New_MDM_Config_Word : std_logic_vector(31 downto 0) :=
"01000010000000000000001000000110";
signal Config_Reg : std_logic_vector(31 downto 0) := New_MDM_Config_Word;
signal MDM_SEL : std_logic;
signal Old_MDM_DRCK : std_logic;
signal Old_MDM_TDI : std_logic;
signal Old_MDM_TDO : std_logic;
signal Old_MDM_SEL : std_logic;
signal Old_MDM_SEL_Mux : std_logic;
signal Old_MDM_SHIFT : std_logic;
signal Old_MDM_UPDATE : std_logic;
signal Old_MDM_RESET : std_logic;
signal Old_MDM_CAPTURE : std_logic;
signal JTAG_Dec_Sel : std_logic_vector(15 downto 0);
begin -- architecture IMP
config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
-----------------------------------------------------------------------------
-- TDI Shift Register
-----------------------------------------------------------------------------
-- Shifts data in when PORT 0 is selected. PORT 0 does not actually
-- exist externaly, but gets selected after asserting the SELECT signal.
-- The first value shifted in after SELECT goes high will select the new
-- PORT.
JTAG_Mux_Shifting : process (DRCK, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
TDI_Shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if MDM_SEL = '1' and SHIFT = '1' then
TDI_Shifter <= TDI & TDI_Shifter(3 downto 1);
end if;
end if;
end process JTAG_Mux_Shifting;
-----------------------------------------------------------------------------
-- PORT Selector Register
-----------------------------------------------------------------------------
-- Captures the shifted data when PORT 0 is selected. The data is captured at
-- the end of the BSCAN transaction (i.e. when the update signal goes low) to
-- prevent any other BSCAN signals to assert incorrectly.
-- Reference : XAPP 139
PORT_Selector_Updating : process (UPDATE, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
PORT_Selector <= (others => '0');
elsif Update'event and Update = '0' then
PORT_Selector <= Port_Selector_1;
end if;
end process PORT_Selector_Updating;
PORT_Selector_Updating_1 : process (UPDATE, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
PORT_Selector_1 <= (others => '0');
elsif Update'event and Update = '1' then
if MDM_SEL = '1' then
PORT_Selector_1 <= TDI_Shifter;
end if;
end if;
end process PORT_Selector_Updating_1;
-----------------------------------------------------------------------------
-- Configuration register
-----------------------------------------------------------------------------
-- TODO Can be replaced by SRLs
Config_Shifting : process (DRCK, SHIFT, config_reset_i)
begin
if SHIFT = '0' or config_reset_i = '1' then
Config_Reg <= New_MDM_Config_Word;
elsif DRCK'event and DRCK = '1' then -- rising clock edge
Config_Reg <= '0' & Config_Reg(31 downto 1);
end if;
end process Config_Shifting;
-----------------------------------------------------------------------------
-- Muxing and demuxing of JTAG Bscan User 1/2/3/4 signals
--
-- This block enables the older MDM/JTAG to co-exist with the newer
-- JTAG multiplexer block
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with PORT_Selector select
TDO <=
Config_Reg(0) when "0000",
Old_MDM_TDO when "0001",
Ext_JTAG_TDO when "0010",
'1' when others;
-----------------------------------------------------------------------------
-- SELECT Decoder
-----------------------------------------------------------------------------
MDM_SEL <= SEL when PORT_Selector = "0000" else '0';
Old_MDM_SEL_Mux <= SEL when PORT_Selector = "0001" else '0';
Ext_JTAG_SEL <= SEL when PORT_Selector = "0010" else '0';
-----------------------------------------------------------------------------
-- Old MDM signals
-----------------------------------------------------------------------------
Old_MDM_DRCK <= DRCK;
Old_MDM_TDI <= TDI;
Old_MDM_CAPTURE <= CAPTURE;
Old_MDM_SHIFT <= SHIFT;
Old_MDM_UPDATE <= UPDATE;
Old_MDM_RESET <= RESET;
-----------------------------------------------------------------------------
-- External JTAG signals
-----------------------------------------------------------------------------
Ext_JTAG_DRCK <= DRCK;
Ext_JTAG_TDI <= TDI;
Ext_JTAG_CAPTURE <= CAPTURE;
Ext_JTAG_SHIFT <= SHIFT;
Ext_JTAG_UPDATE <= UPDATE;
Ext_JTAG_RESET <= RESET;
-----------------------------------------------------------------------------
-- AXI bus interface
-----------------------------------------------------------------------------
ip2bus_rdack <= uart_ip2bus_rdack or dbgreg_ip2bus_rdack;
ip2bus_wrack <= uart_ip2bus_wrack or dbgreg_ip2bus_wrack;
ip2bus_error <= uart_ip2bus_error or dbgreg_ip2bus_error;
ip2bus_data <= uart_ip2bus_data or dbgreg_ip2bus_data;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
bus_clk <= bus2ip_clk;
bus_rst <= not bus2ip_resetn;
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
bus_clk <= '0';
bus_rst <= '0';
end generate No_AXI_IPIF;
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
Use_Uart : if (C_USE_UART = 1) generate
-- Read Only
signal status_Reg : std_logic_vector(7 downto 0);
-- bit 4 enable_interrupts
-- bit 3 tx_Buffer_Full
-- bit 2 tx_Buffer_Empty
-- bit 1 rx_Buffer_Full
-- bit 0 rx_Data_Present
-- Write Only
-- Control Register
-- bit 7-5 Dont'Care
-- bit 4 enable_interrupts
-- bit 3 Dont'Care
-- bit 2 Clear Ext BRK signal
-- bit 1 Reset_RX_FIFO
-- bit 0 Reset_TX_FIFO
signal tx_Buffer_Empty_Pre : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
uart_ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
uart_ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
uart_ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
---------------------------------------------------------------------------
-- Status register
---------------------------------------------------------------------------
status_Reg(0) <= rx_Data_Present;
status_Reg(1) <= rx_Buffer_Full;
status_Reg(2) <= tx_Buffer_Empty;
status_Reg(3) <= tx_Buffer_Full;
status_Reg(4) <= enable_interrupts;
status_Reg(7 downto 5) <= "000";
---------------------------------------------------------------------------
-- Control Register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '1';
reset_TX_FIFO <= '1';
elsif (bus2ip_wrce(3) = '1') then -- Control Register is reg 3
enable_interrupts <= bus2ip_data(4); -- Bit 4 in control reg
clear_Ext_BRK <= bus2ip_data(2); -- Bit 2 in control reg
reset_RX_FIFO <= bus2ip_data(1); -- Bit 1 in control reg
reset_TX_FIFO <= bus2ip_data(0); -- Bit 0 in control reg
else
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '0';
reset_TX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin
uart_ip2bus_data <= (others => '0');
if (bus2ip_rdce(2) = '1') then -- Status register is reg 2
uart_ip2bus_data(status_reg'length-1 downto 0) <= status_reg;
elsif (bus2ip_rdce(0) = '1') then -- RX FIFO is reg 0
uart_ip2bus_data(C_UART_WIDTH-1 downto 0) <= rx_Data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Write bus interface
---------------------------------------------------------------------------
tx_Data <= bus2ip_data(C_UART_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Read and write pulses to the FIFOs
---------------------------------------------------------------------------
write_TX_FIFO <= bus2ip_wrce(1); -- TX FIFO is reg 1
read_RX_FIFO <= bus2ip_rdce(0); -- RX FIFO is reg 0
-- Sample the tx_Buffer_Empty signal in order to detect a rising edge
TX_Buffer_Empty_FDRE : FDRE
port map (
Q => tx_Buffer_Empty_Pre,
C => bus_clk,
CE => '1',
D => tx_Buffer_Empty,
R => write_TX_FIFO);
---------------------------------------------------------------------------
-- Interrupt handling
---------------------------------------------------------------------------
Interrupt <= enable_interrupts and ( rx_Data_Present or
( tx_Buffer_Empty and
not tx_Buffer_Empty_Pre ) );
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
uart_ip2bus_rdack <= '0';
uart_ip2bus_wrack <= '0';
uart_ip2bus_error <= '0';
uart_ip2bus_data <= (others => '0');
Interrupt <= '0';
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
tx_Data <= (others => '0');
write_TX_FIFO <= '0';
read_RX_FIFO <= '0';
end generate No_UART;
-----------------------------------------------------------------------------
-- Debug Register Access
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1) generate
type state_type is
(idle, select_dr, capture_dr, shift_dr, exit1, pause, exit2, update_dr, cmd_done, data_done);
signal bit_size : std_logic_vector(8 downto 0);
signal cmd_val : std_logic_vector(7 downto 0);
signal type_lock : std_logic_vector(1 downto 0);
signal use_mdm : std_logic;
signal reg_data : std_logic_vector(31 downto 0);
signal bit_cnt : std_logic_vector(0 to 8);
signal clk_cnt : std_logic_vector(0 to C_CLOCK_BITS / 2);
signal clk_fall : boolean;
signal clk_rise : boolean;
signal shifting : boolean;
signal data_shift : boolean;
signal direction : std_logic;
signal rd_wr_n : boolean;
signal rdack_data : std_logic;
signal selected : std_logic := '0';
signal shift_index : std_logic_vector(0 to 4);
signal state : state_type;
signal unlocked : boolean;
signal wrack_data : std_logic;
signal dbgreg_TDI : std_logic;
signal dbgreg_RESET : std_logic;
signal dbgreg_SHIFT : std_logic;
signal dbgreg_CAPTURE : std_logic;
signal dbgreg_SEL : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
dbgreg_ip2bus_rdack <= bus2ip_rdce(4) or rdack_data;
dbgreg_ip2bus_wrack <= bus2ip_wrce(4) or bus2ip_wrce(6) or wrack_data;
dbgreg_ip2bus_error <= (bus2ip_rdce(5) or bus2ip_wrce(5)) and not dbgreg_access_lock;
---------------------------------------------------------------------------
-- Control register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
use_mdm <= '0';
type_lock <= (others => '0');
cmd_val <= (others => '0');
bit_size <= (others => '0');
elsif (bus2ip_wrce(4) = '1') and unlocked then -- Control Register is reg 4
type_lock <= bus2ip_data(19 downto 18);
use_mdm <= bus2ip_data(17);
cmd_val <= bus2ip_data(16 downto 9);
bit_size <= bus2ip_data(8 downto 0);
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Data register and TAP state machine
---------------------------------------------------------------------------
DATA_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
reg_data <= (others => '0');
rdack_data <= '0';
wrack_data <= '0';
state <= idle;
shifting <= false;
data_shift <= false;
direction <= '1';
rd_wr_n <= false;
clk_rise <= false;
clk_fall <= false;
clk_cnt <= (others => '0');
bit_cnt <= "000000111";
shift_index <= "00000";
dbgreg_TDI <= '0';
dbgreg_RESET <= '0';
dbgreg_SHIFT <= '0';
dbgreg_CAPTURE <= '0';
dbgreg_SEL <= '0';
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
selected <= '0';
else
rdack_data <= '0';
wrack_data <= '0';
if unlocked and dbgreg_access_lock = '1' and not shifting then
if bus2ip_wrce(5) = '1' then
reg_data <= bus2ip_data;
shifting <= true;
rd_wr_n <= false;
end if;
if bus2ip_rdce(5) = '1' then
shifting <= true;
rd_wr_n <= true;
end if;
end if;
if clk_rise then
case state is
when idle =>
-- Idle - Start when data access occurs
if shifting then
state <= select_dr;
end if;
bit_cnt <= "000000111";
shift_index <= "00000";
selected <= '0';
when select_dr =>
-- TAP state Select DR - Set SEL
state <= capture_dr;
dbgreg_SEL <= '1';
selected <= '1';
when capture_dr =>
-- TAP state Capture DR - Set CAPTURE and pulse DRCK
state <= shift_dr;
dbgreg_CAPTURE <= '1';
DbgReg_DRCK <= '1';
when shift_dr =>
-- TAP state Shift DR - Set SHIFT and pulse DRCK until done or pause
if bit_cnt = (bit_cnt'range => '0') then
state <= exit2; -- Shift done
elsif shift_index = (shift_index'range => direction) then
state <= exit1; -- Acknowledge and pause until next word
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
end if;
if data_shift then
dbgreg_TDI <= reg_data(to_integer(unsigned(shift_index)));
reg_data(to_integer(unsigned(shift_index))) <= Old_MDM_TDO;
else
dbgreg_TDI <= cmd_val(to_integer(unsigned(shift_index)));
end if;
dbgreg_CAPTURE <= '0';
dbgreg_SHIFT <= '1';
DbgReg_DRCK <= '1';
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if direction = '1' then
shift_index <= std_logic_vector(unsigned(shift_index) + 1);
else
shift_index <= std_logic_vector(unsigned(shift_index) - 1);
end if;
when exit1 =>
-- TAP state Exit1 DR - End shift and go to pause
state <= pause;
shifting <= false;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when pause =>
-- TAP state Pause DR - Pause until new data access or abort
if dbgreg_access_lock = '0' then
state <= exit2; -- Abort shift
elsif shifting then
state <= shift_dr; -- Continue with next word
end if;
DbgReg_DRCK <= '0';
when exit2 =>
-- TAP state Exit2 DR - Delay before update
state <= update_dr;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when update_dr =>
-- TAP state Update DR - Pulse UPDATE and acknowledge data access
if data_shift then
state <= data_done;
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
else
state <= cmd_done;
end if;
DbgReg_UPDATE <= '1';
when cmd_done =>
-- Command phase done - Continue with data phase
state <= select_dr;
data_shift <= true;
bit_cnt <= bit_size;
if use_mdm = '1' then
shift_index <= (others => '0');
else
shift_index <= bit_size(shift_index'length - 1 downto 0);
end if;
direction <= use_mdm;
DbgReg_UPDATE <= '0';
when data_done =>
-- Data phase done - End shifting and go back to idle
state <= idle;
data_shift <= false;
shifting <= false;
direction <= '1';
DbgReg_UPDATE <= '0';
end case;
elsif clk_fall then
DbgReg_DRCK <= '0';
end if;
if clk_cnt(clk_cnt'left + 1 to clk_cnt'right) = (clk_cnt'left + 1 to clk_cnt'right => '0') then
clk_rise <= (clk_cnt(clk_cnt'left) = '0');
clk_fall <= (clk_cnt(clk_cnt'left) = '1');
else
clk_rise <= false;
clk_fall <= false;
end if;
clk_cnt <= std_logic_vector(unsigned(clk_cnt) - 1);
end if;
end if;
end process DATA_REG_DFF;
---------------------------------------------------------------------------
-- Lock register
---------------------------------------------------------------------------
LOCK_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
unlocked <= false;
elsif (bus2ip_wrce(6) = '1') then -- Lock Register is reg 6
unlocked <= (bus2ip_data(15 downto 0) = X"EBAB") and (not unlocked);
end if;
end if;
end process LOCK_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (bus2ip_rdce(4), rdack_data, dbgreg_access_lock, reg_data) is
begin
dbgreg_ip2bus_data <= (others => '0');
if (bus2ip_rdce(4) = '1') then -- Status register is reg 4
dbgreg_ip2bus_data(0) <= dbgreg_access_lock;
elsif rdack_data = '1' then -- Data register is reg 5
dbgreg_ip2bus_data <= reg_data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Access lock handling
---------------------------------------------------------------------------
Handle_Access_Lock : process (bus2ip_clk) is
variable jtag_access_lock_1 : std_logic;
variable jtag_force_lock_1 : std_logic;
variable jtag_clear_overrun_1 : std_logic;
variable jtag_busy_1 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of jtag_access_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_force_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_clear_overrun_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_busy_1 : variable is "TRUE";
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
jtag_access_lock_1 := '0';
jtag_force_lock_1 := '0';
jtag_clear_overrun_1 := '0';
jtag_busy_1 := '0';
else
-- Unlock after last access for type "01"
if state = data_done and type_lock = "01" then
dbgreg_access_lock <= '0';
end if;
-- Write to Debug Access Control Register
if bus2ip_wrce(4) = '1' then
case bus2ip_data(19 downto 18) is
when "00" => -- Release lock to abort atomic sequence
dbgreg_access_lock <= '0';
when "01" | "10" => -- Lock before first access
if dbgreg_access_lock = '0' and jtag_busy_1 = '0' and jtag_access_lock_1 = '0' then
dbgreg_access_lock <= '1';
end if;
when "11" => -- Force access lock
dbgreg_access_lock <= '1';
dbgreg_force_lock <= '1';
-- coverage off
when others =>
null;
-- coverage on
end case;
else
dbgreg_force_lock <= '0';
end if;
jtag_access_lock_1 := JTAG_Access_Lock;
-- JTAG force lock
if jtag_force_lock_1 = '1' then
dbgreg_access_lock <= '0';
dbgreg_unlocked <= '1';
else
dbgreg_unlocked <= '0';
end if;
jtag_force_lock_1 := jtag_force_lock;
-- JTAG overrun detection
if selected = '1' and jtag_busy_1 = '1' then
jtag_axis_overrun <= '1';
elsif jtag_clear_overrun_1 = '1' then
jtag_axis_overrun <= '0';
end if;
jtag_clear_overrun_1 := jtag_clear_overrun;
jtag_busy_1 := jtag_busy;
end if;
end if;
end process;
DbgReg_Select <= selected;
Old_MDM_SEL <= dbgreg_SEL when selected = '1' else Old_MDM_SEL_Mux;
TDI <= dbgreg_TDI when selected = '1' else JTAG_TDI;
RESET <= dbgreg_RESET when selected = '1' else JTAG_RESET;
SHIFT <= dbgreg_SHIFT when selected = '1' else JTAG_SHIFT;
CAPTURE <= dbgreg_CAPTURE when selected = '1' else JTAG_CAPTURE;
JTAG_TDO <= '0' when selected = '1' else TDO;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 0) generate
begin
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
DbgReg_Select <= '0';
dbgreg_ip2bus_rdack <= '0';
dbgreg_ip2bus_wrack <= '0';
dbgreg_ip2bus_error <= '0';
dbgreg_ip2bus_data <= (others => '0');
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
Old_MDM_SEL <= Old_MDM_SEL_Mux;
TDI <= JTAG_TDI;
RESET <= JTAG_RESET;
SHIFT <= JTAG_SHIFT;
CAPTURE <= JTAG_CAPTURE;
JTAG_TDO <= TDO;
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- Instantiating the receive and transmit modules
---------------------------------------------------------------------------
JTAG_CONTROL_I : JTAG_CONTROL
generic map (
C_MB_DBG_PORTS => C_MB_DBG_PORTS,
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET,
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS,
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER,
C_USE_UART => C_USE_UART,
C_UART_WIDTH => C_UART_WIDTH,
C_EN_WIDTH => C_EN_WIDTH
)
port map (
Config_Reset => config_reset_i, -- [in std_logic]
Clk => bus_clk, -- [in std_logic]
Rst => bus_rst, -- [in std_logic]
Clear_Ext_BRK => clear_Ext_BRK, -- [in std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
Debug_Rst => Debug_Rst_i, -- [out std_logic]
Read_RX_FIFO => read_RX_FIFO, -- [in std_logic]
Reset_RX_FIFO => reset_RX_FIFO, -- [in std_logic]
RX_Data => rx_Data, -- [out std_logic_vector(0 to 7)]
RX_Data_Present => rx_Data_Present, -- [out std_logic]
RX_Buffer_Full => rx_Buffer_Full, -- [out std_logic]
Write_TX_FIFO => write_TX_FIFO, -- [in std_logic]
Reset_TX_FIFO => reset_TX_FIFO, -- [in std_logic]
TX_Data => tx_Data, -- [in std_logic_vector(0 to 7)]
TX_Buffer_Full => tx_Buffer_Full, -- [out std_logic]
TX_Buffer_Empty => tx_Buffer_Empty, -- [out std_logic]
-- Debug Register Access signals
DbgReg_Access_Lock => dbgreg_access_lock, -- [in std_logic]
DbgReg_Force_Lock => dbgreg_force_lock, -- [in std_logic]
DbgReg_Unlocked => dbgreg_unlocked, -- [in std_logic]
JTAG_Access_Lock => jtag_access_lock, -- [out std_logic]
JTAG_Force_Lock => jtag_force_lock, -- [out std_logic]
JTAG_AXIS_Overrun => jtag_axis_overrun, -- [in std_logic]
JTAG_Clear_Overrun => jtag_clear_overrun, -- [out std_logic]
-- MDM signals
TDI => Old_MDM_TDI, -- [in std_logic]
RESET => Old_MDM_RESET, -- [in std_logic]
UPDATE => Old_MDM_UPDATE, -- [in std_logic]
SHIFT => Old_MDM_SHIFT, -- [in std_logic]
CAPTURE => Old_MDM_CAPTURE, -- [in std_logic]
SEL => Old_MDM_SEL, -- [in std_logic]
DRCK => Old_MDM_DRCK, -- [in std_logic]
TDO => Old_MDM_TDO, -- [out std_logic]
-- AXI Master signals
M_AXI_ACLK => M_AXI_ACLK, -- [in std_logic]
M_AXI_ARESETn => M_AXI_ARESETn, -- [in std_logic]
Master_rd_start => Master_rd_start, -- [out std_logic]
Master_rd_addr => Master_rd_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_rd_len => Master_rd_len, -- [out std_logic_vector(4 downto 0)]
Master_rd_size => Master_rd_size, -- [out std_logic_vector(1 downto 0)]
Master_rd_excl => Master_rd_excl, -- [out std_logic]
Master_rd_idle => Master_rd_idle, -- [out std_logic]
Master_rd_resp => Master_rd_resp, -- [out std_logic_vector(1 downto 0)]
Master_wr_start => Master_wr_start, -- [out std_logic]
Master_wr_addr => Master_wr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_wr_len => Master_wr_len, -- [out std_logic_vector(4 downto 0)]
Master_wr_size => Master_wr_size, -- [out std_logic_vector(1 downto 0)]
Master_wr_excl => Master_wr_excl, -- [out std_logic]
Master_wr_idle => Master_wr_idle, -- [out std_logic]
Master_wr_resp => Master_wr_resp, -- [out std_logic_vector(1 downto 0)]
Master_data_rd => Master_data_rd, -- [out std_logic]
Master_data_out => Master_data_out, -- [in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_exists => Master_data_exists, -- [in std_logic]
Master_data_wr => Master_data_wr, -- [out std_logic]
Master_data_in => Master_data_in, -- [out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_empty => Master_data_empty, -- [in std_logic]
-- MicroBlaze Debug Signals
MB_Debug_Enabled => mb_debug_enabled_i, -- [out std_logic_vector(7 downto 0)]
Dbg_Clk => Dbg_Clk, -- [out std_logic]
Dbg_TDI => Dbg_TDI, -- [in std_logic]
Dbg_TDO => Dbg_TDO, -- [out std_logic]
Dbg_Reg_En => Dbg_Reg_En, -- [out std_logic_vector(0 to 7)]
Dbg_Capture => Dbg_Capture, -- [out std_logic]
Dbg_Shift => Dbg_Shift, -- [out std_logic]
Dbg_Update => Dbg_Update, -- [out std_logic]
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Ext_Trig_In => Ext_Trig_In, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => Ext_Trig_Ack_In, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => Ext_Trig_Out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => Ext_Trig_Ack_Out -- [in std_logic_vector(0 to 3)]
);
-----------------------------------------------------------------------------
-- Enables for each debug port
-----------------------------------------------------------------------------
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i, Dbg_Reg_En,
Dbg_TDO_I, Debug_Rst_I)
variable dbg_tdo_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
dbg_tdo_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_Reg_En_I(I) <= Dbg_Reg_En;
Dbg_Rst_I(I) <= Debug_Rst_i;
else
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end if;
dbg_tdo_or := dbg_tdo_or or Dbg_TDO_I(I);
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end loop; -- I
Dbg_TDO <= dbg_tdo_or;
end process Generate_Dbg_Port_Signals;
MB_Debug_Enabled <= mb_debug_enabled_i;
Dbg_Clk_0 <= Dbg_Clk;
Dbg_TDI_0 <= Dbg_TDI;
Dbg_Reg_En_0 <= Dbg_Reg_En_I(0);
Dbg_Capture_0 <= Dbg_Capture;
Dbg_Shift_0 <= Dbg_Shift;
Dbg_Update_0 <= Dbg_Update;
Dbg_Rst_0 <= Dbg_Rst_I(0);
Dbg_TDO_I(0) <= Dbg_TDO_0;
Dbg_Clk_1 <= Dbg_Clk;
Dbg_TDI_1 <= Dbg_TDI;
Dbg_Reg_En_1 <= Dbg_Reg_En_I(1);
Dbg_Capture_1 <= Dbg_Capture;
Dbg_Shift_1 <= Dbg_Shift;
Dbg_Update_1 <= Dbg_Update;
Dbg_Rst_1 <= Dbg_Rst_I(1);
Dbg_TDO_I(1) <= Dbg_TDO_1;
Dbg_Clk_2 <= Dbg_Clk;
Dbg_TDI_2 <= Dbg_TDI;
Dbg_Reg_En_2 <= Dbg_Reg_En_I(2);
Dbg_Capture_2 <= Dbg_Capture;
Dbg_Shift_2 <= Dbg_Shift;
Dbg_Update_2 <= Dbg_Update;
Dbg_Rst_2 <= Dbg_Rst_I(2);
Dbg_TDO_I(2) <= Dbg_TDO_2;
Dbg_Clk_3 <= Dbg_Clk;
Dbg_TDI_3 <= Dbg_TDI;
Dbg_Reg_En_3 <= Dbg_Reg_En_I(3);
Dbg_Capture_3 <= Dbg_Capture;
Dbg_Shift_3 <= Dbg_Shift;
Dbg_Update_3 <= Dbg_Update;
Dbg_Rst_3 <= Dbg_Rst_I(3);
Dbg_TDO_I(3) <= Dbg_TDO_3;
Dbg_Clk_4 <= Dbg_Clk;
Dbg_TDI_4 <= Dbg_TDI;
Dbg_Reg_En_4 <= Dbg_Reg_En_I(4);
Dbg_Capture_4 <= Dbg_Capture;
Dbg_Shift_4 <= Dbg_Shift;
Dbg_Update_4 <= Dbg_Update;
Dbg_Rst_4 <= Dbg_Rst_I(4);
Dbg_TDO_I(4) <= Dbg_TDO_4;
Dbg_Clk_5 <= Dbg_Clk;
Dbg_TDI_5 <= Dbg_TDI;
Dbg_Reg_En_5 <= Dbg_Reg_En_I(5);
Dbg_Capture_5 <= Dbg_Capture;
Dbg_Shift_5 <= Dbg_Shift;
Dbg_Update_5 <= Dbg_Update;
Dbg_Rst_5 <= Dbg_Rst_I(5);
Dbg_TDO_I(5) <= Dbg_TDO_5;
Dbg_Clk_6 <= Dbg_Clk;
Dbg_TDI_6 <= Dbg_TDI;
Dbg_Reg_En_6 <= Dbg_Reg_En_I(6);
Dbg_Capture_6 <= Dbg_Capture;
Dbg_Shift_6 <= Dbg_Shift;
Dbg_Update_6 <= Dbg_Update;
Dbg_Rst_6 <= Dbg_Rst_I(6);
Dbg_TDO_I(6) <= Dbg_TDO_6;
Dbg_Clk_7 <= Dbg_Clk;
Dbg_TDI_7 <= Dbg_TDI;
Dbg_Reg_En_7 <= Dbg_Reg_En_I(7);
Dbg_Capture_7 <= Dbg_Capture;
Dbg_Shift_7 <= Dbg_Shift;
Dbg_Update_7 <= Dbg_Update;
Dbg_Rst_7 <= Dbg_Rst_I(7);
Dbg_TDO_I(7) <= Dbg_TDO_7;
Dbg_Clk_8 <= Dbg_Clk;
Dbg_TDI_8 <= Dbg_TDI;
Dbg_Reg_En_8 <= Dbg_Reg_En_I(8);
Dbg_Capture_8 <= Dbg_Capture;
Dbg_Shift_8 <= Dbg_Shift;
Dbg_Update_8 <= Dbg_Update;
Dbg_Rst_8 <= Dbg_Rst_I(8);
Dbg_TDO_I(8) <= Dbg_TDO_8;
Dbg_Clk_9 <= Dbg_Clk;
Dbg_TDI_9 <= Dbg_TDI;
Dbg_Reg_En_9 <= Dbg_Reg_En_I(9);
Dbg_Capture_9 <= Dbg_Capture;
Dbg_Shift_9 <= Dbg_Shift;
Dbg_Update_9 <= Dbg_Update;
Dbg_Rst_9 <= Dbg_Rst_I(9);
Dbg_TDO_I(9) <= Dbg_TDO_9;
Dbg_Clk_10 <= Dbg_Clk;
Dbg_TDI_10 <= Dbg_TDI;
Dbg_Reg_En_10 <= Dbg_Reg_En_I(10);
Dbg_Capture_10 <= Dbg_Capture;
Dbg_Shift_10 <= Dbg_Shift;
Dbg_Update_10 <= Dbg_Update;
Dbg_Rst_10 <= Dbg_Rst_I(10);
Dbg_TDO_I(10) <= Dbg_TDO_10;
Dbg_Clk_11 <= Dbg_Clk;
Dbg_TDI_11 <= Dbg_TDI;
Dbg_Reg_En_11 <= Dbg_Reg_En_I(11);
Dbg_Capture_11 <= Dbg_Capture;
Dbg_Shift_11 <= Dbg_Shift;
Dbg_Update_11 <= Dbg_Update;
Dbg_Rst_11 <= Dbg_Rst_I(11);
Dbg_TDO_I(11) <= Dbg_TDO_11;
Dbg_Clk_12 <= Dbg_Clk;
Dbg_TDI_12 <= Dbg_TDI;
Dbg_Reg_En_12 <= Dbg_Reg_En_I(12);
Dbg_Capture_12 <= Dbg_Capture;
Dbg_Shift_12 <= Dbg_Shift;
Dbg_Update_12 <= Dbg_Update;
Dbg_Rst_12 <= Dbg_Rst_I(12);
Dbg_TDO_I(12) <= Dbg_TDO_12;
Dbg_Clk_13 <= Dbg_Clk;
Dbg_TDI_13 <= Dbg_TDI;
Dbg_Reg_En_13 <= Dbg_Reg_En_I(13);
Dbg_Capture_13 <= Dbg_Capture;
Dbg_Shift_13 <= Dbg_Shift;
Dbg_Update_13 <= Dbg_Update;
Dbg_Rst_13 <= Dbg_Rst_I(13);
Dbg_TDO_I(13) <= Dbg_TDO_13;
Dbg_Clk_14 <= Dbg_Clk;
Dbg_TDI_14 <= Dbg_TDI;
Dbg_Reg_En_14 <= Dbg_Reg_En_I(14);
Dbg_Capture_14 <= Dbg_Capture;
Dbg_Shift_14 <= Dbg_Shift;
Dbg_Update_14 <= Dbg_Update;
Dbg_Rst_14 <= Dbg_Rst_I(14);
Dbg_TDO_I(14) <= Dbg_TDO_14;
Dbg_Clk_15 <= Dbg_Clk;
Dbg_TDI_15 <= Dbg_TDI;
Dbg_Reg_En_15 <= Dbg_Reg_En_I(15);
Dbg_Capture_15 <= Dbg_Capture;
Dbg_Shift_15 <= Dbg_Shift;
Dbg_Update_15 <= Dbg_Update;
Dbg_Rst_15 <= Dbg_Rst_I(15);
Dbg_TDO_I(15) <= Dbg_TDO_15;
Dbg_Clk_16 <= Dbg_Clk;
Dbg_TDI_16 <= Dbg_TDI;
Dbg_Reg_En_16 <= Dbg_Reg_En_I(16);
Dbg_Capture_16 <= Dbg_Capture;
Dbg_Shift_16 <= Dbg_Shift;
Dbg_Update_16 <= Dbg_Update;
Dbg_Rst_16 <= Dbg_Rst_I(16);
Dbg_TDO_I(16) <= Dbg_TDO_16;
Dbg_Clk_17 <= Dbg_Clk;
Dbg_TDI_17 <= Dbg_TDI;
Dbg_Reg_En_17 <= Dbg_Reg_En_I(17);
Dbg_Capture_17 <= Dbg_Capture;
Dbg_Shift_17 <= Dbg_Shift;
Dbg_Update_17 <= Dbg_Update;
Dbg_Rst_17 <= Dbg_Rst_I(17);
Dbg_TDO_I(17) <= Dbg_TDO_17;
Dbg_Clk_18 <= Dbg_Clk;
Dbg_TDI_18 <= Dbg_TDI;
Dbg_Reg_En_18 <= Dbg_Reg_En_I(18);
Dbg_Capture_18 <= Dbg_Capture;
Dbg_Shift_18 <= Dbg_Shift;
Dbg_Update_18 <= Dbg_Update;
Dbg_Rst_18 <= Dbg_Rst_I(18);
Dbg_TDO_I(18) <= Dbg_TDO_18;
Dbg_Clk_19 <= Dbg_Clk;
Dbg_TDI_19 <= Dbg_TDI;
Dbg_Reg_En_19 <= Dbg_Reg_En_I(19);
Dbg_Capture_19 <= Dbg_Capture;
Dbg_Shift_19 <= Dbg_Shift;
Dbg_Update_19 <= Dbg_Update;
Dbg_Rst_19 <= Dbg_Rst_I(19);
Dbg_TDO_I(19) <= Dbg_TDO_19;
Dbg_Clk_20 <= Dbg_Clk;
Dbg_TDI_20 <= Dbg_TDI;
Dbg_Reg_En_20 <= Dbg_Reg_En_I(20);
Dbg_Capture_20 <= Dbg_Capture;
Dbg_Shift_20 <= Dbg_Shift;
Dbg_Update_20 <= Dbg_Update;
Dbg_Rst_20 <= Dbg_Rst_I(20);
Dbg_TDO_I(20) <= Dbg_TDO_20;
Dbg_Clk_21 <= Dbg_Clk;
Dbg_TDI_21 <= Dbg_TDI;
Dbg_Reg_En_21 <= Dbg_Reg_En_I(21);
Dbg_Capture_21 <= Dbg_Capture;
Dbg_Shift_21 <= Dbg_Shift;
Dbg_Update_21 <= Dbg_Update;
Dbg_Rst_21 <= Dbg_Rst_I(21);
Dbg_TDO_I(21) <= Dbg_TDO_21;
Dbg_Clk_22 <= Dbg_Clk;
Dbg_TDI_22 <= Dbg_TDI;
Dbg_Reg_En_22 <= Dbg_Reg_En_I(22);
Dbg_Capture_22 <= Dbg_Capture;
Dbg_Shift_22 <= Dbg_Shift;
Dbg_Update_22 <= Dbg_Update;
Dbg_Rst_22 <= Dbg_Rst_I(22);
Dbg_TDO_I(22) <= Dbg_TDO_22;
Dbg_Clk_23 <= Dbg_Clk;
Dbg_TDI_23 <= Dbg_TDI;
Dbg_Reg_En_23 <= Dbg_Reg_En_I(23);
Dbg_Capture_23 <= Dbg_Capture;
Dbg_Shift_23 <= Dbg_Shift;
Dbg_Update_23 <= Dbg_Update;
Dbg_Rst_23 <= Dbg_Rst_I(23);
Dbg_TDO_I(23) <= Dbg_TDO_23;
Dbg_Clk_24 <= Dbg_Clk;
Dbg_TDI_24 <= Dbg_TDI;
Dbg_Reg_En_24 <= Dbg_Reg_En_I(24);
Dbg_Capture_24 <= Dbg_Capture;
Dbg_Shift_24 <= Dbg_Shift;
Dbg_Update_24 <= Dbg_Update;
Dbg_Rst_24 <= Dbg_Rst_I(24);
Dbg_TDO_I(24) <= Dbg_TDO_24;
Dbg_Clk_25 <= Dbg_Clk;
Dbg_TDI_25 <= Dbg_TDI;
Dbg_Reg_En_25 <= Dbg_Reg_En_I(25);
Dbg_Capture_25 <= Dbg_Capture;
Dbg_Shift_25 <= Dbg_Shift;
Dbg_Update_25 <= Dbg_Update;
Dbg_Rst_25 <= Dbg_Rst_I(25);
Dbg_TDO_I(25) <= Dbg_TDO_25;
Dbg_Clk_26 <= Dbg_Clk;
Dbg_TDI_26 <= Dbg_TDI;
Dbg_Reg_En_26 <= Dbg_Reg_En_I(26);
Dbg_Capture_26 <= Dbg_Capture;
Dbg_Shift_26 <= Dbg_Shift;
Dbg_Update_26 <= Dbg_Update;
Dbg_Rst_26 <= Dbg_Rst_I(26);
Dbg_TDO_I(26) <= Dbg_TDO_26;
Dbg_Clk_27 <= Dbg_Clk;
Dbg_TDI_27 <= Dbg_TDI;
Dbg_Reg_En_27 <= Dbg_Reg_En_I(27);
Dbg_Capture_27 <= Dbg_Capture;
Dbg_Shift_27 <= Dbg_Shift;
Dbg_Update_27 <= Dbg_Update;
Dbg_Rst_27 <= Dbg_Rst_I(27);
Dbg_TDO_I(27) <= Dbg_TDO_27;
Dbg_Clk_28 <= Dbg_Clk;
Dbg_TDI_28 <= Dbg_TDI;
Dbg_Reg_En_28 <= Dbg_Reg_En_I(28);
Dbg_Capture_28 <= Dbg_Capture;
Dbg_Shift_28 <= Dbg_Shift;
Dbg_Update_28 <= Dbg_Update;
Dbg_Rst_28 <= Dbg_Rst_I(28);
Dbg_TDO_I(28) <= Dbg_TDO_28;
Dbg_Clk_29 <= Dbg_Clk;
Dbg_TDI_29 <= Dbg_TDI;
Dbg_Reg_En_29 <= Dbg_Reg_En_I(29);
Dbg_Capture_29 <= Dbg_Capture;
Dbg_Shift_29 <= Dbg_Shift;
Dbg_Update_29 <= Dbg_Update;
Dbg_Rst_29 <= Dbg_Rst_I(29);
Dbg_TDO_I(29) <= Dbg_TDO_29;
Dbg_Clk_30 <= Dbg_Clk;
Dbg_TDI_30 <= Dbg_TDI;
Dbg_Reg_En_30 <= Dbg_Reg_En_I(30);
Dbg_Capture_30 <= Dbg_Capture;
Dbg_Shift_30 <= Dbg_Shift;
Dbg_Update_30 <= Dbg_Update;
Dbg_Rst_30 <= Dbg_Rst_I(30);
Dbg_TDO_I(30) <= Dbg_TDO_30;
Dbg_Clk_31 <= Dbg_Clk;
Dbg_TDI_31 <= Dbg_TDI;
Dbg_Reg_En_31 <= Dbg_Reg_En_I(31);
Dbg_Capture_31 <= Dbg_Capture;
Dbg_Shift_31 <= Dbg_Shift;
Dbg_Update_31 <= Dbg_Update;
Dbg_Rst_31 <= Dbg_Rst_I(31);
Dbg_TDO_I(31) <= Dbg_TDO_31;
end architecture IMP;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ASCII_BUFFER is
port(
ASCII_DATA : in STD_LOGIC_VECTOR(7 downto 0);
ASCII_RD: in STD_LOGIC;
ASCII_WE: in STD_LOGIC;
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
ASCII_BUFF: out STD_LOGIC_VECTOR(15 downto 0)
);
end ASCII_BUFFER;
architecture dataflow of ASCII_BUFFER is
type StateType is (init, idle, VALID_KEY, SPECIAL_KEY, BACKSPACE, FLUSH);
signal STATE : StateType := init;
type ram_type is array (0 to 3) of STD_LOGIC_VECTOR(3 downto 0);
signal ram_addr : integer range 0 to 3;
signal ram : ram_type;
signal KEY : STD_LOGIC_VECTOR(3 downto 0);
signal INST: STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
with ASCII_DATA select
KEY <=
x"f" when x"66",
x"e" when x"65",
x"d" when x"64",
x"c" when x"63",
x"b" when x"62",
x"a" when x"61",
x"F" when x"46",
x"E" when x"45",
x"D" when x"44",
x"C" when x"43",
x"B" when x"42",
x"A" when x"41",
x"9" when x"39",
x"8" when x"38",
x"7" when x"37",
x"6" when x"36",
x"5" when x"35",
x"4" when x"34",
x"3" when x"33",
x"2" when x"32",
x"1" when x"31",
x"0" when x"30",
x"0" when OTHERS; -- Null
PROCESS(CLK,RST)
BEGIN
if(RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '1' ) then
case STATE is
when init =>
ASCII_BUFF <= (OTHERS => '0');
ram(0) <= x"0";
ram(1) <= x"0";
ram(2) <= x"0";
ram(3) <= x"0";
ram_addr <= 0;
state <= idle;
when idle =>
ASCII_BUFF <= INST;
if ASCII_RD = '1' and ASCII_WE = '1' then
state <= VALID_KEY;
-- A Valid key was pressed
elsif ASCII_RD = '1' and ASCII_WE = '0' then
state <= SPECIAL_KEY;
--Special key was pressed
else
state <= idle;
end if;
when VALID_KEY =>
ram(ram_addr) <= key;
ram_addr <= ram_addr + 1;
state <= idle;
when SPECIAL_KEY =>
if ASCII_DATA = x"0D" then --0D = enterkey
state <= FLUSH;
elsif ASCII_DATA = x"08" then -- 08 = backspace
state <= BACKSPACE;
else
state <= idle;
end if;
when BACKSPACE =>
if ram_addr > 0 then
ram_addr <= ram_addr - 1;
end if;
ram(ram_addr) <= x"0";
state <= idle;
when FLUSH =>
INST <= ram(0) & ram(1) & ram(2) & ram(3);
state <= init;
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debouncer is
Port (
CLK : in STD_LOGIC;
Din : in STD_LOGIC;
Dout : out STD_LOGIC := '0'
);
end entity;
architecture Behavioral of debouncer is
signal counter: integer range 0 to 10000000 := 0;
signal last_d: STD_LOGIC := '0';
begin
process(CLK)
begin
if (CLK = '1' and CLK'event) then
if (Din /= last_d) then
if (counter = 100) then
counter <= 0;
last_d <= Din;
Dout <= Din;
else
counter <= counter + 1;
end if;
else
counter <= 0;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444_colourbars_ch1 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 colour bars.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_800_600_RGB_444_colourbars_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_800_600_RGB_444_colourbars_ch1;
architecture arch of test_source_800_600_RGB_444_colourbars_ch1 is
type a_test_data_blocks is array (0 to 64*17-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80
constant PIX_0 : std_logic_vector(8 downto 0) := "000000000"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
-- constant HtotH : std_logic_vector(8 downto 0) := "000000100"; -- Total 1056
-- constant HTotL : std_logic_vector(8 downto 0) := "000100000";
-- constant HstH : std_logic_vector(8 downto 0) := "000000000"; -- Start 128 + 88 = 216
-- constant HstL : std_logic_vector(8 downto 0) := "011011000";
-- constant HswH : std_logic_vector(8 downto 0) := "000000000"; -- Sync width 128
-- constant HswL : std_logic_vector(8 downto 0) := "010000000";
-- constant HwidH : std_logic_vector(8 downto 0) := "000000011"; -- Active width 800
-- constant HwidL : std_logic_vector(8 downto 0) := "000100000";
-- constant VtotH : std_logic_vector(8 downto 0) := "000000010"; -- Total Lines 628
-- constant VtotL : std_logic_vector(8 downto 0) := "001110100";
-- constant VstH : std_logic_vector(8 downto 0) := "000000000"; -- Start = 4+23 = 27
-- constant VstL : std_logic_vector(8 downto 0) := "000011011";
-- constant VswH : std_logic_vector(8 downto 0) := "000000000"; -- Vert Sync Width 4
-- constant VswL : std_logic_vector(8 downto 0) := "000000100";
-- constant VheiH : std_logic_vector(8 downto 0) := "000000010"; -- Active lines 600
-- constant VheiL : std_logic_vector(8 downto 0) := "001011000";
-- constant MISC0 : std_logic_vector(8 downto 0) := "000100001"; -- MISC0 - Sync, RGB, Full range, 8bpp
-- constant MISC1 : std_logic_vector(8 downto 0) := "000000000"; -- MISC1
-- constant MvidH : std_logic_vector(8 downto 0) := "000000001"; -- M = 0x012F68
-- constant MvidM : std_logic_vector(8 downto 0) := "000101111";
-- constant MvidL : std_logic_vector(8 downto 0) := "001101000";
-- constant NvidH : std_logic_vector(8 downto 0) := "000001000"; -- N = 0x080000
-- constant NvidM : std_logic_vector(8 downto 0) := "000000000";
-- constant NvidL : std_logic_vector(8 downto 0) := "000000000";
constant test_data_blocks : a_test_data_blocks := (
--- Block 0 - Junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 1 - 8 white pixels and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 2 - 2 white pixels and 6 yellow and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 3 - 8 yellow and padding
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 4 - 4 yellow and 4 cyan padding
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 5 - 8 cyan padding
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 6 - 6 cyan and 2 green + padding
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 7 - 8 green + padding
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 8 - 8 magent + padding
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 9 - 2 magent + 6 red + padding
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 10 - 4 red + padding
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 11 - 4 red + 4 blue + padding
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 12 - 8 Blue + padding
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 13 - 8 x Blue, Blank Start, VB-ID (no vsync), Mvid, MAud and junk
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
BS, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 14 - 8 x Blue, Blank Start, VB-ID (+vsync), Mvid, MAud and junk
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 15 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 16 - just blank end
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE);
signal index : unsigned (10 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks
signal d0: std_logic_vector(8 downto 0) := (others => '0');
signal d1: std_logic_vector(8 downto 0) := (others => '0');
signal line_count : unsigned(9 downto 0) := (others => '0');
signal row_count : unsigned(7 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
begin
M_value <= x"012F68";
N_value <= x"080000";
H_visible <= x"320"; -- 800
V_visible <= x"258"; -- 600
H_total <= x"420"; -- 1056
V_total <= x"274"; -- 628
H_sync_width <= x"080"; -- 128
V_sync_width <= x"004"; -- 4
H_start <= x"0D8"; -- 216
V_start <= x"01b"; -- 37
H_vsync_active_high <= '0';
V_vsync_active_high <= '0';
flag_sync_clock <= '1';
flag_YCCnRGB <= '0';
flag_422n444 <= '0';
flag_range_reduced <= '0';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "001";
ready <= '1';
data(72) <= switch_point;
data(71 downto 18) <= (others => '0');
data(17 downto 0) <= d1 & d0;
process(clk)
begin
if rising_edge(clk) then
d0 <= test_data_blocks(to_integer(index+0));
d1 <= test_data_blocks(to_integer(index+1));
if index(5 downto 0) = 52 then
index(5 downto 0) <= (others => '0');
if row_count = 131 then
row_count <= (others => '0');
if line_count = 627 then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
row_count <= row_count +1;
end if;
--- Block 0 - Junk
--- Block 1 - Mains Stream attribuutes, junk and blank end
--- Block 2 - 8 white pixels and padding
--- Block 3 - 2 white pixels and 6 yellow and padding
--- Block 4 - 8 yellow and padding
--- Block 5 - 4 yellow and 4 cyan padding
--- Block 6 - 8 cyan padding
--- Block 7 - 6 cyan and 2 green + padding
--- Block 8 - 8 green + padding
--- Block 9 - 8 magent + padding
--- Block 10 - 2 magent + 6 red + padding
--- Block 11 - 8 red + padding
--- Block 12 - 4 red + 4 blue + padding
--- Block 13 - 8 Blue + padding
--- Block 14 - 8 x Blue, Blank Start, VB-ID (no vsync), Mvid, MAud and junk
--- Block 15 - 8 x Blue, Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 16 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 17 - just blank end
if line_count = 0 then
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end BE
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01101"; -- Pixels BS and VS-ID block (no VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
elsif line_count < 599 then -- lines of active video (except first and last)
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end BE
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01101"; -- Pixels BS and VS-ID block (no VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
elsif line_count = 599 then -- Last line of active video
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01110"; -- blue Pixels BS and VS-ID block (with VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
else
-----------------------------------------------------------------
-- Allow switching to/from the idle pattern duein the vertical blank
-----------------------------------------------------------------
if row_count < 100 then
switch_point <= '1';
else
switch_point <= '0';
end if;
if row_count = 100 then
index(10 downto 6) <= "01111"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
end if;
else
index <= index + 2;
end if;
end if;
end process;
end architecture; |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 10
-- Project :
-------------------------------------------------------------------------------
-- File : synthesizer.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 14.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Synthesizer structural description
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 14.01.2016 1.0 nikulaj Created
-- 20.01.2016 1.1 nikulaj Implement bonus feature
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synthesizer is -- synthesizer generics and ports
-- generics
generic(
clk_freq_g : integer := 18432000;
sample_rate_g : integer := 48000;
data_width_g : integer := 16;
n_keys_g : integer := 4
);
-- ports
port(
clk : in std_logic;
rst_n : in std_logic;
keys_in : in std_logic_vector(n_keys_g - 1 downto 0);
aud_bclk_out : out std_logic;
aud_data_out : out std_logic;
aud_lrclk_out : out std_logic
);
end synthesizer;
architecture rtl of synthesizer is -- Defining used signals and components
component wave_gen is
generic(
width_g : integer; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end component;
component multi_port_adder is
generic(
operand_width_g : integer := 16; -- Specify default value for both.
num_of_operands_g : integer := 4
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
operands_in : in std_logic_vector((operand_width_g * num_of_operands_g) - 1 downto 0); -- Operand inputs
sum_out : out std_logic_vector(operand_width_g - 1 downto 0) -- Calculation result.
);
end component;
component audio_ctrl is
generic(
ref_clk_freq_g : integer := 18432000; -- Reference clock.
sample_rate_g : integer := 48000; -- Sample clock fs.
data_width_g : integer := 16 -- Data width.
);
port(
clk : in std_logic; -- Main clock.
rst_n : in std_logic; -- Reset, active low.
left_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, left.
right_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, right.
aud_bclk_out : out std_logic; -- Audio bitclock.
aud_data_out : out std_logic; -- Audio data.
aud_lrclk_out : out std_logic -- Audio bitclock L/R select.
);
end component;
type wavegen_output_arr is array (0 to n_keys_g - 1) -- Define an array type to hold
of std_logic_vector(data_width_g - 1 downto 0); -- wavegen output values,
-- so they can be easily modified
-- registers
signal wavegen_output_r : wavegen_output_arr;
signal adder_input_r : std_logic_vector((data_width_g * n_keys_g) - 1 downto 0);
signal adder_output_r : std_logic_vector(data_width_g - 1 downto 0);
signal aud_bclk_r : std_logic;
signal aud_data_r : std_logic;
signal aud_lrclk_r : std_logic;
begin -- rtl
-- registers to outputs
aud_bclk_out <= aud_bclk_r;
aud_data_out <= aud_data_r;
aud_lrclk_out <= aud_lrclk_r;
-- a process that scales wavegen output according to how many wavegenerators
-- are online. If 1 is on, output is divided by 1, 2 = 2, and so on.
-- This prevents overflow that comes from adding two signals together.
waveform_scaling : process(clk, rst_n)
-- process variables
variable temp : integer := 0;
variable divider : integer := 0;
begin
if(rst_n = '0') then
elsif(clk'event and clk = '1') then -- Calculate on rising edge of clock.
divider := 0; -- Only process on clock rising edge, and when NOT in reset mode
for I in 0 to n_keys_g - 1 loop -- calculate how many buttons are pushed
if (keys_in(I) = '0') then
divider := divider + 1;
end if;
end loop;
if (divider = 0) then -- failsafe to prevent div-by-0
divider := 1;
end if;
for I in 0 to n_keys_g - 1 loop -- modify wavegen outputs
temp := to_integer(signed(wavegen_output_r(I)));
temp := temp / divider;
adder_input_r((I+1)*data_width_g - 1 downto I*data_width_g) <= std_logic_vector(to_signed(temp, wavegen_output_r(I)'length));
end loop;
end if;
end process waveform_scaling;
-- instantiate as many wave generators as needed
wave_generators:
for I in 0 to n_keys_g - 1 generate
wavegen_arr : wave_gen
generic map
(
width_g => data_width_g,
step_g => 2**I
)
port map
(
clk => clk,
rst_n => rst_n,
sync_clear_in => keys_in(I),
value_out => wavegen_output_r(I)
);
end generate wave_generators;
i_adder : multi_port_adder
generic map
(
operand_width_g => data_width_g,
num_of_operands_g => n_keys_g
)
port map
(
clk => clk,
rst_n => rst_n,
operands_in => adder_input_r,
sum_out => adder_output_r
);
i_audio_ctrl : audio_ctrl
generic map
(
ref_clk_freq_g => clk_freq_g,
sample_rate_g => sample_rate_g,
data_width_g => data_width_g
)
port map
(
clk => clk,
rst_n => rst_n,
left_data_in => adder_output_r,
right_data_in => adder_output_r,
aud_bclk_out => aud_bclk_r,
aud_data_out => aud_data_r,
aud_lrclk_out => aud_lrclk_r
);
end rtl;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE ANN_ap_fptrunc_0_no_dsp_64_arch OF ANN_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fptrunc_0_no_dsp_64_arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
|
-- maurice daverveldt
-- 1531491
-- ev3a
-- dit bestand bevat de testbench voor de ALU
library ieee;
use ieee.std_logic_1164.all;
use work.opdr5.all;
entity opdr5_tb is
end opdr5_tb;
architecture RTL of opdr5_tb is
component ALU is
port( getal_a, getal_b : in std_logic_vector(7 downto 0);
s : in std_logic_vector(1 downto 0);
resultaat : out std_logic_vector(8 downto 0);
cout : out std_logic);
end component;
signal a,b : std_logic_vector(7 downto 0);
signal s : std_logic_vector(1 downto 0);
signal resultaat : std_logic_vector(8 downto 0);
signal cout: std_logic;
signal OK : std_logic;
begin
DUT: entity work.ALU port map(
getal_a => a,
getal_b => b,
resultaat => resultaat,
s => s,
cout => cout
);
tb : process
begin
-- 01010101 01001010 10010101 00011100 01101011
OK <= '1';
s <= "00";
a <= "01010101"; --zet waarde op portb
b <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010011111" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
a <= "01001010"; --zet waarde op portb
b <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010010100" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
a <= "10010101"; --zet waarde op portb
b <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "011011111" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
a <= "00011100"; --zet waarde op portb
b <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "001100110" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
a <= "01101011"; --zet waarde op portb
b <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010110101" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
s <= "01";
b <= "01010101"; --zet waarde op portb
a <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010011111" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
b <= "01001010"; --zet waarde op portb
a <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010010100" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
b <= "10010101"; --zet waarde op portb
a <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "011011111" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
b <= "00011100"; --zet waarde op portb
a <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "001100110" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
b <= "01101011"; --zet waarde op portb
a <= "01001010"; --zet waarde op porta
wait for 2 ns; --even wachten
if resultaat /= "010110101" then OK <= '0'; --als resultaat niet klopt maak dan ok laag
end if;
wait for 3 ns;
wait;
end process;
end RTL; |
-- NEED RESULT: ARCH00565: Aliasing - dynamic composite types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00565
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (2)
-- 4.3.4 (14)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00565)
-- ENT00565_Test_Bench(ARCH00565_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00565 of E00000 is
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
procedure p1 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
variable correct : boolean := true;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
constant co_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
constant co_st_string_1 : st_string
:= c_st_string_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias ac_st_bit_vector_1 : st_bit_vector
is co_st_bit_vector_1 ;
alias ac_st_string_1 : st_string
is co_st_string_1 ;
alias ac_st_rec1_1 : st_rec1
is co_st_rec1_1 ;
alias ac_st_rec2_1 : st_rec2
is co_st_rec2_1 ;
alias ac_st_rec3_1 : st_rec3
is co_st_rec3_1 ;
alias ac_st_arr1_1 : st_arr1
is co_st_arr1_1 ;
alias av_st_bit_vector_1 : st_bit_vector
is va_st_bit_vector_1 ;
alias av_st_string_1 : st_string
is va_st_string_1 ;
alias av_st_rec1_1 : st_rec1
is va_st_rec1_1 ;
alias av_st_rec2_1 : st_rec2
is va_st_rec2_1 ;
alias av_st_rec3_1 : st_rec3
is va_st_rec3_1 ;
alias av_st_arr1_1 : st_arr1
is va_st_arr1_1 ;
begin
-- test that variables denote same object
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and av_st_string_1 = c_st_string_1 ;
correct := correct and av_st_rec1_1 = c_st_rec1_1 ;
correct := correct and av_st_rec2_1 = c_st_rec2_1 ;
correct := correct and av_st_rec3_1 = c_st_rec3_1 ;
correct := correct and av_st_arr1_1 = c_st_arr1_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and av_st_string_1 = c_st_string_2 ;
correct := correct and av_st_rec1_1 = c_st_rec1_2 ;
correct := correct and av_st_rec2_1 = c_st_rec2_2 ;
correct := correct and av_st_rec3_1 = c_st_rec3_2 ;
correct := correct and av_st_arr1_1 = c_st_arr1_2 ;
av_st_bit_vector_1 := c_st_bit_vector_1 ;
av_st_string_1 := c_st_string_1 ;
av_st_rec1_1 := c_st_rec1_1 ;
av_st_rec2_1 := c_st_rec2_1 ;
av_st_rec3_1 := c_st_rec3_1 ;
av_st_arr1_1 := c_st_arr1_1 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
-- test that constants denote same object
correct := correct and ac_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and ac_st_string_1 = c_st_string_1 ;
correct := correct and ac_st_rec1_1 = c_st_rec1_1 ;
correct := correct and ac_st_rec2_1 = c_st_rec2_1 ;
correct := correct and ac_st_rec3_1 = c_st_rec3_1 ;
correct := correct and ac_st_arr1_1 = c_st_arr1_1 ;
test_report ("ARCH00565",
"Aliasing - dynamic composite types",
correct ) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end ARCH00565 ;
--
entity ENT00565_Test_Bench is
end ENT00565_Test_Bench ;
--
architecture ARCH00565_Test_Bench of ENT00565_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00565 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00565_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_shift is
end tb_shift;
architecture behav of tb_shift is
signal a : t_data := (others => '0');
signal b : t_data := (others => '0');
signal logic : t_data := (others => '0');
signal arith : t_data := (others => '0');
begin
process
variable l : line;
begin
wait for 20 ns;
a <= X"00";
for i in 0 to 10 loop
b <= std_logic_vector(to_unsigned(i, t_data'length));
wait for 20 ns;
end loop;
a <= X"AA";
for i in 0 to 10 loop
b <= std_logic_vector(to_unsigned(i, t_data'length));
wait for 20 ns;
end loop;
a <= X"55";
for i in 0 to 10 loop
b <= std_logic_vector(to_unsigned(i, t_data'length));
wait for 20 ns;
end loop;
a <= X"FF";
for i in 0 to 10 loop
b <= std_logic_vector(to_unsigned(i, t_data'length));
wait for 20 ns;
end loop;
a <= X"7F";
for i in 0 to 10 loop
b <= std_logic_vector(to_unsigned(i, t_data'length));
wait for 20 ns;
end loop;
assert false report "stop" severity failure;
end process;
ashift: entity work.shift_ra
port map(
a => a,
b => b,
c => arith
);
lshift: entity work.shift_rl
port map(
a => a,
b => b,
c => logic
);
end behav;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 07/01/2013
-- Design Name: Adder_GF_2_M
-- Module Name: Adder_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit computes the addition of number_of_elements in GF(2^m).
-- This circuit is pure combinatorial, and only XOR all elements.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of each element.
--
-- number_of_elements :
--
-- The number of elements to be added.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder_gf_2_m is
Generic(
gf_2_m : integer;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end adder_gf_2_m;
architecture RTL of adder_gf_2_m is
signal b : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements - 1) - 1) downto 0);
begin
b((gf_2_m - 1) downto 0) <= a((gf_2_m - 1) downto 0) xor a((2*gf_2_m - 1) downto (gf_2_m));
more_than_two : if number_of_elements > 2 generate
reduction : for Index in 0 to (number_of_elements - 3) generate
b(((gf_2_m)*(Index + 2) - 1) downto ((gf_2_m)*(Index + 1))) <= a(((gf_2_m)*(Index + 3) - 1) downto ((gf_2_m)*(Index + 2))) xor b(((gf_2_m)*(Index + 1) - 1) downto ((gf_2_m)*(Index)));
end generate;
end generate;
o <= b(((gf_2_m)*(number_of_elements - 1) - 1) downto ((gf_2_m)*(number_of_elements - 2)));
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compar_fsm is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector(1 downto 0);
--this is pair of bits of two numbers, a0b0, a1b1, etc.., easier to process
o: out std_logic_vector(1 downto 0)
-- 00 is equal, 10 a is bigger, 01 b is bigger
);
end entity;
architecture compar_fsm of compar_fsm is
type state_type is (A,B,C);
signal state : state_type := C;
begin
process(clk)
begin
if reset = '1' then
state<=C;
o<="00";
elsif rising_edge(clk) then
case state is
when C =>
o<="00";
if (ab(0)='1' and ab(1)='0') then
state<=B;
o<="01";
elsif (ab(0)='0' and ab(1)='1') then
state<=A;
o<="10";
else
state<=C;
end if;
when B =>
o<="01";
if (ab(0)='0' and ab(1)='1') then
state<=A;
o<="10";
else
state<=B;
o<="01";
end if;
when A =>
o<="10";
if (ab(0)='1' and ab(1)='0') then
state<=B;
o<="01";
else
state<=A;
o<="10";
end if;
when others => NULL;
end case;
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00418ent IS
END c03s02b01x01p19n01i00418ent;
ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
type integer_cons_vector is array (15 downto 0) of integer;
constant C1 : integer_cons_vector := (others => 3);
function complex_scalar(s : integer_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_cons_vector;
signal S2 : integer_cons_vector;
signal S3 : integer_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00418"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00418arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00418ent IS
END c03s02b01x01p19n01i00418ent;
ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
type integer_cons_vector is array (15 downto 0) of integer;
constant C1 : integer_cons_vector := (others => 3);
function complex_scalar(s : integer_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_cons_vector;
signal S2 : integer_cons_vector;
signal S3 : integer_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00418"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00418arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00418ent IS
END c03s02b01x01p19n01i00418ent;
ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
type integer_cons_vector is array (15 downto 0) of integer;
constant C1 : integer_cons_vector := (others => 3);
function complex_scalar(s : integer_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_cons_vector;
signal S2 : integer_cons_vector;
signal S3 : integer_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00418"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00418arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc820.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b01x00p03n01i00820ent IS
END c01s02b01x00p03n01i00820ent;
ARCHITECTURE c01s02b01x00p03n01i00820arch_empty OF c01s02b01x00p03n01i00820ent IS
BEGIN
END c01s02b01x00p03n01i00820arch_empty;
ARCHITECTURE c01s02b01x00p03n01i00820arch OF c01s02b01x00p03n01i00820ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s02b01x00p03n01i00820"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s02b01x00p03n01i00820arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc820.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b01x00p03n01i00820ent IS
END c01s02b01x00p03n01i00820ent;
ARCHITECTURE c01s02b01x00p03n01i00820arch_empty OF c01s02b01x00p03n01i00820ent IS
BEGIN
END c01s02b01x00p03n01i00820arch_empty;
ARCHITECTURE c01s02b01x00p03n01i00820arch OF c01s02b01x00p03n01i00820ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s02b01x00p03n01i00820"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s02b01x00p03n01i00820arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc820.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b01x00p03n01i00820ent IS
END c01s02b01x00p03n01i00820ent;
ARCHITECTURE c01s02b01x00p03n01i00820arch_empty OF c01s02b01x00p03n01i00820ent IS
BEGIN
END c01s02b01x00p03n01i00820arch_empty;
ARCHITECTURE c01s02b01x00p03n01i00820arch OF c01s02b01x00p03n01i00820ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s02b01x00p03n01i00820"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s02b01x00p03n01i00820arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 02:47:07 PM
-- Design Name:
-- Module Name: decryptionFinalCore_V1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionFinalCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end decryptionFinalCore_V1;
architecture Behavioral of decryptionFinalCore_V1 is
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
signal mu0_Out, mu1_Out, mu2_Out, mu3_Out, mu4_Out, mu5_Out : STD_LOGIC_VECTOR(31 downto 0);
signal invSubBytes_In, invSubBytes_Out, addRoundKey_KeyIn: STD_LOGIC_VECTOR(31 downto 0);
signal invShiftRows_In, invShiftRows_Out : STD_LOGIC_VECTOR(127 downto 0);
signal ZERO_BIT : STD_LOGIC := '0';
signal ZERO_WORD : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ZERO_BIT <= '0';
ZERO_WORD <= (others => '0');
mu0: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => WORD_IN,
wordBIn => ZERO_WORD,
wordOut => mu0_Out);
mu1: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu0_Out,
wordBIn => ZERO_WORD,
wordOut => mu1_Out);
mu2: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu1_Out,
wordBIn => ZERO_WORD,
wordOut => mu2_Out);
invShiftRows_In <= mu2_Out & mu1_Out & mu0_Out & WORD_IN;
invShiftRows0: invShiftRows port map( CLK => CLK,
RESET => RESET,
blockIn => invShiftRows_In,
blockOut => invShiftRows_Out);
mu3: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => invShiftRows_Out(31 downto 0),
wordBIn => invShiftRows_Out(31 downto 0),
wordOut => mu3_Out);
mu4: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu3_Out,
wordBIn => invShiftRows_Out(63 downto 32),
wordOut => mu4_Out);
mu5: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu4_Out,
wordBIn => invShiftRows_Out(95 downto 64),
wordOut => mu5_Out);
invSubBytes_In <= invShiftRows_Out(127 downto 96) when (memorySourceSelector = '1')
else mu5_Out;
invSubBytes0: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(7 downto 0),
byteOut => invSubBytes_Out(7 downto 0));
invSubBytes1: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(15 downto 8),
byteOut => invSubBytes_Out(15 downto 8));
invSubBytes2: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(23 downto 16),
byteOut => invSubBytes_Out(23 downto 16));
invSubBytes3: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(31 downto 24),
byteOut => invSubBytes_Out(31 downto 24));
addRoundKeySelector: process(cipherKey, keySelector)
begin
case keySelector is
when "11" => addRoundKey_KeyIn <= cipherKey(127 downto 96);
when "10" => addRoundKey_KeyIn <= cipherKey(95 downto 64);
when "01" => addRoundKey_KeyIn <= cipherKey(63 downto 32);
when "00" => addRoundKey_KeyIn <= cipherKey(31 downto 0);
when others => addRoundKey_KeyIn <= (others => '0');
end case;
end process;
addRoundKey0: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => invSubBytes_Out,
keyIn => addRoundKey_KeyIn,
wordOut => WORD_OUT);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
package DataStructures is
-- Simple hashing functions
function Modulo_Int (d : integer; size : positive) return natural;
function Modulo (d : string; size : positive) return natural;
-- Dictionaries
package Integer_Integer_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => integer,
to_hash => Modulo_Int);
package Integer_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo_Int);
package String_String_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => string,
to_hash => Modulo);
package String_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo);
-- Aliases for convenience reasons
alias Integer_Integer_Dict is Integer_Integer_Dict_Pkg.PT_DICT;
alias Integer_Slv_Dict is Integer_StdLogicVector_Dict_Pkg.PT_DICT;
alias String_String_Dict is String_String_Dict_Pkg.PT_DICT;
alias String_Slv_Dict is String_StdLogicVector_Dict_Pkg.PT_DICT;
end package;
package body DataStructures is
-- Simple modulo function for integers
function Modulo_int (d : integer; size : positive) return natural is
begin
return d mod size;
end function Modulo_Int;
-- Simple modulo function for ISO 8859 Latin-1 8-bit strings
-- of arbitrary length (>= VHDL 93)
function Modulo (d : string; size : positive) return natural is
variable hash : natural := 0;
begin
assert size <= ((natural'high - 255) / 256 + 1)
report Modulo[string, natural return natural]'instance_name & ": size parameter too large, possible overflow"
severity failure;
for i in d'range loop
hash := (hash * 256 + Character'Pos (d(i))) mod size;
end loop;
return hash;
end function Modulo;
end package body DataStructures;
|
library ieee;
use ieee.std_logic_1164.all;
package DataStructures is
-- Simple hashing functions
function Modulo_Int (d : integer; size : positive) return natural;
function Modulo (d : string; size : positive) return natural;
-- Dictionaries
package Integer_Integer_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => integer,
to_hash => Modulo_Int);
package Integer_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo_Int);
package String_String_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => string,
to_hash => Modulo);
package String_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo);
-- Aliases for convenience reasons
alias Integer_Integer_Dict is Integer_Integer_Dict_Pkg.PT_DICT;
alias Integer_Slv_Dict is Integer_StdLogicVector_Dict_Pkg.PT_DICT;
alias String_String_Dict is String_String_Dict_Pkg.PT_DICT;
alias String_Slv_Dict is String_StdLogicVector_Dict_Pkg.PT_DICT;
end package;
package body DataStructures is
-- Simple modulo function for integers
function Modulo_int (d : integer; size : positive) return natural is
begin
return d mod size;
end function Modulo_Int;
-- Simple modulo function for ISO 8859 Latin-1 8-bit strings
-- of arbitrary length (>= VHDL 93)
function Modulo (d : string; size : positive) return natural is
variable hash : natural := 0;
begin
assert size <= ((natural'high - 255) / 256 + 1)
report Modulo[string, natural return natural]'instance_name & ": size parameter too large, possible overflow"
severity failure;
for i in d'range loop
hash := (hash * 256 + Character'Pos (d(i))) mod size;
end loop;
return hash;
end function Modulo;
end package body DataStructures;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
--
-------------------------------------------------------------------------------------------
-- Copyright 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
--
-- _ ______ ____ ____ __ __ __
-- | |/ / ___| _ \/ ___|| \/ |/ /_
-- | ' / | | |_) \___ \| |\/| | '_ \
-- | . \ |___| __/ ___) | | | | (_) |
-- |_|\_\____|_| |____/|_| |_|\___/
--
--
--
-- This reference design is to illustrate a way in which a KCPSM6 processor can implement
-- a PMBus protocol and communicate with the UCD9248 power supply controller
-- (Texas Instruments) on the KC705 board. The design also implements a bridge between a
-- UART and a Block Memory (BRAM) within a device so that information associated with the
-- power supply controller can be observed both outside of the device and by another
-- circuit connected to the second port of the BRAM at some point in the future.
--
-- It implements a 115200 baud, 1 stop bit, no parity, no handshake UART connection
-- providing simple text based commands which enable the BRAM treated as 1K words of
-- 32-bits to be read from and written to.
--
-- All data values are represented as 8-digit hexadecimal values.
--
-- Whilst this bridge design could be more efficiently implemented by exploiting the
-- ability for the port of the BRAM to be configured as 9-bits (8-bits plus parity) a
-- full 32-bit data path has been created. The reason for this is that it has been
-- designed initially for an application in which the second port of the BRAM will be
-- used in a 32-bit application. It may be important that all bytes within a 32-bit
-- location are read or written in one transaction (i.e. If four byte transactions
-- were used by this bridge to write a new 32-bit value then the 32-bit application
-- may observe a the intermediate values which would be undesirable).
--
-- If a frequency applied to the bridge module is not 50MHz then the KCPSM6 program will
-- require some adjustments to maintain the same communication settings.
--
-- IMPORTANT: The BRAM must be connected to this module using the same 50MHz clock
-- (Synchronous interface).
--
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
-------------------------------------------------------------------------------------------
--
--
entity clock_control is
Port (
i2c_clk : inout std_logic;
i2c_data : inout std_logic;
i2c_mux_rst_n : out std_logic;
si5324_rst_n : out std_logic;
rst : in std_logic;
clk50 : in std_logic);
end clock_control;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of clock_control is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- KCPSM6 Program Memory with option for JTAG Loader
--
component clock_control_program
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
--
--
--
signal drive_i2c_clk : std_logic;
signal drive_i2c_data : std_logic;
signal i2c_mux_rst_b_int : std_logic;
signal si5324_rst_n_int : std_logic;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of Behavioral : architecture is "v7_xt_conn_trd,v7_xt_conn_trd_v1_1_clock_control,{clock_control=2013.2}";
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
i2c_mux_rst_n <= i2c_mux_rst_b_int; -- active low reset
si5324_rst_n <= si5324_rst_n_int;
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter. The interrupt vector
-- has been set to address 7F0 which would provide 16 instructions to implement an
-- interrupt service route (ISR) before the end of a 2K program space. Interrupt is not
-- used in this design at this time but could be exploited in the future.
--
processor: kcpsm6
generic map ( hwbuild => X"41", -- ASCII Character "A"
interrupt_vector => X"7F0",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk50);
kcpsm6_reset <= rdl or rst;
kcpsm6_sleep <= '0';
interrupt <= interrupt_ack;
--
-- Program memory up to 4k with JTAG Loader option
--
program_rom: clock_control_program
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 0)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk50);
--
-----------------------------------------------------------------------------------------
-- Connections to I2C Bus
-----------------------------------------------------------------------------------------
--
-- The data and clock should be treated as open collector bidirectional signals which
-- use a pull-up on the board to generate a High level.
--
i2c_clk <= '0' when drive_i2c_clk = '0' else 'Z';
i2c_data <= '0' when drive_i2c_data = '0' else 'Z';
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
output_ports: process(clk50)
begin
if clk50'event and clk50 = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Write to status bits at port address 04 hex
if port_id(2) = '1' then
i2c_mux_rst_b_int <= out_port(0);
si5324_rst_n_int <= out_port(1);
end if;
-- Write to I2C Bus at port address 08 hex
if port_id(3) = '1' then
drive_i2c_clk <= out_port(0);
drive_i2c_data <= out_port(1);
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
input_ports: process (clk50)
begin
if clk50'event and clk50 = '1' then
case port_id(2 downto 0) is
-- Read I2C Bus at port address 06 hex
when "110" => in_port(0) <= i2c_clk;
in_port(1) <= i2c_data;
when others => in_port <= (others => '0');
end case;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE clock_control.vhd
--
-------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- Title : Minicircuits Serial Controller Testbench
------------------------------------------------------------------------------
-- Author : Daniel de Oliveira Tavares
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simulation of mc_serial_ctrl with 100101 as data_i
-- and g_clkdiv = 17 as divider of clk_i.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 daniel.tavares Created
-- 2012-10-16 1.1 jose.berkenbrock Names Adpated
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mc_serial_ctrl_tb is
end mc_serial_ctrl_tb;
architecture behavior of mc_serial_ctrl_tb is
-- component Declaration for the Unit Under Test (UUT)
component mc_serial_ctrl
generic(
g_nbits : natural := 6;
g_clkdiv : natural := 128
);
port(
clk_i : in std_logic;
trg_i : in std_logic;
data_i : in std_logic_vector(5 downto 0);
clk_o : out std_logic;
data_o : out std_logic;
le_o : out std_logic
);
end component;
--inputs
signal clk_i : std_logic := '0';
signal trg_i : std_logic := '0';
signal data_i : std_logic_vector(5 downto 0) := (others => '0');
--outputs
signal clk_o : std_logic;
signal data_o : std_logic;
signal le_o : std_logic;
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- instantiate the Unit Under Test (UUT)
uut: mc_serial_ctrl
generic map (
g_clkdiv => 17
)
port map (
clk_i => clk_i,
trg_i => trg_i,
data_i => data_i,
clk_o => clk_o,
data_o => data_o,
le_o => le_o
);
-- Clock process definitions
p_clk_i :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
p_stim: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_i_period*10;
-- insert stimulus here
trg_i <= '1';
data_i <= "100101";
wait for clk_i_period;
trg_i <= '0';
wait;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc96.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p12n02i00096ent IS
generic ( constant c1 : in integer := true );-- Failure_here
END c04s03b02x00p12n02i00096ent;
ARCHITECTURE c04s03b02x00p12n02i00096arch OF c04s03b02x00p12n02i00096ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p12n02i00096 - The type of the default object is not the same as the corresponding interface element."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p12n02i00096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc96.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p12n02i00096ent IS
generic ( constant c1 : in integer := true );-- Failure_here
END c04s03b02x00p12n02i00096ent;
ARCHITECTURE c04s03b02x00p12n02i00096arch OF c04s03b02x00p12n02i00096ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p12n02i00096 - The type of the default object is not the same as the corresponding interface element."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p12n02i00096arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc96.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p12n02i00096ent IS
generic ( constant c1 : in integer := true );-- Failure_here
END c04s03b02x00p12n02i00096ent;
ARCHITECTURE c04s03b02x00p12n02i00096arch OF c04s03b02x00p12n02i00096ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p12n02i00096 - The type of the default object is not the same as the corresponding interface element."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p12n02i00096arch;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 16/07/2014
--! Module Name: MUX2_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--! MUX 2x1, data 16 bit
entity MUX2_Nbit is
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX2_Nbit;
--architecture low_level_MUX2_Nbit of MUX2_Nbit is
--begin
--GENERATE_BIT_MUX2: for I in 0 to (N-1) generate
--MUXF7n : MUXF7 port map (data_out(I), data0(I), data1(I), sel);
--end generate GENERATE_BIT_MUX2;
--end low_level_MUX2_Nbit;
architecture behavioral of MUX2_Nbit is
begin
process(data0, data1, sel)
begin
if sel = '0' then
data_out <= data0;
else
data_out <= data1;
end if;
end process;
end behavioral; |
Subsets and Splits