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module ibuf (o, i);
parameter capacitance = "dont_care";
parameter ibuf_delay_value = "0";
parameter ibuf_low_pwr = "true";
parameter ifd_delay_value = "auto";
parameter iostandard = "default";
`ifdef xil_timing
parameter loc = " unplaced";
`endif
output o;
input i;
buf b1 (o, i);
initial begin
case (capacitance)
"low", "normal", "dont_care" : ;
default : begin
$display("attribute syntax error : the attribute capacitance on ibuf instance %m is set to %s. legal values for this attribute are dont_care, low or normal.", capacitance);
#1 $finish;
end
endcase
case (ibuf_delay_value)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("attribute syntax error : the attribute ibuf_delay_value on ibuf instance %m is set to %s. legal values for this attribute are 0, 1, 2, ... or 16.", ibuf_delay_value);
#1 $finish;
end
endcase
case (ibuf_low_pwr)
"false", "true" : ;
default : begin
$display("attribute syntax error : the attribute ibuf_low_pwr on ibuf instance %m is set to %s. legal values for this attribute are true or false.", ibuf_low_pwr);
#1 $finish;
end
endcase
case (ifd_delay_value)
"auto", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("attribute syntax error : the attribute ifd_delay_value on ibuf instance %m is set to %s. legal values for this attribute are auto, 0, 1, 2, ... or 8.", ifd_delay_value);
#1 $finish;
end
endcase
end
`ifdef xil_timing
specify
(i => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module ibufds (o, i, ib);
`ifdef xil_timing
parameter loc = "unplaced";
`endif
parameter capacitance = "dont_care";
parameter diff_term = "false";
parameter dqs_bias = "false";
parameter ibuf_delay_value = "0";
parameter ibuf_low_pwr = "true";
parameter ifd_delay_value = "auto";
parameter iostandard = "default";
localparam module_name = "ibufds";
output o;
input i, ib;
wire i_in, ib_in;
reg o_out;
reg dqs_bias_binary = 1'b0;
assign o = o_out;
assign i_in = i;
assign ib_in = ib;
initial begin
case (dqs_bias)
"true" : dqs_bias_binary <= #1 1'b1;
"false" : dqs_bias_binary <= #1 1'b0;
default : begin
$display("attribute syntax error : the attribute dqs_bias on %s instance %m is set to %s. legal values for this attribute are true or false.", module_name, dqs_bias);
#1 $finish;
end
endcase
case (capacitance)
"low", "normal", "dont_care" : ;
default : begin
$display("attribute syntax error : the attribute capacitance on %s instance %m is set to %s. legal values for this attribute are dont_care, low or normal.", module_name, capacitance);
#1 $finish;
end
endcase
case (diff_term)
"true", "false" : ;
default : begin
$display("attribute syntax error : the attribute diff_term on %s instance %m is set to %s. legal values for this attribute are true or false.", module_name, diff_term);
#1 $finish;
end
endcase
case (ibuf_delay_value)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("attribute syntax error : the attribute ibuf_delay_value on %s instance %m is set to %s. legal values for this attribute are 0, 1, 2, ... or 16.", module_name, ibuf_delay_value);
#1 $finish;
end
endcase
case (ibuf_low_pwr)
"false", "true" : ;
default : begin
$display("attribute syntax error : the attribute ibuf_low_pwr on %s instance %m is set to %s. legal values for this attribute are true or false.", module_name, ibuf_low_pwr);
#1 $finish;
end
endcase
case (ifd_delay_value)
"auto", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("attribute syntax error : the attribute ifd_delay_value on %s instance %m is set to %s. legal values for this attribute are auto, 0, 1, 2, ... or 8.", module_name, ifd_delay_value);
#1 $finish;
end
endcase
end
always @(i_in or ib_in or dqs_bias_binary) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (dqs_bias_binary == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef xil_timing
specify
(i => o) = (0:0:0, 0:0:0);
(ib => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module ibufgds (o, i, ib);
parameter capacitance = "dont_care";
parameter diff_term = "false";
parameter ibuf_delay_value = "0";
parameter ibuf_low_pwr = "true";
parameter iostandard = "default";
`ifdef xil_timing
parameter loc = "unplaced";
`endif
output o;
input i, ib;
reg o_out;
buf b_0 (o, o_out);
always @(i or ib) begin
if (i == 1'b1 && ib == 1'b0)
o_out <= i;
else if (i == 1'b0 && ib == 1'b1)
o_out <= i;
end
endmodule |
module idelayctrl #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter sim_device = "7series"
)(
output rdy,
input refclk,
input rst
);
localparam module_name = "idelayctrl";
localparam sim_device_7series = 0;
localparam sim_device_ultrascale = 1;
reg trig_attr = 1'b0;
localparam [80:1] sim_device_reg = sim_device;
`ifdef xil_attr_test
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
reg rdy_out = 0;
wire refclk_in;
wire rst_in;
`ifdef xil_timing
wire refclk_delay;
wire rst_delay;
`endif
assign rdy = rdy_out;
`ifdef xil_timing
assign refclk_in = refclk_delay;
assign rst_in = rst_delay;
`else
assign refclk_in = refclk;
assign rst_in = rst;
`endif
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg lost;
reg msg_flag = 1'b0;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((sim_device_reg != "7series") &&
(sim_device_reg != "ultrascale"))) begin
$display("error: [unisim %s-104] sim_device attribute is set to %s. legal values for this attribute are 7series or ultrascale. instance: %m", module_name, sim_device_reg);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
always @(rst_in, lost) begin
if (rst_in == 1'b1) begin
rdy_out <= 1'b0;
end else if (lost == 1)
rdy_out <= 1'b0;
else if (rst_in == 1'b0 && lost == 0)
rdy_out <= 1'b1;
end
always @(posedge rst_in) begin
if (sim_device_reg == "ultrascale" && msg_flag == 1'b0) begin
$display("info: [unisim %s-1] rst simulation behaviour for sim_device %s may not match hardware behaviour when i/odelay delay_format = time if selectio user guide recommendation for i/odelay connections or reset sequence are not followed. for more information, refer to the select io userguide. instance: %m", module_name, sim_device_reg);
msg_flag <= 1'b1;
end
end
initial begin
clock_edge <= 0;
clock_high <= 0;
clock_low <= 0;
lost <= 1;
period <= 0;
end
always @(posedge refclk_in) begin
if(rst_in == 1'b0) begin
clock_edge <= $time;
if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
period <= $time - clock_edge;
else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
period <= 0;
else if ((period == 0) && (clock_edge != 0))
period <= $time - clock_edge;
end
end
always @(posedge refclk_in) begin
clock_low <= 1'b0;
clock_high <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_posedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
lost <= 1;
end
always @(posedge refclk_in) begin
clock_negedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_posedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_high <= 1'b0;
clock_low <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_negedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
lost <= 1;
end
`ifdef xil_timing
reg notifier;
`endif
specify
(rst => rdy) = (0:0:0, 0:0:0);
(posedge rst => (rdy +: 0)) = (0:0:0, 0:0:0);
(refclk => rdy) = (100:100:100, 100:100:100);
`ifdef xil_timing
$period (negedge refclk, 0:0:0, notifier);
$period (posedge refclk, 0:0:0, notifier);
$recrem (negedge rst, posedge refclk, 0:0:0, 0:0:0, notifier, , , rst_delay, refclk_delay);
$recrem (posedge rst, posedge refclk, 0:0:0, 0:0:0, notifier, , , rst_delay, refclk_delay);
$width (negedge refclk, 0:0:0, 0, notifier);
$width (negedge rst, 0:0:0, 0, notifier);
$width (posedge refclk, 0:0:0, 0, notifier);
$width (posedge rst, 0:0:0, 0, notifier);
`endif
specparam pathpulse$ = 0;
endspecify
endmodule |
module lut4 #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter [15:0] init = 16'h0000
)(
output o,
input i0,
input i1,
input i2,
input i3
);
localparam module_name = "lut4";
reg trig_attr = 1'b0;
`ifdef xil_dr
`include "lut4_dr.v"
`else
reg [15:0] init_reg = init;
`endif
reg o_out;
assign o = o_out;
function lut_mux4_f;
input [3:0] d;
input [1:0] s;
begin
if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0))
lut_mux4_f = d[s];
else if ( ~(|d) || &d)
lut_mux4_f = d[0];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}]))
lut_mux4_f = d[{1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}]))
lut_mux4_f = d[{s[1],1'b0}];
else
lut_mux4_f = 1'bx;
end
endfunction
always @(i0 or i1 or i2 or i3) begin
if ( (i0 ^ i1 ^ i2 ^ i3) === 1'b0 || (i0 ^ i1 ^ i2 ^ i3) === 1'b1)
o_out = init_reg[{i3, i2, i1, i0}];
else if ( ~(|init_reg) || &init_reg )
o_out = init_reg[0];
else
o_out = lut_mux4_f ({lut_mux4_f (init_reg[15:12], {i1, i0}),
lut_mux4_f ( init_reg[11:8], {i1, i0}),
lut_mux4_f ( init_reg[7:4], {i1, i0}),
lut_mux4_f ( init_reg[3:0], {i1, i0})}, {i3, i2});
end
`ifdef xil_timing
specify
(i0 => o) = (0:0:0, 0:0:0);
(i1 => o) = (0:0:0, 0:0:0);
(i2 => o) = (0:0:0, 0:0:0);
(i3 => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module lut6 #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter [63:0] init = 64'h0000000000000000
)(
output o,
input i0,
input i1,
input i2,
input i3,
input i4,
input i5
);
localparam module_name = "lut6";
reg trig_attr = 1'b0;
`ifdef xil_dr
`include "lut6_dr.v"
`else
reg [63:0] init_reg = init;
`endif
reg o_out;
assign o = o_out;
function lut_mux8_f;
input [7:0] d;
input [2:0] s;
begin
if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0))
lut_mux8_f = d[s];
else if ( ~(|d) || &d)
lut_mux8_f = d[0];
else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) &&
(d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}]))
lut_mux8_f = d[{1'b0,s[1:0]}];
else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) &&
(d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}]))
lut_mux8_f = d[{s[2],1'b0,s[0]}];
else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) &&
(d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}]))
lut_mux8_f = d[{s[2:1],1'b0}];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}]))
lut_mux8_f = d[{1'b0,1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}]))
lut_mux8_f = d[{1'b0,s[1],1'b0}];
else if (((s[2] === 1'b1) || (s[2] === 1'b0)) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}]))
lut_mux8_f = d[{s[2],1'b0,1'b0}];
else
lut_mux8_f = 1'bx;
end
endfunction
always @(i0 or i1 or i2 or i3 or i4 or i5) begin
if ( (i0 ^ i1 ^ i2 ^ i3 ^ i4 ^ i5) === 1'b0 || (i0 ^ i1 ^ i2 ^ i3 ^ i4 ^ i5) === 1'b1)
o_out = init_reg[{i5, i4, i3, i2, i1, i0}];
else if ( ~(|init_reg) || &init_reg )
o_out = init_reg[0];
else
o_out = lut_mux8_f ({lut_mux8_f (init_reg[63:56], {i2, i1, i0}),
lut_mux8_f (init_reg[55:48], {i2, i1, i0}),
lut_mux8_f (init_reg[47:40], {i2, i1, i0}),
lut_mux8_f (init_reg[39:32], {i2, i1, i0}),
lut_mux8_f (init_reg[31:24], {i2, i1, i0}),
lut_mux8_f (init_reg[23:16], {i2, i1, i0}),
lut_mux8_f ( init_reg[15:8], {i2, i1, i0}),
lut_mux8_f ( init_reg[7:0], {i2, i1, i0})}, {i5, i4, i3});
end
`ifdef xil_timing
specify
(i0 => o) = (0:0:0, 0:0:0);
(i1 => o) = (0:0:0, 0:0:0);
(i2 => o) = (0:0:0, 0:0:0);
(i3 => o) = (0:0:0, 0:0:0);
(i4 => o) = (0:0:0, 0:0:0);
(i5 => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module lut6_2 #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter [63:0] init = 64'h0000000000000000
)(
output o5,
output o6,
input i0,
input i1,
input i2,
input i3,
input i4,
input i5
);
localparam module_name = "lut6_2";
reg trig_attr = 1'b0;
`ifdef xil_dr
`include "lut6_2_dr.v"
`else
reg [63:0] init_reg = init;
`endif
reg o5_out;
reg o6_out;
assign o5 = o5_out;
assign o6 = o6_out;
function lut_mux4_f;
input [3:0] d;
input [1:0] s;
begin
if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0))
lut_mux4_f = d[s];
else if ( ~(|d) || &d)
lut_mux4_f = d[0];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}]))
lut_mux4_f = d[{1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}]))
lut_mux4_f = d[{s[1],1'b0}];
else
lut_mux4_f = 1'bx;
end
endfunction
function lut_mux8_f;
input [7:0] d;
input [2:0] s;
begin
if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0))
lut_mux8_f = d[s];
else if ( ~(|d) || &d)
lut_mux8_f = d[0];
else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) &&
(d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}]))
lut_mux8_f = d[{1'b0,s[1:0]}];
else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) &&
(d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}]))
lut_mux8_f = d[{s[2],1'b0,s[0]}];
else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) &&
(d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}]))
lut_mux8_f = d[{s[2:1],1'b0}];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}]))
lut_mux8_f = d[{1'b0,1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}]))
lut_mux8_f = d[{1'b0,s[1],1'b0}];
else if (((s[2] === 1'b1) || (s[2] === 1'b0)) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}]))
lut_mux8_f = d[{s[2],1'b0,1'b0}];
else
lut_mux8_f = 1'bx;
end
endfunction
always @(i0 or i1 or i2 or i3 or i4) begin
if ( (i0 ^ i1 ^ i2 ^ i3 ^ i4) === 1'b0 || (i0 ^ i1 ^ i2 ^ i3 ^ i4) === 1'b1)
o5_out = init_reg[{i4, i3, i2, i1, i0}];
else if ( ~(|init_reg[31:0]) || &init_reg[31:0] )
o5_out = init_reg[0];
else
o5_out = lut_mux4_f ({lut_mux8_f (init_reg[31:24], {i2, i1, i0}),
lut_mux8_f (init_reg[23:16], {i2, i1, i0}),
lut_mux8_f ( init_reg[15:8], {i2, i1, i0}),
lut_mux8_f ( init_reg[7:0], {i2, i1, i0})}, {i4, i3});
end
always @(i0 or i1 or i2 or i3 or i4 or i5) begin
if ( (i0 ^ i1 ^ i2 ^ i3 ^ i4 ^ i5) === 1'b0 || (i0 ^ i1 ^ i2 ^ i3 ^ i4 ^ i5) === 1'b1)
o6_out = init_reg[{i5, i4, i3, i2, i1, i0}];
else if ( ~(|init_reg) || &init_reg )
o6_out = init_reg[0];
else
o6_out = lut_mux8_f ({lut_mux8_f (init_reg[63:56], {i2, i1, i0}),
lut_mux8_f (init_reg[55:48], {i2, i1, i0}),
lut_mux8_f (init_reg[47:40], {i2, i1, i0}),
lut_mux8_f (init_reg[39:32], {i2, i1, i0}),
lut_mux8_f (init_reg[31:24], {i2, i1, i0}),
lut_mux8_f (init_reg[23:16], {i2, i1, i0}),
lut_mux8_f ( init_reg[15:8], {i2, i1, i0}),
lut_mux8_f ( init_reg[7:0], {i2, i1, i0})}, {i5, i4, i3});
end
`ifdef xil_timing
specify
(i0 => o5) = (0:0:0, 0:0:0);
(i1 => o5) = (0:0:0, 0:0:0);
(i2 => o5) = (0:0:0, 0:0:0);
(i3 => o5) = (0:0:0, 0:0:0);
(i4 => o5) = (0:0:0, 0:0:0);
(i0 => o6) = (0:0:0, 0:0:0);
(i1 => o6) = (0:0:0, 0:0:0);
(i2 => o6) = (0:0:0, 0:0:0);
(i3 => o6) = (0:0:0, 0:0:0);
(i4 => o6) = (0:0:0, 0:0:0);
(i5 => o6) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module muxcy (o, ci, di, s);
`ifdef xil_timing
parameter loc = "unplaced";
`endif
output o;
input ci, di, s;
reg o_out;
always @(ci or di or s)
if (s)
o_out = ci;
else
o_out = di;
assign o = o_out;
`ifdef xil_timing
specify
(ci => o) = (0:0:0, 0:0:0);
(di => o) = (0:0:0, 0:0:0);
(s => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module ram32m #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter [63:0] init_a = 64'h0000000000000000,
parameter [63:0] init_b = 64'h0000000000000000,
parameter [63:0] init_c = 64'h0000000000000000,
parameter [63:0] init_d = 64'h0000000000000000,
parameter [0:0] is_wclk_inverted = 1'b0
)(
output [1:0] doa,
output [1:0] dob,
output [1:0] doc,
output [1:0] dod,
input [4:0] addra,
input [4:0] addrb,
input [4:0] addrc,
input [4:0] addrd,
input [1:0] dia,
input [1:0] dib,
input [1:0] dic,
input [1:0] did,
input wclk,
input we
);
localparam module_name = "ram32m";
reg trig_attr = 1'b0;
`ifdef xil_attr_test
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire is_wclk_inverted_bin;
wire [4:0] addrd_in;
wire [1:0] dia_in;
wire [1:0] dib_in;
wire [1:0] dic_in;
wire [1:0] did_in;
wire wclk_in;
wire we_in;
`ifdef xil_timing
wire [4:0] addrd_dly;
wire [1:0] dia_dly;
wire [1:0] dib_dly;
wire [1:0] dic_dly;
wire [1:0] did_dly;
wire wclk_dly;
wire we_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign addrd_in = addrd_dly;
assign dia_in = dia_dly;
assign dib_in = dib_dly;
assign dic_in = dic_dly;
assign did_in = did_dly;
assign wclk_in = wclk_dly ^ is_wclk_inverted_bin;
assign we_in = (we === 1'bz) || we_dly; `else
assign addrd_in = addrd;
assign dia_in = dia;
assign dib_in = dib;
assign dic_in = dic;
assign did_in = did;
assign wclk_in = wclk ^ is_wclk_inverted_bin;
assign we_in = (we === 1'bz) || we; `endif
assign is_wclk_inverted_bin = is_wclk_inverted;
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [5:0] addr_in2, addr_in1;
initial begin
mem_a = init_a;
mem_b = init_b;
mem_c = init_c;
mem_d = init_d;
end
always @(addrd_in) begin
addr_in2 = 2 * addrd_in;
addr_in1 = 2 * addrd_in + 1;
end
always @(posedge wclk_in)
if (we_in) begin
mem_a[addr_in2] <= #100 dia_in[0];
mem_a[addr_in1] <= #100 dia_in[1];
mem_b[addr_in2] <= #100 dib_in[0];
mem_b[addr_in1] <= #100 dib_in[1];
mem_c[addr_in2] <= #100 dic_in[0];
mem_c[addr_in1] <= #100 dic_in[1];
mem_d[addr_in2] <= #100 did_in[0];
mem_d[addr_in1] <= #100 did_in[1];
end
assign doa[0] = mem_a[2*addra];
assign doa[1] = mem_a[2*addra + 1];
assign dob[0] = mem_b[2*addrb];
assign dob[1] = mem_b[2*addrb + 1];
assign doc[0] = mem_c[2*addrc];
assign doc[1] = mem_c[2*addrc + 1];
assign dod[0] = mem_d[2*addrd_in];
assign dod[1] = mem_d[2*addrd_in + 1];
`ifdef xil_timing
always @(notifier) begin
mem_a[addr_in2] <= 1'bx;
mem_a[addr_in1] <= 1'bx;
mem_b[addr_in2] <= 1'bx;
mem_b[addr_in1] <= 1'bx;
mem_c[addr_in2] <= 1'bx;
mem_c[addr_in1] <= 1'bx;
mem_d[addr_in2] <= 1'bx;
mem_d[addr_in1] <= 1'bx;
end
assign sh_clk_en_p = ~is_wclk_inverted_bin;
assign sh_clk_en_n = is_wclk_inverted_bin;
assign sh_we_clk_en_p = we_in && ~is_wclk_inverted_bin;
assign sh_we_clk_en_n = we_in && is_wclk_inverted_bin;
specify
(wclk => doa[0]) = (0:0:0, 0:0:0);
(wclk => doa[1]) = (0:0:0, 0:0:0);
(wclk => dob[0]) = (0:0:0, 0:0:0);
(wclk => dob[1]) = (0:0:0, 0:0:0);
(wclk => doc[0]) = (0:0:0, 0:0:0);
(wclk => doc[1]) = (0:0:0, 0:0:0);
(wclk => dod[0]) = (0:0:0, 0:0:0);
(wclk => dod[1]) = (0:0:0, 0:0:0);
(addra *> doa[0]) = (0:0:0, 0:0:0);
(addra *> doa[1]) = (0:0:0, 0:0:0);
(addrb *> dob[0]) = (0:0:0, 0:0:0);
(addrb *> dob[1]) = (0:0:0, 0:0:0);
(addrc *> doc[0]) = (0:0:0, 0:0:0);
(addrc *> doc[1]) = (0:0:0, 0:0:0);
(addrd *> dod[0]) = (0:0:0, 0:0:0);
(addrd *> dod[1]) = (0:0:0, 0:0:0);
$period (negedge wclk &&& we, 0:0:0, notifier);
$period (posedge wclk &&& we, 0:0:0, notifier);
$setuphold (negedge wclk, negedge addrd[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[0]);
$setuphold (negedge wclk, negedge addrd[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[1]);
$setuphold (negedge wclk, negedge addrd[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[2]);
$setuphold (negedge wclk, negedge addrd[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[3]);
$setuphold (negedge wclk, negedge addrd[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[4]);
$setuphold (negedge wclk, negedge dia[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dia_dly[0]);
$setuphold (negedge wclk, negedge dia[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dia_dly[1]);
$setuphold (negedge wclk, negedge dib[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dib_dly[0]);
$setuphold (negedge wclk, negedge dib[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dib_dly[1]);
$setuphold (negedge wclk, negedge dic[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dic_dly[0]);
$setuphold (negedge wclk, negedge dic[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dic_dly[1]);
$setuphold (negedge wclk, negedge did[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,did_dly[0]);
$setuphold (negedge wclk, negedge did[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,did_dly[1]);
$setuphold (negedge wclk, negedge we, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,wclk_dly,we_dly);
$setuphold (negedge wclk, posedge addrd[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[0]);
$setuphold (negedge wclk, posedge addrd[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[1]);
$setuphold (negedge wclk, posedge addrd[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[2]);
$setuphold (negedge wclk, posedge addrd[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[3]);
$setuphold (negedge wclk, posedge addrd[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,addrd_dly[4]);
$setuphold (negedge wclk, posedge dia[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dia_dly[0]);
$setuphold (negedge wclk, posedge dia[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dia_dly[1]);
$setuphold (negedge wclk, posedge dib[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dib_dly[0]);
$setuphold (negedge wclk, posedge dib[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dib_dly[1]);
$setuphold (negedge wclk, posedge dic[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dic_dly[0]);
$setuphold (negedge wclk, posedge dic[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,dic_dly[1]);
$setuphold (negedge wclk, posedge did[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,did_dly[0]);
$setuphold (negedge wclk, posedge did[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,wclk_dly,did_dly[1]);
$setuphold (negedge wclk, posedge we, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,wclk_dly,we_dly);
$setuphold (posedge wclk, negedge addrd[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[0]);
$setuphold (posedge wclk, negedge addrd[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[1]);
$setuphold (posedge wclk, negedge addrd[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[2]);
$setuphold (posedge wclk, negedge addrd[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[3]);
$setuphold (posedge wclk, negedge addrd[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[4]);
$setuphold (posedge wclk, negedge dia[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dia_dly[0]);
$setuphold (posedge wclk, negedge dia[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dia_dly[1]);
$setuphold (posedge wclk, negedge dib[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dib_dly[0]);
$setuphold (posedge wclk, negedge dib[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dib_dly[1]);
$setuphold (posedge wclk, negedge dic[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dic_dly[0]);
$setuphold (posedge wclk, negedge dic[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dic_dly[1]);
$setuphold (posedge wclk, negedge did[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,did_dly[0]);
$setuphold (posedge wclk, negedge did[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,did_dly[1]);
$setuphold (posedge wclk, negedge we, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,wclk_dly,we_dly);
$setuphold (posedge wclk, posedge addrd[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[0]);
$setuphold (posedge wclk, posedge addrd[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[1]);
$setuphold (posedge wclk, posedge addrd[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[2]);
$setuphold (posedge wclk, posedge addrd[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[3]);
$setuphold (posedge wclk, posedge addrd[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,addrd_dly[4]);
$setuphold (posedge wclk, posedge dia[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dia_dly[0]);
$setuphold (posedge wclk, posedge dia[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dia_dly[1]);
$setuphold (posedge wclk, posedge dib[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dib_dly[0]);
$setuphold (posedge wclk, posedge dib[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dib_dly[1]);
$setuphold (posedge wclk, posedge dic[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dic_dly[0]);
$setuphold (posedge wclk, posedge dic[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,dic_dly[1]);
$setuphold (posedge wclk, posedge did[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,did_dly[0]);
$setuphold (posedge wclk, posedge did[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,wclk_dly,did_dly[1]);
$setuphold (posedge wclk, posedge we, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,wclk_dly,we_dly);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module srlc32e #(
`ifdef xil_timing
parameter loc = "unplaced",
`endif
parameter [31:0] init = 32'h00000000,
parameter [0:0] is_clk_inverted = 1'b0
)(
output q,
output q31,
input [4:0] a,
input ce,
input clk,
input d
);
`ifdef xil_timing
wire ce_dly;
wire clk_dly;
wire d_dly;
`endif
reg [31:0] data = init;
reg first_time = 1'b1;
initial
begin
assign data = init;
first_time <= #100000 1'b0;
`ifdef xil_timing
while ((((clk_dly !== 1'b0) && (is_clk_inverted == 1'b0)) ||
((clk_dly !== 1'b1) && (is_clk_inverted == 1'b1))) &&
(first_time == 1'b1)) #1000;
`else
while ((((clk !== 1'b0) && (is_clk_inverted == 1'b0)) ||
((clk !== 1'b1) && (is_clk_inverted == 1'b1))) &&
(first_time == 1'b1)) #1000;
`endif
deassign data;
end
`ifdef xil_timing
generate
if (is_clk_inverted == 1'b0) begin : generate_block1
always @(posedge clk_dly) begin
if (ce_dly == 1'b1 || ce_dly === 1'bz) begin data[31:0] <= {data[30:0], d_dly};
end
end
end else begin : generate_block1
always @(negedge clk_dly) begin
if (ce_dly == 1'b1 || ce_dly === 1'bz) begin data[31:0] <= {data[30:0], d_dly};
end
end
end
endgenerate
`else
generate
if (is_clk_inverted == 1'b0) begin : generate_block1
always @(posedge clk) begin
if (ce == 1'b1 || ce === 1'bz) begin data[31:0] <= {data[30:0], d};
end
end
end else begin : generate_block1
always @(negedge clk) begin
if (ce == 1'b1 || ce === 1'bz) begin data[31:0] <= {data[30:0], d};
end
end
end
endgenerate
`endif
assign q = data[a];
assign q31 = data[31];
`ifdef xil_timing
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~is_clk_inverted;
assign sh_clk_en_n = is_clk_inverted;
assign sh_ce_clk_en_p = ce && ~is_clk_inverted;
assign sh_ce_clk_en_n = ce && is_clk_inverted;
`endif
specify
(a[0] => q) = (0:0:0, 0:0:0);
(a[1] => q) = (0:0:0, 0:0:0);
(a[2] => q) = (0:0:0, 0:0:0);
(a[3] => q) = (0:0:0, 0:0:0);
(a[4] => q) = (0:0:0, 0:0:0);
(clk => q) = (100:100:100, 100:100:100);
(clk => q31) = (100:100:100, 100:100:100);
`ifdef xil_timing
$period (negedge clk, 0:0:0, notifier);
$period (posedge clk, 0:0:0, notifier);
$setuphold (negedge clk, negedge ce, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,clk_dly,ce_dly);
$setuphold (negedge clk, negedge d, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,clk_dly,d_dly);
$setuphold (negedge clk, posedge ce, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,clk_dly,ce_dly);
$setuphold (negedge clk, posedge d, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,clk_dly,d_dly);
$setuphold (posedge clk, negedge ce, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,clk_dly,ce_dly);
$setuphold (posedge clk, negedge d, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,clk_dly,d_dly);
$setuphold (posedge clk, posedge ce, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,clk_dly,ce_dly);
$setuphold (posedge clk, posedge d, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,clk_dly,d_dly);
$width (negedge clk, 0:0:0, 0, notifier);
$width (posedge clk, 0:0:0, 0, notifier);
`endif
specparam pathpulse$ = 0;
endspecify
endmodule |
module xorcy (o, ci, li);
`ifdef xil_timing
parameter loc = "unplaced";
`endif
output o;
input ci, li;
xor x1 (o, ci, li);
`ifdef xil_timing
specify
(ci => o) = (0:0:0, 0:0:0);
(li => o) = (0:0:0, 0:0:0);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module sim_uart_receiver
#(
parameter p_ext_clk = 0
)
(
input wire rx,
output reg rdy,
input wire rdy_clr,
input wire clk_50m,
input wire clken,
output reg [7:0] data,
input wire [31:0] scaler
);
initial begin
rdy = 0;
data = 8'b0;
end
parameter rx_state_start = 2'b00;
parameter rx_state_data = 2'b01;
parameter rx_state_stop = 2'b10;
reg [1:0] state = rx_state_start;
reg [31:0] sample = 0;
wire [31:0] sample_max = (scaler << 1) - 1;
wire [31:0] sample_mid = scaler;
reg [3:0] bitpos = 0;
reg [7:0] scratch = 8'b0;
initial begin
end
always @(posedge clk_50m) begin
if (rdy_clr)
rdy <= 0;
if (clken) begin
case (state)
rx_state_start: begin
if (!rx || sample != 0)
sample <= sample + 4'b1;
if (sample == sample_max) begin
state <= rx_state_data;
bitpos <= 0;
sample <= 0;
scratch <= 0;
end
end
rx_state_data: begin
if (sample == sample_max) begin
sample <= 0;
end else begin
sample <= sample + 1;
end
if (sample == sample_mid) begin
scratch[bitpos[2:0]] <= rx;
bitpos <= bitpos + 4'b1;
end
if (bitpos == 8 && sample == sample_max)
state <= rx_state_stop;
end
rx_state_stop: begin
if (sample == sample_max || (sample >= sample_mid && !rx)) begin
state <= rx_state_start;
data <= scratch;
rdy <= 1'b1;
sample <= 0;
end else begin
sample <= sample + 4'b1;
end
end
default: begin
state <= rx_state_start;
end
endcase
end
end
endmodule |
module sirv_pwmgpioport(
input clock,
input reset,
input io_pwm_port_0,
input io_pwm_port_1,
input io_pwm_port_2,
input io_pwm_port_3,
input io_pins_pwm_0_i_ival,
output io_pins_pwm_0_o_oval,
output io_pins_pwm_0_o_oe,
output io_pins_pwm_0_o_ie,
output io_pins_pwm_0_o_pue,
output io_pins_pwm_0_o_ds,
input io_pins_pwm_1_i_ival,
output io_pins_pwm_1_o_oval,
output io_pins_pwm_1_o_oe,
output io_pins_pwm_1_o_ie,
output io_pins_pwm_1_o_pue,
output io_pins_pwm_1_o_ds,
input io_pins_pwm_2_i_ival,
output io_pins_pwm_2_o_oval,
output io_pins_pwm_2_o_oe,
output io_pins_pwm_2_o_ie,
output io_pins_pwm_2_o_pue,
output io_pins_pwm_2_o_ds,
input io_pins_pwm_3_i_ival,
output io_pins_pwm_3_o_oval,
output io_pins_pwm_3_o_oe,
output io_pins_pwm_3_o_ie,
output io_pins_pwm_3_o_pue,
output io_pins_pwm_3_o_ds
);
wire [1:0] t_108;
wire [1:0] t_109;
wire [3:0] t_110;
wire t_114;
wire t_115;
wire t_116;
wire t_117;
assign io_pins_pwm_0_o_oval = t_114;
assign io_pins_pwm_0_o_oe = 1'h1;
assign io_pins_pwm_0_o_ie = 1'h0;
assign io_pins_pwm_0_o_pue = 1'h0;
assign io_pins_pwm_0_o_ds = 1'h0;
assign io_pins_pwm_1_o_oval = t_115;
assign io_pins_pwm_1_o_oe = 1'h1;
assign io_pins_pwm_1_o_ie = 1'h0;
assign io_pins_pwm_1_o_pue = 1'h0;
assign io_pins_pwm_1_o_ds = 1'h0;
assign io_pins_pwm_2_o_oval = t_116;
assign io_pins_pwm_2_o_oe = 1'h1;
assign io_pins_pwm_2_o_ie = 1'h0;
assign io_pins_pwm_2_o_pue = 1'h0;
assign io_pins_pwm_2_o_ds = 1'h0;
assign io_pins_pwm_3_o_oval = t_117;
assign io_pins_pwm_3_o_oe = 1'h1;
assign io_pins_pwm_3_o_ie = 1'h0;
assign io_pins_pwm_3_o_pue = 1'h0;
assign io_pins_pwm_3_o_ds = 1'h0;
assign t_108 = {io_pwm_port_1,io_pwm_port_0};
assign t_109 = {io_pwm_port_3,io_pwm_port_2};
assign t_110 = {t_109,t_108};
assign t_114 = t_110[0];
assign t_115 = t_110[1];
assign t_116 = t_110[2];
assign t_117 = t_110[3];
endmodule |
module _t_146_ext(
input w0_clk,
input [5:0] w0_addr,
input w0_en,
input [87:0] w0_data,
input [3:0] w0_mask,
input r0_clk,
input [5:0] r0_addr,
input r0_en,
output [87:0] r0_data
);
reg [5:0] reg_r0_addr;
reg [87:0] ram [63:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {3 {$random}};
reg_r0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge r0_clk)
if (r0_en) reg_r0_addr <= r0_addr;
always @(posedge w0_clk)
if (w0_en) begin
if (w0_mask[0]) ram[w0_addr][21:0] <= w0_data[21:0];
if (w0_mask[1]) ram[w0_addr][43:22] <= w0_data[43:22];
if (w0_mask[2]) ram[w0_addr][65:44] <= w0_data[65:44];
if (w0_mask[3]) ram[w0_addr][87:66] <= w0_data[87:66];
end
assign r0_data = ram[reg_r0_addr];
endmodule |
module _t_80_ext(
input w0_clk,
input [8:0] w0_addr,
input w0_en,
input [63:0] w0_data,
input [0:0] w0_mask,
input r0_clk,
input [8:0] r0_addr,
input r0_en,
output [63:0] r0_data
);
reg [8:0] reg_r0_addr;
reg [63:0] ram [511:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_r0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge r0_clk)
if (r0_en) reg_r0_addr <= r0_addr;
always @(posedge w0_clk)
if (w0_en) begin
if (w0_mask[0]) ram[w0_addr][63:0] <= w0_data[63:0];
end
assign r0_data = ram[reg_r0_addr];
endmodule |
module tag_array_ext(
input rw0_clk,
input [5:0] rw0_addr,
input rw0_en,
input rw0_wmode,
input [3:0] rw0_wmask,
input [79:0] rw0_wdata,
output [79:0] rw0_rdata
);
reg [5:0] reg_rw0_addr;
reg [79:0] ram [63:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {3 {$random}};
reg_rw0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge rw0_clk)
if (rw0_en && !rw0_wmode) reg_rw0_addr <= rw0_addr;
always @(posedge rw0_clk)
if (rw0_en && rw0_wmode) begin
if (rw0_wmask[0]) ram[rw0_addr][19:0] <= rw0_wdata[19:0];
if (rw0_wmask[1]) ram[rw0_addr][39:20] <= rw0_wdata[39:20];
if (rw0_wmask[2]) ram[rw0_addr][59:40] <= rw0_wdata[59:40];
if (rw0_wmask[3]) ram[rw0_addr][79:60] <= rw0_wdata[79:60];
end
assign rw0_rdata = ram[reg_rw0_addr];
endmodule |
module _t_850_ext(
input rw0_clk,
input [8:0] rw0_addr,
input rw0_en,
input rw0_wmode,
input [63:0] rw0_wdata,
output [63:0] rw0_rdata
);
reg [8:0] reg_rw0_addr;
reg [63:0] ram [511:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_rw0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge rw0_clk)
if (rw0_en && !rw0_wmode) reg_rw0_addr <= rw0_addr;
always @(posedge rw0_clk)
if (rw0_en && rw0_wmode) begin
ram[rw0_addr][63:0] <= rw0_wdata[63:0];
end
assign rw0_rdata = ram[reg_rw0_addr];
endmodule |
module mem_ext(
input w0_clk,
input [24:0] w0_addr,
input w0_en,
input [63:0] w0_data,
input [7:0] w0_mask,
input r0_clk,
input [24:0] r0_addr,
input r0_en,
output [63:0] r0_data
);
reg [24:0] reg_r0_addr;
reg [63:0] ram [33554431:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 33554432; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_r0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge r0_clk)
if (r0_en) reg_r0_addr <= r0_addr;
always @(posedge w0_clk)
if (w0_en) begin
if (w0_mask[0]) ram[w0_addr][7:0] <= w0_data[7:0];
if (w0_mask[1]) ram[w0_addr][15:8] <= w0_data[15:8];
if (w0_mask[2]) ram[w0_addr][23:16] <= w0_data[23:16];
if (w0_mask[3]) ram[w0_addr][31:24] <= w0_data[31:24];
if (w0_mask[4]) ram[w0_addr][39:32] <= w0_data[39:32];
if (w0_mask[5]) ram[w0_addr][47:40] <= w0_data[47:40];
if (w0_mask[6]) ram[w0_addr][55:48] <= w0_data[55:48];
if (w0_mask[7]) ram[w0_addr][63:56] <= w0_data[63:56];
end
assign r0_data = ram[reg_r0_addr];
endmodule |
module mem_0_ext(
input w0_clk,
input [8:0] w0_addr,
input w0_en,
input [63:0] w0_data,
input [7:0] w0_mask,
input r0_clk,
input [8:0] r0_addr,
input r0_en,
output [63:0] r0_data
);
reg [8:0] reg_r0_addr;
reg [63:0] ram [511:0];
`ifdef randomize
integer initvar;
initial begin
#0.002 begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_r0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge r0_clk)
if (r0_en) reg_r0_addr <= r0_addr;
always @(posedge w0_clk)
if (w0_en) begin
if (w0_mask[0]) ram[w0_addr][7:0] <= w0_data[7:0];
if (w0_mask[1]) ram[w0_addr][15:8] <= w0_data[15:8];
if (w0_mask[2]) ram[w0_addr][23:16] <= w0_data[23:16];
if (w0_mask[3]) ram[w0_addr][31:24] <= w0_data[31:24];
if (w0_mask[4]) ram[w0_addr][39:32] <= w0_data[39:32];
if (w0_mask[5]) ram[w0_addr][47:40] <= w0_data[47:40];
if (w0_mask[6]) ram[w0_addr][55:48] <= w0_data[55:48];
if (w0_mask[7]) ram[w0_addr][63:56] <= w0_data[63:56];
end
assign r0_data = ram[reg_r0_addr];
endmodule |
module sirv_qspi_physical_1(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] gen_2;
reg ctrl_sck_pol;
reg [31:0] gen_31;
reg ctrl_sck_pha;
reg [31:0] gen_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] gen_67;
reg ctrl_fmt_endian;
reg [31:0] gen_68;
reg ctrl_fmt_iodir;
reg [31:0] gen_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] gen_70;
reg t_119;
reg [31:0] gen_71;
reg t_120;
reg [31:0] gen_72;
reg sample_d;
reg [31:0] gen_73;
reg t_122;
reg [31:0] gen_74;
reg t_123;
reg [31:0] gen_75;
reg last_d;
reg [31:0] gen_76;
reg [7:0] scnt;
reg [31:0] gen_77;
reg [11:0] tcnt;
reg [31:0] gen_78;
wire stop;
wire beat;
wire [11:0] t_127;
wire [12:0] t_129;
wire [11:0] decr;
wire sched;
wire [11:0] t_130;
reg sck;
reg [31:0] gen_79;
reg cref;
reg [31:0] gen_80;
wire cinv;
wire [1:0] t_133;
wire [1:0] t_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] gen_81;
wire t_135;
wire t_136;
wire t_137;
wire t_138;
wire t_139;
wire t_140;
wire t_141;
wire t_142;
wire t_143;
wire [1:0] t_144;
wire [1:0] t_145;
wire [3:0] t_146;
wire [1:0] t_147;
wire [1:0] t_148;
wire [3:0] t_149;
wire [7:0] t_150;
wire [7:0] buffer_in;
wire t_151;
wire shift;
wire [6:0] t_152;
wire [6:0] t_153;
wire [6:0] t_154;
wire t_155;
wire t_157;
wire [7:0] t_158;
wire [5:0] t_159;
wire [5:0] t_160;
wire [5:0] t_161;
wire [1:0] t_162;
wire [1:0] t_163;
wire [7:0] t_164;
wire [3:0] t_165;
wire [3:0] t_166;
wire [3:0] t_167;
wire [3:0] t_169;
wire [7:0] t_170;
wire [7:0] t_172;
wire [7:0] t_174;
wire [7:0] t_176;
wire [7:0] t_178;
wire [7:0] t_179;
wire [7:0] t_180;
reg [3:0] txd;
reg [31:0] gen_82;
wire [3:0] t_182;
wire [3:0] txd_in;
wire [1:0] t_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire t_186;
wire [1:0] t_188;
wire [3:0] t_190;
wire [1:0] gen_65;
wire [1:0] t_192;
wire [3:0] gen_66;
wire [3:0] t_193;
wire [3:0] t_194;
wire [3:0] gen_0;
wire t_195;
wire t_196;
wire txen_1;
wire txen_0;
wire t_208_0;
wire t_208_1;
wire t_208_2;
wire t_208_3;
wire t_215;
wire t_216;
wire t_217;
wire t_218;
reg done;
reg [31:0] gen_83;
wire t_221;
wire t_222;
wire t_224;
wire t_225;
wire t_226;
wire t_227;
wire t_228;
wire t_229;
wire t_230;
wire [1:0] t_231;
wire [1:0] t_232;
wire [3:0] t_233;
wire [1:0] t_234;
wire [1:0] t_235;
wire [3:0] t_236;
wire [7:0] t_237;
wire [7:0] t_238;
reg xfr;
reg [31:0] gen_84;
wire gen_1;
wire t_243;
wire t_245;
wire t_246;
wire gen_3;
wire gen_4;
wire gen_5;
wire [11:0] gen_6;
wire gen_7;
wire gen_8;
wire gen_9;
wire gen_10;
wire [11:0] gen_11;
wire gen_12;
wire gen_13;
wire gen_14;
wire gen_15;
wire [11:0] gen_16;
wire t_252;
wire t_253;
wire t_254;
wire t_257;
wire gen_17;
wire gen_18;
wire gen_19;
wire gen_20;
wire gen_21;
wire gen_22;
wire gen_23;
wire t_260;
wire [1:0] gen_24;
wire gen_25;
wire gen_26;
wire t_263;
wire t_266;
wire [7:0] gen_27;
wire gen_28;
wire gen_29;
wire gen_30;
wire gen_32;
wire [11:0] gen_33;
wire gen_34;
wire gen_35;
wire gen_36;
wire [11:0] gen_37;
wire gen_38;
wire gen_39;
wire [11:0] gen_40;
wire [1:0] gen_41;
wire gen_42;
wire gen_43;
wire gen_44;
wire [7:0] gen_45;
wire gen_46;
wire gen_47;
wire gen_48;
wire [11:0] gen_49;
wire gen_50;
wire gen_51;
wire [11:0] gen_53;
wire [1:0] gen_54;
wire gen_55;
wire gen_56;
wire gen_57;
wire [7:0] gen_58;
wire gen_59;
wire gen_60;
wire gen_61;
wire [11:0] gen_62;
wire gen_63;
wire gen_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = t_215;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = t_216;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = t_217;
assign io_port_dq_2_oe = t_196;
assign io_port_dq_3_o = t_218;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = t_208_0;
assign io_port_cs_1 = t_208_1;
assign io_port_cs_2 = t_208_2;
assign io_port_cs_3 = t_208_3;
assign io_op_ready = t_260;
assign io_rx_valid = done;
assign io_rx_bits = t_238;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = gen_21;
assign sample = gen_14;
assign setup = gen_60;
assign last = gen_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign t_127 = beat ? {{4'd0}, scnt} : tcnt;
assign t_129 = t_127 - 12'h1;
assign decr = t_129[11:0];
assign sched = gen_1;
assign t_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign t_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign t_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {t_134,t_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign t_135 = io_ctrl_fmt_endian == 1'h0;
assign t_136 = io_op_bits_data[0];
assign t_137 = io_op_bits_data[1];
assign t_138 = io_op_bits_data[2];
assign t_139 = io_op_bits_data[3];
assign t_140 = io_op_bits_data[4];
assign t_141 = io_op_bits_data[5];
assign t_142 = io_op_bits_data[6];
assign t_143 = io_op_bits_data[7];
assign t_144 = {t_142,t_143};
assign t_145 = {t_140,t_141};
assign t_146 = {t_145,t_144};
assign t_147 = {t_138,t_139};
assign t_148 = {t_136,t_137};
assign t_149 = {t_148,t_147};
assign t_150 = {t_149,t_146};
assign buffer_in = t_135 ? io_op_bits_data : t_150;
assign t_151 = sample_d & stop;
assign shift = setup_d | t_151;
assign t_152 = buffer[6:0];
assign t_153 = buffer[7:1];
assign t_154 = shift ? t_152 : t_153;
assign t_155 = buffer[0];
assign t_157 = sample_d ? samples_0 : t_155;
assign t_158 = {t_154,t_157};
assign t_159 = buffer[5:0];
assign t_160 = buffer[7:2];
assign t_161 = shift ? t_159 : t_160;
assign t_162 = buffer[1:0];
assign t_163 = sample_d ? samples_1 : t_162;
assign t_164 = {t_161,t_163};
assign t_165 = buffer[3:0];
assign t_166 = buffer[7:4];
assign t_167 = shift ? t_165 : t_166;
assign t_169 = sample_d ? rxd : t_165;
assign t_170 = {t_167,t_169};
assign t_172 = proto_0 ? t_158 : 8'h0;
assign t_174 = proto_1 ? t_164 : 8'h0;
assign t_176 = proto_2 ? t_170 : 8'h0;
assign t_178 = t_172 | t_174;
assign t_179 = t_178 | t_176;
assign t_180 = t_179;
assign t_182 = buffer_in[7:4];
assign txd_in = accept ? t_182 : t_166;
assign t_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == t_184;
assign txd_sel_1 = 2'h1 == t_184;
assign txd_sel_2 = 2'h2 == t_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign t_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign t_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign t_190 = txd_sel_2 ? txd_in : 4'h0;
assign gen_65 = {{1'd0}, t_186};
assign t_192 = gen_65 | t_188;
assign gen_66 = {{2'd0}, t_192};
assign t_193 = gen_66 | t_190;
assign t_194 = t_193;
assign gen_0 = setup ? t_194 : txd;
assign t_195 = proto_1 & ctrl_fmt_iodir;
assign t_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = t_195 | t_196;
assign txen_0 = proto_0 | txen_1;
assign t_208_0 = 1'h1;
assign t_208_1 = 1'h1;
assign t_208_2 = 1'h1;
assign t_208_3 = 1'h1;
assign t_215 = txd[0];
assign t_216 = txd[1];
assign t_217 = txd[2];
assign t_218 = txd[3];
assign t_221 = done | last_d;
assign t_222 = ctrl_fmt_endian == 1'h0;
assign t_224 = buffer[1];
assign t_225 = buffer[2];
assign t_226 = buffer[3];
assign t_227 = buffer[4];
assign t_228 = buffer[5];
assign t_229 = buffer[6];
assign t_230 = buffer[7];
assign t_231 = {t_229,t_230};
assign t_232 = {t_227,t_228};
assign t_233 = {t_232,t_231};
assign t_234 = {t_225,t_226};
assign t_235 = {t_155,t_224};
assign t_236 = {t_235,t_234};
assign t_237 = {t_236,t_233};
assign t_238 = t_222 ? buffer : t_237;
assign gen_1 = stop ? 1'h1 : beat;
assign t_243 = stop == 1'h0;
assign t_245 = cref == 1'h0;
assign t_246 = cref ^ cinv;
assign gen_3 = xfr ? t_246 : sck;
assign gen_4 = xfr ? cref : 1'h0;
assign gen_5 = xfr ? t_245 : 1'h0;
assign gen_6 = t_245 ? decr : {{4'd0}, scnt};
assign gen_7 = beat ? t_245 : cref;
assign gen_8 = beat ? gen_3 : sck;
assign gen_9 = beat ? gen_4 : 1'h0;
assign gen_10 = beat ? gen_5 : 1'h0;
assign gen_11 = beat ? gen_6 : {{4'd0}, scnt};
assign gen_12 = t_243 ? gen_7 : cref;
assign gen_13 = t_243 ? gen_8 : sck;
assign gen_14 = t_243 ? gen_9 : 1'h0;
assign gen_15 = t_243 ? gen_10 : 1'h0;
assign gen_16 = t_243 ? gen_11 : {{4'd0}, scnt};
assign t_252 = scnt == 8'h1;
assign t_253 = beat & cref;
assign t_254 = t_253 & xfr;
assign t_257 = beat & t_245;
assign gen_17 = t_257 ? 1'h1 : stop;
assign gen_18 = t_257 ? 1'h0 : gen_15;
assign gen_19 = t_257 ? ctrl_sck_pol : gen_13;
assign gen_20 = t_252 ? t_254 : 1'h0;
assign gen_21 = t_252 ? gen_17 : stop;
assign gen_22 = t_252 ? gen_18 : gen_15;
assign gen_23 = t_252 ? gen_19 : gen_13;
assign t_260 = accept & done;
assign gen_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign gen_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign gen_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign t_263 = 1'h0 == io_op_bits_fn;
assign t_266 = io_op_bits_cnt == 8'h0;
assign gen_27 = t_263 ? buffer_in : t_180;
assign gen_28 = t_263 ? cinv : gen_23;
assign gen_29 = t_263 ? 1'h1 : gen_22;
assign gen_30 = t_263 ? t_266 : t_221;
assign gen_32 = io_op_bits_stb ? io_ctrl_sck_pol : gen_28;
assign gen_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign gen_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign gen_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign gen_36 = io_op_bits_fn ? gen_32 : gen_28;
assign gen_37 = io_op_bits_fn ? gen_33 : ctrl_sck_div;
assign gen_38 = io_op_bits_fn ? gen_34 : ctrl_sck_pol;
assign gen_39 = io_op_bits_fn ? gen_35 : ctrl_sck_pha;
assign gen_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : gen_16;
assign gen_41 = io_op_valid ? gen_24 : ctrl_fmt_proto;
assign gen_42 = io_op_valid ? gen_25 : ctrl_fmt_endian;
assign gen_43 = io_op_valid ? gen_26 : ctrl_fmt_iodir;
assign gen_44 = io_op_valid ? t_263 : xfr;
assign gen_45 = io_op_valid ? gen_27 : t_180;
assign gen_46 = io_op_valid ? gen_36 : gen_23;
assign gen_47 = io_op_valid ? gen_29 : gen_22;
assign gen_48 = io_op_valid ? gen_30 : t_221;
assign gen_49 = io_op_valid ? gen_37 : ctrl_sck_div;
assign gen_50 = io_op_valid ? gen_38 : ctrl_sck_pol;
assign gen_51 = io_op_valid ? gen_39 : ctrl_sck_pha;
assign gen_53 = t_260 ? gen_40 : gen_16;
assign gen_54 = t_260 ? gen_41 : ctrl_fmt_proto;
assign gen_55 = t_260 ? gen_42 : ctrl_fmt_endian;
assign gen_56 = t_260 ? gen_43 : ctrl_fmt_iodir;
assign gen_57 = t_260 ? gen_44 : xfr;
assign gen_58 = t_260 ? gen_45 : t_180;
assign gen_59 = t_260 ? gen_46 : gen_23;
assign gen_60 = t_260 ? gen_47 : gen_22;
assign gen_61 = t_260 ? gen_48 : t_221;
assign gen_62 = t_260 ? gen_49 : ctrl_sck_div;
assign gen_63 = t_260 ? gen_50 : ctrl_sck_pol;
assign gen_64 = t_260 ? gen_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (t_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (t_263) begin
sck <= cinv;
end else begin
if (t_252) begin
if (t_257) begin
sck <= ctrl_sck_pol;
end else begin
if (t_243) begin
if (beat) begin
if (xfr) begin
sck <= t_246;
end
end
end
end
end else begin
if (t_243) begin
if (beat) begin
if (xfr) begin
sck <= t_246;
end
end
end
end
end
end
end else begin
if (t_263) begin
sck <= cinv;
end else begin
if (t_252) begin
if (t_257) begin
sck <= ctrl_sck_pol;
end else begin
if (t_243) begin
if (beat) begin
if (xfr) begin
sck <= t_246;
end
end
end
end
end else begin
if (t_243) begin
if (beat) begin
if (xfr) begin
sck <= t_246;
end
end
end
end
end
end
end else begin
if (t_252) begin
if (t_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= gen_13;
end
end else begin
sck <= gen_13;
end
end
end else begin
if (t_252) begin
if (t_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= gen_13;
end
end else begin
sck <= gen_13;
end
end
if (t_260) begin
if (io_op_valid) begin
if (t_263) begin
if (t_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= t_150;
end
end else begin
buffer <= t_180;
end
end else begin
buffer <= t_180;
end
end else begin
buffer <= t_180;
end
if (t_260) begin
if (io_op_valid) begin
xfr <= t_263;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (t_243) begin
if (beat) begin
cref <= t_245;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= t_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (t_260) begin
if (io_op_valid) begin
if (t_263) begin
done <= t_266;
end else begin
done <= t_221;
end
end else begin
done <= t_221;
end
end else begin
done <= t_221;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
t_119 <= 1'h0;
end else begin
t_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_120 <= 1'h0;
end else begin
t_120 <= t_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= t_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_122 <= 1'h0;
end else begin
t_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_123 <= 1'h0;
end else begin
t_123 <= t_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= t_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= gen_53[7:0];
end
endmodule |
module clock_part1 #(parameter cc = 1,
freq = 2_000,
scan_per_sec = 25)
(
input wire clk,
input wire rst,
output wire [7:0] seven_seg,
output wire [3:0] digit_en
);
localparam dig_duration = (freq)/(4 * scan_per_sec);
reg [3:0] sec_ones, sec_tens;
reg [3:0] min_ones, min_tens;
wire nine_sec = (sec_ones == 4'd9);
wire fifty_nine_sec = (sec_tens == 4'd5) & nine_sec;
wire nine_min = (min_ones == 4'd9);
wire fifty_nine_min = (min_tens == 4'd5) & nine_min;
reg sec;
reg scan;
reg [31:0] sec_div;
reg [31:0] scan_div;
always @(posedge clk or posedge rst) begin
if(rst)
sec_div <= 32'b0;
else if(sec_div == freq)
sec_div <= 32'b0;
else
sec_div <= sec_div + 32'b1;
end
always @(posedge clk or posedge rst) begin
if(rst)
scan_div <= 32'b0;
else if(scan_div == dig_duration)
scan_div <= 32'b0;
else
scan_div <= scan_div + 32'b1;
end
always @(posedge clk or posedge rst) begin
if(rst)
sec <= 1'b0;
else if(sec_div == freq)
sec <= 1'b1;
else
sec <= 1'b0;
end
always @(posedge clk or posedge rst) begin
if(rst)
scan <= 1'b0;
else if(scan_div == dig_duration)
scan <= 1'b1;
else
scan <= 1'b0;
end
always @(posedge clk or posedge rst)
if(rst)
sec_ones <= 4'b0;
else if(sec) begin
if(!nine_sec)
sec_ones <= sec_ones + 4'd1;
else
sec_ones <= 0;
end
always @(posedge clk or posedge rst)
if(rst)
sec_tens <= 4'b0;
else if(sec) begin
if(fifty_nine_sec)
sec_tens <= 0;
else if(nine_sec)
sec_tens <= sec_tens + 4'd1;
end
always @(posedge clk or posedge rst)
if(rst)
min_ones <= 4'b0;
else if(fifty_nine_sec & sec) begin
if(!nine_min)
min_ones <= min_ones + 4'd1;
else
min_ones <= 0;
end
always @(posedge clk or posedge rst)
if(rst)
min_tens <= 4'b0;
else if(fifty_nine_sec & sec) begin
if(fifty_nine_min)
min_tens <= 0;
else if(nine_min)
min_tens <= min_tens + 4'd1;
end
reg [1:0] dig_cnt;
always @(posedge clk or posedge rst) begin
if(rst)
dig_cnt <= 2'b0;
else
if(scan) dig_cnt <= dig_cnt + 1'b1;
end
wire [3:0] bcd_mux = (dig_cnt == 2'b00) ? sec_ones :
(dig_cnt == 2'b01) ? sec_tens :
(dig_cnt == 2'b10) ? min_ones : min_tens;
reg [7:0] ca_7seg;
wire[7:0] cc_7seg = ~ ca_7seg;
always @* begin
ca_7seg = 7'b0000000;
case(bcd_mux)
4'd0 : ca_7seg = 7'b0000001;
4'd1 : ca_7seg = 7'b1001111;
4'd2 : ca_7seg = 7'b0010010;
4'd3 : ca_7seg = 7'b0000110;
4'd4 : ca_7seg = 7'b1001100;
4'd5 : ca_7seg = 7'b0100100;
4'd6 : ca_7seg = 7'b0100000;
4'd7 : ca_7seg = 7'b0001111;
4'd8 : ca_7seg = 7'b0000000;
4'd9 : ca_7seg = 7'b0000100;
endcase
end
generate
if(cc==0) begin
assign seven_seg = ca_7seg;
assign digit_en = (4'b1 << dig_cnt);
end else begin
assign seven_seg = cc_7seg;
assign digit_en = ~(4'b1 << dig_cnt);
end
endgenerate
endmodule |
module clock_part2 #(parameter cc = 1,
freq = 2_000,
scan_per_sec = 25,
wb_addr_width = 4
)
(
input wire clk,
input wire rst,
output wire [7:0] seven_seg,
output wire [3:0] digit_en,
input wire [wb_addr_width-1:0] wb_adr_i,
input wire [31:0] wb_dat_i,
output wire [31:0] wb_dat_o,
input wire [3:0] wb_sel_i,
input wire wb_cyc_i,
input wire wb_stb_i,
output reg wb_ack_o,
input wire wb_we_i,
output reg irq
);
localparam dig_duration = (freq)/(4 * scan_per_sec);
localparam [wb_addr_width-1:0] alarm_reg_off = 'h0;
localparam [wb_addr_width-1:0] time_reg_off = 'h4;
localparam [wb_addr_width-1:0] irqclr_reg_off = 'h8;
wire wb_valid = wb_cyc_i & wb_stb_i;
wire wb_we = wb_we_i & wb_valid;
wire wb_re = ~wb_we_i & wb_valid;
wire[3:0] wb_byte_sel = wb_sel_i & {4{wb_we}};
wire wb_time_reg_sel = (wb_adr_i == time_reg_off);
wire wb_alarm_reg_sel = (wb_adr_i == alarm_reg_off);
wire wb_irqclr_reg_sel = (wb_adr_i == irqclr_reg_off);
always @ (posedge clk or posedge rst)
if(rst)
wb_ack_o <= 1'b0;
else
if(wb_valid & ~wb_ack_o)
wb_ack_o <= 1'b1;
else
wb_ack_o <= 1'b0;
reg [15:0] alarm_reg;
always @(posedge clk or posedge rst)
if(rst)
alarm_reg <= 16'h0;
else if(wb_we & (wb_alarm_reg_sel))
alarm_reg <= wb_dat_i[15:0];
reg [3:0] sec_ones, sec_tens;
reg [3:0] min_ones, min_tens;
wire nine_sec = (sec_ones == 4'd9);
wire fifty_nine_sec = (sec_tens == 4'd5) & nine_sec;
wire nine_min = (min_ones == 4'd9);
wire fifty_nine_min = (min_tens == 4'd5) & nine_min;
wire [15:0] time_reg = {min_tens, min_ones, sec_tens, sec_ones};
always @(posedge clk)
if(rst) irq <= 0;
else if(wb_irqclr_reg_sel & wb_we)
irq <= 0;
else if((alarm_reg != 16'h0) && (alarm_reg == time_reg))
irq <= 1;
assign wb_dat_o = (wb_alarm_reg_sel) ? {16'h0, alarm_reg}:
(wb_time_reg_sel) ? {16'h0, time_reg} :
32'h0badbad0;
reg sec;
reg scan;
reg [31:0] sec_div;
reg [31:0] scan_div;
always @(posedge clk or posedge rst) begin
if(rst)
sec_div <= 32'b0;
else if(sec_div == freq)
sec_div <= 32'b0;
else
sec_div <= sec_div + 32'b1;
end
always @(posedge clk or posedge rst) begin
if(rst)
scan_div <= 32'b0;
else if(scan_div == dig_duration)
scan_div <= 32'b0;
else
scan_div <= scan_div + 32'b1;
end
always @(posedge clk or posedge rst) begin
if(rst)
sec <= 1'b0;
else if(sec_div == freq)
sec <= 1'b1;
else
sec <= 1'b0;
end
always @(posedge clk or posedge rst) begin
if(rst)
scan <= 1'b0;
else if(scan_div == dig_duration)
scan <= 1'b1;
else
scan <= 1'b0;
end
always @(posedge clk or posedge rst)
if(rst)
sec_ones <= 4'b0;
else if(wb_time_reg_sel & wb_we)
sec_ones <= wb_dat_i[3:0];
else if(sec) begin
if(!nine_sec)
sec_ones <= sec_ones + 4'd1;
else
sec_ones <= 0;
end
always @(posedge clk or posedge rst)
if(rst)
sec_tens <= 4'b0;
else if(wb_time_reg_sel & wb_we)
sec_tens <= wb_dat_i[7:4];
else if(sec) begin
if(fifty_nine_sec)
sec_tens <= 0;
else if(nine_sec)
sec_tens <= sec_tens + 4'd1;
end
always @(posedge clk or posedge rst)
if(rst)
min_ones <= 4'b0;
else if(wb_time_reg_sel & wb_we)
min_ones <= wb_dat_i[11:8];
else if(fifty_nine_sec & sec) begin
if(!nine_min)
min_ones <= min_ones + 4'd1;
else
min_ones <= 0;
end
always @(posedge clk or posedge rst)
if(rst)
min_tens <= 4'b0;
else if(wb_time_reg_sel & wb_we)
min_tens <= wb_dat_i[15:12];
else if(fifty_nine_sec & sec) begin
if(fifty_nine_min)
min_tens <= 0;
else if(nine_min)
min_tens <= min_tens + 4'd1;
end
reg [1:0] dig_cnt;
always @(posedge clk or posedge rst) begin
if(rst)
dig_cnt <= 2'b0;
else
if(scan) dig_cnt <= dig_cnt + 1'b1;
end
wire [3:0] bcd_mux = (dig_cnt == 2'b00) ? sec_ones :
(dig_cnt == 2'b01) ? sec_tens :
(dig_cnt == 2'b10) ? min_ones : min_tens;
reg [7:0] ca_7seg;
wire[7:0] cc_7seg = ~ ca_7seg;
always @* begin
ca_7seg = 7'b0000000;
case(bcd_mux)
4'd0 : ca_7seg = 7'b0000001;
4'd1 : ca_7seg = 7'b1001111;
4'd2 : ca_7seg = 7'b0010010;
4'd3 : ca_7seg = 7'b0000110;
4'd4 : ca_7seg = 7'b1001100;
4'd5 : ca_7seg = 7'b0100100;
4'd6 : ca_7seg = 7'b0100000;
4'd7 : ca_7seg = 7'b0001111;
4'd8 : ca_7seg = 7'b0000000;
4'd9 : ca_7seg = 7'b0000100;
endcase
end
generate
if(cc==0) begin
assign seven_seg = ca_7seg;
assign digit_en = (4'b1 << dig_cnt);
end else begin
assign seven_seg = cc_7seg;
assign digit_en = ~(4'b1 << dig_cnt);
end
endgenerate
endmodule |
module user_project_wrapper (
`ifdef use_power_pins
inout vdda1, inout vdda2, inout vssa1, inout vssa2, inout vccd1, inout vccd2, inout vssd1, inout vssd2, `endif
input wire wb_clk_i,
input wire wb_rst_i,
input wire wbs_stb_i,
input wire wbs_cyc_i,
input wire wbs_we_i,
input wire [3:0] wbs_sel_i,
input wire [31:0] wbs_dat_i,
input wire [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg [31:0] wbs_dat_o,
input wire [127:0] la_data_in,
output wire [127:0] la_data_out,
input wire [127:0] la_oenb,
input wire [`mprj_io_pads-1:0] io_in,
output wire [`mprj_io_pads-1:0] io_out,
output wire [`mprj_io_pads-1:0] io_oeb,
inout wire [`mprj_io_pads-10:0] analog_io,
input wire user_clock2,
output reg [2:0] user_irq
);
assign io_out[0] = io_in[0];
endmodule |
module bufiodqs (o, dqsmask, i);
parameter dqsmask_enable = "false";
output o;
input dqsmask;
input i;
reg delay_bypass_attr;
reg dqsmask_enable_attr;
wire o_out;
reg attr_err_flag = 0;
buf buf_o(o, o_out);
initial begin
case (dqsmask_enable)
"true" : dqsmask_enable_attr <= 1'b1;
"false" :dqsmask_enable_attr <= 1'b0;
default : begin
$display("attribute syntax error : the attribute dqsmask_enable on bufiodqs instance %m is set to %s. legal values for this attribute are true or false", dqsmask_enable);
attr_err_flag = 1;
end
endcase
if (attr_err_flag)
begin
#1;
$finish;
end
end
reg q1, q2;
wire clk, dglitch_en;
assign clk = (dglitch_en == 1'b1) ? i : 1'b0;
always @(dqsmask or clk) begin
if (dqsmask == 1'b1) q1 = 0;
else #(300) if (clk == 1) q1 = 1;
end
always @(dqsmask or clk) begin
if (dqsmask == 1'b1) q2 = 0;
else #(400) if (clk == 0) q2 = q1;
end
assign dglitch_en = (~q2 | dqsmask);
assign o_out = (dqsmask_enable == "true") ? clk : i;
endmodule |
module subservient_debug_switch
( input wire i_debug_mode,
input wire [31:0] i_wb_dbg_adr,
input wire [31:0] i_wb_dbg_dat,
input wire [3:0] i_wb_dbg_sel,
input wire i_wb_dbg_we,
input wire i_wb_dbg_stb,
output wire [31:0] o_wb_dbg_rdt,
output wire o_wb_dbg_ack,
input wire [31:0] i_wb_dbus_adr,
input wire [31:0] i_wb_dbus_dat,
input wire [3:0] i_wb_dbus_sel,
input wire i_wb_dbus_we,
input wire i_wb_dbus_stb,
output wire [31:0] o_wb_dbus_rdt,
output wire o_wb_dbus_ack,
output wire [31:0] o_wb_mux_adr,
output wire [31:0] o_wb_mux_dat,
output wire [3:0] o_wb_mux_sel,
output wire o_wb_mux_we,
output wire o_wb_mux_stb,
input wire [31:0] i_wb_mux_rdt,
input wire i_wb_mux_ack);
assign o_wb_dbg_rdt = i_wb_mux_rdt;
assign o_wb_dbg_ack = i_wb_mux_ack & i_debug_mode;
assign o_wb_dbus_rdt = i_wb_mux_rdt;
assign o_wb_dbus_ack = i_wb_mux_ack & !i_debug_mode;
assign o_wb_mux_adr = i_debug_mode ? i_wb_dbg_adr : i_wb_dbus_adr;
assign o_wb_mux_dat = i_debug_mode ? i_wb_dbg_dat : i_wb_dbus_dat;
assign o_wb_mux_sel = i_debug_mode ? i_wb_dbg_sel : i_wb_dbus_sel;
assign o_wb_mux_we = i_debug_mode ? i_wb_dbg_we : i_wb_dbus_we ;
assign o_wb_mux_stb = i_debug_mode ? i_wb_dbg_stb : i_wb_dbus_stb;
endmodule |
module subservient_generic_ram
#(parameter depth = 0,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wire i_clk,
input wire i_rst,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata,
input wire i_ren);
reg [7:0] mem [0:depth-1] ;
always @(posedge i_clk) begin
if (i_wen) mem[i_waddr] <= i_wdata;
o_rdata <= mem[i_raddr];
end
initial
if(|memfile) begin
$display("preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
endmodule |
module subservient_gpio
(input wire i_wb_clk,
input wire i_wb_rst,
input wire i_wb_dat,
input wire i_wb_we,
input wire i_wb_stb,
output reg o_wb_rdt,
output reg o_wb_ack,
output reg o_gpio);
always @(posedge i_wb_clk) begin
o_wb_rdt <= o_gpio;
if (i_wb_stb & i_wb_we)
o_gpio <= i_wb_dat;
o_wb_ack <= i_wb_stb & !o_wb_ack;
if (i_wb_rst) begin
o_wb_ack <= 1'b0;
o_gpio <= 1'b0;
end
end
endmodule |
module sirv_spigpioport(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_spi_cs_1,
input io_spi_cs_2,
input io_spi_cs_3,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds,
input io_pins_cs_1_i_ival,
output io_pins_cs_1_o_oval,
output io_pins_cs_1_o_oe,
output io_pins_cs_1_o_ie,
output io_pins_cs_1_o_pue,
output io_pins_cs_1_o_ds,
input io_pins_cs_2_i_ival,
output io_pins_cs_2_o_oval,
output io_pins_cs_2_o_oe,
output io_pins_cs_2_o_ie,
output io_pins_cs_2_o_pue,
output io_pins_cs_2_o_ds,
input io_pins_cs_3_i_ival,
output io_pins_cs_3_o_oval,
output io_pins_cs_3_o_oe,
output io_pins_cs_3_o_ie,
output io_pins_cs_3_o_pue,
output io_pins_cs_3_o_ds
);
wire t_312;
wire t_315;
wire t_318;
wire t_321;
wire [1:0] t_324;
wire [1:0] t_325;
wire [3:0] t_326;
wire t_330;
wire t_331;
wire t_332;
wire t_333;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = t_312;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = t_315;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = t_318;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = t_321;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = t_330;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign io_pins_cs_1_o_oval = t_331;
assign io_pins_cs_1_o_oe = 1'h1;
assign io_pins_cs_1_o_ie = 1'h0;
assign io_pins_cs_1_o_pue = 1'h0;
assign io_pins_cs_1_o_ds = 1'h0;
assign io_pins_cs_2_o_oval = t_332;
assign io_pins_cs_2_o_oe = 1'h1;
assign io_pins_cs_2_o_ie = 1'h0;
assign io_pins_cs_2_o_pue = 1'h0;
assign io_pins_cs_2_o_ds = 1'h0;
assign io_pins_cs_3_o_oval = t_333;
assign io_pins_cs_3_o_oe = 1'h1;
assign io_pins_cs_3_o_ie = 1'h0;
assign io_pins_cs_3_o_pue = 1'h0;
assign io_pins_cs_3_o_ds = 1'h0;
assign t_312 = ~ io_spi_dq_0_oe;
assign t_315 = ~ io_spi_dq_1_oe;
assign t_318 = ~ io_spi_dq_2_oe;
assign t_321 = ~ io_spi_dq_3_oe;
assign t_324 = {io_spi_cs_1,io_spi_cs_0};
assign t_325 = {io_spi_cs_3,io_spi_cs_2};
assign t_326 = {t_325,t_324};
assign t_330 = t_326[0];
assign t_331 = t_326[1];
assign t_332 = t_326[2];
assign t_333 = t_326[3];
endmodule |
module subservient_ram
#( parameter depth = 256,
parameter aw = $clog2(depth))
(input wire i_clk,
input wire i_rst,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output wire [7:0] o_rdata,
input wire i_ren,
output wire [aw-1:0] o_sram_waddr,
output wire [7:0] o_sram_wdata,
output wire o_sram_wen,
output wire [aw-1:0] o_sram_raddr,
input wire [7:0] i_sram_rdata,
output wire o_sram_ren,
input wire [aw-1:2] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_stb,
output wire [31:0] o_wb_rdt,
output reg o_wb_ack);
reg [aw-1:0] rf_waddr_r;
reg [7:0] rf_wdata_r;
reg rf_wen_r;
reg [1:0] bsel;
wire wb_en = i_wb_stb & !rf_wen_r & !o_wb_ack;
wire wb_we = i_wb_we & i_wb_sel[bsel];
assign o_sram_waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : rf_waddr_r;
assign o_sram_wdata = wb_en ? i_wb_dat[bsel*8+:8] : rf_wdata_r;
assign o_sram_wen = wb_en ? wb_we : rf_wen_r;
assign o_sram_raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr;
assign o_sram_ren = wb_en ? !i_wb_we : i_ren;
reg [23:0] wb_rdt;
assign o_wb_rdt = {i_sram_rdata, wb_rdt};
reg regzero;
always @(posedge i_clk) begin
rf_waddr_r <= i_waddr;
rf_wdata_r <= i_wdata;
rf_wen_r <= i_wen;
if (wb_en) bsel <= bsel + 2'd1;
o_wb_ack <= wb_en & &bsel;
if (bsel == 2'b01) wb_rdt[7:0] <= i_sram_rdata;
if (bsel == 2'b10) wb_rdt[15:8] <= i_sram_rdata;
if (bsel == 2'b11) wb_rdt[23:16] <= i_sram_rdata;
if (i_rst) begin
bsel <= 2'd0;
o_wb_ack <= 1'b0;
end
regzero <= &i_raddr[aw-1:2];
end
assign o_rdata = regzero ? 8'd0 : i_sram_rdata;
endmodule |
module subservient_rf_ram_if
#(parameter width=8,
parameter reset_strategy="mini",
parameter csr_regs=4,
parameter depth=32*(32+csr_regs)/width,
parameter l2w = $clog2(width))
(
input wire i_clk,
input wire i_rst,
input wire i_wreq,
input wire i_rreq,
output wire o_ready,
input wire [$clog2(32+csr_regs)-1:0] i_wreg0,
input wire [$clog2(32+csr_regs)-1:0] i_wreg1,
input wire i_wen0,
input wire i_wen1,
input wire i_wdata0,
input wire i_wdata1,
input wire [$clog2(32+csr_regs)-1:0] i_rreg0,
input wire [$clog2(32+csr_regs)-1:0] i_rreg1,
output wire o_rdata0,
output wire o_rdata1,
output wire [$clog2(depth)-1:0] o_waddr,
output wire [width-1:0] o_wdata,
output wire o_wen,
output wire [$clog2(depth)-1:0] o_raddr,
input wire [width-1:0] i_rdata,
output wire o_ren);
reg rgnt;
assign o_ready = rgnt | i_wreq;
reg [4:0] rcnt;
wire [4:0] wcnt;
reg [width-2:0] wdata0_r;
reg [width-1:0] wdata1_r;
reg wen0_r;
reg wen1_r;
wire wtrig0;
wire wtrig1;
generate if (width == 2) begin
assign wtrig0 = ~wcnt[0];
assign wtrig1 = wcnt[0];
end else begin
reg wtrig0_r;
always @(posedge i_clk) wtrig0_r <= wtrig0;
assign wtrig0 = (wcnt[l2w-1:0] == {{l2w-1{1'b1}},1'b0});
assign wtrig1 = wtrig0_r;
end
endgenerate
assign o_wdata = wtrig1 ?
wdata1_r :
{i_wdata0, wdata0_r};
wire [$clog2(32+csr_regs)-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0;
generate if (width == 32)
assign o_waddr = wreg;
else
assign o_waddr = {wreg, wcnt[4:l2w]};
endgenerate
assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r);
generate if (width > 2)
always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]};
else
always @(posedge i_clk) wdata0_r <= i_wdata0;
endgenerate
assign wcnt = rcnt-3;
always @(posedge i_clk) begin
wen0_r <= i_wen0;
wen1_r <= i_wen1;
wdata1_r <= {i_wdata1,wdata1_r[width-1:1]};
end
wire rtrig0;
reg rtrig1;
wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
generate if (width == 32)
assign o_raddr = rreg;
else
assign o_raddr = {rreg, rcnt[4:l2w]};
endgenerate
reg [width-1:0] rdata0;
reg [width-2:0] rdata1;
reg rgate;
reg rvalid;
assign o_rdata0 = rvalid & rdata0[0];
assign o_rdata1 = rvalid & (rtrig1 ? i_rdata[0] : rdata1[0]);
assign rtrig0 = (rcnt[l2w-1:0] == 1);
assign o_ren = rgate & ((rcnt[l2w-1:0] == 0) | rtrig0);
reg rreq_r;
generate if (width>2)
always @(posedge i_clk) begin
rdata1 <= {1'b0,rdata1[width-2:1]}; if (rtrig1)
rdata1[width-2:0] <= i_rdata[width-1:1];
end
else
always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
endgenerate
always @(posedge i_clk) begin
if (o_ready)
rvalid <= rgate;
if (&rcnt)
rgate <= 1'b0;
else if (i_rreq)
rgate <= 1'b1;
rtrig1 <= rtrig0;
rcnt <= rcnt+5'd1;
if (i_rreq)
rcnt <= 5'd0;
if (i_wreq)
rcnt <= 5'd2;
rreq_r <= i_rreq;
rgnt <= rreq_r;
rdata0 <= {1'b0,rdata0[width-1:1]};
if (rtrig0)
rdata0 <= i_rdata;
if (i_rst) begin
if (reset_strategy != "none") begin
rgate <= 1'b0;
rcnt <= 5'd2;
rgnt <= 1'b0;
rreq_r <= 1'b0;
end
end
end
endmodule |
module subservient_fpga_clock_gen
(input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst);
assign o_clk = i_clk;
always @(posedge i_clk) o_rst <= i_rst;
endmodule |
module uart_decoder
(input wire [31:0] baud_rate,
input wire rx);
integer i;
reg [7:0] ch;
real t;
initial begin
@(posedge rx);
t = 1000000000/baud_rate;
forever begin
@(negedge rx);
#(t/2) ch = 0;
for (i=0;i<8;i=i+1)
#t ch[i] = rx;
$write("%c",ch);
$fflush;
end
end
endmodule |
module ha(output c,
s,
input a,
b);
xor g0(s, a, b);
and g1(c, a, b);
endmodule |
module adder_rtl(
output c3, output[2:0] s, input[2:0] a, b, input c0 );
assign {c3, s} = a+b+c0;
endmodule |
module and4(output y, input a, b, c, d);
wire w1, w2;
and g0(w1, a, b);
and g1(w2, c, d);
and g2(y, w1, w2);
endmodule |
module or4(output y, input a, b, c, d);
wire w1, w2;
or g0(w1, a, b);
or g1(w2, c, d);
or g2(y, w1, w2);
endmodule |
module hello (
input wire in,
output reg out
);
initial begin
$display("hello world!");
out = out + in;
end
endmodule |
module rca_gl(
output c3, output[2:0] s, input[2:0] a, b, input c0 );
endmodule |
module cla_gl(
output c3, output[2:0] s, input[2:0] a, b, input c0 );
endmodule |
module sirv_spigpioport_1(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire t_267;
wire t_270;
wire t_273;
wire t_276;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = t_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = t_270;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = t_273;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = t_276;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign t_267 = ~ io_spi_dq_0_oe;
assign t_270 = ~ io_spi_dq_1_oe;
assign t_273 = ~ io_spi_dq_2_oe;
assign t_276 = ~ io_spi_dq_3_oe;
endmodule |
module mult_fast(output reg[7:0] p, input[3:0] a,
b,
input clk);
reg[3:0] a_s0, b_s0;
always @(posedge clk) begin
a_s0 <= a;
b_s0 <= b;
end
wire[3:0] pp0 = a_s0 & {4{b_s0[0]}}; wire[4:1] pp1 = a_s0 & {4{b_s0[1]}}; wire[5:2] pp2 = a_s0 & {4{b_s0[2]}}; wire[6:3] pp3 = a_s0 & {4{b_s0[3]}}; reg[5:1] sum1;
always @(pp0, pp1) begin
sum1[5:1] <= #7 pp0[3:1] + pp1[4:1]; end
reg[7:3] sum3;
always @(pp2, pp3) begin
sum3[7:3] <= #7 pp2[5:3] + pp3[6:3]; end reg[5:0] sum1_s1;
reg[7:2] sum3_s1;
always @(posedge clk) begin
sum1_s1 <= {sum1, pp0[0]};
sum3_s1 <= {sum3, pp2[2]};
end
reg[7:2] sum2;
always @(sum1_s1, sum3_s1) begin
sum2[7:2] <= #8 sum1_s1[5:2] + sum3_s1[7:2]; end always @(posedge clk) begin
p <= {sum2, sum1_s1[1:0]};
end endmodule |
module sirv_spigpioport_2(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire t_267;
reg t_271;
reg [31:0] gen_0;
reg t_272;
reg [31:0] gen_1;
reg t_273;
reg [31:0] gen_2;
wire t_274;
reg t_278;
reg [31:0] gen_3;
reg t_279;
reg [31:0] gen_4;
reg t_280;
reg [31:0] gen_5;
wire t_281;
reg t_285;
reg [31:0] gen_6;
reg t_286;
reg [31:0] gen_7;
reg t_287;
reg [31:0] gen_8;
wire t_288;
reg t_292;
reg [31:0] gen_9;
reg t_293;
reg [31:0] gen_10;
reg t_294;
reg [31:0] gen_11;
assign io_spi_dq_0_i = t_273;
assign io_spi_dq_1_i = t_280;
assign io_spi_dq_2_i = t_287;
assign io_spi_dq_3_i = t_294;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h1;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = t_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h1;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = t_274;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h1;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = t_281;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h1;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = t_288;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h1;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h1;
assign t_267 = ~ io_spi_dq_0_oe;
assign t_274 = ~ io_spi_dq_1_oe;
assign t_281 = ~ io_spi_dq_2_oe;
assign t_288 = ~ io_spi_dq_3_oe;
always @(posedge clock or posedge reset) begin
if(reset) begin
t_271 <= 1'b0;
t_272 <= 1'b0;
t_273 <= 1'b0;
t_278 <= 1'b0;
t_279 <= 1'b0;
t_280 <= 1'b0;
t_285 <= 1'b0;
t_286 <= 1'b0;
t_287 <= 1'b0;
t_292 <= 1'b0;
t_293 <= 1'b0;
t_294 <= 1'b0;
end
else begin
t_271 <= io_pins_dq_0_i_ival;
t_272 <= t_271;
t_273 <= t_272;
t_278 <= io_pins_dq_1_i_ival;
t_279 <= t_278;
t_280 <= t_279;
t_285 <= io_pins_dq_2_i_ival;
t_286 <= t_285;
t_287 <= t_286;
t_292 <= io_pins_dq_3_i_ival;
t_293 <= t_292;
t_294 <= t_293;
end
end
endmodule |
module sirv_uartgpioport(
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd,
input io_pins_rxd_i_ival,
output io_pins_rxd_o_oval,
output io_pins_rxd_o_oe,
output io_pins_rxd_o_ie,
output io_pins_rxd_o_pue,
output io_pins_rxd_o_ds,
input io_pins_txd_i_ival,
output io_pins_txd_o_oval,
output io_pins_txd_o_oe,
output io_pins_txd_o_ie,
output io_pins_txd_o_pue,
output io_pins_txd_o_ds
);
assign io_uart_rxd = io_pins_rxd_i_ival;
assign io_pins_rxd_o_oval = 1'h0;
assign io_pins_rxd_o_oe = 1'h0;
assign io_pins_rxd_o_ie = 1'h1;
assign io_pins_rxd_o_pue = 1'h0;
assign io_pins_rxd_o_ds = 1'h0;
assign io_pins_txd_o_oval = io_uart_txd;
assign io_pins_txd_o_oe = 1'h1;
assign io_pins_txd_o_ie = 1'h0;
assign io_pins_txd_o_pue = 1'h0;
assign io_pins_txd_o_ds = 1'h0;
endmodule |
module sirv_uartrx(
input clock,
input reset,
input io_en,
input io_in,
output io_out_valid,
output [7:0] io_out_bits,
input [15:0] io_div
);
reg [1:0] debounce;
reg [31:0] gen_7;
wire debounce_max;
wire debounce_min;
reg [11:0] prescaler;
reg [31:0] gen_20;
wire start;
wire busy;
wire t_21;
wire pulse;
wire [12:0] t_23;
wire [11:0] t_24;
wire [11:0] gen_0;
wire t_25;
wire [11:0] t_26;
wire [11:0] gen_1;
reg [2:0] sample;
reg [31:0] gen_23;
wire t_28;
wire t_29;
wire t_30;
wire t_31;
wire t_32;
wire t_33;
wire t_34;
wire t_35;
wire [3:0] t_36;
wire [3:0] gen_2;
reg [4:0] timer;
reg [31:0] gen_28;
reg [3:0] counter;
reg [31:0] gen_43;
reg [7:0] shifter;
reg [31:0] gen_44;
wire t_41;
wire expire;
wire sched;
wire [5:0] t_44;
wire [4:0] t_45;
wire [4:0] gen_3;
wire [4:0] gen_4;
reg valid;
reg [31:0] gen_45;
reg [1:0] state;
reg [31:0] gen_46;
wire t_50;
wire t_52;
wire t_54;
wire t_56;
wire t_57;
wire [2:0] t_59;
wire [1:0] t_60;
wire [1:0] gen_5;
wire [2:0] t_64;
wire [1:0] t_65;
wire [1:0] gen_6;
wire [4:0] gen_8;
wire [1:0] gen_9;
wire [1:0] gen_10;
wire gen_11;
wire [4:0] gen_12;
wire [1:0] gen_13;
wire [1:0] gen_14;
wire gen_15;
wire [4:0] gen_16;
wire t_68;
wire [1:0] gen_17;
wire t_72;
wire [1:0] gen_18;
wire [3:0] gen_19;
wire [1:0] gen_21;
wire [3:0] gen_22;
wire gen_24;
wire [1:0] gen_25;
wire [3:0] gen_26;
wire t_74;
wire [4:0] t_77;
wire [3:0] t_78;
wire t_80;
wire [1:0] gen_27;
wire t_83;
wire [6:0] t_84;
wire [7:0] t_85;
wire [7:0] gen_29;
wire gen_30;
wire [3:0] gen_31;
wire [1:0] gen_32;
wire gen_33;
wire [7:0] gen_34;
wire gen_35;
wire gen_36;
wire [3:0] gen_37;
wire [1:0] gen_38;
wire gen_39;
wire [7:0] gen_40;
wire gen_41;
wire t_88;
wire [1:0] gen_42;
assign io_out_valid = valid;
assign io_out_bits = shifter;
assign debounce_max = debounce == 2'h3;
assign debounce_min = debounce == 2'h0;
assign start = gen_15;
assign busy = gen_36;
assign t_21 = prescaler == 12'h0;
assign pulse = t_21 & busy;
assign t_23 = prescaler - 12'h1;
assign t_24 = t_23[11:0];
assign gen_0 = busy ? t_24 : prescaler;
assign t_25 = start | pulse;
assign t_26 = io_div[15:4];
assign gen_1 = t_25 ? t_26 : gen_0;
assign t_28 = sample[0];
assign t_29 = sample[1];
assign t_30 = sample[2];
assign t_31 = t_28 & t_29;
assign t_32 = t_28 & t_30;
assign t_33 = t_31 | t_32;
assign t_34 = t_29 & t_30;
assign t_35 = t_33 | t_34;
assign t_36 = {sample,io_in};
assign gen_2 = pulse ? t_36 : {{1'd0}, sample};
assign t_41 = timer == 5'h0;
assign expire = t_41 & pulse;
assign sched = gen_41;
assign t_44 = timer - 5'h1;
assign t_45 = t_44[4:0];
assign gen_3 = pulse ? t_45 : timer;
assign gen_4 = sched ? 5'hf : gen_3;
assign t_50 = 2'h0 == state;
assign t_52 = io_in == 1'h0;
assign t_54 = t_52 == 1'h0;
assign t_56 = debounce_min == 1'h0;
assign t_57 = t_54 & t_56;
assign t_59 = debounce - 2'h1;
assign t_60 = t_59[1:0];
assign gen_5 = t_57 ? t_60 : debounce;
assign t_64 = debounce + 2'h1;
assign t_65 = t_64[1:0];
assign gen_6 = debounce_max ? 2'h1 : state;
assign gen_8 = debounce_max ? 5'h8 : gen_4;
assign gen_9 = t_52 ? t_65 : gen_5;
assign gen_10 = t_52 ? gen_6 : state;
assign gen_11 = t_52 ? debounce_max : 1'h0;
assign gen_12 = t_52 ? gen_8 : gen_4;
assign gen_13 = t_50 ? gen_9 : debounce;
assign gen_14 = t_50 ? gen_10 : state;
assign gen_15 = t_50 ? gen_11 : 1'h0;
assign gen_16 = t_50 ? gen_12 : gen_4;
assign t_68 = 2'h1 == state;
assign gen_17 = t_35 ? 2'h0 : gen_14;
assign t_72 = t_35 == 1'h0;
assign gen_18 = t_72 ? 2'h2 : gen_17;
assign gen_19 = t_72 ? 4'h8 : counter;
assign gen_21 = expire ? gen_18 : gen_14;
assign gen_22 = expire ? gen_19 : counter;
assign gen_24 = t_68 ? expire : 1'h0;
assign gen_25 = t_68 ? gen_21 : gen_14;
assign gen_26 = t_68 ? gen_22 : counter;
assign t_74 = 2'h2 == state;
assign t_77 = counter - 4'h1;
assign t_78 = t_77[3:0];
assign t_80 = counter == 4'h0;
assign gen_27 = t_80 ? 2'h0 : gen_25;
assign t_83 = t_80 == 1'h0;
assign t_84 = shifter[7:1];
assign t_85 = {t_35,t_84};
assign gen_29 = t_83 ? t_85 : shifter;
assign gen_30 = t_83 ? 1'h1 : gen_24;
assign gen_31 = expire ? t_78 : gen_26;
assign gen_32 = expire ? gen_27 : gen_25;
assign gen_33 = expire ? t_80 : 1'h0;
assign gen_34 = expire ? gen_29 : shifter;
assign gen_35 = expire ? gen_30 : gen_24;
assign gen_36 = t_74 ? 1'h1 : t_68;
assign gen_37 = t_74 ? gen_31 : gen_26;
assign gen_38 = t_74 ? gen_32 : gen_25;
assign gen_39 = t_74 ? gen_33 : 1'h0;
assign gen_40 = t_74 ? gen_34 : shifter;
assign gen_41 = t_74 ? gen_35 : gen_24;
assign t_88 = io_en == 1'h0;
assign gen_42 = t_88 ? 2'h0 : gen_13;
always @(posedge clock or posedge reset)
if (reset) begin
debounce <= 2'h0;
end else begin
if (t_88) begin
debounce <= 2'h0;
end else begin
if (t_50) begin
if (t_52) begin
debounce <= t_65;
end else begin
if (t_57) begin
debounce <= t_60;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 12'h0;
end else begin
if (t_25) begin
prescaler <= t_26;
end else begin
if (busy) begin
prescaler <= t_24;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sample <= 3'b0;
timer <= 5'h0;
counter <= 4'b0;
shifter <= 8'b0;
end
else begin
sample <= gen_2[2:0];
if (t_50) begin
if (t_52) begin
if (debounce_max) begin
timer <= 5'h8;
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= t_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= t_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= t_45;
end
end
end
if (t_74) begin
if (expire) begin
counter <= t_78;
end else begin
if (t_68) begin
if (expire) begin
if (t_72) begin
counter <= 4'h8;
end
end
end
end
end else begin
if (t_68) begin
if (expire) begin
if (t_72) begin
counter <= 4'h8;
end
end
end
end
if (t_74) begin
if (expire) begin
if (t_83) begin
shifter <= t_85;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
valid <= 1'h0;
end else begin
if (t_74) begin
if (expire) begin
valid <= t_80;
end else begin
valid <= 1'h0;
end
end else begin
valid <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (t_74) begin
if (expire) begin
if (t_80) begin
state <= 2'h0;
end else begin
if (t_68) begin
if (expire) begin
if (t_72) begin
state <= 2'h2;
end else begin
if (t_35) begin
state <= 2'h0;
end else begin
if (t_50) begin
if (t_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (t_50) begin
if (t_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end else begin
if (t_50) begin
if (t_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (t_68) begin
if (expire) begin
if (t_72) begin
state <= 2'h2;
end else begin
if (t_35) begin
state <= 2'h0;
end else begin
if (t_50) begin
if (t_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
state <= gen_14;
end
end else begin
state <= gen_14;
end
end
end else begin
if (t_68) begin
if (expire) begin
if (t_72) begin
state <= 2'h2;
end else begin
if (t_35) begin
state <= 2'h0;
end else begin
state <= gen_14;
end
end
end else begin
state <= gen_14;
end
end else begin
state <= gen_14;
end
end
end
endmodule |
module sirv_uarttx(
input clock,
input reset,
input io_en,
output io_in_ready,
input io_in_valid,
input [7:0] io_in_bits,
output io_out,
input [15:0] io_div,
input io_nstop
);
reg [15:0] prescaler;
reg [31:0] gen_6;
wire pulse;
reg [3:0] counter;
reg [31:0] gen_7;
reg [8:0] shifter;
reg [31:0] gen_8;
reg out;
reg [31:0] gen_9;
wire busy;
wire t_32;
wire t_33;
wire t_34;
wire t_36;
wire [8:0] t_38;
wire t_40;
wire [3:0] t_46;
wire [3:0] t_48;
wire [3:0] t_50;
wire [3:0] t_51;
wire [8:0] gen_0;
wire [3:0] gen_1;
wire [16:0] t_53;
wire [15:0] t_54;
wire [15:0] t_55;
wire [15:0] gen_2;
wire t_56;
wire [4:0] t_58;
wire [3:0] t_59;
wire [7:0] t_61;
wire [8:0] t_62;
wire t_63;
wire [3:0] gen_3;
wire [8:0] gen_4;
wire gen_5;
assign io_in_ready = t_33;
assign io_out = out;
assign pulse = prescaler == 16'h0;
assign busy = counter != 4'h0;
assign t_32 = busy == 1'h0;
assign t_33 = io_en & t_32;
assign t_34 = io_in_ready & io_in_valid;
assign t_36 = reset == 1'h0;
assign t_38 = {io_in_bits,1'h0};
assign t_40 = io_nstop == 1'h0;
assign t_46 = t_40 ? 4'ha : 4'h0;
assign t_48 = io_nstop ? 4'hb : 4'h0;
assign t_50 = t_46 | t_48;
assign t_51 = t_50;
assign gen_0 = t_34 ? t_38 : shifter;
assign gen_1 = t_34 ? t_51 : counter;
assign t_53 = prescaler - 16'h1;
assign t_54 = t_53[15:0];
assign t_55 = pulse ? io_div : t_54;
assign gen_2 = busy ? t_55 : prescaler;
assign t_56 = pulse & busy;
assign t_58 = counter - 4'h1;
assign t_59 = t_58[3:0];
assign t_61 = shifter[8:1];
assign t_62 = {1'h1,t_61};
assign t_63 = shifter[0];
assign gen_3 = t_56 ? t_59 : gen_1;
assign gen_4 = t_56 ? t_62 : gen_0;
assign gen_5 = t_56 ? t_63 : out;
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 16'h0;
end else begin
if (busy) begin
if (pulse) begin
prescaler <= io_div;
end else begin
prescaler <= t_54;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
counter <= 4'h0;
end else begin
if (t_56) begin
counter <= t_59;
end else begin
if (t_34) begin
counter <= t_51;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
shifter <= 9'b0;
end
else begin
if (t_56) begin
shifter <= t_62;
end else begin
if (t_34) begin
shifter <= t_38;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
out <= 1'h1;
end else begin
if (t_56) begin
out <= t_63;
end
end
always @(posedge clock or posedge reset) begin
if (t_34 & t_36) begin
$fwrite(32'h80000002,"%c",io_in_bits);
end
end
endmodule |
module fa(input wire [7:0] a,input wire [7:0] b,input wire ctrl,output wire [7:0] add,output wire [7:0] carry);
assign {carry,add} = (ctrl)?a+b:0;
endmodule |
module fs(input wire [7:0] a,input wire [7:0] b,input wire ctrl,output wire [7:0] diff,output wire [7:0] borrow);
assign {borrow,diff} = (ctrl)?a-b:0;
endmodule |
module dv(input wire [7:0] a,input wire [7:0] b,output wire [7:0] quotient,output wire [7:0] remainder);
assign quotient=a/b;
assign remainder=a%b;
endmodule |
module mul(input wire [7:0] a,input wire [7:0] b,output wire [15:0] mul);
assign mul=a*b;
endmodule |
module mux(input wire [7:0] a,input wire [7:0] b,input wire [7:0] c,input wire [7:0] d,input wire [1:0] s,output wire [7:0] y);
assign y=s[0]?(s[1]?d:c):(s[1]?b:a);
endmodule |
module display (
input clk,
input en,
input rstn,
input [31:0] data,
output reg ca,
output reg cb,
output reg cc,
output reg cd,
output reg ce,
output reg cf,
output reg cg,
output dp,
output reg [7:0] an
);
parameter clk_frequency = 100_000_000;
localparam max_counter = clk_frequency / 1000;
reg [31:0] counter; reg one_ms; reg [ 7:0] counter_an; reg [ 5:0] number_display;
assign dp = 1'b1;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
counter <= 32'b0;
one_ms <= 1'b0;
end else if (counter < max_counter - 1) begin
counter <= counter + 1'b1;
one_ms <= 1'b0;
end else begin
counter <= 32'b0;
one_ms <= 1'b1;
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
counter_an <= 8'b0;
end else if (one_ms) begin
if (counter_an < 8'd15) counter_an <= counter_an + 1'b1;
else counter_an <= 8'b0;
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
an <= 8'b11111111;
number_display <= 5'd16;
end else if (en) begin
case (counter_an)
8'd0: begin
an <= 8'b01111111;
number_display <= {1'b0, data[31:28]};
end
8'd1: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd2: begin
an <= 8'b10111111;
number_display <= {1'b0, data[27:24]};
end
8'd3: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd4: begin
an <= 8'b11011111;
number_display <= {1'b0, data[23:20]};
end
8'd5: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd6: begin
an <= 8'b11101111;
number_display <= {1'b0, data[19:16]};
end
8'd7: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd8: begin
an <= 8'b11110111;
number_display <= {1'b0, data[15:12]};
end
8'd9: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd10: begin
an <= 8'b11111011;
number_display <= {1'b0, data[11:8]};
end
8'd11: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd12: begin
an <= 8'b11111101;
number_display <= {1'b0, data[7:4]};
end
8'd13: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
8'd14: begin
an <= 8'b11111110;
number_display <= {1'b0, data[3:0]};
end
8'd15: begin
an <= 8'b11111111;
number_display <= 5'd16;
end
endcase
end else begin
an <= 8'b11111111;
number_display <= 5'd16;
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cg <= 1'b1;
cf <= 1'b1;
ce <= 1'b1;
cd <= 1'b1;
cc <= 1'b1;
cb <= 1'b1;
ca <= 1'b1;
end else
case (number_display)
5'd0: begin
cg <= 1'b1;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd1: begin
cg <= 1'b1;
cf <= 1'b1;
ce <= 1'b1;
cd <= 1'b1;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b1;
end
5'd2: begin
cg <= 1'b0;
cf <= 1'b1;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b1;
cb <= 1'b0;
ca <= 1'b0;
end
5'd3: begin
cg <= 1'b0;
cf <= 1'b1;
ce <= 1'b1;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd4: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b1;
cd <= 1'b1;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b1;
end
5'd5: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b1;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b1;
ca <= 1'b0;
end
5'd6: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b1;
ca <= 1'b0;
end
5'd7: begin
cg <= 1'b1;
cf <= 1'b1;
ce <= 1'b1;
cd <= 1'b1;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd8: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd9: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b1;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd10: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b1;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b0;
end
5'd11: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b1;
ca <= 1'b1;
end
5'd12: begin
cg <= 1'b1;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b1;
cb <= 1'b1;
ca <= 1'b0;
end
5'd13: begin
cg <= 1'b0;
cf <= 1'b1;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b0;
cb <= 1'b0;
ca <= 1'b1;
end
5'd14: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b0;
cc <= 1'b1;
cb <= 1'b1;
ca <= 1'b0;
end
5'd15: begin
cg <= 1'b0;
cf <= 1'b0;
ce <= 1'b0;
cd <= 1'b1;
cc <= 1'b1;
cb <= 1'b1;
ca <= 1'b0;
end
5'd16: begin
cg <= 1'b1;
cf <= 1'b1;
ce <= 1'b1;
cd <= 1'b1;
cc <= 1'b1;
cb <= 1'b1;
ca <= 1'b1;
end
endcase
end
endmodule |
module present_encrypt (
input wire clk,
input wire rst_n,
input wire [63:0] plaintext,
input wire [127:0] key,
output reg done,
output wire [63:0] ciphertext
);
reg [7:0] r0 = 8'h00;
reg [63:0] state;
wire [63:0] state_next;
reg [127:0] key_state;
wire [127:0] key_state_next;
reg [3:0] sbox[0:15];
initial begin
sbox[0] = 12;
sbox[1] = 5;
sbox[2] = 6;
sbox[3] = 11;
sbox[4] = 9;
sbox[5] = 0;
sbox[6] = 10;
sbox[7] = 13;
sbox[8] = 3;
sbox[9] = 14;
sbox[10] = 15;
sbox[11] = 8;
sbox[12] = 4;
sbox[13] = 7;
sbox[14] = 1;
sbox[15] = 2;
end
always @(posedge clk) begin
if (!rst_n) begin
r0 <= 8'h00;
end else if (!done) begin
r0 <= r0 + 8'h01;
end else begin
r0 <= r0;
end
end
always @(posedge clk) begin
if (r0 >= 8'd31) begin
done <= 1'b1;
end else done <= 1'b0;
end
always @(posedge clk) begin
if (!rst_n) begin
state <= plaintext;
key_state <= key;
end else if (!done) begin
state <= state_next;
key_state <= key_state_next;
end else begin
state <= state;
key_state <= key_state;
end
end
wire [63:0] sbox_in; assign sbox_in = state[63:0] ^ key_state[127:64];
wire [63:0] sbox_out; assign sbox_out = {
sbox[sbox_in[63:60]],
sbox[sbox_in[59:56]],
sbox[sbox_in[55:52]],
sbox[sbox_in[51:48]],
sbox[sbox_in[47:44]],
sbox[sbox_in[43:40]],
sbox[sbox_in[39:36]],
sbox[sbox_in[35:32]],
sbox[sbox_in[31:28]],
sbox[sbox_in[27:24]],
sbox[sbox_in[23:20]],
sbox[sbox_in[19:16]],
sbox[sbox_in[15:12]],
sbox[sbox_in[11:8]],
sbox[sbox_in[7:4]],
sbox[sbox_in[3:0]]
};
wire [63:0] player_out;
assign player_out = {
sbox_out[63-0],
sbox_out[63-4],
sbox_out[63-8],
sbox_out[63-12],
sbox_out[63-16],
sbox_out[63-20],
sbox_out[63-24],
sbox_out[63-28],
sbox_out[63-32],
sbox_out[63-36],
sbox_out[63-40],
sbox_out[63-44],
sbox_out[63-48],
sbox_out[63-52],
sbox_out[63-56],
sbox_out[63-60],
sbox_out[63-1],
sbox_out[63-5],
sbox_out[63-9],
sbox_out[63-13],
sbox_out[63-17],
sbox_out[63-21],
sbox_out[63-25],
sbox_out[63-29],
sbox_out[63-33],
sbox_out[63-37],
sbox_out[63-41],
sbox_out[63-45],
sbox_out[63-49],
sbox_out[63-53],
sbox_out[63-57],
sbox_out[63-61],
sbox_out[63-2],
sbox_out[63-6],
sbox_out[63-10],
sbox_out[63-14],
sbox_out[63-18],
sbox_out[63-22],
sbox_out[63-26],
sbox_out[63-30],
sbox_out[63-34],
sbox_out[63-38],
sbox_out[63-42],
sbox_out[63-46],
sbox_out[63-50],
sbox_out[63-54],
sbox_out[63-58],
sbox_out[63-62],
sbox_out[63-3],
sbox_out[63-7],
sbox_out[63-11],
sbox_out[63-15],
sbox_out[63-19],
sbox_out[63-23],
sbox_out[63-27],
sbox_out[63-31],
sbox_out[63-35],
sbox_out[63-39],
sbox_out[63-43],
sbox_out[63-47],
sbox_out[63-51],
sbox_out[63-55],
sbox_out[63-59],
sbox_out[63-63]
};
assign state_next = player_out;
wire [127:0] key_shift = {key_state[66:0], key_state[127:67]};
wire [ 7:0] key_sbox = {sbox[key_shift[127:124]], sbox[key_shift[123:120]]};
wire [ 4:0] key_const = key_shift[66:62] ^ r0[4:0];
assign key_state_next = {key_sbox, key_shift[119:67], key_const, key_shift[61:0]};
assign ciphertext = state_next ^ key_state_next[127:64];
endmodule |
module glbl ();
parameter roc_width = 100000;
parameter toc_width = 0;
parameter gres_width = 10000;
parameter gres_start = 10000;
wire gsr;
wire gts;
wire gwe;
wire prld;
wire grestore;
tri1 p_up_tmp;
tri (weak1, strong0) pll_lockg = p_up_tmp;
wire progb_glbl;
wire cclko_glbl;
wire fcsbo_glbl;
wire [3:0] do_glbl;
wire [3:0] di_glbl;
reg gsr_int;
reg gts_int;
reg prld_int;
reg grestore_int;
wire jtag_tdo_glbl;
wire jtag_tck_glbl;
wire jtag_tdi_glbl;
wire jtag_tms_glbl;
wire jtag_trst_glbl;
reg jtag_capture_glbl;
reg jtag_reset_glbl;
reg jtag_shift_glbl;
reg jtag_update_glbl;
reg jtag_runtest_glbl;
reg jtag_sel1_glbl = 0;
reg jtag_sel2_glbl = 0 ;
reg jtag_sel3_glbl = 0;
reg jtag_sel4_glbl = 0;
reg jtag_user_tdo1_glbl = 1'bz;
reg jtag_user_tdo2_glbl = 1'bz;
reg jtag_user_tdo3_glbl = 1'bz;
reg jtag_user_tdo4_glbl = 1'bz;
assign (strong1, weak0) gsr = gsr_int;
assign (strong1, weak0) gts = gts_int;
assign (weak1, weak0) prld = prld_int;
assign (strong1, weak0) grestore = grestore_int;
initial begin
gsr_int = 1'b1;
prld_int = 1'b1;
#(roc_width)
gsr_int = 1'b0;
prld_int = 1'b0;
end
initial begin
gts_int = 1'b1;
#(toc_width)
gts_int = 1'b0;
end
initial begin
grestore_int = 1'b0;
#(gres_start);
grestore_int = 1'b1;
#(gres_width);
grestore_int = 1'b0;
end
endmodule |
module case_box(in_0, out_0);
input [7:0] in_0;
output [255:0] out_0;
wire [7:0] in_0;
wire [255:0] out_0;
wire n_9, n_10, n_19, n_29, n_39, n_49, n_59, n_69;
wire n_79, n_89, n_99, n_109, n_119, n_129, n_139, n_149;
wire n_159, n_170, n_330, n_490, n_650, n_810, n_970, n_1130;
wire n_1290, n_1450, n_1610, n_1770, n_1930, n_2410, n_4361, n_4362;
wire n_4363, n_4364, n_4365, n_4366, n_4367, n_4368, n_4369, n_4370;
assign n_10 = ~(n_4361 & n_4362 & n_4363 & n_4364);
assign n_9 = ~(n_4365 & n_4366 & n_4367 & n_4368);
assign out_0[255] = ~(n_9 | n_10);
assign n_19 = ~(n_4365 & n_4366 & n_4367 & in_0[0]);
assign out_0[254] = ~(n_19 | n_10);
assign n_29 = ~(n_4365 & n_4366 & in_0[1] & n_4368);
assign out_0[253] = ~(n_29 | n_10);
assign n_39 = ~(n_4365 & n_4366 & in_0[1] & in_0[0]);
assign out_0[252] = ~(n_39 | n_10);
assign n_49 = ~(n_4365 & in_0[2] & n_4367 & n_4368);
assign out_0[251] = ~(n_49 | n_10);
assign n_59 = ~(n_4365 & in_0[2] & n_4367 & in_0[0]);
assign out_0[250] = ~(n_59 | n_10);
assign n_69 = ~(n_4365 & in_0[2] & in_0[1] & n_4368);
assign out_0[249] = ~(n_69 | n_10);
assign n_79 = ~(n_4365 & in_0[2] & in_0[1] & in_0[0]);
assign out_0[248] = ~(n_79 | n_10);
assign n_89 = ~(in_0[3] & n_4366 & n_4367 & n_4368);
assign out_0[247] = ~(n_89 | n_10);
assign n_99 = ~(in_0[3] & n_4366 & n_4367 & in_0[0]);
assign out_0[246] = ~(n_99 | n_10);
assign n_109 = ~(in_0[3] & n_4366 & in_0[1] & n_4368);
assign out_0[245] = ~(n_109 | n_10);
assign n_119 = ~(in_0[3] & n_4366 & in_0[1] & in_0[0]);
assign out_0[244] = ~(n_119 | n_10);
assign n_129 = ~(in_0[3] & in_0[2] & n_4367 & n_4368);
assign out_0[243] = ~(n_129 | n_10);
assign n_139 = ~(in_0[3] & in_0[2] & n_4367 & in_0[0]);
assign out_0[242] = ~(n_139 | n_10);
assign n_149 = ~(in_0[3] & in_0[2] & in_0[1] & n_4368);
assign out_0[241] = ~(n_149 | n_10);
assign n_159 = ~(in_0[3] & in_0[2] & in_0[1] & in_0[0]);
assign out_0[240] = ~(n_159 | n_10);
assign n_170 = ~(n_4361 & n_4362 & n_4363 & in_0[4]);
assign out_0[239] = ~(n_9 | n_170);
assign out_0[238] = ~(n_19 | n_170);
assign out_0[237] = ~(n_29 | n_170);
assign out_0[236] = ~(n_39 | n_170);
assign out_0[235] = ~(n_49 | n_170);
assign out_0[234] = ~(n_59 | n_170);
assign out_0[233] = ~(n_69 | n_170);
assign out_0[232] = ~(n_79 | n_170);
assign out_0[231] = ~(n_89 | n_170);
assign out_0[230] = ~(n_99 | n_170);
assign out_0[229] = ~(n_109 | n_170);
assign out_0[228] = ~(n_119 | n_170);
assign out_0[227] = ~(n_129 | n_170);
assign out_0[226] = ~(n_139 | n_170);
assign out_0[225] = ~(n_149 | n_170);
assign out_0[224] = ~(n_159 | n_170);
assign n_330 = ~(n_4361 & n_4362 & in_0[5] & n_4364);
assign out_0[223] = ~(n_9 | n_330);
assign out_0[222] = ~(n_19 | n_330);
assign out_0[221] = ~(n_29 | n_330);
assign out_0[220] = ~(n_39 | n_330);
assign out_0[219] = ~(n_49 | n_330);
assign out_0[218] = ~(n_59 | n_330);
assign out_0[217] = ~(n_69 | n_330);
assign out_0[216] = ~(n_79 | n_330);
assign out_0[215] = ~(n_89 | n_330);
assign out_0[214] = ~(n_99 | n_330);
assign out_0[213] = ~(n_109 | n_330);
assign out_0[212] = ~(n_119 | n_330);
assign out_0[211] = ~(n_129 | n_330);
assign out_0[210] = ~(n_139 | n_330);
assign out_0[209] = ~(n_149 | n_330);
assign out_0[208] = ~(n_159 | n_330);
assign n_490 = ~(n_4361 & n_4362 & in_0[5] & in_0[4]);
assign out_0[207] = ~(n_9 | n_490);
assign out_0[206] = ~(n_19 | n_490);
assign out_0[205] = ~(n_29 | n_490);
assign out_0[204] = ~(n_39 | n_490);
assign out_0[203] = ~(n_49 | n_490);
assign out_0[202] = ~(n_59 | n_490);
assign out_0[201] = ~(n_69 | n_490);
assign out_0[200] = ~(n_79 | n_490);
assign out_0[199] = ~(n_89 | n_490);
assign out_0[198] = ~(n_99 | n_490);
assign out_0[197] = ~(n_109 | n_490);
assign out_0[196] = ~(n_119 | n_490);
assign out_0[195] = ~(n_129 | n_490);
assign out_0[194] = ~(n_139 | n_490);
assign out_0[193] = ~(n_149 | n_490);
assign out_0[192] = ~(n_159 | n_490);
assign n_650 = ~(n_4361 & in_0[6] & n_4363 & n_4364);
assign out_0[191] = ~(n_9 | n_650);
assign out_0[190] = ~(n_19 | n_650);
assign out_0[189] = ~(n_29 | n_650);
assign out_0[188] = ~(n_39 | n_650);
assign out_0[187] = ~(n_49 | n_650);
assign out_0[186] = ~(n_59 | n_650);
assign out_0[185] = ~(n_69 | n_650);
assign out_0[184] = ~(n_79 | n_650);
assign out_0[183] = ~(n_89 | n_650);
assign out_0[182] = ~(n_99 | n_650);
assign out_0[181] = ~(n_109 | n_650);
assign out_0[180] = ~(n_119 | n_650);
assign out_0[179] = ~(n_129 | n_650);
assign out_0[178] = ~(n_139 | n_650);
assign out_0[177] = ~(n_149 | n_650);
assign out_0[176] = ~(n_159 | n_650);
assign n_810 = ~(n_4361 & in_0[6] & n_4363 & in_0[4]);
assign out_0[175] = ~(n_9 | n_810);
assign out_0[174] = ~(n_19 | n_810);
assign out_0[173] = ~(n_29 | n_810);
assign out_0[172] = ~(n_39 | n_810);
assign out_0[171] = ~(n_49 | n_810);
assign out_0[170] = ~(n_59 | n_810);
assign out_0[169] = ~(n_69 | n_810);
assign out_0[168] = ~(n_79 | n_810);
assign out_0[167] = ~(n_89 | n_810);
assign out_0[166] = ~(n_99 | n_810);
assign out_0[165] = ~(n_109 | n_810);
assign out_0[164] = ~(n_119 | n_810);
assign out_0[163] = ~(n_129 | n_810);
assign out_0[162] = ~(n_139 | n_810);
assign out_0[161] = ~(n_149 | n_810);
assign out_0[160] = ~(n_159 | n_810);
assign n_970 = ~(n_4361 & in_0[6] & in_0[5] & n_4364);
assign out_0[159] = ~(n_9 | n_970);
assign out_0[158] = ~(n_19 | n_970);
assign out_0[157] = ~(n_29 | n_970);
assign out_0[156] = ~(n_39 | n_970);
assign out_0[155] = ~(n_49 | n_970);
assign out_0[154] = ~(n_59 | n_970);
assign out_0[153] = ~(n_69 | n_970);
assign out_0[152] = ~(n_79 | n_970);
assign out_0[151] = ~(n_89 | n_970);
assign out_0[150] = ~(n_99 | n_970);
assign out_0[149] = ~(n_109 | n_970);
assign out_0[148] = ~(n_119 | n_970);
assign out_0[147] = ~(n_129 | n_970);
assign out_0[146] = ~(n_139 | n_970);
assign out_0[145] = ~(n_149 | n_970);
assign out_0[144] = ~(n_159 | n_970);
assign n_1130 = ~(n_4361 & in_0[6] & in_0[5] & in_0[4]);
assign out_0[143] = ~(n_9 | n_1130);
assign out_0[142] = ~(n_19 | n_1130);
assign out_0[141] = ~(n_29 | n_1130);
assign out_0[140] = ~(n_39 | n_1130);
assign out_0[139] = ~(n_49 | n_1130);
assign out_0[138] = ~(n_59 | n_1130);
assign out_0[137] = ~(n_69 | n_1130);
assign out_0[136] = ~(n_79 | n_1130);
assign out_0[135] = ~(n_89 | n_1130);
assign out_0[134] = ~(n_99 | n_1130);
assign out_0[133] = ~(n_109 | n_1130);
assign out_0[132] = ~(n_119 | n_1130);
assign out_0[131] = ~(n_129 | n_1130);
assign out_0[130] = ~(n_139 | n_1130);
assign out_0[129] = ~(n_149 | n_1130);
assign out_0[128] = ~(n_159 | n_1130);
assign n_1290 = ~(in_0[7] & n_4362 & n_4363 & n_4364);
assign out_0[127] = ~(n_9 | n_1290);
assign out_0[126] = ~(n_19 | n_1290);
assign out_0[125] = ~(n_29 | n_1290);
assign out_0[124] = ~(n_39 | n_1290);
assign out_0[123] = ~(n_49 | n_1290);
assign out_0[122] = ~(n_59 | n_1290);
assign out_0[121] = ~(n_69 | n_1290);
assign out_0[120] = ~(n_79 | n_1290);
assign out_0[119] = ~(n_89 | n_1290);
assign out_0[118] = ~(n_99 | n_1290);
assign out_0[117] = ~(n_109 | n_1290);
assign out_0[116] = ~(n_119 | n_1290);
assign out_0[115] = ~(n_129 | n_1290);
assign out_0[114] = ~(n_139 | n_1290);
assign out_0[113] = ~(n_149 | n_1290);
assign out_0[112] = ~(n_159 | n_1290);
assign n_1450 = ~(in_0[7] & n_4362 & n_4363 & in_0[4]);
assign out_0[111] = ~(n_9 | n_1450);
assign out_0[110] = ~(n_19 | n_1450);
assign out_0[109] = ~(n_29 | n_1450);
assign out_0[108] = ~(n_39 | n_1450);
assign out_0[107] = ~(n_49 | n_1450);
assign out_0[106] = ~(n_59 | n_1450);
assign out_0[105] = ~(n_69 | n_1450);
assign out_0[104] = ~(n_79 | n_1450);
assign out_0[103] = ~(n_89 | n_1450);
assign out_0[102] = ~(n_99 | n_1450);
assign out_0[101] = ~(n_109 | n_1450);
assign out_0[100] = ~(n_119 | n_1450);
assign out_0[99] = ~(n_129 | n_1450);
assign out_0[98] = ~(n_139 | n_1450);
assign out_0[97] = ~(n_149 | n_1450);
assign out_0[96] = ~(n_159 | n_1450);
assign n_1610 = ~(in_0[7] & n_4362 & in_0[5] & n_4364);
assign out_0[95] = ~(n_9 | n_1610);
assign out_0[94] = ~(n_19 | n_1610);
assign out_0[93] = ~(n_29 | n_1610);
assign out_0[92] = ~(n_39 | n_1610);
assign out_0[91] = ~(n_49 | n_1610);
assign out_0[90] = ~(n_59 | n_1610);
assign out_0[89] = ~(n_69 | n_1610);
assign out_0[88] = ~(n_79 | n_1610);
assign out_0[87] = ~(n_89 | n_1610);
assign out_0[86] = ~(n_99 | n_1610);
assign out_0[85] = ~(n_109 | n_1610);
assign out_0[84] = ~(n_119 | n_1610);
assign out_0[83] = ~(n_129 | n_1610);
assign out_0[82] = ~(n_139 | n_1610);
assign out_0[81] = ~(n_149 | n_1610);
assign out_0[80] = ~(n_159 | n_1610);
assign n_1770 = ~(in_0[7] & n_4362 & in_0[5] & in_0[4]);
assign out_0[79] = ~(n_9 | n_1770);
assign out_0[78] = ~(n_19 | n_1770);
assign out_0[77] = ~(n_29 | n_1770);
assign out_0[76] = ~(n_39 | n_1770);
assign out_0[75] = ~(n_49 | n_1770);
assign out_0[74] = ~(n_59 | n_1770);
assign out_0[73] = ~(n_69 | n_1770);
assign out_0[72] = ~(n_79 | n_1770);
assign out_0[71] = ~(n_89 | n_1770);
assign out_0[70] = ~(n_99 | n_1770);
assign out_0[69] = ~(n_109 | n_1770);
assign out_0[68] = ~(n_119 | n_1770);
assign out_0[67] = ~(n_129 | n_1770);
assign out_0[66] = ~(n_139 | n_1770);
assign out_0[65] = ~(n_149 | n_1770);
assign out_0[64] = ~(n_159 | n_1770);
assign n_1930 = ~(in_0[7] & in_0[6] & n_4363 & n_4364);
assign out_0[63] = ~(n_9 | n_1930);
assign out_0[62] = ~(n_19 | n_1930);
assign out_0[61] = ~(n_29 | n_1930);
assign out_0[60] = ~(n_39 | n_1930);
assign out_0[59] = ~(n_49 | n_1930);
assign out_0[58] = ~(n_59 | n_1930);
assign out_0[57] = ~(n_69 | n_1930);
assign out_0[56] = ~(n_79 | n_1930);
assign out_0[55] = ~(n_89 | n_1930);
assign out_0[54] = ~(n_99 | n_1930);
assign out_0[53] = ~(n_109 | n_1930);
assign out_0[52] = ~(n_119 | n_1930);
assign out_0[51] = ~(n_129 | n_1930);
assign out_0[50] = ~(n_139 | n_1930);
assign out_0[49] = ~(n_149 | n_1930);
assign out_0[48] = ~(n_159 | n_1930);
assign n_4369 = ~(in_0[7] & in_0[6] & n_4363 & in_0[4]);
assign out_0[47] = ~(n_9 | n_4369);
assign out_0[46] = ~(n_19 | n_4369);
assign out_0[45] = ~(n_29 | n_4369);
assign out_0[44] = ~(n_39 | n_4369);
assign out_0[43] = ~(n_49 | n_4369);
assign out_0[42] = ~(n_59 | n_4369);
assign out_0[41] = ~(n_69 | n_4369);
assign out_0[40] = ~(n_79 | n_4369);
assign out_0[39] = ~(n_89 | n_4369);
assign out_0[38] = ~(n_99 | n_4369);
assign out_0[37] = ~(n_109 | n_4369);
assign out_0[36] = ~(n_119 | n_4369);
assign out_0[35] = ~(n_129 | n_4369);
assign out_0[34] = ~(n_139 | n_4369);
assign out_0[33] = ~(n_149 | n_4369);
assign out_0[32] = ~(n_159 | n_4369);
assign n_4370 = ~(in_0[7] & in_0[6] & in_0[5] & n_4364);
assign out_0[31] = ~(n_9 | n_4370);
assign out_0[30] = ~(n_19 | n_4370);
assign out_0[29] = ~(n_29 | n_4370);
assign out_0[28] = ~(n_39 | n_4370);
assign out_0[27] = ~(n_49 | n_4370);
assign out_0[26] = ~(n_59 | n_4370);
assign out_0[25] = ~(n_69 | n_4370);
assign out_0[24] = ~(n_79 | n_4370);
assign out_0[23] = ~(n_89 | n_4370);
assign out_0[22] = ~(n_99 | n_4370);
assign out_0[21] = ~(n_109 | n_4370);
assign out_0[20] = ~(n_119 | n_4370);
assign out_0[19] = ~(n_129 | n_4370);
assign out_0[18] = ~(n_139 | n_4370);
assign out_0[17] = ~(n_149 | n_4370);
assign out_0[16] = ~(n_159 | n_4370);
assign n_2410 = ~(in_0[7] & in_0[6] & in_0[5] & in_0[4]);
assign out_0[15] = ~(n_9 | n_2410);
assign out_0[14] = ~(n_19 | n_2410);
assign out_0[13] = ~(n_29 | n_2410);
assign out_0[12] = ~(n_39 | n_2410);
assign out_0[11] = ~(n_49 | n_2410);
assign out_0[10] = ~(n_59 | n_2410);
assign out_0[9] = ~(n_69 | n_2410);
assign out_0[8] = ~(n_79 | n_2410);
assign out_0[7] = ~(n_89 | n_2410);
assign out_0[6] = ~(n_99 | n_2410);
assign out_0[5] = ~(n_109 | n_2410);
assign out_0[4] = ~(n_119 | n_2410);
assign out_0[3] = ~(n_129 | n_2410);
assign out_0[2] = ~(n_139 | n_2410);
assign out_0[1] = ~(n_149 | n_2410);
assign out_0[0] = ~(n_159 | n_2410);
assign n_4361 = ~(in_0[7]);
assign n_4362 = ~(in_0[6]);
assign n_4363 = ~(in_0[5]);
assign n_4364 = ~(in_0[4]);
assign n_4365 = ~(in_0[3]);
assign n_4366 = ~(in_0[2]);
assign n_4367 = ~(in_0[1]);
assign n_4368 = ~(in_0[0]);
endmodule |
module add_unsigned(a, b, z);
input [3:0] a;
input b;
output [3:0] z;
wire [3:0] a;
wire b;
wire [3:0] z;
wire n_11, n_18, n_21, n_28, n_30, n_34, n_35, n_37;
wire n_38;
assign z[0] = a[0] ^ b;
assign n_11 = ~(a[0] & b);
assign n_21 = ~(n_18 & a[1]);
assign n_30 = ~(n_28 & a[2]);
assign z[1] = ~(n_18 ^ n_34);
assign z[2] = ~(n_28 ^ n_35);
assign z[3] = ~(n_37 ^ n_38);
assign n_18 = ~(n_11);
assign n_34 = ~(a[1]);
assign n_35 = ~(a[2]);
assign n_38 = ~(a[3]);
assign n_28 = ~(n_21);
assign n_37 = ~(n_30);
endmodule |
module case_box_1(in_0, out_0);
input [3:0] in_0;
output [10:0] out_0;
wire [3:0] in_0;
wire [10:0] out_0;
wire n_5, n_7, n_9, n_10, n_12, n_14, n_16, n_18;
wire n_23, n_26, n_96, n_97;
assign out_0[10] = ~(n_5 | n_10);
assign n_5 = ~(n_96 & n_97);
assign n_96 = ~(in_0[0]);
assign n_97 = ~(in_0[1]);
assign n_10 = ~(n_7 & n_9);
assign n_7 = ~(in_0[3]);
assign n_9 = ~(in_0[2]);
assign out_0[9] = ~(n_10 | n_12);
assign n_12 = ~(in_0[0] & n_97);
assign out_0[8] = ~(n_10 | n_14);
assign n_14 = ~(n_96 & in_0[1]);
assign out_0[7] = ~(n_10 | n_16);
assign n_16 = ~(in_0[0] & in_0[1]);
assign out_0[6] = ~(n_5 | n_18);
assign n_18 = ~(n_7 & in_0[2]);
assign out_0[5] = ~(n_12 | n_18);
assign out_0[4] = ~(n_14 | n_18);
assign out_0[3] = ~(n_16 | n_18);
assign out_0[2] = ~(n_5 | n_23);
assign n_23 = ~(in_0[3] & n_9);
assign out_0[1] = ~(n_12 | n_23);
assign out_0[0] = ~(n_7 | n_26);
assign n_26 = ~(in_0[2] | in_0[1]);
endmodule |
module xor_op(a, b, z);
input [31:0] a, b;
output [31:0] z;
wire [31:0] a, b;
wire [31:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
assign z[8] = a[8] ^ b[8];
assign z[9] = a[9] ^ b[9];
assign z[10] = a[10] ^ b[10];
assign z[11] = a[11] ^ b[11];
assign z[12] = a[12] ^ b[12];
assign z[13] = a[13] ^ b[13];
assign z[14] = a[14] ^ b[14];
assign z[15] = a[15] ^ b[15];
assign z[16] = a[16] ^ b[16];
assign z[17] = a[17] ^ b[17];
assign z[18] = a[18] ^ b[18];
assign z[19] = a[19] ^ b[19];
assign z[20] = a[20] ^ b[20];
assign z[21] = a[21] ^ b[21];
assign z[22] = a[22] ^ b[22];
assign z[23] = a[23] ^ b[23];
assign z[24] = a[24] ^ b[24];
assign z[25] = a[25] ^ b[25];
assign z[26] = a[26] ^ b[26];
assign z[27] = a[27] ^ b[27];
assign z[28] = a[28] ^ b[28];
assign z[29] = a[29] ^ b[29];
assign z[30] = a[30] ^ b[30];
assign z[31] = a[31] ^ b[31];
endmodule |
module xor_op_3(a, b, z);
input [31:0] a, b;
output [31:0] z;
wire [31:0] a, b;
wire [31:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
assign z[8] = a[8] ^ b[8];
assign z[9] = a[9] ^ b[9];
assign z[10] = a[10] ^ b[10];
assign z[11] = a[11] ^ b[11];
assign z[12] = a[12] ^ b[12];
assign z[13] = a[13] ^ b[13];
assign z[14] = a[14] ^ b[14];
assign z[15] = a[15] ^ b[15];
assign z[16] = a[16] ^ b[16];
assign z[17] = a[17] ^ b[17];
assign z[18] = a[18] ^ b[18];
assign z[19] = a[19] ^ b[19];
assign z[20] = a[20] ^ b[20];
assign z[21] = a[21] ^ b[21];
assign z[22] = a[22] ^ b[22];
assign z[23] = a[23] ^ b[23];
assign z[24] = a[24] ^ b[24];
assign z[25] = a[25] ^ b[25];
assign z[26] = a[26] ^ b[26];
assign z[27] = a[27] ^ b[27];
assign z[28] = a[28] ^ b[28];
assign z[29] = a[29] ^ b[29];
assign z[30] = a[30] ^ b[30];
assign z[31] = a[31] ^ b[31];
endmodule |
module xor_op_4(a, b, z);
input [31:0] a, b;
output [31:0] z;
wire [31:0] a, b;
wire [31:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
assign z[8] = a[8] ^ b[8];
assign z[9] = a[9] ^ b[9];
assign z[10] = a[10] ^ b[10];
assign z[11] = a[11] ^ b[11];
assign z[12] = a[12] ^ b[12];
assign z[13] = a[13] ^ b[13];
assign z[14] = a[14] ^ b[14];
assign z[15] = a[15] ^ b[15];
assign z[16] = a[16] ^ b[16];
assign z[17] = a[17] ^ b[17];
assign z[18] = a[18] ^ b[18];
assign z[19] = a[19] ^ b[19];
assign z[20] = a[20] ^ b[20];
assign z[21] = a[21] ^ b[21];
assign z[22] = a[22] ^ b[22];
assign z[23] = a[23] ^ b[23];
assign z[24] = a[24] ^ b[24];
assign z[25] = a[25] ^ b[25];
assign z[26] = a[26] ^ b[26];
assign z[27] = a[27] ^ b[27];
assign z[28] = a[28] ^ b[28];
assign z[29] = a[29] ^ b[29];
assign z[30] = a[30] ^ b[30];
assign z[31] = a[31] ^ b[31];
endmodule |
module xor_op_10(a, b, z);
input [31:0] a, b;
output [31:0] z;
wire [31:0] a, b;
wire [31:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
assign z[8] = a[8] ^ b[8];
assign z[9] = a[9] ^ b[9];
assign z[10] = a[10] ^ b[10];
assign z[11] = a[11] ^ b[11];
assign z[12] = a[12] ^ b[12];
assign z[13] = a[13] ^ b[13];
assign z[14] = a[14] ^ b[14];
assign z[15] = a[15] ^ b[15];
assign z[16] = a[16] ^ b[16];
assign z[17] = a[17] ^ b[17];
assign z[18] = a[18] ^ b[18];
assign z[19] = a[19] ^ b[19];
assign z[20] = a[20] ^ b[20];
assign z[21] = a[21] ^ b[21];
assign z[22] = a[22] ^ b[22];
assign z[23] = a[23] ^ b[23];
assign z[24] = a[24] ^ b[24];
assign z[25] = a[25] ^ b[25];
assign z[26] = a[26] ^ b[26];
assign z[27] = a[27] ^ b[27];
assign z[28] = a[28] ^ b[28];
assign z[29] = a[29] ^ b[29];
assign z[30] = a[30] ^ b[30];
assign z[31] = a[31] ^ b[31];
endmodule |
module or_op(a, z);
input [3:0] a;
output z;
wire [3:0] a;
wire z;
wire n_5;
assign n_5 = ~(a[3] | a[2] | a[1] | a[0]);
assign z = ~(n_5);
endmodule |
module or_op_36(a, z);
input [2:0] a;
output z;
wire [2:0] a;
wire z;
wire n_4;
assign n_4 = ~(a[2] | a[1] | a[0]);
assign z = ~(n_4);
endmodule |
module xor_op_40(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_41(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_43(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_45(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_47(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_49(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_51(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_53(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_55(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_57(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_63(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_65(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_67(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_71(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_72(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_73(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_74(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_75(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_76(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_80(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_81(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_82(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_83(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_85(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_86(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_87(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_91(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_93(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_95(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_99(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_101(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_103(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_105(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_109(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_111(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_113(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module xor_op_117(a, b, z);
input [7:0] a, b;
output [7:0] z;
wire [7:0] a, b;
wire [7:0] z;
assign z[0] = a[0] ^ b[0];
assign z[1] = a[1] ^ b[1];
assign z[2] = a[2] ^ b[2];
assign z[3] = a[3] ^ b[3];
assign z[4] = a[4] ^ b[4];
assign z[5] = a[5] ^ b[5];
assign z[6] = a[6] ^ b[6];
assign z[7] = a[7] ^ b[7];
endmodule |
module sub_unsigned(a, b, z);
input [3:0] a;
input b;
output [3:0] z;
wire [3:0] a;
wire b;
wire [3:0] z;
wire n_18, n_21, n_24, n_26, n_27, n_28, n_34, n_36;
wire n_43, n_45;
assign n_18 = ~(b);
assign n_45 = a[0] ^ n_18;
assign n_24 = ~(n_21 & b);
assign n_34 = ~(n_26 & n_27);
assign n_43 = ~(n_28 & n_36);
assign z[1] = ~(n_24 ^ a[1]);
assign z[2] = ~(n_34 ^ a[2]);
assign z[3] = ~(n_43 ^ a[3]);
assign n_28 = ~(a[2]);
assign n_26 = ~(a[1]);
assign n_21 = ~(a[0]);
assign z[0] = ~(n_45);
assign n_27 = ~(n_24);
assign n_36 = ~(n_34);
endmodule |
Subsets and Splits