text
stringlengths 21
997k
|
|---|
module halfsub(input a,
input b,
output diff,
output borrow);
xor (diff,a,b);
and (borrow,~a,b);
endmodule |
module mux2_1(input a,input b,input s,output y);
assign y = (~s&a)|(s&b);
endmodule |
module mux2_1(input a,input b,input s,output reg y);
always @(a,b)
case(s)
0: begin y= a; end
1: begin y= b; end
endcase
endmodule |
module mux2_1(input a,input b,input s,output y);
wire m ;
wire n;
and a1(m,a,~s);
and a2(n,b,s);
or (y,m,n);
endmodule |
module popcount #(
parameter inputs = 8,
parameter counter_bits = 4
) (
input [inputs-1:0] in,
output reg [counter_bits-1:0] count
);
integer i;
always @(*) begin
if (inputs == 4) begin
count = in[3] + in[2] + in[1] + in[0];
end else if (inputs == 8) begin
count = in[7] + in[6] + in[5] + in[4] + in[3] + in[2] + in[1] + in[0];
end else if (inputs == 10) begin
count = in[9] + in[8] +
in[7] + in[6] + in[5] + in[4] + in[3] + in[2] + in[1] + in[0];
end else if (inputs == 16) begin
count = in[15]+in[14] +in[13] +in[12] +in[11] +in[10] + in[9] + in[8] +
in[7] + in[6] + in[5] + in[4] + in[3] + in[2] + in[1] + in[0];
end else begin
count = 0;
for (i = 0; i < inputs; i = i + 1) begin
count = count + in[i];
end
end
end
endmodule |
module wishbonetobmb (
input io_input_cyc,
input io_input_stb,
output io_input_ack,
input io_input_we,
input [13:0] io_input_adr,
output [31:0] io_input_dat_miso,
input [31:0] io_input_dat_mosi,
input [3:0] io_input_sel,
output io_output_cmd_valid,
input io_output_cmd_ready,
output io_output_cmd_payload_last,
output [0:0] io_output_cmd_payload_fragment_opcode,
output [15:0] io_output_cmd_payload_fragment_address,
output [1:0] io_output_cmd_payload_fragment_length,
output [31:0] io_output_cmd_payload_fragment_data,
output [3:0] io_output_cmd_payload_fragment_mask,
input io_output_rsp_valid,
output io_output_rsp_ready,
input io_output_rsp_payload_last,
input [0:0] io_output_rsp_payload_fragment_opcode,
input [31:0] io_output_rsp_payload_fragment_data,
input ctrlcd_clk,
input ctrlcd_reset
);
reg _zz_io_output_cmd_valid;
wire io_output_cmd_fire;
wire io_output_rsp_fire;
assign io_output_cmd_payload_fragment_address = ({2'd0,io_input_adr} <<< 2'd2);
assign io_output_cmd_payload_fragment_opcode = (io_input_we ? 1'b1 : 1'b0);
assign io_output_cmd_payload_fragment_data = io_input_dat_mosi;
assign io_output_cmd_payload_fragment_mask = io_input_sel;
assign io_output_cmd_payload_fragment_length = 2'b11;
assign io_output_cmd_payload_last = 1'b1;
assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready);
assign io_output_rsp_fire = (io_output_rsp_valid && io_output_rsp_ready);
assign io_output_cmd_valid = ((io_input_cyc && io_input_stb) && (! _zz_io_output_cmd_valid));
assign io_input_ack = io_output_rsp_fire;
assign io_input_dat_miso = io_output_rsp_payload_fragment_data;
assign io_output_rsp_ready = 1'b1;
always @(posedge ctrlcd_clk or posedge ctrlcd_reset) begin
if(ctrlcd_reset) begin
_zz_io_output_cmd_valid <= 1'b0;
end else begin
if(io_output_cmd_fire) begin
_zz_io_output_cmd_valid <= 1'b1;
end
if(io_output_rsp_fire) begin
_zz_io_output_cmd_valid <= 1'b0;
end
end
end
endmodule |
module buffercc_2 (
input io_datain,
output io_dataout,
input phycd_clk,
input phycd_reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
initial begin
`ifndef synthesis
buffers_0 = $urandom;
buffers_1 = $urandom;
`endif
end
assign io_dataout = buffers_1;
always @(posedge phycd_clk) begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
endmodule |
module buffercc (
input io_datain,
output io_dataout,
input ctrlcd_clk,
input ctrlcd_reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
initial begin
`ifndef synthesis
buffers_0 = $urandom;
buffers_1 = $urandom;
`endif
end
assign io_dataout = buffers_1;
always @(posedge ctrlcd_clk) begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
endmodule |
module usblsfsphyfilter (
input io_lowspeed,
input io_usb_dp,
input io_usb_dm,
output io_filtered_dp,
output io_filtered_dm,
output io_filtered_d,
output io_filtered_se0,
output io_filtered_sample,
input phycd_clk,
input phycd_reset
);
wire [4:0] _zz_timer_sampledo;
wire frontend_value;
reg timer_clear;
reg [4:0] timer_counter;
wire [4:0] timer_counterlimit;
wire when_usbdevicephy_l104;
wire [3:0] timer_sampleat;
wire timer_sampledo;
reg io_usb_dp_regnext;
reg io_usb_dm_regnext;
wire when_usbdevicephy_l111;
assign _zz_timer_sampledo = {1'd0, timer_sampleat};
assign frontend_value = (io_lowspeed ? io_usb_dm : io_usb_dp);
always @(*) begin
timer_clear = 1'b0;
if(when_usbdevicephy_l111) begin
timer_clear = 1'b1;
end
end
assign timer_counterlimit = (io_lowspeed ? 5'h1f : 5'h03);
assign when_usbdevicephy_l104 = ((timer_counter == timer_counterlimit) || timer_clear);
assign timer_sampleat = (io_lowspeed ? 4'b1110 : 4'b0000);
assign timer_sampledo = ((timer_counter == _zz_timer_sampledo) && (! timer_clear));
assign when_usbdevicephy_l111 = ((io_usb_dp ^ io_usb_dp_regnext) || (io_usb_dm ^ io_usb_dm_regnext));
assign io_filtered_dp = io_usb_dp;
assign io_filtered_dm = io_usb_dm;
assign io_filtered_d = frontend_value;
assign io_filtered_sample = timer_sampledo;
assign io_filtered_se0 = ((! io_usb_dp) && (! io_usb_dm));
always @(posedge phycd_clk) begin
timer_counter <= (timer_counter + 5'h01);
if(when_usbdevicephy_l104) begin
timer_counter <= 5'h00;
end
io_usb_dp_regnext <= io_usb_dp;
io_usb_dm_regnext <= io_usb_dm;
end
endmodule |
module usbcrc16 (
input [7:0] io_data,
input io_enable,
input io_init,
output [15:0] io_crc,
output io_crcerror,
input ctrlcd_clk,
input ctrlcd_reset
);
wire _zz_crcnext_0;
wire _zz_crcnext_0_1;
wire [0:0] _zz_crc;
wire [4:0] _zz_crc_1;
wire [15:0] initial_value;
wire [15:0] verify_value;
wire crcnext_0;
wire crcnext_1;
wire crcnext_2;
wire crcnext_3;
wire crcnext_4;
wire crcnext_5;
wire crcnext_6;
wire crcnext_7;
wire crcnext_8;
wire crcnext_9;
wire crcnext_10;
wire crcnext_11;
wire crcnext_12;
wire crcnext_13;
wire crcnext_14;
wire crcnext_15;
reg [15:0] crc;
assign _zz_crcnext_0 = crc[0];
assign _zz_crcnext_0_1 = crc[1];
assign _zz_crc = crcnext_5;
assign _zz_crc_1 = {crcnext_4,{crcnext_3,{crcnext_2,{crcnext_1,crcnext_0}}}};
assign initial_value = 16'hffff;
assign verify_value = 16'hb001;
assign crcnext_0 = ((((((((((((((((_zz_crcnext_0 ^ _zz_crcnext_0_1) ^ crc[2]) ^ crc[3]) ^ crc[4]) ^ crc[5]) ^ crc[6]) ^ crc[7]) ^ crc[8]) ^ io_data[0]) ^ io_data[1]) ^ io_data[2]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]) ^ io_data[7]);
assign crcnext_1 = crc[9];
assign crcnext_2 = crc[10];
assign crcnext_3 = crc[11];
assign crcnext_4 = crc[12];
assign crcnext_5 = crc[13];
assign crcnext_6 = ((crc[0] ^ crc[14]) ^ io_data[0]);
assign crcnext_7 = ((((crc[0] ^ crc[1]) ^ crc[15]) ^ io_data[0]) ^ io_data[1]);
assign crcnext_8 = (((crc[1] ^ crc[2]) ^ io_data[1]) ^ io_data[2]);
assign crcnext_9 = (((crc[2] ^ crc[3]) ^ io_data[2]) ^ io_data[3]);
assign crcnext_10 = (((crc[3] ^ crc[4]) ^ io_data[3]) ^ io_data[4]);
assign crcnext_11 = (((crc[4] ^ crc[5]) ^ io_data[4]) ^ io_data[5]);
assign crcnext_12 = (((crc[5] ^ crc[6]) ^ io_data[5]) ^ io_data[6]);
assign crcnext_13 = (((crc[6] ^ crc[7]) ^ io_data[6]) ^ io_data[7]);
assign crcnext_14 = (((((((((((((crc[0] ^ crc[1]) ^ crc[2]) ^ crc[3]) ^ crc[4]) ^ crc[5]) ^ crc[6]) ^ io_data[0]) ^ io_data[1]) ^ io_data[2]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]);
assign crcnext_15 = (((((((((((((((crc[0] ^ crc[1]) ^ crc[2]) ^ crc[3]) ^ crc[4]) ^ crc[5]) ^ crc[6]) ^ crc[7]) ^ io_data[0]) ^ io_data[1]) ^ io_data[2]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]) ^ io_data[7]);
assign io_crc = crc;
assign io_crcerror = (crc != verify_value);
always @(posedge ctrlcd_clk or posedge ctrlcd_reset) begin
if(ctrlcd_reset) begin
crc <= initial_value;
end else begin
if(io_init) begin
crc <= initial_value;
end else begin
if(io_enable) begin
crc <= {crcnext_15,{crcnext_14,{crcnext_13,{crcnext_12,{crcnext_11,{crcnext_10,{crcnext_9,{crcnext_8,{crcnext_7,{crcnext_6,{_zz_crc,_zz_crc_1}}}}}}}}}}};
end
end
end
end
endmodule |
module usbcrc5 (
input [15:0] io_data,
input io_enable,
input io_init,
output [4:0] io_crc,
output io_crcerror,
input ctrlcd_clk,
input ctrlcd_reset
);
wire [15:0] _zz_initial_value;
wire [15:0] _zz_verify_value;
wire [4:0] initial_value;
wire [4:0] verify_value;
wire crcnext_0;
wire crcnext_1;
wire crcnext_2;
wire crcnext_3;
wire crcnext_4;
reg [4:0] crc;
assign _zz_initial_value = 16'hffff;
assign _zz_verify_value = 16'h0006;
assign initial_value = _zz_initial_value[4:0];
assign verify_value = _zz_verify_value[4:0];
assign crcnext_0 = (((((((((crc[3] ^ crc[4]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]) ^ io_data[7]) ^ io_data[10]) ^ io_data[11]) ^ io_data[13]);
assign crcnext_1 = ((((((((((crc[0] ^ crc[4]) ^ io_data[0]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]) ^ io_data[7]) ^ io_data[8]) ^ io_data[11]) ^ io_data[12]) ^ io_data[14]);
assign crcnext_2 = (((((((((((crc[0] ^ crc[1]) ^ io_data[0]) ^ io_data[1]) ^ io_data[5]) ^ io_data[6]) ^ io_data[7]) ^ io_data[8]) ^ io_data[9]) ^ io_data[12]) ^ io_data[13]) ^ io_data[15]);
assign crcnext_3 = ((((((((((((crc[1] ^ crc[2]) ^ crc[3]) ^ crc[4]) ^ io_data[1]) ^ io_data[2]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[8]) ^ io_data[9]) ^ io_data[11]) ^ io_data[14]);
assign crcnext_4 = (((((((((((crc[2] ^ crc[3]) ^ crc[4]) ^ io_data[2]) ^ io_data[3]) ^ io_data[4]) ^ io_data[5]) ^ io_data[6]) ^ io_data[9]) ^ io_data[10]) ^ io_data[12]) ^ io_data[15]);
assign io_crc = crc;
assign io_crcerror = (crc != verify_value);
always @(posedge ctrlcd_clk or posedge ctrlcd_reset) begin
if(ctrlcd_reset) begin
crc <= initial_value;
end else begin
if(io_init) begin
crc <= initial_value;
end else begin
if(io_enable) begin
crc <= {crcnext_4,{crcnext_3,{crcnext_2,{crcnext_1,crcnext_0}}}};
end
end
end
end
endmodule |
module buffercc_13 (
input io_datain,
output io_dataout,
input ctrlcd_clk,
input phycd_reset_synchronized
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataout = buffers_1;
always @(posedge ctrlcd_clk or posedge phycd_reset_synchronized) begin
if(phycd_reset_synchronized) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
end
endmodule |
module buffercc_12 (
input io_datain,
output io_dataout,
input ctrlcd_clk,
input phycd_reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataout = buffers_1;
always @(posedge ctrlcd_clk or posedge phycd_reset) begin
if(phycd_reset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
end
endmodule |
module buffercc_16 (
input io_datain,
output io_dataout,
input phycd_clk,
input ctrlcd_reset_synchronized
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataout = buffers_1;
always @(posedge phycd_clk or posedge ctrlcd_reset_synchronized) begin
if(ctrlcd_reset_synchronized) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
end
endmodule |
module buffercc_15 (
input io_datain,
output io_dataout,
input phycd_clk,
input ctrlcd_reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataout = buffers_1;
always @(posedge phycd_clk or posedge ctrlcd_reset) begin
if(ctrlcd_reset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
end
endmodule |
module buffercc_14 (
input io_datain,
output io_dataout,
input ctrlcd_clk,
input ctrlcd_reset
);
(* async_reg = "true" *) reg buffers_0;
(* async_reg = "true" *) reg buffers_1;
assign io_dataout = buffers_1;
always @(posedge ctrlcd_clk or posedge ctrlcd_reset) begin
if(ctrlcd_reset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_datain;
buffers_1 <= buffers_0;
end
end
endmodule |
module obi_cdc_fast_primary (
input rst_ni,
input ctrl_clk_i,
input ctrl_req_i,
output wire ctrl_gnt_o,
input [31:0] ctrl_addr_i,
input ctrl_we_i,
input [3:0] ctrl_be_i,
input [31:0] ctrl_wdata_i,
output wire ctrl_rvalid_o,
output reg [31:0] ctrl_rdata_o,
input secondary_clk_i,
output wire secondary_req_o,
input secondary_gnt_i,
output wire [31:0] secondary_addr_o,
output wire secondary_we_o,
output wire [3:0] secondary_be_o,
output wire [31:0] secondary_wdata_o,
input secondary_rvalid_i,
input [31:0] secondary_rdata_i
);
reg gnt_in_flight,
req_ff1, req_ff2,
rvalid_buff, rvalid_ff1, rvalid_ff2, rvalid_ff3,
gnt_ack, gnt_ack_ff1, gnt_ack_ff2, gnt_ack_ff3,
gnt_ff1, gnt_ff2, gnt_ff3,
rst_n_ctrl_ff1, rst_n_ctrl_ff2,
rst_n_secondary_ff1, rst_n_secondary_ff2;
reg [31:0] rdata_buff;
always @(posedge secondary_clk_i) begin
if ((gnt_ack_ff2 && !gnt_ack_ff3) || !rst_n_secondary_ff2)
gnt_in_flight <= 'b0;
else if (req_ff2 && secondary_gnt_i && !gnt_in_flight)
gnt_in_flight <= 'b1;
end
always @(posedge ctrl_clk_i or negedge gnt_in_flight) begin
if(!gnt_in_flight)
gnt_ack <= 'b0;
else if(!rst_n_ctrl_ff2)
gnt_ack <= 'b0;
else if(gnt_ff2 && !gnt_ff3)
gnt_ack <= 'b1;
end
always @(posedge secondary_clk_i) begin
if (!rst_n_secondary_ff2) begin
gnt_ack_ff1 <= 'b0;
gnt_ack_ff2 <= 'b0;
gnt_ack_ff3 <= 'b0;
end else begin
gnt_ack_ff3 <= gnt_ack_ff2;
gnt_ack_ff2 <= gnt_ack_ff1;
gnt_ack_ff1 <= gnt_ack;
end
end
assign secondary_addr_o = ctrl_addr_i;
assign secondary_we_o = ctrl_we_i;
assign secondary_be_o = ctrl_be_i;
assign secondary_wdata_o = ctrl_wdata_i;
assign secondary_req_o = req_ff2 && !gnt_in_flight;
always @(posedge secondary_clk_i) begin
if (!rst_n_secondary_ff2) begin
req_ff2 <= 'b0;
req_ff1 <= 'b0;
end else begin
req_ff2 <= req_ff1;
req_ff1 <= ctrl_req_i;
end
end
assign ctrl_gnt_o = gnt_ff2 && !gnt_ff3;
assign ctrl_rvalid_o = rvalid_ff3;
always @(posedge secondary_clk_i) begin
if (secondary_rvalid_i) begin
rdata_buff <= secondary_rdata_i;
end
rvalid_buff <= secondary_rvalid_i;
end
always @(posedge ctrl_clk_i) begin
if (!rst_n_ctrl_ff2) begin
gnt_ff3 <= 'b0;
gnt_ff2 <= 'b0;
gnt_ff1 <= 'b0;
rvalid_ff1 <= 'b0;
ctrl_rdata_o <= 'b0;
end else begin
gnt_ff3 <= gnt_ff2;
gnt_ff2 <= gnt_ff1;
gnt_ff1 <= gnt_in_flight;
rvalid_ff3 <= rvalid_ff2;
rvalid_ff2 <= rvalid_ff1;
rvalid_ff1 <= rvalid_buff;
if (rvalid_ff2 && !rvalid_ff3)
ctrl_rdata_o <= rdata_buff;
end
end
always @(posedge ctrl_clk_i) begin
if (!rst_ni) begin
rst_n_ctrl_ff2 <= 'b0;
rst_n_ctrl_ff1 <= 'b0;
end else begin
rst_n_ctrl_ff2 <= rst_n_ctrl_ff1;
rst_n_ctrl_ff1 <= 'b1;
end
end
always @(posedge secondary_clk_i) begin
if (!rst_ni) begin
rst_n_secondary_ff2 <= 'b0;
rst_n_secondary_ff1 <= 'b0;
end else begin
rst_n_secondary_ff2 <= rst_n_secondary_ff1;
rst_n_secondary_ff1 <= 'b1;
end
end
endmodule |
module obi_demux_1_to_2 #(
parameter port1_base_addr = 32'h00001000,
parameter port1_end_addr = 32'h00001fff,
parameter port2_base_addr = 32'h80000000,
parameter port2_end_addr = 32'h8000ffff)
(
input clk_i,
input rst_ni,
input ctrl_req_i,
output reg ctrl_gnt_o,
input [31:0] ctrl_addr_i,
input ctrl_we_i,
input [3:0] ctrl_be_i,
input [31:0] ctrl_wdata_i,
output reg ctrl_rvalid_o,
output reg [31:0] ctrl_rdata_o,
output reg port1_req_o,
input port1_gnt_i,
output wire [31:0] port1_addr_o,
output wire port1_we_o,
output wire [3:0] port1_be_o,
output wire [31:0] port1_wdata_o,
input port1_rvalid_i,
input [31:0] port1_rdata_i,
output reg port2_req_o,
input port2_gnt_i,
output wire [31:0] port2_addr_o,
output wire port2_we_o,
output wire [3:0] port2_be_o,
output wire [31:0] port2_wdata_o,
input port2_rvalid_i,
input [31:0] port2_rdata_i,
output wire illegal_access_o
);
reg [1:0] addr_sel, resp_sel;
always @(*) begin
if ((ctrl_addr_i >= port1_base_addr) && (ctrl_addr_i <= port1_end_addr))
addr_sel = 1;
else if ((ctrl_addr_i >= port2_base_addr) && (ctrl_addr_i <= port2_end_addr))
addr_sel = 2;
else
addr_sel = 0;
end
always @(*) begin
case (addr_sel)
1: ctrl_gnt_o = port1_gnt_i;
2: ctrl_gnt_o = port2_gnt_i;
default: ctrl_gnt_o = 1; endcase
end
always @(*) begin
port1_req_o = (addr_sel == 1) ? ctrl_req_i : 1'b0;
port2_req_o = (addr_sel == 2) ? ctrl_req_i : 1'b0;
end
assign port1_addr_o = ctrl_addr_i;
assign port1_wdata_o = ctrl_wdata_i;
assign port1_be_o = ctrl_be_i;
assign port1_we_o = ctrl_we_i;
assign port2_addr_o = ctrl_addr_i;
assign port2_wdata_o = ctrl_wdata_i;
assign port2_be_o = ctrl_be_i;
assign port2_we_o = ctrl_we_i;
wire accepted;
assign accepted = ctrl_req_i && ctrl_gnt_o && !ctrl_we_i;
always @(posedge clk_i) begin
if (!rst_ni)
resp_sel <= 0;
else if (accepted) begin
resp_sel <= addr_sel;
end
end
always @(*) begin
case (resp_sel)
1: ctrl_rvalid_o = port1_rvalid_i;
2: ctrl_rvalid_o = port2_rvalid_i;
default: ctrl_rvalid_o = 1; endcase
end
always @(*) begin
case (resp_sel)
1: ctrl_rdata_o = port1_rdata_i;
2: ctrl_rdata_o = port2_rdata_i;
default: ctrl_rdata_o = 32'hdead_beef; endcase
end
assign illegal_access_o = (addr_sel == 0) && ctrl_req_i;
endmodule |
module obi_demux_1_to_4 #(
parameter port1_base_addr = 32'h00001000,
parameter port1_end_addr = 32'h00001fff,
parameter port2_base_addr = 32'h80000000,
parameter port2_end_addr = 32'h8000ffff,
parameter port3_base_addr = 32'h20000000,
parameter port3_end_addr = 32'h3fffffff,
parameter port4_base_addr = 32'h10000000,
parameter port4_end_addr = 32'h10001fff )
(
input clk_i,
input rst_ni,
input ctrl_req_i,
output reg ctrl_gnt_o,
input [31:0] ctrl_addr_i,
input ctrl_we_i,
input [3:0] ctrl_be_i,
input [31:0] ctrl_wdata_i,
output reg ctrl_rvalid_o,
output reg [31:0] ctrl_rdata_o,
output reg port1_req_o,
input port1_gnt_i,
output wire [31:0] port1_addr_o,
output wire port1_we_o,
output wire [3:0] port1_be_o,
output wire [31:0] port1_wdata_o,
input port1_rvalid_i,
input [31:0] port1_rdata_i,
output reg port2_req_o,
input port2_gnt_i,
output wire [31:0] port2_addr_o,
output wire port2_we_o,
output wire [3:0] port2_be_o,
output wire [31:0] port2_wdata_o,
input port2_rvalid_i,
input [31:0] port2_rdata_i,
output reg port3_req_o,
input port3_gnt_i,
output wire [31:0] port3_addr_o,
output wire port3_we_o,
output wire [3:0] port3_be_o,
output wire [31:0] port3_wdata_o,
input port3_rvalid_i,
input [31:0] port3_rdata_i,
output reg port4_req_o,
input port4_gnt_i,
output wire [31:0] port4_addr_o,
output wire port4_we_o,
output wire [3:0] port4_be_o,
output wire [31:0] port4_wdata_o,
input port4_rvalid_i,
input [31:0] port4_rdata_i,
output wire illegal_access_o
);
reg[2:0] addr_sel, resp_sel;
always @(*) begin
if ((ctrl_addr_i >= port1_base_addr) && (ctrl_addr_i <= port1_end_addr))
addr_sel = 1;
else if ((ctrl_addr_i >= port2_base_addr) && (ctrl_addr_i <= port2_end_addr))
addr_sel = 2;
else if ((ctrl_addr_i >= port3_base_addr) && (ctrl_addr_i <= port3_end_addr))
addr_sel = 3;
else if ((ctrl_addr_i >= port4_base_addr) && (ctrl_addr_i <= port4_end_addr))
addr_sel = 4;
else
addr_sel = 0;
end
always @(*) begin
case (addr_sel)
1: ctrl_gnt_o = port1_gnt_i;
2: ctrl_gnt_o = port2_gnt_i;
3: ctrl_gnt_o = port3_gnt_i;
4: ctrl_gnt_o = port4_gnt_i;
default: ctrl_gnt_o = 1; endcase
end
always @(*) begin
port1_req_o = (addr_sel == 1) ? ctrl_req_i : 1'b0;
port2_req_o = (addr_sel == 2) ? ctrl_req_i : 1'b0;
port3_req_o = (addr_sel == 3) ? ctrl_req_i : 1'b0;
port4_req_o = (addr_sel == 4) ? ctrl_req_i : 1'b0;
end
assign port1_addr_o = ctrl_addr_i;
assign port1_wdata_o = ctrl_wdata_i;
assign port1_be_o = ctrl_be_i;
assign port1_we_o = ctrl_we_i;
assign port2_addr_o = ctrl_addr_i;
assign port2_wdata_o = ctrl_wdata_i;
assign port2_be_o = ctrl_be_i;
assign port2_we_o = ctrl_we_i;
assign port3_addr_o = ctrl_addr_i;
assign port3_wdata_o = ctrl_wdata_i;
assign port3_be_o = ctrl_be_i;
assign port3_we_o = ctrl_we_i;
assign port4_addr_o = ctrl_addr_i;
assign port4_wdata_o = ctrl_wdata_i;
assign port4_be_o = ctrl_be_i;
assign port4_we_o = ctrl_we_i;
wire accepted;
assign accepted = ctrl_req_i && ctrl_gnt_o && !ctrl_we_i;
always @(posedge clk_i) begin
if (!rst_ni)
resp_sel <= 0;
else if (accepted) begin
resp_sel <= addr_sel;
end
end
always @(*) begin
case (resp_sel)
1: ctrl_rvalid_o = port1_rvalid_i;
2: ctrl_rvalid_o = port2_rvalid_i;
3: ctrl_rvalid_o = port3_rvalid_i;
4: ctrl_rvalid_o = port4_rvalid_i;
default: ctrl_rvalid_o = 1; endcase
end
always @(*) begin
case (resp_sel)
1: ctrl_rdata_o = port1_rdata_i;
2: ctrl_rdata_o = port2_rdata_i;
3: ctrl_rdata_o = port3_rdata_i;
4: ctrl_rdata_o = port4_rdata_i;
default: ctrl_rdata_o = 32'hdead_beef; endcase
end
assign illegal_access_o = (addr_sel == 0) && ctrl_req_i;
endmodule |
module obi_mux_fp_2_to_1 (
input clk_i,
input rst_ni,
input pri_req_i,
output wire pri_gnt_o,
input [31:0] pri_addr_i,
input pri_we_i,
input [3:0] pri_be_i,
input [31:0] pri_wdata_i,
output wire pri_rvalid_o,
output wire [31:0] pri_rdata_o,
input sec_req_i,
output wire sec_gnt_o,
input [31:0] sec_addr_i,
input sec_we_i,
input [3:0] sec_be_i,
input [31:0] sec_wdata_i,
output wire sec_rvalid_o,
output wire [31:0] sec_rdata_o,
output wire shr_req_o,
input shr_gnt_i,
output wire [31:0] shr_addr_o,
output wire shr_we_o,
output wire [3:0] shr_be_o,
output wire [31:0] shr_wdata_o,
input shr_rvalid_i,
input [31:0] shr_rdata_i
);
wire pri_accepted, sec_accepted;
wire sec_posession, gnt_masked, available;
assign sec_posession = ~pri_req_i;
assign available = shr_rvalid_i || !(pri_read_outstanding || sec_read_outstanding) ;
assign gnt_masked = shr_gnt_i && available;
assign pri_accepted = pri_req_i && pri_gnt_o && !pri_we_i;
assign sec_accepted = sec_req_i && sec_gnt_o && !sec_we_i;
assign sec_gnt_o = (sec_posession ? gnt_masked : 0);
assign pri_gnt_o = (sec_posession ? 0 : gnt_masked);
assign shr_req_o = sec_posession ? sec_req_i : pri_req_i ;
assign shr_addr_o = sec_posession ? sec_addr_i : pri_addr_i ;
assign shr_we_o = sec_posession ? sec_we_i : pri_we_i ;
assign shr_be_o = sec_posession ? sec_be_i : pri_be_i ;
assign shr_wdata_o = sec_posession ? sec_wdata_i : pri_wdata_i ;
reg pri_read_outstanding, sec_read_outstanding;
assign sec_rvalid_o = sec_read_outstanding ? shr_rvalid_i : 0;
assign sec_rdata_o = sec_read_outstanding ? shr_rdata_i : 0;
assign pri_rvalid_o = pri_read_outstanding ? shr_rvalid_i : 0;
assign pri_rdata_o = pri_read_outstanding ? shr_rdata_i : 0;
always @(posedge clk_i) begin
if (!rst_ni) begin
pri_read_outstanding <= 0;
sec_read_outstanding <= 0;
end else if (available) begin
pri_read_outstanding <= pri_accepted;
sec_read_outstanding <= sec_accepted;
end
end
endmodule |
module obi_mux_fp_3_to_1 (
input clk_i,
input rst_ni,
input pri_req_i,
output wire pri_gnt_o,
input [31:0] pri_addr_i,
input pri_we_i,
input [3:0] pri_be_i,
input [31:0] pri_wdata_i,
output wire pri_rvalid_o,
output wire [31:0] pri_rdata_o,
input sec_req_i,
output wire sec_gnt_o,
input [31:0] sec_addr_i,
input sec_we_i,
input [3:0] sec_be_i,
input [31:0] sec_wdata_i,
output wire sec_rvalid_o,
output wire [31:0] sec_rdata_o,
input ter_req_i,
output wire ter_gnt_o,
input [31:0] ter_addr_i,
input ter_we_i,
input [3:0] ter_be_i,
input [31:0] ter_wdata_i,
output wire ter_rvalid_o,
output wire [31:0] ter_rdata_o,
output wire shr_req_o,
input shr_gnt_i,
output wire [31:0] shr_addr_o,
output wire shr_we_o,
output wire [3:0] shr_be_o,
output wire [31:0] shr_wdata_o,
input shr_rvalid_i,
input [31:0] shr_rdata_i
);
wire pri_accepted, sec_accepted, ter_accepted;
wire sec_posession, ter_posession, gnt_masked, available;
assign sec_posession = ~pri_req_i;
assign ter_posession = ~pri_req_i && ~sec_req_i;
assign available = shr_rvalid_i || !(pri_read_outstanding || sec_read_outstanding || ter_read_outstanding) ;
assign gnt_masked = shr_gnt_i && available;
assign pri_accepted = pri_req_i && pri_gnt_o && !pri_we_i;
assign sec_accepted = sec_req_i && sec_gnt_o && !sec_we_i;
assign ter_accepted = ter_req_i && ter_gnt_o && !ter_we_i;
assign sec_gnt_o = (sec_posession ? gnt_masked : 0);
assign ter_gnt_o = (ter_posession ? gnt_masked : 0);
assign pri_gnt_o = (sec_posession || ter_posession ? 0 : gnt_masked);
assign shr_req_o = ter_posession ? ter_req_i : (sec_posession ? sec_req_i : pri_req_i) ;
assign shr_addr_o = ter_posession ? ter_addr_i : (sec_posession ? sec_addr_i : pri_addr_i) ;
assign shr_we_o = ter_posession ? ter_we_i : (sec_posession ? sec_we_i : pri_we_i) ;
assign shr_be_o = ter_posession ? ter_be_i : (sec_posession ? sec_be_i : pri_be_i) ;
assign shr_wdata_o = ter_posession ? ter_wdata_i : (sec_posession ? sec_wdata_i : pri_wdata_i) ;
reg pri_read_outstanding, sec_read_outstanding, ter_read_outstanding;
assign sec_rvalid_o = sec_read_outstanding ? shr_rvalid_i : 0;
assign sec_rdata_o = sec_read_outstanding ? shr_rdata_i : 0;
assign pri_rvalid_o = pri_read_outstanding ? shr_rvalid_i : 0;
assign pri_rdata_o = pri_read_outstanding ? shr_rdata_i : 0;
assign ter_rvalid_o = ter_read_outstanding ? shr_rvalid_i : 0;
assign ter_rdata_o = ter_read_outstanding ? shr_rdata_i : 0;
always @(posedge clk_i) begin
if (!rst_ni) begin
pri_read_outstanding <= 0;
sec_read_outstanding <= 0;
ter_read_outstanding <= 0;
end else if (available) begin
pri_read_outstanding <= pri_accepted;
sec_read_outstanding <= sec_accepted;
ter_read_outstanding <= ter_accepted;
end
end
endmodule |
module wb_to_obi (
input clk_i,
input wb_rst_i, input wbs_stb_i,
input wbs_cyc_i, input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wire wbs_ack_o,
output wire [31:0] wbs_dat_o,
output wire req_o,
input gnt_i,
output wire [31:0] addr_o,
output wire we_o,
output wire [3:0] be_o,
output wire [31:0] wdata_o,
input rvalid_i,
input [31:0] rdata_i
);
reg read_outstanding, write_completed;
wire read_accepted_a, write_accepted_a;
assign read_accepted_a = (req_o && gnt_i) && !wbs_we_i;
assign write_accepted_a = (req_o && gnt_i) && wbs_we_i;
always @(posedge clk_i) begin
if (wb_rst_i)
read_outstanding <= 'b0;
else begin
if (read_outstanding && (rvalid_i && !read_accepted_a))
read_outstanding <= 'b0;
if (!read_outstanding && read_accepted_a)
read_outstanding <= 'b1;
end
end
always @(posedge clk_i) begin
write_completed <= write_accepted_a;
end
assign req_o = wbs_stb_i && !read_outstanding;
assign addr_o = wbs_adr_i;
assign we_o = wbs_we_i;
assign be_o = wbs_sel_i;
assign wdata_o = wbs_dat_i;
assign wbs_dat_o = rdata_i;
assign wbs_ack_o = write_completed || (read_outstanding && rvalid_i);
`ifdef verilator
wire _unused;
assign _unused = wbs_cyc_i;
`endif
endmodule |
module logo_svg ();
endmodule |
module test_sys_ctrl (
input pclk,
input presetn,
input psel,
input penable,
input pwrite,
input [31:0] paddr,
input [31:0] pwdata,
output reg [31:0] prdata,
output reg pready,
output reg pslverr
,output reg[0:0] sys_ctrl0_pdc_use_arm_ctrl
,output reg[2:0] sys_ctrl0_l2c_strip_mode
,output reg[4:0] sys_ctrl0_smmu_mmusid
,output reg[0:0] sys_ctrl0_mem_repair_en
,output reg[6:0] sys_ctrl0_mem_repair_done
,output reg[3:0] test_reg_test_field0
,output reg[1:0] test_reg_test_filed1
);
endmodule |
module image_write(input clk, input [7:0] r,g,b);
parameter width = 512, height = 512;
parameter length = width*height*3;
integer fd;
integer count;
initial begin
fd = $fopen("mlam_out.txt","w");
count = 0;
end
always @(posedge clk) begin
#1;
$fwriteh(fd, r);
$fwrite(fd,"\n");
$fwriteh(fd, g);
$fwrite(fd,"\n");
$fwriteh(fd, b);
$fwrite(fd,"\n");
count = count + 3;
if(count == length) begin
$fclose(fd);
$finish;
end
end
endmodule |
module majority(a,b,c,out);
input a,b,c;
output out;
assign out = a&b | b&c | c&a;
endmodule |
module image_write(input clk, input [7:0] r,g,b);
parameter width = 512, height = 512;
parameter length = width*height*3;
integer fd;
integer count;
initial begin
fd = $fopen("mlam2_out.txt","w");
count = 0;
end
always @(posedge clk) begin
#1;
$fwriteh(fd, r);
$fwrite(fd,"\n");
$fwriteh(fd, g);
$fwrite(fd,"\n");
$fwriteh(fd, b);
$fwrite(fd,"\n");
count = count + 3;
if(count == length) begin
$fclose(fd);
$finish;
end
end
endmodule |
module image_write(input clk, input [7:0] r,g,b);
parameter width = 512, height = 512;
parameter length = width*height*3;
integer fd;
integer count;
initial begin
fd = $fopen("mlam3_out.txt","w");
count = 0;
end
always @(posedge clk) begin
#1;
$fwriteh(fd, r);
$fwrite(fd,"\n");
$fwriteh(fd, g);
$fwrite(fd,"\n");
$fwriteh(fd, b);
$fwrite(fd,"\n");
count = count + 3;
if(count == length) begin
$fclose(fd);
$finish;
end
end
endmodule |
module image_write(input clk, input [7:0] r,g,b);
parameter width = 512, height = 512;
parameter length = width*height*3;
integer fd;
integer count;
initial begin
fd = $fopen("mlam4_out.txt","w");
count = 0;
end
always @(posedge clk) begin
#1;
$fwriteh(fd, r);
$fwrite(fd,"\n");
$fwriteh(fd, g);
$fwrite(fd,"\n");
$fwriteh(fd, b);
$fwrite(fd,"\n");
count = count + 3;
if(count == length) begin
$fclose(fd);
$finish;
end
end
endmodule |
module image_write(input clk, input [7:0] r);
parameter width = 512, height = 512;
parameter length = width*height;
integer fd;
integer count;
initial begin
fd = $fopen("mlafa_3333_3333_lenna_grey.txt","w");
count = 0;
end
always @(posedge clk) begin
#1;
$fwriteh(fd, r);
$fwrite(fd,"\n");
count = count + 1;
if(count == length) begin
$fclose(fd);
$finish;
end
end
endmodule |
module majority(a,b,c,out);
input a,b,c;
output reg out;
always @(*)
out <= a&b | b&c | c&a;
endmodule |
module collision
(
output [5:0] out,
input [5:0] in,
input rnd
);
wire a, b, c, d, e, f, ad, be, cf, triple, no_rnd;
wire cha, chb, chc, chd, che, chf;
wire aout, bout, cout, dout, eout, fout;
assign a = in[0];
assign b = in[1];
assign c = in[2];
assign d = in[3];
assign e = in[4];
assign f = in[5];
assign ad = ( (a & d) & (~(b | c | e | f)) );
assign be = ( (b & e) & (~(a | c | d | f)) );
assign cf = ( (c & f) & (~(a | b | d | e)) );
assign triple = ( (a ^ b) & (b ^ c) & (c ^ d) & (d ^ e) & (e ^ f) );
assign no_rnd = ~rnd;
assign cha = (ad | triple | (rnd & be) | (no_rnd & cf));
assign chb = (be | triple | (rnd & cf) | (no_rnd & ad));
assign chc = (cf | triple | (rnd & ad) | (no_rnd & be));
assign chd = cha;
assign che = chb;
assign chf = chc;
assign aout = a ^ cha;
assign bout = b ^ chb;
assign cout = c ^ chc;
assign dout = d ^ chd;
assign eout = e ^ che;
assign fout = f ^ chf;
assign out = {fout, eout, dout, cout, bout, aout};
endmodule |
module m10k_1000_8(
output reg [7:0] q,
input [7:0] d,
input [18:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [307200:0] ;
always @ (posedge clk) begin
if (we) begin
mem[write_address] <= d;
end
q <= mem[read_address]; end
endmodule |
module mem
#(
parameter addr_nbits = 9,
parameter data_nbits = 12,
parameter mem_size = 480
)(
output reg [data_nbits-1:0] read_data,
input [data_nbits-1:0] write_data,
input [addr_nbits-1:0] write_address, read_address,
input write_enable, clk
);
reg [data_nbits-1:0] mem [mem_size-1:0] ;
always @ (posedge clk) begin
if (write_enable) begin
mem[write_address] <= write_data;
end
read_data <= mem[read_address];
end
endmodule |
module propagation
(
output [5:0] out,
input [5:0] l_up, l_n, l_down, r_up, r_n, r_down, n,
input [3:0] wall
);
wire a, b, c, d, e, f;
wire a_in, b_in, c_in, d_in, e_in, f_in;
wire w_u, w_d, w_l, w_r;
wire nw_u, nw_d, nw_l, nw_r;
wire aout, bout, cout, dout, eout, fout;
assign a = n[0];
assign b = n[1];
assign c = n[2];
assign d = n[3];
assign e = n[4];
assign f = n[5];
assign a_in = r_down[0];
assign b_in = r_n [1];
assign c_in = r_up [2];
assign d_in = l_up [3];
assign e_in = l_n [4];
assign f_in = l_down[5];
assign w_u = wall[3];
assign w_d = wall[2];
assign w_l = wall[1];
assign w_r = wall[0];
assign nw_u = (~w_u);
assign nw_d = (~w_d);
assign nw_l = (~w_l);
assign nw_r = (~w_r);
assign aout = (((nw_r & nw_d) & a_in) | (w_d & c) | (w_r & f));
assign dout = (((nw_l & nw_u) & d_in) | (w_u & f) | (w_l & c));
assign bout = ((nw_r & b_in) | (w_r & e));
assign eout = ((nw_l & e_in) | (w_l & b));
assign cout = (((nw_r & nw_u) & c_in) | (w_u & a) | (w_r & d));
assign fout = (((nw_l & nw_d) & f_in) | (w_d & d) | (w_l & a));
assign out = {fout, eout, dout, cout, bout, aout};
endmodule |
module rand63(rand_out, seed_in, clk, rst);
output wire [15:0] rand_out ;
input wire clk, rst ;
input wire [63:1] seed_in;
reg [4:1] sr1, sr2, sr3, sr4, sr5, sr6, sr7, sr8,
sr9, sr10, sr11, sr12, sr13, sr14, sr15, sr16;
assign rand_out = {sr1[3], sr2[3], sr3[3], sr4[3],
sr5[3], sr6[3], sr7[3], sr8[3],
sr9[3], sr10[3], sr11[3], sr12[3],
sr13[3], sr14[3], sr15[3], sr16[3]} ;
always @ (posedge clk) begin
if (rst)
begin
sr1 <= seed_in[4:1] ;
sr2 <= seed_in[8:5] ;
sr3 <= seed_in[12:9] ;
sr4 <= seed_in[16:13] ;
sr5 <= seed_in[20:17] ;
sr6 <= seed_in[24:21] ;
sr7 <= seed_in[28:25] ;
sr8 <= seed_in[32:29] ;
sr9 <= seed_in[36:33] ;
sr10 <= seed_in[40:37] ;
sr11 <= seed_in[44:41] ;
sr12 <= seed_in[48:45] ;
sr13 <= seed_in[52:49] ;
sr14 <= seed_in[56:53] ;
sr15 <= seed_in[60:57] ;
sr16 <= {1'b0,seed_in[63:61]} ;
end
else
begin
sr1 <= {sr1[3:1], sr16[3]^sr15[3]} ;
sr2 <= {sr2[3:1], sr16[3]^sr1[4]} ;
sr3 <= {sr3[3:1], sr1[4]^sr2[4]} ;
sr4 <= {sr4[3:1], sr2[4]^sr3[4]} ;
sr5 <= {sr5[3:1], sr3[4]^sr4[4]} ;
sr6 <= {sr6[3:1], sr4[4]^sr5[4]} ;
sr7 <= {sr7[3:1], sr5[4]^sr6[4]} ;
sr8 <= {sr8[3:1], sr6[4]^sr7[4]} ;
sr9 <= {sr9[3:1], sr7[4]^sr8[4]} ;
sr10 <= {sr10[3:1], sr8[4]^sr9[4]} ;
sr11 <= {sr11[3:1], sr9[4]^sr10[4]} ;
sr12 <= {sr12[3:1], sr10[4]^sr11[4]} ;
sr13 <= {sr13[3:1], sr11[4]^sr12[4]} ;
sr14 <= {sr14[3:1], sr12[4]^sr13[4]} ;
sr15 <= {sr15[3:1], sr13[4]^sr14[4]} ;
sr16 <= {sr16[3:1], sr14[4]^sr15[4]} ;
end
end
endmodule |
module computer_system (
hps_io_hps_io_emac1_inst_tx_clk,
hps_io_hps_io_emac1_inst_txd0,
hps_io_hps_io_emac1_inst_txd1,
hps_io_hps_io_emac1_inst_txd2,
hps_io_hps_io_emac1_inst_txd3,
hps_io_hps_io_emac1_inst_rxd0,
hps_io_hps_io_emac1_inst_mdio,
hps_io_hps_io_emac1_inst_mdc,
hps_io_hps_io_emac1_inst_rx_ctl,
hps_io_hps_io_emac1_inst_tx_ctl,
hps_io_hps_io_emac1_inst_rx_clk,
hps_io_hps_io_emac1_inst_rxd1,
hps_io_hps_io_emac1_inst_rxd2,
hps_io_hps_io_emac1_inst_rxd3,
hps_io_hps_io_qspi_inst_io0,
hps_io_hps_io_qspi_inst_io1,
hps_io_hps_io_qspi_inst_io2,
hps_io_hps_io_qspi_inst_io3,
hps_io_hps_io_qspi_inst_ss0,
hps_io_hps_io_qspi_inst_clk,
hps_io_hps_io_sdio_inst_cmd,
hps_io_hps_io_sdio_inst_d0,
hps_io_hps_io_sdio_inst_d1,
hps_io_hps_io_sdio_inst_clk,
hps_io_hps_io_sdio_inst_d2,
hps_io_hps_io_sdio_inst_d3,
hps_io_hps_io_usb1_inst_d0,
hps_io_hps_io_usb1_inst_d1,
hps_io_hps_io_usb1_inst_d2,
hps_io_hps_io_usb1_inst_d3,
hps_io_hps_io_usb1_inst_d4,
hps_io_hps_io_usb1_inst_d5,
hps_io_hps_io_usb1_inst_d6,
hps_io_hps_io_usb1_inst_d7,
hps_io_hps_io_usb1_inst_clk,
hps_io_hps_io_usb1_inst_stp,
hps_io_hps_io_usb1_inst_dir,
hps_io_hps_io_usb1_inst_nxt,
hps_io_hps_io_spim1_inst_clk,
hps_io_hps_io_spim1_inst_mosi,
hps_io_hps_io_spim1_inst_miso,
hps_io_hps_io_spim1_inst_ss0,
hps_io_hps_io_uart0_inst_rx,
hps_io_hps_io_uart0_inst_tx,
hps_io_hps_io_i2c0_inst_sda,
hps_io_hps_io_i2c0_inst_scl,
hps_io_hps_io_i2c1_inst_sda,
hps_io_hps_io_i2c1_inst_scl,
hps_io_hps_io_gpio_inst_gpio09,
hps_io_hps_io_gpio_inst_gpio35,
hps_io_hps_io_gpio_inst_gpio40,
hps_io_hps_io_gpio_inst_gpio41,
hps_io_hps_io_gpio_inst_gpio48,
hps_io_hps_io_gpio_inst_gpio53,
hps_io_hps_io_gpio_inst_gpio54,
hps_io_hps_io_gpio_inst_gpio61,
m10k_pll_locked_export,
m10k_pll_outclk0_clk,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
system_pll_ref_clk_clk,
system_pll_ref_reset_reset,
vga_pio_locked_export,
vga_pio_outclk0_clk);
output hps_io_hps_io_emac1_inst_tx_clk;
output hps_io_hps_io_emac1_inst_txd0;
output hps_io_hps_io_emac1_inst_txd1;
output hps_io_hps_io_emac1_inst_txd2;
output hps_io_hps_io_emac1_inst_txd3;
input hps_io_hps_io_emac1_inst_rxd0;
inout hps_io_hps_io_emac1_inst_mdio;
output hps_io_hps_io_emac1_inst_mdc;
input hps_io_hps_io_emac1_inst_rx_ctl;
output hps_io_hps_io_emac1_inst_tx_ctl;
input hps_io_hps_io_emac1_inst_rx_clk;
input hps_io_hps_io_emac1_inst_rxd1;
input hps_io_hps_io_emac1_inst_rxd2;
input hps_io_hps_io_emac1_inst_rxd3;
inout hps_io_hps_io_qspi_inst_io0;
inout hps_io_hps_io_qspi_inst_io1;
inout hps_io_hps_io_qspi_inst_io2;
inout hps_io_hps_io_qspi_inst_io3;
output hps_io_hps_io_qspi_inst_ss0;
output hps_io_hps_io_qspi_inst_clk;
inout hps_io_hps_io_sdio_inst_cmd;
inout hps_io_hps_io_sdio_inst_d0;
inout hps_io_hps_io_sdio_inst_d1;
output hps_io_hps_io_sdio_inst_clk;
inout hps_io_hps_io_sdio_inst_d2;
inout hps_io_hps_io_sdio_inst_d3;
inout hps_io_hps_io_usb1_inst_d0;
inout hps_io_hps_io_usb1_inst_d1;
inout hps_io_hps_io_usb1_inst_d2;
inout hps_io_hps_io_usb1_inst_d3;
inout hps_io_hps_io_usb1_inst_d4;
inout hps_io_hps_io_usb1_inst_d5;
inout hps_io_hps_io_usb1_inst_d6;
inout hps_io_hps_io_usb1_inst_d7;
input hps_io_hps_io_usb1_inst_clk;
output hps_io_hps_io_usb1_inst_stp;
input hps_io_hps_io_usb1_inst_dir;
input hps_io_hps_io_usb1_inst_nxt;
output hps_io_hps_io_spim1_inst_clk;
output hps_io_hps_io_spim1_inst_mosi;
input hps_io_hps_io_spim1_inst_miso;
output hps_io_hps_io_spim1_inst_ss0;
input hps_io_hps_io_uart0_inst_rx;
output hps_io_hps_io_uart0_inst_tx;
inout hps_io_hps_io_i2c0_inst_sda;
inout hps_io_hps_io_i2c0_inst_scl;
inout hps_io_hps_io_i2c1_inst_sda;
inout hps_io_hps_io_i2c1_inst_scl;
inout hps_io_hps_io_gpio_inst_gpio09;
inout hps_io_hps_io_gpio_inst_gpio35;
inout hps_io_hps_io_gpio_inst_gpio40;
inout hps_io_hps_io_gpio_inst_gpio41;
inout hps_io_hps_io_gpio_inst_gpio48;
inout hps_io_hps_io_gpio_inst_gpio53;
inout hps_io_hps_io_gpio_inst_gpio54;
inout hps_io_hps_io_gpio_inst_gpio61;
output m10k_pll_locked_export;
output m10k_pll_outclk0_clk;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input system_pll_ref_clk_clk;
input system_pll_ref_reset_reset;
output vga_pio_locked_export;
output vga_pio_outclk0_clk;
endmodule |
module computer_system_parallel_port_in_axi (
clk,
reset,
address,
byteenable,
chipselect,
read,
write,
writedata,
in_port,
readdata
);
parameter dw = 31;
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input read;
input write;
input [31: 0] writedata;
input [dw: 0] in_port;
output reg [31: 0] readdata;
reg [31: 0] data;
reg [dw: 0] data_in;
genvar i;
always @(posedge clk)
begin
data_in <= in_port;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 2'h0)
readdata <= {{(31-dw){1'b0}}, data_in};
else
readdata <= 32'h00000000;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data <= {(dw + 1){1'b0}};
else if ((chipselect == 1'b1) &&
(write == 1'b1) &&
(address == 2'h0))
begin
if (byteenable[0])
data[ 7: 0] <= writedata[ 7: 0];
if (byteenable[1])
data[15: 8] <= writedata[15: 8];
if (byteenable[2])
data[23:16] <= writedata[23:16];
if (byteenable[3])
data[31:24] <= writedata[31:24];
end
end
endmodule |
module computer_system (
audio_adcdat,
audio_adclrck,
audio_bclk,
audio_dacdat,
audio_daclrck,
audio_pll_ref_clk_clk,
audio_pll_ref_reset_reset,
av_config_sdat,
av_config_sclk,
clock_bridge_0_in_clk_clk,
ebab_video_in_external_interface_address,
ebab_video_in_external_interface_byte_enable,
ebab_video_in_external_interface_read,
ebab_video_in_external_interface_write,
ebab_video_in_external_interface_write_data,
ebab_video_in_external_interface_acknowledge,
ebab_video_in_external_interface_read_data,
hex3_hex0_export,
hps_io_hps_io_emac1_inst_tx_clk,
hps_io_hps_io_emac1_inst_txd0,
hps_io_hps_io_emac1_inst_txd1,
hps_io_hps_io_emac1_inst_txd2,
hps_io_hps_io_emac1_inst_txd3,
hps_io_hps_io_emac1_inst_rxd0,
hps_io_hps_io_emac1_inst_mdio,
hps_io_hps_io_emac1_inst_mdc,
hps_io_hps_io_emac1_inst_rx_ctl,
hps_io_hps_io_emac1_inst_tx_ctl,
hps_io_hps_io_emac1_inst_rx_clk,
hps_io_hps_io_emac1_inst_rxd1,
hps_io_hps_io_emac1_inst_rxd2,
hps_io_hps_io_emac1_inst_rxd3,
hps_io_hps_io_qspi_inst_io0,
hps_io_hps_io_qspi_inst_io1,
hps_io_hps_io_qspi_inst_io2,
hps_io_hps_io_qspi_inst_io3,
hps_io_hps_io_qspi_inst_ss0,
hps_io_hps_io_qspi_inst_clk,
hps_io_hps_io_sdio_inst_cmd,
hps_io_hps_io_sdio_inst_d0,
hps_io_hps_io_sdio_inst_d1,
hps_io_hps_io_sdio_inst_clk,
hps_io_hps_io_sdio_inst_d2,
hps_io_hps_io_sdio_inst_d3,
hps_io_hps_io_usb1_inst_d0,
hps_io_hps_io_usb1_inst_d1,
hps_io_hps_io_usb1_inst_d2,
hps_io_hps_io_usb1_inst_d3,
hps_io_hps_io_usb1_inst_d4,
hps_io_hps_io_usb1_inst_d5,
hps_io_hps_io_usb1_inst_d6,
hps_io_hps_io_usb1_inst_d7,
hps_io_hps_io_usb1_inst_clk,
hps_io_hps_io_usb1_inst_stp,
hps_io_hps_io_usb1_inst_dir,
hps_io_hps_io_usb1_inst_nxt,
hps_io_hps_io_spim1_inst_clk,
hps_io_hps_io_spim1_inst_mosi,
hps_io_hps_io_spim1_inst_miso,
hps_io_hps_io_spim1_inst_ss0,
hps_io_hps_io_uart0_inst_rx,
hps_io_hps_io_uart0_inst_tx,
hps_io_hps_io_i2c0_inst_sda,
hps_io_hps_io_i2c0_inst_scl,
hps_io_hps_io_i2c1_inst_sda,
hps_io_hps_io_i2c1_inst_scl,
hps_io_hps_io_gpio_inst_gpio09,
hps_io_hps_io_gpio_inst_gpio35,
hps_io_hps_io_gpio_inst_gpio40,
hps_io_hps_io_gpio_inst_gpio41,
hps_io_hps_io_gpio_inst_gpio48,
hps_io_hps_io_gpio_inst_gpio53,
hps_io_hps_io_gpio_inst_gpio54,
hps_io_hps_io_gpio_inst_gpio61,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
pushbuttons_export,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
slider_switches_export,
system_pll_ref_clk_clk,
system_pll_ref_reset_reset,
vga_clk,
vga_hs,
vga_vs,
vga_blank,
vga_sync,
vga_r,
vga_g,
vga_b,
vga_pll_ref_clk_clk,
vga_pll_ref_reset_reset,
video_in_td_clk27,
video_in_td_data,
video_in_td_hs,
video_in_td_vs,
video_in_clk27_reset,
video_in_td_reset,
video_in_overflow_flag,
audio_clk_clk,
sdram_clk_clk);
input audio_adcdat;
input audio_adclrck;
input audio_bclk;
output audio_dacdat;
input audio_daclrck;
input audio_pll_ref_clk_clk;
input audio_pll_ref_reset_reset;
inout av_config_sdat;
output av_config_sclk;
input clock_bridge_0_in_clk_clk;
input [29:0] ebab_video_in_external_interface_address;
input [1:0] ebab_video_in_external_interface_byte_enable;
input ebab_video_in_external_interface_read;
input ebab_video_in_external_interface_write;
input [15:0] ebab_video_in_external_interface_write_data;
output ebab_video_in_external_interface_acknowledge;
output [15:0] ebab_video_in_external_interface_read_data;
output [15:0] hex3_hex0_export;
output hps_io_hps_io_emac1_inst_tx_clk;
output hps_io_hps_io_emac1_inst_txd0;
output hps_io_hps_io_emac1_inst_txd1;
output hps_io_hps_io_emac1_inst_txd2;
output hps_io_hps_io_emac1_inst_txd3;
input hps_io_hps_io_emac1_inst_rxd0;
inout hps_io_hps_io_emac1_inst_mdio;
output hps_io_hps_io_emac1_inst_mdc;
input hps_io_hps_io_emac1_inst_rx_ctl;
output hps_io_hps_io_emac1_inst_tx_ctl;
input hps_io_hps_io_emac1_inst_rx_clk;
input hps_io_hps_io_emac1_inst_rxd1;
input hps_io_hps_io_emac1_inst_rxd2;
input hps_io_hps_io_emac1_inst_rxd3;
inout hps_io_hps_io_qspi_inst_io0;
inout hps_io_hps_io_qspi_inst_io1;
inout hps_io_hps_io_qspi_inst_io2;
inout hps_io_hps_io_qspi_inst_io3;
output hps_io_hps_io_qspi_inst_ss0;
output hps_io_hps_io_qspi_inst_clk;
inout hps_io_hps_io_sdio_inst_cmd;
inout hps_io_hps_io_sdio_inst_d0;
inout hps_io_hps_io_sdio_inst_d1;
output hps_io_hps_io_sdio_inst_clk;
inout hps_io_hps_io_sdio_inst_d2;
inout hps_io_hps_io_sdio_inst_d3;
inout hps_io_hps_io_usb1_inst_d0;
inout hps_io_hps_io_usb1_inst_d1;
inout hps_io_hps_io_usb1_inst_d2;
inout hps_io_hps_io_usb1_inst_d3;
inout hps_io_hps_io_usb1_inst_d4;
inout hps_io_hps_io_usb1_inst_d5;
inout hps_io_hps_io_usb1_inst_d6;
inout hps_io_hps_io_usb1_inst_d7;
input hps_io_hps_io_usb1_inst_clk;
output hps_io_hps_io_usb1_inst_stp;
input hps_io_hps_io_usb1_inst_dir;
input hps_io_hps_io_usb1_inst_nxt;
output hps_io_hps_io_spim1_inst_clk;
output hps_io_hps_io_spim1_inst_mosi;
input hps_io_hps_io_spim1_inst_miso;
output hps_io_hps_io_spim1_inst_ss0;
input hps_io_hps_io_uart0_inst_rx;
output hps_io_hps_io_uart0_inst_tx;
inout hps_io_hps_io_i2c0_inst_sda;
inout hps_io_hps_io_i2c0_inst_scl;
inout hps_io_hps_io_i2c1_inst_sda;
inout hps_io_hps_io_i2c1_inst_scl;
inout hps_io_hps_io_gpio_inst_gpio09;
inout hps_io_hps_io_gpio_inst_gpio35;
inout hps_io_hps_io_gpio_inst_gpio40;
inout hps_io_hps_io_gpio_inst_gpio41;
inout hps_io_hps_io_gpio_inst_gpio48;
inout hps_io_hps_io_gpio_inst_gpio53;
inout hps_io_hps_io_gpio_inst_gpio54;
inout hps_io_hps_io_gpio_inst_gpio61;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input [3:0] pushbuttons_export;
output [12:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [15:0] sdram_dq;
output [1:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
input [9:0] slider_switches_export;
input system_pll_ref_clk_clk;
input system_pll_ref_reset_reset;
output vga_clk;
output vga_hs;
output vga_vs;
output vga_blank;
output vga_sync;
output [7:0] vga_r;
output [7:0] vga_g;
output [7:0] vga_b;
input vga_pll_ref_clk_clk;
input vga_pll_ref_reset_reset;
input video_in_td_clk27;
input [7:0] video_in_td_data;
input video_in_td_hs;
input video_in_td_vs;
input video_in_clk27_reset;
output video_in_td_reset;
output video_in_overflow_flag;
output audio_clk_clk;
output sdram_clk_clk;
endmodule |
module accumulator(input clk,input [3:0] in, input acc_en, input reset, output reg [3:0] acc_out);
always @(posedge clk)
begin
if (reset) acc_out <= 4'b0000;
else if (acc_en)
begin
acc_out <= in; end
end
endmodule |
module adder_1bit(input a,b,cin, output sum, cout);
wire sum_1;
wire carry_1, carry_2;
assign sum_1=a^b;
assign sum=sum_1^cin;
assign carry_1=sum_1&cin;
assign carry_2=a&b;
assign cout=carry_1|carry_2;
endmodule |
module data_memory(input clk,rst,write_en,input [3:0]data_in, input[3:0]address, output reg [3:0]data_out);
reg [3:0] memory [0:15];
always@(posedge clk or posedge write_en)
begin
if (write_en)
begin
memory[address]<=data_in;
end
else
begin
data_out<=memory[address];
end
end
endmodule |
module input_ports(input d4,d5,d6,d7,output reg signal, output reg [1:0]pin_in);
always@*
begin
case(d4)
1'b1:
begin
pin_in<=2'b00;
signal<=1;
end
1'b0:
begin
pin_in<=2'b00;
signal<=0;
end
endcase
case(d5)
1'b1:
begin
pin_in<=2'b01;
signal<=1;
end
1'b0:
begin
pin_in<=2'b01;
signal<=0;
end
endcase
case(d6)
1'b1:
begin
pin_in<=2'b10;
signal<=1;
end
1'b0:
begin
pin_in<=2'b10;
signal<=0;
end
endcase
case(d7)
1'b1:
begin
pin_in<=2'b11;
signal<=1;
end
1'b0:
begin
pin_in<=2'b11;
signal<=0;
end
endcase
end
endmodule |
module instruction_decoder(input [7:0]opcode_in,input clk, rst, output reg [3:0]opcode,operand);
always@(*)
begin
if (rst)
begin
opcode <=4'b0000;
end
else
begin
opcode = opcode_in[7:4];
operand = opcode_in[3:0];
end
end
endmodule |
module output_ports (input [1:0] pin, input [3:0] signal, output reg d0, d1, d2, d3);
always @* begin
case (pin)
2'b00: d0 <= signal[0]; 2'b01: d1 <= signal[1]; 2'b10: d2 <= signal[2]; 2'b11: d3 <= signal[3]; endcase
end
endmodule |
module program_counter(input clk,rst,output reg[2:0]program_counter_out);
reg [2:0]temp;
always@(*)
begin
if(rst)
begin
program_counter_out<=3'b000;
temp<=3'b000;
end
else if(temp<3'b111)
begin
program_counter_out<=temp;
temp<=temp+1;
end
end
endmodule |
module program_memory(input clk, rst, input [7:0] address, output reg [7:0] data_out);
parameter mem_size = 28; reg [7:0] memory [0:mem_size-1];
initial
begin memory[0] = 8'b1111_0001;memory[1] = 8'b1101_0001;memory[2] = 8'b1111_1000;memory[3] = 8'b0001_0001;memory[4] = 8'b1101_0010;
memory[5] = 8'b1111_1111;memory[6] = 8'b1101_0011;memory[7] = 8'b1111_0111;memory[8] = 8'b0010_0011;memory[9] = 8'b1101_0100;
memory[10] = 8'b1111_1010;memory[11] = 8'b1101_0101;memory[12] = 8'b1111_0011;memory[13] = 8'b0011_0101;memory[14] = 8'b1101_0110;
memory[15] = 8'b1111_1111;memory[16] = 8'b1101_0111;memory[17] = 8'b1111_0011;memory[18] = 8'b0110_0111;memory[19] = 8'b1101_1000 ;memory[20] = 8'b1110_1000;
memory[21] = 8'b1011_1011;
memory[22] = 8'b1111_0000;memory[23] = 8'b1101_1111;memory[24] = 8'b1111_0101;memory[25] = 8'b1001_1111;
end
always @(posedge clk) begin
data_out <= memory[address];
end
endmodule |
module sub_1bit(input a,b,b_in,output diff, output borrow);
assign diff = a^b^b_in;
assign borrow = ~a & (b^b_in) | b & b_in;
endmodule |
module flowcontrol(
input wire management_allowinstruction,
input wire stateexecute,
input wire requestinginstruction,
input wire instructionbusy,
input wire requestingdata,
input wire databusy,
input wire pipe0_active,
input wire pipe1_active,
input wire pipe2_active,
input wire pipe1_shouldstall,
input wire pipe2_shouldstall,
output wire steppipe,
output wire stallpipe,
output wire progresspipe
);
wire fetchbusy = requestinginstruction && instructionbusy;
wire loadstorebusy = requestingdata && databusy;
wire stepblocked = fetchbusy || loadstorebusy;
wire pipeactive = pipe0_active || pipe1_active || pipe2_active;
assign stallpipe = !management_allowinstruction || pipe1_shouldstall || pipe2_shouldstall;
assign steppipe = stateexecute && !stepblocked;
assign progresspipe = pipeactive || management_allowinstruction;
endmodule |
module programcounter(
input wire clk,
input wire rst,
input wire[31:0] resetprogramcounteraddress,
input wire management_writeprogramcounter_set,
input wire management_writeprogramcounter_jump,
input wire[31:0] management_writedata,
input wire state,
input wire progresspipe,
input wire steppipe,
input wire stallpipe,
input wire intrap,
input wire[31:0] trapvector,
input wire pipe1_isret,
input wire[31:0] trapreturnvector,
input wire pipe1_jumpenable,
input wire[31:0] pipe1_nextprogramcounter,
output reg[31:0] fetchprogramcounter,
output reg[31:0] nextfetchprogramcounter,
output reg[31:0] executeprogramcounter,
output reg stepprogramcounter
);
localparam state_halt = 1'b0;
localparam state_execute = 1'b1;
always @(*) begin
if (rst) begin
nextfetchprogramcounter = resetprogramcounteraddress;
stepprogramcounter = 1'b0;
end else begin
nextfetchprogramcounter = fetchprogramcounter;
stepprogramcounter = 1'b0;
case (state)
state_halt: begin
end
state_execute: begin
if (intrap) begin
nextfetchprogramcounter = trapvector;
stepprogramcounter = 1'b1;
end else if (pipe1_isret) begin
nextfetchprogramcounter = trapreturnvector;
stepprogramcounter = 1'b1;
end else if (pipe1_jumpenable) begin
nextfetchprogramcounter = pipe1_nextprogramcounter;
stepprogramcounter = 1'b1;
end else if (!stallpipe) begin
nextfetchprogramcounter = fetchprogramcounter + 4;
stepprogramcounter = 1'b1;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
fetchprogramcounter <= 32'b0;
executeprogramcounter <= 32'b0;
end else begin
case (state)
state_halt: begin
if (!progresspipe) begin
if (management_writeprogramcounter_set) fetchprogramcounter <= management_writedata;
else if (management_writeprogramcounter_jump) fetchprogramcounter <= executeprogramcounter + management_writedata;
end
end
state_execute: begin
if (steppipe) begin
if (stepprogramcounter) fetchprogramcounter <= nextfetchprogramcounter;
if (!stallpipe) executeprogramcounter <= fetchprogramcounter;
end
end
endcase
end
end
endmodule |
module csr_readregister #(
parameter address = 12'h000
)(
input wire csrreadenable,
input wire[11:0] csrreadaddress,
output wire[31:0] csrreaddata,
output wire csrrequestoutput,
input wire[31:0] value
);
wire csrreadenabled = csrreadaddress == address;
assign csrreaddata = csrreadenabled && csrreadenable ? value : 32'b0;
assign csrrequestoutput = csrreadenabled && csrreadenable;
endmodule |
module pipefetch (
input wire clk,
input wire rst,
input wire run,
input wire pipestartup,
input wire steppipe,
input wire pipestall,
output reg currentpipestall,
output wire active,
input wire[31:0] currentinstruction,
output reg[31:0] lastinstruction,
input wire[31:0] fetchprogramcounter,
output wire addressmisaligned,
output wire[31:0] fetchaddress,
output wire fetchenable,
input wire fetchbusy
);
reg[31:0] cachedinstruction;
reg instructioncached;
reg usecachedinstruction;
always @(posedge clk) begin
if (rst) begin
currentpipestall <= 1'b1;
lastinstruction <= ~32'b0;
cachedinstruction <= 32'b0;
usecachedinstruction <= 1'b0;
end else begin
if (steppipe) begin
currentpipestall <= pipestall;
if (!pipestall) lastinstruction <= usecachedinstruction ? cachedinstruction : currentinstruction;
else lastinstruction <= ~32'b0;
usecachedinstruction <= 1'b0;
end else begin
usecachedinstruction <= instructioncached;
if (instructioncached && !usecachedinstruction) cachedinstruction <= currentinstruction;
end
end
end
always @(negedge clk) begin
if (rst) begin
instructioncached <= 1'b0;
end else begin
if (steppipe) begin
instructioncached <= 1'b0;
end else begin
if (!fetchbusy && fetchenable) begin
instructioncached <= 1'b1;
end
end
end
end
assign active = !pipestall;
assign addressmisaligned = |fetchprogramcounter[1:0];
assign fetchaddress = fetchprogramcounter;
assign fetchenable = run && (pipestartup || !usecachedinstruction);
endmodule |
module memorycontroller (
input wire clk,
input wire rst,
input wire[31:0] coreinstructionaddress,
input wire coreinstructionenable,
output reg[31:0] coreinstructiondataread,
output reg coreinstructionbusy,
input wire[31:0] coredataaddress,
input wire[3:0] coredatabyteselect,
input wire coredataenable,
input wire coredatawriteenable,
input wire[31:0] coredatadatawrite,
output reg[31:0] coredatadataread,
output reg coredatabusy,
output reg[23:0] localmemoryaddress,
output reg[3:0] localmemorybyteselect,
output reg localmemoryenable,
output reg localmemorywriteenable,
output reg[31:0] localmemorydatawrite,
input wire[31:0] localmemorydataread,
input wire localmemorybusy,
output reg[27:0] wbaddress,
output reg[3:0] wbbyteselect,
output reg wbenable,
output reg wbwriteenable,
output reg[31:0] wbdatawrite,
input wire[31:0] wbdataread,
input wire wbbusy
);
localparam local_memory_address = 4'b0000;
localparam wb_address = 4'b0001;
localparam source_none = 2'h0;
localparam source_instruction = 2'h1;
localparam source_data = 2'h2;
wire instruction_enablelocalmemoryrequest = coreinstructionenable && (coreinstructionaddress[31:24] == { local_memory_address, 4'b0000 });
wire data_enablelocalmemoryrequest = coredataenable && ( coredataaddress[31:24] == { local_memory_address, 4'b0000 });
wire instruction_enablewbrequest = coreinstructionenable && (coreinstructionaddress[31:28] == wb_address);
wire data_enablewbrequest = coredataenable && ( coredataaddress[31:28] == wb_address);
reg[1:0] localmemory_source = source_none;
always @(posedge clk) begin
if (rst) begin
localmemory_source <= source_none;
end else begin
case (localmemory_source)
source_none: begin
if (instruction_enablelocalmemoryrequest) localmemory_source <= source_instruction;
else if (data_enablelocalmemoryrequest) localmemory_source <= source_data;
end
source_instruction: begin
if (!instruction_enablelocalmemoryrequest) begin
if (data_enablelocalmemoryrequest) localmemory_source <= source_data;
else localmemory_source <= source_none;
end
end
source_data: begin
if (!data_enablelocalmemoryrequest) begin
if (instruction_enablelocalmemoryrequest) localmemory_source <= source_instruction;
else localmemory_source <= source_none;
end
end
default: begin
localmemory_source <= source_none;
end
endcase
end
end
reg[1:0] wb_source = source_none;
always @(posedge clk) begin
if (rst) begin
wb_source <= source_none;
end else begin
case (wb_source)
source_none: begin
if (instruction_enablewbrequest) wb_source <= source_instruction;
else if (data_enablewbrequest) wb_source <= source_data;
end
source_instruction: begin
if (!instruction_enablewbrequest) begin
if (data_enablewbrequest) wb_source <= source_data;
else wb_source <= source_none;
end
end
source_data: begin
if (!data_enablewbrequest) begin
if (instruction_enablewbrequest) wb_source <= source_instruction;
else wb_source <= source_none;
end
end
default: begin
wb_source <= source_none;
end
endcase
end
end
always @(*) begin
case (localmemory_source)
source_instruction: begin
localmemoryaddress = coreinstructionaddress[23:0];
localmemorybyteselect = 4'b1111;
localmemoryenable = coreinstructionenable;
localmemorywriteenable = 1'b0;
localmemorydatawrite = 32'b0;
end
source_data: begin
localmemoryaddress = coredataaddress[23:0];
localmemorybyteselect = coredatabyteselect;
localmemoryenable = coredataenable;
localmemorywriteenable = coredatawriteenable;
localmemorydatawrite = coredatadatawrite;
end
default: begin
if (instruction_enablelocalmemoryrequest) begin
localmemoryaddress = coreinstructionaddress[23:0];
localmemorybyteselect = 4'b1111;
localmemoryenable = coreinstructionenable;
localmemorywriteenable = 1'b0;
localmemorydatawrite = 32'b0;
end else if (data_enablelocalmemoryrequest) begin
localmemoryaddress = coredataaddress[23:0];
localmemorybyteselect = coredatabyteselect;
localmemoryenable = coredataenable;
localmemorywriteenable = coredatawriteenable;
localmemorydatawrite = coredatadatawrite;
end else begin
localmemoryaddress = 24'b0;
localmemorybyteselect = 4'b0;
localmemoryenable = 1'b0;
localmemorywriteenable = 1'b0;
localmemorydatawrite = 32'b0;
end
end
endcase
end
always @(*) begin
case (wb_source)
source_instruction: begin
wbaddress = coreinstructionaddress[27:0];
wbbyteselect = 4'b1111;
wbenable = coreinstructionenable;
wbwriteenable = 1'b0;
wbdatawrite = 32'b0;
end
source_data: begin
wbaddress = coredataaddress[27:0];
wbbyteselect = coredatabyteselect;
wbenable = coredataenable;
wbwriteenable = coredatawriteenable;
wbdatawrite = coredatadatawrite;
end
default: begin
if (instruction_enablewbrequest) begin
wbaddress = coreinstructionaddress[27:0];
wbbyteselect = 4'b1111;
wbenable = coreinstructionenable;
wbwriteenable = 1'b0;
wbdatawrite = 32'b0;
end else if (data_enablewbrequest) begin
wbaddress = coredataaddress[27:0];
wbbyteselect = coredatabyteselect;
wbenable = coredataenable;
wbwriteenable = coredatawriteenable;
wbdatawrite = coredatadatawrite;
end else begin
wbaddress = 28'b0;
wbbyteselect = 4'b0;
wbenable = 1'b0;
wbwriteenable = 1'b0;
wbdatawrite = 32'b0;
end
end
endcase
end
always @(*) begin
if (rst) begin
coreinstructiondataread = ~32'b0;
coreinstructionbusy = 1'b1;
end else begin
if (localmemory_source == source_instruction) begin
coreinstructiondataread = localmemorydataread;
coreinstructionbusy = localmemorybusy;
end else if (wb_source == source_instruction) begin
coreinstructiondataread = wbdataread;
coreinstructionbusy = wbbusy;
end else begin
coreinstructiondataread = ~32'b0;
coreinstructionbusy = 1'b1;
end
end
end
always @(*) begin
if (rst) begin
coredatadataread = ~32'b0;
coredatabusy = 1'b1;
end else begin
if (localmemory_source == source_data) begin
coredatadataread = localmemorydataread;
coredatabusy = localmemorybusy;
end else if (wb_source == source_data) begin
coredatadataread = wbdataread;
coredatabusy = wbbusy;
end
else begin
coredatadataread = ~32'b0;
coredatabusy = 1'b1;
end
end
end
endmodule |
module core_wbinterface #(
parameter address_width = 28
)(
input wire wb_clk_i,
input wire wb_rst_i,
output wire wb_cyc_o,
output wire wb_stb_o,
output wire wb_we_o,
output reg[3:0] wb_sel_o,
output reg[31:0] wb_data_o,
output reg[address_width-1:0] wb_adr_o,
input wire wb_ack_i,
input wire wb_stall_i,
input wire wb_error_i,
input wire[31:0] wb_data_i,
input wire[address_width-1:0] wbaddress,
input wire[3:0] wbbyteselect,
input wire wbenable,
input wire wbwriteenable,
input wire[31:0] wbdatawrite,
output wire[31:0] wbdataread,
output reg wbbusy
);
localparam state_idle = 2'h0;
localparam state_write_single = 2'h1;
localparam state_read_single = 2'h2;
reg[1:0] state = state_idle;
reg[31:0] readdatabuffered;
always @(posedge wb_clk_i) begin
if (wb_rst_i || (wb_error_i && state != state_idle)) begin
state <= state_idle;
readdatabuffered <= ~32'b0;
wb_sel_o <= 4'b0;
wb_adr_o <= 0;
wb_data_o <= ~32'b0;
wbbusy <= 1'b0;
end else begin
case (state)
state_idle: begin
readdatabuffered <= ~32'b0;
wbbusy <= 1'b1;
if (wbenable) begin
if (wbwriteenable) begin
state <= state_write_single;
wb_data_o <= wbdatawrite;
end else begin
state <= state_read_single;
wb_data_o <= ~32'b0;
end
wb_sel_o <= wbbyteselect;
wb_adr_o <= wbaddress;
end
end
state_write_single: begin
if (wbenable) begin
if (wb_ack_i) begin
state <= state_idle;
wbbusy <= 1'b0;
end
end else begin
state <= state_idle;
end
end
state_read_single: begin
if (wbenable) begin
if (wb_ack_i) begin
state <= state_idle;
readdatabuffered <= wb_data_i;
wbbusy <= 1'b0;
end
end else begin
state <= state_idle;
end
end
default: begin
state <= state_idle;
wbbusy <= 1'b1;
end
endcase
end
end
assign wb_cyc_o = state != state_idle && wbenable;
assign wb_stb_o = wb_cyc_o;
assign wb_we_o = state == state_write_single;
assign wbdataread = readdatabuffered;
wire _unused_wb_stall_i = wb_stall_i;
endmodule |
module memorypage #(
parameter address_size = 24,
parameter sram_address_size = 9,
parameter page_index_address_size = 4,
parameter index = 0
)(
input wire clk,
input wire rst,
input wire automaticpaging,
input wire automaticpagingchanged,
input wire manualpageaddressset,
input wire[manual_page_address_size-1:0] manualpageaddress,
input wire pageselected,
input wire pageloading,
input wire pageflushing,
input wire busenable,
input wire buswriteenable,
input wire[address_size-1:0] busvirtualaddress,
output wire[sram_address_size+1:0] busphysicaladdress,
output wire[sram_address_size+1:0] cachesramaddress,
input wire cachesrambusy,
output reg pagevalid,
output wire wordready,
input wire qspi_enable,
input wire writeenable,
output wire[23:0] qspi_address,
output wire qspi_changeaddress,
output wire qspi_requestdata,
output wire qspi_storedata,
input wire qspi_wordcomplete,
input wire qspi_initialised,
input wire qspi_busy,
output wire pageaddressset
);
localparam page_number_address_size = (address_size - page_data_address_size - 2);
localparam page_data_address_size = (sram_address_size - page_index_address_size);
localparam page_data_counter_address_size = (page_data_address_size + 1);
localparam manual_page_address_size = (page_number_address_size - page_index_address_size);
localparam state_empty = 2'b00;
localparam state_loading = 2'b01;
localparam state_loaded = 2'b10;
localparam state_flushing = 2'b11;
reg[1:0] state = state_empty;
reg datadirty;
reg pendingaddresschange;
wire[page_index_address_size-1:0] pageindex = index;
reg[page_number_address_size-1:0] currentpageaddress;
reg[address_size-1:0] loadaddress;
wire [address_size-1:0] nextloadaddress = loadaddress + 4;
reg[page_data_counter_address_size-1:0] cachedcount;
wire[page_data_counter_address_size-1:0] nextcachedcount = cachedcount + 1;
wire[page_data_counter_address_size-1:0] cachedcountfinal = 1 << page_data_address_size;
wire[page_number_address_size-1:0] targetpageaddress = busvirtualaddress[page_number_address_size+page_data_address_size+2-1:page_data_address_size+2];
wire[page_data_counter_address_size-1:0] targetsubpageaddress = { 1'b0, busvirtualaddress[page_data_address_size+1:2] };
always @(*) begin
if (automaticpaging) pagevalid = pageaddressset && (targetpageaddress == currentpageaddress);
else pagevalid = pageaddressset && (targetpageaddress[page_index_address_size-1:0] == currentpageaddress[page_index_address_size-1:0]);
end
wire invalidpage = busenable && ~|busvirtualaddress[1:0] && automaticpaging && !pagevalid;
assign wordready = qspi_enable && qspi_initialised && pagevalid && pageselected && (targetsubpageaddress < cachedcount) && (state != state_flushing) && !invalidpage && !pendingaddresschange;
reg[page_number_address_size-1:0] currentpageaddressloadaddress;
reg requireaddresschange;
always @(*) begin
currentpageaddressloadaddress = {page_number_address_size{1'b0}};
requireaddresschange = 1'b0;
if (automaticpaging) begin
if (busenable && ~|busvirtualaddress[1:0] && invalidpage && pageselected) begin
currentpageaddressloadaddress = targetpageaddress;
requireaddresschange = 1'b1;
end
end else begin
if (manualpageaddressset) begin
currentpageaddressloadaddress = { manualpageaddress, pageindex };
requireaddresschange = 1'b1;
end
end
end
assign qspi_address = { currentpageaddress[address_size-page_data_address_size-2-1:0], {page_data_address_size{1'b0}}, 2'b00 };
assign qspi_changeaddress = pendingaddresschange && (pageloading || pageflushing) && !qspi_busy;
reg memoryoperationpending;
always @(posedge clk) begin
if (rst) begin
memoryoperationpending <= 1'b0;
end else begin
if (memoryoperationpending) begin
if (!cachesrambusy) memoryoperationpending <= 1'b0;
end if (pageloading || pageflushing) begin
if (qspi_wordcomplete && cachesrambusy) memoryoperationpending <= 1'b1;
end else begin
memoryoperationpending <= 1'b0;
end
end
end
reg pendingload;
reg[23:0] pendingloadaddress;
always @(posedge clk) begin
if (rst) begin
state <= state_empty;
datadirty <= 1'b0;
loadaddress <= 24'b0;
cachedcount <= {page_data_counter_address_size{1'b0}};
pendingload <= 1'b0;
pendingloadaddress <= 24'b0;
end else begin
case(state)
state_empty: begin
if (requireaddresschange) begin
`ifdef sim && debug_cached_memory
$display("changing base address of cached memory page 0x%h to 0x%h", pageindex, qspi_address);
$fflush();
`endif
state <= state_loading;
datadirty <= 1'b0;
loadaddress <= qspi_address;
cachedcount <= {page_data_counter_address_size{1'b0}};
end
end
state_loading: begin
if (automaticpagingchanged) begin
state <= state_empty;
end else if (!pendingaddresschange && (qspi_wordcomplete || memoryoperationpending) && pageloading && !cachesrambusy) begin
if (nextcachedcount == cachedcountfinal) begin
state <= state_loaded;
cachedcount <= nextcachedcount;
end else begin
loadaddress <= nextloadaddress;
cachedcount <= nextcachedcount;
end
end
if (busenable && ~|busvirtualaddress[1:0] && buswriteenable) datadirty <= 1'b1;
end
state_loaded: begin
if (automaticpagingchanged) begin
if (writeenable && datadirty) begin
state <= state_flushing;
pendingload <= 1'b0;
end else begin
state <= state_empty;
end
end else if (requireaddresschange) begin
if (writeenable && datadirty) begin
state <= state_flushing;
pendingload <= 1'b1;
pendingloadaddress <= qspi_address;
end else begin
`ifdef sim && debug_cached_memory
$display("changing base address of cached memory page 0x%h to 0x%h", pageindex, qspi_address);
$fflush();
`endif
state <= state_loading;
datadirty <= 1'b0;
loadaddress <= qspi_address;
cachedcount <= {page_data_counter_address_size{1'b0}};
end
end else begin
if (busenable && ~|busvirtualaddress[1:0] && buswriteenable) datadirty <= 1'b1;
end
end
state_flushing: begin
if (!pendingaddresschange) begin
if ((qspi_wordcomplete || memoryoperationpending) && pageflushing && !cachesrambusy) begin
if (nextcachedcount == cachedcountfinal) begin
if (pendingload) begin
state <= state_loading;
datadirty <= 1'b0;
pendingload <= 1'b0;
loadaddress <= pendingloadaddress;
cachedcount <= {page_data_counter_address_size{1'b0}};
end else begin
state <= state_empty;
cachedcount <= nextcachedcount;
end
end else begin
loadaddress <= nextloadaddress;
cachedcount <= nextcachedcount;
end
end
end
end
default: state <= state_empty;
endcase
end
end
assign pageaddressset = state == state_loading || state == state_loaded;
assign qspi_storedata = state == state_flushing;
assign qspi_requestdata = state == state_loading;
always @(posedge clk) begin
if (rst) begin
currentpageaddress <= {page_number_address_size{1'b0}};
pendingaddresschange <= 1'b0;
end else if (qspi_changeaddress) begin
pendingaddresschange <= 1'b0;
end else if (requireaddresschange) begin
currentpageaddress <= currentpageaddressloadaddress;
pendingaddresschange <= 1'b1;
end else if (pendingaddresschange && automaticpagingchanged) begin
pendingaddresschange <= 1'b0;
end
end
assign busphysicaladdress = { pageindex, busvirtualaddress[page_data_address_size+1:2], 2'b00};
assign cachesramaddress = { pageindex, loadaddress[page_data_address_size+1:2], 2'b00 };
endmodule |
module dataregister #(
parameter width = 32,
parameter address = 12'b0
)(
input wire enable,
input wire peripheralbus_we,
input wire peripheralbus_oe,
output wire peripheralbus_busy,
input wire[11:0] peripheralbus_address,
input wire[3:0] peripheralbus_byteselect,
output wire[31:0] peripheralbus_dataread,
input wire[31:0] peripheralbus_datawrite,
output wire requestoutput,
output wire[width-1:0] writedata,
output wire writedata_en,
input wire writedata_busy,
input wire[width-1:0] readdata,
output wire readdata_en,
input wire readdata_busy
);
wire[31:0] datamask = {
peripheralbus_byteselect[3] ? 8'hff : 8'h00,
peripheralbus_byteselect[2] ? 8'hff : 8'h00,
peripheralbus_byteselect[1] ? 8'hff : 8'h00,
peripheralbus_byteselect[0] ? 8'hff : 8'h00
};
wire registerselect = enable && (peripheralbus_address == address);
wire we = registerselect && peripheralbus_we && !peripheralbus_oe;
wire oe = registerselect && peripheralbus_oe && !peripheralbus_we;
assign writedata = we ? peripheralbus_datawrite[width-1:0] : {width{1'b0}};
assign writedata_en = we;
generate
if (width < 32) wire _unused_peripheralbus_datawrite = &{ 1'b0, peripheralbus_datawrite[31:width], 1'b0 };
endgenerate
wire[31:0] basereaddata;
generate
if (width == 32) begin
assign basereaddata = readdata;
end else begin
wire[32-width-1:0] zeropadding = 'b0;
assign basereaddata = { zeropadding, readdata };
end
endgenerate
assign peripheralbus_dataread = oe ? basereaddata & datamask : 32'b0;
assign peripheralbus_busy = registerselect && ((we && writedata_busy) | (oe && readdata_busy));
assign requestoutput = oe;
assign readdata_en = oe;
endmodule |
module deviceselect #(
parameter id = 4'h0
)(
input wire peripheralenable,
input wire[15:0] peripheralbus_address,
output wire[11:0] localaddress,
output wire deviceenable
);
assign deviceenable = peripheralenable && (peripheralbus_address[15:12] == id[3:0]);
assign localaddress = peripheralbus_address[11:0];
endmodule |
module wbperipheralbusinterface (
`ifdef use_power_pins
inout vpwr,
inout vgnd,
`endif
input wire wb_clk_i,
input wire wb_rst_i,
input wire wb_stb_i,
input wire wb_cyc_i,
input wire wb_we_i,
input wire[3:0] wb_sel_i,
input wire[31:0] wb_data_i,
input wire[23:0] wb_adr_i,
output wire wb_ack_o,
output wire wb_stall_o,
output wire wb_error_o,
output wire[31:0] wb_data_o,
output wire peripheralbus_we,
output wire peripheralbus_oe,
input wire peripheralbus_busy,
output wire[23:0] peripheralbus_address,
output wire[3:0] peripheralbus_byteselect,
input wire[31:0] peripheralbus_dataread,
output wire[31:0] peripheralbus_datawrite
);
localparam state_idle = 2'h0;
localparam state_write_single = 2'h1;
localparam state_read_single = 2'h2;
localparam state_finish = 2'h3;
reg[1:0] state = state_idle;
reg[23:0] currentaddress;
reg[3:0] currentbyteselect;
reg stall = 1'b0;
reg acknowledge = 1'b0;
reg[31:0] dataread_buffered;
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
state <= state_idle;
stall <= 1'b0;
acknowledge <= 1'b0;
dataread_buffered <= ~32'b0;
end else begin
case (state)
state_idle: begin
stall <= 1'b0;
acknowledge <= 1'b0;
dataread_buffered <= ~32'b0;
if (wb_cyc_i) begin
if (wb_stb_i) begin
currentaddress <= wb_adr_i;
currentbyteselect <= wb_sel_i;
stall <= 1'b1;
if (wb_we_i) begin
state <= state_write_single;
end else begin
state <= state_read_single;
end
end
end
end
state_write_single: begin
if (!peripheralbus_busy) begin
state <= state_finish;
acknowledge <= 1'b1;
end
end
state_read_single: begin
if (!peripheralbus_busy) begin
state <= state_finish;
acknowledge <= 1'b1;
dataread_buffered <= peripheralbus_dataread;
end
end
state_finish: begin
state <= state_idle;
stall <= 1'b0;
acknowledge <= 1'b0;
dataread_buffered <= ~32'b0;
end
default: begin
state <= state_idle;
stall <= 1'b0;
acknowledge <= 1'b0;
end
endcase
end
end
assign wb_ack_o = acknowledge;
assign wb_stall_o = stall;
assign wb_error_o = 1'b0;
assign peripheralbus_we = state == state_write_single;
assign peripheralbus_oe = state == state_read_single;
assign peripheralbus_address = state != state_idle ? currentaddress : 24'b0;
assign peripheralbus_byteselect = state != state_idle ? currentbyteselect : 4'b0;
assign wb_data_o = dataread_buffered;
assign peripheralbus_datawrite = state == state_write_single ? wb_data_i : 32'b0;
endmodule |
module localmemoryinterface_rw #(
parameter address_size = 24,
parameter sram_address_size = 9
)(
input wire clk,
input wire rst,
input wire[address_size-1:0] primaryaddress,
input wire[3:0] primarybyteselect,
input wire primaryenable,
input wire primarywriteenable,
input wire[31:0] primarydatawrite,
output wire[31:0] primarydataread,
output wire primarybusy,
input wire[address_size-1:0] secondaryaddress,
input wire[3:0] secondarybyteselect,
input wire secondaryenable,
input wire secondarywriteenable,
input wire[31:0] secondarydatawrite,
output wire[31:0] secondarydataread,
output wire secondarybusy,
output wire sram_primaryselect,
output wire sram_primarywriteenable,
output wire[sram_address_size-1:0] sram_primaryaddress,
output reg[3:0] sram_primarywritemask,
output reg[31:0] sram_primarydatawrite,
input wire[31:0] sram_primarydataread
);
localparam primary = 1'b0;
localparam secondary = 1'b1;
wire primarysramenable;
wire primarysramwriteenable = primarysramenable && primarywriteenable && ~|primaryaddress[1:0];
wire secondarysramenable;
wire secondarysramwriteenable = secondarysramenable && secondarywriteenable && ~|secondaryaddress[1:0];
generate
if (address_size <= sram_address_size+2) begin
assign primarysramenable = primaryenable;
assign secondarysramenable = secondaryenable;
end else begin
assign primarysramenable = primaryaddress[address_size-1:sram_address_size+2] == 'b0 && primaryenable;
assign secondarysramenable = secondaryaddress[address_size-1:sram_address_size+2] == 'b0 && secondaryenable;
end
endgenerate
wire[31:0] rwportreaddata;
wire rwactiondone;
reg primaryactiondone = 1'b0;
reg[3:0] lastprimarybyteselect = 4'b0;
always @(posedge clk) begin
if (rst) begin
primaryactiondone <= 1'b0;
lastprimarybyteselect <= 4'b0;
end else if (rwactiondone && (wrcontroller == primary)) begin
primaryactiondone <= 1'b1;
lastprimarybyteselect <= primarybyteselect;
end else begin
primaryactiondone <= 1'b0;
end
end
reg secondaryactiondone = 1'b0;
reg[3:0] lastsecondarybyteselect = 4'b0;
always @(posedge clk) begin
if (rst) begin
secondaryactiondone <= 1'b0;
lastsecondarybyteselect <= 4'b0;
end else if (rwactiondone && (wrcontroller == secondary)) begin
secondaryactiondone <= 1'b1;
lastsecondarybyteselect <= secondarybyteselect;
end else if (secondaryactiondone) begin
secondaryactiondone <= 1'b0;
end
end
reg wrcontroller = 1'b0;
always @(negedge clk) begin
if (rst) begin
wrcontroller <= 1'b0;
end else begin
if (rwactiondone || !rwportenable) begin
if (primarysramenable) begin
wrcontroller <= primary;
end else if (secondarysramenable) begin
wrcontroller <= secondary;
end
end
end
end
assign primarybusy = primarysramenable && (wrcontroller != primary || !primaryactiondone);
assign secondarybusy = secondarysramenable && (wrcontroller != secondary || !secondaryactiondone);
wire rwportenable = wrcontroller ? secondarysramenable : primarysramenable;
reg rwwriteenable;
reg[sram_address_size-1:0] rwaddress;
always @(*) begin
if (rst) begin
rwwriteenable = 1'b0;
rwaddress = 'b0;
end else begin
case (wrcontroller)
primary: begin
rwwriteenable = primarysramwriteenable;
rwaddress = primaryaddress[sram_address_size+1:2];
end
secondary: begin
rwwriteenable = secondarysramwriteenable;
rwaddress = secondaryaddress[sram_address_size+1:2];
end
endcase
end
end
assign primarydataread = {
lastprimarybyteselect[3] && primaryactiondone ? rwportreaddata[31:24] : ~8'h00,
lastprimarybyteselect[2] && primaryactiondone ? rwportreaddata[23:16] : ~8'h00,
lastprimarybyteselect[1] && primaryactiondone ? rwportreaddata[15:8] : ~8'h00,
lastprimarybyteselect[0] && primaryactiondone ? rwportreaddata[7:0] : ~8'h00
};
assign secondarydataread = {
lastsecondarybyteselect[3] && secondaryactiondone ? rwportreaddata[31:24] : ~8'h00,
lastsecondarybyteselect[2] && secondaryactiondone ? rwportreaddata[23:16] : ~8'h00,
lastsecondarybyteselect[1] && secondaryactiondone ? rwportreaddata[15:8] : ~8'h00,
lastsecondarybyteselect[0] && secondaryactiondone ? rwportreaddata[7:0] : ~8'h00
};
always @(*) begin
if (rst) begin
sram_primarywritemask = 4'b0;
sram_primarydatawrite = 32'b0;
end else begin
if (wrcontroller == primary) begin
sram_primarywritemask = primarybyteselect;
sram_primarydatawrite = primarydatawrite;
end else if (wrcontroller == secondary) begin
sram_primarywritemask = secondarybyteselect;
sram_primarydatawrite = secondarydatawrite;
end else begin
sram_primarywritemask = 4'b0;
sram_primarydatawrite = 32'b0;
end
end
end
assign sram_primaryselect = rwportenable;
assign sram_primarywriteenable = rwwriteenable;
assign sram_primaryaddress = rwaddress;
assign rwactiondone = rwportenable;
assign rwportreaddata = sram_primarydataread;
endmodule |
module videomemory (
`ifdef use_power_pins
inout vpwr,
inout vgnd,
`endif
input wire clk,
input wire rst,
input wire peripheralbus_we,
input wire peripheralbus_oe,
output wire peripheralbus_busy,
input wire[23:0] peripheralbus_address,
input wire[3:0] peripheralbus_byteselect,
input wire[31:0] peripheralbus_datawrite,
output wire[31:0] peripheralbus_dataread,
output wire requestoutput,
input wire pixel_spritemode,
input wire pixel_fetchdata,
input wire[sram_address_size+3-1:0] pixel_address,
output reg[31:0] pixel_data,
output reg sram_pixel_primaryselect,
output wire sram_pixel_primarywriteenable,
output wire[3:0] sram_pixel_primarywritemask,
output wire[sram_address_size-1:0] sram_pixel_primaryaddress,
output wire[31:0] sram_pixel_primarydatawrite,
input wire[31:0] sram_pixel_primarydataread,
output reg sram_pixel_secondaryselect,
output reg[sram_address_size-1:0] sram_pixel_secondaryaddress,
input wire[31:0] sram_pixel_secondarydataread,
output reg sram_tilemap_primaryselect,
output wire sram_tilemap_primarywriteenable,
output wire[3:0] sram_tilemap_primarywritemask,
output wire[sram_address_size-1:0] sram_tilemap_primaryaddress,
output wire[31:0] sram_tilemap_primarydatawrite,
input wire[31:0] sram_tilemap_primarydataread,
output reg sram_tilemap_secondaryselect,
output reg[sram_address_size-1:0] sram_tilemap_secondaryaddress,
input wire[31:0] sram_tilemap_secondarydataread
);
localparam sram_address_size = 10;
localparam sram_peripheral_bus_address = 11'h000;
wire peripheralbusvalidaddress = peripheralbus_address[23:sram_address_size+3] == sram_peripheral_bus_address;
wire peripheralbusreadenable = peripheralbus_oe && peripheralbusvalidaddress;
wire peripheralbuswriteenable = peripheralbus_we && peripheralbusvalidaddress;
wire peripheralbusenablesram = peripheralbusreadenable || peripheralbuswriteenable;
wire peripheralbussrambank = peripheralbus_address[sram_address_size+2];
always @(*) begin
sram_pixel_primaryselect = 1'b0;
sram_tilemap_primaryselect = 1'b0;
if (peripheralbusenablesram) begin
case (peripheralbussrambank)
1'b0: sram_pixel_primaryselect = 1'b1;
1'b1: sram_tilemap_primaryselect = 1'b1;
endcase
end
end
reg wbreadready = 1'b0;
always @(posedge clk) begin
if (rst) wbreadready <= 1'b0;
else if (peripheralbusreadenable) wbreadready <= 1'b1;
else wbreadready <= 1'b0;
end
reg[31:0] readdata;
assign peripheralbus_dataread = {
peripheralbus_byteselect[3] && wbreadready ? readdata[31:24] : 8'h00,
peripheralbus_byteselect[2] && wbreadready ? readdata[23:16] : 8'h00,
peripheralbus_byteselect[1] && wbreadready ? readdata[15:8] : 8'h00,
peripheralbus_byteselect[0] && wbreadready ? readdata[7:0] : 8'h00
};
assign peripheralbus_busy = peripheralbusreadenable && !wbreadready;
assign requestoutput = peripheralbusreadenable;
assign sram_pixel_primarywriteenable = peripheralbuswriteenable;
assign sram_pixel_primarywritemask = peripheralbus_byteselect;
assign sram_pixel_primaryaddress = peripheralbus_address[sram_address_size+1:2];
assign sram_pixel_primarydatawrite = peripheralbus_datawrite;
assign sram_tilemap_primarywriteenable = peripheralbuswriteenable;
assign sram_tilemap_primarywritemask = peripheralbus_byteselect;
assign sram_tilemap_primaryaddress = peripheralbus_address[sram_address_size+1:2];
assign sram_tilemap_primarydatawrite = peripheralbus_datawrite;
always @(*) begin
if (peripheralbusreadenable) begin
case (peripheralbussrambank)
1'b0: readdata = sram_pixel_primarydataread;
1'b1: readdata = sram_tilemap_primarydataread;
endcase
end else begin
readdata = ~32'b0;
end
end
always @(*) begin
sram_pixel_secondaryselect = 1'b0;
sram_tilemap_secondaryselect = 1'b0;
if (pixel_fetchdata) begin
if (pixel_spritemode) begin
sram_pixel_secondaryselect = 1'b1;
sram_tilemap_secondaryselect = 1'b1;
end else begin
case (pixel_address[sram_address_size+2])
1'b0: sram_pixel_secondaryselect = 1'b1;
1'b1: sram_tilemap_secondaryselect = 1'b1;
endcase
end
end
end
always @(*) begin
if (pixel_spritemode) begin
sram_pixel_secondaryaddress = sram_tilemap_secondarydataread[sram_address_size-1:0];
sram_tilemap_secondaryaddress = pixel_address[sram_address_size+1:2];
end else begin
sram_pixel_secondaryaddress = pixel_address[sram_address_size+1:2];
sram_tilemap_secondaryaddress = pixel_address[sram_address_size+1:2];
end
end
always @(*) begin
pixel_data = 32'b0;
if (pixel_fetchdata) begin
if (pixel_spritemode) begin
pixel_data = sram_pixel_secondarydataread;
end else begin
case (pixel_address[sram_address_size+2])
1'b0: pixel_data = sram_pixel_secondarydataread;
1'b1: pixel_data = sram_tilemap_secondarydataread;
endcase
end
end
end
wire[1:0] _unused_peripheralbus_address = peripheralbus_address[1:0];
endmodule |
module controllerarbiter (
input wire clk,
input wire rst,
input wire[3:0] request,
output wire[1:0] controllerselected
);
localparam controller0 = 2'h0;
localparam controller1 = 2'h1;
localparam controller2 = 2'h2;
localparam controller3 = 2'h3;
reg[1:0] currentcontroller = controller0;
reg[1:0] nextcontroller;
always @(*) begin
nextcontroller = currentcontroller;
case (currentcontroller)
controller0: begin
if (!request[0]) begin
if (request[1]) nextcontroller = controller1;
else if (request[2]) nextcontroller = controller2;
else if (request[3]) nextcontroller = controller3;
end
end
controller1: begin
if (!request[1]) begin
if (request[2]) nextcontroller = controller2;
else if (request[3]) nextcontroller = controller3;
else if (request[0]) nextcontroller = controller0;
end
end
controller2: begin
if (!request[2]) begin
if (request[3]) nextcontroller = controller3;
else if (request[0]) nextcontroller = controller0;
else if (request[1]) nextcontroller = controller1;
end
end
controller3: begin
if (!request[3]) begin
if (request[0]) nextcontroller = controller0;
else if (request[1]) nextcontroller = controller1;
else if (request[2]) nextcontroller = controller2;
end
end
endcase
end
always @(posedge clk) begin
if (rst) currentcontroller <= controller0;
else currentcontroller <= nextcontroller;
end
assign controllerselected = nextcontroller;
endmodule |
module id_ex (
input clk ,
input id_alusrc , input id_memtoreg , input id_regwrite ,
input id_memread ,
input id_memwrite ,
input id_branch ,
input id_jump ,
input [ 1:0] id_aluop ,
input [63:0] id_pcaddress,
input [63:0] id_readdata1,
input [63:0] id_readdata2,
input [63:0] id_eximm ,
input id_funct7 ,
input [ 2:0] id_funct3 ,
input [ 4:0] id_rdreg ,
output reg ex_alusrc , output reg ex_memtoreg , output reg ex_regwrite ,
output reg ex_memread ,
output reg ex_memwrite ,
output reg ex_branch ,
output reg ex_jump ,
output reg [ 1:0] ex_aluop ,
output reg [63:0] ex_pcaddress,
output reg [63:0] ex_readdata1,
output reg [63:0] ex_readdata2,
output reg [63:0] ex_eximm ,
output reg ex_funct7 ,
output reg [ 2:0] ex_funct3 ,
output reg [ 4:0] ex_rdreg
);
always @(posedge clk) begin
ex_alusrc <= id_alusrc;
ex_memtoreg <= id_memtoreg;
ex_regwrite <= id_regwrite;
ex_memread <= id_memread;
ex_memwrite <= id_memwrite;
ex_branch <= id_branch;
ex_jump <= id_jump;
ex_aluop <= id_aluop;
ex_pcaddress <= id_pcaddress;
ex_readdata1 <= id_readdata1;
ex_readdata2 <= id_readdata2;
ex_funct7 <= id_funct7;
ex_funct3 <= id_funct3;
ex_rdreg <= id_rdreg;
ex_eximm <= id_eximm;
end
endmodule |
module if_id (
input clk ,
input [63:0] if_pcaddress ,
input [31:0] if_instruction,
output reg [63:0] id_pcaddress ,
output reg [63:0] id_instruction
);
always@(posedge clk)begin
id_pcaddress = if_pcaddress;
id_instruction = if_instruction;
end
endmodule |
module instructionmemory (
input [63:0] pc_address , output reg [31:0] instruction );
reg [31:0] inst_mem[0:1024];
initial
$readmemh ("rom.txt", inst_mem);
always @(*) begin
instruction = inst_mem[pc_address[63:2]];
end
endmodule |
module capture #( parameter pcount = 1000 )
(
input i_clk, i_rst,
input [4:0] i_100,
input [4:0] i_010,
input [4:0] i_001,
output [4:0] o_100,
output [4:0] o_010,
output [4:0] o_001
);
reg [7:0] r_rst = 'hff;
wire w_rst = r_rst[7];
always @( posedge i_clk )
if( i_rst )
r_rst <= 'hff;
else
r_rst <= { r_rst, 1'b0 };
reg [15:0] r_cnt;
always @( posedge i_clk )
if( w_rst )
r_cnt <= 'd0;
else
if( r_cnt == pcount )
r_cnt <= 'd0;
else
r_cnt <= r_cnt + 1;
reg [4:0] r_100, r_010, r_001;
assign o_100 = r_100;
assign o_010 = r_010;
assign o_001 = r_001;
always @( posedge i_clk )
if( w_rst ) begin
r_100 <= 'd0;
r_010 <= 'd0;
r_001 <= 'd0;
end
else if( r_cnt == pcount ) begin
r_100 <= i_100;
r_010 <= i_010;
r_001 <= i_001;
end
endmodule |
module grey_10
(
input i_clk, i_rst,
output [4:0] o_cnt,
output o_clk_div
);
localparam pzero = 'b10001;
localparam pone = 'b00001;
localparam ptwo = 'b00011;
localparam pthree = 'b00010;
localparam pfour = 'b00110;
localparam pfive = 'b00100;
localparam psix = 'b01100;
localparam pseven = 'b01000;
localparam peight = 'b11000;
localparam pnine = 'b10000;
reg [7:0] r_rst = 'hff;
wire w_rst = r_rst[7];
always @( posedge i_clk )
if( i_rst )
r_rst <= 'hff;
else
r_rst <= { r_rst, 1'b0 };
reg [4:0] r_cnt;
assign o_cnt = r_cnt;
always @( posedge i_clk )
if( w_rst )
r_cnt <= pzero;
else
r_cnt <= f_next( r_cnt );
reg r_clk_div, r_start;
assign o_clk_div = r_clk_div;
always @( posedge i_clk )
if( w_rst ) begin
r_clk_div <= 'b1;
r_start <= 'b1;
end
else
casex({ r_cnt == pfour, r_cnt == pnine, r_start })
'b1xx: r_clk_div <= 'b1;
'b01x: r_clk_div <= 'b0;
'b001: begin
r_clk_div <= 'b0;
r_start <= 'b0;
end
default: r_clk_div <= r_clk_div;
endcase
function [4:0] f_next( input [4:0] f_in );
case( f_in )
pzero: f_next = pone;
pone: f_next = ptwo;
ptwo: f_next = pthree;
pthree: f_next = pfour;
pfour: f_next = pfive;
pfive: f_next = psix;
psix: f_next = pseven;
pseven: f_next = peight;
peight: f_next = pnine;
default: f_next = pzero;
endcase
endfunction
endmodule |
module led
(
input i_clk, i_rst,
input [4:0] i_grey,
output [7:0] o_led
);
localparam pzero = 'b10001;
localparam pone = 'b00001;
localparam ptwo = 'b00011;
localparam pthree = 'b00010;
localparam pfour = 'b00110;
localparam pfive = 'b00100;
localparam psix = 'b01100;
localparam pseven = 'b01000;
localparam peight = 'b11000;
localparam pnine = 'b10000;
localparam pdp = 'b10101;
reg [4:0] r_led;
assign o_led = r_led;
always @( posedge i_clk )
if( i_rst )
r_led <= 'd0;
else
case( i_grey )
pzero: r_led <= 'b00111111;
pone: r_led <= 'b00000110;
ptwo: r_led <= 'b01011011;
pthree: r_led <= 'b01001111;
pfour: r_led <= 'b01100110;
pfive: r_led <= 'b01101101;
psix: r_led <= 'b01111101;
pseven: r_led <= 'b00000111;
peight: r_led <= 'b01111111;
pnine: r_led <= 'b01101111;
pdp: r_led <= 'b10000000;
default: r_led <= 'b01000000;
endcase
endmodule |
module ringd #( parameter pstages = 5 )
(
output o_clk
);
wire [7:0] w_rst;
reg r_rst = 'b1;
always @( w_rst[7] )
r_rst <= 'b0;
localparam pdel = 0.020;
assign #pdel w_rst[0] = r_rst;
assign #pdel w_rst[1] = w_rst[0];
assign #pdel w_rst[2] = w_rst[1];
assign #pdel w_rst[3] = w_rst[2];
assign #pdel w_rst[4] = w_rst[3];
assign #pdel w_rst[5] = w_rst[4];
assign #pdel w_rst[6] = w_rst[5];
assign #pdel w_rst[7] = w_rst[6];
localparam pnum = ( pstages * 2 ) - 1;
wire [pnum:0] w_clk;
assign o_clk = w_clk[1];
genvar ii;
for( ii=0; ii<pnum; ii=ii+2 ) begin
wire w_init = ( ii % 4 ) >> 1;
localparam xx = ii+3 > pnum ? 1 : ii+3;
localparam yy = ii+2 > pnum ? 0 : ii+2;
assign #pdel w_clk[ ii+1 :ii] = f_inv( r_rst, w_init, w_clk[ xx :yy], w_clk[ ii+1 :ii] );
end
function [1:0] f_inv( input i_rst, i_init,
input [1:0] i_pn, i_ppn );
if( i_rst )
if( i_init )
f_inv = 'b10;
else
f_inv = 'b01;
else
case( i_pn )
'b01: f_inv = 'b10;
'b10: f_inv = 'b01;
default: f_inv = i_ppn;
endcase
endfunction
endmodule |
module mariam_updown_counter(
`ifdef use_power_pins
inout vccd1, inout vssd1, `endif
input clk, reset,up_down, output[3:0] counter, output wire [3:0]io_oeb);
reg [3:0] counter_up_down;
assign io_oeb= 4'b0000;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule |
module ds18b20_dri(
input clk , input rst_n ,
inout dq , output reg [19:0] temp_data , output reg sign );
localparam rom_skip_cmd = 8'hcc; localparam convert_cmd = 8'h44; localparam read_temp = 8'hbe; localparam init = 3'd1 ; localparam rom_skip = 3'd2 ; localparam wr_byte = 3'd3 ; localparam temp_convert = 3'd4 ; localparam delay = 3'd5 ; localparam rd_temp = 3'd6 ; localparam rd_byte = 3'd7 ;
reg [ 5:0] cnt ; reg clk_1us ; reg [19:0] cnt_1us ; reg [ 2:0] cur_state ; reg [ 2:0] next_state ; reg [ 3:0] flow_cnt ; reg [ 3:0] wr_cnt ; reg [ 4:0] rd_cnt ; reg [ 7:0] wr_data ; reg [ 4:0] bit_width ; reg [15:0] rd_data ; reg [15:0] org_data ; reg [10:0] data1 ; reg [ 3:0] cmd_cnt ; reg init_done ; reg st_done ; reg cnt_1us_en ; reg dq_out ;
wire [19:0] data2 ;
assign dq = dq_out;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 6'b0;
clk_1us <= 1'b0;
end
else if(cnt < 6'd49) begin
cnt <= cnt + 1'b1;
clk_1us <= clk_1us;
end
else begin
cnt <= 6'b0;
clk_1us <= ~clk_1us;
end
end
always @ (posedge clk_1us or negedge rst_n) begin
if (!rst_n)
cnt_1us <= 20'b0;
else if (cnt_1us_en)
cnt_1us <= cnt_1us + 1'b1;
else
cnt_1us <= 20'b0;
end
always @ (posedge clk_1us or negedge rst_n) begin
if(!rst_n)
cur_state <= init;
else
cur_state <= next_state;
end
always @( * ) begin
case(cur_state)
init: begin if (init_done)
next_state = rom_skip;
else
next_state = init;
end
rom_skip: begin if(st_done)
next_state = wr_byte;
else
next_state = rom_skip;
end
wr_byte: begin if(st_done)
case(cmd_cnt) 4'b1: next_state = temp_convert;
4'd2: next_state = delay;
4'd3: next_state = rd_temp;
4'd4: next_state = rd_byte;
default:
next_state = temp_convert;
endcase
else
next_state = wr_byte;
end
temp_convert: begin if(st_done)
next_state = wr_byte;
else
next_state = temp_convert;
end
delay: begin if(st_done)
next_state = init;
else
next_state = delay;
end
rd_temp: begin if(st_done)
next_state = wr_byte;
else
next_state = rd_temp;
end
rd_byte: begin if(st_done)
next_state = init;
else
next_state = rd_byte;
end
default: next_state = init;
endcase
end
always @ (posedge clk_1us or negedge rst_n) begin
if(!rst_n) begin
flow_cnt <= 4'b0;
init_done <= 1'b0;
cnt_1us_en <= 1'b1;
dq_out <= 1'bz;
st_done <= 1'b0;
rd_data <= 16'b0;
rd_cnt <= 5'd0;
wr_cnt <= 4'd0;
cmd_cnt <= 3'd0;
end
else begin
st_done <= 1'b0;
case (next_state)
init:begin init_done <= 1'b0;
case(flow_cnt)
4'd0:
flow_cnt <= flow_cnt + 1'b1;
4'd1: begin cnt_1us_en <= 1'b1;
if(cnt_1us < 20'd500)
dq_out <= 1'b0;
else begin
cnt_1us_en <= 1'b0;
dq_out <= 1'bz;
flow_cnt <= flow_cnt + 1'b1;
end
end
4'd2:begin cnt_1us_en <= 1'b1;
if(cnt_1us < 20'd30)
dq_out <= 1'bz;
else
flow_cnt <= flow_cnt + 1'b1;
end
4'd3: begin if(!dq)
flow_cnt <= flow_cnt + 1'b1;
else
flow_cnt <= flow_cnt;
end
4'd4: begin if(cnt_1us == 20'd500) begin
cnt_1us_en <= 1'b0;
init_done <= 1'b1; flow_cnt <= 4'd0;
end
else
flow_cnt <= flow_cnt;
end
default: flow_cnt <= 4'd0;
endcase
end
rom_skip: begin wr_data <= rom_skip_cmd;
flow_cnt <= 4'd0;
st_done <= 1'b1;
end
wr_byte: begin if(wr_cnt <= 4'd7) begin
case (flow_cnt)
4'd0: begin
dq_out <= 1'b0; cnt_1us_en <= 1'b1; flow_cnt <= flow_cnt + 1'b1;
end
4'd1: begin flow_cnt <= flow_cnt + 1'b1;
end
4'd2: begin
if(cnt_1us < 20'd60) dq_out <= wr_data[wr_cnt];
else if(cnt_1us < 20'd63)
dq_out <= 1'bz; else
flow_cnt <= flow_cnt + 1'b1;
end
4'd3: begin flow_cnt <= 0;
cnt_1us_en <= 1'b0;
wr_cnt <= wr_cnt + 1'b1; end
default : flow_cnt <= 0;
endcase
end
else begin st_done <= 1'b1;
wr_cnt <= 4'b0;
cmd_cnt <= (cmd_cnt == 3'd4) ? 3'd1 : (cmd_cnt+ 1'b1);
end
end
temp_convert: begin wr_data <= convert_cmd;
st_done <= 1'b1;
end
delay: begin cnt_1us_en <= 1'b1;
if(cnt_1us == 20'd500000) begin
st_done <= 1'b1;
cnt_1us_en <= 1'b0;
end
end
rd_temp: begin wr_data <= read_temp;
bit_width <= 5'd16; st_done <= 1'b1;
end
rd_byte: begin if(rd_cnt < bit_width) begin
case(flow_cnt)
4'd0: begin
cnt_1us_en <= 1'b1;
dq_out <= 1'b0; flow_cnt <= flow_cnt + 1'b1;
end
4'd1: begin
dq_out <= 1'bz; if(cnt_1us == 20'd14) begin
rd_data <= {dq,rd_data[15:1]};
flow_cnt <= flow_cnt + 1'b1 ;
end
end
4'd2: begin
if (cnt_1us <= 20'd64) dq_out <= 1'bz;
else begin
flow_cnt <= 4'd0;
rd_cnt <= rd_cnt + 1'b1; cnt_1us_en <= 1'b0;
end
end
default : flow_cnt <= 4'd0;
endcase
end
else begin
st_done <= 1'b1;
org_data <= rd_data;
rd_cnt <= 5'b0;
end
end
default: ;
endcase
end
end
always @(posedge clk_1us or negedge rst_n) begin
if(!rst_n) begin
sign <= 1'b0;
data1 <= 11'b0;
end
else if(org_data[15] == 1'b0) begin
sign <= 1'b0;
data1 <= org_data[10:0];
end
else if(org_data[15] == 1'b1) begin
sign <= 1'b1;
data1 <= ~org_data[10:0] + 1'b1;
end
end
assign data2 = (data1 * 11'd625)/ 7'd100;
always @(posedge clk_1us or negedge rst_n) begin
if(!rst_n)
temp_data <= 20'b0;
else
temp_data <= data2;
end
endmodule |
module lelbc_test_rf(in,key,cnt,result);
input [0:63]in;
input [0:127]key;
input [0:3]cnt;
output [0:63]result;
reg [0:3] sbox[0:15];
initial begin
sbox[ 0]=4'hc; sbox[ 1]=4'he; sbox[ 2]=4'h6; sbox[ 3]=4'ha;
sbox[ 4]=4'h4; sbox[ 5]=4'hf; sbox[ 6]=4'h2; sbox[ 7]=4'h7;
sbox[ 8]=4'h9; sbox[ 9]=4'h8; sbox[10]=4'h3; sbox[11]=4'hb;
sbox[12]=4'h0; sbox[13]=4'hd; sbox[14]=4'h1; sbox[15]=4'h5;
end
wire [0:63]in1;
assign in1[0:31]=in[0:31]^key[0:31];
wire [0:31]temp1;
assign temp1={in1[5:31],in1[0:4]};
assign in1[32:63]=temp1[0:31]^in[32:63];
wire [0:63]in2;
assign in2={sbox[ in1[0:3] ],sbox[ in1[4:7] ],sbox[ in1[8:11] ],sbox[ in1[12:15]],sbox[ in1[16:19]],sbox[ in1[20:23]],sbox[ in1[24:27]],sbox[ in1[28:31]],sbox[ in1[32:35] ],sbox[ in1[36:39] ],sbox[ in1[40:43] ],sbox[ in1[44:47]],sbox[ in1[48:51]],sbox[ in1[52:55]],sbox[ in1[56:59]],sbox[ in1[60:63]]}; wire [0:31]temp2;
wire [0:63]in3;
assign temp2={in2[37:63],in2[32:36]};
assign in3[0:31]=temp2[0:31]^in2[0:31];
assign in3[32:63]=in2[32:63]^key[32:63];
assign result=in3;
endmodule |
module uart_loop (
input sys_clk, input sys_rst_n, input recv_done, input [63:0] recv_data, input tx_busy, output reg send_en, output reg [63:0] send_data
);
reg recv_done_d0;
reg recv_done_d1;
reg tx_ready;
reg encrypt_start;
reg [63:0] state;
reg [79:0] keys;
reg clk;
reg [23:0] counter;
wire recv_done_flag;
wire encrypt_end;
wire [0:63] result;
assign recv_done_flag = (~recv_done_d1) & recv_done_d0;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
recv_done_d0 <= 1'b0;
recv_done_d1 <= 1'b0;
end else begin
recv_done_d0 <= recv_done;
recv_done_d1 <= recv_done_d0;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
tx_ready <= 1'b0;
send_en <= 1'b0;
send_data <= 8'd0;
end else begin
if (recv_done_flag) begin
tx_ready <= 1'b1;
send_en <= 1'b0;
send_data <= recv_data;
end else begin
if (tx_ready && (~tx_busy)) begin
tx_ready <= 1'b0;
send_en <= 1'b1;
send_data <= recv_data;
end
end
end
end
endmodule |
module comparator_top #(parameter functional = 1) (
`ifdef use_power_pins
input vdd,
input vss,
input dvdd,
input dvss,
`endif
`ifndef cocotb_sim
input `real vinp,
input `real vinm,
`else
input real vinp,
input real vinm,
`endif output vout
);
`ifdef functional
assign vout = (vinp > vinm) ? 1'b1 : 1'b0;
`endif
endmodule |
module dac_3v_8bit #(parameter functional = 1)(
`ifdef use_power_pins
input vdd,
input vss,
input dvdd,
input dvss,
`endif
`ifndef cocotb_sim
input `real vlow,
input `real vhigh,
`else
input real vlow,
input real vhigh,
`endif input ena,
input b0,
input b1,
input b2,
input b3,
input b4,
input b5,
input b6,
input b7,
`ifndef cocotb_sim
output `real out
`else
output real out
`endif
);
`ifdef functional
`ifndef cocotb_sim
reg `real dacvalue;
`else
real dacvalue;
`endif
assign out = dacvalue;
initial begin
dacvalue <= 0;
end
always @* begin
if (ena == 1'b1) begin
dacvalue = vlow + {b7, b6, b5, b4, b3, b2, b1, b0} * (vhigh - vlow) / 255.0;
end else begin
dacvalue = 0.0;
end
end
`endif
endmodule |
module sar #(parameter size = 8) (
`ifdef use_power_pins
input dvdd,
input dvss,
`endif
input wire clk, input wire rst_n, input wire soc, input wire cmp, output wire hold, output wire [size-1:0] data, output wire eoc );
reg [1:0] rstn_sync;
wire rstn = rstn_sync[1];
always @(posedge clk)
rstn_sync[1:0] <= {rstn_sync[0], rstn};
reg [size-1:0] result;
reg [size-1:0] shift;
reg [1:0] state, nstate;
localparam idle = 0,
sample= 1,
conv = 2,
done = 3;
always @*
case (state)
idle : if(soc) nstate = sample;
else nstate = idle;
sample : nstate = conv;
conv : if(shift == 1'b1) nstate = done;
else nstate = conv;
done : nstate = idle;
default: nstate = idle;
endcase
always @(posedge clk or negedge rstn)
if(!rstn)
state <= idle;
else
state <= nstate;
always @(posedge clk)
if(state == idle)
shift <= 1'b1 << (size-1);
else if(state == conv)
shift<= shift >> 1;
wire [size-1:0] current = (cmp == 1'b0) ? ~shift : {size{1'b1}} ;
wire [size-1:0] next = shift >> 1;
always @(posedge clk)
if(state == idle)
result <= 1'b1 << (size-1);
else if(state == conv)
result <= (result | next) & current;
assign data = result;
assign eoc = (state==done);
assign hold = (state == conv);
endmodule |
module gradient_computation(
input wire clk,
input wire rst,
input wire [15:0] in, input wire [15:0] derivative, output wire [15:0] out );
reg [15:0] out_int;
always @(posedge clk or posedge rst) begin
if (rst) begin
out_int <= 16'h0;
end else begin
out_int <= in * derivative;
end
end
assign out = out_int;
endmodule |
module forward_prop (
input wire clk,
input wire rst,
input wire start,
input wire mmu_ready,
input wire [15:0] mmu_data,
input wire activate_ready,
input wire [15:0] activate_out,
output wire mmu_we,
output wire mmu_valid,
output wire [15:0] mmu_address,
output wire [15:0] activate_in,
output wire [1:0] activate_ctrl,
output wire done
);
localparam neuron_data_base_address = 16'h0000;
localparam weights_base_address = 16'h0100;
localparam biases_base_address = 16'h0200;
parameter idle = 3'b000;
parameter read_data = 3'b001;
parameter read_weights = 3'b010;
parameter read_biases = 3'b011;
parameter compute = 3'b100;
reg [1:0] layer_activation [0:3];
always @(posedge clk or posedge rst) begin
if (rst) begin
layer_activation[0] <= 2'b00; layer_activation[1] <= 2'b01; layer_activation[2] <= 2'b10; layer_activation[3] <= 2'b00; end
end
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] data_in, w, b, neuron_out; reg [4:0] neuron_counter; reg [1:0] layer_counter; reg done_signal;
reg [15:0] mmu_address_int;
reg mmu_valid_int;
reg mmu_we_int;
reg [15:0] activate_in_int;
reg [1:0] activate_ctrl_int;
always @(posedge clk or posedge rst) begin
if (rst) begin
neuron_counter <= 5'b0;
layer_counter <= 2'b0;
done_signal <= 1'b0;
end else if (state == compute && next_state == read_data && neuron_counter == 5'b110) begin
neuron_counter <= 5'b0;
layer_counter <= layer_counter + 1'b1;
end else if (state == compute && next_state == read_data) begin
neuron_counter <= neuron_counter + 1'b1;
end else if (state == compute && next_state == idle) begin
done_signal <= 1'b1;
end
end
always @(posedge clk or posedge rst) begin
if (rst)
state <= idle;
else
state <= next_state;
end
always @* begin
next_state = state;
case (state)
idle: if (start) next_state = read_data;
read_data: next_state = read_weights;
read_weights: next_state = read_biases;
read_biases: next_state = compute;
compute: next_state = (layer_counter == 2'b11 || (layer_counter != 2'b10 && neuron_counter == 5'b010)) ? idle : read_data;
default: next_state = idle;
endcase
end
always @(posedge clk) begin
case (state)
read_data: begin
mmu_address_int <= neuron_data_base_address + (layer_counter << 4) + neuron_counter;
mmu_valid_int <= 1;
mmu_we_int <= 0;
if (mmu_ready)
data_in <= mmu_data;
if (mmu_ready)
state <= read_weights;
end
read_weights: begin
mmu_address_int <= weights_base_address + (layer_counter << 4) + neuron_counter;
mmu_we_int <= 0;
mmu_valid_int <= 1;
if (mmu_ready)
w <= mmu_data;
if (mmu_ready)
state <= read_biases;
end
read_biases: begin
mmu_address_int <= biases_base_address + neuron_counter;
mmu_we_int <= 0;
mmu_valid_int <= 1;
if (mmu_ready)
b <= mmu_data;
if (mmu_ready)
state <= compute;
end
compute: begin
activate_in_int <= data_in * w + b;
activate_ctrl_int <= layer_activation[layer_counter];
mmu_valid_int <= 0;
if (activate_ready)
neuron_out <= activate_out;
if (activate_ready)
state <= idle;
end
default:;
endcase
end
assign mmu_address = mmu_address_int;
assign mmu_valid = mmu_valid_int;
assign mmu_we = mmu_we_int;
assign activate_in = activate_in_int;
assign activate_ctrl = activate_ctrl_int;
assign done = done_signal;
endmodule |
module mmu (
input wire clk,
input wire rst,
input wire [15:0] address,
input wire we,
input wire [15:0] data_in,
output reg [15:0] data_out
);
reg [15:0] neuron_data_memory [0:5];
reg [15:0] weights_memory [0:17];
reg [15:0] biases_memory [0:6];
always @(posedge clk or posedge rst) begin
if (rst) begin
data_out <= 16'h0;
end else if (we) begin
if (address < 16'h0100) begin
neuron_data_memory[address[3:0]] <= data_in;
end else if (address < 16'h0200) begin
weights_memory[address[4:0]] <= data_in;
end else begin
biases_memory[address[2:0]] <= data_in;
end
end else begin
if (address < 16'h0100) begin
data_out <= neuron_data_memory[address[3:0]];
end else if (address < 16'h0200) begin
data_out <= weights_memory[address[4:0]];
end else begin
data_out <= biases_memory[address[2:0]];
end
end
end
endmodule |
Subsets and Splits