text
stringlengths 21
997k
|
|---|
module f_228_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_2n6_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_5dp_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_5xc_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_5xx_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_60n_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_6n6_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_88r_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_cc9_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b01 :
2'b11;
endmodule |
module f_edcrc9dd4_bet (
input wire[1:0] portc,
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portc == 2'b01) & (portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b01) & (porta == 2'b11) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_h4k_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_he4_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_hhddxxddd_bet (
input wire[1:0] portc,
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portc == 2'b11) & (portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_k00 (
input wire portb,
input wire porta,
output wire out
);
assign out =
(portb == 1 & porta == 1);
endmodule |
module f_n28_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_ppppppzd0_bet (
input wire[1:0] portc,
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portc == 2'b01) & (portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b01) & (portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b01) & (portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b01) & (portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b01) & (portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b01) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b01) & (porta == 2'b11) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b11) & (portb == 2'b01) & (porta == 2'b10) ? 2'b01 :
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portc == 2'b10) & (portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b11) ? 2'b01 :
(portc == 2'b10) & (portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b01) & (porta == 2'b10) ? 2'b01 :
(portc == 2'b10) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_rdc_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_rrdrddddd_bet (
input wire[1:0] portc,
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portc == 2'b11) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portc == 2'b10) & (portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_rrd_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_xe2_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b01) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b10) & (porta == 2'b01) ? 2'b01 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module f_zd0pppppp_bet (
input wire[1:0] portc,
input wire[1:0] portb,
input wire[1:0] porta,
output reg[1:0] out
);
always @(posedge portc[1])
out <=
(porta == 2'b01) ? 2'b01 :
(porta == 2'b10) ? 2'b10 :
2'b11 ;
endmodule |
module f_zzr_bet (
input wire[1:0] portb,
input wire[1:0] porta,
output wire[1:0] out
);
assign out =
(portb == 2'b10) & (porta == 2'b01) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b11) ? 2'b10 :
(portb == 2'b01) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b11) & (porta == 2'b10) ? 2'b10 :
(portb == 2'b10) & (porta == 2'b10) ? 2'b10 :
2'b11;
endmodule |
module tt_um_loopback (
input wire [7:0] ui_in, output wire [7:0] uo_out, input wire [7:0] uio_in, output wire [7:0] uio_out, output wire [7:0] uio_oe, input wire ena,
input wire clk,
input wire rst_n
);
assign uo_out[6:0] = {7{ui_in[0]}};
assign uo_out[7] = &ui_in[7:4];
endmodule |
module tt_um_power_test (
input wire [7:0] ui_in, output wire [7:0] uo_out, input wire [7:0] uio_in, output wire [7:0] uio_out, output wire [7:0] uio_oe, input wire ena,
input wire clk,
input wire rst_n
);
assign uo_out[7:0] = ui_in[6:0] + uio_in[6:0];
assign uio_oe = 8'h00;
endmodule |
module tt_um_urish_sram_poc (
input wire [7:0] ui_in, output wire [7:0] uo_out, input wire [7:0] uio_in, output wire [7:0] uio_out, output wire [7:0] uio_oe, input wire ena,
input wire clk,
input wire rst_n,
output ram_clk0,
output ram_csb0, output ram_web0, output [3:0] ram_wmask0, output [8:0] ram_addr0, output [31:0] ram_din0, input [31:0] ram_dout0 );
reg [2:0] addr_high_reg;
wire bank_select = ui_in[6];
wire [5:0] addr_low = ui_in[5:0];
wire [2:0] addr_high_in = uio_in[2:0];
wire [8:0] addr = {bank_select ? addr_high_in : addr_high_reg, addr_low};
wire [1:0] byte_index = ui_in[1:0];
assign uio_oe = 8'b0; assign uio_out = 8'b0;
wire we = ui_in[7] && !bank_select;
wire we0 = we && (byte_index == 0);
wire we1 = we && (byte_index == 1);
wire we2 = we && (byte_index == 2);
wire we3 = we && (byte_index == 3);
wire [4:0] bit_index = {byte_index, 3'b000};
assign ram_din0 = {24'b0, uio_in} << bit_index;
reg [4:0] out_bit_index;
assign uo_out = ram_dout0[out_bit_index +: 8];
assign ram_clk0 = clk;
assign ram_csb0 = !rst_n;
assign ram_web0 = !we;
assign ram_wmask0 = {we3, we2, we1, we0};
assign ram_addr0 = {4'b0, addr[6:2]};
always @(posedge clk)
begin
if(rst_n) begin
out_bit_index <= bit_index;
addr_high_reg <= bank_select ? addr_high_in : addr_high_reg;
end else begin
out_bit_index <= 0;
addr_high_reg <= 0;
end
end
endmodule |
module input_sync(
input wire clk,
input wire d,
output wire q
);
reg dff1, dff2;
assign q = dff2;
always @(posedge clk) {dff2,dff1} <= {dff1,d};
endmodule |
module sky130_sram_2kbyte_1rw1r_32x512_8(
`ifdef use_power_pins
vccd1,
vssd1,
`endif
clk0,csb0,web0,wmask0,addr0,din0,dout0,
clk1,csb1,addr1,dout1
);
parameter num_wmasks = 4 ;
parameter data_width = 32 ;
parameter addr_width = 9 ;
parameter ram_depth = 1 << addr_width;
parameter delay = 3 ;
parameter verbose = 1 ; parameter t_hold = 1 ;
`ifdef use_power_pins
inout vccd1;
inout vssd1;
`endif
input clk0; input csb0; input web0; input [num_wmasks-1:0] wmask0; input [addr_width-1:0] addr0;
input [data_width-1:0] din0;
output [data_width-1:0] dout0;
input clk1; input csb1; input [addr_width-1:0] addr1;
output [data_width-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [num_wmasks-1:0] wmask0_reg;
reg [addr_width-1:0] addr0_reg;
reg [data_width-1:0] din0_reg;
reg [data_width-1:0] dout0;
always @(posedge clk0)
begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
#(t_hold) dout0 = 32'bx;
if ( !csb0_reg && web0_reg && verbose )
$display($time," reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
if ( !csb0_reg && !web0_reg && verbose )
$display($time," writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
end
reg csb1_reg;
reg [addr_width-1:0] addr1_reg;
reg [data_width-1:0] dout1;
always @(posedge clk1)
begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display($time," warning: writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
#(t_hold) dout1 = 32'bx;
if ( !csb1_reg && verbose )
$display($time," reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
end
reg [data_width-1:0] mem [0:ram_depth-1];
always @ (negedge clk0)
begin : mem_write0
if ( !csb0_reg && !web0_reg ) begin
if (wmask0_reg[0])
mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1])
mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2])
mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3])
mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
always @ (negedge clk0)
begin : mem_read0
if (!csb0_reg && web0_reg)
dout0 <= #(delay) mem[addr0_reg];
end
always @ (negedge clk1)
begin : mem_read1
if (!csb1_reg)
dout1 <= #(delay) mem[addr1_reg];
end
endmodule |
module sky130_fd_sc_hd__udp_mux_2to1 (
output wire x ,
input wire a0,
input wire a1,
input wire s
);
assign x = s ? a1 : a0;
endmodule |
module sky130_fd_sc_hd__udp_mux_4to2 (
output wire x ,
input wire a0,
input wire a1,
input wire a2,
input wire a3,
input wire s0,
input wire s1
);
wire [3:0] all_inputs;
wire [1:0] all_select;
assign all_inputs = {a3, a2, a1, a0};
assign all_select = {s1, s0};
assign x = all_inputs[all_select];
endmodule |
module sky130_fd_sc_hd__udp_mux_2to1_n (
output wire y ,
input wire a0,
input wire a1,
input wire s
);
assign y = ~(s ? a1 : a0);
endmodule |
module sky130_fd_sc_hd__udp_dlatch$lp_pp$pg$n (
output reg q ,
input wire d ,
input wire gate ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(*) begin
if (gate) q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dlatch$pr_pp$pg$n (
output reg q ,
input wire d ,
input wire gate ,
input wire reset ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(*) begin
if (reset) begin
q <= 'd0;
end if (gate) begin
q <= d;
end
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dlatch$p_pp$pg$n (
output reg q ,
input wire d ,
input wire gate ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(*) begin
if (gate) q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dff$p_pp$pg$n (
output reg q ,
input wire d ,
input wire clk ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(posedge clk) begin
q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dff$ps_pp$pg$n (
output reg q ,
input wire d ,
input wire clk ,
input wire set ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(posedge clk, posedge set) begin
if (set) begin
q <= 1'b1;
end else begin
q <= d;
end
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dff$pr_pp$pg$n (
output reg q ,
input wire d ,
input wire clk ,
input wire reset ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(posedge clk, posedge reset) begin
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_dff$nsr_pp$pg$n (
output reg q ,
input wire set ,
input wire reset ,
input wire clk_n ,
input wire d ,
input wire notifier,
input wire vpwr ,
input wire vgnd
);
always @(negedge clk_n, posedge reset, posedge set) begin
if (reset) begin
q <= 1'b0;
end else if (set) begin
q <= 1'b1;
end else begin
q <= d;
end
end
wire _unused;
assign _unused = &{ 1'b0, notifier, vpwr, vgnd };
endmodule |
module sky130_fd_sc_hd__udp_pwrgood_pp$g (
output wire udp_out,
input wire udp_in ,
input wire vgnd
);
assign udp_out = udp_in && !vgnd;
endmodule |
module sky130_fd_sc_hd__udp_pwrgood_pp$p (
output wire udp_out,
input wire udp_in ,
input wire vpwr
);
assign udp_out = udp_in && vpwr;
endmodule |
module sky130_fd_sc_hd__udp_pwrgood_pp$pg (
output wire udp_out,
input wire udp_in ,
input wire vpwr ,
input wire vgnd
);
assign udp_out = udp_in && vpwr && !vgnd;
endmodule |
module sky130_fd_sc_hd__udp_pwrgood$l_pp$pg (
output wire udp_out,
input wire udp_in ,
input wire vpwr ,
input wire vgnd
);
assign udp_out = udp_in && vpwr && !vgnd;
endmodule |
module sky130_fd_sc_hd__udp_pwrgood$l_pp$pg$s (
output wire udp_out,
input wire udp_in ,
input wire vpwr ,
input wire vgnd ,
input wire sleep
);
assign udp_out = udp_in && vpwr && !vgnd && !sleep;
endmodule |
module sky130_fd_sc_hd__a211o_1(
output wire x ,
input wire a1 ,
input wire a2 ,
input wire b1 ,
input wire c1 ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = ((a1 & a2) | b1 | c1);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__a31o_1(
output wire x ,
input wire a1 ,
input wire a2 ,
input wire a3 ,
input wire b1 ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = ((a1 & a2 & a3) | b1);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and2_1(
output wire x ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a & b;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and2_4(
output wire x ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a & b;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and2b_1(
output wire x ,
input wire a_n ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & b;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and2b_2(
output wire x ,
input wire a_n ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & b;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and3b_1(
output wire x ,
input wire a_n ,
input wire b ,
input wire c ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & b & c;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and3b_4(
output wire x ,
input wire a_n ,
input wire b ,
input wire c ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & b & c;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and4_1(
output wire x ,
input wire a ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a & b & c & d;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and4b_1(
output wire x ,
input wire a_n ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & b & c & d;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__and4bb_1(
output wire x ,
input wire a_n ,
input wire b_n ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = (~a_n) & (~b_n) & c & d;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__buf_1(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__buf_2(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__buf_4(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkinv_2(
output wire y ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkinv_4(
output wire y ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkbuf_2(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkbuf_4(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkbuf_8(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkdlybuf4s25_1(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkdlybuf4s50_1(
output wire x ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__clkinv_1(
output wire y ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dfrtp_4(
output reg q ,
input wire clk ,
input wire d ,
input wire reset_b,
input wire vpwr ,
input wire vgnd ,
input wire vpb ,
input wire vnb
);
wire reset = ~reset_b;
always @(posedge clk, posedge reset) begin
if (reset) q <= 'd0;
else q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dfrtn_1(
output reg q ,
input wire clk_n ,
input wire d ,
input wire reset_b,
input wire vpwr ,
input wire vgnd ,
input wire vpb ,
input wire vnb
);
wire clk = ~clk_n;
wire reset = ~reset_b;
always @(posedge clk, posedge reset) begin
if (reset) q <= 'd0;
else q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dfrtp_1(
output reg q ,
input wire clk ,
input wire d ,
input wire reset_b,
input wire vpwr ,
input wire vgnd ,
input wire vpb ,
input wire vnb
);
wire reset = ~reset_b;
always @(posedge clk, posedge reset) begin
if (reset) q <= 'd0;
else q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dfsbp_1(
output reg q ,
output wire q_n ,
input wire clk ,
input wire d ,
input wire set_b,
input wire vpwr ,
input wire vgnd ,
input wire vpb ,
input wire vnb
);
wire set = ~set_b;
always @(posedge clk, posedge set) begin
if (set) q <= 'd1;
else q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
assign q_n = ~q;
endmodule |
module sky130_fd_sc_hd__dfxtp_1(
output reg q ,
input wire clk ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
always @(posedge clk) begin
q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dfxtp_4(
output reg q ,
input wire clk ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
always @(posedge clk) begin
q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dlclkp_1(
output wire gclk,
input wire gate,
input wire clk ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
reg gate_q;
always @(negedge clk) gate_q <= gate;
assign gclk = gate_q & clk;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dlxtn_1(
output reg q ,
input wire d ,
input wire gate_n,
input wire vpwr ,
input wire vgnd ,
input wire vpb ,
input wire vnb
);
always @(gate_n, d) begin
if (~gate_n) q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__dlxtp_1(
output reg q ,
input wire d ,
input wire gate,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
always @(gate, d) begin
if (gate) q <= d;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__ebufn_1(
output wire z ,
input wire a ,
input wire te_b,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign z = (~te_b) ? a : 1'dz;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__einvp_2(
output wire z ,
input wire a ,
input wire te ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign z = te ? (~a) : 1'dz;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__fa_1(
output wire cout,
output wire sum ,
input wire a ,
input wire b ,
input wire cin ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign { cout, sum } = (a + b + cin);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__fa_2(
output wire cout,
output wire sum ,
input wire a ,
input wire b ,
input wire cin ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign { cout, sum } = (a + b + cin);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__inv_1(
output wire y ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__inv_4(
output wire y ,
input wire a ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~a;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__mux2_1(
output wire x ,
input wire a0 ,
input wire a1 ,
input wire s ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = s ? a1 : a0;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__mux2i_1(
output wire y ,
input wire a0 ,
input wire a1 ,
input wire s ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(s ? a1 : a0);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__mux4_1(
output wire x ,
input wire a0 ,
input wire a1 ,
input wire a2 ,
input wire a3 ,
input wire s0 ,
input wire s1 ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
wire [3:0] choices = { a3, a2, a1, a0 };
wire [1:0] selects = { s1, s0 };
assign x = choices[selects];
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand2_1(
output wire y ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a & b);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand2_2(
output wire y ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a & b);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand3_2(
output wire y ,
input wire a ,
input wire b ,
input wire c ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a & b & c);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand4_1(
output wire y ,
input wire a ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a & b & c & d);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand4b_1(
output wire y ,
input wire a_n ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~((~a_n) & b & c & d);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nand4bb_1(
output wire y ,
input wire a_n ,
input wire b_n ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~((~a_n) & (~b_n) & c & d);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nor2_1(
output wire y ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a | b);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nor4_1(
output wire y ,
input wire a ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a | b | c | d);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__nor4b_1(
output wire y ,
input wire a ,
input wire b ,
input wire c ,
input wire d_n ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign y = ~(a | b | c | (~d_n));
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__o21a_1(
output wire x ,
input wire a1 ,
input wire a2 ,
input wire b1 ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = ((a1 | a2) & b1);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__or4_1(
output wire x ,
input wire a ,
input wire b ,
input wire c ,
input wire d ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a | b | c | d;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__or4b_1(
output wire x ,
input wire a ,
input wire b ,
input wire c ,
input wire d_n ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a | b | c | (~d_n);
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__sdfxtp_1(
output reg q ,
input wire clk ,
input wire d ,
input wire scd ,
input wire sce ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
wire choice;
assign choice = sce ? scd : d;
always @(posedge clk) begin
q <= choice;
end
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module sky130_fd_sc_hd__xor2_1(
output wire x ,
input wire a ,
input wire b ,
input wire vpwr,
input wire vgnd,
input wire vpb ,
input wire vnb
);
assign x = a ^ b;
wire _unused;
assign _unused = &{ 1'b0, vpwr, vgnd, vpb, vnb };
endmodule |
module bufg
`ifdef xil_timing
#(
parameter loc = "unplaced"
)
`endif
(
output o,
input i
);
localparam module_name = "bufg";
`ifdef xil_timing
reg notifier;
`endif
buf b1 (o, i);
`ifndef xil_xeclib
`ifdef xil_timing
specify
(i => o) = (0:0:0, 0:0:0);
$period (negedge i, 0:0:0, notifier);
$period (posedge i, 0:0:0, notifier);
specparam pathpulse$ = 0;
endspecify
`endif
`endif
endmodule |
module bufh (o, i);
`ifdef xil_timing
parameter loc = " unplaced";
reg notifier;
`endif
output o;
input i;
buf b1 (o, i);
`ifdef xil_timing
specify
(i => o) = (0:0:0, 0:0:0);
$period (posedge i, 0:0:0, notifier);
specparam pathpulse$ = 0;
endspecify
`endif
endmodule |
module sirv_pwm16_core(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countlo_write_valid,
input [31:0] io_regs_countlo_write_bits,
output [31:0] io_regs_countlo_read,
input io_regs_counthi_write_valid,
input [31:0] io_regs_counthi_write_bits,
output [31:0] io_regs_counthi_read,
input io_regs_s_write_valid,
input [15:0] io_regs_s_write_bits,
output [15:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [15:0] io_regs_cmp_0_write_bits,
output [15:0] io_regs_cmp_0_read,
input io_regs_cmp_1_write_valid,
input [15:0] io_regs_cmp_1_write_bits,
output [15:0] io_regs_cmp_1_read,
input io_regs_cmp_2_write_valid,
input [15:0] io_regs_cmp_2_write_bits,
output [15:0] io_regs_cmp_2_read,
input io_regs_cmp_3_write_valid,
input [15:0] io_regs_cmp_3_write_bits,
output [15:0] io_regs_cmp_3_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
output io_ip_1,
output io_ip_2,
output io_ip_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire [3:0] t_178;
reg [3:0] scale;
reg [31:0] gen_22;
wire [3:0] gen_0;
reg [15:0] cmp_0;
reg [31:0] gen_23;
wire [15:0] gen_1;
reg [15:0] cmp_1;
reg [31:0] gen_24;
wire [15:0] gen_2;
reg [15:0] cmp_2;
reg [31:0] gen_25;
wire [15:0] gen_3;
reg [15:0] cmp_3;
reg [31:0] gen_26;
wire [15:0] gen_4;
wire counten;
reg [4:0] t_196;
reg [31:0] gen_27;
wire [4:0] gen_18;
wire [5:0] t_197;
reg [25:0] t_199;
reg [31:0] gen_28;
wire t_200;
wire [26:0] t_202;
wire [26:0] gen_5;
wire [30:0] t_203;
wire [32:0] t_207;
wire [27:0] t_208;
wire [32:0] gen_6;
wire [27:0] gen_7;
wire [30:0] t_209;
wire [15:0] s;
wire t_210;
wire [3:0] t_211;
reg [3:0] center;
reg [31:0] gen_29;
wire [3:0] gen_8;
wire t_215;
wire t_216;
wire [15:0] t_217;
wire [15:0] t_218;
wire elapsed_0;
wire t_220;
wire t_221;
wire [15:0] t_223;
wire elapsed_1;
wire t_225;
wire t_226;
wire [15:0] t_228;
wire elapsed_2;
wire t_230;
wire t_231;
wire [15:0] t_233;
wire elapsed_3;
wire [5:0] gen_19;
wire [5:0] t_234;
wire [4:0] t_235;
wire [26:0] gen_20;
wire [26:0] t_239;
wire [26:0] t_241;
wire [25:0] t_242;
wire [30:0] t_243;
wire [4:0] gen_21;
wire [5:0] t_245;
wire [4:0] t_246;
wire [30:0] t_247;
wire feed;
wire t_248;
reg zerocmp;
reg [31:0] gen_30;
wire gen_9;
wire t_252;
wire countreset;
wire [32:0] gen_10;
wire [27:0] gen_11;
wire t_255;
reg t_259;
reg [31:0] gen_31;
wire gen_12;
wire t_261;
wire t_262;
wire t_263;
reg t_267;
reg [31:0] gen_32;
wire gen_13;
wire t_268;
reg t_269;
reg [31:0] gen_33;
wire [1:0] t_282;
wire [1:0] t_283;
wire [3:0] t_284;
reg [3:0] ip;
reg [31:0] gen_34;
wire [1:0] t_286;
wire [1:0] t_287;
wire [3:0] t_288;
wire [3:0] t_289;
wire [3:0] t_290;
wire [3:0] t_297;
wire [3:0] t_298;
wire [3:0] t_299;
wire [3:0] t_300;
wire [3:0] t_301;
wire [3:0] t_304;
wire [3:0] gen_14;
wire [3:0] t_305;
reg [3:0] gang;
reg [31:0] gen_35;
wire [3:0] gen_15;
wire t_316;
wire t_319;
wire t_323;
reg oneshot;
reg [31:0] gen_36;
wire gen_16;
wire t_325;
reg countalways;
reg [31:0] gen_37;
wire gen_17;
wire [4:0] t_333;
wire [8:0] t_334;
wire [1:0] t_335;
wire [2:0] t_336;
wire [11:0] t_337;
wire [2:0] t_338;
wire [3:0] t_339;
wire [7:0] t_340;
wire [7:0] t_341;
wire [15:0] t_342;
wire [19:0] t_343;
wire [31:0] t_344;
wire t_350_0;
wire t_350_1;
wire t_350_2;
wire t_350_3;
wire t_352;
wire t_353;
wire t_354;
wire t_355;
wire [2:0] t_357;
wire [3:0] t_358;
wire [3:0] t_359;
wire [3:0] t_360;
wire [3:0] t_361;
wire t_364_0;
wire t_364_1;
wire t_364_2;
wire t_364_3;
wire t_366;
wire t_367;
wire t_368;
wire t_369;
wire t_370;
assign io_regs_cfg_read = t_344;
assign io_regs_countlo_read = {{1'd0}, t_203};
assign io_regs_counthi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_cmp_1_read = cmp_1;
assign io_regs_cmp_2_read = cmp_2;
assign io_regs_cmp_3_read = cmp_3;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = t_350_0;
assign io_ip_1 = t_350_1;
assign io_ip_2 = t_350_2;
assign io_ip_3 = t_350_3;
assign io_gpio_0 = t_364_0;
assign io_gpio_1 = t_364_1;
assign io_gpio_2 = t_364_2;
assign io_gpio_3 = t_364_3;
assign t_178 = io_regs_cfg_write_bits[3:0];
assign gen_0 = io_regs_cfg_write_valid ? t_178 : scale;
assign gen_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign gen_2 = io_regs_cmp_1_write_valid ? io_regs_cmp_1_write_bits : cmp_1;
assign gen_3 = io_regs_cmp_2_write_valid ? io_regs_cmp_2_write_bits : cmp_2;
assign gen_4 = io_regs_cmp_3_write_valid ? io_regs_cmp_3_write_bits : cmp_3;
assign counten = t_370;
assign gen_18 = {{4'd0}, counten};
assign t_197 = t_196 + gen_18;
assign t_200 = t_197[5];
assign t_202 = t_199 + 26'h1;
assign gen_5 = t_200 ? t_202 : {{1'd0}, t_199};
assign t_203 = {t_199,t_196};
assign t_207 = {1'h0,io_regs_countlo_write_bits};
assign t_208 = t_207[32:5];
assign gen_6 = io_regs_countlo_write_valid ? t_207 : {{27'd0}, t_197};
assign gen_7 = io_regs_countlo_write_valid ? t_208 : {{1'd0}, gen_5};
assign t_209 = t_203 >> scale;
assign s = t_209[15:0];
assign t_210 = s[15];
assign t_211 = io_regs_cfg_write_bits[19:16];
assign gen_8 = io_regs_cfg_write_valid ? t_211 : center;
assign t_215 = center[0];
assign t_216 = t_210 & t_215;
assign t_217 = ~ s;
assign t_218 = t_216 ? t_217 : s;
assign elapsed_0 = t_218 >= cmp_0;
assign t_220 = center[1];
assign t_221 = t_210 & t_220;
assign t_223 = t_221 ? t_217 : s;
assign elapsed_1 = t_223 >= cmp_1;
assign t_225 = center[2];
assign t_226 = t_210 & t_225;
assign t_228 = t_226 ? t_217 : s;
assign elapsed_2 = t_228 >= cmp_2;
assign t_230 = center[3];
assign t_231 = t_210 & t_230;
assign t_233 = t_231 ? t_217 : s;
assign elapsed_3 = t_233 >= cmp_3;
assign gen_19 = {{1'd0}, t_196};
assign t_234 = gen_19 ^ t_197;
assign t_235 = t_234[5:1];
assign gen_20 = {{1'd0}, t_199};
assign t_239 = gen_20 ^ t_202;
assign t_241 = t_200 ? t_239 : 27'h0;
assign t_242 = t_241[26:1];
assign t_243 = {t_242,t_235};
assign gen_21 = {{1'd0}, scale};
assign t_245 = gen_21 + 5'h10;
assign t_246 = t_245[4:0];
assign t_247 = t_243 >> t_246;
assign feed = t_247[0];
assign t_248 = io_regs_cfg_write_bits[9];
assign gen_9 = io_regs_cfg_write_valid ? t_248 : zerocmp;
assign t_252 = zerocmp & elapsed_0;
assign countreset = feed | t_252;
assign gen_10 = countreset ? 33'h0 : gen_6;
assign gen_11 = countreset ? 28'h0 : gen_7;
assign t_255 = io_regs_cfg_write_bits[10];
assign gen_12 = io_regs_cfg_write_valid ? t_255 : t_259;
assign t_261 = countreset == 1'h0;
assign t_262 = t_259 & t_261;
assign t_263 = io_regs_cfg_write_bits[8];
assign gen_13 = io_regs_cfg_write_valid ? t_263 : t_267;
assign t_268 = t_262 | t_267;
assign t_282 = {t_221,t_216};
assign t_283 = {t_231,t_226};
assign t_284 = {t_283,t_282};
assign t_286 = {elapsed_1,elapsed_0};
assign t_287 = {elapsed_3,elapsed_2};
assign t_288 = {t_287,t_286};
assign t_289 = t_284 & t_288;
assign t_290 = ~ t_284;
assign t_297 = t_269 ? 4'hf : 4'h0;
assign t_298 = t_297 & ip;
assign t_299 = t_288 | t_298;
assign t_300 = t_290 & t_299;
assign t_301 = t_289 | t_300;
assign t_304 = io_regs_cfg_write_bits[31:28];
assign gen_14 = io_regs_cfg_write_valid ? t_304 : t_301;
assign t_305 = io_regs_cfg_write_bits[27:24];
assign gen_15 = io_regs_cfg_write_valid ? t_305 : gang;
assign t_316 = io_regs_cfg_write_bits[13];
assign t_319 = t_316 & t_261;
assign t_323 = io_regs_cfg_write_valid | countreset;
assign gen_16 = t_323 ? t_319 : oneshot;
assign t_325 = io_regs_cfg_write_bits[12];
assign gen_17 = io_regs_cfg_write_valid ? t_325 : countalways;
assign t_333 = {t_267,4'h0};
assign t_334 = {t_333,scale};
assign t_335 = {1'h0,t_259};
assign t_336 = {t_335,zerocmp};
assign t_337 = {t_336,t_334};
assign t_338 = {2'h0,oneshot};
assign t_339 = {t_338,countalways};
assign t_340 = {4'h0,center};
assign t_341 = {ip,gang};
assign t_342 = {t_341,t_340};
assign t_343 = {t_342,t_339};
assign t_344 = {t_343,t_337};
assign t_350_0 = t_352;
assign t_350_1 = t_353;
assign t_350_2 = t_354;
assign t_350_3 = t_355;
assign t_352 = ip[0];
assign t_353 = ip[1];
assign t_354 = ip[2];
assign t_355 = ip[3];
assign t_357 = ip[3:1];
assign t_358 = {t_352,t_357};
assign t_359 = gang & t_358;
assign t_360 = ~ t_359;
assign t_361 = ip & t_360;
assign t_364_0 = t_366;
assign t_364_1 = t_367;
assign t_364_2 = t_368;
assign t_364_3 = t_369;
assign t_366 = t_361[0];
assign t_367 = t_361[1];
assign t_368 = t_361[2];
assign t_369 = t_361[3];
assign t_370 = countalways | oneshot;
always @(posedge clock or posedge reset)
if(reset) begin
scale <= 4'b0;
cmp_0 <= 16'b0;
cmp_1 <= 16'b0;
cmp_2 <= 16'b0;
cmp_3 <= 16'b0;
t_196 <= 5'b0;
t_199 <= 26'b0;
center <= 4'b0;
zerocmp <= 1'b0;
t_259 <= 1'b0;
t_267 <= 1'b0;
t_269 <= 1'b0;
ip <= 4'b0;
gang <= 4'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= t_178;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
if (io_regs_cmp_1_write_valid) begin
cmp_1 <= io_regs_cmp_1_write_bits;
end
if (io_regs_cmp_2_write_valid) begin
cmp_2 <= io_regs_cmp_2_write_bits;
end
if (io_regs_cmp_3_write_valid) begin
cmp_3 <= io_regs_cmp_3_write_bits;
end
t_196 <= gen_10[4:0];
t_199 <= gen_11[25:0];
if (io_regs_cfg_write_valid) begin
center <= t_211;
end
if (io_regs_cfg_write_valid) begin
zerocmp <= t_248;
end
if (io_regs_cfg_write_valid) begin
t_259 <= t_255;
end
if (io_regs_cfg_write_valid) begin
t_267 <= t_263;
end
t_269 <= t_268;
if (io_regs_cfg_write_valid) begin
ip <= t_304;
end else begin
ip <= t_301;
end
if (io_regs_cfg_write_valid) begin
gang <= t_305;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
oneshot <= 1'h0;
end else begin
if (t_323) begin
oneshot <= t_319;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
countalways <= 1'h0;
end else begin
if (io_regs_cfg_write_valid) begin
countalways <= t_325;
end
end
endmodule |
module glbl ();
parameter roc_width = 100000;
parameter toc_width = 0;
wire gsr;
wire gts;
wire gwe;
wire prld;
tri1 p_up_tmp;
tri (weak1, strong0) pll_lockg = p_up_tmp;
wire progb_glbl;
wire cclko_glbl;
wire fcsbo_glbl;
wire [3:0] do_glbl;
wire [3:0] di_glbl;
reg gsr_int;
reg gts_int;
reg prld_int;
wire jtag_tdo_glbl;
wire jtag_tck_glbl;
wire jtag_tdi_glbl;
wire jtag_tms_glbl;
wire jtag_trst_glbl;
reg jtag_capture_glbl;
reg jtag_reset_glbl;
reg jtag_shift_glbl;
reg jtag_update_glbl;
reg jtag_runtest_glbl;
reg jtag_sel1_glbl = 0;
reg jtag_sel2_glbl = 0 ;
reg jtag_sel3_glbl = 0;
reg jtag_sel4_glbl = 0;
reg jtag_user_tdo1_glbl = 1'bz;
reg jtag_user_tdo2_glbl = 1'bz;
reg jtag_user_tdo3_glbl = 1'bz;
reg jtag_user_tdo4_glbl = 1'bz;
assign (strong1, weak0) gsr = gsr_int;
assign (strong1, weak0) gts = gts_int;
assign (weak1, weak0) prld = prld_int;
initial begin
gsr_int = 1'b1;
prld_int = 1'b1;
#(roc_width)
gsr_int = 1'b0;
prld_int = 1'b0;
end
initial begin
gts_int = 1'b1;
#(toc_width)
gts_int = 1'b0;
end
endmodule |
Subsets and Splits