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module bits_to_bytes
(
input clock,
input enable,
input reset,
input bit_in,
input input_strobe,
output reg [7:0] byte_out,
output reg output_strobe
);
reg [7:0] bit_buf;
reg [2:0] addr;
always @(posedge clock) begin
if (reset) begin
addr <= 0;
bit_buf <= 0;
byte_out <= 0;
output_strobe <= 0;
end else if (enable & input_strobe) begin
bit_buf[7] <= bit_in;
bit_buf[6:0] <= bit_buf[7:1];
addr <= addr + 1;
if (addr == 7) begin
byte_out <= {bit_in, bit_buf[7:1]};
output_strobe <= 1;
end else begin
output_strobe <= 0;
end
end else begin
output_strobe <= 0;
end
end
endmodule |
module calc_mean
(
input clock,
input enable,
input reset,
input signed [15:0] a,
input signed [15:0] b,
input sign,
input input_strobe,
output reg signed [15:0] c,
output reg output_strobe
);
reg signed [15:0] aa;
reg signed [15:0] bb;
reg signed [15:0] cc;
reg [1:0] delay;
reg [1:0] sign_stage;
always @(posedge clock) begin
if (reset) begin
aa <= 0;
bb <= 0;
cc <= 0;
c <= 0;
output_strobe <= 0;
delay <= 0;
end else if (enable) begin
delay[0] <= input_strobe;
delay[1] <= delay[0];
output_strobe <= delay[1];
sign_stage[1] <= sign_stage[0];
sign_stage[0] <= sign;
aa <= a>>>1;
bb <= b>>>1;
cc <= aa + bb;
c <= sign_stage[1]? ~cc+1: cc;
end
end
endmodule |
module sky130_sram_1kbyte_1rw1r_32x256_8(
`ifdef use_power_pins
vccd1,
vssd1,
`endif
clk0,csb0,web0,wmask0,addr0,din0,dout0,
clk1,csb1,addr1,dout1
);
parameter num_wmasks = 4 ;
parameter data_width = 32 ;
parameter addr_width = 8 ;
parameter ram_depth = 1 << addr_width;
parameter delay = 3 ;
parameter verbose = 1 ; parameter t_hold = 1 ;
`ifdef use_power_pins
inout vccd1;
inout vssd1;
`endif
input clk0; input csb0; input web0; input [num_wmasks-1:0] wmask0; input [addr_width-1:0] addr0;
input [data_width-1:0] din0;
output [data_width-1:0] dout0;
input clk1; input csb1; input [addr_width-1:0] addr1;
output [data_width-1:0] dout1;
endmodule |
module usb_ep(
input clk,
input direction_in,
input setup,
input success,
input[6:0] cnt,
output reg toggle,
output bank_usb,
output reg[1:0] handshake,
output bank_in,
output bank_out,
output in_data_valid,
input ctrl_dir_in,
output reg[15:0] ctrl_rd_data,
input[15:0] ctrl_wr_data,
input[1:0] ctrl_wr_en
);
localparam
hs_ack = 2'b00,
hs_none = 2'b01,
hs_nak = 2'b10,
hs_stall = 2'b11;
reg ep_setup;
reg ep_out_full;
reg ep_out_empty;
reg ep_in_full;
reg ep_out_stall;
reg ep_in_stall;
reg ep_out_toggle;
reg ep_in_toggle;
reg[6:0] ep_in_cnt;
reg[6:0] ep_out_cnt;
assign in_data_valid = (cnt != ep_in_cnt);
assign bank_usb = 1'b0;
assign bank_in = 1'b0;
assign bank_out = 1'b0;
always @(*) begin
if (!direction_in && setup)
toggle = 1'b0;
else if (ep_setup)
toggle = 1'b1;
else if (direction_in)
toggle = ep_in_toggle;
else
toggle = ep_out_toggle;
end
always @(*) begin
if (direction_in) begin
if (!ep_in_stall && !ep_setup && ep_in_full) begin
handshake = hs_ack;
end else if (!ep_setup && ep_in_stall) begin
handshake = hs_stall;
end else begin
handshake = hs_nak;
end
end else begin
if (setup || (!ep_out_stall && !ep_setup && ep_out_full)) begin
handshake = hs_ack;
end else if (!ep_setup && ep_out_stall) begin
handshake = hs_stall;
end else begin
handshake = hs_nak;
end
end
end
always @(*) begin
if (ctrl_dir_in) begin
ctrl_rd_data[15:8] = ep_in_cnt;
ctrl_rd_data[7:0] = { ep_in_toggle, ep_in_stall, 1'b0, !ep_in_full, ep_in_full };
end else begin
ctrl_rd_data[15:8] = ep_out_cnt;
ctrl_rd_data[7:0] = { ep_out_toggle, ep_out_stall, ep_setup, ep_out_empty, ep_out_full };
end
end
wire flush = ctrl_wr_data[5] || ctrl_wr_data[4] || ctrl_wr_data[3];
always @(posedge clk) begin
if (success) begin
if (direction_in) begin
ep_in_full <= 1'b0;
ep_in_toggle <= !ep_in_toggle;
end else begin
if (setup)
ep_setup <= 1'b1;
ep_out_toggle <= !ep_out_toggle;
ep_out_empty <= 1'b0;
ep_out_full <= 1'b0;
ep_out_cnt <= cnt;
end
end
if (ctrl_wr_en[1] && ctrl_dir_in) begin
ep_in_cnt <= ctrl_wr_data[14:8];
end
if (ctrl_wr_en[0] && ctrl_dir_in) begin
if (ctrl_wr_data[5]) begin
ep_in_toggle <= 1'b0;
ep_in_stall <= 1'b0;
end
if (ctrl_wr_data[4]) begin
ep_in_toggle <= 1'b1;
ep_in_stall <= 1'b0;
end
if (ctrl_wr_data[3])
ep_in_stall <= 1'b1;
if (flush)
ep_in_full <= 1'b0;
if (ctrl_wr_data[0])
ep_in_full <= 1'b1;
end
if (ctrl_wr_en[0] && !ctrl_dir_in) begin
if (ctrl_wr_data[5]) begin
ep_out_toggle <= 1'b0;
ep_out_stall <= 1'b0;
end
if (ctrl_wr_data[4]) begin
ep_out_toggle <= 1'b1;
ep_out_stall <= 1'b0;
end
if (ctrl_wr_data[3])
ep_out_stall <= 1'b1;
if (flush) begin
ep_out_full <= 1'b0;
ep_out_empty <= 1'b1;
end
if (ctrl_wr_data[2])
ep_setup <= 1'b0;
if (ctrl_wr_data[1])
ep_out_empty <= 1'b1;
if (ctrl_wr_data[0])
ep_out_full <= 1'b1;
end
end
endmodule |
module usb_ep_banked(
input clk,
input direction_in,
input setup,
input success,
input[6:0] cnt,
output reg toggle,
output bank_usb,
output reg[1:0] handshake,
output bank_in,
output bank_out,
output in_data_valid,
input ctrl_dir_in,
output reg[15:0] ctrl_rd_data,
input[15:0] ctrl_wr_data,
input[1:0] ctrl_wr_en
);
localparam
hs_ack = 2'b00,
hs_none = 2'b01,
hs_nak = 2'b10,
hs_stall = 2'b11;
reg ep_setup;
reg ep_out_full;
reg ep_out_empty;
reg ep_in_empty;
reg ep_out_stall;
reg ep_in_stall;
reg ep_out_toggle;
reg ep_in_toggle;
reg ep_in_bank;
reg[6:0] ep_in_cnt_0;
reg[6:0] ep_in_cnt_1;
reg[6:0] ep_out_cnt;
assign in_data_valid = (cnt != (ep_in_toggle? ep_in_cnt_1: ep_in_cnt_0));
assign bank_usb = direction_in? ep_in_toggle: 1'b0;
assign bank_in = ep_in_bank;
assign bank_out = 1'b0;
always @(*) begin
if (!direction_in && setup)
toggle = 1'b0;
else if (ep_setup)
toggle = 1'b1;
else if (direction_in)
toggle = ep_in_toggle;
else
toggle = ep_out_toggle;
end
always @(*) begin
if (direction_in) begin
if (!ep_in_stall && !ep_setup && !ep_in_empty) begin
handshake = hs_ack;
end else if (!ep_setup && ep_in_stall) begin
handshake = hs_stall;
end else begin
handshake = hs_nak;
end
end else begin
if (setup || (!ep_out_stall && !ep_setup && ep_out_full)) begin
handshake = hs_ack;
end else if (!ep_setup && ep_out_stall) begin
handshake = hs_stall;
end else begin
handshake = hs_nak;
end
end
end
always @(*) begin
if (ctrl_dir_in) begin
ctrl_rd_data[15:8] = ep_in_bank? ep_in_cnt_1: ep_in_cnt_0;
ctrl_rd_data[7:0] = { ep_in_bank, ep_in_toggle, ep_in_stall, 1'b0, ep_in_empty, !ep_in_empty && ep_in_toggle == ep_in_bank };
end else begin
ctrl_rd_data[15:8] = ep_out_cnt;
ctrl_rd_data[7:0] = { ep_out_toggle, ep_out_stall, ep_setup, ep_out_empty, ep_out_full };
end
end
wire flush = ctrl_wr_data[5] || ctrl_wr_data[4] || ctrl_wr_data[3];
always @(posedge clk) begin
if (success) begin
if (direction_in) begin
if (ep_in_toggle != ep_in_bank)
ep_in_empty <= 1'b1;
ep_in_toggle = !ep_in_toggle;
end else begin
if (setup)
ep_setup <= 1'b1;
ep_out_toggle = !ep_out_toggle;
ep_out_empty <= 1'b0;
ep_out_cnt <= cnt;
end
end
if (ctrl_wr_en[1] && ctrl_dir_in) begin
if (ep_in_bank)
ep_in_cnt_1 <= ctrl_wr_data[14:8];
else
ep_in_cnt_0 <= ctrl_wr_data[14:8];
end
if (ctrl_wr_en[0] && ctrl_dir_in) begin
if (ctrl_wr_data[5]) begin
ep_in_toggle = 1'b0;
ep_in_stall <= 1'b0;
ep_in_bank <= 1'b0;
end
if (ctrl_wr_data[4]) begin
ep_in_toggle = 1'b1;
ep_in_stall <= 1'b0;
ep_in_bank <= 1'b1;
end
if (ctrl_wr_data[3]) begin
ep_in_stall <= 1'b1;
ep_in_bank <= ep_in_toggle;
end
if (flush) begin
ep_in_empty <= 1'b1;
end
if (ctrl_wr_data[0]) begin
ep_in_empty <= 1'b0;
ep_in_bank <= !ep_in_bank;
end
end
if (ctrl_wr_en[0] && !ctrl_dir_in) begin
if (ctrl_wr_data[5]) begin
ep_out_toggle = 1'b0;
ep_out_stall <= 1'b0;
end
if (ctrl_wr_data[4]) begin
ep_out_toggle = 1'b1;
ep_out_stall <= 1'b0;
end
if (ctrl_wr_data[3])
ep_out_stall <= 1'b1;
if (flush) begin
ep_out_full <= 1'b0;
ep_out_empty <= 1'b1;
end
if (ctrl_wr_data[2])
ep_setup <= 1'b0;
if (ctrl_wr_data[1]) begin
ep_out_empty <= 1'b1;
ep_out_full <= 1'b0;
end
if (ctrl_wr_data[0])
ep_out_full <= 1'b1;
end
end
endmodule |
module usb_crc5(
input rst_n,
input clk,
input clken,
input d,
output valid
);
reg[4:0] r;
reg[4:0] next;
wire top = r[4];
assign valid = (next == 5'b01100);
always @(*) begin
if (top == d)
next = { r[3], r[2], r[1], r[0], 1'b0 };
else
next = { r[3], r[2], !r[1], r[0], 1'b1 };
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r <= 5'b11111;
end else if (clken) begin
r <= next;
end
end
endmodule |
module usb_crc16(
input rst_n,
input clk,
input clken,
input d,
input dump,
output out,
output valid
);
reg[15:0] r;
reg[15:0] next;
assign out = r[15];
assign valid = (next == 16'b1000000000001101);
always @(*) begin
if (dump || out == d)
next = { r[14:0], 1'b0 };
else
next = { !r[14], r[13:2], !r[1], r[0], 1'b1 };
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r <= 16'hffff;
end else if (clken) begin
r <= next;
end
end
endmodule |
module usb_clk_recovery(
input rst_n,
input clk,
input i,
output strobe
);
reg[1:0] cntr;
reg prev_i;
assign strobe = cntr == 1'b0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cntr <= 1'b0;
prev_i <= 1'b0;
end else begin
if (i == prev_i) begin
cntr <= cntr - 1'b1;
end else begin
cntr <= 1'b1;
end
prev_i <= i;
end
end
endmodule |
module usb_bit_destuff(
input rst_n,
input clk,
input clken,
input d,
output strobe);
reg[6:0] data;
assign strobe = clken && (data != 7'b0111111);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data <= 7'b0000000;
end else if (clken) begin
data <= { data[5:0], d };
end
end
endmodule |
module usb_sync_detect(
input rst_n,
input clk,
input clken,
input j,
input se0,
output sync);
reg[6:0] data;
assign sync = (data == 7'b0101010 && !j && !se0);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data <= 1'd0;
end else if (clken) begin
data <= { data[5:0], j || se0 };
end
end
endmodule |
module usb_reset_detect(
input rst_n,
input clk,
input se0,
output usb_rst);
reg[18:0] cntr;
assign usb_rst = cntr == 1'b0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cntr <= 1'b0;
end else begin
if (se0) begin
if (!usb_rst)
cntr <= cntr - 1'b1;
end else begin
cntr <= 19'd480000;
end
end
end
endmodule |
module multisample3(
input clk,
input in,
output reg out
);
reg[2:0] r;
always @(r) begin
case (r)
3'b000: out = 1'b0;
3'b001: out = 1'b0;
3'b010: out = 1'b0;
3'b011: out = 1'b1;
3'b100: out = 1'b0;
3'b101: out = 1'b1;
3'b110: out = 1'b1;
3'b111: out = 1'b1;
endcase
end
always @(posedge clk) begin
r <= { r[1:0], in };
end
endmodule |
module multisample5(
input clk,
input in,
output reg out
);
reg[4:0] r;
always @(r) begin
case (r)
5'b00000: out = 1'b0;
5'b00001: out = 1'b0;
5'b00010: out = 1'b0;
5'b00011: out = 1'b0;
5'b00100: out = 1'b0;
5'b00101: out = 1'b0;
5'b00110: out = 1'b0;
5'b00111: out = 1'b1;
5'b01000: out = 1'b0;
5'b01001: out = 1'b0;
5'b01010: out = 1'b0;
5'b01011: out = 1'b1;
5'b01100: out = 1'b0;
5'b01101: out = 1'b1;
5'b01110: out = 1'b1;
5'b01111: out = 1'b1;
5'b10000: out = 1'b0;
5'b10001: out = 1'b0;
5'b10010: out = 1'b0;
5'b10011: out = 1'b1;
5'b10100: out = 1'b0;
5'b10101: out = 1'b1;
5'b10110: out = 1'b1;
5'b10111: out = 1'b1;
5'b11000: out = 1'b0;
5'b11001: out = 1'b1;
5'b11010: out = 1'b1;
5'b11011: out = 1'b1;
5'b11100: out = 1'b1;
5'b11101: out = 1'b1;
5'b11110: out = 1'b1;
5'b11111: out = 1'b1;
endcase
end
always @(posedge clk) begin
r <= { r[3:0], in };
end
endmodule |
module nrzi_decode(
input clk,
input clken,
input i,
output o
);
reg prev_i;
assign o = (prev_i == i);
always @(posedge clk) begin
if (clken) begin
prev_i <= i;
end
end
endmodule |
module usbf_crc16
(
input [ 15:0] crc_in_i
,input [ 7:0] din_i
,output [ 15:0] crc_out_o
);
assign crc_out_o[15] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[14] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^
crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[13] = din_i[6] ^ din_i[7] ^
crc_in_i[7] ^ crc_in_i[6];
assign crc_out_o[12] = din_i[5] ^ din_i[6] ^
crc_in_i[6] ^ crc_in_i[5];
assign crc_out_o[11] = din_i[4] ^ din_i[5] ^
crc_in_i[5] ^ crc_in_i[4];
assign crc_out_o[10] = din_i[3] ^ din_i[4] ^
crc_in_i[4] ^ crc_in_i[3];
assign crc_out_o[9] = din_i[2] ^ din_i[3] ^
crc_in_i[3] ^ crc_in_i[2];
assign crc_out_o[8] = din_i[1] ^ din_i[2] ^
crc_in_i[2] ^ crc_in_i[1];
assign crc_out_o[7] = din_i[0] ^ din_i[1] ^
crc_in_i[15] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[6] = din_i[0] ^
crc_in_i[14] ^ crc_in_i[0];
assign crc_out_o[5] = crc_in_i[13];
assign crc_out_o[4] = crc_in_i[12];
assign crc_out_o[3] = crc_in_i[11];
assign crc_out_o[2] = crc_in_i[10];
assign crc_out_o[1] = crc_in_i[9];
assign crc_out_o[0] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
crc_in_i[8] ^ crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
endmodule |
module usb_desc_rom
(
input hs_i,
input [7:0] addr_i,
output [7:0] data_o
);
reg [7:0] desc_rom_r;
always @ *
begin
case (addr_i)
8'd0: desc_rom_r = 8'h12;
8'd1: desc_rom_r = 8'h01;
8'd2: desc_rom_r = 8'h00;
8'd3: desc_rom_r = 8'h02;
8'd4: desc_rom_r = 8'h02;
8'd5: desc_rom_r = 8'h00;
8'd6: desc_rom_r = 8'h00;
8'd7: desc_rom_r = hs_i ? 8'h40 : 8'h08;
8'd8: desc_rom_r = 8'h50; 8'd9: desc_rom_r = 8'h1d; 8'd10: desc_rom_r = 8'h49; 8'd11: desc_rom_r = 8'h61; 8'd12: desc_rom_r = 8'h01;
8'd13: desc_rom_r = 8'h01;
8'd14: desc_rom_r = 8'h00;
8'd15: desc_rom_r = 8'h00;
8'd16: desc_rom_r = 8'h00;
8'd17: desc_rom_r = 8'h01;
8'd18: desc_rom_r = 8'h09;
8'd19: desc_rom_r = 8'h02;
8'd20: desc_rom_r = 8'h43;
8'd21: desc_rom_r = 8'h00;
8'd22: desc_rom_r = 8'h02;
8'd23: desc_rom_r = 8'h01;
8'd24: desc_rom_r = 8'h00;
8'd25: desc_rom_r = 8'h80;
8'd26: desc_rom_r = 8'h32;
8'd27: desc_rom_r = 8'h09;
8'd28: desc_rom_r = 8'h04;
8'd29: desc_rom_r = 8'h00;
8'd30: desc_rom_r = 8'h00;
8'd31: desc_rom_r = 8'h01;
8'd32: desc_rom_r = 8'h02;
8'd33: desc_rom_r = 8'h02;
8'd34: desc_rom_r = 8'h01;
8'd35: desc_rom_r = 8'h00;
8'd36: desc_rom_r = 8'h05;
8'd37: desc_rom_r = 8'h24;
8'd38: desc_rom_r = 8'h00;
8'd39: desc_rom_r = 8'h10;
8'd40: desc_rom_r = 8'h01;
8'd41: desc_rom_r = 8'h05;
8'd42: desc_rom_r = 8'h24;
8'd43: desc_rom_r = 8'h01;
8'd44: desc_rom_r = 8'h03;
8'd45: desc_rom_r = 8'h01;
8'd46: desc_rom_r = 8'h04;
8'd47: desc_rom_r = 8'h24;
8'd48: desc_rom_r = 8'h02;
8'd49: desc_rom_r = 8'h06;
8'd50: desc_rom_r = 8'h05;
8'd51: desc_rom_r = 8'h24;
8'd52: desc_rom_r = 8'h06;
8'd53: desc_rom_r = 8'h00;
8'd54: desc_rom_r = 8'h01;
8'd55: desc_rom_r = 8'h07;
8'd56: desc_rom_r = 8'h05;
8'd57: desc_rom_r = 8'h83;
8'd58: desc_rom_r = 8'h03;
8'd59: desc_rom_r = 8'h40;
8'd60: desc_rom_r = 8'h00;
8'd61: desc_rom_r = 8'h02;
8'd62: desc_rom_r = 8'h09;
8'd63: desc_rom_r = 8'h04;
8'd64: desc_rom_r = 8'h01;
8'd65: desc_rom_r = 8'h00;
8'd66: desc_rom_r = 8'h02;
8'd67: desc_rom_r = 8'h0a;
8'd68: desc_rom_r = 8'h00;
8'd69: desc_rom_r = 8'h00;
8'd70: desc_rom_r = 8'h00;
8'd71: desc_rom_r = 8'h07;
8'd72: desc_rom_r = 8'h05;
8'd73: desc_rom_r = 8'h01;
8'd74: desc_rom_r = 8'h02;
8'd75: desc_rom_r = hs_i ? 8'h00 : 8'h40;
8'd76: desc_rom_r = hs_i ? 8'h02 : 8'h00;
8'd77: desc_rom_r = 8'h00;
8'd78: desc_rom_r = 8'h07;
8'd79: desc_rom_r = 8'h05;
8'd80: desc_rom_r = 8'h82;
8'd81: desc_rom_r = 8'h02;
8'd82: desc_rom_r = hs_i ? 8'h00 : 8'h40;
8'd83: desc_rom_r = hs_i ? 8'h02 : 8'h00;
8'd84: desc_rom_r = 8'h00;
8'd85: desc_rom_r = 8'h04;
8'd86: desc_rom_r = 8'h03;
8'd87: desc_rom_r = 8'h09;
8'd88: desc_rom_r = 8'h04;
8'd89: desc_rom_r = 8'h1e;
8'd90: desc_rom_r = 8'h03;
8'd91: desc_rom_r = 8'h55;
8'd92: desc_rom_r = 8'h00;
8'd93: desc_rom_r = 8'h4c;
8'd94: desc_rom_r = 8'h00;
8'd95: desc_rom_r = 8'h54;
8'd96: desc_rom_r = 8'h00;
8'd97: desc_rom_r = 8'h52;
8'd98: desc_rom_r = 8'h00;
8'd99: desc_rom_r = 8'h41;
8'd100: desc_rom_r = 8'h00;
8'd101: desc_rom_r = 8'h2d;
8'd102: desc_rom_r = 8'h00;
8'd103: desc_rom_r = 8'h45;
8'd104: desc_rom_r = 8'h00;
8'd105: desc_rom_r = 8'h4d;
8'd106: desc_rom_r = 8'h00;
8'd107: desc_rom_r = 8'h42;
8'd108: desc_rom_r = 8'h00;
8'd109: desc_rom_r = 8'h45;
8'd110: desc_rom_r = 8'h00;
8'd111: desc_rom_r = 8'h44;
8'd112: desc_rom_r = 8'h00;
8'd113: desc_rom_r = 8'h44;
8'd114: desc_rom_r = 8'h00;
8'd115: desc_rom_r = 8'h45;
8'd116: desc_rom_r = 8'h00;
8'd117: desc_rom_r = 8'h44;
8'd118: desc_rom_r = 8'h00;
8'd119: desc_rom_r = 8'h1e;
8'd120: desc_rom_r = 8'h03;
8'd121: desc_rom_r = 8'h55;
8'd122: desc_rom_r = 8'h00;
8'd123: desc_rom_r = 8'h53;
8'd124: desc_rom_r = 8'h00;
8'd125: desc_rom_r = 8'h42;
8'd126: desc_rom_r = 8'h00;
8'd127: desc_rom_r = 8'h20;
8'd128: desc_rom_r = 8'h00;
8'd129: desc_rom_r = 8'h44;
8'd130: desc_rom_r = 8'h00;
8'd131: desc_rom_r = 8'h45;
8'd132: desc_rom_r = 8'h00;
8'd133: desc_rom_r = 8'h4d;
8'd134: desc_rom_r = 8'h00;
8'd135: desc_rom_r = 8'h4f;
8'd136: desc_rom_r = 8'h00;
8'd137: desc_rom_r = 8'h20;
8'd138: desc_rom_r = 8'h00;
8'd139: desc_rom_r = 8'h20;
8'd140: desc_rom_r = 8'h00;
8'd141: desc_rom_r = 8'h20;
8'd142: desc_rom_r = 8'h00;
8'd143: desc_rom_r = 8'h20;
8'd144: desc_rom_r = 8'h00;
8'd145: desc_rom_r = 8'h20;
8'd146: desc_rom_r = 8'h00;
8'd147: desc_rom_r = 8'h20;
8'd148: desc_rom_r = 8'h00;
8'd149: desc_rom_r = 8'h0e;
8'd150: desc_rom_r = 8'h03;
8'd151: desc_rom_r = 8'h30;
8'd152: desc_rom_r = 8'h00;
8'd153: desc_rom_r = 8'h30;
8'd154: desc_rom_r = 8'h00;
8'd155: desc_rom_r = 8'h30;
8'd156: desc_rom_r = 8'h00;
8'd157: desc_rom_r = 8'h30;
8'd158: desc_rom_r = 8'h00;
8'd159: desc_rom_r = 8'h30;
8'd160: desc_rom_r = 8'h00;
8'd161: desc_rom_r = 8'h30;
8'd162: desc_rom_r = 8'h00;
8'd163: desc_rom_r = 8'h00;
8'd164: desc_rom_r = 8'hc2;
8'd165: desc_rom_r = 8'h01;
8'd166: desc_rom_r = 8'h00;
8'd167: desc_rom_r = 8'h00;
8'd168: desc_rom_r = 8'h00;
8'd169: desc_rom_r = 8'h08;
default: desc_rom_r = 8'h00;
endcase
end
assign data_o = desc_rom_r;
endmodule |
module xtea(clock, reset, mode, data_in1, data_in2, key_in, data_out1, data_out2, all_done);
parameter s0 = 8'd0, s1 = 8'd1, s2 = 8'd2, s3 = 8'd3, s4 = 8'd4, s5 = 8'd5, s6 = 8'd6, s7 = 8'd7, s8 = 8'd8, s9 = 8'd9, s10 = 8'd10,
s11 = 8'd11, s12 = 8'd12, s13 = 8'd13, s14 = 8'd14, s15 = 8'd15, s16 = 8'd16, s17 = 8'd17;
input clock, reset, mode;
input[31:0] data_in1, data_in2;
input[127:0] key_in;
output[31:0] data_out1, data_out2;
output all_done;
wire clock, reset;
wire[31:0] data_in1, data_in2;
wire[127:0] key_in;
reg all_done, while_flag, modereg;
reg[1:0] selectslice;
reg[7:0] state;
reg[7:0] x;
reg[31:0] data_out1, data_out2, sum, workunit1, workunit2, delta;
always @(posedge clock or posedge reset)
begin
if (reset)
state = s0;
else begin
case (state)
s0: state = s1;
s1: state = s2;
s2: state = s3;
s3: state = while_flag ? s4 : s14;
s4: state = modereg ? s10 : s5;
s5: state = s6;
s6: state = s7;
s7: state = s8;
s8: state = s9;
s9: state = s2;
s10: state = s11;
s11: state = s12;
s12: state = s13;
s13: state = s14;
s14: state = s2;
s15: state = s16;
s16: state = s17;
s17: state = s17;
default: state = 4'bxxxx;
endcase
end
end
always @(posedge clock or posedge reset)
begin
if (reset) begin
data_out1 = 32'h00000000;
data_out2 = 32'h00000000;
x = 8'b00000000;
sum = 32'h00000000;
while_flag = 1'b0;
workunit1 = 32'h00000000;
workunit2 = 32'h00000000;
selectslice = 1'b0;
all_done = 1'b0;
delta = 32'h00000000;
modereg = 1'b0;
end
else begin
case (state)
s1: begin
workunit1 = data_in1;
workunit2 = data_in2;
delta = 32'h9e3779b9;
sum = 32'hc6ef3720;
modereg = mode;
end
s2: if (x < 8'd32) while_flag = 1'b1; else while_flag = 1'b0;
s3: begin
end
s4: begin
end
s5: selectslice = (sum >> 32'd11 & 32'd3);
s6: case (selectslice)
2'b00: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s7: sum = sum - delta;
s8: selectslice = (sum & 32'd3);
s9: begin
case (selectslice)
2'b00: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
s10: selectslice = (sum & 32'd3);
s11: case (selectslice)
2'b00: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s12: sum = sum + delta;
s13: selectslice = (sum >> 32'd11 & 32'd3);
s14: begin
case (selectslice)
2'b00: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
s15: begin
end
s16: begin
data_out1 = workunit1;
data_out2 = workunit2;
end
s17: all_done = 1'b1;
default: begin
data_out1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end
endcase
end
end
endmodule |
module y_huff(clk, rst, enable,
y11, y12, y13, y14, y15, y16, y17, y18, y21, y22, y23, y24, y25, y26, y27, y28,
y31, y32, y33, y34, y35, y36, y37, y38, y41, y42, y43, y44, y45, y46, y47, y48,
y51, y52, y53, y54, y55, y56, y57, y58, y61, y62, y63, y64, y65, y66, y67, y68,
y71, y72, y73, y74, y75, y76, y77, y78, y81, y82, y83, y84, y85, y86, y87, y88,
jpeg_bitstream, data_ready, output_reg_count, end_of_block_output,
end_of_block_empty);
input clk;
input rst;
input enable;
input [10:0] y11, y12, y13, y14, y15, y16, y17, y18, y21, y22, y23, y24;
input [10:0] y25, y26, y27, y28, y31, y32, y33, y34, y35, y36, y37, y38;
input [10:0] y41, y42, y43, y44, y45, y46, y47, y48, y51, y52, y53, y54;
input [10:0] y55, y56, y57, y58, y61, y62, y63, y64, y65, y66, y67, y68;
input [10:0] y71, y72, y73, y74, y75, y76, y77, y78, y81, y82, y83, y84;
input [10:0] y85, y86, y87, y88;
output [31:0] jpeg_bitstream;
output data_ready;
output [4:0] output_reg_count;
output end_of_block_output;
output end_of_block_empty;
reg [7:0] block_counter;
reg [11:0] y11_amp, y11_1_pos, y11_1_neg, y11_diff;
reg [11:0] y11_previous, y11_1;
reg [10:0] y12_amp, y12_pos, y12_neg;
reg [10:0] y21_pos, y21_neg, y31_pos, y31_neg, y22_pos, y22_neg;
reg [10:0] y13_pos, y13_neg, y14_pos, y14_neg, y15_pos, y15_neg;
reg [10:0] y16_pos, y16_neg, y17_pos, y17_neg, y18_pos, y18_neg;
reg [10:0] y23_pos, y23_neg, y24_pos, y24_neg, y25_pos, y25_neg;
reg [10:0] y26_pos, y26_neg, y27_pos, y27_neg, y28_pos, y28_neg;
reg [10:0] y32_pos, y32_neg;
reg [10:0] y33_pos, y33_neg, y34_pos, y34_neg, y35_pos, y35_neg;
reg [10:0] y36_pos, y36_neg, y37_pos, y37_neg, y38_pos, y38_neg;
reg [10:0] y41_pos, y41_neg, y42_pos, y42_neg;
reg [10:0] y43_pos, y43_neg, y44_pos, y44_neg, y45_pos, y45_neg;
reg [10:0] y46_pos, y46_neg, y47_pos, y47_neg, y48_pos, y48_neg;
reg [10:0] y51_pos, y51_neg, y52_pos, y52_neg;
reg [10:0] y53_pos, y53_neg, y54_pos, y54_neg, y55_pos, y55_neg;
reg [10:0] y56_pos, y56_neg, y57_pos, y57_neg, y58_pos, y58_neg;
reg [10:0] y61_pos, y61_neg, y62_pos, y62_neg;
reg [10:0] y63_pos, y63_neg, y64_pos, y64_neg, y65_pos, y65_neg;
reg [10:0] y66_pos, y66_neg, y67_pos, y67_neg, y68_pos, y68_neg;
reg [10:0] y71_pos, y71_neg, y72_pos, y72_neg;
reg [10:0] y73_pos, y73_neg, y74_pos, y74_neg, y75_pos, y75_neg;
reg [10:0] y76_pos, y76_neg, y77_pos, y77_neg, y78_pos, y78_neg;
reg [10:0] y81_pos, y81_neg, y82_pos, y82_neg;
reg [10:0] y83_pos, y83_neg, y84_pos, y84_neg, y85_pos, y85_neg;
reg [10:0] y86_pos, y86_neg, y87_pos, y87_neg, y88_pos, y88_neg;
reg [3:0] y11_bits_pos, y11_bits_neg, y11_bits, y11_bits_1;
reg [3:0] y12_bits_pos, y12_bits_neg, y12_bits, y12_bits_1;
reg [3:0] y12_bits_2, y12_bits_3;
reg y11_msb, y12_msb, y12_msb_1, data_ready;
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
reg enable_13, enable_module, enable_latch_7, enable_latch_8;
reg y12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
reg rollover_4, rollover_5, rollover_6, rollover_7;
reg y21_et_zero, y21_msb, y31_et_zero, y31_msb;
reg y22_et_zero, y22_msb, y13_et_zero, y13_msb;
reg y14_et_zero, y14_msb, y15_et_zero, y15_msb;
reg y16_et_zero, y16_msb, y17_et_zero, y17_msb;
reg y18_et_zero, y18_msb;
reg y23_et_zero, y23_msb, y24_et_zero, y24_msb;
reg y25_et_zero, y25_msb, y26_et_zero, y26_msb;
reg y27_et_zero, y27_msb, y28_et_zero, y28_msb;
reg y32_et_zero, y32_msb, y33_et_zero, y33_msb;
reg y34_et_zero, y34_msb, y35_et_zero, y35_msb;
reg y36_et_zero, y36_msb, y37_et_zero, y37_msb;
reg y38_et_zero, y38_msb;
reg y41_et_zero, y41_msb, y42_et_zero, y42_msb;
reg y43_et_zero, y43_msb, y44_et_zero, y44_msb;
reg y45_et_zero, y45_msb, y46_et_zero, y46_msb;
reg y47_et_zero, y47_msb, y48_et_zero, y48_msb;
reg y51_et_zero, y51_msb, y52_et_zero, y52_msb;
reg y53_et_zero, y53_msb, y54_et_zero, y54_msb;
reg y55_et_zero, y55_msb, y56_et_zero, y56_msb;
reg y57_et_zero, y57_msb, y58_et_zero, y58_msb;
reg y61_et_zero, y61_msb, y62_et_zero, y62_msb;
reg y63_et_zero, y63_msb, y64_et_zero, y64_msb;
reg y65_et_zero, y65_msb, y66_et_zero, y66_msb;
reg y67_et_zero, y67_msb, y68_et_zero, y68_msb;
reg y71_et_zero, y71_msb, y72_et_zero, y72_msb;
reg y73_et_zero, y73_msb, y74_et_zero, y74_msb;
reg y75_et_zero, y75_msb, y76_et_zero, y76_msb;
reg y77_et_zero, y77_msb, y78_et_zero, y78_msb;
reg y81_et_zero, y81_msb, y82_et_zero, y82_msb;
reg y83_et_zero, y83_msb, y84_et_zero, y84_msb;
reg y85_et_zero, y85_msb, y86_et_zero, y86_msb;
reg y87_et_zero, y87_msb, y88_et_zero, y88_msb;
reg y12_et_zero_1, y12_et_zero_2, y12_et_zero_3, y12_et_zero_4, y12_et_zero_5;
reg [10:0] y_dc [11:0];
reg [3:0] y_dc_code_length [11:0];
reg [15:0] y_ac [161:0];
reg [4:0] y_ac_code_length [161:0];
reg [7:0] y_ac_run_code [250:0];
reg [10:0] y11_huff, y11_huff_1, y11_huff_2;
reg [15:0] y12_huff, y12_huff_1, y12_huff_2;
reg [3:0] y11_huff_count, y11_huff_shift, y11_huff_shift_1, y11_amp_shift, y12_amp_shift;
reg [3:0] y12_huff_shift, y12_huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
reg [4:0] y12_huff_count, y12_huff_count_1;
reg [4:0] output_reg_count, y11_output_count, old_orc_1, old_orc_2;
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, y12_oc_1;
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
reg [4:0] y12_output_count;
reg [4:0] y12_edge, y12_edge_1, y12_edge_2, y12_edge_3, y12_edge_4;
reg [31:0] jpeg_bitstream, jpeg_bs, jpeg_bs_1, jpeg_bs_2, jpeg_bs_3, jpeg_bs_4, jpeg_bs_5;
reg [31:0] jpeg_y12_bs, jpeg_y12_bs_1, jpeg_y12_bs_2, jpeg_y12_bs_3, jpeg_y12_bs_4;
reg [31:0] jpeg_ro_bs, jpeg_ro_bs_1, jpeg_ro_bs_2, jpeg_ro_bs_3, jpeg_ro_bs_4;
reg [21:0] y11_jpeg_lsbs_3;
reg [10:0] y11_jpeg_lsbs, y11_jpeg_lsbs_1, y11_jpeg_lsbs_2;
reg [9:0] y12_jpeg_lsbs, y12_jpeg_lsbs_1, y12_jpeg_lsbs_2, y12_jpeg_lsbs_3;
reg [25:0] y11_jpeg_bits, y11_jpeg_bits_1, y12_jpeg_bits, y12_jpeg_lsbs_4;
reg [7:0] y12_code_entry;
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
reg end_of_block_empty;
wire [7:0] code_index = { zrl_2, y12_bits };
always @(posedge clk)
begin
if (rst) begin
third_8_all_0s <= 0; fourth_8_all_0s <= 0;
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
eighth_8_all_0s <= 0;
end
else if (enable_1) begin
third_8_all_0s <= y25_et_zero & y34_et_zero & y43_et_zero & y52_et_zero
& y61_et_zero & y71_et_zero & y62_et_zero & y53_et_zero;
fourth_8_all_0s <= y44_et_zero & y35_et_zero & y26_et_zero & y17_et_zero
& y18_et_zero & y27_et_zero & y36_et_zero & y45_et_zero;
fifth_8_all_0s <= y54_et_zero & y63_et_zero & y72_et_zero & y81_et_zero
& y82_et_zero & y73_et_zero & y64_et_zero & y55_et_zero;
sixth_8_all_0s <= y46_et_zero & y37_et_zero & y28_et_zero & y38_et_zero
& y47_et_zero & y56_et_zero & y65_et_zero & y74_et_zero;
seventh_8_all_0s <= y83_et_zero & y84_et_zero & y75_et_zero & y66_et_zero
& y57_et_zero & y48_et_zero & y58_et_zero & y67_et_zero;
eighth_8_all_0s <= y76_et_zero & y85_et_zero & y86_et_zero & y77_et_zero
& y68_et_zero & y78_et_zero & y87_et_zero & y88_et_zero;
end
end
always @(posedge clk)
begin
if (rst)
end_of_block <= 0;
else if (enable)
end_of_block <= 0;
else if (enable_module & block_counter < 32)
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter < 48)
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
& eighth_8_all_0s;
else if (enable_module & block_counter <= 64)
end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter > 64)
end_of_block <= 1;
end
always @(posedge clk)
begin
if (rst) begin
block_counter <= 0;
end
else if (enable) begin
block_counter <= 0;
end
else if (enable_module) begin
block_counter <= block_counter + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
output_reg_count <= 0;
end
else if (end_of_block_output) begin
output_reg_count <= 0;
end
else if (enable_6) begin
output_reg_count <= output_reg_count + y11_output_count;
end
else if (enable_latch_7) begin
output_reg_count <= output_reg_count + y12_oc_1;
end
end
always @(posedge clk)
begin
if (rst) begin
old_orc_1 <= 0;
end
else if (end_of_block_output) begin
old_orc_1 <= 0;
end
else if (enable_module) begin
old_orc_1 <= output_reg_count;
end
end
always @(posedge clk)
begin
if (rst) begin
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
rollover_6 <= 0; rollover_7 <= 0;
old_orc_2 <= 0;
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
end_of_block_output <= 0; end_of_block_empty <= 0;
end
else if (enable_module) begin
rollover <= (old_orc_1 > output_reg_count);
rollover_1 <= rollover;
rollover_2 <= rollover_1;
rollover_3 <= rollover_2;
rollover_4 <= rollover_3;
rollover_5 <= rollover_4;
rollover_6 <= rollover_5;
rollover_7 <= rollover_6;
old_orc_2 <= old_orc_1;
orc_3 <= old_orc_2;
orc_4 <= orc_3; orc_5 <= orc_4;
orc_6 <= orc_5; orc_7 <= orc_6;
orc_8 <= orc_7;
data_ready <= rollover_6 | block_counter == 77;
end_of_block_output <= block_counter == 77;
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs_5 <= 0;
end
else if (enable_module) begin
jpeg_bs_5[31] <= (rollover_6 & orc_7 > 0) ? jpeg_ro_bs_4[31] : jpeg_bs_4[31];
jpeg_bs_5[30] <= (rollover_6 & orc_7 > 1) ? jpeg_ro_bs_4[30] : jpeg_bs_4[30];
jpeg_bs_5[29] <= (rollover_6 & orc_7 > 2) ? jpeg_ro_bs_4[29] : jpeg_bs_4[29];
jpeg_bs_5[28] <= (rollover_6 & orc_7 > 3) ? jpeg_ro_bs_4[28] : jpeg_bs_4[28];
jpeg_bs_5[27] <= (rollover_6 & orc_7 > 4) ? jpeg_ro_bs_4[27] : jpeg_bs_4[27];
jpeg_bs_5[26] <= (rollover_6 & orc_7 > 5) ? jpeg_ro_bs_4[26] : jpeg_bs_4[26];
jpeg_bs_5[25] <= (rollover_6 & orc_7 > 6) ? jpeg_ro_bs_4[25] : jpeg_bs_4[25];
jpeg_bs_5[24] <= (rollover_6 & orc_7 > 7) ? jpeg_ro_bs_4[24] : jpeg_bs_4[24];
jpeg_bs_5[23] <= (rollover_6 & orc_7 > 8) ? jpeg_ro_bs_4[23] : jpeg_bs_4[23];
jpeg_bs_5[22] <= (rollover_6 & orc_7 > 9) ? jpeg_ro_bs_4[22] : jpeg_bs_4[22];
jpeg_bs_5[21] <= (rollover_6 & orc_7 > 10) ? jpeg_ro_bs_4[21] : jpeg_bs_4[21];
jpeg_bs_5[20] <= (rollover_6 & orc_7 > 11) ? jpeg_ro_bs_4[20] : jpeg_bs_4[20];
jpeg_bs_5[19] <= (rollover_6 & orc_7 > 12) ? jpeg_ro_bs_4[19] : jpeg_bs_4[19];
jpeg_bs_5[18] <= (rollover_6 & orc_7 > 13) ? jpeg_ro_bs_4[18] : jpeg_bs_4[18];
jpeg_bs_5[17] <= (rollover_6 & orc_7 > 14) ? jpeg_ro_bs_4[17] : jpeg_bs_4[17];
jpeg_bs_5[16] <= (rollover_6 & orc_7 > 15) ? jpeg_ro_bs_4[16] : jpeg_bs_4[16];
jpeg_bs_5[15] <= (rollover_6 & orc_7 > 16) ? jpeg_ro_bs_4[15] : jpeg_bs_4[15];
jpeg_bs_5[14] <= (rollover_6 & orc_7 > 17) ? jpeg_ro_bs_4[14] : jpeg_bs_4[14];
jpeg_bs_5[13] <= (rollover_6 & orc_7 > 18) ? jpeg_ro_bs_4[13] : jpeg_bs_4[13];
jpeg_bs_5[12] <= (rollover_6 & orc_7 > 19) ? jpeg_ro_bs_4[12] : jpeg_bs_4[12];
jpeg_bs_5[11] <= (rollover_6 & orc_7 > 20) ? jpeg_ro_bs_4[11] : jpeg_bs_4[11];
jpeg_bs_5[10] <= (rollover_6 & orc_7 > 21) ? jpeg_ro_bs_4[10] : jpeg_bs_4[10];
jpeg_bs_5[9] <= (rollover_6 & orc_7 > 22) ? jpeg_ro_bs_4[9] : jpeg_bs_4[9];
jpeg_bs_5[8] <= (rollover_6 & orc_7 > 23) ? jpeg_ro_bs_4[8] : jpeg_bs_4[8];
jpeg_bs_5[7] <= (rollover_6 & orc_7 > 24) ? jpeg_ro_bs_4[7] : jpeg_bs_4[7];
jpeg_bs_5[6] <= (rollover_6 & orc_7 > 25) ? jpeg_ro_bs_4[6] : jpeg_bs_4[6];
jpeg_bs_5[5] <= (rollover_6 & orc_7 > 26) ? jpeg_ro_bs_4[5] : jpeg_bs_4[5];
jpeg_bs_5[4] <= (rollover_6 & orc_7 > 27) ? jpeg_ro_bs_4[4] : jpeg_bs_4[4];
jpeg_bs_5[3] <= (rollover_6 & orc_7 > 28) ? jpeg_ro_bs_4[3] : jpeg_bs_4[3];
jpeg_bs_5[2] <= (rollover_6 & orc_7 > 29) ? jpeg_ro_bs_4[2] : jpeg_bs_4[2];
jpeg_bs_5[1] <= (rollover_6 & orc_7 > 30) ? jpeg_ro_bs_4[1] : jpeg_bs_4[1];
jpeg_bs_5[0] <= jpeg_bs_4[0];
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs_4 <= 0; jpeg_ro_bs_4 <= 0;
end
else if (enable_module) begin
jpeg_bs_4 <= (old_orc_6 == 1) ? jpeg_bs_3 >> 1 : jpeg_bs_3;
jpeg_ro_bs_4 <= (y12_edge_4 <= 1) ? jpeg_ro_bs_3 << 1 : jpeg_ro_bs_3;
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs_3 <= 0; old_orc_6 <= 0; jpeg_ro_bs_3 <= 0;
y12_edge_4 <= 0;
end
else if (enable_module) begin
jpeg_bs_3 <= (old_orc_5 >= 2) ? jpeg_bs_2 >> 2 : jpeg_bs_2;
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
jpeg_ro_bs_3 <= (y12_edge_3 <= 2) ? jpeg_ro_bs_2 << 2 : jpeg_ro_bs_2;
y12_edge_4 <= (y12_edge_3 <= 2) ? y12_edge_3 : y12_edge_3 - 2;
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs_2 <= 0; old_orc_5 <= 0; jpeg_ro_bs_2 <= 0;
y12_edge_3 <= 0;
end
else if (enable_module) begin
jpeg_bs_2 <= (old_orc_4 >= 4) ? jpeg_bs_1 >> 4 : jpeg_bs_1;
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
jpeg_ro_bs_2 <= (y12_edge_2 <= 4) ? jpeg_ro_bs_1 << 4 : jpeg_ro_bs_1;
y12_edge_3 <= (y12_edge_2 <= 4) ? y12_edge_2 : y12_edge_2 - 4;
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs_1 <= 0; old_orc_4 <= 0; jpeg_ro_bs_1 <= 0;
y12_edge_2 <= 0;
end
else if (enable_module) begin
jpeg_bs_1 <= (old_orc_3 >= 8) ? jpeg_bs >> 8 : jpeg_bs;
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
jpeg_ro_bs_1 <= (y12_edge_1 <= 8) ? jpeg_ro_bs << 8 : jpeg_ro_bs;
y12_edge_2 <= (y12_edge_1 <= 8) ? y12_edge_1 : y12_edge_1 - 8;
end
end
always @(posedge clk)
begin
if (rst) begin
jpeg_bs <= 0; old_orc_3 <= 0; jpeg_ro_bs <= 0;
y12_edge_1 <= 0; y11_jpeg_bits_1 <= 0;
end
else if (enable_module) begin
jpeg_bs <= (old_orc_2 >= 16) ? y11_jpeg_bits >> 10 : y11_jpeg_bits << 6;
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
jpeg_ro_bs <= (y12_edge <= 16) ? y11_jpeg_bits_1 << 16 : y11_jpeg_bits_1;
y12_edge_1 <= (y12_edge <= 16) ? y12_edge : y12_edge - 16;
y11_jpeg_bits_1 <= y11_jpeg_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_jpeg_bits <= 0; y12_edge <= 0;
end
else if (enable_module) begin
y12_jpeg_bits[25] <= (y12_huff_shift_1 >= 16) ? y12_jpeg_lsbs_4[25] : y12_huff_2[15];
y12_jpeg_bits[24] <= (y12_huff_shift_1 >= 15) ? y12_jpeg_lsbs_4[24] : y12_huff_2[14];
y12_jpeg_bits[23] <= (y12_huff_shift_1 >= 14) ? y12_jpeg_lsbs_4[23] : y12_huff_2[13];
y12_jpeg_bits[22] <= (y12_huff_shift_1 >= 13) ? y12_jpeg_lsbs_4[22] : y12_huff_2[12];
y12_jpeg_bits[21] <= (y12_huff_shift_1 >= 12) ? y12_jpeg_lsbs_4[21] : y12_huff_2[11];
y12_jpeg_bits[20] <= (y12_huff_shift_1 >= 11) ? y12_jpeg_lsbs_4[20] : y12_huff_2[10];
y12_jpeg_bits[19] <= (y12_huff_shift_1 >= 10) ? y12_jpeg_lsbs_4[19] : y12_huff_2[9];
y12_jpeg_bits[18] <= (y12_huff_shift_1 >= 9) ? y12_jpeg_lsbs_4[18] : y12_huff_2[8];
y12_jpeg_bits[17] <= (y12_huff_shift_1 >= 8) ? y12_jpeg_lsbs_4[17] : y12_huff_2[7];
y12_jpeg_bits[16] <= (y12_huff_shift_1 >= 7) ? y12_jpeg_lsbs_4[16] : y12_huff_2[6];
y12_jpeg_bits[15] <= (y12_huff_shift_1 >= 6) ? y12_jpeg_lsbs_4[15] : y12_huff_2[5];
y12_jpeg_bits[14] <= (y12_huff_shift_1 >= 5) ? y12_jpeg_lsbs_4[14] : y12_huff_2[4];
y12_jpeg_bits[13] <= (y12_huff_shift_1 >= 4) ? y12_jpeg_lsbs_4[13] : y12_huff_2[3];
y12_jpeg_bits[12] <= (y12_huff_shift_1 >= 3) ? y12_jpeg_lsbs_4[12] : y12_huff_2[2];
y12_jpeg_bits[11] <= (y12_huff_shift_1 >= 2) ? y12_jpeg_lsbs_4[11] : y12_huff_2[1];
y12_jpeg_bits[10] <= (y12_huff_shift_1 >= 1) ? y12_jpeg_lsbs_4[10] : y12_huff_2[0];
y12_jpeg_bits[9:0] <= y12_jpeg_lsbs_4[9:0];
y12_edge <= old_orc_2 + 26; end
end
always @(posedge clk)
begin
if (rst) begin
y11_jpeg_bits <= 0;
end
else if (enable_7) begin
y11_jpeg_bits[25] <= (y11_huff_shift_1 >= 11) ? y11_jpeg_lsbs_3[21] : y11_huff_2[10];
y11_jpeg_bits[24] <= (y11_huff_shift_1 >= 10) ? y11_jpeg_lsbs_3[20] : y11_huff_2[9];
y11_jpeg_bits[23] <= (y11_huff_shift_1 >= 9) ? y11_jpeg_lsbs_3[19] : y11_huff_2[8];
y11_jpeg_bits[22] <= (y11_huff_shift_1 >= 8) ? y11_jpeg_lsbs_3[18] : y11_huff_2[7];
y11_jpeg_bits[21] <= (y11_huff_shift_1 >= 7) ? y11_jpeg_lsbs_3[17] : y11_huff_2[6];
y11_jpeg_bits[20] <= (y11_huff_shift_1 >= 6) ? y11_jpeg_lsbs_3[16] : y11_huff_2[5];
y11_jpeg_bits[19] <= (y11_huff_shift_1 >= 5) ? y11_jpeg_lsbs_3[15] : y11_huff_2[4];
y11_jpeg_bits[18] <= (y11_huff_shift_1 >= 4) ? y11_jpeg_lsbs_3[14] : y11_huff_2[3];
y11_jpeg_bits[17] <= (y11_huff_shift_1 >= 3) ? y11_jpeg_lsbs_3[13] : y11_huff_2[2];
y11_jpeg_bits[16] <= (y11_huff_shift_1 >= 2) ? y11_jpeg_lsbs_3[12] : y11_huff_2[1];
y11_jpeg_bits[15] <= (y11_huff_shift_1 >= 1) ? y11_jpeg_lsbs_3[11] : y11_huff_2[0];
y11_jpeg_bits[14:4] <= y11_jpeg_lsbs_3[10:0];
end
else if (enable_latch_8) begin
y11_jpeg_bits <= y12_jpeg_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_oc_1 <= 0; y12_jpeg_lsbs_4 <= 0;
y12_huff_2 <= 0; y12_huff_shift_1 <= 0;
end
else if (enable_module) begin
y12_oc_1 <= (y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
y12_bits_3 + y12_huff_count_1;
y12_jpeg_lsbs_4 <= y12_jpeg_lsbs_3 << y12_huff_shift;
y12_huff_2 <= y12_huff_1;
y12_huff_shift_1 <= y12_huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_jpeg_lsbs_3 <= 0; y11_huff_2 <= 0;
y11_huff_shift_1 <= 0;
end
else if (enable_6) begin
y11_jpeg_lsbs_3 <= y11_jpeg_lsbs_2 << y11_huff_shift;
y11_huff_2 <= y11_huff_1;
y11_huff_shift_1 <= y11_huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_huff_shift <= 0;
y12_huff_1 <= 0; y12_jpeg_lsbs_3 <= 0; y12_bits_3 <= 0;
y12_huff_count_1 <= 0; y12_et_zero_5 <= 0; code_15_0 <= 0;
end
else if (enable_module) begin
y12_huff_shift <= 16 - y12_huff_count;
y12_huff_1 <= y12_huff;
y12_jpeg_lsbs_3 <= y12_jpeg_lsbs_2;
y12_bits_3 <= y12_bits_2;
y12_huff_count_1 <= y12_huff_count;
y12_et_zero_5 <= y12_et_zero_4;
code_15_0 <= zrl_et_15 & !end_of_block;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_output_count <= 0; y11_jpeg_lsbs_2 <= 0; y11_huff_shift <= 0;
y11_huff_1 <= 0;
end
else if (enable_5) begin
y11_output_count <= y11_bits_1 + y11_huff_count;
y11_jpeg_lsbs_2 <= y11_jpeg_lsbs_1 << y11_amp_shift;
y11_huff_shift <= 11 - y11_huff_count;
y11_huff_1 <= y11_huff;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_jpeg_lsbs_2 <= 0;
y12_huff <= 0; y12_huff_count <= 0; y12_bits_2 <= 0;
y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
end
else if (enable_module) begin
y12_jpeg_lsbs_2 <= y12_jpeg_lsbs_1 << y12_amp_shift;
y12_huff <= y_ac[y12_code_entry];
y12_huff_count <= y_ac_code_length[y12_code_entry];
y12_bits_2 <= y12_bits_1;
y12_et_zero_4 <= y12_et_zero_3;
zrl_et_15 <= zrl_3 == 15;
zrl_3 <= zrl_2;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_huff <= 0; y11_huff_count <= 0; y11_amp_shift <= 0;
y11_jpeg_lsbs_1 <= 0; y11_bits_1 <= 0;
end
else if (enable_4) begin
y11_huff[10:0] <= y_dc[y11_bits];
y11_huff_count <= y_dc_code_length[y11_bits];
y11_amp_shift <= 11 - y11_bits;
y11_jpeg_lsbs_1 <= y11_jpeg_lsbs;
y11_bits_1 <= y11_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_code_entry <= 0; y12_jpeg_lsbs_1 <= 0; y12_amp_shift <= 0;
y12_bits_1 <= 0; y12_et_zero_3 <= 0; zrl_2 <= 0;
end
else if (enable_module) begin
y12_code_entry <= y_ac_run_code[code_index];
y12_jpeg_lsbs_1 <= y12_jpeg_lsbs;
y12_amp_shift <= 10 - y12_bits;
y12_bits_1 <= y12_bits;
y12_et_zero_3 <= y12_et_zero_2;
zrl_2 <= zrl_1;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_bits <= 0; y11_jpeg_lsbs <= 0;
end
else if (enable_3) begin
y11_bits <= y11_msb ? y11_bits_neg : y11_bits_pos;
y11_jpeg_lsbs <= y11_amp[10:0]; end
end
always @(posedge clk)
begin
if (rst) begin
y12_bits <= 0; y12_jpeg_lsbs <= 0; zrl_1 <= 0;
y12_et_zero_2 <= 0;
end
else if (enable_module) begin
y12_bits <= y12_msb_1 ? y12_bits_neg : y12_bits_pos;
y12_jpeg_lsbs <= y12_amp[9:0]; zrl_1 <= block_counter == 62 & y12_et_zero ? 0 : zero_run_length;
y12_et_zero_2 <= y12_et_zero_1;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_amp <= 0;
end
else if (enable_2) begin
y11_amp <= y11_msb ? y11_1_neg : y11_1_pos;
end
end
always @(posedge clk)
begin
if (rst)
zero_run_length <= 0;
else if (enable)
zero_run_length <= 0;
else if (enable_module)
zero_run_length <= y12_et_zero ? zero_run_length + 1: 0;
end
always @(posedge clk)
begin
if (rst) begin
y12_amp <= 0;
y12_et_zero_1 <= 0; y12_msb_1 <= 0;
end
else if (enable_module) begin
y12_amp <= y12_msb ? y12_neg : y12_pos;
y12_et_zero_1 <= y12_et_zero;
y12_msb_1 <= y12_msb;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_1_pos <= 0; y11_1_neg <= 0; y11_msb <= 0;
y11_previous <= 0;
end
else if (enable_1) begin
y11_1_pos <= y11_diff;
y11_1_neg <= y11_diff - 1;
y11_msb <= y11_diff[11];
y11_previous <= y11_1;
end
end
always @(posedge clk)
begin
if (rst) begin
y12_pos <= 0; y12_neg <= 0; y12_msb <= 0; y12_et_zero <= 0;
y13_pos <= 0; y13_neg <= 0; y13_msb <= 0; y13_et_zero <= 0;
y14_pos <= 0; y14_neg <= 0; y14_msb <= 0; y14_et_zero <= 0;
y15_pos <= 0; y15_neg <= 0; y15_msb <= 0; y15_et_zero <= 0;
y16_pos <= 0; y16_neg <= 0; y16_msb <= 0; y16_et_zero <= 0;
y17_pos <= 0; y17_neg <= 0; y17_msb <= 0; y17_et_zero <= 0;
y18_pos <= 0; y18_neg <= 0; y18_msb <= 0; y18_et_zero <= 0;
y21_pos <= 0; y21_neg <= 0; y21_msb <= 0; y21_et_zero <= 0;
y22_pos <= 0; y22_neg <= 0; y22_msb <= 0; y22_et_zero <= 0;
y23_pos <= 0; y23_neg <= 0; y23_msb <= 0; y23_et_zero <= 0;
y24_pos <= 0; y24_neg <= 0; y24_msb <= 0; y24_et_zero <= 0;
y25_pos <= 0; y25_neg <= 0; y25_msb <= 0; y25_et_zero <= 0;
y26_pos <= 0; y26_neg <= 0; y26_msb <= 0; y26_et_zero <= 0;
y27_pos <= 0; y27_neg <= 0; y27_msb <= 0; y27_et_zero <= 0;
y28_pos <= 0; y28_neg <= 0; y28_msb <= 0; y28_et_zero <= 0;
y31_pos <= 0; y31_neg <= 0; y31_msb <= 0; y31_et_zero <= 0;
y32_pos <= 0; y32_neg <= 0; y32_msb <= 0; y32_et_zero <= 0;
y33_pos <= 0; y33_neg <= 0; y33_msb <= 0; y33_et_zero <= 0;
y34_pos <= 0; y34_neg <= 0; y34_msb <= 0; y34_et_zero <= 0;
y35_pos <= 0; y35_neg <= 0; y35_msb <= 0; y35_et_zero <= 0;
y36_pos <= 0; y36_neg <= 0; y36_msb <= 0; y36_et_zero <= 0;
y37_pos <= 0; y37_neg <= 0; y37_msb <= 0; y37_et_zero <= 0;
y38_pos <= 0; y38_neg <= 0; y38_msb <= 0; y38_et_zero <= 0;
y41_pos <= 0; y41_neg <= 0; y41_msb <= 0; y41_et_zero <= 0;
y42_pos <= 0; y42_neg <= 0; y42_msb <= 0; y42_et_zero <= 0;
y43_pos <= 0; y43_neg <= 0; y43_msb <= 0; y43_et_zero <= 0;
y44_pos <= 0; y44_neg <= 0; y44_msb <= 0; y44_et_zero <= 0;
y45_pos <= 0; y45_neg <= 0; y45_msb <= 0; y45_et_zero <= 0;
y46_pos <= 0; y46_neg <= 0; y46_msb <= 0; y46_et_zero <= 0;
y47_pos <= 0; y47_neg <= 0; y47_msb <= 0; y47_et_zero <= 0;
y48_pos <= 0; y48_neg <= 0; y48_msb <= 0; y48_et_zero <= 0;
y51_pos <= 0; y51_neg <= 0; y51_msb <= 0; y51_et_zero <= 0;
y52_pos <= 0; y52_neg <= 0; y52_msb <= 0; y52_et_zero <= 0;
y53_pos <= 0; y53_neg <= 0; y53_msb <= 0; y53_et_zero <= 0;
y54_pos <= 0; y54_neg <= 0; y54_msb <= 0; y54_et_zero <= 0;
y55_pos <= 0; y55_neg <= 0; y55_msb <= 0; y55_et_zero <= 0;
y56_pos <= 0; y56_neg <= 0; y56_msb <= 0; y56_et_zero <= 0;
y57_pos <= 0; y57_neg <= 0; y57_msb <= 0; y57_et_zero <= 0;
y58_pos <= 0; y58_neg <= 0; y58_msb <= 0; y58_et_zero <= 0;
y61_pos <= 0; y61_neg <= 0; y61_msb <= 0; y61_et_zero <= 0;
y62_pos <= 0; y62_neg <= 0; y62_msb <= 0; y62_et_zero <= 0;
y63_pos <= 0; y63_neg <= 0; y63_msb <= 0; y63_et_zero <= 0;
y64_pos <= 0; y64_neg <= 0; y64_msb <= 0; y64_et_zero <= 0;
y65_pos <= 0; y65_neg <= 0; y65_msb <= 0; y65_et_zero <= 0;
y66_pos <= 0; y66_neg <= 0; y66_msb <= 0; y66_et_zero <= 0;
y67_pos <= 0; y67_neg <= 0; y67_msb <= 0; y67_et_zero <= 0;
y68_pos <= 0; y68_neg <= 0; y68_msb <= 0; y68_et_zero <= 0;
y71_pos <= 0; y71_neg <= 0; y71_msb <= 0; y71_et_zero <= 0;
y72_pos <= 0; y72_neg <= 0; y72_msb <= 0; y72_et_zero <= 0;
y73_pos <= 0; y73_neg <= 0; y73_msb <= 0; y73_et_zero <= 0;
y74_pos <= 0; y74_neg <= 0; y74_msb <= 0; y74_et_zero <= 0;
y75_pos <= 0; y75_neg <= 0; y75_msb <= 0; y75_et_zero <= 0;
y76_pos <= 0; y76_neg <= 0; y76_msb <= 0; y76_et_zero <= 0;
y77_pos <= 0; y77_neg <= 0; y77_msb <= 0; y77_et_zero <= 0;
y78_pos <= 0; y78_neg <= 0; y78_msb <= 0; y78_et_zero <= 0;
y81_pos <= 0; y81_neg <= 0; y81_msb <= 0; y81_et_zero <= 0;
y82_pos <= 0; y82_neg <= 0; y82_msb <= 0; y82_et_zero <= 0;
y83_pos <= 0; y83_neg <= 0; y83_msb <= 0; y83_et_zero <= 0;
y84_pos <= 0; y84_neg <= 0; y84_msb <= 0; y84_et_zero <= 0;
y85_pos <= 0; y85_neg <= 0; y85_msb <= 0; y85_et_zero <= 0;
y86_pos <= 0; y86_neg <= 0; y86_msb <= 0; y86_et_zero <= 0;
y87_pos <= 0; y87_neg <= 0; y87_msb <= 0; y87_et_zero <= 0;
y88_pos <= 0; y88_neg <= 0; y88_msb <= 0; y88_et_zero <= 0;
end
else if (enable) begin
y12_pos <= y12;
y12_neg <= y12 - 1;
y12_msb <= y12[10];
y12_et_zero <= !(|y12);
y13_pos <= y13;
y13_neg <= y13 - 1;
y13_msb <= y13[10];
y13_et_zero <= !(|y13);
y14_pos <= y14;
y14_neg <= y14 - 1;
y14_msb <= y14[10];
y14_et_zero <= !(|y14);
y15_pos <= y15;
y15_neg <= y15 - 1;
y15_msb <= y15[10];
y15_et_zero <= !(|y15);
y16_pos <= y16;
y16_neg <= y16 - 1;
y16_msb <= y16[10];
y16_et_zero <= !(|y16);
y17_pos <= y17;
y17_neg <= y17 - 1;
y17_msb <= y17[10];
y17_et_zero <= !(|y17);
y18_pos <= y18;
y18_neg <= y18 - 1;
y18_msb <= y18[10];
y18_et_zero <= !(|y18);
y21_pos <= y21;
y21_neg <= y21 - 1;
y21_msb <= y21[10];
y21_et_zero <= !(|y21);
y22_pos <= y22;
y22_neg <= y22 - 1;
y22_msb <= y22[10];
y22_et_zero <= !(|y22);
y23_pos <= y23;
y23_neg <= y23 - 1;
y23_msb <= y23[10];
y23_et_zero <= !(|y23);
y24_pos <= y24;
y24_neg <= y24 - 1;
y24_msb <= y24[10];
y24_et_zero <= !(|y24);
y25_pos <= y25;
y25_neg <= y25 - 1;
y25_msb <= y25[10];
y25_et_zero <= !(|y25);
y26_pos <= y26;
y26_neg <= y26 - 1;
y26_msb <= y26[10];
y26_et_zero <= !(|y26);
y27_pos <= y27;
y27_neg <= y27 - 1;
y27_msb <= y27[10];
y27_et_zero <= !(|y27);
y28_pos <= y28;
y28_neg <= y28 - 1;
y28_msb <= y28[10];
y28_et_zero <= !(|y28);
y31_pos <= y31;
y31_neg <= y31 - 1;
y31_msb <= y31[10];
y31_et_zero <= !(|y31);
y32_pos <= y32;
y32_neg <= y32 - 1;
y32_msb <= y32[10];
y32_et_zero <= !(|y32);
y33_pos <= y33;
y33_neg <= y33 - 1;
y33_msb <= y33[10];
y33_et_zero <= !(|y33);
y34_pos <= y34;
y34_neg <= y34 - 1;
y34_msb <= y34[10];
y34_et_zero <= !(|y34);
y35_pos <= y35;
y35_neg <= y35 - 1;
y35_msb <= y35[10];
y35_et_zero <= !(|y35);
y36_pos <= y36;
y36_neg <= y36 - 1;
y36_msb <= y36[10];
y36_et_zero <= !(|y36);
y37_pos <= y37;
y37_neg <= y37 - 1;
y37_msb <= y37[10];
y37_et_zero <= !(|y37);
y38_pos <= y38;
y38_neg <= y38 - 1;
y38_msb <= y38[10];
y38_et_zero <= !(|y38);
y41_pos <= y41;
y41_neg <= y41 - 1;
y41_msb <= y41[10];
y41_et_zero <= !(|y41);
y42_pos <= y42;
y42_neg <= y42 - 1;
y42_msb <= y42[10];
y42_et_zero <= !(|y42);
y43_pos <= y43;
y43_neg <= y43 - 1;
y43_msb <= y43[10];
y43_et_zero <= !(|y43);
y44_pos <= y44;
y44_neg <= y44 - 1;
y44_msb <= y44[10];
y44_et_zero <= !(|y44);
y45_pos <= y45;
y45_neg <= y45 - 1;
y45_msb <= y45[10];
y45_et_zero <= !(|y45);
y46_pos <= y46;
y46_neg <= y46 - 1;
y46_msb <= y46[10];
y46_et_zero <= !(|y46);
y47_pos <= y47;
y47_neg <= y47 - 1;
y47_msb <= y47[10];
y47_et_zero <= !(|y47);
y48_pos <= y48;
y48_neg <= y48 - 1;
y48_msb <= y48[10];
y48_et_zero <= !(|y48);
y51_pos <= y51;
y51_neg <= y51 - 1;
y51_msb <= y51[10];
y51_et_zero <= !(|y51);
y52_pos <= y52;
y52_neg <= y52 - 1;
y52_msb <= y52[10];
y52_et_zero <= !(|y52);
y53_pos <= y53;
y53_neg <= y53 - 1;
y53_msb <= y53[10];
y53_et_zero <= !(|y53);
y54_pos <= y54;
y54_neg <= y54 - 1;
y54_msb <= y54[10];
y54_et_zero <= !(|y54);
y55_pos <= y55;
y55_neg <= y55 - 1;
y55_msb <= y55[10];
y55_et_zero <= !(|y55);
y56_pos <= y56;
y56_neg <= y56 - 1;
y56_msb <= y56[10];
y56_et_zero <= !(|y56);
y57_pos <= y57;
y57_neg <= y57 - 1;
y57_msb <= y57[10];
y57_et_zero <= !(|y57);
y58_pos <= y58;
y58_neg <= y58 - 1;
y58_msb <= y58[10];
y58_et_zero <= !(|y58);
y61_pos <= y61;
y61_neg <= y61 - 1;
y61_msb <= y61[10];
y61_et_zero <= !(|y61);
y62_pos <= y62;
y62_neg <= y62 - 1;
y62_msb <= y62[10];
y62_et_zero <= !(|y62);
y63_pos <= y63;
y63_neg <= y63 - 1;
y63_msb <= y63[10];
y63_et_zero <= !(|y63);
y64_pos <= y64;
y64_neg <= y64 - 1;
y64_msb <= y64[10];
y64_et_zero <= !(|y64);
y65_pos <= y65;
y65_neg <= y65 - 1;
y65_msb <= y65[10];
y65_et_zero <= !(|y65);
y66_pos <= y66;
y66_neg <= y66 - 1;
y66_msb <= y66[10];
y66_et_zero <= !(|y66);
y67_pos <= y67;
y67_neg <= y67 - 1;
y67_msb <= y67[10];
y67_et_zero <= !(|y67);
y68_pos <= y68;
y68_neg <= y68 - 1;
y68_msb <= y68[10];
y68_et_zero <= !(|y68);
y71_pos <= y71;
y71_neg <= y71 - 1;
y71_msb <= y71[10];
y71_et_zero <= !(|y71);
y72_pos <= y72;
y72_neg <= y72 - 1;
y72_msb <= y72[10];
y72_et_zero <= !(|y72);
y73_pos <= y73;
y73_neg <= y73 - 1;
y73_msb <= y73[10];
y73_et_zero <= !(|y73);
y74_pos <= y74;
y74_neg <= y74 - 1;
y74_msb <= y74[10];
y74_et_zero <= !(|y74);
y75_pos <= y75;
y75_neg <= y75 - 1;
y75_msb <= y75[10];
y75_et_zero <= !(|y75);
y76_pos <= y76;
y76_neg <= y76 - 1;
y76_msb <= y76[10];
y76_et_zero <= !(|y76);
y77_pos <= y77;
y77_neg <= y77 - 1;
y77_msb <= y77[10];
y77_et_zero <= !(|y77);
y78_pos <= y78;
y78_neg <= y78 - 1;
y78_msb <= y78[10];
y78_et_zero <= !(|y78);
y81_pos <= y81;
y81_neg <= y81 - 1;
y81_msb <= y81[10];
y81_et_zero <= !(|y81);
y82_pos <= y82;
y82_neg <= y82 - 1;
y82_msb <= y82[10];
y82_et_zero <= !(|y82);
y83_pos <= y83;
y83_neg <= y83 - 1;
y83_msb <= y83[10];
y83_et_zero <= !(|y83);
y84_pos <= y84;
y84_neg <= y84 - 1;
y84_msb <= y84[10];
y84_et_zero <= !(|y84);
y85_pos <= y85;
y85_neg <= y85 - 1;
y85_msb <= y85[10];
y85_et_zero <= !(|y85);
y86_pos <= y86;
y86_neg <= y86 - 1;
y86_msb <= y86[10];
y86_et_zero <= !(|y86);
y87_pos <= y87;
y87_neg <= y87 - 1;
y87_msb <= y87[10];
y87_et_zero <= !(|y87);
y88_pos <= y88;
y88_neg <= y88 - 1;
y88_msb <= y88[10];
y88_et_zero <= !(|y88);
end
else if (enable_module) begin
y12_pos <= y21_pos;
y12_neg <= y21_neg;
y12_msb <= y21_msb;
y12_et_zero <= y21_et_zero;
y21_pos <= y31_pos;
y21_neg <= y31_neg;
y21_msb <= y31_msb;
y21_et_zero <= y31_et_zero;
y31_pos <= y22_pos;
y31_neg <= y22_neg;
y31_msb <= y22_msb;
y31_et_zero <= y22_et_zero;
y22_pos <= y13_pos;
y22_neg <= y13_neg;
y22_msb <= y13_msb;
y22_et_zero <= y13_et_zero;
y13_pos <= y14_pos;
y13_neg <= y14_neg;
y13_msb <= y14_msb;
y13_et_zero <= y14_et_zero;
y14_pos <= y23_pos;
y14_neg <= y23_neg;
y14_msb <= y23_msb;
y14_et_zero <= y23_et_zero;
y23_pos <= y32_pos;
y23_neg <= y32_neg;
y23_msb <= y32_msb;
y23_et_zero <= y32_et_zero;
y32_pos <= y41_pos;
y32_neg <= y41_neg;
y32_msb <= y41_msb;
y32_et_zero <= y41_et_zero;
y41_pos <= y51_pos;
y41_neg <= y51_neg;
y41_msb <= y51_msb;
y41_et_zero <= y51_et_zero;
y51_pos <= y42_pos;
y51_neg <= y42_neg;
y51_msb <= y42_msb;
y51_et_zero <= y42_et_zero;
y42_pos <= y33_pos;
y42_neg <= y33_neg;
y42_msb <= y33_msb;
y42_et_zero <= y33_et_zero;
y33_pos <= y24_pos;
y33_neg <= y24_neg;
y33_msb <= y24_msb;
y33_et_zero <= y24_et_zero;
y24_pos <= y15_pos;
y24_neg <= y15_neg;
y24_msb <= y15_msb;
y24_et_zero <= y15_et_zero;
y15_pos <= y16_pos;
y15_neg <= y16_neg;
y15_msb <= y16_msb;
y15_et_zero <= y16_et_zero;
y16_pos <= y25_pos;
y16_neg <= y25_neg;
y16_msb <= y25_msb;
y16_et_zero <= y25_et_zero;
y25_pos <= y34_pos;
y25_neg <= y34_neg;
y25_msb <= y34_msb;
y25_et_zero <= y34_et_zero;
y34_pos <= y43_pos;
y34_neg <= y43_neg;
y34_msb <= y43_msb;
y34_et_zero <= y43_et_zero;
y43_pos <= y52_pos;
y43_neg <= y52_neg;
y43_msb <= y52_msb;
y43_et_zero <= y52_et_zero;
y52_pos <= y61_pos;
y52_neg <= y61_neg;
y52_msb <= y61_msb;
y52_et_zero <= y61_et_zero;
y61_pos <= y71_pos;
y61_neg <= y71_neg;
y61_msb <= y71_msb;
y61_et_zero <= y71_et_zero;
y71_pos <= y62_pos;
y71_neg <= y62_neg;
y71_msb <= y62_msb;
y71_et_zero <= y62_et_zero;
y62_pos <= y53_pos;
y62_neg <= y53_neg;
y62_msb <= y53_msb;
y62_et_zero <= y53_et_zero;
y53_pos <= y44_pos;
y53_neg <= y44_neg;
y53_msb <= y44_msb;
y53_et_zero <= y44_et_zero;
y44_pos <= y35_pos;
y44_neg <= y35_neg;
y44_msb <= y35_msb;
y44_et_zero <= y35_et_zero;
y35_pos <= y26_pos;
y35_neg <= y26_neg;
y35_msb <= y26_msb;
y35_et_zero <= y26_et_zero;
y26_pos <= y17_pos;
y26_neg <= y17_neg;
y26_msb <= y17_msb;
y26_et_zero <= y17_et_zero;
y17_pos <= y18_pos;
y17_neg <= y18_neg;
y17_msb <= y18_msb;
y17_et_zero <= y18_et_zero;
y18_pos <= y27_pos;
y18_neg <= y27_neg;
y18_msb <= y27_msb;
y18_et_zero <= y27_et_zero;
y27_pos <= y36_pos;
y27_neg <= y36_neg;
y27_msb <= y36_msb;
y27_et_zero <= y36_et_zero;
y36_pos <= y45_pos;
y36_neg <= y45_neg;
y36_msb <= y45_msb;
y36_et_zero <= y45_et_zero;
y45_pos <= y54_pos;
y45_neg <= y54_neg;
y45_msb <= y54_msb;
y45_et_zero <= y54_et_zero;
y54_pos <= y63_pos;
y54_neg <= y63_neg;
y54_msb <= y63_msb;
y54_et_zero <= y63_et_zero;
y63_pos <= y72_pos;
y63_neg <= y72_neg;
y63_msb <= y72_msb;
y63_et_zero <= y72_et_zero;
y72_pos <= y81_pos;
y72_neg <= y81_neg;
y72_msb <= y81_msb;
y72_et_zero <= y81_et_zero;
y81_pos <= y82_pos;
y81_neg <= y82_neg;
y81_msb <= y82_msb;
y81_et_zero <= y82_et_zero;
y82_pos <= y73_pos;
y82_neg <= y73_neg;
y82_msb <= y73_msb;
y82_et_zero <= y73_et_zero;
y73_pos <= y64_pos;
y73_neg <= y64_neg;
y73_msb <= y64_msb;
y73_et_zero <= y64_et_zero;
y64_pos <= y55_pos;
y64_neg <= y55_neg;
y64_msb <= y55_msb;
y64_et_zero <= y55_et_zero;
y55_pos <= y46_pos;
y55_neg <= y46_neg;
y55_msb <= y46_msb;
y55_et_zero <= y46_et_zero;
y46_pos <= y37_pos;
y46_neg <= y37_neg;
y46_msb <= y37_msb;
y46_et_zero <= y37_et_zero;
y37_pos <= y28_pos;
y37_neg <= y28_neg;
y37_msb <= y28_msb;
y37_et_zero <= y28_et_zero;
y28_pos <= y38_pos;
y28_neg <= y38_neg;
y28_msb <= y38_msb;
y28_et_zero <= y38_et_zero;
y38_pos <= y47_pos;
y38_neg <= y47_neg;
y38_msb <= y47_msb;
y38_et_zero <= y47_et_zero;
y47_pos <= y56_pos;
y47_neg <= y56_neg;
y47_msb <= y56_msb;
y47_et_zero <= y56_et_zero;
y56_pos <= y65_pos;
y56_neg <= y65_neg;
y56_msb <= y65_msb;
y56_et_zero <= y65_et_zero;
y65_pos <= y74_pos;
y65_neg <= y74_neg;
y65_msb <= y74_msb;
y65_et_zero <= y74_et_zero;
y74_pos <= y83_pos;
y74_neg <= y83_neg;
y74_msb <= y83_msb;
y74_et_zero <= y83_et_zero;
y83_pos <= y84_pos;
y83_neg <= y84_neg;
y83_msb <= y84_msb;
y83_et_zero <= y84_et_zero;
y84_pos <= y75_pos;
y84_neg <= y75_neg;
y84_msb <= y75_msb;
y84_et_zero <= y75_et_zero;
y75_pos <= y66_pos;
y75_neg <= y66_neg;
y75_msb <= y66_msb;
y75_et_zero <= y66_et_zero;
y66_pos <= y57_pos;
y66_neg <= y57_neg;
y66_msb <= y57_msb;
y66_et_zero <= y57_et_zero;
y57_pos <= y48_pos;
y57_neg <= y48_neg;
y57_msb <= y48_msb;
y57_et_zero <= y48_et_zero;
y48_pos <= y58_pos;
y48_neg <= y58_neg;
y48_msb <= y58_msb;
y48_et_zero <= y58_et_zero;
y58_pos <= y67_pos;
y58_neg <= y67_neg;
y58_msb <= y67_msb;
y58_et_zero <= y67_et_zero;
y67_pos <= y76_pos;
y67_neg <= y76_neg;
y67_msb <= y76_msb;
y67_et_zero <= y76_et_zero;
y76_pos <= y85_pos;
y76_neg <= y85_neg;
y76_msb <= y85_msb;
y76_et_zero <= y85_et_zero;
y85_pos <= y86_pos;
y85_neg <= y86_neg;
y85_msb <= y86_msb;
y85_et_zero <= y86_et_zero;
y86_pos <= y77_pos;
y86_neg <= y77_neg;
y86_msb <= y77_msb;
y86_et_zero <= y77_et_zero;
y77_pos <= y68_pos;
y77_neg <= y68_neg;
y77_msb <= y68_msb;
y77_et_zero <= y68_et_zero;
y68_pos <= y78_pos;
y68_neg <= y78_neg;
y68_msb <= y78_msb;
y68_et_zero <= y78_et_zero;
y78_pos <= y87_pos;
y78_neg <= y87_neg;
y78_msb <= y87_msb;
y78_et_zero <= y87_et_zero;
y87_pos <= y88_pos;
y87_neg <= y88_neg;
y87_msb <= y88_msb;
y87_et_zero <= y88_et_zero;
y88_pos <= 0;
y88_neg <= 0;
y88_msb <= 0;
y88_et_zero <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
y11_diff <= 0; y11_1 <= 0;
end
else if (enable) begin y11_diff <= {y11[10], y11} - y11_previous;
y11_1 <= y11[10] ? { 1'b1, y11 } : { 1'b0, y11 };
end
end
always @(posedge clk)
begin
if (rst)
y11_bits_pos <= 0;
else if (y11_1_pos[10] == 1)
y11_bits_pos <= 11;
else if (y11_1_pos[9] == 1)
y11_bits_pos <= 10;
else if (y11_1_pos[8] == 1)
y11_bits_pos <= 9;
else if (y11_1_pos[7] == 1)
y11_bits_pos <= 8;
else if (y11_1_pos[6] == 1)
y11_bits_pos <= 7;
else if (y11_1_pos[5] == 1)
y11_bits_pos <= 6;
else if (y11_1_pos[4] == 1)
y11_bits_pos <= 5;
else if (y11_1_pos[3] == 1)
y11_bits_pos <= 4;
else if (y11_1_pos[2] == 1)
y11_bits_pos <= 3;
else if (y11_1_pos[1] == 1)
y11_bits_pos <= 2;
else if (y11_1_pos[0] == 1)
y11_bits_pos <= 1;
else
y11_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
y11_bits_neg <= 0;
else if (y11_1_neg[10] == 0)
y11_bits_neg <= 11;
else if (y11_1_neg[9] == 0)
y11_bits_neg <= 10;
else if (y11_1_neg[8] == 0)
y11_bits_neg <= 9;
else if (y11_1_neg[7] == 0)
y11_bits_neg <= 8;
else if (y11_1_neg[6] == 0)
y11_bits_neg <= 7;
else if (y11_1_neg[5] == 0)
y11_bits_neg <= 6;
else if (y11_1_neg[4] == 0)
y11_bits_neg <= 5;
else if (y11_1_neg[3] == 0)
y11_bits_neg <= 4;
else if (y11_1_neg[2] == 0)
y11_bits_neg <= 3;
else if (y11_1_neg[1] == 0)
y11_bits_neg <= 2;
else if (y11_1_neg[0] == 0)
y11_bits_neg <= 1;
else
y11_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst)
y12_bits_pos <= 0;
else if (y12_pos[9] == 1)
y12_bits_pos <= 10;
else if (y12_pos[8] == 1)
y12_bits_pos <= 9;
else if (y12_pos[7] == 1)
y12_bits_pos <= 8;
else if (y12_pos[6] == 1)
y12_bits_pos <= 7;
else if (y12_pos[5] == 1)
y12_bits_pos <= 6;
else if (y12_pos[4] == 1)
y12_bits_pos <= 5;
else if (y12_pos[3] == 1)
y12_bits_pos <= 4;
else if (y12_pos[2] == 1)
y12_bits_pos <= 3;
else if (y12_pos[1] == 1)
y12_bits_pos <= 2;
else if (y12_pos[0] == 1)
y12_bits_pos <= 1;
else
y12_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
y12_bits_neg <= 0;
else if (y12_neg[9] == 0)
y12_bits_neg <= 10;
else if (y12_neg[8] == 0)
y12_bits_neg <= 9;
else if (y12_neg[7] == 0)
y12_bits_neg <= 8;
else if (y12_neg[6] == 0)
y12_bits_neg <= 7;
else if (y12_neg[5] == 0)
y12_bits_neg <= 6;
else if (y12_neg[4] == 0)
y12_bits_neg <= 5;
else if (y12_neg[3] == 0)
y12_bits_neg <= 4;
else if (y12_neg[2] == 0)
y12_bits_neg <= 3;
else if (y12_neg[1] == 0)
y12_bits_neg <= 2;
else if (y12_neg[0] == 0)
y12_bits_neg <= 1;
else
y12_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst) begin
enable_module <= 0;
end
else if (enable) begin
enable_module <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_7 <= 0;
end
else if (block_counter == 68) begin
enable_latch_7 <= 0;
end
else if (enable_6) begin
enable_latch_7 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_8 <= 0;
end
else if (enable_7) begin
enable_latch_8 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
enable_13 <= 0;
end
else begin
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
enable_13 <= enable_12;
end
end
always @(posedge clk)
begin
y_dc_code_length[0] <= 2;
y_dc_code_length[1] <= 2;
y_dc_code_length[2] <= 2;
y_dc_code_length[3] <= 3;
y_dc_code_length[4] <= 4;
y_dc_code_length[5] <= 5;
y_dc_code_length[6] <= 6;
y_dc_code_length[7] <= 7;
y_dc_code_length[8] <= 8;
y_dc_code_length[9] <= 9;
y_dc_code_length[10] <= 10;
y_dc_code_length[11] <= 11;
y_dc[0] <= 11'b00000000000;
y_dc[1] <= 11'b01000000000;
y_dc[2] <= 11'b10000000000;
y_dc[3] <= 11'b11000000000;
y_dc[4] <= 11'b11100000000;
y_dc[5] <= 11'b11110000000;
y_dc[6] <= 11'b11111000000;
y_dc[7] <= 11'b11111100000;
y_dc[8] <= 11'b11111110000;
y_dc[9] <= 11'b11111111000;
y_dc[10] <= 11'b11111111100;
y_dc[11] <= 11'b11111111110;
y_ac_code_length[0] <= 2;
y_ac_code_length[1] <= 2;
y_ac_code_length[2] <= 3;
y_ac_code_length[3] <= 4;
y_ac_code_length[4] <= 4;
y_ac_code_length[5] <= 4;
y_ac_code_length[6] <= 5;
y_ac_code_length[7] <= 5;
y_ac_code_length[8] <= 5;
y_ac_code_length[9] <= 6;
y_ac_code_length[10] <= 6;
y_ac_code_length[11] <= 7;
y_ac_code_length[12] <= 7;
y_ac_code_length[13] <= 7;
y_ac_code_length[14] <= 7;
y_ac_code_length[15] <= 8;
y_ac_code_length[16] <= 8;
y_ac_code_length[17] <= 8;
y_ac_code_length[18] <= 9;
y_ac_code_length[19] <= 9;
y_ac_code_length[20] <= 9;
y_ac_code_length[21] <= 9;
y_ac_code_length[22] <= 9;
y_ac_code_length[23] <= 10;
y_ac_code_length[24] <= 10;
y_ac_code_length[25] <= 10;
y_ac_code_length[26] <= 10;
y_ac_code_length[27] <= 10;
y_ac_code_length[28] <= 11;
y_ac_code_length[29] <= 11;
y_ac_code_length[30] <= 11;
y_ac_code_length[31] <= 11;
y_ac_code_length[32] <= 12;
y_ac_code_length[33] <= 12;
y_ac_code_length[34] <= 12;
y_ac_code_length[35] <= 12;
y_ac_code_length[36] <= 15;
y_ac_code_length[37] <= 16;
y_ac_code_length[38] <= 16;
y_ac_code_length[39] <= 16;
y_ac_code_length[40] <= 16;
y_ac_code_length[41] <= 16;
y_ac_code_length[42] <= 16;
y_ac_code_length[43] <= 16;
y_ac_code_length[44] <= 16;
y_ac_code_length[45] <= 16;
y_ac_code_length[46] <= 16;
y_ac_code_length[47] <= 16;
y_ac_code_length[48] <= 16;
y_ac_code_length[49] <= 16;
y_ac_code_length[50] <= 16;
y_ac_code_length[51] <= 16;
y_ac_code_length[52] <= 16;
y_ac_code_length[53] <= 16;
y_ac_code_length[54] <= 16;
y_ac_code_length[55] <= 16;
y_ac_code_length[56] <= 16;
y_ac_code_length[57] <= 16;
y_ac_code_length[58] <= 16;
y_ac_code_length[59] <= 16;
y_ac_code_length[60] <= 16;
y_ac_code_length[61] <= 16;
y_ac_code_length[62] <= 16;
y_ac_code_length[63] <= 16;
y_ac_code_length[64] <= 16;
y_ac_code_length[65] <= 16;
y_ac_code_length[66] <= 16;
y_ac_code_length[67] <= 16;
y_ac_code_length[68] <= 16;
y_ac_code_length[69] <= 16;
y_ac_code_length[70] <= 16;
y_ac_code_length[71] <= 16;
y_ac_code_length[72] <= 16;
y_ac_code_length[73] <= 16;
y_ac_code_length[74] <= 16;
y_ac_code_length[75] <= 16;
y_ac_code_length[76] <= 16;
y_ac_code_length[77] <= 16;
y_ac_code_length[78] <= 16;
y_ac_code_length[79] <= 16;
y_ac_code_length[80] <= 16;
y_ac_code_length[81] <= 16;
y_ac_code_length[82] <= 16;
y_ac_code_length[83] <= 16;
y_ac_code_length[84] <= 16;
y_ac_code_length[85] <= 16;
y_ac_code_length[86] <= 16;
y_ac_code_length[87] <= 16;
y_ac_code_length[88] <= 16;
y_ac_code_length[89] <= 16;
y_ac_code_length[90] <= 16;
y_ac_code_length[91] <= 16;
y_ac_code_length[92] <= 16;
y_ac_code_length[93] <= 16;
y_ac_code_length[94] <= 16;
y_ac_code_length[95] <= 16;
y_ac_code_length[96] <= 16;
y_ac_code_length[97] <= 16;
y_ac_code_length[98] <= 16;
y_ac_code_length[99] <= 16;
y_ac_code_length[100] <= 16;
y_ac_code_length[101] <= 16;
y_ac_code_length[102] <= 16;
y_ac_code_length[103] <= 16;
y_ac_code_length[104] <= 16;
y_ac_code_length[105] <= 16;
y_ac_code_length[106] <= 16;
y_ac_code_length[107] <= 16;
y_ac_code_length[108] <= 16;
y_ac_code_length[109] <= 16;
y_ac_code_length[110] <= 16;
y_ac_code_length[111] <= 16;
y_ac_code_length[112] <= 16;
y_ac_code_length[113] <= 16;
y_ac_code_length[114] <= 16;
y_ac_code_length[115] <= 16;
y_ac_code_length[116] <= 16;
y_ac_code_length[117] <= 16;
y_ac_code_length[118] <= 16;
y_ac_code_length[119] <= 16;
y_ac_code_length[120] <= 16;
y_ac_code_length[121] <= 16;
y_ac_code_length[122] <= 16;
y_ac_code_length[123] <= 16;
y_ac_code_length[124] <= 16;
y_ac_code_length[125] <= 16;
y_ac_code_length[126] <= 16;
y_ac_code_length[127] <= 16;
y_ac_code_length[128] <= 16;
y_ac_code_length[129] <= 16;
y_ac_code_length[130] <= 16;
y_ac_code_length[131] <= 16;
y_ac_code_length[132] <= 16;
y_ac_code_length[133] <= 16;
y_ac_code_length[134] <= 16;
y_ac_code_length[135] <= 16;
y_ac_code_length[136] <= 16;
y_ac_code_length[137] <= 16;
y_ac_code_length[138] <= 16;
y_ac_code_length[139] <= 16;
y_ac_code_length[140] <= 16;
y_ac_code_length[141] <= 16;
y_ac_code_length[142] <= 16;
y_ac_code_length[143] <= 16;
y_ac_code_length[144] <= 16;
y_ac_code_length[145] <= 16;
y_ac_code_length[146] <= 16;
y_ac_code_length[147] <= 16;
y_ac_code_length[148] <= 16;
y_ac_code_length[149] <= 16;
y_ac_code_length[150] <= 16;
y_ac_code_length[151] <= 16;
y_ac_code_length[152] <= 16;
y_ac_code_length[153] <= 16;
y_ac_code_length[154] <= 16;
y_ac_code_length[155] <= 16;
y_ac_code_length[156] <= 16;
y_ac_code_length[157] <= 16;
y_ac_code_length[158] <= 16;
y_ac_code_length[159] <= 16;
y_ac_code_length[160] <= 16;
y_ac_code_length[161] <= 16;
y_ac[0] <= 16'b0000000000000000;
y_ac[1] <= 16'b0100000000000000;
y_ac[2] <= 16'b1000000000000000;
y_ac[3] <= 16'b1010000000000000;
y_ac[4] <= 16'b1011000000000000;
y_ac[5] <= 16'b1100000000000000;
y_ac[6] <= 16'b1101000000000000;
y_ac[7] <= 16'b1101100000000000;
y_ac[8] <= 16'b1110000000000000;
y_ac[9] <= 16'b1110100000000000;
y_ac[10] <= 16'b1110110000000000;
y_ac[11] <= 16'b1111000000000000;
y_ac[12] <= 16'b1111001000000000;
y_ac[13] <= 16'b1111010000000000;
y_ac[14] <= 16'b1111011000000000;
y_ac[15] <= 16'b1111100000000000;
y_ac[16] <= 16'b1111100100000000;
y_ac[17] <= 16'b1111101000000000;
y_ac[18] <= 16'b1111101100000000;
y_ac[19] <= 16'b1111101110000000;
y_ac[20] <= 16'b1111110000000000;
y_ac[21] <= 16'b1111110010000000;
y_ac[22] <= 16'b1111110100000000;
y_ac[23] <= 16'b1111110110000000;
y_ac[24] <= 16'b1111110111000000;
y_ac[25] <= 16'b1111111000000000;
y_ac[26] <= 16'b1111111001000000;
y_ac[27] <= 16'b1111111010000000;
y_ac[28] <= 16'b1111111011000000;
y_ac[29] <= 16'b1111111011100000;
y_ac[30] <= 16'b1111111100000000;
y_ac[31] <= 16'b1111111100100000;
y_ac[32] <= 16'b1111111101000000;
y_ac[33] <= 16'b1111111101010000;
y_ac[34] <= 16'b1111111101100000;
y_ac[35] <= 16'b1111111101110000;
y_ac[36] <= 16'b1111111110000000;
y_ac[37] <= 16'b1111111110000010;
y_ac[38] <= 16'b1111111110000011;
y_ac[39] <= 16'b1111111110000100;
y_ac[40] <= 16'b1111111110000101;
y_ac[41] <= 16'b1111111110000110;
y_ac[42] <= 16'b1111111110000111;
y_ac[43] <= 16'b1111111110001000;
y_ac[44] <= 16'b1111111110001001;
y_ac[45] <= 16'b1111111110001010;
y_ac[46] <= 16'b1111111110001011;
y_ac[47] <= 16'b1111111110001100;
y_ac[48] <= 16'b1111111110001101;
y_ac[49] <= 16'b1111111110001110;
y_ac[50] <= 16'b1111111110001111;
y_ac[51] <= 16'b1111111110010000;
y_ac[52] <= 16'b1111111110010001;
y_ac[53] <= 16'b1111111110010010;
y_ac[54] <= 16'b1111111110010011;
y_ac[55] <= 16'b1111111110010100;
y_ac[56] <= 16'b1111111110010101;
y_ac[57] <= 16'b1111111110010110;
y_ac[58] <= 16'b1111111110010111;
y_ac[59] <= 16'b1111111110011000;
y_ac[60] <= 16'b1111111110011001;
y_ac[61] <= 16'b1111111110011010;
y_ac[62] <= 16'b1111111110011011;
y_ac[63] <= 16'b1111111110011100;
y_ac[64] <= 16'b1111111110011101;
y_ac[65] <= 16'b1111111110011110;
y_ac[66] <= 16'b1111111110011111;
y_ac[67] <= 16'b1111111110100000;
y_ac[68] <= 16'b1111111110100001;
y_ac[69] <= 16'b1111111110100010;
y_ac[70] <= 16'b1111111110100011;
y_ac[71] <= 16'b1111111110100100;
y_ac[72] <= 16'b1111111110100101;
y_ac[73] <= 16'b1111111110100110;
y_ac[74] <= 16'b1111111110100111;
y_ac[75] <= 16'b1111111110101000;
y_ac[76] <= 16'b1111111110101001;
y_ac[77] <= 16'b1111111110101010;
y_ac[78] <= 16'b1111111110101011;
y_ac[79] <= 16'b1111111110101100;
y_ac[80] <= 16'b1111111110101101;
y_ac[81] <= 16'b1111111110101110;
y_ac[82] <= 16'b1111111110101111;
y_ac[83] <= 16'b1111111110110000;
y_ac[84] <= 16'b1111111110110001;
y_ac[85] <= 16'b1111111110110010;
y_ac[86] <= 16'b1111111110110011;
y_ac[87] <= 16'b1111111110110100;
y_ac[88] <= 16'b1111111110110101;
y_ac[89] <= 16'b1111111110110110;
y_ac[90] <= 16'b1111111110110111;
y_ac[91] <= 16'b1111111110111000;
y_ac[92] <= 16'b1111111110111001;
y_ac[93] <= 16'b1111111110111010;
y_ac[94] <= 16'b1111111110111011;
y_ac[95] <= 16'b1111111110111100;
y_ac[96] <= 16'b1111111110111101;
y_ac[97] <= 16'b1111111110111110;
y_ac[98] <= 16'b1111111110111111;
y_ac[99] <= 16'b1111111111000000;
y_ac[100] <= 16'b1111111111000001;
y_ac[101] <= 16'b1111111111000010;
y_ac[102] <= 16'b1111111111000011;
y_ac[103] <= 16'b1111111111000100;
y_ac[104] <= 16'b1111111111000101;
y_ac[105] <= 16'b1111111111000110;
y_ac[106] <= 16'b1111111111000111;
y_ac[107] <= 16'b1111111111001000;
y_ac[108] <= 16'b1111111111001001;
y_ac[109] <= 16'b1111111111001010;
y_ac[110] <= 16'b1111111111001011;
y_ac[111] <= 16'b1111111111001100;
y_ac[112] <= 16'b1111111111001101;
y_ac[113] <= 16'b1111111111001110;
y_ac[114] <= 16'b1111111111001111;
y_ac[115] <= 16'b1111111111010000;
y_ac[116] <= 16'b1111111111010001;
y_ac[117] <= 16'b1111111111010010;
y_ac[118] <= 16'b1111111111010011;
y_ac[119] <= 16'b1111111111010100;
y_ac[120] <= 16'b1111111111010101;
y_ac[121] <= 16'b1111111111010110;
y_ac[122] <= 16'b1111111111010111;
y_ac[123] <= 16'b1111111111011000;
y_ac[124] <= 16'b1111111111011001;
y_ac[125] <= 16'b1111111111011010;
y_ac[126] <= 16'b1111111111011011;
y_ac[127] <= 16'b1111111111011100;
y_ac[128] <= 16'b1111111111011101;
y_ac[129] <= 16'b1111111111011110;
y_ac[130] <= 16'b1111111111011111;
y_ac[131] <= 16'b1111111111100000;
y_ac[132] <= 16'b1111111111100001;
y_ac[133] <= 16'b1111111111100010;
y_ac[134] <= 16'b1111111111100011;
y_ac[135] <= 16'b1111111111100100;
y_ac[136] <= 16'b1111111111100101;
y_ac[137] <= 16'b1111111111100110;
y_ac[138] <= 16'b1111111111100111;
y_ac[139] <= 16'b1111111111101000;
y_ac[140] <= 16'b1111111111101001;
y_ac[141] <= 16'b1111111111101010;
y_ac[142] <= 16'b1111111111101011;
y_ac[143] <= 16'b1111111111101100;
y_ac[144] <= 16'b1111111111101101;
y_ac[145] <= 16'b1111111111101110;
y_ac[146] <= 16'b1111111111101111;
y_ac[147] <= 16'b1111111111110000;
y_ac[148] <= 16'b1111111111110001;
y_ac[149] <= 16'b1111111111110010;
y_ac[150] <= 16'b1111111111110011;
y_ac[151] <= 16'b1111111111110100;
y_ac[152] <= 16'b1111111111110101;
y_ac[153] <= 16'b1111111111110110;
y_ac[154] <= 16'b1111111111110111;
y_ac[155] <= 16'b1111111111111000;
y_ac[156] <= 16'b1111111111111001;
y_ac[157] <= 16'b1111111111111010;
y_ac[158] <= 16'b1111111111111011;
y_ac[159] <= 16'b1111111111111100;
y_ac[160] <= 16'b1111111111111101;
y_ac[161] <= 16'b1111111111111110;
y_ac_run_code[1] <= 0;
y_ac_run_code[2] <= 1;
y_ac_run_code[3] <= 2;
y_ac_run_code[0] <= 3;
y_ac_run_code[4] <= 4;
y_ac_run_code[17] <= 5;
y_ac_run_code[5] <= 6;
y_ac_run_code[18] <= 7;
y_ac_run_code[33] <= 8;
y_ac_run_code[49] <= 9;
y_ac_run_code[65] <= 10;
y_ac_run_code[6] <= 11;
y_ac_run_code[19] <= 12;
y_ac_run_code[81] <= 13;
y_ac_run_code[97] <= 14;
y_ac_run_code[7] <= 15;
y_ac_run_code[34] <= 16;
y_ac_run_code[113] <= 17;
y_ac_run_code[20] <= 18;
y_ac_run_code[50] <= 19;
y_ac_run_code[129] <= 20;
y_ac_run_code[145] <= 21;
y_ac_run_code[161] <= 22;
y_ac_run_code[8] <= 23;
y_ac_run_code[35] <= 24;
y_ac_run_code[66] <= 25;
y_ac_run_code[177] <= 26;
y_ac_run_code[193] <= 27;
y_ac_run_code[21] <= 28;
y_ac_run_code[82] <= 29;
y_ac_run_code[209] <= 30;
y_ac_run_code[240] <= 31;
y_ac_run_code[36] <= 32;
y_ac_run_code[51] <= 33;
y_ac_run_code[98] <= 34;
y_ac_run_code[114] <= 35;
y_ac_run_code[130] <= 36;
y_ac_run_code[9] <= 37;
y_ac_run_code[10] <= 38;
y_ac_run_code[22] <= 39;
y_ac_run_code[23] <= 40;
y_ac_run_code[24] <= 41;
y_ac_run_code[25] <= 42;
y_ac_run_code[26] <= 43;
y_ac_run_code[37] <= 44;
y_ac_run_code[38] <= 45;
y_ac_run_code[39] <= 46;
y_ac_run_code[40] <= 47;
y_ac_run_code[41] <= 48;
y_ac_run_code[42] <= 49;
y_ac_run_code[52] <= 50;
y_ac_run_code[53] <= 51;
y_ac_run_code[54] <= 52;
y_ac_run_code[55] <= 53;
y_ac_run_code[56] <= 54;
y_ac_run_code[57] <= 55;
y_ac_run_code[58] <= 56;
y_ac_run_code[67] <= 57;
y_ac_run_code[68] <= 58;
y_ac_run_code[69] <= 59;
y_ac_run_code[70] <= 60;
y_ac_run_code[71] <= 61;
y_ac_run_code[72] <= 62;
y_ac_run_code[73] <= 63;
y_ac_run_code[74] <= 64;
y_ac_run_code[83] <= 65;
y_ac_run_code[84] <= 66;
y_ac_run_code[85] <= 67;
y_ac_run_code[86] <= 68;
y_ac_run_code[87] <= 69;
y_ac_run_code[88] <= 70;
y_ac_run_code[89] <= 71;
y_ac_run_code[90] <= 72;
y_ac_run_code[99] <= 73;
y_ac_run_code[100] <= 74;
y_ac_run_code[101] <= 75;
y_ac_run_code[102] <= 76;
y_ac_run_code[103] <= 77;
y_ac_run_code[104] <= 78;
y_ac_run_code[105] <= 79;
y_ac_run_code[106] <= 80;
y_ac_run_code[115] <= 81;
y_ac_run_code[116] <= 82;
y_ac_run_code[117] <= 83;
y_ac_run_code[118] <= 84;
y_ac_run_code[119] <= 85;
y_ac_run_code[120] <= 86;
y_ac_run_code[121] <= 87;
y_ac_run_code[122] <= 88;
y_ac_run_code[131] <= 89;
y_ac_run_code[132] <= 90;
y_ac_run_code[133] <= 91;
y_ac_run_code[134] <= 92;
y_ac_run_code[135] <= 93;
y_ac_run_code[136] <= 94;
y_ac_run_code[137] <= 95;
y_ac_run_code[138] <= 96;
y_ac_run_code[146] <= 97;
y_ac_run_code[147] <= 98;
y_ac_run_code[148] <= 99;
y_ac_run_code[149] <= 100;
y_ac_run_code[150] <= 101;
y_ac_run_code[151] <= 102;
y_ac_run_code[152] <= 103;
y_ac_run_code[153] <= 104;
y_ac_run_code[154] <= 105;
y_ac_run_code[162] <= 106;
y_ac_run_code[163] <= 107;
y_ac_run_code[164] <= 108;
y_ac_run_code[165] <= 109;
y_ac_run_code[166] <= 110;
y_ac_run_code[167] <= 111;
y_ac_run_code[168] <= 112;
y_ac_run_code[169] <= 113;
y_ac_run_code[170] <= 114;
y_ac_run_code[178] <= 115;
y_ac_run_code[179] <= 116;
y_ac_run_code[180] <= 117;
y_ac_run_code[181] <= 118;
y_ac_run_code[182] <= 119;
y_ac_run_code[183] <= 120;
y_ac_run_code[184] <= 121;
y_ac_run_code[185] <= 122;
y_ac_run_code[186] <= 123;
y_ac_run_code[194] <= 124;
y_ac_run_code[195] <= 125;
y_ac_run_code[196] <= 126;
y_ac_run_code[197] <= 127;
y_ac_run_code[198] <= 128;
y_ac_run_code[199] <= 129;
y_ac_run_code[200] <= 130;
y_ac_run_code[201] <= 131;
y_ac_run_code[202] <= 132;
y_ac_run_code[210] <= 133;
y_ac_run_code[211] <= 134;
y_ac_run_code[212] <= 135;
y_ac_run_code[213] <= 136;
y_ac_run_code[214] <= 137;
y_ac_run_code[215] <= 138;
y_ac_run_code[216] <= 139;
y_ac_run_code[217] <= 140;
y_ac_run_code[218] <= 141;
y_ac_run_code[225] <= 142;
y_ac_run_code[226] <= 143;
y_ac_run_code[227] <= 144;
y_ac_run_code[228] <= 145;
y_ac_run_code[229] <= 146;
y_ac_run_code[230] <= 147;
y_ac_run_code[231] <= 148;
y_ac_run_code[232] <= 149;
y_ac_run_code[233] <= 150;
y_ac_run_code[234] <= 151;
y_ac_run_code[241] <= 152;
y_ac_run_code[242] <= 153;
y_ac_run_code[243] <= 154;
y_ac_run_code[244] <= 155;
y_ac_run_code[245] <= 156;
y_ac_run_code[246] <= 157;
y_ac_run_code[247] <= 158;
y_ac_run_code[248] <= 159;
y_ac_run_code[249] <= 160;
y_ac_run_code[250] <= 161;
y_ac_run_code[16] <= 0;
y_ac_run_code[32] <= 0;
y_ac_run_code[48] <= 0;
y_ac_run_code[64] <= 0;
y_ac_run_code[80] <= 0;
y_ac_run_code[96] <= 0;
y_ac_run_code[112] <= 0;
y_ac_run_code[128] <= 0;
y_ac_run_code[144] <= 0;
y_ac_run_code[160] <= 0;
y_ac_run_code[176] <= 0;
y_ac_run_code[192] <= 0;
y_ac_run_code[208] <= 0;
y_ac_run_code[224] <= 0;
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[31] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[31] <= jpeg_bs_5[31];
else if (enable_module && orc_8 == 0)
jpeg_bitstream[31] <= jpeg_bs_5[31];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[30] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[30] <= jpeg_bs_5[30];
else if (enable_module && orc_8 <= 1)
jpeg_bitstream[30] <= jpeg_bs_5[30];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[29] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[29] <= jpeg_bs_5[29];
else if (enable_module && orc_8 <= 2)
jpeg_bitstream[29] <= jpeg_bs_5[29];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[28] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[28] <= jpeg_bs_5[28];
else if (enable_module && orc_8 <= 3)
jpeg_bitstream[28] <= jpeg_bs_5[28];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[27] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[27] <= jpeg_bs_5[27];
else if (enable_module && orc_8 <= 4)
jpeg_bitstream[27] <= jpeg_bs_5[27];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[26] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[26] <= jpeg_bs_5[26];
else if (enable_module && orc_8 <= 5)
jpeg_bitstream[26] <= jpeg_bs_5[26];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[25] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[25] <= jpeg_bs_5[25];
else if (enable_module && orc_8 <= 6)
jpeg_bitstream[25] <= jpeg_bs_5[25];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[24] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[24] <= jpeg_bs_5[24];
else if (enable_module && orc_8 <= 7)
jpeg_bitstream[24] <= jpeg_bs_5[24];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[23] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[23] <= jpeg_bs_5[23];
else if (enable_module && orc_8 <= 8)
jpeg_bitstream[23] <= jpeg_bs_5[23];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[22] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[22] <= jpeg_bs_5[22];
else if (enable_module && orc_8 <= 9)
jpeg_bitstream[22] <= jpeg_bs_5[22];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[21] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[21] <= jpeg_bs_5[21];
else if (enable_module && orc_8 <= 10)
jpeg_bitstream[21] <= jpeg_bs_5[21];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[20] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[20] <= jpeg_bs_5[20];
else if (enable_module && orc_8 <= 11)
jpeg_bitstream[20] <= jpeg_bs_5[20];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[19] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[19] <= jpeg_bs_5[19];
else if (enable_module && orc_8 <= 12)
jpeg_bitstream[19] <= jpeg_bs_5[19];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[18] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[18] <= jpeg_bs_5[18];
else if (enable_module && orc_8 <= 13)
jpeg_bitstream[18] <= jpeg_bs_5[18];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[17] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[17] <= jpeg_bs_5[17];
else if (enable_module && orc_8 <= 14)
jpeg_bitstream[17] <= jpeg_bs_5[17];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[16] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[16] <= jpeg_bs_5[16];
else if (enable_module && orc_8 <= 15)
jpeg_bitstream[16] <= jpeg_bs_5[16];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[15] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[15] <= jpeg_bs_5[15];
else if (enable_module && orc_8 <= 16)
jpeg_bitstream[15] <= jpeg_bs_5[15];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[14] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[14] <= jpeg_bs_5[14];
else if (enable_module && orc_8 <= 17)
jpeg_bitstream[14] <= jpeg_bs_5[14];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[13] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[13] <= jpeg_bs_5[13];
else if (enable_module && orc_8 <= 18)
jpeg_bitstream[13] <= jpeg_bs_5[13];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[12] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[12] <= jpeg_bs_5[12];
else if (enable_module && orc_8 <= 19)
jpeg_bitstream[12] <= jpeg_bs_5[12];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[11] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[11] <= jpeg_bs_5[11];
else if (enable_module && orc_8 <= 20)
jpeg_bitstream[11] <= jpeg_bs_5[11];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[10] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[10] <= jpeg_bs_5[10];
else if (enable_module && orc_8 <= 21)
jpeg_bitstream[10] <= jpeg_bs_5[10];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[9] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[9] <= jpeg_bs_5[9];
else if (enable_module && orc_8 <= 22)
jpeg_bitstream[9] <= jpeg_bs_5[9];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[8] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[8] <= jpeg_bs_5[8];
else if (enable_module && orc_8 <= 23)
jpeg_bitstream[8] <= jpeg_bs_5[8];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[7] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[7] <= jpeg_bs_5[7];
else if (enable_module && orc_8 <= 24)
jpeg_bitstream[7] <= jpeg_bs_5[7];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[6] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[6] <= jpeg_bs_5[6];
else if (enable_module && orc_8 <= 25)
jpeg_bitstream[6] <= jpeg_bs_5[6];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[5] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[5] <= jpeg_bs_5[5];
else if (enable_module && orc_8 <= 26)
jpeg_bitstream[5] <= jpeg_bs_5[5];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[4] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[4] <= jpeg_bs_5[4];
else if (enable_module && orc_8 <= 27)
jpeg_bitstream[4] <= jpeg_bs_5[4];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[3] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[3] <= jpeg_bs_5[3];
else if (enable_module && orc_8 <= 28)
jpeg_bitstream[3] <= jpeg_bs_5[3];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[2] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[2] <= jpeg_bs_5[2];
else if (enable_module && orc_8 <= 29)
jpeg_bitstream[2] <= jpeg_bs_5[2];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[1] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[1] <= jpeg_bs_5[1];
else if (enable_module && orc_8 <= 30)
jpeg_bitstream[1] <= jpeg_bs_5[1];
end
always @(posedge clk)
begin
if (rst)
jpeg_bitstream[0] <= 0;
else if (enable_module && rollover_7)
jpeg_bitstream[0] <= jpeg_bs_5[0];
else if (enable_module && orc_8 <= 31)
jpeg_bitstream[0] <= jpeg_bs_5[0];
end
endmodule |
module zipdiv(i_clk, i_reset, i_wr, i_signed, i_numerator, i_denominator,
o_busy, o_valid, o_err, o_quotient, o_flags);
parameter bw=32, lgbw = 5;
input wire i_clk, i_reset;
input wire i_wr, i_signed;
input wire [(bw-1):0] i_numerator, i_denominator;
output reg o_busy, o_valid, o_err;
output reg [(bw-1):0] o_quotient;
output wire [3:0] o_flags;
reg r_busy;
reg [(2*bw-2):0] r_divisor;
reg [(bw-1):0] r_dividend;
wire [(bw):0] diff; assign diff = r_dividend - r_divisor[(bw-1):0];
reg r_sign, pre_sign, r_z, r_c, last_bit;
reg [(lgbw-1):0] r_bit;
reg zero_divisor;
initial r_busy = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_busy <= 1'b0;
else if (i_wr)
r_busy <= 1'b1;
else if ((last_bit)||(zero_divisor))
r_busy <= 1'b0;
initial o_busy = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_busy <= 1'b0;
else if (i_wr)
o_busy <= 1'b1;
else if (((last_bit)&&(!r_sign))||(zero_divisor))
o_busy <= 1'b0;
else if (!r_busy)
o_busy <= 1'b0;
initial zero_divisor = 1'b0;
always @(posedge i_clk)
if (i_reset)
zero_divisor <= 1'b0;
else if (i_wr)
zero_divisor <= (i_denominator == 0);
else if (!r_busy)
zero_divisor <= 1'b0;
initial o_valid = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_valid <= 1'b0;
else if (r_busy)
begin
if ((last_bit)||(zero_divisor))
o_valid <= (zero_divisor)||(!r_sign);
end else if (r_sign)
begin
o_valid <= (!zero_divisor); end else
o_valid <= 1'b0;
initial o_err = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_err <= 1'b0;
else if (o_valid)
o_err <= 1'b0;
else if (((r_busy)||(r_sign))&&(zero_divisor))
o_err <= 1'b1;
else
o_err <= 1'b0;
initial r_bit = 0;
always @(posedge i_clk)
if (i_reset)
r_bit <= 0;
else if ((r_busy)&&(!pre_sign))
r_bit <= r_bit + 1'b1;
else
r_bit <= 0;
initial last_bit = 1'b0;
always @(posedge i_clk)
if (i_reset)
last_bit <= 1'b0;
else if (r_busy)
last_bit <= (r_bit == {(lgbw){1'b1}}-1'b1);
else
last_bit <= 1'b0;
initial pre_sign = 1'b0;
always @(posedge i_clk)
if (i_reset)
pre_sign <= 1'b0;
else if (i_wr)
pre_sign <= (i_signed)&&((i_numerator[bw-1])||(i_denominator[bw-1]));
else
pre_sign <= 1'b0;
initial r_z = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_z <= 1'b0;
else if((r_busy)&&(r_divisor[(2*bw-2):(bw)] == 0)&&(!diff[bw]))
r_z <= 1'b0;
else if (i_wr)
r_z <= 1'b1;
initial r_dividend = 0;
always @(posedge i_clk)
if (i_reset)
r_dividend <= 0;
else if (pre_sign)
begin
if (r_dividend[bw-1])
r_dividend <= -r_dividend;
end else if((r_busy)&&(r_divisor[(2*bw-2):(bw)]==0)&&(!diff[bw]))
r_dividend <= diff[(bw-1):0];
else if (!r_busy)
r_dividend <= i_numerator;
initial r_divisor = 0;
always @(posedge i_clk)
if (i_reset)
r_divisor <= 0;
else if (pre_sign)
begin
if (r_divisor[(2*bw-2)])
r_divisor[(2*bw-2):(bw-1)]
<= -r_divisor[(2*bw-2):(bw-1)];
end else if (r_busy)
r_divisor <= { 1'b0, r_divisor[(2*bw-2):1] };
else
r_divisor <= { i_denominator, {(bw-1){1'b0}} };
initial r_sign = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_sign <= 1'b0;
else if (pre_sign)
r_sign <= ((r_divisor[(2*bw-2)])^(r_dividend[(bw-1)]));
else if (r_busy)
r_sign <= (r_sign)&&(!zero_divisor);
else
r_sign <= 1'b0;
initial o_quotient = 0;
always @(posedge i_clk)
if (i_reset)
o_quotient <= 0;
else if (r_busy)
begin
o_quotient <= { o_quotient[(bw-2):0], 1'b0 };
if ((r_divisor[(2*bw-2):(bw)] == 0)&&(!diff[bw]))
o_quotient[0] <= 1'b1;
end else if (r_sign)
o_quotient <= -o_quotient;
else
o_quotient <= 0;
initial r_c = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_c <= 1'b0;
else
r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
wire w_n;
assign w_n = o_quotient[(bw-1)];
assign o_flags = { 1'b0, w_n, r_c, r_z };
`ifdef formal
reg f_past_valid;
initial f_past_valid = 0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
`ifdef div
`define assume assume
`else
`define assume assert
`endif
initial `assume(i_reset);
always @(*)
if (!f_past_valid)
`assume(i_reset);
always @(posedge i_clk)
if ((!f_past_valid)||($past(i_reset)))
begin
assert(!o_busy);
assert(!o_valid);
assert(!o_err);
assert(!r_busy);
assert(!zero_divisor);
assert(r_bit==0);
assert(!last_bit);
assert(!pre_sign);
assert(!r_z);
assert(r_dividend==0);
assert(o_quotient==0);
assert(!r_c);
assert(r_divisor==0);
`assume(!i_wr);
end
always @(*)
if (o_busy)
`assume(!i_wr);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(o_busy))&&(!o_busy))
begin
assert(o_valid);
end
always @(*)
if (o_err)
assert(o_valid);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_wr)))
assert(!pre_sign);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))&&($past(i_signed))
&&(|$past({i_numerator[bw-1],i_denominator[bw-1]})))
assert(pre_sign);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
assert(o_busy);
always @(posedge i_clk)
if ((f_past_valid)&&($past(o_valid)))
assert(!o_valid);
always @(*)
if ((o_valid)&&(!o_err))
assert(r_z == ((o_quotient == 0)? 1'b1:1'b0));
always @(*)
if ((o_valid)&&(!o_err))
assert(w_n == o_quotient[bw-1]);
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(r_busy))&&(!$past(i_wr)))
assert(!o_busy);
always @(posedge i_clk)
assert((!o_busy)||(!o_valid));
always @(posedge i_clk)
if(o_busy) `assume(!i_wr);
always @(*)
if(r_busy) assert(o_busy);
reg [bw:0] f_bits_set;
always @(posedge i_clk)
if (i_reset)
f_bits_set <= 0;
else if (i_wr)
f_bits_set <= 0;
else if ((r_busy)&&(!pre_sign))
f_bits_set <= { f_bits_set[bw-1:0], 1'b1 };
always @(*)
if ((o_valid)&&(!o_err))
assert((!f_bits_set[bw])&&(&f_bits_set[bw-1:0]));
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&($past(r_busy))
&&($past(r_divisor[2*bw-2:bw])==0))
begin
if ($past(r_divisor) == 0)
assert(o_err);
else if ($past(pre_sign))
begin
if ($past(r_dividend[bw-1]))
assert(r_dividend == -$past(r_dividend));
if ($past(r_divisor[(2*bw-2)]))
begin
assert(r_divisor[(2*bw-2):(bw-1)]
== -$past(r_divisor[(2*bw-2):(bw-1)]));
assert(r_divisor[bw-2:0] == 0);
end
end else begin
if (o_quotient[0])
assert(r_dividend == $past(diff));
else
assert(r_dividend == $past(r_dividend));
assert(r_divisor[2*bw-2]==0);
assert(r_divisor[2*bw-3:0]==$past(r_divisor[2*bw-2:1]));
end
if ($past(r_dividend) >= $past(r_divisor[bw-1:0]))
assert(o_quotient[0]);
else
assert(!o_quotient[0]);
end
`endif
endmodule |
module inverter (
input wire in,
output out );
assign out = !in;
endmodule |
module def_test (
input wire in,
output out,
output tied_to_zero,
output manufacturing_grid_missaligned_pin
);
assign tied_to_zero = 1;
assign manufacturing_grid_missaligned_pin = 1;
assign out = !in;
endmodule |
module counter #(
parameter bits = 32
)(
input clk,
input reset,
input valid,
input [3:0] wstrb,
input [15:0] wdata,
input [bits-1:0] la_write,
input [bits-1:0] la_input,
output ready,
output [15:0] rdata,
output [15:0] count
);
reg ready;
reg [15:0] count;
reg [15:0] rdata;
always @(posedge clk) begin
if (reset) begin
count <= 0;
ready <= 0;
end else begin
ready <= 1'b0;
if (~|la_write) begin
count <= count + 1;
end
if (valid && !ready) begin
ready <= 1'b1;
rdata <= count;
if (wstrb[0]) count[7:0] <= wdata[7:0];
if (wstrb[1]) count[15:8] <= wdata[15:8];
end else if (|la_write) begin
count <= la_write & la_input;
end
end
end
endmodule |
module e203_exu_branchslv(
input cmt_i_valid,
output cmt_i_ready,
input cmt_i_rv32,
input cmt_i_dret, input cmt_i_mret, input cmt_i_fencei, input cmt_i_bjp,
input cmt_i_bjp_prdt, input cmt_i_bjp_rslv, input [`e203_pc_size-1:0] cmt_i_pc,
input [`e203_xlen-1:0] cmt_i_imm,
input [`e203_pc_size-1:0] csr_epc_r,
input [`e203_pc_size-1:0] csr_dpc_r,
input nonalu_excpirq_flush_req_raw,
input brchmis_flush_ack,
output brchmis_flush_req,
output [`e203_pc_size-1:0] brchmis_flush_add_op1,
output [`e203_pc_size-1:0] brchmis_flush_add_op2,
`ifdef e203_timing_boost output [`e203_pc_size-1:0] brchmis_flush_pc,
`endif
output cmt_mret_ena,
output cmt_dret_ena,
output cmt_fencei_ena,
input clk,
input rst_n
);
wire brchmis_flush_ack_pre;
wire brchmis_flush_req_pre;
assign brchmis_flush_req = brchmis_flush_req_pre & (~nonalu_excpirq_flush_req_raw);
assign brchmis_flush_ack_pre = brchmis_flush_ack & (~nonalu_excpirq_flush_req_raw);
wire brchmis_need_flush = (
(cmt_i_bjp & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv))
| cmt_i_fencei
| cmt_i_mret
| cmt_i_dret
);
wire cmt_i_is_branch = (
cmt_i_bjp
| cmt_i_fencei
| cmt_i_mret
| cmt_i_dret
);
assign brchmis_flush_req_pre = cmt_i_valid & brchmis_need_flush;
assign brchmis_flush_add_op1 = cmt_i_dret ? csr_dpc_r : cmt_i_mret ? csr_epc_r : cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_dret ? `e203_pc_size'b0 : cmt_i_mret ? `e203_pc_size'b0 :
(cmt_i_fencei | cmt_i_bjp_prdt) ? (cmt_i_rv32 ? `e203_pc_size'd4 : `e203_pc_size'd2)
: cmt_i_imm[`e203_pc_size-1:0];
`ifdef e203_timing_boost assign brchmis_flush_pc =
(cmt_i_fencei | (cmt_i_bjp & cmt_i_bjp_prdt)) ? (cmt_i_pc + (cmt_i_rv32 ? `e203_pc_size'd4 : `e203_pc_size'd2)) :
(cmt_i_bjp & (~cmt_i_bjp_prdt)) ? (cmt_i_pc + cmt_i_imm[`e203_pc_size-1:0]) :
cmt_i_dret ? csr_dpc_r :
csr_epc_r ; `endif
wire brchmis_flush_hsked = brchmis_flush_req & brchmis_flush_ack;
assign cmt_mret_ena = cmt_i_mret & brchmis_flush_hsked;
assign cmt_dret_ena = cmt_i_dret & brchmis_flush_hsked;
assign cmt_fencei_ena = cmt_i_fencei & brchmis_flush_hsked;
assign cmt_i_ready = (~cmt_i_is_branch) |
(
(brchmis_need_flush ? brchmis_flush_ack_pre : 1'b1)
& (~nonalu_excpirq_flush_req_raw)
);
endmodule |
module axi_register_slice #(
parameter data_width = 32,
parameter forward_register = 0,
parameter backward_register = 0)
(
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [data_width-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [data_width-1:0] m_axi_data
);
wire [data_width-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [data_width-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if(forward_register == 1)begin
reg fwd_valid = 1'b0;
reg [data_width-1:0] fwd_data = 'h00;
assign fwd_valid_s = fwd_valid;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_data_s = fwd_data;
always@(posedge clk) begin
if(~fwd_valid | m_axi_ready)begin
fwd_data <= bwd_data_s;
end
end
always@(posedge clk) begin
if(resetn == 0)begin
fwd_valid <= 1'b0;
end
else begin
if(bwd_valid_s)begin
fwd_valid <= 1'b1;
end
else if(m_axi_ready) begin
fwd_valid <= 1'b0;
end
end
end
end
else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if(backward_register == 1)begin
reg bwd_ready = 1'b1;
reg [data_width-1:0] bwd_data = 'h00;
assign bwd_ready_s = bwd_ready;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
always@(posedge clk)begin
if(bwd_ready)begin
bwd_data <= s_axi_data;
end
end
always@(posedge clk)begin
if(resetn == 0)begin
bwd_ready <= 1'b1;
end
else begin
if(fwd_ready_s)begin
bwd_ready <= 1'b1;
end
else if(s_axi_valid)begin
bwd_ready <= 1'b0;
end
end
end
end
else begin
assign bwd_data_s = s_axi_data;
assign bwd_valid_s = s_axi_valid;
assign bwd_ready_s = fwd_ready_s;
end
endgenerate
assign s_axi_ready = bwd_ready_s;
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
endmodule |
module buffer_cell (
input wire in,
output wire out
);
assign out = in;
endmodule |
module and_cell (
input wire a,
input wire b,
output wire out
);
assign out = a & b;
endmodule |
module or_cell (
input wire a,
input wire b,
output wire out
);
assign out = a | b;
endmodule |
module xor_cell (
input wire a,
input wire b,
output wire out
);
assign out = a ^ b;
endmodule |
module nand_cell (
input wire a,
input wire b,
output wire out
);
assign out = !(a&b);
endmodule |
module not_cell (
input wire in,
output wire out
);
assign out = !in;
endmodule |
module mux_cell (
input wire a,
input wire b,
input wire sel,
output wire out
);
assign out = sel ? b : a;
endmodule |
module dff_cell (
input wire clk,
input wire d,
output reg q,
output wire notq
);
assign notq = !q;
always @(posedge clk)
q <= d;
endmodule |
module dffsr_cell (
input wire clk,
input wire d,
input wire s,
input wire r,
output reg q,
output wire notq
);
assign notq = !q;
always @(posedge clk or posedge s or posedge r) begin
if (r)
q <= 0;
else if (s)
q <= 1;
else
q <= d;
end
endmodule |
module vgasyncgen (
output reg io_h_sync,
output reg io_v_sync,
output reg io_activevideo,
output reg [9:0] io_x,
output reg [9:0] io_y,
input clk,
input reset
);
wire [9:0] _zz_h_counter_valuenext;
wire [0:0] _zz_h_counter_valuenext_1;
wire [9:0] _zz_v_counter_valuenext;
wire [0:0] _zz_v_counter_valuenext_1;
reg h_counter_willincrement;
wire h_counter_willclear;
reg [9:0] h_counter_valuenext;
reg [9:0] h_counter_value;
wire h_counter_willoverflowifinc;
wire h_counter_willoverflow;
reg v_counter_willincrement;
wire v_counter_willclear;
reg [9:0] v_counter_valuenext;
reg [9:0] v_counter_value;
wire v_counter_willoverflowifinc;
wire v_counter_willoverflow;
wire when_vgasyncgen_l29;
wire when_vgasyncgen_l36;
wire when_vgasyncgen_l44;
function zz_h_counter_willincrement(input dummy);
begin
zz_h_counter_willincrement = 1'b0; zz_h_counter_willincrement = 1'b1; end
endfunction
wire _zz_1;
assign _zz_h_counter_valuenext_1 = h_counter_willincrement;
assign _zz_h_counter_valuenext = {9'd0, _zz_h_counter_valuenext_1};
assign _zz_v_counter_valuenext_1 = v_counter_willincrement;
assign _zz_v_counter_valuenext = {9'd0, _zz_v_counter_valuenext_1};
assign _zz_1 = zz_h_counter_willincrement(1'b0);
always @(*) h_counter_willincrement = _zz_1;
assign h_counter_willclear = 1'b0; assign h_counter_willoverflowifinc = (h_counter_value == 10'h31f); assign h_counter_willoverflow = (h_counter_willoverflowifinc && h_counter_willincrement); always @(*) begin
if(h_counter_willoverflow) begin
h_counter_valuenext = 10'h0; end else begin
h_counter_valuenext = (h_counter_value + _zz_h_counter_valuenext); end
if(h_counter_willclear) begin
h_counter_valuenext = 10'h0; end
end
always @(*) begin
v_counter_willincrement = 1'b0; if(h_counter_willoverflow) begin
v_counter_willincrement = 1'b1; end
end
assign v_counter_willclear = 1'b0; assign v_counter_willoverflowifinc = (v_counter_value == 10'h20b); assign v_counter_willoverflow = (v_counter_willoverflowifinc && v_counter_willincrement); always @(*) begin
if(v_counter_willoverflow) begin
v_counter_valuenext = 10'h0; end else begin
v_counter_valuenext = (v_counter_value + _zz_v_counter_valuenext); end
if(v_counter_willclear) begin
v_counter_valuenext = 10'h0; end
end
assign when_vgasyncgen_l29 = ((10'h010 <= h_counter_value) && (h_counter_value <= 10'h070)); always @(*) begin
if(when_vgasyncgen_l29) begin
io_h_sync = 1'b0; end else begin
io_h_sync = 1'b1; end
end
assign when_vgasyncgen_l36 = ((10'h00b <= v_counter_value) && (v_counter_value <= 10'h00d)); always @(*) begin
if(when_vgasyncgen_l36) begin
io_v_sync = 1'b0; end else begin
io_v_sync = 1'b1; end
end
assign when_vgasyncgen_l44 = ((10'h0a0 <= h_counter_value) && (10'h02c <= v_counter_value)); always @(*) begin
if(when_vgasyncgen_l44) begin
io_activevideo = 1'b1; end else begin
io_activevideo = 1'b0; end
end
always @(*) begin
if(when_vgasyncgen_l44) begin
io_x = (h_counter_value - 10'h0a0); end else begin
io_x = 10'h0; end
end
always @(*) begin
if(when_vgasyncgen_l44) begin
io_y = (v_counter_value - 10'h02c); end else begin
io_y = 10'h0; end
end
always @(posedge clk or posedge reset) begin
if(reset) begin
h_counter_value <= 10'h0; v_counter_value <= 10'h0; end else begin
h_counter_value <= h_counter_valuenext; v_counter_value <= v_counter_valuenext; end
end
endmodule |
module clockcounters (
output [5:0] io_seconds,
output [5:0] io_minutes,
output [3:0] io_hours,
input clk,
input reset
);
wire [24:0] _zz_c_counter_valuenext;
wire [0:0] _zz_c_counter_valuenext_1;
wire [5:0] _zz_s_counter_valuenext;
wire [0:0] _zz_s_counter_valuenext_1;
wire [5:0] _zz_m_counter_valuenext;
wire [0:0] _zz_m_counter_valuenext_1;
wire [3:0] _zz_h_counter_valuenext;
wire [0:0] _zz_h_counter_valuenext_1;
reg c_counter_willincrement;
wire c_counter_willclear;
reg [24:0] c_counter_valuenext;
reg [24:0] c_counter_value;
wire c_counter_willoverflowifinc;
wire c_counter_willoverflow;
reg s_counter_willincrement;
wire s_counter_willclear;
reg [5:0] s_counter_valuenext;
reg [5:0] s_counter_value;
wire s_counter_willoverflowifinc;
wire s_counter_willoverflow;
reg m_counter_willincrement;
wire m_counter_willclear;
reg [5:0] m_counter_valuenext;
reg [5:0] m_counter_value;
wire m_counter_willoverflowifinc;
wire m_counter_willoverflow;
reg h_counter_willincrement;
wire h_counter_willclear;
reg [3:0] h_counter_valuenext;
reg [3:0] h_counter_value;
wire h_counter_willoverflowifinc;
wire h_counter_willoverflow;
function zz_c_counter_willincrement(input dummy);
begin
zz_c_counter_willincrement = 1'b0; zz_c_counter_willincrement = 1'b1; end
endfunction
wire _zz_1;
assign _zz_c_counter_valuenext_1 = c_counter_willincrement;
assign _zz_c_counter_valuenext = {24'd0, _zz_c_counter_valuenext_1};
assign _zz_s_counter_valuenext_1 = s_counter_willincrement;
assign _zz_s_counter_valuenext = {5'd0, _zz_s_counter_valuenext_1};
assign _zz_m_counter_valuenext_1 = m_counter_willincrement;
assign _zz_m_counter_valuenext = {5'd0, _zz_m_counter_valuenext_1};
assign _zz_h_counter_valuenext_1 = h_counter_willincrement;
assign _zz_h_counter_valuenext = {3'd0, _zz_h_counter_valuenext_1};
assign _zz_1 = zz_c_counter_willincrement(1'b0);
always @(*) c_counter_willincrement = _zz_1;
assign c_counter_willclear = 1'b0; assign c_counter_willoverflowifinc = (c_counter_value == 25'h17d783f); assign c_counter_willoverflow = (c_counter_willoverflowifinc && c_counter_willincrement); always @(*) begin
if(c_counter_willoverflow) begin
c_counter_valuenext = 25'h0; end else begin
c_counter_valuenext = (c_counter_value + _zz_c_counter_valuenext); end
if(c_counter_willclear) begin
c_counter_valuenext = 25'h0; end
end
always @(*) begin
s_counter_willincrement = 1'b0; if(c_counter_willoverflow) begin
s_counter_willincrement = 1'b1; end
end
assign s_counter_willclear = 1'b0; assign s_counter_willoverflowifinc = (s_counter_value == 6'h3b); assign s_counter_willoverflow = (s_counter_willoverflowifinc && s_counter_willincrement); always @(*) begin
if(s_counter_willoverflow) begin
s_counter_valuenext = 6'h0; end else begin
s_counter_valuenext = (s_counter_value + _zz_s_counter_valuenext); end
if(s_counter_willclear) begin
s_counter_valuenext = 6'h0; end
end
always @(*) begin
m_counter_willincrement = 1'b0; if(s_counter_willoverflow) begin
m_counter_willincrement = 1'b1; end
end
assign m_counter_willclear = 1'b0; assign m_counter_willoverflowifinc = (m_counter_value == 6'h3b); assign m_counter_willoverflow = (m_counter_willoverflowifinc && m_counter_willincrement); always @(*) begin
if(m_counter_willoverflow) begin
m_counter_valuenext = 6'h0; end else begin
m_counter_valuenext = (m_counter_value + _zz_m_counter_valuenext); end
if(m_counter_willclear) begin
m_counter_valuenext = 6'h0; end
end
always @(*) begin
h_counter_willincrement = 1'b0; if(m_counter_willoverflow) begin
h_counter_willincrement = 1'b1; end
end
assign h_counter_willclear = 1'b0; assign h_counter_willoverflowifinc = (h_counter_value == 4'b1011); assign h_counter_willoverflow = (h_counter_willoverflowifinc && h_counter_willincrement); always @(*) begin
if(h_counter_willoverflow) begin
h_counter_valuenext = 4'b0000; end else begin
h_counter_valuenext = (h_counter_value + _zz_h_counter_valuenext); end
if(h_counter_willclear) begin
h_counter_valuenext = 4'b0000; end
end
assign io_seconds = s_counter_value; assign io_minutes = m_counter_value; assign io_hours = h_counter_value; always @(posedge clk or posedge reset) begin
if(reset) begin
c_counter_value <= 25'h0; s_counter_value <= 6'h0; m_counter_value <= 6'h0; h_counter_value <= 4'b0000; end else begin
c_counter_value <= c_counter_valuenext; s_counter_value <= s_counter_valuenext; m_counter_value <= m_counter_valuenext; h_counter_value <= h_counter_valuenext; end
end
endmodule |
module e203_exu_longpwbck(
input lsu_wbck_i_valid, output lsu_wbck_i_ready, input [`e203_xlen-1:0] lsu_wbck_i_wdat,
input [`e203_itag_width -1:0] lsu_wbck_i_itag,
input lsu_wbck_i_err , input lsu_cmt_i_buserr ,
input [`e203_addr_size -1:0] lsu_cmt_i_badaddr,
input lsu_cmt_i_ld,
input lsu_cmt_i_st,
output longp_wbck_o_valid, input longp_wbck_o_ready, output [`e203_flen-1:0] longp_wbck_o_wdat,
output [5-1:0] longp_wbck_o_flags,
output [`e203_rfidx_width -1:0] longp_wbck_o_rdidx,
output longp_wbck_o_rdfpu,
output longp_excp_o_valid,
input longp_excp_o_ready,
output longp_excp_o_insterr,
output longp_excp_o_ld,
output longp_excp_o_st,
output longp_excp_o_buserr , output [`e203_addr_size-1:0] longp_excp_o_badaddr,
output [`e203_pc_size -1:0] longp_excp_o_pc,
input oitf_empty,
input [`e203_itag_width -1:0] oitf_ret_ptr,
input [`e203_rfidx_width-1:0] oitf_ret_rdidx,
input [`e203_pc_size-1:0] oitf_ret_pc,
input oitf_ret_rdwen,
input oitf_ret_rdfpu,
output oitf_ret_ena,
input clk,
input rst_n
);
wire wbck_ready4lsu = (lsu_wbck_i_itag == oitf_ret_ptr) & (~oitf_empty);
wire wbck_sel_lsu = lsu_wbck_i_valid & wbck_ready4lsu;
assign {
longp_excp_o_insterr
,longp_excp_o_ld
,longp_excp_o_st
,longp_excp_o_buserr
,longp_excp_o_badaddr } =
({`e203_addr_size+4{wbck_sel_lsu}} &
{
1'b0,
lsu_cmt_i_ld,
lsu_cmt_i_st,
lsu_cmt_i_buserr,
lsu_cmt_i_badaddr
})
;
wire wbck_i_ready;
wire wbck_i_valid;
wire [`e203_flen-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`e203_rfidx_width-1:0] wbck_i_rdidx;
wire [`e203_pc_size-1:0] wbck_i_pc;
wire wbck_i_rdwen;
wire wbck_i_rdfpu;
wire wbck_i_err ;
assign lsu_wbck_i_ready = wbck_ready4lsu & wbck_i_ready;
assign wbck_i_valid = ({1{wbck_sel_lsu}} & lsu_wbck_i_valid)
;
`ifdef e203_flen_is_32 wire [`e203_flen-1:0] lsu_wbck_i_wdat_exd = lsu_wbck_i_wdat;
`else wire [`e203_flen-1:0] lsu_wbck_i_wdat_exd = {{`e203_flen-`e203_xlen{1'b0}},lsu_wbck_i_wdat};
`endif assign wbck_i_wdat = ({`e203_flen{wbck_sel_lsu}} & lsu_wbck_i_wdat_exd )
;
assign wbck_i_flags = 5'b0
;
assign wbck_i_err = wbck_sel_lsu & lsu_wbck_i_err
;
assign wbck_i_pc = oitf_ret_pc;
assign wbck_i_rdidx = oitf_ret_rdidx;
assign wbck_i_rdwen = oitf_ret_rdwen;
assign wbck_i_rdfpu = oitf_ret_rdfpu;
wire need_wbck = wbck_i_rdwen & (~wbck_i_err);
wire need_excp = wbck_i_err;
assign wbck_i_ready =
(need_wbck ? longp_wbck_o_ready : 1'b1)
& (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_wbck_o_valid = need_wbck & wbck_i_valid & (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_excp_o_valid = need_excp & wbck_i_valid & (need_wbck ? longp_wbck_o_ready : 1'b1);
assign longp_wbck_o_wdat = wbck_i_wdat ;
assign longp_wbck_o_flags = wbck_i_flags ;
assign longp_wbck_o_rdfpu = wbck_i_rdfpu ;
assign longp_wbck_o_rdidx = wbck_i_rdidx;
assign longp_excp_o_pc = wbck_i_pc;
assign oitf_ret_ena = wbck_i_valid & wbck_i_ready;
endmodule |
module e203_exu_wbck(
input alu_wbck_i_valid, output alu_wbck_i_ready, input [`e203_xlen-1:0] alu_wbck_i_wdat,
input [`e203_rfidx_width-1:0] alu_wbck_i_rdidx,
input longp_wbck_i_valid, output longp_wbck_i_ready, input [`e203_flen-1:0] longp_wbck_i_wdat,
input [5-1:0] longp_wbck_i_flags,
input [`e203_rfidx_width-1:0] longp_wbck_i_rdidx,
input longp_wbck_i_rdfpu,
output rf_wbck_o_ena,
output [`e203_xlen-1:0] rf_wbck_o_wdat,
output [`e203_rfidx_width-1:0] rf_wbck_o_rdidx,
input clk,
input rst_n
);
wire wbck_ready4alu = (~longp_wbck_i_valid);
wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;
wire wbck_ready4longp = 1'b1;
wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;
wire rf_wbck_o_ready = 1'b1;
wire wbck_i_ready;
wire wbck_i_valid;
wire [`e203_flen-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`e203_rfidx_width-1:0] wbck_i_rdidx;
wire wbck_i_rdfpu;
assign alu_wbck_i_ready = wbck_ready4alu & wbck_i_ready;
assign longp_wbck_i_ready = wbck_ready4longp & wbck_i_ready;
assign wbck_i_valid = wbck_sel_alu ? alu_wbck_i_valid : longp_wbck_i_valid;
`ifdef e203_flen_is_32 assign wbck_i_wdat = wbck_sel_alu ? alu_wbck_i_wdat : longp_wbck_i_wdat;
`else assign wbck_i_wdat = wbck_sel_alu ? {{`e203_flen-`e203_xlen{1'b0}},alu_wbck_i_wdat} : longp_wbck_i_wdat;
`endif assign wbck_i_flags = wbck_sel_alu ? 5'b0 : longp_wbck_i_flags;
assign wbck_i_rdidx = wbck_sel_alu ? alu_wbck_i_rdidx : longp_wbck_i_rdidx;
assign wbck_i_rdfpu = wbck_sel_alu ? 1'b0 : longp_wbck_i_rdfpu;
assign wbck_i_ready = rf_wbck_o_ready;
wire rf_wbck_o_valid = wbck_i_valid;
wire wbck_o_ena = rf_wbck_o_valid & rf_wbck_o_ready;
assign rf_wbck_o_ena = wbck_o_ena & (~wbck_i_rdfpu);
assign rf_wbck_o_wdat = wbck_i_wdat[`e203_xlen-1:0];
assign rf_wbck_o_rdidx = wbck_i_rdidx;
endmodule |
module e203_irq_sync #(
parameter master = 1
) (
input clk,
input rst_n,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
input dbg_irq_a,
output ext_irq_r,
output sft_irq_r,
output tmr_irq_r,
output dbg_irq_r
);
generate
if(master == 1) begin:master_gen
`ifndef e203_has_lockstep `ifdef e203_irq_need_sync sirv_gnrl_sync # (
.dp(`e203_async_ff_levels),
.dw(1)
) u_dbg_irq_sync(
.din_a (dbg_irq_a),
.dout (dbg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.dp(`e203_async_ff_levels),
.dw(1)
) u_ext_irq_sync(
.din_a (ext_irq_a),
.dout (ext_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.dp(`e203_async_ff_levels),
.dw(1)
) u_sft_irq_sync(
.din_a (sft_irq_a),
.dout (sft_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.dp(`e203_async_ff_levels),
.dw(1)
) u_tmr_irq_sync(
.din_a (tmr_irq_a),
.dout (tmr_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
`else assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
`endif `endif
end
else begin:slave_gen
assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
end
endgenerate
endmodule |
module memory#(
parameter bits = 32
)(
input clk,
input rst,
input read_e,
input write_e,
input [31:0] data_in,
input [31:0] addr_in,
output reg ready,
output reg [575:0] ram_data_o
);
reg [575:0] enc_data;
reg [5:0] counter = 0;
always @(posedge clk)
begin
if(rst)
begin
ram_data_o <= 32'b0;
enc_data <= 32'b0;
counter <= 6'b0;
ready <= 0;
end
else
begin
if (read_e & !write_e & ready)
begin
if (addr_in == 32'h55)
begin
ram_data_o <= enc_data;
end
end
end
end
always @(posedge clk)
begin
if (!read_e & write_e & !ready & !rst)
begin
if (addr_in == 32'h55)
begin
if (counter<18)
begin
if (counter == 0)
enc_data[31:0] <= data_in[31:0];
else if (counter == 1)
enc_data[63:32] <= data_in[31:0];
else if (counter == 2)
enc_data[95:64] <= data_in[31:0];
else if (counter == 3)
enc_data[127:96] <= data_in[31:0];
else if (counter == 4)
enc_data[159:128] <= data_in[31:0];
else if (counter == 5)
enc_data[191:160] <= data_in[31:0];
else if (counter == 6)
enc_data[223:192] <= data_in[31:0];
else if (counter == 7)
enc_data[255:224] <= data_in[31:0];
else if (counter == 8)
enc_data[287:256] <= data_in[31:0];
else if (counter == 9)
enc_data[319:288] <= data_in[31:0];
else if (counter == 10)
enc_data[351:320] <= data_in[31:0];
else if (counter == 11)
enc_data[383:352] <= data_in[31:0];
else if (counter == 12)
enc_data[415:384] <= data_in[31:0];
else if (counter == 13)
enc_data[447:416] <= data_in[31:0];
else if (counter == 14)
enc_data[479:448] <= data_in[31:0];
else if (counter == 15)
enc_data[511:480] <= data_in[31:0];
else if (counter == 16)
enc_data[543:512] <= data_in[31:0];
else if (counter == 17)
begin
enc_data[575:544] <= data_in[31:0];
ready <= 1;
end
counter = counter + 1;
end
else
ready <= 1;
end
end
end
endmodule |
module theta_rho_pi_chi_iota(
input clk,
input rst,
input [1023:0] c_in,
input [575:0] x_data_in,
output reg [575:0] r_o,
output reg ready
);
reg [63:0] cube [4:0][4:0];
reg [2:0] step = 0;
reg [4:0] round;
reg [2:0] rst_counter = 0;
reg [2:0] rst_counter_1 = 0;
reg [2:0] rst_counter_2 = 0;
reg [2:0] rst_counter_3 = 0;
reg [2:0] rst_counter_4 = 0;
reg [63:0] b [4:0][4:0];
reg [63:0] c [4:0];
reg [63:0] d [4:0];
reg [2:0] c_counter = 0;
reg [2:0] d_counter = 0;
reg [2:0] a_counter = 0;
always @ (posedge clk)
begin
if(rst)
begin
r_o <= 0;
step <= 0;
round <= 0;
ready <= 0;
for(rst_counter_4=0; rst_counter_4<=4; rst_counter_4=rst_counter_4+1)
begin
c[rst_counter_4] <= 0;
d[rst_counter_4] <= 0;
end
for(rst_counter=0; rst_counter<=4; rst_counter=rst_counter+1)
begin
for(rst_counter_3=0; rst_counter_3<=4; rst_counter_3=rst_counter_3+1)
begin
b[rst_counter][rst_counter_3] <= 0;
end
end
for(rst_counter_1=0; rst_counter_1<=4; rst_counter_1=rst_counter_1+1)
begin
for(rst_counter_2=0; rst_counter_2<=4; rst_counter_2=rst_counter_2+1)
begin
cube[rst_counter_1][rst_counter_2] <= 0;
end
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step==0)
begin
ready <= 0;
cube[0][0] <= x_data_in[63:0];
cube[0][1] <= x_data_in[127:64];
cube[0][2] <= x_data_in[191:128];
cube[0][3] <= x_data_in[255:192];
cube[0][4] <= x_data_in[319:256];
cube[1][0] <= x_data_in[383:320];
cube[1][1] <= x_data_in[447:384];
cube[1][2] <= x_data_in[511:448];
cube[1][3] <= x_data_in[575:512];
cube[1][4] <= c_in[63:0];
cube[2][0] <= c_in[127:64];
cube[2][1] <= c_in[191:128];
cube[2][2] <= c_in[255:192];
cube[2][3] <= c_in[319:256];
cube[2][4] <= c_in[383:320];
cube[3][0] <= c_in[447:384];
cube[3][1] <= c_in[511:448];
cube[3][2] <= c_in[575:512];
cube[3][3] <= c_in[639:576];
cube[3][4] <= c_in[703:640];
cube[4][0] <= c_in[767:704];
cube[4][1] <= c_in[831:768];
cube[4][2] <= c_in[895:832];
cube[4][3] <= c_in[959:896];
cube[4][4] <= c_in[1023:960];
step <= 1;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 1)
begin
for(c_counter=0; c_counter<=4; c_counter=c_counter+1)
begin
c[c_counter] <= cube[c_counter][0] ^ cube[c_counter][1] ^ cube[c_counter][2] ^ cube[c_counter][3];
end
step <= 2;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 2)
begin
d[0] <= ({c[1][0],c[1][63:1]}) ^ c[4];
d[1] <= ({c[2][0],c[2][63:1]}) ^ c[0];
d[2] <= ({c[3][0],c[3][63:1]}) ^ c[1];
d[3] <= ({c[4][0],c[4][63:1]}) ^ c[2];
d[4] <= ({c[0][0],c[0][63:1]}) ^ c[3];
step <= 3;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 3)
begin
for(a_counter=0; a_counter<=4; a_counter=a_counter+1)
begin
for(d_counter=0; d_counter<=4; d_counter=d_counter+1)
begin
cube[a_counter][d_counter] <= cube[a_counter][d_counter] ^ d[a_counter];
end
end
step <= 4;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step==4)
begin
b[0][0] <= cube[0][0];
b[0][1] <= {cube[3][0][27:0],cube[3][0][63:28]};
b[0][2] <= {cube[1][0][0],cube[1][0][63:1]};
b[0][3] <= {cube[4][0][26:0],cube[4][0][63:27]};
b[0][4] <= {cube[2][0][61:0],cube[2][0][63:62]};
b[1][0] <= {cube[1][1][43:0],cube[1][1][63:44]};
b[1][1] <= {cube[4][1][19:0],cube[4][1][63:20]};
b[1][2] <= {cube[2][1][5:0],cube[2][1][63:6]};
b[1][3] <= {cube[0][1][35:0],cube[0][1][63:36]};
b[1][4] <= {cube[3][1][54:0],cube[3][1][63:55]};
b[2][0] <= {cube[2][2][42:0],cube[2][2][63:43]};
b[2][1] <= {cube[0][2][2:0],cube[0][2][63:3]};
b[2][2] <= {cube[3][2][24:0],cube[3][2][63:25]};
b[2][3] <= {cube[1][2][9:0],cube[1][2][63:10]};
b[2][4] <= {cube[4][2][38:0],cube[4][2][63:39]};
b[3][0] <= {cube[3][3][20:0],cube[3][3][63:21]};
b[3][1] <= {cube[1][3][44:0],cube[1][3][63:45]};
b[3][2] <= {cube[4][3][7:0],cube[4][3][63:8]};
b[3][3] <= {cube[2][3][14:0],cube[2][3][63:14]};
b[3][4] <= {cube[0][3][40:0],cube[0][3][63:41]};
b[4][0] <= {cube[4][4][13:0],cube[4][4][63:14]};
b[4][1] <= {cube[2][4][60:0],cube[2][4][63:61]};
b[4][2] <= {cube[0][4][17:0],cube[0][1][63:18]};
b[4][3] <= {cube[3][4][55:0],cube[3][4][63:56]};
b[4][4] <= {cube[1][4][1:0],cube[1][4][63:2]};
step <= 5;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 5)
begin
cube[0][0] <= b[0][0] ^ (~b[1][0] & b[2][0]);
cube[0][1] <= b[0][1] ^ (~b[1][1] & b[2][1]);
cube[0][2] <= b[0][2] ^ (~b[1][2] & b[2][2]);
cube[0][3] <= b[0][3] ^ (~b[1][3] & b[2][3]);
cube[0][4] <= b[0][4] ^ (~b[1][4] & b[2][4]);
cube[1][0] <= b[1][0] ^ (~b[2][0] & b[3][0]);
cube[1][1] <= b[1][1] ^ (~b[2][1] & b[3][1]);
cube[1][2] <= b[1][2] ^ (~b[2][2] & b[3][2]);
cube[1][3] <= b[1][3] ^ (~b[2][3] & b[3][3]);
cube[1][4] <= b[1][4] ^ (~b[2][4] & b[3][4]);
cube[2][0] <= b[2][0] ^ (~b[3][0] & b[4][0]);
cube[2][1] <= b[2][1] ^ (~b[3][1] & b[4][1]);
cube[2][2] <= b[2][2] ^ (~b[3][2] & b[4][2]);
cube[2][3] <= b[2][3] ^ (~b[3][3] & b[4][3]);
cube[2][4] <= b[2][4] ^ (~b[3][4] & b[4][4]);
cube[3][0] <= b[3][0] ^ (~b[4][0] & b[0][0]);
cube[3][1] <= b[3][1] ^ (~b[4][1] & b[0][1]);
cube[3][2] <= b[3][2] ^ (~b[4][2] & b[0][2]);
cube[3][3] <= b[3][3] ^ (~b[4][3] & b[0][3]);
cube[3][4] <= b[3][4] ^ (~b[4][4] & b[0][4]);
cube[4][0] <= b[4][0] ^ (~b[0][0] & b[1][0]);
cube[4][1] <= b[4][1] ^ (~b[0][1] & b[1][1]);
cube[4][2] <= b[4][2] ^ (~b[0][2] & b[1][2]);
cube[4][3] <= b[4][3] ^ (~b[0][3] & b[1][3]);
cube[4][4] <= b[4][4] ^ (~b[0][4] & b[1][4]);
step <= 6;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 6)
begin
if (round == 0)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000000000001;
end
else if(round==1)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000000008082;
end
else if(round==2)
begin
cube[0][0] <= cube[0][0] ^ 64'h800000000000808a;
end
else if(round==3)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000080008000;
end
else if(round==4)
begin
cube[0][0] <= cube[0][0] ^ 64'h000000000000808b;
end
else if(round==5)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000080000001;
end
else if(round==6)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000080008081;
end
else if(round==7)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000008009;
end
else if(round==8)
begin
cube[0][0] <= cube[0][0] ^ 64'h000000000000008a;
end
else if(round==9)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000000000088;
end
else if(round==10)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000080008009;
end
else if(round==11)
begin
cube[0][0] <= cube[0][0] ^ 64'h000000008000000a;
end
else if(round==12)
begin
cube[0][0] <= cube[0][0] ^ 64'h000000008000808b;
end
else if(round==13)
begin
cube[0][0] <= cube[0][0] ^ 64'h800000000000008b;
end
else if(round==14)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000008089;
end
else if(round==15)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000008003;
end
else if(round==16)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000008002;
end
else if(round==17)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000000080;
end
else if(round==18)
begin
cube[0][0] <= cube[0][0] ^ 64'h000000000000800a;
end
else if(round==19)
begin
cube[0][0] <= cube[0][0] ^ 64'h800000008000000a;
end
else if(round==20)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000080008081;
end
else if(round==21)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000000008080;
end
else if(round==22)
begin
cube[0][0] <= cube[0][0] ^ 64'h0000000080000001;
end
else if(round==23)
begin
cube[0][0] <= cube[0][0] ^ 64'h8000000080008008;
end
else
begin
cube[0][0] <= 0;
end
step <= 7;
end
end
end
always @(posedge clk)
begin
if(!rst)
begin
if(step == 7)
begin
if (round < 23)
begin
step <= 1;
round <= round + 1;
end
else
begin
r_o[63:0] <= cube[0][0];
r_o[127:64] <= cube[0][1];
r_o[191:128] <= cube[0][2];
r_o[255:192] <= cube[0][3];
r_o[319:256] <= cube[0][4];
r_o[383:320] <= cube[1][0];
r_o[447:384] <= cube[1][1];
r_o[511:448] <= cube[1][2];
r_o[575:512] <= cube[1][3];
ready <= 1;
end
end
end
end
endmodule |
module x_o(
input clk,
input rst,
input [575:0] data_in,
input [575:0] r_in,
output reg [575:0] x_data_o
);
always @ (posedge clk)
begin
if (rst)
x_data_o <= 0;
else if (!rst)
x_data_o <= (r_in ^ data_in);
end
endmodule |
module e203_clkgate (
input clk_in,
input test_mode,
input clock_en,
output clk_out
);
`ifdef fpga_source assign clk_out = clk_in;
`endif
`ifndef fpga_source
reg enb;
always@(*)
if (!clk_in)
enb = (clock_en | test_mode);
assign clk_out = enb & clk_in;
`endif
endmodule |
module e203_extend_csr(
input nice_csr_valid,
output nice_csr_ready,
input [31:0] nice_csr_addr,
input nice_csr_wr,
input [31:0] nice_csr_wdata,
output [31:0] nice_csr_rdata,
input clk,
input rst_n
);
assign nice_csr_ready = 1'b1;
assign nice_csr_rdata = 32'b0;
endmodule |
module e203_srams(
`ifdef e203_has_itcm input itcm_ram_sd,
input itcm_ram_ds,
input itcm_ram_ls,
input itcm_ram_cs,
input itcm_ram_we,
input [`e203_itcm_ram_aw-1:0] itcm_ram_addr,
input [`e203_itcm_ram_mw-1:0] itcm_ram_wem,
input [`e203_itcm_ram_dw-1:0] itcm_ram_din,
output [`e203_itcm_ram_dw-1:0] itcm_ram_dout,
input clk_itcm_ram,
input rst_itcm,
`endif
`ifdef e203_has_dtcm input dtcm_ram_sd,
input dtcm_ram_ds,
input dtcm_ram_ls,
input dtcm_ram_cs,
input dtcm_ram_we,
input [`e203_dtcm_ram_aw-1:0] dtcm_ram_addr,
input [`e203_dtcm_ram_mw-1:0] dtcm_ram_wem,
input [`e203_dtcm_ram_dw-1:0] dtcm_ram_din,
output [`e203_dtcm_ram_dw-1:0] dtcm_ram_dout,
input clk_dtcm_ram,
input rst_dtcm,
`endif
input test_mode
);
`ifdef e203_has_itcm wire [`e203_itcm_ram_dw-1:0] itcm_ram_dout_pre;
e203_itcm_ram u_e203_itcm_ram (
.sd (itcm_ram_sd),
.ds (itcm_ram_ds),
.ls (itcm_ram_ls),
.cs (itcm_ram_cs ),
.we (itcm_ram_we ),
.addr (itcm_ram_addr ),
.wem (itcm_ram_wem ),
.din (itcm_ram_din ),
.dout (itcm_ram_dout_pre ),
.rst_n(rst_itcm ),
.clk (clk_itcm_ram )
);
assign itcm_ram_dout = itcm_ram_dout_pre;
`endif
`ifdef e203_has_dtcm wire [`e203_dtcm_ram_dw-1:0] dtcm_ram_dout_pre;
e203_dtcm_ram u_e203_dtcm_ram (
.sd (dtcm_ram_sd),
.ds (dtcm_ram_ds),
.ls (dtcm_ram_ls),
.cs (dtcm_ram_cs ),
.we (dtcm_ram_we ),
.addr (dtcm_ram_addr ),
.wem (dtcm_ram_wem ),
.din (dtcm_ram_din ),
.dout (dtcm_ram_dout_pre ),
.rst_n(rst_dtcm ),
.clk (clk_dtcm_ram )
);
assign dtcm_ram_dout = dtcm_ram_dout_pre;
`endif
endmodule |
module sirv_debug_rom(
input [7-1:2] rom_addr,
output [32-1:0] rom_dout
);
wire [31:0] debug_rom [0:28];
assign rom_dout = debug_rom[rom_addr];
assign debug_rom[ 0][7 : 0] = 8'h6f;
assign debug_rom[ 0][15: 8] = 8'h00;
assign debug_rom[ 0][23:16] = 8'hc0;
assign debug_rom[ 0][31:24] = 8'h03;
assign debug_rom[ 1][7 : 0] = 8'h6f;
assign debug_rom[ 1][15: 8] = 8'h00;
assign debug_rom[ 1][23:16] = 8'hc0;
assign debug_rom[ 1][31:24] = 8'h00;
assign debug_rom[ 2][7 : 0] = 8'h13;
assign debug_rom[ 2][15: 8] = 8'h04;
assign debug_rom[ 2][23:16] = 8'hf0;
assign debug_rom[ 2][31:24] = 8'hff;
assign debug_rom[ 3][7 : 0] = 8'h6f;
assign debug_rom[ 3][15: 8] = 8'h00;
assign debug_rom[ 3][23:16] = 8'h80;
assign debug_rom[ 3][31:24] = 8'h00;
assign debug_rom[ 4][7 : 0] = 8'h13;
assign debug_rom[ 4][15: 8] = 8'h04;
assign debug_rom[ 4][23:16] = 8'h00;
assign debug_rom[ 4][31:24] = 8'h00;
assign debug_rom[ 5][7 : 0] = 8'h0f;
assign debug_rom[ 5][15: 8] = 8'h00;
assign debug_rom[ 5][23:16] = 8'hf0;
assign debug_rom[ 5][31:24] = 8'h0f;
assign debug_rom[ 6][7 : 0] = 8'h83;
assign debug_rom[ 6][15: 8] = 8'h24;
assign debug_rom[ 6][23:16] = 8'h80;
assign debug_rom[ 6][31:24] = 8'h41;
assign debug_rom[ 7][7 : 0] = 8'h23;
assign debug_rom[ 7][15: 8] = 8'h2c;
assign debug_rom[ 7][23:16] = 8'h80;
assign debug_rom[ 7][31:24] = 8'h40;
assign debug_rom[ 8][7 : 0] = 8'h73;
assign debug_rom[ 8][15: 8] = 8'h24;
assign debug_rom[ 8][23:16] = 8'h40;
assign debug_rom[ 8][31:24] = 8'hf1;
assign debug_rom[ 9][7 : 0] = 8'h23;
assign debug_rom[ 9][15: 8] = 8'h20;
assign debug_rom[ 9][23:16] = 8'h80;
assign debug_rom[ 9][31:24] = 8'h10;
assign debug_rom[10][7 : 0] = 8'h73;
assign debug_rom[10][15: 8] = 8'h24;
assign debug_rom[10][23:16] = 8'h00;
assign debug_rom[10][31:24] = 8'h7b;
assign debug_rom[11][7 : 0] = 8'h13;
assign debug_rom[11][15: 8] = 8'h74;
assign debug_rom[11][23:16] = 8'h84;
assign debug_rom[11][31:24] = 8'h00;
assign debug_rom[12][7 : 0] = 8'h63;
assign debug_rom[12][15: 8] = 8'h1a;
assign debug_rom[12][23:16] = 8'h04;
assign debug_rom[12][31:24] = 8'h02;
assign debug_rom[13][7 : 0] = 8'h73;
assign debug_rom[13][15: 8] = 8'h24;
assign debug_rom[13][23:16] = 8'h20;
assign debug_rom[13][31:24] = 8'h7b;
assign debug_rom[14][7 : 0] = 8'h73;
assign debug_rom[14][15: 8] = 8'h00;
assign debug_rom[14][23:16] = 8'h20;
assign debug_rom[14][31:24] = 8'h7b;
assign debug_rom[15][7 : 0] = 8'h73;
assign debug_rom[15][15: 8] = 8'h10;
assign debug_rom[15][23:16] = 8'h24;
assign debug_rom[15][31:24] = 8'h7b;
assign debug_rom[16][7 : 0] = 8'h73;
assign debug_rom[16][15: 8] = 8'h24;
assign debug_rom[16][23:16] = 8'h00;
assign debug_rom[16][31:24] = 8'h7b;
assign debug_rom[17][7 : 0] = 8'h13;
assign debug_rom[17][15: 8] = 8'h74;
assign debug_rom[17][23:16] = 8'h04;
assign debug_rom[17][31:24] = 8'h1c;
assign debug_rom[18][7 : 0] = 8'h13;
assign debug_rom[18][15: 8] = 8'h04;
assign debug_rom[18][23:16] = 8'h04;
assign debug_rom[18][31:24] = 8'hf4;
assign debug_rom[19][7 : 0] = 8'h63;
assign debug_rom[19][15: 8] = 8'h16;
assign debug_rom[19][23:16] = 8'h04;
assign debug_rom[19][31:24] = 8'h00;
assign debug_rom[20][7 : 0] = 8'h23;
assign debug_rom[20][15: 8] = 8'h2c;
assign debug_rom[20][23:16] = 8'h90;
assign debug_rom[20][31:24] = 8'h40;
assign debug_rom[21][7 : 0] = 8'h67;
assign debug_rom[21][15: 8] = 8'h00;
assign debug_rom[21][23:16] = 8'h00;
assign debug_rom[21][31:24] = 8'h40;
assign debug_rom[22][7 : 0] = 8'h73;
assign debug_rom[22][15: 8] = 8'h24;
assign debug_rom[22][23:16] = 8'h40;
assign debug_rom[22][31:24] = 8'hf1;
assign debug_rom[23][7 : 0] = 8'h23;
assign debug_rom[23][15: 8] = 8'h26;
assign debug_rom[23][23:16] = 8'h80;
assign debug_rom[23][31:24] = 8'h10;
assign debug_rom[24][7 : 0] = 8'h73;
assign debug_rom[24][15: 8] = 8'h60;
assign debug_rom[24][23:16] = 8'h04;
assign debug_rom[24][31:24] = 8'h7b;
assign debug_rom[25][7 : 0] = 8'h73;
assign debug_rom[25][15: 8] = 8'h24;
assign debug_rom[25][23:16] = 8'h00;
assign debug_rom[25][31:24] = 8'h7b;
assign debug_rom[26][7 : 0] = 8'h13;
assign debug_rom[26][15: 8] = 8'h74;
assign debug_rom[26][23:16] = 8'h04;
assign debug_rom[26][31:24] = 8'h02;
assign debug_rom[27][7 : 0] = 8'he3;
assign debug_rom[27][15: 8] = 8'h0c;
assign debug_rom[27][23:16] = 8'h04;
assign debug_rom[27][31:24] = 8'hfe;
assign debug_rom[28][7 : 0] = 8'h6f;
assign debug_rom[28][15: 8] = 8'hf0;
assign debug_rom[28][23:16] = 8'h1f;
assign debug_rom[28][31:24] = 8'hfe;
endmodule |
module sirv_gnrl_dffrs # (
parameter dw = 32
) (
input [dw-1:0] dnxt,
output [dw-1:0] qout,
input clk,
input rst_n
);
reg [dw-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : dffrs_proc
if (rst_n == 1'b0)
qout_r <= {dw{1'b1}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffr # (
parameter dw = 32
) (
input [dw-1:0] dnxt,
output [dw-1:0] qout,
input clk,
input rst_n
);
reg [dw-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : dffr_proc
if (rst_n == 1'b0)
qout_r <= {dw{1'b0}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_sim_ram
#(parameter dp = 512,
parameter force_x2zero = 0,
parameter dw = 32,
parameter mw = 4,
parameter aw = 32
)
(
input clk,
input [dw-1 :0] din,
input [aw-1 :0] addr,
input cs,
input we,
input [mw-1:0] wem,
output [dw-1:0] dout
);
reg [dw-1:0] mem_r [0:dp-1];
reg [aw-1:0] addr_r;
wire [mw-1:0] wen;
wire ren;
assign ren = cs & (~we);
assign wen = ({mw{cs & we}} & wem);
genvar i;
always @(posedge clk)
begin
if (ren) begin
addr_r <= addr;
end
end
generate
for (i = 0; i < mw; i = i+1) begin :mem
if((8*i+8) > dw ) begin: last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][dw-1:8*i] <= din[dw-1:8*i];
end
end
end
else begin: non_last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
end
end
end
end
endgenerate
wire [dw-1:0] dout_pre;
assign dout_pre = mem_r[addr_r];
generate
if(force_x2zero == 1) begin: force_x_to_zero
for (i = 0; i < dw; i = i+1) begin:force_x_gen
`ifndef synthesis assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
`else assign dout[i] = dout_pre[i];
`endif end
end
else begin:no_force_x_to_zero
assign dout = dout_pre;
end
endgenerate
endmodule |
module sirv_mrom # (
parameter aw = 12,
parameter dw = 32,
parameter dp = 1024
)(
input [aw-1:2] rom_addr,
output [dw-1:0] rom_dout
);
wire [31:0] mask_rom [0:dp-1];
assign rom_dout = mask_rom[rom_addr];
genvar i;
generate
if(1) begin: jump_to_ram_gen
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h7ffff297; end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h00028067; end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000000;
end
end
end
else begin: jump_to_non_ram_gen
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h100006f;
end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==2) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==3) begin: rom1_gen
assign mask_rom[i] = 32'h6661; end
else if(i==4) begin: rom1_gen
assign mask_rom[i] = 32'h20400000 | 32'h000002b7;
end
else if(i==5) begin: rom1_gen
assign mask_rom[i] = 32'h28067;
end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000000;
end
end
end
endgenerate
endmodule |
module sirv_aon_porrst(
output porrst_n
);
`ifdef fpga_source assign porrst_n = 1'b1;
`else assign porrst_n = 1'b1;
`endif
endmodule |
module sirv_asyncresetreg (
input d,
output reg q,
input en,
input clk,
input rst);
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule |
module sirv_clint(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [25:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [25:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [25:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtctick
);
reg [31:0] time_0;
reg [31:0] gen_62;
reg [31:0] time_1;
reg [31:0] gen_63;
wire [63:0] t_904;
wire [64:0] t_906;
wire [63:0] t_907;
wire [31:0] t_909;
wire [63:0] gen_6;
wire [31:0] gen_7;
reg [31:0] timecmp_0_0;
reg [31:0] gen_64;
reg [31:0] timecmp_0_1;
reg [31:0] gen_65;
reg ipi_0;
reg [31:0] gen_66;
wire [63:0] t_915;
wire t_916;
wire t_940_ready;
wire t_940_valid;
wire t_940_bits_read;
wire [13:0] t_940_bits_index;
wire [31:0] t_940_bits_data;
wire [3:0] t_940_bits_mask;
wire [9:0] t_940_bits_extra;
wire t_957;
wire [23:0] t_958;
wire [1:0] t_959;
wire [6:0] t_960;
wire [9:0] t_961;
wire t_979_ready;
wire t_979_valid;
wire t_979_bits_read;
wire [31:0] t_979_bits_data;
wire [9:0] t_979_bits_extra;
wire t_1015_ready;
wire t_1015_valid;
wire t_1015_bits_read;
wire [13:0] t_1015_bits_index;
wire [31:0] t_1015_bits_data;
wire [3:0] t_1015_bits_mask;
wire [9:0] t_1015_bits_extra;
wire t_1058_0;
wire t_1058_1;
wire t_1058_2;
wire t_1058_3;
wire t_1058_4;
wire t_1063_0;
wire t_1063_1;
wire t_1063_2;
wire t_1063_3;
wire t_1063_4;
wire t_1068_0;
wire t_1068_1;
wire t_1068_2;
wire t_1068_3;
wire t_1068_4;
wire t_1073_0;
wire t_1073_1;
wire t_1073_2;
wire t_1073_3;
wire t_1073_4;
wire t_1078_0;
wire t_1078_1;
wire t_1078_2;
wire t_1078_3;
wire t_1078_4;
wire t_1083_0;
wire t_1083_1;
wire t_1083_2;
wire t_1083_3;
wire t_1083_4;
wire t_1088_0;
wire t_1088_1;
wire t_1088_2;
wire t_1088_3;
wire t_1088_4;
wire t_1093_0;
wire t_1093_1;
wire t_1093_2;
wire t_1093_3;
wire t_1093_4;
wire t_1135;
wire t_1136;
wire t_1137;
wire t_1138;
wire [7:0] t_1142;
wire [7:0] t_1146;
wire [7:0] t_1150;
wire [7:0] t_1154;
wire [15:0] t_1155;
wire [15:0] t_1156;
wire [31:0] t_1157;
wire [31:0] t_1185;
wire t_1187;
wire t_1200;
wire [31:0] gen_8;
wire [31:0] t_1219;
wire t_1240;
wire [31:0] gen_9;
wire t_1280;
wire [63:0] gen_10;
wire t_1320;
wire [31:0] gen_11;
wire t_1360;
wire [31:0] gen_12;
wire t_1421_0;
wire t_1421_1;
wire t_1421_2;
wire t_1421_3;
wire t_1421_4;
wire t_1421_5;
wire t_1421_6;
wire t_1421_7;
wire t_1472_0;
wire t_1472_1;
wire t_1472_2;
wire t_1472_3;
wire t_1472_4;
wire t_1472_5;
wire t_1472_6;
wire t_1472_7;
wire t_1523_0;
wire t_1523_1;
wire t_1523_2;
wire t_1523_3;
wire t_1523_4;
wire t_1523_5;
wire t_1523_6;
wire t_1523_7;
wire t_1574_0;
wire t_1574_1;
wire t_1574_2;
wire t_1574_3;
wire t_1574_4;
wire t_1574_5;
wire t_1574_6;
wire t_1574_7;
wire t_1585;
wire t_1586;
wire t_1597;
wire [1:0] t_1599;
wire [2:0] t_1600;
wire gen_0;
wire gen_13;
wire gen_14;
wire gen_15;
wire gen_16;
wire gen_17;
wire gen_18;
wire gen_19;
wire gen_1;
wire gen_20;
wire gen_21;
wire gen_22;
wire gen_23;
wire gen_24;
wire gen_25;
wire gen_26;
wire t_1619;
wire gen_2;
wire gen_27;
wire gen_28;
wire gen_29;
wire gen_30;
wire gen_31;
wire gen_32;
wire gen_33;
wire gen_3;
wire gen_34;
wire gen_35;
wire gen_36;
wire gen_37;
wire gen_38;
wire gen_39;
wire gen_40;
wire t_1622;
wire t_1623;
wire t_1624;
wire t_1625;
wire t_1626;
wire [7:0] t_1628;
wire t_1647;
wire t_1648;
wire t_1649;
wire t_1650;
wire t_1653;
wire t_1654;
wire t_1656;
wire t_1657;
wire t_1658;
wire t_1660;
wire t_1664;
wire t_1666;
wire t_1689;
wire t_1690;
wire t_1696;
wire t_1700;
wire t_1706;
wire t_1709;
wire t_1710;
wire t_1716;
wire t_1720;
wire t_1726;
wire t_1729;
wire t_1730;
wire t_1736;
wire t_1740;
wire t_1746;
wire t_1749;
wire t_1750;
wire t_1756;
wire t_1760;
wire t_1766;
wire t_1838_0;
wire t_1838_1;
wire t_1838_2;
wire t_1838_3;
wire t_1838_4;
wire t_1838_5;
wire t_1838_6;
wire t_1838_7;
wire [31:0] t_1861_0;
wire [31:0] t_1861_1;
wire [31:0] t_1861_2;
wire [31:0] t_1861_3;
wire [31:0] t_1861_4;
wire [31:0] t_1861_5;
wire [31:0] t_1861_6;
wire [31:0] t_1861_7;
wire gen_4;
wire gen_41;
wire gen_42;
wire gen_43;
wire gen_44;
wire gen_45;
wire gen_46;
wire gen_47;
wire [31:0] gen_5;
wire [31:0] gen_48;
wire [31:0] gen_49;
wire [31:0] gen_50;
wire [31:0] gen_51;
wire [31:0] gen_52;
wire [31:0] gen_53;
wire [31:0] gen_54;
wire [31:0] t_1874;
wire [1:0] t_1875;
wire [4:0] t_1877;
wire [2:0] t_1878;
wire [2:0] t_1889_opcode;
wire [1:0] t_1889_param;
wire [2:0] t_1889_size;
wire [4:0] t_1889_source;
wire t_1889_sink;
wire [1:0] t_1889_addr_lo;
wire [31:0] t_1889_data;
wire t_1889_error;
wire [2:0] gen_55 = 3'b0;
reg [31:0] gen_67;
wire [1:0] gen_56 = 2'b0;
reg [31:0] gen_68;
wire [2:0] gen_57 = 3'b0;
reg [31:0] gen_69;
wire [4:0] gen_58 = 5'b0;
reg [31:0] gen_70;
wire [25:0] gen_59 = 26'b0;
reg [31:0] gen_71;
wire [3:0] gen_60 = 4'b0;
reg [31:0] gen_72;
wire [31:0] gen_61 = 32'b0;
reg [31:0] gen_73;
assign io_in_0_a_ready = t_940_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = gen_55;
assign io_in_0_b_bits_param = gen_56;
assign io_in_0_b_bits_size = gen_57;
assign io_in_0_b_bits_source = gen_58;
assign io_in_0_b_bits_address = gen_59;
assign io_in_0_b_bits_mask = gen_60;
assign io_in_0_b_bits_data = gen_61;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = t_979_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, t_979_bits_read};
assign io_in_0_d_bits_param = t_1889_param;
assign io_in_0_d_bits_size = t_1889_size;
assign io_in_0_d_bits_source = t_1889_source;
assign io_in_0_d_bits_sink = t_1889_sink;
assign io_in_0_d_bits_addr_lo = t_1889_addr_lo;
assign io_in_0_d_bits_data = t_979_bits_data;
assign io_in_0_d_bits_error = t_1889_error;
assign io_in_0_e_ready = 1'h1;
assign io_tiles_0_mtip = t_916;
assign io_tiles_0_msip = ipi_0;
assign t_904 = {time_1,time_0};
assign t_906 = t_904 + 64'h1;
assign t_907 = t_906[63:0];
assign t_909 = t_907[63:32];
assign gen_6 = io_rtctick ? t_907 : {{32'd0}, time_0};
assign gen_7 = io_rtctick ? t_909 : time_1;
assign t_915 = {timecmp_0_1,timecmp_0_0};
assign t_916 = t_904 >= t_915;
assign t_940_ready = t_1623;
assign t_940_valid = io_in_0_a_valid;
assign t_940_bits_read = t_957;
assign t_940_bits_index = t_958[13:0];
assign t_940_bits_data = io_in_0_a_bits_data;
assign t_940_bits_mask = io_in_0_a_bits_mask;
assign t_940_bits_extra = t_961;
assign t_957 = io_in_0_a_bits_opcode == 3'h4;
assign t_958 = io_in_0_a_bits_address[25:2];
assign t_959 = io_in_0_a_bits_address[1:0];
assign t_960 = {t_959,io_in_0_a_bits_source};
assign t_961 = {t_960,io_in_0_a_bits_size};
assign t_979_ready = io_in_0_d_ready;
assign t_979_valid = t_1626;
assign t_979_bits_read = t_1015_bits_read;
assign t_979_bits_data = t_1874;
assign t_979_bits_extra = t_1015_bits_extra;
assign t_1015_ready = t_1625;
assign t_1015_valid = t_1624;
assign t_1015_bits_read = t_940_bits_read;
assign t_1015_bits_index = t_940_bits_index;
assign t_1015_bits_data = t_940_bits_data;
assign t_1015_bits_mask = t_940_bits_mask;
assign t_1015_bits_extra = t_940_bits_extra;
assign t_1058_0 = t_1650;
assign t_1058_1 = t_1750;
assign t_1058_2 = t_1690;
assign t_1058_3 = t_1710;
assign t_1058_4 = t_1730;
assign t_1063_0 = t_1656;
assign t_1063_1 = t_1756;
assign t_1063_2 = t_1696;
assign t_1063_3 = t_1716;
assign t_1063_4 = t_1736;
assign t_1068_0 = 1'h1;
assign t_1068_1 = 1'h1;
assign t_1068_2 = 1'h1;
assign t_1068_3 = 1'h1;
assign t_1068_4 = 1'h1;
assign t_1073_0 = 1'h1;
assign t_1073_1 = 1'h1;
assign t_1073_2 = 1'h1;
assign t_1073_3 = 1'h1;
assign t_1073_4 = 1'h1;
assign t_1078_0 = 1'h1;
assign t_1078_1 = 1'h1;
assign t_1078_2 = 1'h1;
assign t_1078_3 = 1'h1;
assign t_1078_4 = 1'h1;
assign t_1083_0 = 1'h1;
assign t_1083_1 = 1'h1;
assign t_1083_2 = 1'h1;
assign t_1083_3 = 1'h1;
assign t_1083_4 = 1'h1;
assign t_1088_0 = t_1660;
assign t_1088_1 = t_1760;
assign t_1088_2 = t_1700;
assign t_1088_3 = t_1720;
assign t_1088_4 = t_1740;
assign t_1093_0 = t_1666;
assign t_1093_1 = t_1766;
assign t_1093_2 = t_1706;
assign t_1093_3 = t_1726;
assign t_1093_4 = t_1746;
assign t_1135 = t_1015_bits_mask[0];
assign t_1136 = t_1015_bits_mask[1];
assign t_1137 = t_1015_bits_mask[2];
assign t_1138 = t_1015_bits_mask[3];
assign t_1142 = t_1135 ? 8'hff : 8'h0;
assign t_1146 = t_1136 ? 8'hff : 8'h0;
assign t_1150 = t_1137 ? 8'hff : 8'h0;
assign t_1154 = t_1138 ? 8'hff : 8'h0;
assign t_1155 = {t_1146,t_1142};
assign t_1156 = {t_1154,t_1150};
assign t_1157 = {t_1156,t_1155};
assign t_1185 = ~ t_1157;
assign t_1187 = t_1185 == 32'h0;
assign t_1200 = t_1093_0 & t_1187;
assign gen_8 = t_1200 ? t_1015_bits_data : {{31'd0}, ipi_0};
assign t_1219 = {{31'd0}, ipi_0};
assign t_1240 = t_1093_1 & t_1187;
assign gen_9 = t_1240 ? t_1015_bits_data : timecmp_0_1;
assign t_1280 = t_1093_2 & t_1187;
assign gen_10 = t_1280 ? {{32'd0}, t_1015_bits_data} : gen_6;
assign t_1320 = t_1093_3 & t_1187;
assign gen_11 = t_1320 ? t_1015_bits_data : gen_7;
assign t_1360 = t_1093_4 & t_1187;
assign gen_12 = t_1360 ? t_1015_bits_data : timecmp_0_0;
assign t_1421_0 = t_1068_0;
assign t_1421_1 = 1'h1;
assign t_1421_2 = t_1068_2;
assign t_1421_3 = t_1068_3;
assign t_1421_4 = t_1068_4;
assign t_1421_5 = t_1068_1;
assign t_1421_6 = 1'h1;
assign t_1421_7 = 1'h1;
assign t_1472_0 = t_1073_0;
assign t_1472_1 = 1'h1;
assign t_1472_2 = t_1073_2;
assign t_1472_3 = t_1073_3;
assign t_1472_4 = t_1073_4;
assign t_1472_5 = t_1073_1;
assign t_1472_6 = 1'h1;
assign t_1472_7 = 1'h1;
assign t_1523_0 = t_1078_0;
assign t_1523_1 = 1'h1;
assign t_1523_2 = t_1078_2;
assign t_1523_3 = t_1078_3;
assign t_1523_4 = t_1078_4;
assign t_1523_5 = t_1078_1;
assign t_1523_6 = 1'h1;
assign t_1523_7 = 1'h1;
assign t_1574_0 = t_1083_0;
assign t_1574_1 = 1'h1;
assign t_1574_2 = t_1083_2;
assign t_1574_3 = t_1083_3;
assign t_1574_4 = t_1083_4;
assign t_1574_5 = t_1083_1;
assign t_1574_6 = 1'h1;
assign t_1574_7 = 1'h1;
assign t_1585 = t_1015_bits_index[0];
assign t_1586 = t_1015_bits_index[1];
assign t_1597 = t_1015_bits_index[12];
assign t_1599 = {t_1597,t_1586};
assign t_1600 = {t_1599,t_1585};
assign gen_0 = gen_19;
assign gen_13 = 3'h1 == t_1600 ? t_1421_1 : t_1421_0;
assign gen_14 = 3'h2 == t_1600 ? t_1421_2 : gen_13;
assign gen_15 = 3'h3 == t_1600 ? t_1421_3 : gen_14;
assign gen_16 = 3'h4 == t_1600 ? t_1421_4 : gen_15;
assign gen_17 = 3'h5 == t_1600 ? t_1421_5 : gen_16;
assign gen_18 = 3'h6 == t_1600 ? t_1421_6 : gen_17;
assign gen_19 = 3'h7 == t_1600 ? t_1421_7 : gen_18;
assign gen_1 = gen_26;
assign gen_20 = 3'h1 == t_1600 ? t_1472_1 : t_1472_0;
assign gen_21 = 3'h2 == t_1600 ? t_1472_2 : gen_20;
assign gen_22 = 3'h3 == t_1600 ? t_1472_3 : gen_21;
assign gen_23 = 3'h4 == t_1600 ? t_1472_4 : gen_22;
assign gen_24 = 3'h5 == t_1600 ? t_1472_5 : gen_23;
assign gen_25 = 3'h6 == t_1600 ? t_1472_6 : gen_24;
assign gen_26 = 3'h7 == t_1600 ? t_1472_7 : gen_25;
assign t_1619 = t_1015_bits_read ? gen_0 : gen_1;
assign gen_2 = gen_33;
assign gen_27 = 3'h1 == t_1600 ? t_1523_1 : t_1523_0;
assign gen_28 = 3'h2 == t_1600 ? t_1523_2 : gen_27;
assign gen_29 = 3'h3 == t_1600 ? t_1523_3 : gen_28;
assign gen_30 = 3'h4 == t_1600 ? t_1523_4 : gen_29;
assign gen_31 = 3'h5 == t_1600 ? t_1523_5 : gen_30;
assign gen_32 = 3'h6 == t_1600 ? t_1523_6 : gen_31;
assign gen_33 = 3'h7 == t_1600 ? t_1523_7 : gen_32;
assign gen_3 = gen_40;
assign gen_34 = 3'h1 == t_1600 ? t_1574_1 : t_1574_0;
assign gen_35 = 3'h2 == t_1600 ? t_1574_2 : gen_34;
assign gen_36 = 3'h3 == t_1600 ? t_1574_3 : gen_35;
assign gen_37 = 3'h4 == t_1600 ? t_1574_4 : gen_36;
assign gen_38 = 3'h5 == t_1600 ? t_1574_5 : gen_37;
assign gen_39 = 3'h6 == t_1600 ? t_1574_6 : gen_38;
assign gen_40 = 3'h7 == t_1600 ? t_1574_7 : gen_39;
assign t_1622 = t_1015_bits_read ? gen_2 : gen_3;
assign t_1623 = t_1015_ready & t_1619;
assign t_1624 = t_940_valid & t_1619;
assign t_1625 = t_979_ready & t_1622;
assign t_1626 = t_1015_valid & t_1622;
assign t_1628 = 8'h1 << t_1600;
assign t_1647 = t_940_valid & t_1015_ready;
assign t_1648 = t_1647 & t_1015_bits_read;
assign t_1649 = t_1628[0];
assign t_1650 = t_1648 & t_1649;
assign t_1653 = t_1015_bits_read == 1'h0;
assign t_1654 = t_1647 & t_1653;
assign t_1656 = t_1654 & t_1649;
assign t_1657 = t_1015_valid & t_979_ready;
assign t_1658 = t_1657 & t_1015_bits_read;
assign t_1660 = t_1658 & t_1649;
assign t_1664 = t_1657 & t_1653;
assign t_1666 = t_1664 & t_1649;
assign t_1689 = t_1628[2];
assign t_1690 = t_1648 & t_1689;
assign t_1696 = t_1654 & t_1689;
assign t_1700 = t_1658 & t_1689;
assign t_1706 = t_1664 & t_1689;
assign t_1709 = t_1628[3];
assign t_1710 = t_1648 & t_1709;
assign t_1716 = t_1654 & t_1709;
assign t_1720 = t_1658 & t_1709;
assign t_1726 = t_1664 & t_1709;
assign t_1729 = t_1628[4];
assign t_1730 = t_1648 & t_1729;
assign t_1736 = t_1654 & t_1729;
assign t_1740 = t_1658 & t_1729;
assign t_1746 = t_1664 & t_1729;
assign t_1749 = t_1628[5];
assign t_1750 = t_1648 & t_1749;
assign t_1756 = t_1654 & t_1749;
assign t_1760 = t_1658 & t_1749;
assign t_1766 = t_1664 & t_1749;
assign t_1838_0 = 1'h1;
assign t_1838_1 = 1'h1;
assign t_1838_2 = 1'h1;
assign t_1838_3 = 1'h1;
assign t_1838_4 = 1'h1;
assign t_1838_5 = 1'h1;
assign t_1838_6 = 1'h1;
assign t_1838_7 = 1'h1;
assign t_1861_0 = t_1219;
assign t_1861_1 = 32'h0;
assign t_1861_2 = time_0;
assign t_1861_3 = time_1;
assign t_1861_4 = timecmp_0_0;
assign t_1861_5 = timecmp_0_1;
assign t_1861_6 = 32'h0;
assign t_1861_7 = 32'h0;
assign gen_4 = gen_47;
assign gen_41 = 3'h1 == t_1600 ? t_1838_1 : t_1838_0;
assign gen_42 = 3'h2 == t_1600 ? t_1838_2 : gen_41;
assign gen_43 = 3'h3 == t_1600 ? t_1838_3 : gen_42;
assign gen_44 = 3'h4 == t_1600 ? t_1838_4 : gen_43;
assign gen_45 = 3'h5 == t_1600 ? t_1838_5 : gen_44;
assign gen_46 = 3'h6 == t_1600 ? t_1838_6 : gen_45;
assign gen_47 = 3'h7 == t_1600 ? t_1838_7 : gen_46;
assign gen_5 = gen_54;
assign gen_48 = 3'h1 == t_1600 ? t_1861_1 : t_1861_0;
assign gen_49 = 3'h2 == t_1600 ? t_1861_2 : gen_48;
assign gen_50 = 3'h3 == t_1600 ? t_1861_3 : gen_49;
assign gen_51 = 3'h4 == t_1600 ? t_1861_4 : gen_50;
assign gen_52 = 3'h5 == t_1600 ? t_1861_5 : gen_51;
assign gen_53 = 3'h6 == t_1600 ? t_1861_6 : gen_52;
assign gen_54 = 3'h7 == t_1600 ? t_1861_7 : gen_53;
assign t_1874 = gen_4 ? gen_5 : 32'h0;
assign t_1875 = t_979_bits_extra[9:8];
assign t_1877 = t_979_bits_extra[7:3];
assign t_1878 = t_979_bits_extra[2:0];
assign t_1889_opcode = 3'h0;
assign t_1889_param = 2'h0;
assign t_1889_size = t_1878;
assign t_1889_source = t_1877;
assign t_1889_sink = 1'h0;
assign t_1889_addr_lo = t_1875;
assign t_1889_data = 32'h0;
assign t_1889_error = 1'h0;
always @(posedge clock or posedge reset) begin
if (reset) begin
time_0 <= 32'h0;
end else begin
time_0 <= gen_10[31:0];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
time_1 <= 32'h0;
end else begin
if (t_1320) begin
time_1 <= t_1015_bits_data;
end else begin
if (io_rtctick) begin
time_1 <= t_909;
end
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_0 <= 32'hffff_ffff;
end
else if (t_1360) begin
timecmp_0_0 <= t_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_1 <= 32'hffff_ffff;
end
else if (t_1240) begin
timecmp_0_1 <= t_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ipi_0 <= 1'h0;
end else begin
ipi_0 <= gen_8[0];
end
end
endmodule |
module sirv_deglitchshiftregister(
input clock,
input reset,
input io_d,
output io_q
);
reg t_8;
reg [31:0] gen_0;
reg t_9;
reg [31:0] gen_1;
reg sync;
reg [31:0] gen_2;
reg last;
reg [31:0] gen_3;
wire t_12;
assign io_q = t_12;
assign t_12 = sync & last;
always @(posedge clock) begin t_8 <= io_d;
t_9 <= t_8;
sync <= t_9;
last <= sync;
end
endmodule |
module sirv_expl_axi_slv #(
parameter aw = 32,
parameter dw = 32
)(
input axi_arvalid,
output axi_arready,
input [aw-1:0] axi_araddr,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input [1:0] axi_arlock,
input [1:0] axi_arburst,
input [3:0] axi_arlen,
input [2:0] axi_arsize,
input axi_awvalid,
output axi_awready,
input [aw-1:0] axi_awaddr,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input [1:0] axi_awlock,
input [1:0] axi_awburst,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
output axi_rvalid,
input axi_rready,
output [dw-1:0] axi_rdata,
output [1:0] axi_rresp,
output axi_rlast,
input axi_wvalid,
output axi_wready,
input [dw-1:0] axi_wdata,
input [(dw/8)-1:0] axi_wstrb,
input axi_wlast,
output axi_bvalid,
input axi_bready,
output [1:0] axi_bresp,
input clk,
input rst_n
);
assign axi_rvalid = axi_arvalid;
assign axi_arready = axi_rready;
assign axi_rdata = {dw{1'b0}};
assign axi_rresp = 2'b0;
assign axi_rlast = 1'b1;
assign axi_bvalid = axi_wvalid;
assign axi_wready = axi_bready;
assign axi_bresp = 2'b0;
assign axi_awready = 1'b1;
endmodule |
module sirv_jtaggpioport(
input clock,
input reset,
output io_jtag_tck,
output io_jtag_tms,
output io_jtag_tdi,
input io_jtag_tdo,
output io_jtag_trst,
input io_jtag_drv_tdo,
input io_pins_tck_i_ival,
output io_pins_tck_o_oval,
output io_pins_tck_o_oe,
output io_pins_tck_o_ie,
output io_pins_tck_o_pue,
output io_pins_tck_o_ds,
input io_pins_tms_i_ival,
output io_pins_tms_o_oval,
output io_pins_tms_o_oe,
output io_pins_tms_o_ie,
output io_pins_tms_o_pue,
output io_pins_tms_o_ds,
input io_pins_tdi_i_ival,
output io_pins_tdi_o_oval,
output io_pins_tdi_o_oe,
output io_pins_tdi_o_ie,
output io_pins_tdi_o_pue,
output io_pins_tdi_o_ds,
input io_pins_tdo_i_ival,
output io_pins_tdo_o_oval,
output io_pins_tdo_o_oe,
output io_pins_tdo_o_ie,
output io_pins_tdo_o_pue,
output io_pins_tdo_o_ds,
input io_pins_trst_n_i_ival,
output io_pins_trst_n_o_oval,
output io_pins_trst_n_o_oe,
output io_pins_trst_n_o_ie,
output io_pins_trst_n_o_pue,
output io_pins_trst_n_o_ds
);
wire t_101;
wire t_117;
assign io_jtag_tck = t_101;
assign io_jtag_tms = io_pins_tms_i_ival;
assign io_jtag_tdi = io_pins_tdi_i_ival;
assign io_jtag_trst = t_117;
assign io_pins_tck_o_oval = 1'h0;
assign io_pins_tck_o_oe = 1'h0;
assign io_pins_tck_o_ie = 1'h1;
assign io_pins_tck_o_pue = 1'h1;
assign io_pins_tck_o_ds = 1'h0;
assign io_pins_tms_o_oval = 1'h0;
assign io_pins_tms_o_oe = 1'h0;
assign io_pins_tms_o_ie = 1'h1;
assign io_pins_tms_o_pue = 1'h1;
assign io_pins_tms_o_ds = 1'h0;
assign io_pins_tdi_o_oval = 1'h0;
assign io_pins_tdi_o_oe = 1'h0;
assign io_pins_tdi_o_ie = 1'h1;
assign io_pins_tdi_o_pue = 1'h1;
assign io_pins_tdi_o_ds = 1'h0;
assign io_pins_tdo_o_oval = io_jtag_tdo;
assign io_pins_tdo_o_oe = io_jtag_drv_tdo;
assign io_pins_tdo_o_ie = 1'h0;
assign io_pins_tdo_o_pue = 1'h0;
assign io_pins_tdo_o_ds = 1'h0;
assign io_pins_trst_n_o_oval = 1'h0;
assign io_pins_trst_n_o_oe = 1'h0;
assign io_pins_trst_n_o_ie = 1'h1;
assign io_pins_trst_n_o_pue = 1'h1;
assign io_pins_trst_n_o_ds = 1'h0;
assign t_101 = $unsigned(io_pins_tck_i_ival);
assign t_117 = ~ io_pins_trst_n_i_ival;
endmodule |
module sirv_levelgateway(
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inflight;
reg [31:0] gen_2;
wire t_12;
wire gen_0;
wire gen_1;
wire t_16;
wire t_17;
assign io_plic_valid = t_17;
assign t_12 = io_interrupt & io_plic_ready;
assign gen_0 = t_12 ? 1'h1 : inflight;
assign gen_1 = io_plic_complete ? 1'h0 : gen_0;
assign t_16 = inflight == 1'h0;
assign t_17 = io_interrupt & t_16;
always @(posedge clock or posedge reset) begin
if (reset) begin
inflight <= 1'h0;
end else begin
if (io_plic_complete) begin
inflight <= 1'h0;
end else begin
if (t_12) begin
inflight <= 1'h1;
end
end
end
end
endmodule |
module sirv_pmu_core(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_valid,
output io_control_bits_hfclkrst,
output io_control_bits_corerst,
output io_control_bits_reserved1,
output io_control_bits_vddpaden,
output io_control_bits_reserved0,
input [1:0] io_resetcause,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupprogram_0_write_valid,
input [31:0] io_regs_wakeupprogram_0_write_bits,
output [31:0] io_regs_wakeupprogram_0_read,
input io_regs_wakeupprogram_1_write_valid,
input [31:0] io_regs_wakeupprogram_1_write_bits,
output [31:0] io_regs_wakeupprogram_1_read,
input io_regs_wakeupprogram_2_write_valid,
input [31:0] io_regs_wakeupprogram_2_write_bits,
output [31:0] io_regs_wakeupprogram_2_read,
input io_regs_wakeupprogram_3_write_valid,
input [31:0] io_regs_wakeupprogram_3_write_bits,
output [31:0] io_regs_wakeupprogram_3_read,
input io_regs_wakeupprogram_4_write_valid,
input [31:0] io_regs_wakeupprogram_4_write_bits,
output [31:0] io_regs_wakeupprogram_4_read,
input io_regs_wakeupprogram_5_write_valid,
input [31:0] io_regs_wakeupprogram_5_write_bits,
output [31:0] io_regs_wakeupprogram_5_read,
input io_regs_wakeupprogram_6_write_valid,
input [31:0] io_regs_wakeupprogram_6_write_bits,
output [31:0] io_regs_wakeupprogram_6_read,
input io_regs_wakeupprogram_7_write_valid,
input [31:0] io_regs_wakeupprogram_7_write_bits,
output [31:0] io_regs_wakeupprogram_7_read,
input io_regs_sleepprogram_0_write_valid,
input [31:0] io_regs_sleepprogram_0_write_bits,
output [31:0] io_regs_sleepprogram_0_read,
input io_regs_sleepprogram_1_write_valid,
input [31:0] io_regs_sleepprogram_1_write_bits,
output [31:0] io_regs_sleepprogram_1_read,
input io_regs_sleepprogram_2_write_valid,
input [31:0] io_regs_sleepprogram_2_write_bits,
output [31:0] io_regs_sleepprogram_2_read,
input io_regs_sleepprogram_3_write_valid,
input [31:0] io_regs_sleepprogram_3_write_bits,
output [31:0] io_regs_sleepprogram_3_read,
input io_regs_sleepprogram_4_write_valid,
input [31:0] io_regs_sleepprogram_4_write_bits,
output [31:0] io_regs_sleepprogram_4_read,
input io_regs_sleepprogram_5_write_valid,
input [31:0] io_regs_sleepprogram_5_write_bits,
output [31:0] io_regs_sleepprogram_5_read,
input io_regs_sleepprogram_6_write_valid,
input [31:0] io_regs_sleepprogram_6_write_bits,
output [31:0] io_regs_sleepprogram_6_read,
input io_regs_sleepprogram_7_write_valid,
input [31:0] io_regs_sleepprogram_7_write_bits,
output [31:0] io_regs_sleepprogram_7_read
);
reg wantsleep;
reg run;
reg [31:0] gen_37;
reg awake;
reg [31:0] gen_38;
wire t_364;
wire t_365;
wire t_366;
wire t_367;
wire t_368;
wire t_369;
wire t_370;
wire t_371;
wire t_372;
wire t_373;
wire t_374;
wire t_375;
wire t_376;
wire t_377;
wire t_378;
wire t_379;
wire t_380;
wire t_381;
wire t_383;
wire t_385;
wire t_386;
wire t_388;
reg unlocked;
reg [31:0] gen_39;
wire gen_0;
wire t_391;
reg [31:0] gen_40;
wire gen_1;
reg [2:0] pc;
reg [31:0] gen_41;
reg [1:0] wakeupcause;
reg [31:0] gen_42;
wire t_394;
reg [3:0] t_396;
reg [31:0] gen_43;
wire [3:0] gen_2;
wire [3:0] ie;
reg [8:0] wakeupprogram_0;
reg [31:0] gen_44;
reg [8:0] wakeupprogram_1;
reg [31:0] gen_45;
reg [8:0] wakeupprogram_2;
reg [31:0] gen_46;
reg [8:0] wakeupprogram_3;
reg [31:0] gen_47;
reg [8:0] wakeupprogram_4;
reg [31:0] gen_48;
reg [8:0] wakeupprogram_5;
reg [31:0] gen_49;
reg [8:0] wakeupprogram_6;
reg [31:0] gen_50;
reg [8:0] wakeupprogram_7;
reg [31:0] gen_51;
reg [8:0] sleepprogram_0;
reg [31:0] gen_52;
reg [8:0] sleepprogram_1;
reg [31:0] gen_53;
reg [8:0] sleepprogram_2;
reg [31:0] gen_54;
reg [8:0] sleepprogram_3;
reg [31:0] gen_55;
reg [8:0] sleepprogram_4;
reg [31:0] gen_56;
reg [8:0] sleepprogram_5;
reg [31:0] gen_57;
reg [8:0] sleepprogram_6;
reg [31:0] gen_58;
reg [8:0] sleepprogram_7;
reg [31:0] gen_59;
wire [2:0] t_423;
wire t_425;
wire [2:0] t_427;
wire t_429;
wire t_433;
wire [8:0] t_434;
wire [8:0] t_439;
wire [8:0] t_440;
wire [8:0] t_449;
wire [8:0] t_454;
wire [8:0] t_455;
wire [8:0] t_456;
wire [8:0] t_469;
wire [8:0] t_474;
wire [8:0] t_475;
wire [8:0] t_484;
wire [8:0] t_489;
wire [8:0] t_490;
wire [8:0] t_491;
wire [8:0] insnbits;
wire insn_sigs_hfclkrst;
wire insn_sigs_corerst;
wire insn_sigs_reserved1;
wire insn_sigs_vddpaden;
wire insn_sigs_reserved0;
wire [3:0] insn_dt;
wire [3:0] t_515;
wire t_516;
wire t_517;
wire t_518;
wire t_519;
wire t_520;
reg [15:0] count;
reg [31:0] gen_60;
wire [16:0] t_523;
wire [15:0] t_524;
wire [15:0] t_525;
wire [15:0] t_526;
wire tick;
wire [3:0] npc;
wire last;
wire t_530;
wire t_531;
wire t_532;
wire [15:0] gen_3;
wire gen_4;
wire [3:0] gen_5;
wire [15:0] gen_6;
wire gen_7;
wire [3:0] gen_8;
wire t_540;
wire [1:0] t_541;
wire [1:0] t_542;
wire [3:0] t_543;
wire [3:0] t_544;
wire t_546;
wire t_548;
wire t_549;
wire t_552;
wire t_553;
wire t_554;
wire [1:0] t_560;
wire [1:0] t_561;
wire [1:0] t_562;
wire gen_9;
wire gen_10;
wire [1:0] gen_11;
wire t_563;
wire gen_12;
wire gen_13;
wire gen_14;
wire gen_15;
wire gen_16;
wire [1:0] gen_17;
wire gen_18;
wire [9:0] gen_35;
wire [9:0] t_567;
wire [9:0] gen_36;
wire [9:0] t_568;
wire t_570;
wire [31:0] gen_19;
wire t_571;
wire [31:0] gen_20;
wire t_572;
wire [31:0] gen_21;
wire t_573;
wire [31:0] gen_22;
wire t_574;
wire [31:0] gen_23;
wire t_575;
wire [31:0] gen_24;
wire t_576;
wire [31:0] gen_25;
wire t_577;
wire [31:0] gen_26;
wire t_578;
wire [31:0] gen_27;
wire t_579;
wire [31:0] gen_28;
wire t_580;
wire [31:0] gen_29;
wire t_581;
wire [31:0] gen_30;
wire t_582;
wire [31:0] gen_31;
wire t_583;
wire [31:0] gen_32;
wire t_584;
wire [31:0] gen_33;
wire t_585;
wire [31:0] gen_34;
assign io_control_valid = t_532;
assign io_control_bits_hfclkrst = insn_sigs_hfclkrst;
assign io_control_bits_corerst = insn_sigs_corerst;
assign io_control_bits_reserved1 = insn_sigs_reserved1;
assign io_control_bits_vddpaden = insn_sigs_vddpaden;
assign io_control_bits_reserved0 = insn_sigs_reserved0;
assign io_regs_ie_read = ie;
assign io_regs_cause_read = {{22'd0}, t_568};
assign io_regs_sleep_read = {31'h0,wantsleep};
assign io_regs_key_read = {{31'd0}, unlocked};
assign io_regs_wakeupprogram_0_read = {{23'd0}, wakeupprogram_0};
assign io_regs_wakeupprogram_1_read = {{23'd0}, wakeupprogram_1};
assign io_regs_wakeupprogram_2_read = {{23'd0}, wakeupprogram_2};
assign io_regs_wakeupprogram_3_read = {{23'd0}, wakeupprogram_3};
assign io_regs_wakeupprogram_4_read = {{23'd0}, wakeupprogram_4};
assign io_regs_wakeupprogram_5_read = {{23'd0}, wakeupprogram_5};
assign io_regs_wakeupprogram_6_read = {{23'd0}, wakeupprogram_6};
assign io_regs_wakeupprogram_7_read = {{23'd0}, wakeupprogram_7};
assign io_regs_sleepprogram_0_read = {{23'd0}, sleepprogram_0};
assign io_regs_sleepprogram_1_read = {{23'd0}, sleepprogram_1};
assign io_regs_sleepprogram_2_read = {{23'd0}, sleepprogram_2};
assign io_regs_sleepprogram_3_read = {{23'd0}, sleepprogram_3};
assign io_regs_sleepprogram_4_read = {{23'd0}, sleepprogram_4};
assign io_regs_sleepprogram_5_read = {{23'd0}, sleepprogram_5};
assign io_regs_sleepprogram_6_read = {{23'd0}, sleepprogram_6};
assign io_regs_sleepprogram_7_read = {{23'd0}, sleepprogram_7};
assign t_364 = io_regs_sleepprogram_0_write_valid | io_regs_sleepprogram_1_write_valid;
assign t_365 = t_364 | io_regs_sleepprogram_2_write_valid;
assign t_366 = t_365 | io_regs_sleepprogram_3_write_valid;
assign t_367 = t_366 | io_regs_sleepprogram_4_write_valid;
assign t_368 = t_367 | io_regs_sleepprogram_5_write_valid;
assign t_369 = t_368 | io_regs_sleepprogram_6_write_valid;
assign t_370 = t_369 | io_regs_sleepprogram_7_write_valid;
assign t_371 = io_regs_wakeupprogram_0_write_valid | io_regs_wakeupprogram_1_write_valid;
assign t_372 = t_371 | io_regs_wakeupprogram_2_write_valid;
assign t_373 = t_372 | io_regs_wakeupprogram_3_write_valid;
assign t_374 = t_373 | io_regs_wakeupprogram_4_write_valid;
assign t_375 = t_374 | io_regs_wakeupprogram_5_write_valid;
assign t_376 = t_375 | io_regs_wakeupprogram_6_write_valid;
assign t_377 = t_376 | io_regs_wakeupprogram_7_write_valid;
assign t_378 = t_370 | t_377;
assign t_379 = t_378 | io_regs_sleep_write_valid;
assign t_380 = t_379 | io_regs_cause_write_valid;
assign t_381 = t_380 | io_regs_ie_write_valid;
assign t_383 = io_regs_key_write_bits == 32'h51f15e;
assign t_385 = t_381 == 1'h0;
assign t_386 = t_383 & t_385;
assign t_388 = io_regs_key_write_valid | t_381;
assign gen_0 = t_388 ? t_386 : unlocked;
assign t_391 = io_regs_sleep_write_valid & unlocked;
assign gen_1 = t_391 ? 1'h1 : wantsleep;
assign t_394 = io_regs_ie_write_valid & unlocked;
assign gen_2 = t_394 ? io_regs_ie_write_bits : t_396;
assign ie = t_396 | 4'h1;
assign t_423 = pc & 3'h3;
assign t_425 = pc >= 3'h4;
assign t_427 = t_423 & 3'h1;
assign t_429 = t_423 >= 3'h2;
assign t_433 = t_427 >= 3'h1;
assign t_434 = t_433 ? wakeupprogram_7 : wakeupprogram_6;
assign t_439 = t_433 ? wakeupprogram_5 : wakeupprogram_4;
assign t_440 = t_429 ? t_434 : t_439;
assign t_449 = t_433 ? wakeupprogram_3 : wakeupprogram_2;
assign t_454 = t_433 ? wakeupprogram_1 : wakeupprogram_0;
assign t_455 = t_429 ? t_449 : t_454;
assign t_456 = t_425 ? t_440 : t_455;
assign t_469 = t_433 ? sleepprogram_7 : sleepprogram_6;
assign t_474 = t_433 ? sleepprogram_5 : sleepprogram_4;
assign t_475 = t_429 ? t_469 : t_474;
assign t_484 = t_433 ? sleepprogram_3 : sleepprogram_2;
assign t_489 = t_433 ? sleepprogram_1 : sleepprogram_0;
assign t_490 = t_429 ? t_484 : t_489;
assign t_491 = t_425 ? t_475 : t_490;
assign insnbits = awake ? t_456 : t_491;
assign insn_sigs_hfclkrst = t_520;
assign insn_sigs_corerst = t_519;
assign insn_sigs_reserved1 = t_518;
assign insn_sigs_vddpaden = t_517;
assign insn_sigs_reserved0 = t_516;
assign insn_dt = t_515;
assign t_515 = insnbits[3:0];
assign t_516 = insnbits[4];
assign t_517 = insnbits[5];
assign t_518 = insnbits[6];
assign t_519 = insnbits[7];
assign t_520 = insnbits[8];
assign t_523 = count + 16'h1;
assign t_524 = t_523[15:0];
assign t_525 = count ^ t_524;
assign t_526 = t_525 >> insn_dt;
assign tick = t_526[0];
assign npc = pc + 3'h1;
assign last = npc >= 4'h8;
assign t_530 = last == 1'h0;
assign t_531 = run & t_530;
assign t_532 = t_531 & tick;
assign gen_3 = tick ? 16'h0 : t_524;
assign gen_4 = tick ? t_530 : run;
assign gen_5 = tick ? npc : {{1'd0}, pc};
assign gen_6 = run ? gen_3 : count;
assign gen_7 = run ? gen_4 : run;
assign gen_8 = run ? gen_5 : {{1'd0}, pc};
assign t_540 = run == 1'h0;
assign t_541 = {io_wakeup_rtc,io_wakeup_reset};
assign t_542 = {io_wakeup_awakeup,io_wakeup_dwakeup};
assign t_543 = {t_542,t_541};
assign t_544 = ie & t_543;
assign t_546 = awake == 1'h0;
assign t_548 = t_544 != 4'h0;
assign t_549 = t_546 & t_548;
assign t_552 = t_544[0];
assign t_553 = t_544[1];
assign t_554 = t_544[2];
assign t_560 = t_554 ? 2'h2 : 2'h3;
assign t_561 = t_553 ? 2'h1 : t_560;
assign t_562 = t_552 ? 2'h0 : t_561;
assign gen_9 = t_549 ? 1'h1 : gen_7;
assign gen_10 = t_549 ? 1'h1 : awake;
assign gen_11 = t_549 ? t_562 : wakeupcause;
assign t_563 = awake & wantsleep; assign gen_12 = t_563 ? 1'h1 : gen_9;
assign gen_13 = t_563 ? 1'h0 : gen_10;
assign gen_14 = t_563 ? 1'h0 : gen_1;
assign gen_15 = t_540 ? gen_12 : gen_7;
assign gen_16 = t_540 ? gen_13 : awake;
assign gen_17 = t_540 ? gen_11 : wakeupcause;
assign gen_18 = t_540 ? gen_14 : gen_1;
assign gen_35 = {{8'd0}, io_resetcause};
assign t_567 = gen_35 << 8;
assign gen_36 = {{8'd0}, wakeupcause};
assign t_568 = gen_36 | t_567;
assign t_570 = io_regs_wakeupprogram_0_write_valid & unlocked;
assign gen_19 = t_570 ? io_regs_wakeupprogram_0_write_bits : {{23'd0}, wakeupprogram_0};
assign t_571 = io_regs_wakeupprogram_1_write_valid & unlocked;
assign gen_20 = t_571 ? io_regs_wakeupprogram_1_write_bits : {{23'd0}, wakeupprogram_1};
assign t_572 = io_regs_wakeupprogram_2_write_valid & unlocked;
assign gen_21 = t_572 ? io_regs_wakeupprogram_2_write_bits : {{23'd0}, wakeupprogram_2};
assign t_573 = io_regs_wakeupprogram_3_write_valid & unlocked;
assign gen_22 = t_573 ? io_regs_wakeupprogram_3_write_bits : {{23'd0}, wakeupprogram_3};
assign t_574 = io_regs_wakeupprogram_4_write_valid & unlocked;
assign gen_23 = t_574 ? io_regs_wakeupprogram_4_write_bits : {{23'd0}, wakeupprogram_4};
assign t_575 = io_regs_wakeupprogram_5_write_valid & unlocked;
assign gen_24 = t_575 ? io_regs_wakeupprogram_5_write_bits : {{23'd0}, wakeupprogram_5};
assign t_576 = io_regs_wakeupprogram_6_write_valid & unlocked;
assign gen_25 = t_576 ? io_regs_wakeupprogram_6_write_bits : {{23'd0}, wakeupprogram_6};
assign t_577 = io_regs_wakeupprogram_7_write_valid & unlocked;
assign gen_26 = t_577 ? io_regs_wakeupprogram_7_write_bits : {{23'd0}, wakeupprogram_7};
assign t_578 = io_regs_sleepprogram_0_write_valid & unlocked;
assign gen_27 = t_578 ? io_regs_sleepprogram_0_write_bits : {{23'd0}, sleepprogram_0};
assign t_579 = io_regs_sleepprogram_1_write_valid & unlocked;
assign gen_28 = t_579 ? io_regs_sleepprogram_1_write_bits : {{23'd0}, sleepprogram_1};
assign t_580 = io_regs_sleepprogram_2_write_valid & unlocked;
assign gen_29 = t_580 ? io_regs_sleepprogram_2_write_bits : {{23'd0}, sleepprogram_2};
assign t_581 = io_regs_sleepprogram_3_write_valid & unlocked;
assign gen_30 = t_581 ? io_regs_sleepprogram_3_write_bits : {{23'd0}, sleepprogram_3};
assign t_582 = io_regs_sleepprogram_4_write_valid & unlocked;
assign gen_31 = t_582 ? io_regs_sleepprogram_4_write_bits : {{23'd0}, sleepprogram_4};
assign t_583 = io_regs_sleepprogram_5_write_valid & unlocked;
assign gen_32 = t_583 ? io_regs_sleepprogram_5_write_bits : {{23'd0}, sleepprogram_5};
assign t_584 = io_regs_sleepprogram_6_write_valid & unlocked;
assign gen_33 = t_584 ? io_regs_sleepprogram_6_write_bits : {{23'd0}, sleepprogram_6};
assign t_585 = io_regs_sleepprogram_7_write_valid & unlocked;
assign gen_34 = t_585 ? io_regs_sleepprogram_7_write_bits : {{23'd0}, sleepprogram_7};
always @(posedge clock or posedge reset)
if (reset) begin
run <= 1'h1;
end else begin
if (t_540) begin
if (t_563) begin
run <= 1'h1;
end else begin
if (t_549) begin
run <= 1'h1;
end else begin
if (run) begin
if (tick) begin
run <= t_530;
end
end
end
end
end else begin
if (run) begin
if (tick) begin
run <= t_530;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
awake <= 1'h1;
end else begin
if (t_540) begin
if (t_563) begin
awake <= 1'h0;
end else begin
if (t_549) begin
awake <= 1'h1;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
unlocked <= 1'h0;
end else begin
if (t_388) begin
unlocked <= t_386;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
wantsleep <= 1'h0;
end else begin
if (t_540) begin
if (t_563) begin
wantsleep <= 1'h0;
end else begin
if (t_391) begin
wantsleep <= io_regs_sleep_write_bits[0];
end
end
end else begin
if (t_391) begin
wantsleep <= io_regs_sleep_write_bits[0];
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
pc <= 3'h0;
end else begin
pc <= gen_8[2:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupcause <= 2'h0;
end else begin
if (t_540) begin
if (t_549) begin
if (t_552) begin
wakeupcause <= 2'h0;
end else begin
if (t_553) begin
wakeupcause <= 2'h1;
end else begin
if (t_554) begin
wakeupcause <= 2'h2;
end else begin
wakeupcause <= 2'h3;
end
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
t_396 <= 4'b0;
end
else if (t_394) begin
t_396 <= io_regs_ie_write_bits;
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_0 <= 9'h1f0;
end else begin
wakeupprogram_0 <= gen_19[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_1 <= 9'hf8;
end else begin
wakeupprogram_1 <= gen_20[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_2 <= 9'h30;
end else begin
wakeupprogram_2 <= gen_21[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_3 <= 9'h30;
end else begin
wakeupprogram_3 <= gen_22[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_4 <= 9'h30;
end else begin
wakeupprogram_4 <= gen_23[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_5 <= 9'h30;
end else begin
wakeupprogram_5 <= gen_24[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_6 <= 9'h30;
end else begin
wakeupprogram_6 <= gen_25[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupprogram_7 <= 9'h30;
end else begin
wakeupprogram_7 <= gen_26[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_0 <= 9'hf0;
end else begin
sleepprogram_0 <= gen_27[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_1 <= 9'h1f0;
end else begin
sleepprogram_1 <= gen_28[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_2 <= 9'h1d0;
end else begin
sleepprogram_2 <= gen_29[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_3 <= 9'h1c0;
end else begin
sleepprogram_3 <= gen_30[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_4 <= 9'h1c0;
end else begin
sleepprogram_4 <= gen_31[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_5 <= 9'h1c0;
end else begin
sleepprogram_5 <= gen_32[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_6 <= 9'h1c0;
end else begin
sleepprogram_6 <= gen_33[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepprogram_7 <= 9'h1c0;
end else begin
sleepprogram_7 <= gen_34[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
count <= 16'h0;
end else begin
if (run) begin
if (tick) begin
count <= 16'h0;
end else begin
count <= t_524;
end
end
end
endmodule |
module sirv_qspi_arbiter(
input clock,
input reset,
output io_inner_0_tx_ready,
input io_inner_0_tx_valid,
input [7:0] io_inner_0_tx_bits,
output io_inner_0_rx_valid,
output [7:0] io_inner_0_rx_bits,
input [7:0] io_inner_0_cnt,
input [1:0] io_inner_0_fmt_proto,
input io_inner_0_fmt_endian,
input io_inner_0_fmt_iodir,
input io_inner_0_cs_set,
input io_inner_0_cs_clear,
input io_inner_0_cs_hold,
output io_inner_0_active,
input io_inner_0_lock,
output io_inner_1_tx_ready,
input io_inner_1_tx_valid,
input [7:0] io_inner_1_tx_bits,
output io_inner_1_rx_valid,
output [7:0] io_inner_1_rx_bits,
input [7:0] io_inner_1_cnt,
input [1:0] io_inner_1_fmt_proto,
input io_inner_1_fmt_endian,
input io_inner_1_fmt_iodir,
input io_inner_1_cs_set,
input io_inner_1_cs_clear,
input io_inner_1_cs_hold,
output io_inner_1_active,
input io_inner_1_lock,
input io_outer_tx_ready,
output io_outer_tx_valid,
output [7:0] io_outer_tx_bits,
input io_outer_rx_valid,
input [7:0] io_outer_rx_bits,
output [7:0] io_outer_cnt,
output [1:0] io_outer_fmt_proto,
output io_outer_fmt_endian,
output io_outer_fmt_iodir,
output io_outer_cs_set,
output io_outer_cs_clear,
output io_outer_cs_hold,
input io_outer_active,
input io_sel
);
wire t_335_0;
wire t_335_1;
reg sel_0;
reg [31:0] gen_4;
reg sel_1;
reg [31:0] gen_5;
wire t_346;
wire t_349;
wire t_351;
wire t_352;
wire [7:0] t_354;
wire [7:0] t_356;
wire [7:0] t_358;
wire [7:0] t_359;
wire [7:0] t_361;
wire [7:0] t_363;
wire [7:0] t_365;
wire [7:0] t_366;
wire [2:0] t_367;
wire [3:0] t_368;
wire [3:0] t_370;
wire [2:0] t_371;
wire [3:0] t_372;
wire [3:0] t_374;
wire [3:0] t_379;
wire [1:0] t_384_proto;
wire t_384_endian;
wire t_384_iodir;
wire t_388;
wire t_389;
wire [1:0] t_390;
wire [1:0] t_391;
wire [2:0] t_392;
wire [2:0] t_394;
wire [1:0] t_395;
wire [2:0] t_396;
wire [2:0] t_398;
wire [2:0] t_406;
wire t_414_set;
wire t_414_clear;
wire t_414_hold;
wire t_421;
wire t_422;
wire t_423;
wire t_424;
wire t_425;
wire t_426;
wire t_427;
wire t_428;
wire t_429;
wire t_431;
wire nsel_0;
wire nsel_1;
wire t_445;
wire t_448;
wire t_450;
wire lock;
wire t_452;
wire [1:0] t_453;
wire [1:0] t_454;
wire t_455;
wire gen_0;
wire gen_1;
wire gen_2;
wire gen_3;
assign io_inner_0_tx_ready = t_424;
assign io_inner_0_rx_valid = t_425;
assign io_inner_0_rx_bits = io_outer_rx_bits;
assign io_inner_0_active = t_426;
assign io_inner_1_tx_ready = t_427;
assign io_inner_1_rx_valid = t_428;
assign io_inner_1_rx_bits = io_outer_rx_bits;
assign io_inner_1_active = t_429;
assign io_outer_tx_valid = t_352;
assign io_outer_tx_bits = t_359;
assign io_outer_cnt = t_366;
assign io_outer_fmt_proto = t_384_proto;
assign io_outer_fmt_endian = t_384_endian;
assign io_outer_fmt_iodir = t_384_iodir;
assign io_outer_cs_set = t_414_set;
assign io_outer_cs_clear = gen_3;
assign io_outer_cs_hold = t_414_hold;
assign t_335_0 = 1'h1;
assign t_335_1 = 1'h0;
assign t_346 = sel_0 ? io_inner_0_tx_valid : 1'h0;
assign t_349 = sel_1 ? io_inner_1_tx_valid : 1'h0;
assign t_351 = t_346 | t_349;
assign t_352 = t_351;
assign t_354 = sel_0 ? io_inner_0_tx_bits : 8'h0;
assign t_356 = sel_1 ? io_inner_1_tx_bits : 8'h0;
assign t_358 = t_354 | t_356;
assign t_359 = t_358;
assign t_361 = sel_0 ? io_inner_0_cnt : 8'h0;
assign t_363 = sel_1 ? io_inner_1_cnt : 8'h0;
assign t_365 = t_361 | t_363;
assign t_366 = t_365;
assign t_367 = {io_inner_0_fmt_proto,io_inner_0_fmt_endian};
assign t_368 = {t_367,io_inner_0_fmt_iodir};
assign t_370 = sel_0 ? t_368 : 4'h0;
assign t_371 = {io_inner_1_fmt_proto,io_inner_1_fmt_endian};
assign t_372 = {t_371,io_inner_1_fmt_iodir};
assign t_374 = sel_1 ? t_372 : 4'h0;
assign t_379 = t_370 | t_374;
assign t_384_proto = t_390;
assign t_384_endian = t_389;
assign t_384_iodir = t_388;
assign t_388 = t_379[0];
assign t_389 = t_379[1];
assign t_390 = t_379[3:2];
assign t_391 = {io_inner_0_cs_set,io_inner_0_cs_clear};
assign t_392 = {t_391,io_inner_0_cs_hold};
assign t_394 = sel_0 ? t_392 : 3'h0;
assign t_395 = {io_inner_1_cs_set,io_inner_1_cs_clear};
assign t_396 = {t_395,io_inner_1_cs_hold};
assign t_398 = sel_1 ? t_396 : 3'h0;
assign t_406 = t_394 | t_398;
assign t_414_set = t_423;
assign t_414_clear = t_422;
assign t_414_hold = t_421;
assign t_421 = t_406[0];
assign t_422 = t_406[1];
assign t_423 = t_406[2];
assign t_424 = io_outer_tx_ready & sel_0;
assign t_425 = io_outer_rx_valid & sel_0;
assign t_426 = io_outer_active & sel_0;
assign t_427 = io_outer_tx_ready & sel_1;
assign t_428 = io_outer_rx_valid & sel_1;
assign t_429 = io_outer_active & sel_1;
assign t_431 = io_sel == 1'h0;
assign nsel_0 = t_431;
assign nsel_1 = io_sel;
assign t_445 = sel_0 ? io_inner_0_lock : 1'h0;
assign t_448 = sel_1 ? io_inner_1_lock : 1'h0;
assign t_450 = t_445 | t_448;
assign lock = t_450;
assign t_452 = lock == 1'h0;
assign t_453 = {sel_1,sel_0};
assign t_454 = {nsel_1,nsel_0};
assign t_455 = t_453 != t_454;
assign gen_0 = t_455 ? 1'h1 : t_414_clear;
assign gen_1 = t_452 ? nsel_0 : sel_0;
assign gen_2 = t_452 ? nsel_1 : sel_1;
assign gen_3 = t_452 ? gen_0 : t_414_clear;
always @(posedge clock or posedge reset)
if (reset) begin
sel_0 <= t_335_0;
end else begin
if (t_452) begin
sel_0 <= nsel_0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sel_1 <= t_335_1;
end else begin
if (t_452) begin
sel_1 <= nsel_1;
end
end
endmodule |
module sirv_qspi_physical(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] gen_2;
reg ctrl_sck_pol;
reg [31:0] gen_31;
reg ctrl_sck_pha;
reg [31:0] gen_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] gen_67;
reg ctrl_fmt_endian;
reg [31:0] gen_68;
reg ctrl_fmt_iodir;
reg [31:0] gen_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] gen_70;
reg t_119;
reg [31:0] gen_71;
reg t_120;
reg [31:0] gen_72;
reg sample_d;
reg [31:0] gen_73;
reg t_122;
reg [31:0] gen_74;
reg t_123;
reg [31:0] gen_75;
reg last_d;
reg [31:0] gen_76;
reg [7:0] scnt;
reg [31:0] gen_77;
reg [11:0] tcnt;
reg [31:0] gen_78;
wire stop;
wire beat;
wire [11:0] t_127;
wire [12:0] t_129;
wire [11:0] decr;
wire sched;
wire [11:0] t_130;
reg sck;
reg [31:0] gen_79;
reg cref;
reg [31:0] gen_80;
wire cinv;
wire [1:0] t_133;
wire [1:0] t_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] gen_81;
wire t_135;
wire t_136;
wire t_137;
wire t_138;
wire t_139;
wire t_140;
wire t_141;
wire t_142;
wire t_143;
wire [1:0] t_144;
wire [1:0] t_145;
wire [3:0] t_146;
wire [1:0] t_147;
wire [1:0] t_148;
wire [3:0] t_149;
wire [7:0] t_150;
wire [7:0] buffer_in;
wire t_151;
wire shift;
wire [6:0] t_152;
wire [6:0] t_153;
wire [6:0] t_154;
wire t_155;
wire t_157;
wire [7:0] t_158;
wire [5:0] t_159;
wire [5:0] t_160;
wire [5:0] t_161;
wire [1:0] t_162;
wire [1:0] t_163;
wire [7:0] t_164;
wire [3:0] t_165;
wire [3:0] t_166;
wire [3:0] t_167;
wire [3:0] t_169;
wire [7:0] t_170;
wire [7:0] t_172;
wire [7:0] t_174;
wire [7:0] t_176;
wire [7:0] t_178;
wire [7:0] t_179;
wire [7:0] t_180;
reg [3:0] txd;
reg [31:0] gen_82;
wire [3:0] t_182;
wire [3:0] txd_in;
wire [1:0] t_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire t_186;
wire [1:0] t_188;
wire [3:0] t_190;
wire [1:0] gen_65;
wire [1:0] t_192;
wire [3:0] gen_66;
wire [3:0] t_193;
wire [3:0] t_194;
wire [3:0] gen_0;
wire t_195;
wire t_196;
wire txen_1;
wire txen_0;
wire t_202_0;
wire t_206;
wire t_207;
wire t_208;
wire t_209;
reg done;
reg [31:0] gen_83;
wire t_212;
wire t_213;
wire t_215;
wire t_216;
wire t_217;
wire t_218;
wire t_219;
wire t_220;
wire t_221;
wire [1:0] t_222;
wire [1:0] t_223;
wire [3:0] t_224;
wire [1:0] t_225;
wire [1:0] t_226;
wire [3:0] t_227;
wire [7:0] t_228;
wire [7:0] t_229;
reg xfr;
reg [31:0] gen_84;
wire gen_1;
wire t_234;
wire t_236;
wire t_237;
wire gen_3;
wire gen_4;
wire gen_5;
wire [11:0] gen_6;
wire gen_7;
wire gen_8;
wire gen_9;
wire gen_10;
wire [11:0] gen_11;
wire gen_12;
wire gen_13;
wire gen_14;
wire gen_15;
wire [11:0] gen_16;
wire t_243;
wire t_244;
wire t_245;
wire t_248;
wire gen_17;
wire gen_18;
wire gen_19;
wire gen_20;
wire gen_21;
wire gen_22;
wire gen_23;
wire t_251;
wire [1:0] gen_24;
wire gen_25;
wire gen_26;
wire t_256;
wire t_259;
wire [7:0] gen_27;
wire gen_28;
wire gen_29;
wire gen_30;
wire gen_32;
wire [11:0] gen_33;
wire gen_34;
wire gen_35;
wire gen_36;
wire [11:0] gen_37;
wire gen_38;
wire gen_39;
wire [11:0] gen_40;
wire [1:0] gen_41;
wire gen_42;
wire gen_43;
wire gen_44;
wire [7:0] gen_45;
wire gen_46;
wire gen_47;
wire gen_48;
wire [11:0] gen_49;
wire gen_50;
wire gen_51;
wire [11:0] gen_53;
wire [1:0] gen_54;
wire gen_55;
wire gen_56;
wire gen_57;
wire [7:0] gen_58;
wire gen_59;
wire gen_60;
wire gen_61;
wire [11:0] gen_62;
wire gen_63;
wire gen_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = t_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = t_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = t_208;
assign io_port_dq_2_oe = t_196;
assign io_port_dq_3_o = t_209;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = t_202_0;
assign io_op_ready = t_251;
assign io_rx_valid = done;
assign io_rx_bits = t_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = gen_21;
assign sample = gen_14;
assign setup = gen_60;
assign last = gen_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign t_127 = beat ? {{4'd0}, scnt} : tcnt;
assign t_129 = t_127 - 12'h1;
assign decr = t_129[11:0];
assign sched = gen_1;
assign t_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign t_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign t_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {t_134,t_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign t_135 = io_ctrl_fmt_endian == 1'h0;
assign t_136 = io_op_bits_data[0];
assign t_137 = io_op_bits_data[1];
assign t_138 = io_op_bits_data[2];
assign t_139 = io_op_bits_data[3];
assign t_140 = io_op_bits_data[4];
assign t_141 = io_op_bits_data[5];
assign t_142 = io_op_bits_data[6];
assign t_143 = io_op_bits_data[7];
assign t_144 = {t_142,t_143};
assign t_145 = {t_140,t_141};
assign t_146 = {t_145,t_144};
assign t_147 = {t_138,t_139};
assign t_148 = {t_136,t_137};
assign t_149 = {t_148,t_147};
assign t_150 = {t_149,t_146};
assign buffer_in = t_135 ? io_op_bits_data : t_150;
assign t_151 = sample_d & stop;
assign shift = setup_d | t_151;
assign t_152 = buffer[6:0];
assign t_153 = buffer[7:1];
assign t_154 = shift ? t_152 : t_153;
assign t_155 = buffer[0];
assign t_157 = sample_d ? samples_0 : t_155;
assign t_158 = {t_154,t_157};
assign t_159 = buffer[5:0];
assign t_160 = buffer[7:2];
assign t_161 = shift ? t_159 : t_160;
assign t_162 = buffer[1:0];
assign t_163 = sample_d ? samples_1 : t_162;
assign t_164 = {t_161,t_163};
assign t_165 = buffer[3:0];
assign t_166 = buffer[7:4];
assign t_167 = shift ? t_165 : t_166;
assign t_169 = sample_d ? rxd : t_165;
assign t_170 = {t_167,t_169};
assign t_172 = proto_0 ? t_158 : 8'h0;
assign t_174 = proto_1 ? t_164 : 8'h0;
assign t_176 = proto_2 ? t_170 : 8'h0;
assign t_178 = t_172 | t_174;
assign t_179 = t_178 | t_176;
assign t_180 = t_179;
assign t_182 = buffer_in[7:4];
assign txd_in = accept ? t_182 : t_166;
assign t_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == t_184;
assign txd_sel_1 = 2'h1 == t_184;
assign txd_sel_2 = 2'h2 == t_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign t_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign t_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign t_190 = txd_sel_2 ? txd_in : 4'h0;
assign gen_65 = {{1'd0}, t_186};
assign t_192 = gen_65 | t_188;
assign gen_66 = {{2'd0}, t_192};
assign t_193 = gen_66 | t_190;
assign t_194 = t_193;
assign gen_0 = setup ? t_194 : txd;
assign t_195 = proto_1 & ctrl_fmt_iodir;
assign t_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = t_195 | t_196;
assign txen_0 = proto_0 | txen_1;
assign t_202_0 = 1'h1;
assign t_206 = txd[0];
assign t_207 = txd[1];
assign t_208 = txd[2];
assign t_209 = txd[3];
assign t_212 = done | last_d;
assign t_213 = ctrl_fmt_endian == 1'h0;
assign t_215 = buffer[1];
assign t_216 = buffer[2];
assign t_217 = buffer[3];
assign t_218 = buffer[4];
assign t_219 = buffer[5];
assign t_220 = buffer[6];
assign t_221 = buffer[7];
assign t_222 = {t_220,t_221};
assign t_223 = {t_218,t_219};
assign t_224 = {t_223,t_222};
assign t_225 = {t_216,t_217};
assign t_226 = {t_155,t_215};
assign t_227 = {t_226,t_225};
assign t_228 = {t_227,t_224};
assign t_229 = t_213 ? buffer : t_228;
assign gen_1 = stop ? 1'h1 : beat;
assign t_234 = stop == 1'h0;
assign t_236 = cref == 1'h0;
assign t_237 = cref ^ cinv;
assign gen_3 = xfr ? t_237 : sck;
assign gen_4 = xfr ? cref : 1'h0;
assign gen_5 = xfr ? t_236 : 1'h0;
assign gen_6 = t_236 ? decr : {{4'd0}, scnt};
assign gen_7 = beat ? t_236 : cref;
assign gen_8 = beat ? gen_3 : sck;
assign gen_9 = beat ? gen_4 : 1'h0;
assign gen_10 = beat ? gen_5 : 1'h0;
assign gen_11 = beat ? gen_6 : {{4'd0}, scnt};
assign gen_12 = t_234 ? gen_7 : cref;
assign gen_13 = t_234 ? gen_8 : sck;
assign gen_14 = t_234 ? gen_9 : 1'h0;
assign gen_15 = t_234 ? gen_10 : 1'h0;
assign gen_16 = t_234 ? gen_11 : {{4'd0}, scnt};
assign t_243 = scnt == 8'h1;
assign t_244 = beat & cref;
assign t_245 = t_244 & xfr;
assign t_248 = beat & t_236;
assign gen_17 = t_248 ? 1'h1 : stop;
assign gen_18 = t_248 ? 1'h0 : gen_15;
assign gen_19 = t_248 ? ctrl_sck_pol : gen_13;
assign gen_20 = t_243 ? t_245 : 1'h0;
assign gen_21 = t_243 ? gen_17 : stop;
assign gen_22 = t_243 ? gen_18 : gen_15;
assign gen_23 = t_243 ? gen_19 : gen_13;
assign t_251 = accept & done;
assign gen_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign gen_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign gen_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign t_256 = 1'h0 == io_op_bits_fn;
assign t_259 = io_op_bits_cnt == 8'h0;
assign gen_27 = t_256 ? buffer_in : t_180;
assign gen_28 = t_256 ? cinv : gen_23;
assign gen_29 = t_256 ? 1'h1 : gen_22;
assign gen_30 = t_256 ? t_259 : t_212;
assign gen_32 = io_op_bits_stb ? io_ctrl_sck_pol : gen_28;
assign gen_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign gen_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign gen_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign gen_36 = io_op_bits_fn ? gen_32 : gen_28;
assign gen_37 = io_op_bits_fn ? gen_33 : ctrl_sck_div;
assign gen_38 = io_op_bits_fn ? gen_34 : ctrl_sck_pol;
assign gen_39 = io_op_bits_fn ? gen_35 : ctrl_sck_pha;
assign gen_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : gen_16;
assign gen_41 = io_op_valid ? gen_24 : ctrl_fmt_proto;
assign gen_42 = io_op_valid ? gen_25 : ctrl_fmt_endian;
assign gen_43 = io_op_valid ? gen_26 : ctrl_fmt_iodir;
assign gen_44 = io_op_valid ? t_256 : xfr;
assign gen_45 = io_op_valid ? gen_27 : t_180;
assign gen_46 = io_op_valid ? gen_36 : gen_23;
assign gen_47 = io_op_valid ? gen_29 : gen_22;
assign gen_48 = io_op_valid ? gen_30 : t_212;
assign gen_49 = io_op_valid ? gen_37 : ctrl_sck_div;
assign gen_50 = io_op_valid ? gen_38 : ctrl_sck_pol;
assign gen_51 = io_op_valid ? gen_39 : ctrl_sck_pha;
assign gen_53 = t_251 ? gen_40 : gen_16;
assign gen_54 = t_251 ? gen_41 : ctrl_fmt_proto;
assign gen_55 = t_251 ? gen_42 : ctrl_fmt_endian;
assign gen_56 = t_251 ? gen_43 : ctrl_fmt_iodir;
assign gen_57 = t_251 ? gen_44 : xfr;
assign gen_58 = t_251 ? gen_45 : t_180;
assign gen_59 = t_251 ? gen_46 : gen_23;
assign gen_60 = t_251 ? gen_47 : gen_22;
assign gen_61 = t_251 ? gen_48 : t_212;
assign gen_62 = t_251 ? gen_49 : ctrl_sck_div;
assign gen_63 = t_251 ? gen_50 : ctrl_sck_pol;
assign gen_64 = t_251 ? gen_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (t_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (t_256) begin
sck <= cinv;
end else begin
if (t_243) begin
if (t_248) begin
sck <= ctrl_sck_pol;
end else begin
if (t_234) begin
if (beat) begin
if (xfr) begin
sck <= t_237;
end
end
end
end
end else begin
if (t_234) begin
if (beat) begin
if (xfr) begin
sck <= t_237;
end
end
end
end
end
end
end else begin
if (t_256) begin
sck <= cinv;
end else begin
if (t_243) begin
if (t_248) begin
sck <= ctrl_sck_pol;
end else begin
if (t_234) begin
if (beat) begin
if (xfr) begin
sck <= t_237;
end
end
end
end
end else begin
if (t_234) begin
if (beat) begin
if (xfr) begin
sck <= t_237;
end
end
end
end
end
end
end else begin
if (t_243) begin
if (t_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= gen_13;
end
end else begin
sck <= gen_13;
end
end
end else begin
if (t_243) begin
if (t_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= gen_13;
end
end else begin
sck <= gen_13;
end
end
if (t_251) begin
if (io_op_valid) begin
if (t_256) begin
if (t_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= t_150;
end
end else begin
buffer <= t_180;
end
end else begin
buffer <= t_180;
end
end else begin
buffer <= t_180;
end
if (t_251) begin
if (io_op_valid) begin
xfr <= t_256;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (t_234) begin
if (beat) begin
cref <= t_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= t_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (t_251) begin
if (io_op_valid) begin
if (t_256) begin
done <= t_259;
end else begin
done <= t_212;
end
end else begin
done <= t_212;
end
end else begin
done <= t_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
t_119 <= 1'h0;
end else begin
t_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_120 <= 1'h0;
end else begin
t_120 <= t_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= t_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_122 <= 1'h0;
end else begin
t_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
t_123 <= 1'h0;
end else begin
t_123 <= t_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= t_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= gen_53[7:0];
end
endmodule |
module sirv_queue(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_read,
input [9:0] io_enq_bits_index,
input [31:0] io_enq_bits_data,
input [3:0] io_enq_bits_mask,
input [9:0] io_enq_bits_extra,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_read,
output [9:0] io_deq_bits_index,
output [31:0] io_deq_bits_data,
output [3:0] io_deq_bits_mask,
output [9:0] io_deq_bits_extra,
output io_count
);
reg ram_read [0:0];
reg [31:0] gen_0;
wire ram_read_t_83_data;
wire ram_read_t_83_addr;
wire ram_read_t_69_data;
wire ram_read_t_69_addr;
wire ram_read_t_69_mask;
wire ram_read_t_69_en;
reg [9:0] ram_index [0:0];
reg [31:0] gen_1;
wire [9:0] ram_index_t_83_data;
wire ram_index_t_83_addr;
wire [9:0] ram_index_t_69_data;
wire ram_index_t_69_addr;
wire ram_index_t_69_mask;
wire ram_index_t_69_en;
reg [31:0] ram_data [0:0];
reg [31:0] gen_2;
wire [31:0] ram_data_t_83_data;
wire ram_data_t_83_addr;
wire [31:0] ram_data_t_69_data;
wire ram_data_t_69_addr;
wire ram_data_t_69_mask;
wire ram_data_t_69_en;
reg [3:0] ram_mask [0:0];
reg [31:0] gen_3;
wire [3:0] ram_mask_t_83_data;
wire ram_mask_t_83_addr;
wire [3:0] ram_mask_t_69_data;
wire ram_mask_t_69_addr;
wire ram_mask_t_69_mask;
wire ram_mask_t_69_en;
reg [9:0] ram_extra [0:0];
reg [31:0] gen_4;
wire [9:0] ram_extra_t_83_data;
wire ram_extra_t_83_addr;
wire [9:0] ram_extra_t_69_data;
wire ram_extra_t_69_addr;
wire ram_extra_t_69_mask;
wire ram_extra_t_69_en;
reg maybe_full;
reg [31:0] gen_5;
wire t_65;
wire t_66;
wire do_enq;
wire t_67;
wire do_deq;
wire t_77;
wire gen_8;
wire t_79;
wire gen_9;
wire [1:0] t_90;
wire ptr_diff;
wire [1:0] t_92;
assign io_enq_ready = gen_9;
assign io_deq_valid = t_79;
assign io_deq_bits_read = ram_read_t_83_data;
assign io_deq_bits_index = ram_index_t_83_data;
assign io_deq_bits_data = ram_data_t_83_data;
assign io_deq_bits_mask = ram_mask_t_83_data;
assign io_deq_bits_extra = ram_extra_t_83_data;
assign io_count = t_92[0];
assign ram_read_t_83_addr = 1'h0;
assign ram_read_t_83_data = ram_read[ram_read_t_83_addr];
assign ram_read_t_69_data = io_enq_bits_read;
assign ram_read_t_69_addr = 1'h0;
assign ram_read_t_69_mask = do_enq;
assign ram_read_t_69_en = do_enq;
assign ram_index_t_83_addr = 1'h0;
assign ram_index_t_83_data = ram_index[ram_index_t_83_addr];
assign ram_index_t_69_data = io_enq_bits_index;
assign ram_index_t_69_addr = 1'h0;
assign ram_index_t_69_mask = do_enq;
assign ram_index_t_69_en = do_enq;
assign ram_data_t_83_addr = 1'h0;
assign ram_data_t_83_data = ram_data[ram_data_t_83_addr];
assign ram_data_t_69_data = io_enq_bits_data;
assign ram_data_t_69_addr = 1'h0;
assign ram_data_t_69_mask = do_enq;
assign ram_data_t_69_en = do_enq;
assign ram_mask_t_83_addr = 1'h0;
assign ram_mask_t_83_data = ram_mask[ram_mask_t_83_addr];
assign ram_mask_t_69_data = io_enq_bits_mask;
assign ram_mask_t_69_addr = 1'h0;
assign ram_mask_t_69_mask = do_enq;
assign ram_mask_t_69_en = do_enq;
assign ram_extra_t_83_addr = 1'h0;
assign ram_extra_t_83_data = ram_extra[ram_extra_t_83_addr];
assign ram_extra_t_69_data = io_enq_bits_extra;
assign ram_extra_t_69_addr = 1'h0;
assign ram_extra_t_69_mask = do_enq;
assign ram_extra_t_69_en = do_enq;
assign t_65 = maybe_full == 1'h0;
assign t_66 = io_enq_ready & io_enq_valid;
assign do_enq = t_66;
assign t_67 = io_deq_ready & io_deq_valid;
assign do_deq = t_67;
assign t_77 = do_enq != do_deq;
assign gen_8 = t_77 ? do_enq : maybe_full;
assign t_79 = t_65 == 1'h0;
assign gen_9 = io_deq_ready ? 1'h1 : t_65;
assign t_90 = 1'h0 - 1'h0;
assign ptr_diff = t_90[0:0];
assign t_92 = {maybe_full,ptr_diff};
always @(posedge clock) begin if(ram_read_t_69_en & ram_read_t_69_mask) begin
ram_read[ram_read_t_69_addr] <= ram_read_t_69_data;
end
if(ram_index_t_69_en & ram_index_t_69_mask) begin
ram_index[ram_index_t_69_addr] <= ram_index_t_69_data;
end
if(ram_data_t_69_en & ram_data_t_69_mask) begin
ram_data[ram_data_t_69_addr] <= ram_data_t_69_data;
end
if(ram_mask_t_69_en & ram_mask_t_69_mask) begin
ram_mask[ram_mask_t_69_addr] <= ram_mask_t_69_data;
end
if(ram_extra_t_69_en & ram_extra_t_69_mask) begin
ram_extra[ram_extra_t_69_addr] <= ram_extra_t_69_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (t_77) begin
maybe_full <= do_enq;
end
end
end
endmodule |
module sirv_queue_1(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output [7:0] io_deq_bits,
output [3:0] io_count
);
reg [7:0] ram [0:7];
reg [31:0] gen_0;
wire [7:0] ram_t_51_data;
wire [2:0] ram_t_51_addr;
wire [7:0] ram_t_35_data;
wire [2:0] ram_t_35_addr;
wire ram_t_35_mask;
wire ram_t_35_en;
reg [2:0] t_27;
reg [31:0] gen_1;
reg [2:0] t_29;
reg [31:0] gen_2;
reg maybe_full;
reg [31:0] gen_3;
wire ptr_match;
wire t_32;
wire empty;
wire full;
wire t_33;
wire do_enq;
wire t_34;
wire do_deq;
wire [3:0] t_39;
wire [2:0] t_40;
wire [2:0] gen_4;
wire [3:0] t_44;
wire [2:0] t_45;
wire [2:0] gen_5;
wire t_46;
wire gen_6;
wire t_48;
wire t_50;
wire [3:0] t_52;
wire [2:0] ptr_diff;
wire t_53;
wire [3:0] t_54;
assign io_enq_ready = t_50;
assign io_deq_valid = t_48;
assign io_deq_bits = ram_t_51_data;
assign io_count = t_54;
assign ram_t_51_addr = t_29;
assign ram_t_51_data = ram[ram_t_51_addr];
assign ram_t_35_data = io_enq_bits;
assign ram_t_35_addr = t_27;
assign ram_t_35_mask = do_enq;
assign ram_t_35_en = do_enq;
assign ptr_match = t_27 == t_29;
assign t_32 = maybe_full == 1'h0;
assign empty = ptr_match & t_32;
assign full = ptr_match & maybe_full;
assign t_33 = io_enq_ready & io_enq_valid;
assign do_enq = t_33;
assign t_34 = io_deq_ready & io_deq_valid;
assign do_deq = t_34;
assign t_39 = t_27 + 3'h1;
assign t_40 = t_39[2:0];
assign gen_4 = do_enq ? t_40 : t_27;
assign t_44 = t_29 + 3'h1;
assign t_45 = t_44[2:0];
assign gen_5 = do_deq ? t_45 : t_29;
assign t_46 = do_enq != do_deq;
assign gen_6 = t_46 ? do_enq : maybe_full;
assign t_48 = empty == 1'h0;
assign t_50 = full == 1'h0;
assign t_52 = t_27 - t_29;
assign ptr_diff = t_52[2:0];
assign t_53 = maybe_full & ptr_match;
assign t_54 = {t_53,ptr_diff};
always @(posedge clock) begin if(ram_t_35_en & ram_t_35_mask) begin
ram[ram_t_35_addr] <= ram_t_35_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
t_27 <= 3'h0;
end else begin
if (do_enq) begin
t_27 <= t_40;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
t_29 <= 3'h0;
end else begin
if (do_deq) begin
t_29 <= t_45;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (t_46) begin
maybe_full <= do_enq;
end
end
endmodule |
module sirv_repeater_6(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input io_enq_bits_mask,
input [7:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output io_deq_bits_mask,
output [7:0] io_deq_bits_data
);
reg full;
reg [31:0] gen_9;
reg [2:0] saved_opcode;
reg [31:0] gen_10;
reg [2:0] saved_param;
reg [31:0] gen_11;
reg [2:0] saved_size;
reg [31:0] gen_12;
reg [1:0] saved_source;
reg [31:0] gen_13;
reg [29:0] saved_address;
reg [31:0] gen_14;
reg saved_mask;
reg [31:0] gen_15;
reg [7:0] saved_data;
reg [31:0] gen_16;
wire t_77;
wire t_79;
wire t_80;
wire [2:0] t_81_opcode;
wire [2:0] t_81_param;
wire [2:0] t_81_size;
wire [1:0] t_81_source;
wire [29:0] t_81_address;
wire t_81_mask;
wire [7:0] t_81_data;
wire t_89;
wire t_90;
wire gen_0;
wire [2:0] gen_1;
wire [2:0] gen_2;
wire [2:0] gen_3;
wire [1:0] gen_4;
wire [29:0] gen_5;
wire gen_6;
wire [7:0] gen_7;
wire t_92;
wire t_94;
wire t_95;
wire gen_8;
assign io_full = full;
assign io_enq_ready = t_80;
assign io_deq_valid = t_77;
assign io_deq_bits_opcode = t_81_opcode;
assign io_deq_bits_param = t_81_param;
assign io_deq_bits_size = t_81_size;
assign io_deq_bits_source = t_81_source;
assign io_deq_bits_address = t_81_address;
assign io_deq_bits_mask = t_81_mask;
assign io_deq_bits_data = t_81_data;
assign t_77 = io_enq_valid | full;
assign t_79 = full == 1'h0;
assign t_80 = io_deq_ready & t_79;
assign t_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign t_81_param = full ? saved_param : io_enq_bits_param;
assign t_81_size = full ? saved_size : io_enq_bits_size;
assign t_81_source = full ? saved_source : io_enq_bits_source;
assign t_81_address = full ? saved_address : io_enq_bits_address;
assign t_81_mask = full ? saved_mask : io_enq_bits_mask;
assign t_81_data = full ? saved_data : io_enq_bits_data;
assign t_89 = io_enq_ready & io_enq_valid;
assign t_90 = t_89 & io_repeat;
assign gen_0 = t_90 ? 1'h1 : full;
assign gen_1 = t_90 ? io_enq_bits_opcode : saved_opcode;
assign gen_2 = t_90 ? io_enq_bits_param : saved_param;
assign gen_3 = t_90 ? io_enq_bits_size : saved_size;
assign gen_4 = t_90 ? io_enq_bits_source : saved_source;
assign gen_5 = t_90 ? io_enq_bits_address : saved_address;
assign gen_6 = t_90 ? io_enq_bits_mask : saved_mask;
assign gen_7 = t_90 ? io_enq_bits_data : saved_data;
assign t_92 = io_deq_ready & io_deq_valid;
assign t_94 = io_repeat == 1'h0;
assign t_95 = t_92 & t_94;
assign gen_8 = t_95 ? 1'h0 : gen_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (t_95) begin
full <= 1'h0;
end else begin
if (t_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 1'b0;
saved_data <= 8'b0;
end
else begin
if (t_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (t_90) begin
saved_param <= io_enq_bits_param;
end
if (t_90) begin
saved_size <= io_enq_bits_size;
end
if (t_90) begin
saved_source <= io_enq_bits_source;
end
if (t_90) begin
saved_address <= io_enq_bits_address;
end
if (t_90) begin
saved_mask <= io_enq_bits_mask;
end
if (t_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule |
module sirv_qspi_flashmap(
input clock,
input reset,
input io_en,
input [1:0] io_ctrl_insn_cmd_proto,
input [7:0] io_ctrl_insn_cmd_code,
input io_ctrl_insn_cmd_en,
input [1:0] io_ctrl_insn_addr_proto,
input [2:0] io_ctrl_insn_addr_len,
input [7:0] io_ctrl_insn_pad_code,
input [3:0] io_ctrl_insn_pad_cnt,
input [1:0] io_ctrl_insn_data_proto,
input io_ctrl_fmt_endian,
output io_addr_ready,
input io_addr_valid,
input [31:0] io_addr_bits_next,
input [31:0] io_addr_bits_hold,
input io_data_ready,
output io_data_valid,
output [7:0] io_data_bits,
input io_link_tx_ready,
output io_link_tx_valid,
output [7:0] io_link_tx_bits,
input io_link_rx_valid,
input [7:0] io_link_rx_bits,
output [7:0] io_link_cnt,
output [1:0] io_link_fmt_proto,
output io_link_fmt_endian,
output io_link_fmt_iodir,
output io_link_cs_set,
output io_link_cs_clear,
output io_link_cs_hold,
input io_link_active,
output io_link_lock
);
wire [32:0] t_110;
wire [31:0] addr;
wire t_111;
wire merge;
wire t_113;
wire t_114;
wire t_115;
wire [3:0] t_120;
wire [2:0] t_122;
wire [1:0] t_124;
wire [3:0] gen_46;
wire [3:0] t_126;
wire [3:0] gen_47;
wire [3:0] t_127;
wire [3:0] t_128;
reg [3:0] cnt;
reg [31:0] gen_5;
wire cnt_en;
wire cnt_cmp_0;
wire cnt_cmp_1;
wire cnt_cmp_2;
wire cnt_cmp_3;
wire cnt_cmp_4;
wire cnt_last;
wire cnt_done;
wire t_143;
wire t_144;
wire [4:0] t_146;
wire [3:0] t_147;
wire [3:0] gen_0;
wire gen_1;
wire [3:0] gen_2;
reg [2:0] state;
reg [31:0] gen_9;
wire t_149;
wire [2:0] gen_3;
wire t_153;
wire [2:0] t_154;
wire [2:0] gen_4;
wire [2:0] gen_6;
wire gen_7;
wire t_157;
wire gen_8;
wire [2:0] gen_10;
wire gen_11;
wire gen_12;
wire t_160;
wire gen_13;
wire gen_14;
wire [7:0] gen_15;
wire gen_16;
wire gen_17;
wire gen_18;
wire [2:0] gen_19;
wire gen_20;
wire gen_21;
wire gen_22;
wire [7:0] gen_23;
wire t_163;
wire [2:0] gen_24;
wire [3:0] gen_25;
wire [1:0] gen_26;
wire [2:0] gen_28;
wire [3:0] gen_29;
wire t_164;
wire [7:0] t_165;
wire [7:0] t_166;
wire [7:0] t_167;
wire [7:0] t_168;
wire [7:0] t_170;
wire [7:0] t_172;
wire [7:0] t_174;
wire [7:0] t_176;
wire [7:0] t_178;
wire [7:0] t_179;
wire [7:0] t_180;
wire [7:0] t_181;
wire [2:0] gen_30;
wire [7:0] gen_31;
wire [2:0] gen_33;
wire t_183;
wire [2:0] gen_34;
wire [3:0] gen_35;
wire [7:0] gen_36;
wire [2:0] gen_37;
wire t_184;
wire [2:0] gen_38;
wire [1:0] gen_39;
wire gen_40;
wire [2:0] gen_41;
wire t_185;
wire t_187;
wire [2:0] gen_42;
wire gen_43;
wire gen_44;
wire [2:0] gen_45;
assign io_addr_ready = gen_18;
assign io_data_valid = gen_44;
assign io_data_bits = gen_23;
assign io_link_tx_valid = gen_43;
assign io_link_tx_bits = gen_36;
assign io_link_cnt = {{4'd0}, gen_35};
assign io_link_fmt_proto = gen_39;
assign io_link_fmt_endian = io_ctrl_fmt_endian;
assign io_link_fmt_iodir = gen_40;
assign io_link_cs_set = 1'h1;
assign io_link_cs_clear = gen_20;
assign io_link_cs_hold = 1'h1;
assign io_link_lock = gen_21;
assign t_110 = io_addr_bits_hold + 32'h1;
assign addr = t_110[31:0];
assign t_111 = io_addr_bits_next == addr;
assign merge = io_link_active & t_111;
assign t_113 = 2'h0 == io_link_fmt_proto;
assign t_114 = 2'h1 == io_link_fmt_proto;
assign t_115 = 2'h2 == io_link_fmt_proto;
assign t_120 = t_113 ? 4'h8 : 4'h0;
assign t_122 = t_114 ? 3'h4 : 3'h0;
assign t_124 = t_115 ? 2'h2 : 2'h0;
assign gen_46 = {{1'd0}, t_122};
assign t_126 = t_120 | gen_46;
assign gen_47 = {{2'd0}, t_124};
assign t_127 = t_126 | gen_47;
assign t_128 = t_127;
assign cnt_en = t_164;
assign cnt_cmp_0 = cnt == 4'h0;
assign cnt_cmp_1 = cnt == 4'h1;
assign cnt_cmp_2 = cnt == 4'h2;
assign cnt_cmp_3 = cnt == 4'h3;
assign cnt_cmp_4 = cnt == 4'h4;
assign cnt_last = cnt_cmp_1 & io_link_tx_ready;
assign cnt_done = cnt_last | cnt_cmp_0;
assign t_143 = cnt_cmp_0 == 1'h0;
assign t_144 = io_link_tx_ready & io_link_tx_valid;
assign t_146 = cnt - 4'h1;
assign t_147 = t_146[3:0];
assign gen_0 = t_144 ? t_147 : cnt;
assign gen_1 = cnt_en ? t_143 : 1'h1;
assign gen_2 = cnt_en ? gen_0 : cnt;
assign t_149 = 3'h0 == state;
assign gen_3 = merge ? 3'h4 : state;
assign t_153 = merge == 1'h0;
assign t_154 = io_ctrl_insn_cmd_en ? 3'h1 : 3'h2;
assign gen_4 = t_153 ? t_154 : gen_3;
assign gen_6 = io_addr_valid ? gen_4 : state;
assign gen_7 = io_addr_valid ? t_153 : 1'h0;
assign t_157 = io_addr_valid == 1'h0;
assign gen_8 = t_157 ? 1'h0 : 1'h1;
assign gen_10 = io_en ? gen_6 : state;
assign gen_11 = io_en ? gen_7 : 1'h0;
assign gen_12 = io_en ? gen_8 : 1'h1;
assign t_160 = io_en == 1'h0;
assign gen_13 = t_160 ? io_addr_valid : 1'h0;
assign gen_14 = t_160 ? io_data_ready : io_en;
assign gen_15 = t_160 ? 8'h0 : io_link_rx_bits;
assign gen_16 = t_160 ? 1'h0 : gen_12;
assign gen_17 = t_149 ? 1'h0 : gen_1;
assign gen_18 = t_149 ? gen_14 : 1'h0;
assign gen_19 = t_149 ? gen_10 : state;
assign gen_20 = t_149 ? gen_11 : 1'h0;
assign gen_21 = t_149 ? gen_16 : 1'h1;
assign gen_22 = t_149 ? gen_13 : 1'h0;
assign gen_23 = t_149 ? gen_15 : io_link_rx_bits;
assign t_163 = 3'h1 == state;
assign gen_24 = io_link_tx_ready ? 3'h2 : gen_19;
assign gen_25 = io_link_tx_ready ? {{1'd0}, io_ctrl_insn_addr_len} : gen_2;
assign gen_26 = t_163 ? io_ctrl_insn_cmd_proto : io_ctrl_insn_addr_proto;
assign gen_28 = t_163 ? gen_24 : gen_19;
assign gen_29 = t_163 ? gen_25 : gen_2;
assign t_164 = 3'h2 == state;
assign t_165 = io_addr_bits_hold[7:0];
assign t_166 = io_addr_bits_hold[15:8];
assign t_167 = io_addr_bits_hold[23:16];
assign t_168 = io_addr_bits_hold[31:24];
assign t_170 = cnt_cmp_1 ? t_165 : 8'h0;
assign t_172 = cnt_cmp_2 ? t_166 : 8'h0;
assign t_174 = cnt_cmp_3 ? t_167 : 8'h0;
assign t_176 = cnt_cmp_4 ? t_168 : 8'h0;
assign t_178 = t_170 | t_172;
assign t_179 = t_178 | t_174;
assign t_180 = t_179 | t_176;
assign t_181 = t_180;
assign gen_30 = cnt_done ? 3'h3 : gen_28;
assign gen_31 = t_164 ? t_181 : io_ctrl_insn_cmd_code;
assign gen_33 = t_164 ? gen_30 : gen_28;
assign t_183 = 3'h3 == state;
assign gen_34 = io_link_tx_ready ? 3'h4 : gen_33;
assign gen_35 = t_183 ? io_ctrl_insn_pad_cnt : t_128;
assign gen_36 = t_183 ? io_ctrl_insn_pad_code : gen_31;
assign gen_37 = t_183 ? gen_34 : gen_33;
assign t_184 = 3'h4 == state;
assign gen_38 = io_link_tx_ready ? 3'h5 : gen_37;
assign gen_39 = t_184 ? io_ctrl_insn_data_proto : gen_26;
assign gen_40 = t_184 ? 1'h0 : 1'h1;
assign gen_41 = t_184 ? gen_38 : gen_37;
assign t_185 = 3'h5 == state;
assign t_187 = io_data_ready & io_data_valid;
assign gen_42 = t_187 ? 3'h0 : gen_41;
assign gen_43 = t_185 ? 1'h0 : gen_17;
assign gen_44 = t_185 ? io_link_rx_valid : gen_22;
assign gen_45 = t_185 ? gen_42 : gen_41;
always @(posedge clock or posedge reset)
if (reset) begin
cnt <= 4'b0;
end
else begin
if (t_163) begin
if (io_link_tx_ready) begin
cnt <= {{1'd0}, io_ctrl_insn_addr_len};
end else begin
if (cnt_en) begin
if (t_144) begin
cnt <= t_147;
end
end
end
end else begin
if (cnt_en) begin
if (t_144) begin
cnt <= t_147;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 3'h0;
end else begin
if (t_185) begin
if (t_187) begin
state <= 3'h0;
end else begin
if (t_184) begin
if (io_link_tx_ready) begin
state <= 3'h5;
end else begin
if (t_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
if (t_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
if (t_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
if (t_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (t_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end else begin
if (t_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (t_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end
end else begin
if (t_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
if (t_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (t_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end else begin
if (t_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (t_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end
end
end else begin
if (t_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
if (t_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
state <= gen_19;
end
end else begin
state <= gen_19;
end
end
end else begin
if (t_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
state <= gen_19;
end
end else begin
state <= gen_19;
end
end
end
end
end else begin
if (t_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
if (t_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
state <= gen_28;
end
end else begin
state <= gen_28;
end
end
end else begin
if (t_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
state <= gen_28;
end
end else begin
state <= gen_28;
end
end
end
end
end else begin
if (t_184) begin
if (io_link_tx_ready) begin
state <= 3'h5;
end else begin
if (t_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
state <= gen_33;
end
end else begin
state <= gen_33;
end
end
end else begin
if (t_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
state <= gen_33;
end
end else begin
state <= gen_33;
end
end
end
end
endmodule |
module input_stage #(
parameter extsig_num = 32
) (
input wire clk_i,
input wire rstn_i,
input wire ctrl_active_i,
input wire ctrl_update_i,
input wire ctrl_arm_i,
input wire cnt_end_i,
input wire [7:0] cfg_sel_i,
input wire cfg_sel_clk_i,
input wire [2:0] cfg_mode_i,
input wire ls_clk_i,
input wire [extsig_num - 1:0] signal_i,
output reg event_o
);
wire s_rise;
wire s_rise_ls_clk;
wire s_fall;
reg s_int_evnt;
wire s_event;
wire r_active;
reg r_event;
reg r_oldval;
reg s_int_sig;
reg [7:0] r_sel;
reg [2:0] r_mode;
reg r_armed;
reg [2:0] r_ls_clk_sync;
assign s_rise = ~r_oldval & s_int_sig;
assign s_fall = r_oldval & ~s_int_sig;
assign s_rise_ls_clk = ~r_ls_clk_sync[2] & r_ls_clk_sync[1];
always @(posedge clk_i or negedge rstn_i) begin : proc_r_ls_clk_sync
if (~rstn_i)
r_ls_clk_sync <= 'h0;
else
r_ls_clk_sync <= {r_ls_clk_sync[1:0], ls_clk_i};
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_mode
if (~rstn_i) begin
r_mode <= 0;
r_sel <= 0;
end else if (ctrl_update_i) begin
r_mode <= cfg_mode_i;
r_sel <= cfg_sel_i;
end
end
always @(*) begin : proc_event_o
if (cfg_sel_clk_i)
event_o = s_int_evnt & s_rise_ls_clk;
else
event_o = s_int_evnt;
end
always @(*) begin : proc_s_int_evnt
case (r_mode)
3'b000: s_int_evnt = 1'b1;
3'b001: s_int_evnt = ~s_int_sig;
3'b010: s_int_evnt = s_int_sig;
3'b011: s_int_evnt = s_rise;
3'b100: s_int_evnt = s_fall;
3'b101: s_int_evnt = s_rise | s_fall;
3'b110:
begin
if (r_armed)
s_int_evnt = (s_rise ? 1'b1 : r_event);
else
s_int_evnt = 1'b0;
end
3'b111:
begin
if (r_armed)
s_int_evnt = (s_fall ? 1'b1 : r_event);
else
s_int_evnt = 1'b0;
end
endcase
end
integer i;
always @(*) begin : proc_int_sig
s_int_sig = 0;
for (i = 0; i < extsig_num; i = i + 1) begin
if (r_sel == i) s_int_sig = signal_i[i];
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_event
if (~rstn_i) begin
r_event <= 1'b0;
r_armed <= 1'b0;
end else begin
if (r_armed)
r_event <= s_int_evnt;
else if (cnt_end_i)
r_event <= 1'b0;
if (ctrl_arm_i)
r_armed <= 1'b1;
else if (cnt_end_i)
r_armed <= 1'b0;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_sync
if (~rstn_i) begin
r_oldval <= 0;
end else if (ctrl_active_i) begin
if (!cfg_sel_clk_i || (cfg_sel_clk_i && s_rise_ls_clk))
r_oldval <= s_int_sig;
end
end
endmodule |
module prescaler (
input wire clk_i,
input wire rstn_i,
input wire ctrl_active_i,
input wire ctrl_update_i,
input wire ctrl_rst_i,
input wire [7:0] cfg_presc_i,
input wire event_i,
output reg event_o
);
reg [7:0] r_presc;
reg [7:0] r_counter;
always @(posedge clk_i or negedge rstn_i) begin : proc_r_presc
if (~rstn_i)
r_presc <= 0;
else if (ctrl_update_i) r_presc <= cfg_presc_i;
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_counter
if (~rstn_i) begin
r_counter <= 0;
event_o <= 0;
end else if (ctrl_rst_i) begin
r_counter <= 0;
event_o <= 0;
end else if (ctrl_active_i) begin
if (event_i) begin
if (r_presc == 0) begin
event_o <= 1'b1;
end else if (r_counter == r_presc) begin
event_o <= 1'b1;
r_counter <= 0;
end else begin
event_o <= 1'b0;
r_counter <= r_counter + 1;
end
end else begin
event_o <= 1'b0;
end
end else begin
r_counter <= 0;
event_o <= 0;
end
end
endmodule |
module timer_cntrl (
input wire clk_i,
input wire rstn_i,
input wire cfg_start_i,
input wire cfg_stop_i,
input wire cfg_rst_i,
input wire cfg_update_i,
input wire cfg_arm_i,
output reg ctrl_cnt_upd_o,
output reg ctrl_all_upd_o,
output wire ctrl_active_o,
output reg ctrl_rst_o,
output wire ctrl_arm_o,
input wire cnt_update_i,
output wire [7:0] status_o
);
reg r_active;
reg r_pending;
assign ctrl_arm_o = cfg_arm_i;
assign status_o = {6'h00, r_pending};
assign ctrl_active_o = r_active;
always @(*) begin : proc_sm
if (cfg_start_i && !r_active) begin
ctrl_rst_o = 1'b1;
ctrl_cnt_upd_o = 1'b1;
ctrl_all_upd_o = 1'b1;
end else begin
ctrl_rst_o = cfg_rst_i;
ctrl_cnt_upd_o = cfg_update_i;
ctrl_all_upd_o = cnt_update_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_active
if (~rstn_i) begin
r_active <= 0;
r_pending <= 0;
end else begin
if (cfg_start_i)
r_active <= 1;
else if (cfg_stop_i)
r_active <= 0;
if (cnt_update_i && !cfg_update_i)
r_pending <= 0;
else if (cfg_update_i)
r_pending <= 1;
end
end
endmodule |
module up_down_counter #(
parameter num_bits = 16
)
(
input wire clk_i,
input wire rstn_i,
input wire cfg_sawtooth_i,
input wire [num_bits - 1:0] cfg_start_i,
input wire [num_bits - 1:0] cfg_end_i,
input wire ctrl_update_i,
input wire ctrl_rst_i,
input wire ctrl_active_i,
input wire counter_event_i,
output wire counter_end_o,
output wire counter_saw_o,
output wire counter_evt_o,
output wire [num_bits - 1:0] counter_o
);
reg [num_bits - 1:0] r_counter;
reg [num_bits - 1:0] r_start;
reg [num_bits - 1:0] r_end;
reg [num_bits - 1:0] s_counter;
reg [num_bits - 1:0] s_start;
reg [num_bits - 1:0] s_end;
reg r_direction; reg r_sawtooth;
reg r_event;
reg s_direction; reg s_sawtooth;
wire s_is_update;
reg s_do_update;
reg s_pending_update;
reg r_pending_update;
assign counter_o = r_counter;
assign counter_saw_o = r_sawtooth;
assign counter_evt_o = ctrl_active_i & r_event;
assign counter_end_o = (ctrl_active_i & r_event) & s_is_update;
assign s_is_update = r_sawtooth ? (r_counter == r_end) : (r_direction && (r_counter == (r_start - 1)));
always @(posedge clk_i or negedge rstn_i) begin : proc_r_event
if (~rstn_i) begin
r_event <= 0;
r_pending_update <= 0;
end else begin
r_pending_update <= s_pending_update;
if (ctrl_active_i)
r_event <= counter_event_i;
end
end
always @(*) begin : proc_s_do_update
s_pending_update = r_pending_update;
s_do_update = 0;
if (ctrl_update_i || r_pending_update) begin
if (ctrl_update_i && !ctrl_active_i) begin
s_pending_update = 0;
s_do_update = 1;
end else if (s_is_update) begin
s_pending_update = 0;
s_do_update = counter_event_i;
end else begin
s_pending_update = 1;
s_do_update = 0;
end
end else if (ctrl_rst_i) begin
s_pending_update = 0;
s_do_update = 1;
end
end
always @(*) begin : proc_s_counter
s_counter = r_counter;
s_start = r_start;
s_sawtooth = r_sawtooth;
s_end = r_end;
s_direction = r_direction;
if (s_do_update) begin
s_counter = cfg_start_i;
s_start = cfg_start_i;
s_sawtooth = cfg_sawtooth_i;
s_end = cfg_end_i;
s_direction = 1'b0;
end else if (counter_event_i && ctrl_active_i) begin
if (!r_direction && (r_counter == r_end)) begin
if (r_sawtooth) begin
s_counter = r_start;
s_direction = 1'b0;
end else begin
s_counter = r_counter - 1;
s_direction = 1'b1;
end
end else if (r_direction && (r_counter == r_start)) begin
s_counter = r_counter + 1;
s_direction = 1'b0;
end else if (r_direction) begin
s_counter = r_counter - 1;
end else begin
s_counter = r_counter + 1;
end
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_counter
if (~rstn_i) begin
r_counter <= 0;
r_start <= 0;
r_end <= 0;
r_direction <= 0;
r_sawtooth <= 1'b1;
end else begin
if (s_do_update || (counter_event_i && ctrl_active_i)) begin
r_counter <= s_counter;
r_direction <= s_direction;
end
if (s_do_update) begin
r_start <= s_start;
r_end <= s_end;
r_sawtooth <= s_sawtooth;
end
end
end
endmodule |
module spi_master_clkgen (
input wire clk,
input wire rstn,
input wire en,
input wire [7:0] clk_div,
input wire clk_div_valid,
output reg spi_clk,
output reg spi_fall,
output reg spi_rise
);
reg [7:0] counter_trgt;
reg [7:0] counter_trgt_next;
reg [7:0] counter;
reg [7:0] counter_next;
reg spi_clk_next;
reg running;
always @(*) begin
spi_rise = 1'b0;
spi_fall = 1'b0;
if (clk_div_valid)
counter_trgt_next = clk_div;
else
counter_trgt_next = counter_trgt;
if (counter == counter_trgt) begin
counter_next = 0;
spi_clk_next = ~spi_clk;
if (spi_clk == 1'b0)
spi_rise = running;
else
spi_fall = running;
end else begin
counter_next = counter + 1;
spi_clk_next = spi_clk;
end
end
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
counter_trgt <= 'h0;
counter <= 'h0;
spi_clk <= 1'b0;
running <= 1'b0;
end else begin
counter_trgt <= counter_trgt_next;
if (!((spi_clk == 1'b0) && ~en)) begin
running <= 1'b1;
spi_clk <= spi_clk_next;
counter <= counter_next;
end else
running <= 1'b0;
end
end
endmodule |
module spi_master_fifo
#(
parameter data_width = 32,
parameter buffer_depth = 2,
parameter log_buffer_depth = `log2(buffer_depth)
)
(
input wire clk_i,
input wire rst_ni,
input wire clr_i,
output wire [log_buffer_depth:0] elements_o,
output wire [data_width - 1:0] data_o,
output wire valid_o,
input wire ready_i,
input wire valid_i,
input wire [data_width - 1:0] data_i,
output wire ready_o
);
reg [log_buffer_depth - 1:0] pointer_in; reg [log_buffer_depth - 1:0] pointer_out; reg [log_buffer_depth:0] elements; reg [data_width - 1:0] buffer [buffer_depth - 1:0];
wire full;
integer loop1;
assign full = (elements == buffer_depth);
assign elements_o = elements;
always @(posedge clk_i or negedge rst_ni) begin : elements_sequential
if (rst_ni == 1'b0)
elements <= 0;
else if (clr_i)
elements <= 0;
else if ((ready_i && valid_o) && (!valid_i || full))
elements <= elements - 1;
else if (((!valid_o || !ready_i) && valid_i) && !full)
elements <= elements + 1;
end
always @(posedge clk_i or negedge rst_ni) begin : buffers_sequential
if (rst_ni == 1'b0) begin
for (loop1 = 0; loop1 < buffer_depth; loop1 = loop1 + 1)
buffer[loop1] <= 0;
end
else if (valid_i && !full)
buffer[pointer_in] <= data_i;
end
always @(posedge clk_i or negedge rst_ni) begin : sequential
if (rst_ni == 1'b0) begin
pointer_out <= 0;
pointer_in <= 0;
end else if (clr_i) begin
pointer_out <= 0;
pointer_in <= 0;
end else begin
if (valid_i && !full) begin
if (pointer_in == $unsigned(buffer_depth - 1))
pointer_in <= 0;
else
pointer_in <= pointer_in + 1;
end
if (ready_i && valid_o) begin
if (pointer_out == $unsigned(buffer_depth - 1))
pointer_out <= 0;
else
pointer_out <= pointer_out + 1;
end
end
end
assign data_o = buffer[pointer_out];
assign valid_o = (elements != 0);
assign ready_o = ~full;
endmodule |
module spi_master_rx (
input wire clk,
input wire rstn,
input wire en,
input wire rx_edge,
output wire rx_done,
input wire sdi0,
input wire sdi1,
input wire sdi2,
input wire sdi3,
input wire en_quad_in,
input wire [15:0] counter_in,
input wire counter_in_upd,
output wire [31:0] data,
input wire data_ready,
output reg data_valid,
output reg clk_en_o
);
localparam [1:0] idle = 0;
localparam [1:0] receive = 1;
localparam [1:0] wait_fifo = 2;
localparam [1:0] wait_fifo_done = 3;
reg [31:0] data_int;
reg [31:0] data_int_next;
reg [15:0] counter;
reg [15:0] counter_trgt;
reg [15:0] counter_next;
reg [15:0] counter_trgt_next;
wire done;
wire reg_done;
reg [1:0] rx_cs;
reg [1:0] rx_ns;
assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
assign data = data_int_next;
assign rx_done = done;
always @(*) begin
if (counter_in_upd)
counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in);
else
counter_trgt_next = counter_trgt;
end
assign done = (counter == (counter_trgt - 1)) && rx_edge;
always @(*) begin
rx_ns = rx_cs;
clk_en_o = 1'b0;
data_int_next = data_int;
data_valid = 1'b0;
counter_next = counter;
case (rx_cs)
idle: begin
clk_en_o = 1'b0;
if (en) rx_ns = receive;
end
receive: begin
clk_en_o = 1'b1;
if (rx_edge) begin
counter_next = counter + 1;
if (en_quad_in)
data_int_next = {data_int[27:0], sdi3, sdi2, sdi1, sdi0};
else
data_int_next = {data_int[30:0], sdi1};
if (rx_done) begin
counter_next = 0;
data_valid = 1'b1;
if (data_ready)
rx_ns = idle;
else
rx_ns = wait_fifo_done;
end else if (reg_done) begin
data_valid = 1'b1;
if (~data_ready) begin
clk_en_o = 1'b0;
rx_ns = wait_fifo;
end
end
end
end
wait_fifo_done: begin
data_valid = 1'b1;
if (data_ready) rx_ns = idle;
end
wait_fifo: begin
data_valid = 1'b1;
if (data_ready) rx_ns = receive;
end
endcase
end
always @(posedge clk or negedge rstn) begin
if (rstn == 0) begin
counter <= 0;
counter_trgt <= 'h8;
data_int <= 'b0;
rx_cs <= idle;
end else begin
counter <= counter_next;
counter_trgt <= counter_trgt_next;
data_int <= data_int_next;
rx_cs <= rx_ns;
end
end
endmodule |
module spi_master_tx (
input wire clk,
input wire rstn,
input wire en,
input wire tx_edge,
output wire tx_done,
output wire sdo0,
output wire sdo1,
output wire sdo2,
output wire sdo3,
input wire en_quad_in,
input wire [15:0] counter_in,
input wire counter_in_upd,
input wire [31:0] data,
input wire data_valid,
output reg data_ready,
output reg clk_en_o
);
localparam [0:0] idle = 0;
localparam [0:0] transmit = 1;
reg [31:0] data_int;
reg [31:0] data_int_next;
reg [15:0] counter;
reg [15:0] counter_trgt;
reg [15:0] counter_next;
reg [15:0] counter_trgt_next;
wire done;
wire reg_done;
reg [0:0] tx_cs;
reg [0:0] tx_ns;
assign sdo0 = (en_quad_in ? data_int[28] : data_int[31]);
assign sdo1 = data_int[29];
assign sdo2 = data_int[30];
assign sdo3 = data_int[31];
assign tx_done = done;
assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
always @(*) begin
if (counter_in_upd)
counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in);
else
counter_trgt_next = counter_trgt;
end
assign done = (counter == (counter_trgt - 1)) && tx_edge;
always @(*) begin
tx_ns = tx_cs;
clk_en_o = 1'b0;
data_int_next = data_int;
data_ready = 1'b0;
counter_next = counter;
case (tx_cs)
idle: begin
clk_en_o = 1'b0;
if (en && data_valid) begin
data_int_next = data;
data_ready = 1'b1;
tx_ns = transmit;
end
end
transmit: begin
clk_en_o = 1'b1;
if (tx_edge) begin
counter_next = counter + 1;
data_int_next = (en_quad_in ? {data_int[27:0], 4'b0000} : {data_int[30:0], 1'b0});
if (tx_done) begin
counter_next = 0;
if (en && data_valid) begin
data_int_next = data;
data_ready = 1'b1;
tx_ns = transmit;
end else begin
clk_en_o = 1'b0;
tx_ns = idle;
end
end else if (reg_done) begin
if (data_valid) begin
data_int_next = data;
data_ready = 1'b1;
end else begin
clk_en_o = 1'b0;
tx_ns = idle;
end
end
end
end
endcase
end
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
counter <= 0;
counter_trgt <= 'h8;
data_int <= 'h0;
tx_cs <= idle;
end else begin
counter <= counter_next;
counter_trgt <= counter_trgt_next;
data_int <= data_int_next;
tx_cs <= tx_ns;
end
end
endmodule |
module io_generic_fifo
#(
parameter data_width = 32,
parameter buffer_depth = 2,
parameter log_buffer_depth = $clog2(buffer_depth)
)
(
input wire clk_i,
input wire rstn_i,
input wire clr_i,
output wire [log_buffer_depth:0] elements_o,
output wire [data_width - 1:0] data_o,
output wire valid_o,
input wire ready_i,
input wire valid_i,
input wire [data_width - 1:0] data_i,
output wire ready_o
);
reg [log_buffer_depth - 1:0] pointer_in; reg [log_buffer_depth - 1:0] pointer_out;
reg [log_buffer_depth:0] elements; reg [data_width - 1:0] buffer [buffer_depth - 1:0];
wire full;
assign full = (elements == buffer_depth);
assign elements_o = elements;
always @(posedge clk_i or negedge rstn_i) begin : elements_sequential
if (rstn_i == 1'b0)
elements <= 0;
else if (clr_i)
elements <= 0;
else if ((ready_i && valid_o) && (!valid_i || full))
elements <= elements - 1;
else if (((!valid_o || !ready_i) && valid_i) && !full)
elements <= elements + 1;
end
integer loop1;
always @(posedge clk_i or negedge rstn_i) begin : buffers_sequential
if (rstn_i == 1'b0) begin
for (loop1 = 0; loop1 < buffer_depth; loop1 = loop1 + 1) begin
buffer[loop1] <= 0;
end
end else if (valid_i && !full) begin
buffer[pointer_in] <= data_i; end
end
always @(posedge clk_i or negedge rstn_i) begin : sequential
if (rstn_i == 1'b0) begin
pointer_out <= 0;
pointer_in <= 0;
end else if (clr_i) begin
pointer_out <= 0;
pointer_in <= 0;
end else begin
if (valid_i && !full) begin
if (pointer_in == $unsigned(buffer_depth - 1))
pointer_in <= 0;
else
pointer_in <= pointer_in + 1;
end
if (ready_i && valid_o) begin
if (pointer_out == $unsigned(buffer_depth - 1))
pointer_out <= 0;
else
pointer_out <= pointer_out + 1;
end
end
end
assign data_o = buffer[pointer_out];
assign valid_o = (elements != 0);
assign ready_o = ~full;
endmodule |
module uart_interrupt
#(
parameter tx_fifo_depth = 32,
parameter rx_fifo_depth = 32
)
(
input wire clk_i,
input wire rstn_i,
input wire [2:0] ier_i,
input wire error_i,
input wire [$clog2(rx_fifo_depth):0] rx_elements_i,
input wire [$clog2(tx_fifo_depth):0] tx_elements_i,
input wire [1:0] trigger_level_i,
input wire [3:0] clr_int_i,
output wire interrupt_o,
output wire [3:0] iir_o
);
reg [3:0] iir_n;
reg [3:0] iir_q;
reg trigger_level_reached;
always @(*) begin
trigger_level_reached = 1'b0;
case (trigger_level_i)
2'b00:
if ($unsigned(rx_elements_i) == 1)
trigger_level_reached = 1'b1;
2'b01:
if ($unsigned(rx_elements_i) == 4)
trigger_level_reached = 1'b1;
2'b10:
if ($unsigned(rx_elements_i) == 8)
trigger_level_reached = 1'b1;
2'b11:
if ($unsigned(rx_elements_i) == 14)
trigger_level_reached = 1'b1;
endcase
end
always @(*) begin
if (clr_int_i == 4'b0) begin
if (ier_i[2] & error_i)
iir_n = 4'b1100;
else if (ier_i[0] & trigger_level_reached)
iir_n = 4'b1000;
else if (ier_i[1] & (tx_elements_i == 0))
iir_n = 4'b0100;
else
iir_n = iir_q;
end else begin
iir_n = iir_q & ~clr_int_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i)
iir_q <= 4'b0;
else
iir_q <= iir_n;
end
assign iir_o = iir_q;
assign interrupt_o = iir_q[2] | iir_q[3];
endmodule |
module uart_tx (
input wire clk_i,
input wire rstn_i,
output reg tx_o,
output wire busy_o,
input wire cfg_en_i,
input wire [15:0] cfg_div_i,
input wire cfg_parity_en_i,
input wire [1:0] cfg_parity_sel_i,
input wire [1:0] cfg_bits_i,
input wire cfg_stop_bits_i,
input wire [7:0] tx_data_i,
input wire tx_valid_i,
output reg tx_ready_o
);
localparam [2:0] idle = 0;
localparam [2:0] start_bit = 1;
localparam [2:0] data = 2;
localparam [2:0] parity = 3;
localparam [2:0] stop_bit_first = 4;
localparam [2:0] stop_bit_last = 5;
reg [2:0] cs,ns;
reg [7:0] reg_data;
reg [7:0] reg_data_next;
reg [2:0] reg_bit_count;
reg [2:0] reg_bit_count_next;
reg [2:0] s_target_bits;
reg parity_bit;
reg parity_bit_next;
reg sampledata;
reg [15:0] baud_cnt;
reg baudgen_en;
reg bit_done;
assign busy_o = (cs != idle);
always @(*) begin
case (cfg_bits_i)
2'b00: s_target_bits = 3'h4;
2'b01: s_target_bits = 3'h5;
2'b10: s_target_bits = 3'h6;
2'b11: s_target_bits = 3'h7;
endcase
end
always @(*) begin
ns = cs;
tx_o = 1'b1;
sampledata = 1'b0;
reg_bit_count_next = reg_bit_count;
reg_data_next = {1'b1, reg_data[7:1]};
tx_ready_o = 1'b0;
baudgen_en = 1'b0;
parity_bit_next = parity_bit;
case (cs)
idle: begin
if (cfg_en_i)
tx_ready_o = 1'b1;
if (tx_valid_i) begin
ns = start_bit;
sampledata = 1'b1;
reg_data_next = tx_data_i;
end
end
start_bit: begin
tx_o = 1'b0;
parity_bit_next = 1'b0;
baudgen_en = 1'b1;
if (bit_done)
ns = data;
end
data: begin
tx_o = reg_data[0];
baudgen_en = 1'b1;
parity_bit_next = parity_bit ^ reg_data[0];
if (bit_done) begin
if (reg_bit_count == s_target_bits) begin
reg_bit_count_next = 'h0;
if (cfg_parity_en_i)
ns = parity;
else
ns = stop_bit_first;
end else begin
reg_bit_count_next = reg_bit_count + 1;
sampledata = 1'b1;
end
end
end
parity: begin
case (cfg_parity_sel_i)
2'b00: tx_o = ~parity_bit;
2'b01: tx_o = parity_bit;
2'b10: tx_o = 1'b0;
2'b11: tx_o = 1'b1;
endcase
baudgen_en = 1'b1;
if (bit_done)
ns = stop_bit_first;
end
stop_bit_first: begin
tx_o = 1'b1;
baudgen_en = 1'b1;
if (bit_done) begin
if (cfg_stop_bits_i)
ns = stop_bit_last;
else
ns = idle;
end
end
stop_bit_last: begin
tx_o = 1'b1;
baudgen_en = 1'b1;
if (bit_done)
ns = idle;
end
default: ns = idle;
endcase
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
cs <= idle;
reg_data <= 8'hff;
reg_bit_count <= 'h0;
parity_bit <= 1'b0;
end else begin
if (bit_done)
parity_bit <= parity_bit_next;
if (sampledata)
reg_data <= reg_data_next;
reg_bit_count <= reg_bit_count_next;
if (cfg_en_i)
cs <= ns;
else
cs <= idle;
end
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end else if (baudgen_en) begin
if (baud_cnt == cfg_div_i) begin
baud_cnt <= 'h0;
bit_done <= 1'b1;
end
else begin
baud_cnt <= baud_cnt + 1;
bit_done <= 1'b0;
end
end else begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end
end
always @(posedge clk_i or negedge rstn_i) begin
if ((tx_valid_i & tx_ready_o) & rstn_i)
$fwrite(32'h80000002, "%c", tx_data_i);
end
endmodule |
module e203_subsys_pll(
input pll_asleep,
input pllrefclk, output plloutclk,
input pll_reset,
input [1:0] pll_od,
input [7:0] pll_m,
input [4:0] pll_n
);
wire pllout;
`ifdef fpga_source assign pllout = pllrefclk;
`else assign pllout = pllrefclk;
`endif
assign plloutclk = pllout;
endmodule |
module \buf ();
wire \$empty_module_filler ;
endmodule |
module ch(ch_y, ch_z, ch_out, ch_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] \$5 ;
wire [31:0] \$7 ;
output [31:0] ch_out;
wire [31:0] ch_out;
input [31:0] ch_x;
wire [31:0] ch_x;
input [31:0] ch_y;
wire [31:0] ch_y;
input [31:0] ch_z;
wire [31:0] ch_z;
assign \$1 = ch_x & ch_y;
assign \$3 = ~ ch_x;
assign \$5 = \$3 & ch_z;
assign \$7 = \$1 ^ \$5 ;
assign ch_out = \$7 ;
endmodule |
module maj(maj_y, maj_z, maj_out, maj_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] \$5 ;
wire [31:0] \$7 ;
wire [31:0] \$9 ;
output [31:0] maj_out;
wire [31:0] maj_out;
input [31:0] maj_x;
wire [31:0] maj_x;
input [31:0] maj_y;
wire [31:0] maj_y;
input [31:0] maj_z;
wire [31:0] maj_z;
assign \$9 = \$5 ^ \$7 ;
assign \$1 = maj_x & maj_y;
assign \$3 = maj_x & maj_z;
assign \$5 = \$1 ^ \$3 ;
assign \$7 = maj_y & maj_z;
assign maj_out = \$9 ;
endmodule |
module rot0(rot0_out, rot0_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] a;
wire [31:0] b;
wire [31:0] c;
output [31:0] rot0_out;
wire [31:0] rot0_out;
input [31:0] rot0_x;
wire [31:0] rot0_x;
assign \$1 = a ^ b;
assign \$3 = \$1 ^ c;
assign rot0_out = \$3 ;
assign c = { rot0_x[21:0], rot0_x[31:22] };
assign b = { rot0_x[12:0], rot0_x[31:13] };
assign a = { rot0_x[1:0], rot0_x[31:2] };
endmodule |
module rot1(rot1_out, rot1_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] a;
wire [31:0] b;
wire [31:0] c;
output [31:0] rot1_out;
wire [31:0] rot1_out;
input [31:0] rot1_x;
wire [31:0] rot1_x;
assign \$1 = a ^ b;
assign \$3 = \$1 ^ c;
assign rot1_out = \$3 ;
assign c = { rot1_x[24:0], rot1_x[31:25] };
assign b = { rot1_x[10:0], rot1_x[31:11] };
assign a = { rot1_x[5:0], rot1_x[31:6] };
endmodule |
module s0(s0_out, s0_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] \$5 ;
wire [31:0] a;
wire [31:0] b;
wire [31:0] c;
output [31:0] s0_out;
wire [31:0] s0_out;
input [31:0] s0_x;
wire [31:0] s0_x;
assign \$3 = a ^ b;
assign \$5 = \$3 ^ c;
assign s0_out = \$5 ;
assign c = \$1 ;
assign b = { s0_x[17:0], s0_x[31:18] };
assign a = { s0_x[6:0], s0_x[31:7] };
assign \$1 = { 3'h0, s0_x[31:3] };
endmodule |
module s1(s1_out, s1_x);
wire [31:0] \$1 ;
wire [31:0] \$3 ;
wire [31:0] \$5 ;
output [31:0] s1_out;
wire [31:0] s1_out;
input [31:0] s1_x;
wire [31:0] s1_x;
assign \$1 = { s1_x[16:0], s1_x[31:17] } ^ { s1_x[18:0], s1_x[31:19] };
assign \$5 = \$1 ^ \$3 ;
assign s1_out = \$5 ;
assign \$3 = { 10'h000, s1_x[31:10] };
endmodule |
module gbsha_top #(parameter n_taps = 1,
bw_in = 6,
bw_product = 12,
bw_out = 8
)
(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
reg coefficient_loaded;
wire signed [bw_in - 1:0] x_in = io_in[bw_in - 1 + 2:2];
wire signed [bw_out - 1:0] y_out;
assign io_out[bw_out - 1:0] = y_out;
if (bw_out < 8)
assign io_out[7:bw_out] = 0;
reg signed [bw_in - 1:0] coefficient;
reg signed [bw_in - 1:0] x;
wire signed [bw_product - 1:0] product;
always @(posedge clk) begin
if (reset) begin
x <= 0;
coefficient <= 0;
coefficient_loaded <= 0;
end else if (!coefficient_loaded) begin
coefficient <= x_in;
coefficient_loaded <= 1;
end else begin
x <= x_in;
end
end
assign product = x * coefficient;
assign y_out = product[bw_out - 1:0];
endmodule |
module pwm (
input [7:0] io_in, output [7:0] io_out );
wire clk = io_in[0]; wire btn_incrpwm = io_in[1]; wire btn_decrpwm = io_in[2]; reg inled; reg deled; reg led; reg clock_1hz; assign io_out[0] = inled; assign io_out[1] = deled; assign io_out[2] = led; assign io_out[3] = clock_1hz;
reg [7:0] duty_cycle = 8'h3f; reg [7:0] count = 8'h00; reg [11:0] bucount = 12'h000; reg [11:0] bdcount = 12'h000; reg debounced_btn_incrpwm; reg debounced_btn_decrpwm;
reg[27:0] counter=28'd0;
parameter divisor = 28'd12500;
always @(posedge clk)
begin
counter <= counter + 28'd1;
if(counter>=(divisor-1))
counter <= 28'd0;
clock_1hz <= (counter<divisor/2)?1'b1:1'b0;
end
always @(posedge clk) begin
if (debounced_btn_incrpwm && (duty_cycle < 8'h7f)) begin
duty_cycle <= duty_cycle + 1; end
else if (debounced_btn_decrpwm && (duty_cycle > 8'h00)) begin
duty_cycle <= duty_cycle - 1; end
count <= count + 1;
if (duty_cycle == 8'h00)begin
deled <= 1'b1;
end
else begin
deled <= 1'b0;
end
if (duty_cycle == 8'h7f)begin
inled <= 1'b1;
end
else begin
inled <= 1'b0;
end
if (count < duty_cycle) begin led <= 1'b1;
end
else begin
led <= 1'b0;
end
if (count == 8'h7f) begin count <= 8'h00; end
end
always @(posedge clk) begin
if (btn_incrpwm == 1'b1) begin
bucount <= bucount + 1; end
else begin
bucount <= 8'h00; end
if (bucount == 12'h1ff) begin
debounced_btn_incrpwm <= 1'b1; end
else begin
debounced_btn_incrpwm <= 1'b0;
end
end
always @(posedge clk) begin
if (btn_decrpwm == 1'b1) begin
bdcount <= bdcount + 1; end
else begin
bdcount <= 8'h00; end
if (bdcount == 12'h1ff) begin
debounced_btn_decrpwm <= 1'b1; end
else begin
debounced_btn_decrpwm<= 1'b0;
end
end
endmodule |
module sirv_expl_apb_slv #(
parameter aw = 32,
parameter dw = 32
)(
input [aw-1:0] apb_paddr,
input apb_pwrite,
input apb_pselx,
input apb_penable,
input [dw-1:0] apb_pwdata,
output [dw-1:0] apb_prdata,
input clk,
input rst_n
);
assign apb_prdata = {dw{1'b0}};
endmodule |
module user_proj_example #(
parameter [31:0] base_address = 32'h03000000, parameter [31:0] key_0_address = base_address,
parameter [31:0] key_1_address = base_address + 4,
parameter [31:0] plain_0_address = base_address + 8,
parameter [31:0] plain_1_address = base_address + 12,
parameter [31:0] cmos_out_0_address = base_address + 16,
parameter [31:0] cmos_out_1_address = base_address + 20,
parameter [31:0] control_0_address = base_address + 24
)(
`ifdef use_power_pins
inout vccd1, inout vssd1, `endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
input [15:0] io_in,
output [15:0] io_out,
output [15:0] io_oeb,
output [2:0] irq
);
wire clk;
wire rst;
wire [15:0] io_in;
wire [15:0] io_out;
wire [15:0] io_oeb;
wire valid;
wire [3:0] wstrb;
wire [31:0] la_write;
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_ack_o = ack_internal;
assign wbs_dat_o = rdata;
assign io_oeb = {(15){rst}};
assign irq = 3'b000;
assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
localparam depth_log2 = 5;
localparam elements = 2**depth_log2;
localparam width = 32;
reg [width-1:0] storage [elements-1:0];
reg ack_internal;
reg [31:0] rdata;
genvar i ;
generate
for (i=0; i<elements; i=i+1) begin
always @(posedge clk) begin
if(rst) begin
storage[i] <= {width{1'b0}};
end
end
end
endgenerate
always @(posedge clk) begin
if(!rst && valid) begin case(wbs_adr_i)
key_0_address, key_1_address,
plain_0_address, plain_1_address,
control_0_address: begin
if (wstrb[0]) storage[wbs_adr_i[depth_log2-1:0]][7:0] <= wbs_dat_i[7:0];
if (wstrb[1]) storage[wbs_adr_i[depth_log2-1:0]][15:8] <= wbs_dat_i[15:8];
if (wstrb[2]) storage[wbs_adr_i[depth_log2-1:0]][23:16] <= wbs_dat_i[23:16];
if (wstrb[3]) storage[wbs_adr_i[depth_log2-1:0]][31:24] <= wbs_dat_i[31:24];
end
endcase
end
end
always @(posedge clk) begin
if(valid && !wbs_we_i) case(wbs_adr_i)
key_0_address, key_1_address,
plain_0_address, plain_1_address,
cmos_out_0_address, cmos_out_1_address,
control_0_address:
rdata <= storage[wbs_adr_i [depth_log2-1:0]];
default:
rdata <= 32'b0;
endcase
end
always @(posedge clk) begin
if(rst)
ack_internal <= 0;
else
ack_internal <= (valid && !ack_internal && ((wbs_adr_i & (width/8 - 1)) == {$clog2(width/8){1'b0}}) && (wbs_adr_i >= base_address) && (wbs_adr_i <= base_address + 24));
end
endmodule |
module wshbone_slave #(
parameter [31:0] base_address = 32'h03000000, parameter [31:0] key_0_address = base_address,
parameter [31:0] key_1_address = base_address + 4,
parameter [31:0] plain_0_address = base_address + 8,
parameter [31:0] plain_1_address = base_address + 12,
parameter [31:0] cmos_out_0_address = base_address + 16,
parameter [31:0] cmos_out_1_address = base_address + 20,
parameter [31:0] control_0_address = base_address + 24 )
(
input wire clk,
input wire reset,
input wire i_wb_cyc, input wire i_wb_stb, input wire i_wb_we, input wire [31:0] i_wb_addr, input wire [31:0] i_wb_data, output reg o_wb_ack, output wire o_wb_stall, output reg [31:0] o_wb_data
);
localparam depth_log2 = 5;
localparam elements = 2**depth_log2;
localparam width = 32;
reg [width-1:0] storage [elements-1:0];
assign o_wb_stall = 0;
genvar i ;
generate
for (i=0; i<elements; i=i+1) begin
always @(posedge clk) begin
if(reset) begin
storage[i] <= {width{1'b0}};
end
end
end
endgenerate
always @(posedge clk) begin
if(!reset && i_wb_stb && i_wb_cyc && i_wb_we && !o_wb_stall) begin
case(i_wb_addr)
key_0_address:
storage[i_wb_addr [depth_log2-1:0]] <= i_wb_data;
key_1_address:
storage[i_wb_addr [depth_log2-1:0]] <= i_wb_data;
plain_0_address:
storage[i_wb_addr [depth_log2-1:0]] <= i_wb_data;
plain_1_address:
storage[i_wb_addr [depth_log2-1:0]] <= i_wb_data;
control_0_address:
storage[i_wb_addr [depth_log2-1:0]] <= i_wb_data;
endcase
end
end
always @(posedge clk) begin
if(i_wb_stb && i_wb_cyc && !i_wb_we && !o_wb_stall)
case(i_wb_addr)
key_0_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
key_1_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
plain_0_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
plain_1_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
cmos_out_0_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
cmos_out_1_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
control_0_address:
o_wb_data <= storage[i_wb_addr [depth_log2-1:0]];
default:
o_wb_data <= 32'b0;
endcase
end
always @(posedge clk) begin
if(reset)
o_wb_ack <= 0;
else
o_wb_ack <= (i_wb_stb && !o_wb_stall && ((i_wb_addr & (width/8 - 1)) == {$clog2(width/8){1'b0}}) && (i_wb_addr >= base_address) && (i_wb_addr <= base_address + 24));
end
`ifdef formal
default clocking @(posedge clk); endclocking
default disable iff (reset);
cyc: assume property (i_wb_cyc |=> i_wb_cyc && o_wb_ack);
write: cover property (##1 $rose(i_wb_stb) |-> ##[+] o_wb_data[3:0] == 4'b1010);
read: cover property (##1 $rose(i_wb_stb) |-> ##[+] leds[7:0] == 8'b11110000);
`endif
endmodule |
module discriminator(rst, edge_count, note, match_exact, match_high, match_far, clk);
reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
wire \$1 ;
wire \$10 ;
wire \$101 ;
wire [4:0] \$12 ;
wire [4:0] \$13 ;
wire \$15 ;
wire \$17 ;
wire [3:0] \$19 ;
wire [3:0] \$20 ;
wire [3:0] \$22 ;
wire [3:0] \$24 ;
wire [3:0] \$26 ;
wire [3:0] \$28 ;
wire \$3 ;
wire [3:0] \$30 ;
wire [3:0] \$32 ;
wire [3:0] \$34 ;
wire [3:0] \$36 ;
wire [3:0] \$38 ;
wire [8:0] \$40 ;
wire [8:0] \$42 ;
wire [8:0] \$44 ;
wire [8:0] \$46 ;
wire [8:0] \$48 ;
wire \$5 ;
wire [8:0] \$50 ;
wire [8:0] \$52 ;
wire [8:0] \$54 ;
wire [8:0] \$56 ;
wire [8:0] \$58 ;
wire [5:0] \$60 ;
wire [5:0] \$62 ;
wire [5:0] \$64 ;
wire [5:0] \$66 ;
wire [5:0] \$68 ;
wire [5:0] \$7 ;
wire [5:0] \$70 ;
wire [5:0] \$72 ;
wire [5:0] \$74 ;
wire [5:0] \$76 ;
wire [5:0] \$78 ;
wire [5:0] \$8 ;
wire \$80 ;
wire [9:0] \$82 ;
wire [9:0] \$83 ;
wire \$85 ;
wire [5:0] \$87 ;
wire [6:0] \$89 ;
wire \$91 ;
wire [5:0] \$93 ;
wire [6:0] \$95 ;
wire \$97 ;
wire [5:0] \$99 ;
input clk;
wire clk;
reg [3:0] curnoteindex = 4'h0;
reg [3:0] \curnoteindex$next ;
(* enum_base_type = "discriminatorstate" *)
(* enum_value_000 = "powerup" *)
(* enum_value_001 = "init" *)
(* enum_value_010 = "calculatedifffromtarget" *)
(* enum_value_011 = "compare" *)
(* enum_value_100 = "movedtonextcheckbounds" *)
(* enum_value_101 = "detectedvalidnote" *)
(* enum_value_110 = "displayresult" *)
reg [2:0] curstate = 3'h0;
reg [2:0] \curstate$next ;
reg [5:0] detectionwindow = 6'h00;
reg [5:0] \detectionwindow$next ;
reg [5:0] detectionwindowmidpoint = 6'h00;
reg [5:0] \detectionwindowmidpoint$next ;
input [7:0] edge_count;
wire [7:0] edge_count;
reg inputfreqhigher = 1'h0;
reg \inputfreqhigher$next ;
output match_exact;
reg match_exact = 1'h0;
reg \match_exact$next ;
output match_far;
reg match_far = 1'h0;
reg \match_far$next ;
output match_high;
reg match_high = 1'h0;
reg \match_high$next ;
reg [4:0] nomatchcount = 5'h00;
reg [4:0] \nomatchcount$next ;
output [3:0] note;
reg [3:0] note = 4'h0;
reg [3:0] \note$next ;
reg [5:0] readingproximityresult = 6'h00;
reg [5:0] \readingproximityresult$next ;
input rst;
wire rst;
reg [8:0] subtractresult = 9'h000;
reg [8:0] \subtractresult$next ;
assign \$101 = readingproximityresult <= \$99 ;
always @(posedge clk)
curstate <= \curstate$next ;
always @(posedge clk)
nomatchcount <= \nomatchcount$next ;
always @(posedge clk)
curnoteindex <= \curnoteindex$next ;
always @(posedge clk)
note <= \note$next ;
always @(posedge clk)
subtractresult <= \subtractresult$next ;
always @(posedge clk)
detectionwindow <= \detectionwindow$next ;
always @(posedge clk)
detectionwindowmidpoint <= \detectionwindowmidpoint$next ;
assign \$10 = subtractresult <= detectionwindow;
always @(posedge clk)
readingproximityresult <= \readingproximityresult$next ;
always @(posedge clk)
inputfreqhigher <= \inputfreqhigher$next ;
always @(posedge clk)
match_exact <= \match_exact$next ;
always @(posedge clk)
match_far <= \match_far$next ;
always @(posedge clk)
match_high <= \match_high$next ;
assign \$13 = curnoteindex + 1'h1;
assign \$15 = nomatchcount == 5'h1f;
assign \$17 = subtractresult <= detectionwindow;
assign \$1 = subtractresult <= detectionwindow;
assign \$3 = curnoteindex < 4'ha;
assign \$40 = 8'hd0 - edge_count;
assign \$42 = 8'haf - edge_count;
assign \$44 = 8'h9c - edge_count;
assign \$46 = 8'h82 - edge_count;
assign \$48 = 8'h74 - edge_count;
assign \$50 = 8'h68 - edge_count;
assign \$52 = 8'h57 - edge_count;
assign \$54 = 8'h4d - edge_count;
assign \$56 = 8'h3a - edge_count;
assign \$58 = 8'h2b - edge_count;
assign \$5 = curnoteindex < 4'ha;
assign \$80 = subtractresult <= detectionwindowmidpoint;
assign \$83 = detectionwindow - subtractresult;
assign \$85 = subtractresult <= detectionwindowmidpoint;
assign \$8 = nomatchcount + 1'h1;
assign \$89 = detectionwindowmidpoint - \$87 ;
assign \$91 = readingproximityresult >= \$89 ;
assign \$95 = detectionwindowmidpoint - \$93 ;
assign \$97 = readingproximityresult >= \$95 ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
(* full_case = 32'd1 *)
casez (curstate)
3'h0:
\curstate$next = 3'h1;
3'h1:
\curstate$next = 3'h2;
3'h2:
\curstate$next = 3'h3;
3'h3:
(* full_case = 32'd1 *)
casez (\$1 )
1'h1:
\curstate$next = 3'h5;
default:
\curstate$next = 3'h4;
endcase
3'h4:
(* full_case = 32'd1 *)
casez (\$3 )
1'h1:
\curstate$next = 3'h2;
default:
\curstate$next = 3'h1;
endcase
3'h5:
\curstate$next = 3'h6;
3'h6:
\curstate$next = 3'h1;
default:
\curstate$next = 3'h0;
endcase
casez (rst)
1'h1:
\curstate$next = 3'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\nomatchcount$next = nomatchcount;
casez (curstate)
3'h0:
\nomatchcount$next = 5'h00;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
(* full_case = 32'd1 *)
casez (\$5 )
1'h1:
;
default:
\nomatchcount$next = \$8 [4:0];
endcase
3'h5:
\nomatchcount$next = 5'h00;
endcase
casez (rst)
1'h1:
\nomatchcount$next = 5'h00;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\match_far$next = match_far;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
;
3'h5:
;
3'h6:
(* full_case = 32'd1 *)
casez (\$97 )
1'h1:
\match_far$next = 1'h0;
default:
(* full_case = 32'd1 *)
casez (\$101 )
1'h1:
\match_far$next = 1'h1;
default:
\match_far$next = 1'h0;
endcase
endcase
endcase
casez (rst)
1'h1:
\match_far$next = 1'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\match_high$next = match_high;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
;
3'h5:
;
3'h6:
\match_high$next = inputfreqhigher;
endcase
casez (rst)
1'h1:
\match_high$next = 1'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\curnoteindex$next = curnoteindex;
casez (curstate)
3'h0:
;
3'h1:
\curnoteindex$next = 4'h0;
3'h2:
;
3'h3:
(* full_case = 32'd1 *)
casez (\$10 )
1'h1:
;
default:
\curnoteindex$next = \$13 [3:0];
endcase
endcase
casez (rst)
1'h1:
\curnoteindex$next = 4'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\note$next = note;
casez (curstate)
3'h0:
;
3'h1:
casez (\$15 )
1'h1:
\note$next = 4'h0;
endcase
3'h2:
;
3'h3:
casez (\$17 )
1'h1:
(* full_case = 32'd1 *)
casez (curnoteindex)
4'h0:
\note$next = \$20 ;
4'h1:
\note$next = \$22 ;
4'h2:
\note$next = \$24 ;
4'h3:
\note$next = \$26 ;
4'h4:
\note$next = \$28 ;
4'h5:
\note$next = \$30 ;
4'h6:
\note$next = \$32 ;
4'h7:
\note$next = \$34 ;
4'h8:
\note$next = \$36 ;
4'h?:
\note$next = \$38 ;
endcase
endcase
endcase
casez (rst)
1'h1:
\note$next = 4'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\subtractresult$next = subtractresult;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
(* full_case = 32'd1 *)
casez (curnoteindex)
4'h0:
\subtractresult$next = \$40 ;
4'h1:
\subtractresult$next = \$42 ;
4'h2:
\subtractresult$next = \$44 ;
4'h3:
\subtractresult$next = \$46 ;
4'h4:
\subtractresult$next = \$48 ;
4'h5:
\subtractresult$next = \$50 ;
4'h6:
\subtractresult$next = \$52 ;
4'h7:
\subtractresult$next = \$54 ;
4'h8:
\subtractresult$next = \$56 ;
4'h?:
\subtractresult$next = \$58 ;
endcase
endcase
casez (rst)
1'h1:
\subtractresult$next = 9'h000;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\detectionwindow$next = detectionwindow;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
(* full_case = 32'd1 *)
casez (curnoteindex)
4'h0:
\detectionwindow$next = 6'h18;
4'h1:
\detectionwindow$next = 6'h14;
4'h2:
\detectionwindow$next = 6'h12;
4'h3:
\detectionwindow$next = 6'h0f;
4'h4:
\detectionwindow$next = 6'h0d;
4'h5:
\detectionwindow$next = 6'h0c;
4'h6:
\detectionwindow$next = 6'h0a;
4'h7:
\detectionwindow$next = 6'h09;
4'h8:
\detectionwindow$next = 6'h06;
4'h?:
\detectionwindow$next = 6'h05;
endcase
endcase
casez (rst)
1'h1:
\detectionwindow$next = 6'h00;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\detectionwindowmidpoint$next = detectionwindowmidpoint;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
(* full_case = 32'd1 *)
casez (curnoteindex)
4'h0:
\detectionwindowmidpoint$next = \$60 ;
4'h1:
\detectionwindowmidpoint$next = \$62 ;
4'h2:
\detectionwindowmidpoint$next = \$64 ;
4'h3:
\detectionwindowmidpoint$next = \$66 ;
4'h4:
\detectionwindowmidpoint$next = \$68 ;
4'h5:
\detectionwindowmidpoint$next = \$70 ;
4'h6:
\detectionwindowmidpoint$next = \$72 ;
4'h7:
\detectionwindowmidpoint$next = \$74 ;
4'h8:
\detectionwindowmidpoint$next = \$76 ;
4'h?:
\detectionwindowmidpoint$next = \$78 ;
endcase
endcase
casez (rst)
1'h1:
\detectionwindowmidpoint$next = 6'h00;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\readingproximityresult$next = readingproximityresult;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
;
3'h5:
(* full_case = 32'd1 *)
casez (\$80 )
1'h1:
\readingproximityresult$next = subtractresult[5:0];
default:
\readingproximityresult$next = \$83 [5:0];
endcase
endcase
casez (rst)
1'h1:
\readingproximityresult$next = 6'h00;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\inputfreqhigher$next = inputfreqhigher;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
;
3'h5:
(* full_case = 32'd1 *)
casez (\$85 )
1'h1:
\inputfreqhigher$next = 1'h1;
default:
\inputfreqhigher$next = 1'h0;
endcase
endcase
casez (rst)
1'h1:
\inputfreqhigher$next = 1'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\match_exact$next = match_exact;
casez (curstate)
3'h0:
;
3'h1:
;
3'h2:
;
3'h3:
;
3'h4:
;
3'h5:
;
3'h6:
(* full_case = 32'd1 *)
casez (\$91 )
1'h1:
\match_exact$next = 1'h1;
default:
\match_exact$next = 1'h0;
endcase
endcase
casez (rst)
1'h1:
\match_exact$next = 1'h0;
endcase
end
assign \$7 = \$8 ;
assign \$12 = \$13 ;
assign \$82 = \$83 ;
assign \$20 = 4'h1;
assign \$22 = 4'h6;
assign \$24 = 4'h5;
assign \$26 = 4'h3;
assign \$28 = 4'h2;
assign \$30 = 4'h1;
assign \$32 = 4'h6;
assign \$34 = 4'h5;
assign \$36 = 4'h2;
assign \$38 = 4'h6;
assign \$60 = 6'h0c;
assign \$62 = 6'h0a;
assign \$64 = 6'h09;
assign \$66 = 6'h07;
assign \$68 = 6'h06;
assign \$70 = 6'h06;
assign \$72 = 6'h05;
assign \$74 = 6'h04;
assign \$76 = 6'h03;
assign \$78 = 6'h02;
assign \$87 = { 4'h0, detectionwindow[5:4] };
assign \$93 = { 4'h0, detectionwindow[5:4] };
assign \$99 = { 1'h0, detectionwindowmidpoint[5:1] };
endmodule |
module ffsync(rst, \input , syncout, clk);
input clk;
wire clk;
input \input ;
wire \input ;
input rst;
wire rst;
reg stage0 = 1'h0;
wire \stage0$next ;
reg stage1 = 1'h0;
wire \stage1$next ;
output syncout;
wire syncout;
always @(posedge clk)
stage0 <= \stage0$next ;
always @(posedge clk)
stage1 <= \stage1$next ;
assign syncout = stage1;
assign \stage1$next = stage0;
assign \stage0$next = \input ;
endmodule |
module notedisplay(rst, value, segments, clk);
reg \$auto$verilog_backend.cc:2083:dump_module$4 = 0;
wire \$1 ;
input clk;
wire clk;
input rst;
wire rst;
output [7:0] segments;
reg [7:0] segments = 8'h00;
reg [7:0] \segments$next ;
input [2:0] value;
wire [2:0] value;
assign \$1 = value < 4'h8;
always @(posedge clk)
segments <= \segments$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
\segments$next = 8'h00;
casez (\$1 )
1'h1:
(* full_case = 32'd1 *)
casez (value)
3'h0:
\segments$next = 8'h02;
3'h1:
\segments$next = 8'hf6;
3'h2:
\segments$next = 8'hee;
3'h3:
\segments$next = 8'h3e;
3'h4:
\segments$next = 8'h9c;
3'h5:
\segments$next = 8'h7a;
3'h6:
\segments$next = 8'h9e;
3'h?:
\segments$next = 8'h8e;
endcase
endcase
casez (rst)
1'h1:
\segments$next = 8'h00;
endcase
end
endmodule |
module proxdisplay(rst, value, segments, clk);
reg \$auto$verilog_backend.cc:2083:dump_module$5 = 0;
wire \$1 ;
input clk;
wire clk;
input rst;
wire rst;
output [7:0] segments;
reg [7:0] segments = 8'h00;
reg [7:0] \segments$next ;
input [2:0] value;
wire [2:0] value;
assign \$1 = value < 4'h8;
always @(posedge clk)
segments <= \segments$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
\segments$next = 8'h00;
casez (\$1 )
1'h1:
(* full_case = 32'd1 *)
casez (value)
3'h0:
\segments$next = 8'h2a;
3'h1:
\segments$next = 8'h01;
3'h2:
\segments$next = 8'h46;
3'h3:
\segments$next = 8'h01;
3'h4:
\segments$next = 8'h38;
3'h5:
\segments$next = 8'h01;
3'h6:
\segments$next = 8'hc4;
3'h?:
\segments$next = 8'h01;
endcase
endcase
casez (rst)
1'h1:
\segments$next = 8'h00;
endcase
end
endmodule |
module ram(
input csn,
input clk,
inout io0,
inout io1,
inout io2,
inout io3
);
reg [7:0] memory [16*1024*1024-1:0];
wire [7:0] test_val = memory[200];
reg [3:0] output_enables = 4'h0;
reg [3:0] out_vals = 4'h0;
reg [7:0] dout = 0;
reg [3:0] step_counter = 0;
reg [7:0] din = 0;
reg [7:0] cmd = 0;
reg has_cmd = 0;
reg quad_mode = 0;
reg [1:0] address_step = 0;
reg [23:0] address = 0;
reg [3:0] delay_steps = 0;
assign io0 = output_enables[0] ? out_vals[0] : 1'bz;
assign io1 = output_enables[1] ? out_vals[1] : 1'bz;
assign io2 = output_enables[2] ? out_vals[2] : 1'bz;
assign io3 = output_enables[3] ? out_vals[3] : 1'bz;
always @(posedge csn) begin
if(cmd == 8'h35) begin
quad_mode <= 1;
end else if(cmd == 8'hf5) begin
quad_mode <= 0;
end
delay_steps <= 0;
address <= 0;
address_step <= 0;
has_cmd <= 0;
step_counter <= 0;
cmd <= 0;
din <= 0;
output_enables <= 4'h0;
out_vals <= 4'h0;
end
always @(posedge clk) begin
if(!csn) begin
if(delay_steps > 0) begin
delay_steps <= delay_steps - 1;
end else begin
if(cmd != 8'heb || address_step != 0) begin
step_counter <= step_counter + 1;
if(quad_mode) begin
case(step_counter)
0: din[7:4] <= {io3, io2, io1, io0};
1: din[3:0] <= {io3, io2, io1, io0};
endcase
end else begin
din <= {din[6:0], io0};
end
end
end
end
end
always @(negedge clk) begin
if(delay_steps == 0) begin
if(cmd == 8'heb && address_step == 0) begin
step_counter <= step_counter + 1;
if(quad_mode) begin
out_vals <= dout[7:4];
dout <= {dout[3:0], 4'h0};
end else begin
out_vals <= {2'b00, dout[7], 1'b0};
dout <= {dout[6:0], 1'b0};
end
end
if((quad_mode && step_counter == 2) || (!quad_mode && step_counter == 8)) begin
step_counter <= 0;
if(cmd == 8'heb && address_step == 0) begin
output_enables <= quad_mode ? 4'hf : 4'b0010;
address <= address + 1;
dout <= memory[address];
end else begin
if(!has_cmd) begin
has_cmd <= 1;
cmd <= din;
if(quad_mode && din == 8'heb) begin
address_step <= 1;
end else if(quad_mode && din == 8'h38) begin
address_step <= 1;
end
end else if(address_step != 0) begin
address_step <= address_step + 1;
address = {address[15:0], din};
if(address_step == 3 && cmd == 8'heb) begin
delay_steps <= 3;
end
end else if(cmd == 8'h38) begin
address <= address + 1;
memory[address] <= din;
end
end
end
end
end
endmodule |
module spi(
input [7:0] divisor,
input [7:0] din,
output reg [7:0] dout,
output reg sclk,
output reg do,
input di,
input start,
output reg busy,
input clk,
input rst
);
reg [7:0] data_out_buff;
reg [7:0] data_in_buff;
reg [7:0] div_counter;
reg [4:0] counter;
always @(posedge clk) begin
if(rst) begin
counter <= 5'b11111;
dout <= 0;
end else begin
if(start) begin
counter <= 5'b10000;
div_counter <= 0;
data_out_buff <= din;
data_in_buff <= 1;
sclk <= 0;
end
if(counter != 5'b11111) begin
busy <= 1;
div_counter <= div_counter + 1;
if(div_counter == divisor) begin
div_counter <= 0;
counter <= counter - 1;
if(!counter[0]) begin
do <= data_out_buff[7];
data_out_buff <= {data_out_buff[6:0], 1'b0};
sclk <= 0;
end else begin
sclk <= 1;
data_in_buff <= {data_in_buff[6:0], di};
end
end
end else begin
sclk <= 0;
do <= 0;
busy <= 0;
dout <= data_in_buff;
end
end
end
endmodule |
module uart(
input [15:0] divisor,
input [7:0] din,
output reg [7:0] dout,
output reg tx,
input rx,
input start,
output reg busy,
output reg has_byte,
input clr_hb,
input clk,
input rst
);
reg [9:0] data_buff;
reg [15:0] div_counter;
reg [3:0] counter;
reg receiving;
reg [7:0] receive_buff;
reg [3:0] receive_counter;
reg [15:0] receive_div_counter;
`ifdef sim
wire txclk = div_counter == divisor;
wire rxclk = receive_div_counter == divisor;
`endif
always @(posedge clk) begin
if(rst) begin
tx <= 1;
busy <= 0;
counter <= 0;
div_counter <= 0;
receive_div_counter <= 0;
receiving <= 0;
dout <= 0;
has_byte <= 0;
end else begin
if(clr_hb) begin
has_byte <= 0;
end
if(start) begin
counter <= 4'b1010;
div_counter <= 0;
data_buff <= {1'b1, din, 1'b0};
end
if(counter != 0) begin
busy <= 1;
div_counter <= div_counter + 1;
if(div_counter == divisor) begin
div_counter <= 0;
counter <= counter - 1;
tx <= data_buff[0];
data_buff <= {1'b0, data_buff[9:1]};
end
end else begin
tx <= 1;
busy <= 0;
end
if(!receiving && !rx) begin
receiving <= 1;
receive_counter <= 4'b1000;
receive_buff <= 0;
receive_div_counter <= 0;
end
if(receiving) begin
receive_div_counter <= receive_div_counter + 1;
if(receive_div_counter == divisor) begin
receive_div_counter <= 0;
receive_counter <= receive_counter - 1;
if(receive_counter == 0) begin
receiving <= 0;
dout <= receive_buff;
has_byte <= 1;
end else begin
receive_buff <= {rx, receive_buff[7:1]};
end
end
end
end
end
endmodule |
module w25q128jvxim (csn, clk, dio, do, wpn, holdn);
input csn, clk;
inout dio;
inout wpn;
inout holdn;
inout do;
parameter num_pages = 65536;
parameter num_sec_pages = 3;
parameter pagesize = 256;
parameter sectorsize = 4096;
parameter halfblocksize = 32768;
parameter blocksize = 65536;
parameter num_blocks = num_pages * pagesize / blocksize;
parameter num_lockbits = num_blocks - 2 + 32;
parameter manufacturer = 8'hef;
parameter device_id = 8'h17;
parameter jedec_id_hi = 8'h70;
parameter jedec_id_lo = 8'h18;
parameter unique_id = 64'h0102030405060708;
parameter address_mask = (num_pages * pagesize) - 1;
`define mem_filename "spiflash/testpgm.txt" `define secsi_filename "spiflash/secsi.hex"
`define sfdp_filename "spiflash/sfdp.hex"
`define sreg_filename "spiflash/sreg.hex"
reg [7:0] memory [0:(num_pages * pagesize) - 1]; reg [7:0] page_latch [0:pagesize-1]; reg [7:0] secsi[0:(num_sec_pages * (sectorsize/pagesize) * pagesize) - 1]; reg [7:0] sfdp[0:pagesize]; reg lock_array[0:num_lockbits-1];
reg [23:0] status_reg; reg [23:0] status_reg_shadow; reg status_reg_otp [23:0]; reg [23:0] byte_address; reg [23:0] prog_byte_address; reg [7:0] mode_reg; reg [7:0] wrap_reg; reg [7:0] read_param_reg; reg [7:0] read_param_reg_shadow;
reg flag_prog_page; reg flag_prog_secsi_page; reg flag_erase_sector; reg flag_erase_secsi_sector;
reg flag_erase_half_block; reg flag_erase_block; reg flag_erase_bulk; reg flag_power_up_exec;
reg flag_power_down;
reg flag_power_up_sig_read;
reg flag_write_status_reg;
reg flag_suspend; reg flag_resume; reg flag_suspend_enabled; reg flag_slow_read_reg;
wire flag_slow_read = flag_slow_read_reg;
reg flag_volatile_sr_write; reg flag_read_op_reg;
wire #1 flag_read_op = flag_read_op_reg; reg flag_qpi_mode; reg flag_enable_reset; reg flag_reset; reg flag_reset_condition; reg flag_set_read_param;
reg timing_error;
reg [7:0] in_byte; reg [7:0] out_byte;
reg wpn_reg, wpn_output_enable_reg;
wire wpn_output_enable = wpn_output_enable_reg;
reg holdn_reg, holdn_output_enable;
reg do_reg, do_output_enable, temp_do_output_enable;
reg dio_reg, dio_output_enable_reg, temp_dio_output_enable_reg;
wire dio_output_enable = dio_output_enable_reg;
reg holdn_active;
reg [7:0] cmd_byte;
reg [7:0] null_reg;
reg [7:0] temp;
integer x;
integer fileno;
reg [15:0] file_sector;
reg [15:0] file_length;
`define cmd_write_disable 8'h04
`define cmd_write_enable 8'h06
`define cmd_read_status 8'h05
`define cmd_write_status 8'h01
`define cmd_read_status2 8'h35
`define cmd_write_status2 8'h31
`define cmd_read_status3 8'h15
`define cmd_write_status3 8'h11
`define cmd_read_data 8'h03
`define cmd_read_data_fast 8'h0b
`define cmd_read_data_fast_wrap 8'h0c
`define cmd_read_data_fast_dtr 8'h0d
`define cmd_read_data_fast_dtr_wrap 8'h0e
`define cmd_read_data_fast_dual 8'h3b
`define cmd_read_data_fast_dual_io 8'hbb
`define cmd_read_data_fast_dual_io_dtr 8'hbd
`define cmd_read_data_fast_quad 8'h6b
`define cmd_read_data_fast_quad_io 8'heb
`define cmd_read_data_fast_quad_io_dtr 8'hed
`define cmd_page_program 8'h02
`define cmd_page_program_quad 8'h32
`define cmd_block_erase 8'hd8
`define cmd_half_block_erase 8'h52
`define cmd_sector_erase 8'h20
`define cmd_bulk_erase 8'hc7
`define cmd_bulk_erase2 8'h60
`define cmd_deep_powerdown 8'hb9
`define cmd_read_signature 8'hab
`define cmd_read_id 8'h90
`define cmd_read_id_dual 8'h92
`define cmd_read_id_quad 8'h94
`define cmd_read_jedec_id 8'h9f
`define cmd_read_unique_id 8'h4b
`define cmd_suspend 8'h75
`define cmd_resume 8'h7a
`define cmd_set_burst_wrap 8'h77
`define cmd_mode_reset 8'hff
`define cmd_disable_qpi 8'hff
`define cmd_enable_qpi 8'h38
`define cmd_enable_reset 8'h66
`define cmd_chip_reset 8'h99
`define cmd_set_read_param 8'hc0
`define cmd_sreg_program 8'h42
`define cmd_sreg_erase 8'h44
`define cmd_sreg_read 8'h48
`define cmd_write_enable_vsr 8'h50
`define cmd_read_sfdp 8'h5a
`define cmd_individual_lock 8'h36
`define cmd_individual_unlock 8'h39
`define cmd_read_block_lock 8'h3d
`define cmd_global_block_lock 8'h7e
`define cmd_global_block_unlock 8'h98
`define status_hld_rst 24'h800000
`define status_drv1 24'h400000
`define status_drv0 24'h200000
`define status_wps 24'h040000
`define status_sus 24'h008000
`define status_cmp 24'h004000
`define status_lb3 24'h002000
`define status_lb2 24'h001000
`define status_lb1 24'h000800
`define status_qe 24'h000200
`define status_srl 24'h000100
`define status_srp 24'h000080
`define status_sec 24'h000040
`define status_tb 24'h000020
`define status_bp2 24'h000010
`define status_bp1 24'h000008
`define status_bp0 24'h000004
`define status_wel 24'h000002
`define status_wip 24'h000001
`define hld_rst 23
`define drv1 22
`define drv0 21
`define wps 18
`define sus 15
`define cmpb 14
`define lb3 13
`define lb2 12
`define lb1 11
`define qe 9
`define srl 8
`define srp 7
`define sec 6
`define tb 5
`define bp2 4
`define bp1 3
`define bp0 2
`define wel 1
`define wip 0
wire flag_quad_mode = status_reg[`qe];
wire flag_quad_mode_cs = !flag_quad_mode & !csn;
specify
specparam treset_suspend_max = 1000;
specparam tslch = 5;
$setup(negedge csn, posedge clk, tslch, timing_error);
specparam tchsl = 5;
$setup(posedge clk, negedge csn, tchsl, timing_error);
specparam tshsl_r = 10;
specparam tshsl_w = 50;
$width(posedge csn &&& flag_read_op, tshsl_r, 0, timing_error);
$width(posedge csn &&& (~flag_read_op), tshsl_w, 0, timing_error);
specparam tchsh = 5;
$setup(posedge clk, posedge csn, tchsh, timing_error);
specparam tshch = 5;
$setup(posedge csn, posedge clk, tshch, timing_error);
specparam tcyc = 10; specparam tclh = 4; specparam tcll = 4; $period(posedge clk &&& (~flag_slow_read), tcyc, timing_error);
$width(posedge clk &&& (~flag_slow_read), tclh, 0, timing_error);
$width(negedge clk &&& (~flag_slow_read), tcll, 0, timing_error);
specparam tcycr = 20; specparam tcrlh = 8; specparam tcrll = 8; $period(posedge clk &&& (flag_slow_read), tcycr, timing_error);
$width(posedge clk &&& (flag_slow_read), tcrlh, 0, timing_error);
$width(negedge clk &&& (flag_slow_read), tcrll, 0, timing_error);
specparam tdvch = 2; specparam tchdx = 5;
$setup(dio, posedge clk &&& (~dio_output_enable), tdvch, timing_error);
$hold(posedge clk, dio &&& (~dio_output_enable), tchdx, timing_error);
specparam twhsl = 20;
specparam tshwl = 100;
specparam thlqz = 12;
specparam thhqx = 7;
specparam tsus = 20000;
specparam tchhl = 5;
$setup(posedge clk, negedge holdn &&& (flag_quad_mode_cs),tchhl, timing_error);
specparam thlch = 5; $hold(posedge clk, negedge holdn &&& (flag_quad_mode_cs),thlch, timing_error);
specparam tchhh = 5;
$setup(posedge clk, posedge holdn &&& (flag_quad_mode_cs),tchhh, timing_error);
specparam thhch = 5;
$hold(posedge clk, posedge holdn &&& (flag_quad_mode_cs), thhch, timing_error);
endspecify
parameter tclqv = 7; parameter tshqz = 7; parameter tw = 1000; parameter tres1 = 30000; parameter tres2 = 30000; parameter tdp = 3000; parameter tpp = 700000; parameter tse = 30000000; parameter tbe1 = 120000000; parameter tbe2 = 150000000; parameter tce_40 = 1000000000;
initial
begin :initialization
$readmemh(`mem_filename,memory);
$readmemh(`secsi_filename,secsi);
$readmemh(`sfdp_filename,sfdp);
$readmemh(`sreg_filename,status_reg_otp);
chip_reset();
end
assign dio = dio_output_enable_reg ? dio_reg : 1'bz;
assign do = do_output_enable ? do_reg : 1'bz;
assign wpn = wpn_output_enable_reg ? wpn_reg : 1'bz;
assign holdn = holdn_output_enable ? holdn_reg : 1'bz;
always @(negedge csn) begin :read_opcode
flag_read_op_reg = 1'b1;
mode_reg = mode_reg & 8'hf0;
if((mode_reg & 8'h30) != 8'h20) input_byte(cmd_byte);
if(!is_qpi(cmd_byte))
begin
$display("warning: non-qpi command was executed in qpi mode");
$stop;
end
if(cmd_byte != `cmd_chip_reset)
flag_enable_reset = 0;
case (cmd_byte)
`cmd_set_read_param :
begin
if(!status_reg[`wip] && !flag_power_down && flag_qpi_mode)
begin
input_byte(read_param_reg_shadow);
flag_set_read_param = 1;
get_posclk_holdn;
flag_set_read_param = 0;
end
end
`cmd_enable_qpi :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
if(status_reg[`qe] == 1)
flag_qpi_mode = 1;
end
end
`cmd_mode_reset :
begin
if(!flag_power_down)
flag_qpi_mode = 0;
end
`cmd_enable_reset : begin
flag_enable_reset = 1;
end
`cmd_chip_reset :
begin
if(flag_enable_reset == 1)
begin
flag_reset = 1;
@(posedge clk);
flag_reset = 0;
end
end
`cmd_deep_powerdown :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
flag_power_down = 1;
@(posedge clk);
flag_power_down = 0;
end
end
`cmd_read_signature :
begin
if(!status_reg[`wip])
begin
flag_power_up_exec = 1;
input_byte(null_reg);
input_byte(null_reg);
input_byte(null_reg);
forever
begin
output_byte(device_id);
flag_power_up_sig_read = 1;
end
end
end
`cmd_read_jedec_id :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
output_byte(manufacturer);
output_byte(jedec_id_hi);
output_byte(jedec_id_lo);
end
end
`cmd_read_id :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
byte_address = 0;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
forever
begin
if(byte_address[0])
begin
output_byte(device_id);
output_byte(manufacturer);
end
else
begin
output_byte(manufacturer);
output_byte(device_id);
end
end
end
end
`cmd_read_id_dual :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
byte_address = 0;
input_byte_dual(byte_address[23:16]);
input_byte_dual(byte_address[15:8]);
input_byte_dual(byte_address[7:0]);
input_byte_dual(mode_reg[7:0]);
forever
begin
if(byte_address[0])
begin
output_byte_dual(device_id);
output_byte_dual(manufacturer);
end
else
begin
output_byte_dual(manufacturer);
output_byte_dual(device_id);
end
end
end
end
`cmd_read_id_quad :
begin
if(!status_reg[`wip] && !flag_power_down && status_reg[`qe])
begin
byte_address = 0;
input_byte_quad(byte_address[23:16]);
input_byte_quad(byte_address[15:8]);
input_byte_quad(byte_address[7:0]);
input_byte_quad(mode_reg[7:0]);
input_byte_quad(temp[7:0]);
input_byte_quad(temp[7:0]);
forever
begin
if(byte_address[0])
begin
output_byte_quad(device_id);
output_byte_quad(manufacturer);
end
else
begin
output_byte_quad(manufacturer);
output_byte_quad(device_id);
end
end
end
end
`cmd_read_unique_id :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte(null_reg);
input_byte(null_reg);
input_byte(null_reg);
input_byte(null_reg);
output_byte(unique_id[63:56]);
output_byte(unique_id[55:48]);
output_byte(unique_id[47:40]);
output_byte(unique_id[39:32]);
output_byte(unique_id[31:24]);
output_byte(unique_id[23:16]);
output_byte(unique_id[15:8]);
output_byte(unique_id[7:0]);
end
end
`cmd_write_enable :
begin
if((!flag_power_down) && (wpn || status_reg[`qe]))
status_reg[`wel] = 1;
end
`cmd_write_enable_vsr :
begin
if(!flag_power_down)
flag_volatile_sr_write = 1;
end
`cmd_write_disable :
begin
if(!flag_power_down)
status_reg[`wel] = 0;
end
`cmd_read_status :
begin
if(!flag_power_down)
begin
forever
begin
output_byte(status_reg[7:0]);
end
end
end
`cmd_read_status2 :
begin
if(!flag_power_down)
begin
forever
begin
output_byte(status_reg[15:8]);
end
end
end
`cmd_read_status3 :
begin
if(!flag_power_down)
begin
forever
begin
output_byte(status_reg[23:16]);
end
end
end
`cmd_write_status :
begin
if(!status_reg[`wip] && (status_reg[`wel] || flag_volatile_sr_write) && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
case ({status_reg[`srl],status_reg[`srp]})
2'b00, 2'b01 :
begin
if((status_reg[`srp] && wpn) || !status_reg[`srp] || status_reg[`qe])
begin
status_reg_shadow[23:8] = status_reg[23:8];
input_byte(status_reg_shadow[7:0]);
flag_write_status_reg = 1;
if(flag_qpi_mode == 1)
@(posedge clk);
else
get_posclk_holdn; flag_write_status_reg = 0;
input_byte_no1stclock(temp);
flag_write_status_reg = 1;
status_reg_shadow[15:8] = temp;
if(flag_qpi_mode == 1)
@(posedge clk);
else
get_posclk_holdn; flag_write_status_reg = 0;
end
end
endcase
end
end
`cmd_write_status2 :
begin
if(!status_reg[`wip] && (status_reg[`wel] || flag_volatile_sr_write) && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
case ({status_reg[`srl],status_reg[`srp]})
2'b00, 2'b01 :
begin
if((status_reg[`srp] && wpn) || !status_reg[`srp] || status_reg[`qe])
begin
status_reg_shadow[23:16] = status_reg[23:16];
status_reg_shadow[7:0] = status_reg[7:0];
input_byte(status_reg_shadow[15:8]);
flag_write_status_reg = 1;
if(flag_qpi_mode == 1)
@(posedge clk);
else
get_posclk_holdn; flag_write_status_reg = 0;
end
end
endcase
end
end
`cmd_write_status3 :
begin
if(!status_reg[`wip] && (status_reg[`wel] || flag_volatile_sr_write) && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
case ({status_reg[`srl],status_reg[`srp]})
2'b00, 2'b01 :
begin
if((status_reg[`srp] && wpn) || !status_reg[`srp] || status_reg[`qe])
begin
status_reg_shadow[15:0] = status_reg[15:0];
input_byte(status_reg_shadow[23:16]);
flag_write_status_reg = 1;
if(flag_qpi_mode == 1)
@(posedge clk);
else
get_posclk_holdn; flag_write_status_reg = 0;
end
end
endcase
end
end
`cmd_page_program :
begin
if(status_reg[`wel] && !status_reg[`sus] && !flag_power_down)
begin
flag_read_op_reg = 1'b0;
write_page(0);
end
end
`cmd_page_program_quad :
begin
if(status_reg[`wel]&& !status_reg[`sus] && status_reg[`qe] && !flag_power_down)
begin
flag_read_op_reg = 1'b0;
write_page(1);
end
end
`cmd_suspend :
begin
if(!flag_power_down && !flag_erase_bulk)
begin
if((!flag_suspend) && (flag_erase_sector || flag_erase_secsi_sector || flag_erase_half_block || flag_erase_block || flag_prog_page || flag_prog_secsi_page))
begin
flag_suspend = 1'b1;
get_posclk_holdn; flag_suspend = 1'b0;
end
end
end
`cmd_resume :
begin
if(!flag_power_down)
begin
if(flag_suspend)
begin
flag_resume = 1'b1;
get_posclk_holdn; flag_resume = 1'b0;
end
end
end
`cmd_sector_erase :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
if(!write_protected(byte_address))
begin
flag_erase_sector = 1;
get_posclk_holdn; flag_erase_sector = 0;
end
end
end
`cmd_half_block_erase :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
if(!write_protected(byte_address))
begin
flag_erase_half_block = 1;
get_posclk_holdn; flag_erase_half_block = 0;
end
end
end
`cmd_block_erase :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
if(!write_protected(byte_address))
begin
flag_erase_block = 1;
get_posclk_holdn; flag_erase_block = 0;
end
end
end
`cmd_bulk_erase, `cmd_bulk_erase2 :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
case ({status_reg[`bp0],status_reg[`bp1]})
2'b00 :
begin
flag_erase_bulk = 1;
get_posclk_holdn;
flag_erase_bulk = 0;
end
endcase
end
end
`cmd_read_data :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
flag_slow_read_reg = 1'b1;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
forever
begin
byte_address = byte_address & address_mask;
output_byte(memory[byte_address]);
byte_address = byte_address + 1;
end
end
end
`cmd_read_data_fast :
begin
if(!flag_power_down)
read_page(1,0);
end
`cmd_read_data_fast_dtr :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte_dtr(byte_address[23:16]);
input_byte_dtr(byte_address[15:8]);
input_byte_dtr(byte_address[7:0]);
for(x = 5; x >= 0; x=x-1)
begin
get_posclk_holdn;
null_reg[x] = dio;
end
forever
begin
byte_address = byte_address & address_mask;
output_byte_dtr(memory[byte_address]);
byte_address = byte_address + 1;
end
end
end
`cmd_read_data_fast_dual_io_dtr :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte_dual_dtr(byte_address[23:16]);
input_byte_dual_dtr(byte_address[15:8]);
input_byte_dual_dtr(byte_address[7:0]);
input_byte_dual_dtr(mode_reg[7:0]);
for(x = 3; x >= 0; x=x-1)
begin
get_posclk_holdn;
null_reg[x] = dio;
end
forever
begin
byte_address = byte_address & address_mask;
output_byte_dual_dtr(memory[byte_address]);
byte_address = byte_address + 1;
end
end
end
`cmd_read_data_fast_quad_io_dtr :
begin
if(!status_reg[`wip] && !flag_power_down && status_reg[`qe])
begin
input_byte_quad_dtr(byte_address[23:16]);
input_byte_quad_dtr(byte_address[15:8]);
input_byte_quad_dtr(byte_address[7:0]);
input_byte_quad_dtr(mode_reg[7:0]);
for(x = 6; x >= 0; x=x-1)
begin
get_posclk_holdn;
null_reg[x] = dio;
end
forever
begin
byte_address = byte_address & address_mask;
output_byte_quad_dtr(memory[byte_address]);
byte_address = byte_address + 1;
end
end
end
`cmd_read_data_fast_dtr_wrap :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte_quad_dtr(byte_address[23:16]);
input_byte_quad_dtr(byte_address[15:8]);
input_byte_quad_dtr(byte_address[7:0]);
input_byte_quad_dtr(null_reg);
forever
begin
byte_address = byte_address & address_mask;
output_byte_quad_dtr(memory[byte_address]);
case ({read_param_reg[1],read_param_reg[0]})
2'b00 :
byte_address[2:0] = byte_address[2:0] + 1;
2'b01 :
byte_address[3:0] = byte_address[3:0] + 1;
2'b10 :
byte_address[4:0] = byte_address[4:0] + 1;
2'b11 :
byte_address[5:0] = byte_address[5:0] + 1;
endcase
end
end
end
`cmd_read_data_fast_wrap :
begin
if(!flag_power_down)
begin
if(flag_qpi_mode)
read_page_quadio(cmd_byte);
end
end
`cmd_read_data_fast_dual :
begin
if(!flag_power_down)
read_page(2,0);
end
`cmd_read_data_fast_quad :
begin
if(!flag_power_down && status_reg[`qe])
read_page(3,0);
end
`cmd_read_data_fast_dual_io :
begin
if(!flag_power_down)
read_page_dualio;
end
`cmd_read_data_fast_quad_io :
begin
if(!flag_power_down && status_reg[`qe])
read_page_quadio(cmd_byte);
end
`cmd_set_burst_wrap :
begin
if(!status_reg[`wip] && !flag_power_down && status_reg[`qe])
begin
input_byte_quad(temp[7:0]);
input_byte_quad(temp[7:0]);
input_byte_quad(temp[7:0]);
input_byte_quad(wrap_reg[7:0]);
end
end
`cmd_read_sfdp :
begin
if(!flag_power_down)
begin
flag_slow_read_reg = 1'b1;
read_page(0,2);
end
end
`cmd_sreg_read :
begin
if(!flag_power_down)
begin
read_page(0,1);
end
end
`cmd_sreg_erase :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
case (byte_address[23:8])
16'h10 :
begin
if(!status_reg[`lb1])
begin
flag_erase_secsi_sector = 1;
get_posclk_holdn;
flag_erase_secsi_sector = 0;
end
end
16'h20 :
begin
if(!status_reg[`lb2])
begin
flag_erase_secsi_sector = 1;
get_posclk_holdn;
flag_erase_secsi_sector = 0;
end
end
16'h30 :
begin
if(!status_reg[`lb3])
begin
flag_erase_secsi_sector = 1;
get_posclk_holdn;
flag_erase_secsi_sector = 0;
end
end
endcase
end
end
`cmd_sreg_program :
begin
if(status_reg[`wel] && !flag_power_down && !status_reg[`sus])
begin
flag_read_op_reg = 1'b0;
begin
if(!status_reg[`wip])
begin
input_byte(prog_byte_address[23:16]);
input_byte(prog_byte_address[15:8]);
input_byte(prog_byte_address[7:0]);
case (byte_address[23:8])
16'h10 :
if(!status_reg[`lb1])
fill_page_latch(0,prog_byte_address,1);
16'h20 :
if(!status_reg[`lb2])
fill_page_latch(0,prog_byte_address,1);
16'h30 :
if(!status_reg[`lb3])
fill_page_latch(0,prog_byte_address,1);
endcase
end
end
end
end
`cmd_global_block_lock :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
for(x = 0; x < num_lockbits; x=x+1)
lock_array[x] = 1;
end
end
`cmd_global_block_unlock :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
for(x = 0; x < num_lockbits; x=x+1)
lock_array[x] = 0;
end
end
`cmd_individual_lock :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
lock_array[lockbit_index(byte_address)] = 1;
end
end
`cmd_individual_unlock :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
lock_array[lockbit_index(byte_address)] = 0;
end
end
`cmd_read_block_lock :
begin
if(!status_reg[`wip] && !flag_power_down)
begin
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
null_reg[7:1] = 0;
null_reg[0] = lock_array[lockbit_index(byte_address)];
output_byte(null_reg);
end
end
default :
begin
$display("invalid opcode. (%0h)",cmd_byte);
$stop;
end
endcase
end
always @(posedge csn) begin :disable_interface
#tshqz; holdn_active = 1'b0; do_output_enable = 1'b0; dio_output_enable_reg = 1'b0; wpn_output_enable_reg = 1'b0; holdn_output_enable = 1'b0; flag_slow_read_reg = 1'b0;
disable input_byte;
disable input_byte_dual;
disable input_mode_dual;
disable input_byte_quad;
disable output_byte;
disable output_byte_dual;
disable output_byte_quad;
disable read_opcode;
disable write_page;
disable fill_page_latch;
disable read_page;
disable read_page_dualio;
disable read_page_quadio;
disable get_posclk_holdn;
disable get_negclk_holdn;
end
always @(negedge (holdn & !status_reg[`qe] & !csn))
begin
if(!holdn)
begin
#thlqz;
temp_dio_output_enable_reg = dio_output_enable_reg;
temp_do_output_enable = do_output_enable;
dio_output_enable_reg = 1'b0; do_output_enable = 1'b0;
holdn_active = 1'b1;
end
end
always @(posedge holdn)
begin
if(holdn_active == 1'b1)
begin
#thhqx;
dio_output_enable_reg = temp_dio_output_enable_reg;
do_output_enable = temp_do_output_enable;
holdn_active = 1'b0;
end
end
task chip_reset;
integer x;
begin
temp_dio_output_enable_reg = 1'b0;
dio_output_enable_reg = 1'b0; temp_do_output_enable = 1'b0;
do_output_enable = 1'b0; wpn_output_enable_reg = 1'b0; holdn_output_enable = 1'b0; holdn_active = 1'b0;
dio_reg = 1'b0;
do_reg = 1'b0;
wpn_reg = 1'b0;
holdn_reg = 1'b0;
mode_reg = 8'h00; wrap_reg = 8'b00010000; read_param_reg = 8'h00;
status_reg = 0; status_reg[`qe] = status_reg_otp[`qe];
status_reg[`srl] = status_reg_otp[`srl];
status_reg[`srp] = status_reg_otp[`srp];
status_reg[`bp0] = status_reg_otp[`bp0];
status_reg[`bp1] = status_reg_otp[`bp1];
status_reg[`bp2] = status_reg_otp[`bp2];
status_reg[`sec] = status_reg_otp[`sec];
status_reg[`tb] = status_reg_otp[`tb];
status_reg[`cmpb] = status_reg_otp[`cmpb];
status_reg[`wps] = status_reg_otp[`wps];
status_reg[`drv0] = status_reg_otp[`drv0];
status_reg[`drv1] = status_reg_otp[`drv1];
status_reg[`hld_rst] = status_reg_otp[`hld_rst];
status_reg[`lb1] = status_reg_otp[`lb1];
status_reg[`lb2] = status_reg_otp[`lb2];
status_reg[`lb3] = status_reg_otp[`lb3];
flag_prog_page = 0;
flag_prog_secsi_page = 0;
flag_erase_sector = 0;
flag_erase_half_block = 0;
flag_erase_block = 0;
flag_erase_secsi_sector = 0;
flag_erase_bulk = 0;
flag_power_down = 0;
flag_power_up_exec = 0;
flag_power_up_sig_read = 0;
flag_write_status_reg = 0;
flag_slow_read_reg = 1'b0; flag_read_op_reg = 1'b0; flag_suspend = 1'b0; flag_suspend_enabled = 1'b0;
flag_volatile_sr_write = 1'b0;
flag_qpi_mode = 0;
flag_enable_reset = 0;
flag_reset = 0;
flag_reset_condition = 0;
flag_set_read_param = 0;
timing_error = 0;
cmd_byte = 0;
null_reg = 0;
in_byte = 0;
out_byte = 0;
for(x = 0; x < num_lockbits; x=x+1)
lock_array[x] = 1;
end
endtask
task input_byte;
output [7:0] input_data;
integer x;
begin
if(flag_qpi_mode == 1)
input_byte_quad(input_data);
else
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
for(x = 7; x >= 0; x=x-1)
begin
get_posclk_holdn;
input_data[x] = dio;
end
in_byte = input_data;
end
end
endtask
task input_byte_dtr;
output [7:0] input_data;
integer x;
begin
if(flag_qpi_mode == 1)
input_byte_quad(input_data);
else
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
for(x = 7; x >= 0; x=x-2)
begin
get_posclk_holdn;
input_data[x] = dio;
get_negclk_holdn;
input_data[x-1] = dio;
end
in_byte = input_data;
end
end
endtask
task input_byte_no1stclock;
output [7:0] input_data;
integer x;
begin
if(flag_qpi_mode == 1)
input_byte_quad_no1stclock(input_data);
else
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
for(x = 7; x >= 0; x=x-1)
begin
if(x != 7)
get_posclk_holdn;
input_data[x] = dio;
end
in_byte = input_data;
end
end
endtask
task input_byte_dual;
output [7:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 7; x >= 0; x=x-2)
begin
get_posclk_holdn;
input_data[x-1] = dio;
input_data[x] = do;
end
in_byte = input_data;
end
endtask
task input_byte_dual_dtr;
output [7:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 7; x >= 0; x=x-4)
begin
get_posclk_holdn;
input_data[x-1] = dio;
input_data[x] = do;
get_negclk_holdn;
input_data[x-3] = dio;
input_data[x-2] = do;
end
in_byte = input_data;
end
endtask
task input_mode_dual;
output [5:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 5; x >= 0; x=x-2)
begin
get_posclk_holdn;
input_data[x-1] = dio;
input_data[x] = do;
end
end
endtask
task input_byte_quad;
output [7:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
if(wpn_output_enable_reg != 1'b0)
wpn_output_enable_reg = 1'b0;
if(holdn_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 7; x >= 0; x=x-4)
begin
@(posedge clk);
input_data[x-3] = dio;
input_data[x-2] = do;
input_data[x-1] = wpn;
input_data[x] = holdn;
end
in_byte = input_data;
end
endtask
task input_byte_quad_dtr;
output [7:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
if(wpn_output_enable_reg != 1'b0)
wpn_output_enable_reg = 1'b0;
if(holdn_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 7; x >= 0; x=x-8)
begin
@(posedge clk);
input_data[x-3] = dio;
input_data[x-2] = do;
input_data[x-1] = wpn;
input_data[x] = holdn;
@(negedge clk);
input_data[x-7] = dio;
input_data[x-6] = do;
input_data[x-5] = wpn;
input_data[x-4] = holdn;
end
in_byte = input_data;
end
endtask
task input_byte_quad_no1stclock;
output [7:0] input_data;
integer x;
begin
if(dio_output_enable_reg != 1'b0)
dio_output_enable_reg = 1'b0;
if(do_output_enable != 1'b0)
do_output_enable = 1'b0;
if(wpn_output_enable_reg != 1'b0)
wpn_output_enable_reg = 1'b0;
if(holdn_output_enable != 1'b0)
do_output_enable = 1'b0;
for(x = 7; x >= 0; x=x-4)
begin
if(x != 7)
@(posedge clk);
input_data[x-3] = dio;
input_data[x-2] = do;
input_data[x-1] = wpn;
input_data[x] = holdn;
end
in_byte = input_data;
end
endtask
task output_byte;
input [7:0] output_data;
integer x;
begin
if(flag_qpi_mode == 1)
output_byte_quad(output_data);
else
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-1)
begin
get_negclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
#tclqv do_reg = output_data[x];
end
end
end
endtask
task output_byte_dtr;
input [7:0] output_data;
integer x;
begin
if(flag_qpi_mode == 1)
output_byte_quad(output_data);
else
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-2)
begin
get_negclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
#tclqv do_reg = output_data[x];
get_posclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
#tclqv do_reg = output_data[x-1];
end
end
end
endtask
task output_byte_dual;
input [7:0] output_data;
integer x;
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-2)
begin
get_negclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
#tclqv ;
dio_reg = output_data[x-1];
do_reg = output_data[x];
end
end
endtask
task output_byte_dual_dtr;
input [7:0] output_data;
integer x;
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-4)
begin
get_negclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
#tclqv ;
dio_reg = output_data[x-1];
do_reg = output_data[x];
get_posclk_holdn;
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
#tclqv ;
dio_reg = output_data[x-3];
do_reg = output_data[x-2];
end
end
endtask
task output_byte_quad;
input [7:0] output_data;
integer x;
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-4)
begin
@(negedge clk);
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
if(wpn_output_enable_reg == 1'b0)
wpn_output_enable_reg = 1'b1;
if(holdn_output_enable == 1'b0)
holdn_output_enable = 1'b1;
#tclqv;
dio_reg = output_data[x-3];
do_reg = output_data[x-2];
wpn_reg = output_data[x-1];
holdn_reg = output_data[x];
end
end
endtask
task output_byte_quad_dtr;
input [7:0] output_data;
integer x;
begin
out_byte = output_data;
for(x = 7; x >= 0; x=x-8)
begin
@(negedge clk);
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
if(wpn_output_enable_reg == 1'b0)
wpn_output_enable_reg = 1'b1;
if(holdn_output_enable == 1'b0)
holdn_output_enable = 1'b1;
#tclqv;
dio_reg = output_data[x-3];
do_reg = output_data[x-2];
wpn_reg = output_data[x-1];
holdn_reg = output_data[x];
@(posedge clk);
if(do_output_enable == 1'b0) do_output_enable = 1'b1;
if(dio_output_enable_reg == 1'b0)
dio_output_enable_reg = 1'b1;
if(wpn_output_enable_reg == 1'b0)
wpn_output_enable_reg = 1'b1;
if(holdn_output_enable == 1'b0)
holdn_output_enable = 1'b1;
#tclqv;
dio_reg = output_data[x-7];
do_reg = output_data[x-6];
wpn_reg = output_data[x-5];
holdn_reg = output_data[x-4];
end
end
endtask
task get_negclk_holdn;
begin
if(status_reg[`qe]) @(negedge clk); else
@(negedge (clk & holdn));
end
endtask
task get_posclk_holdn;
begin
if(status_reg[`qe]) @(posedge clk); else
@(posedge (clk & holdn));
end
endtask
task wait_reset_suspend;
input [31:0] delay;
integer waitx;
integer num_iterations;
begin
waitx = 0;
if(delay >= treset_suspend_max)
begin
num_iterations = delay / treset_suspend_max;
for(waitx = 0; waitx < num_iterations; waitx=waitx+1) begin
if(flag_reset_condition) waitx = num_iterations; else
begin
wait(!flag_suspend_enabled || flag_reset_condition);
#treset_suspend_max;
end
end
end
num_iterations = delay % treset_suspend_max;
for(waitx = 0; waitx < num_iterations; waitx=waitx+1)
begin
if(flag_reset_condition) waitx = num_iterations;
else
begin
wait(!flag_suspend_enabled || flag_reset_condition); #1;
end
end
end
endtask
task wait_reset;
input [31:0] delay;
integer waitx;
integer num_iterations;
begin
waitx = 0;
if(delay >= treset_suspend_max)
begin
num_iterations = delay / treset_suspend_max;
for(waitx = 0; waitx < num_iterations; waitx=waitx+1) begin
if(flag_reset_condition) waitx = num_iterations; else
#treset_suspend_max; end
end
num_iterations = delay % treset_suspend_max;
for(waitx = 0; waitx < num_iterations; waitx=waitx+1) begin
if(flag_reset_condition) waitx = num_iterations;
else
#1;
end
end
endtask
function write_protected;
input [23:0] byte_address;
begin
if(status_reg[`wps])
write_protected = lock_array[lockbit_index(byte_address)];
else
begin
casez ({status_reg[`sec], status_reg[`tb],status_reg[`bp2],status_reg[`bp1],status_reg[`bp0]})
5'b??000 :
write_protected = 1'b0 ^ status_reg[`cmpb];
5'b00001 :
begin
if(byte_address >= (num_pages * 63 / 64 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b00010 :
begin
if(byte_address >= (num_pages * 31 / 32 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b00011 :
begin
if(byte_address >= (num_pages * 15 / 16 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b00100 :
begin
if(byte_address >= (num_pages * 7 / 8 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b00101 :
begin
if(byte_address >= (num_pages * 3 / 4 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b00110 :
begin
if(byte_address >= (num_pages * 1 / 2 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01001 :
begin
if(byte_address < (num_pages * 1 / 64 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01010 :
begin
if(byte_address < (num_pages * 1 / 32 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01011 :
begin
if(byte_address < (num_pages * 1 / 16 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01100:
begin
if(byte_address < (num_pages * 1 / 8 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01101 :
begin
if(byte_address < (num_pages * 1 / 4 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b01110 :
begin
if(byte_address < (num_pages * 1 / 2 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b10001 :
begin
if(byte_address >= (num_pages * 4095 / 4096 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b10010 :
begin
if(byte_address >= (num_pages * 2047 / 2048 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b10011 :
begin
if(byte_address >= (num_pages * 1023 / 1024 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b1010? :
begin
if(byte_address >= (num_pages * 511 / 512 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b11001 :
begin
if(byte_address < (num_pages * 1 / 4096 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b11010 :
begin
if(byte_address < (num_pages * 1 / 2048 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b11011 :
begin
if(byte_address < (num_pages * 1 / 1024 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b1110? :
begin
if(byte_address < (num_pages * 1 / 512 * pagesize))
write_protected = 1'b1 ^ status_reg[`cmpb];
else
write_protected = 1'b0 ^ status_reg[`cmpb];
end
5'b??111 :
begin
write_protected = 1'b1 ^ status_reg[`cmpb];
end
endcase
end
end
endfunction
function is_qpi;
input [7:0] cmd_byte;
begin
if(flag_qpi_mode == 1)
begin
case (cmd_byte)
`cmd_write_enable, `cmd_write_enable_vsr, `cmd_write_disable, `cmd_read_status,
`cmd_read_status2, `cmd_read_status3, `cmd_write_status, `cmd_write_status2, `cmd_write_status3, `cmd_page_program,
`cmd_individual_lock, `cmd_individual_unlock, `cmd_read_block_lock, `cmd_global_block_lock, `cmd_global_block_unlock,
`cmd_sector_erase,`cmd_half_block_erase, `cmd_block_erase, `cmd_bulk_erase, `cmd_bulk_erase2,
`cmd_suspend, `cmd_resume, `cmd_deep_powerdown, `cmd_set_read_param, `cmd_read_data_fast,
`cmd_read_data_fast_wrap, `cmd_read_data_fast_quad_io, `cmd_read_signature, `cmd_read_id, `cmd_read_jedec_id,
`cmd_read_unique_id, `cmd_disable_qpi, `cmd_enable_reset, `cmd_chip_reset, `cmd_read_data_fast_dtr_wrap,
`cmd_read_data_fast_dtr, `cmd_read_data_fast_quad_io_dtr :
begin
is_qpi = 1;
end
default :
begin
is_qpi = 0;
$display("invalid opcode for qpi mode. (%0h)",cmd_byte);
end
endcase
end
else
is_qpi = 1;
end
endfunction
function integer lockbit_index;
input [23:0] byte_address;
begin
if((byte_address[23:16] == 0) || (byte_address[23:16] == (num_blocks-1)))
begin
if(byte_address[23:16] == 0)
lockbit_index = byte_address[15:0] / sectorsize;
else
lockbit_index = (byte_address[15:0] / sectorsize) + 16;
end
else
lockbit_index = byte_address[23:16] - 1 + 32;
end
endfunction
task read_page;
input [1:0] fast_read; input [1:0] mem_read; integer x;
begin
if(!status_reg[`wip])
begin
input_byte(byte_address[23:16]);
input_byte(byte_address[15:8]);
input_byte(byte_address[7:0]);
if(fast_read)
begin
if(flag_qpi_mode == 1)
begin
for(x = 0; x <= read_param_reg[5:4];x = x + 1)
input_byte(null_reg);
end
else
input_byte(null_reg);
end
if(mem_read) input_byte(null_reg);
forever
begin
if(mem_read == 1) begin
case(byte_address[23:8])
16'h10 :
output_byte(secsi[byte_address[7:0]]);
16'h20 :
output_byte(secsi[byte_address[7:0]+pagesize]);
16'h30 :
output_byte(secsi[byte_address[7:0]]+(2*pagesize));
default :
begin
$display("invalid security page address (%x)",byte_address);
$stop;
end
endcase
end
else if(mem_read == 2) begin
if(byte_address[23:8] == 0)
output_byte(sfdp[byte_address[7:0]]);
else
begin
$display("invalid sfdp page address (%x)", byte_address);
$stop;
end
end
else begin
byte_address = byte_address & address_mask;
if(fast_read == 2)
output_byte_dual(memory[byte_address]);
else if(fast_read == 3)
output_byte_quad(memory[byte_address]);
else
output_byte(memory[byte_address]);
end
if(mem_read)
byte_address[7:0] = byte_address[7:0] + 1;
else
byte_address = byte_address + 1;
end
end
end
endtask
task read_page_dualio;
begin
if(!status_reg[`wip])
begin
input_byte_dual(byte_address[23:16]);
input_byte_dual(byte_address[15:8]);
input_byte_dual(byte_address[7:0]);
input_mode_dual(mode_reg[7:2]); get_posclk_holdn;
forever
begin
byte_address = byte_address & address_mask;
output_byte_dual(memory[byte_address]);
byte_address = byte_address + 1;
end
end
end
endtask
task read_page_quadio;
input [7:0] cmd;
integer x;
begin
input_byte_quad(byte_address[23:16]);
input_byte_quad(byte_address[15:8]);
input_byte_quad(byte_address[7:0]);
if(!status_reg[`wip])
begin
case (cmd)
`cmd_read_data_fast_quad_io :
begin
input_byte_quad(mode_reg[7:0]);
input_byte_quad(null_reg);
input_byte_quad(null_reg);
end
`cmd_read_data_fast_wrap :
begin
for(x = 0; x <= read_param_reg[5:4];x = x + 1)
input_byte_quad(null_reg);
end
endcase
forever
begin
byte_address = byte_address & address_mask;
output_byte_quad(memory[byte_address]);
if(cmd == `cmd_read_data_fast_wrap)
begin
case ({read_param_reg[1],read_param_reg[0]})
2'b00 :
byte_address[2:0] = byte_address[2:0] + 1;
2'b01 :
byte_address[3:0] = byte_address[3:0] + 1;
2'b10 :
byte_address[4:0] = byte_address[4:0] + 1;
2'b11 :
byte_address[5:0] = byte_address[5:0] + 1;
endcase
end
else
if(!wrap_reg[4] && ( cmd == `cmd_read_data_fast_quad_io ))
begin
case ({wrap_reg[6],wrap_reg[5]})
2'b00 :
byte_address[2:0] = byte_address[2:0] + 1;
2'b01 :
byte_address[3:0] = byte_address[3:0] + 1;
2'b10 :
byte_address[4:0] = byte_address[4:0] + 1;
2'b11 :
byte_address[5:0] = byte_address[5:0] + 1;
endcase
end
else
byte_address = byte_address + 1;
end
end
end
endtask
task write_page;
input quadio;
integer x;
integer address;
begin
if(!status_reg[`wip])
begin
input_byte(prog_byte_address[23:16]);
input_byte(prog_byte_address[15:8]);
input_byte(prog_byte_address[7:0]);
if(!write_protected(prog_byte_address))
fill_page_latch(quadio,prog_byte_address,0);
end
end
endtask
task fill_page_latch;
input quadio;
input [23:0] prog_address;
input flag_secsi;
integer x;
integer address;
begin
if(flag_secsi)
begin
address = (prog_address >> 4) - 23'h100;
address[7:0] = 0;
end
else
begin
address = prog_address;
address[7:0] = 0;
end
for(x = 0; x < pagesize; x=x+1)
page_latch[x] = flag_secsi ? secsi[address+x] : memory[address+x];
forever
begin
if(quadio)
input_byte_quad(temp);
else
input_byte(temp);
page_latch[prog_address[7:0]] = temp;
if(flag_secsi)
flag_prog_secsi_page = 1;
else
flag_prog_page = 1;
prog_address[7:0] = prog_address[7:0] + 1;
end
end
endtask
task dump_mem;
integer x;
integer file;
begin
file = $fopen(`mem_filename);
$fwrite(file,"");
for(x = 0; x < (num_pages * pagesize); x=x+1)
begin
if(x % 16)
$fwrite(file,"%h ", memory[x]);
else
$fwrite(file,"\n%h ", memory[x]);
end
$fclose(file);
end
endtask
always @(posedge flag_set_read_param)
begin :set_read_param
@(posedge csn);
if(flag_set_read_param == 1)
begin
read_param_reg = read_param_reg_shadow;
end
flag_set_read_param = 0;
end
always @(posedge flag_reset)
begin :reset
@(posedge csn);
if((flag_reset == 1) && (flag_write_status_reg == 0)) begin
status_reg[`wip] = 1;
flag_reset_condition = 1;
#tres1;
chip_reset();
end
flag_reset = 0;
end
always @(posedge flag_power_up_exec)
begin :power_up
@(posedge csn);
if(flag_power_up_exec == 1)
begin
if(flag_power_up_sig_read == 1)
#tres2;
else
#tres1;
flag_power_down = 0;
flag_power_up_exec = 0;
flag_power_up_sig_read = 0;
flag_suspend = 0;
end
end
always @(posedge flag_power_down)
begin :power_down
@(posedge csn);
if(flag_power_down == 1)
begin
#tdp;
end
end
always @(posedge flag_suspend)
begin :erase_suspend
@(posedge csn); if(flag_suspend == 1)
begin
status_reg[`sus] = 1;
wait_reset(tsus);
flag_suspend_enabled = 1'b1;
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
end
always @(posedge flag_resume)
begin :erase_resume
@(posedge csn); if(flag_resume == 1)
begin
status_reg[`sus] = 0;
flag_suspend_enabled = 1'b0;
flag_suspend = 1'b0;
flag_resume = 1'b0;
status_reg[`wel] = 1;
status_reg[`wip] = 1;
end
end
always @(posedge flag_erase_sector) begin :erase_sector
integer x;
@(posedge csn); if(flag_erase_sector == 1)
begin
status_reg[`wip] = 1;
wait_reset_suspend(tse);
for(x = 0; x < sectorsize; x=x+1)
memory[(byte_address[23:12] * sectorsize) + x] = 8'hff;
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_erase_sector = 0;
end
always @(posedge flag_erase_secsi_sector) begin :erase_secsi_sector
integer x;
@(posedge csn); if(flag_erase_secsi_sector == 1)
begin
status_reg[`wip] = 1;
case(byte_address[23:8])
16'h10 :
begin
wait_reset_suspend(tse);
for(x = 0; x < pagesize; x=x+1)
secsi[x] = 8'hff;
end
16'h20 :
begin
wait_reset_suspend(tse);
for(x = 0; x < pagesize; x=x+1)
secsi[x+pagesize] = 8'hff;
end
16'h30 :
begin
wait_reset_suspend(tse);
for(x = 0; x < pagesize; x=x+1)
secsi[x+(pagesize * 2)] = 8'hff;
end
default :
begin
$display("invalid security page erase address (%x)",byte_address);
$stop;
end
endcase
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_erase_secsi_sector = 0;
end
always @(posedge flag_erase_block) begin :erase_block
integer x;
@(posedge csn); if(flag_erase_block == 1)
begin
status_reg[`wip] = 1;
wait_reset_suspend(tbe2);
for(x = 0; x < blocksize; x=x+1)
memory[(byte_address[23:16] * blocksize) + x] = 8'hff;
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_erase_block = 0;
end
always @(posedge flag_erase_half_block) begin :erase_half_block
integer x;
@(posedge csn); if(flag_erase_half_block == 1)
begin
status_reg[`wip] = 1;
wait_reset_suspend(tbe1);
for(x = 0; x < halfblocksize; x=x+1)
memory[(byte_address[23:15] * halfblocksize) + x] = 8'hff;
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_erase_half_block = 0;
end
always @(posedge flag_erase_bulk) begin :erase_bulk
integer x;
@(posedge csn); if(flag_erase_bulk == 1)
begin
status_reg[`wip] = 1;
for(x = 0; x < 40; x=x+1)
wait_reset(tce_40);
for(x = 0; x < pagesize * num_pages; x=x+1)
memory[x] = 8'hff;
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_erase_bulk = 0;
end
always @(posedge flag_prog_page) begin :program_to_page
integer x;
@(posedge csn); begin
status_reg[`wip] = 1;
prog_byte_address[7:0] = 0;
for(x = 0; x < pagesize; x=x+1)
begin
memory[prog_byte_address+x] = page_latch[x] & memory[prog_byte_address+x];
wait_reset_suspend(tpp / pagesize);
end
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_prog_page = 0;
end
always @(posedge flag_prog_secsi_page) begin :program_to_secsi_page
integer x;
@(posedge csn); begin
status_reg[`wip] = 1;
prog_byte_address[7:0] = 0;
case(prog_byte_address[23:8])
16'h10 :
begin
for(x = 0; x < pagesize; x=x+1)
begin
secsi[x] = page_latch[x] & secsi[x];
wait_reset_suspend(tpp / pagesize);
end
end
16'h20 :
begin
for(x = 0; x < pagesize; x=x+1)
begin
secsi[x+pagesize] = page_latch[x] & secsi[x+pagesize];
wait_reset_suspend(tpp / pagesize);
end
end
16'h30 :
begin
for(x = 0; x < pagesize; x=x+1)
begin
secsi[x+(pagesize*2)] = page_latch[x] & secsi[x+(pagesize*2)];
wait_reset_suspend(tpp / pagesize);
end
end
default :
begin
$display("invalid security page program address (%x)",prog_byte_address);
$stop;
end
endcase
status_reg[`wip] = 0;
status_reg[`wel] = 0;
end
flag_prog_secsi_page = 0;
end
always @(posedge flag_write_status_reg) begin :write_status_reg
@(posedge csn); if(flag_write_status_reg == 1)
begin
status_reg[`wip] = 1;
status_reg[`qe] = status_reg_shadow[`qe];
status_reg[`srl] = status_reg_shadow[`srl];
status_reg[`srp] = status_reg_shadow[`srp];
status_reg[`bp0] = status_reg_shadow[`bp0];
status_reg[`bp1] = status_reg_shadow[`bp1];
status_reg[`bp2] = status_reg_shadow[`bp2];
status_reg[`sec] = status_reg_shadow[`sec];
status_reg[`tb] = status_reg_shadow[`tb];
status_reg[`cmpb] = status_reg_shadow[`cmpb];
status_reg[`wps] = status_reg_shadow[`wps];
status_reg[`drv0] = status_reg_shadow[`drv0];
status_reg[`drv1] = status_reg_shadow[`drv1];
status_reg[`hld_rst] = status_reg_shadow[`hld_rst];
status_reg[`lb1] = status_reg[`lb1] | status_reg_shadow[`lb1];
status_reg[`lb2] = status_reg[`lb2] | status_reg_shadow[`lb2];
status_reg[`lb3] = status_reg[`lb3] | status_reg_shadow[`lb3];
if(!flag_volatile_sr_write)
begin
status_reg_otp[`qe] = status_reg_shadow[`qe];
status_reg_otp[`srl] = status_reg_shadow[`srl];
status_reg_otp[`srp] = status_reg_shadow[`srp];
status_reg_otp[`bp0] = status_reg_shadow[`bp0];
status_reg_otp[`bp1] = status_reg_shadow[`bp1];
status_reg_otp[`bp2] = status_reg_shadow[`bp2];
status_reg_otp[`sec] = status_reg_shadow[`sec];
status_reg_otp[`tb] = status_reg_shadow[`tb];
status_reg_otp[`cmpb] = status_reg_shadow[`cmpb];
status_reg_otp[`wps] = status_reg_shadow[`wps];
status_reg_otp[`drv0] = status_reg_shadow[`drv0];
status_reg_otp[`drv1] = status_reg_shadow[`drv1];
status_reg_otp[`hld_rst] = status_reg_shadow[`hld_rst];
status_reg_otp[`lb1] = status_reg[`lb1] | status_reg_shadow[`lb1];
status_reg_otp[`lb2] = status_reg[`lb2] | status_reg_shadow[`lb2];
status_reg_otp[`lb3] = status_reg[`lb3] | status_reg_shadow[`lb3];
end
if(status_reg[`qe] == 0)
flag_qpi_mode = 0;
if(status_reg[`wel])
wait_reset(tw);
status_reg[`wip] = 0;
status_reg[`wel] = 0;
flag_volatile_sr_write = 0;
flag_write_status_reg = 0;
end
end
endmodule |
module sirv_otp_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata
);
assign i_icb_cmd_ready = 1'b0;
assign i_icb_rsp_valid = 1'b0;
assign i_icb_rsp_rdata = 32'b0;
assign f_icb_cmd_ready = 1'b0;
assign f_icb_rsp_valid = 1'b0;
assign f_icb_rsp_rdata = 32'b0;
endmodule |
module tt_um_test (
input wire [7:0] ui_in, output wire [7:0] uo_out, input wire [7:0] uio_in, output wire [7:0] uio_out, output wire [7:0] uio_oe, input wire ena,
input wire clk,
input wire rst_n
);
reg rst_n_i;
reg [7:0] cnt;
always @(posedge clk or negedge rst_n)
if (~rst_n)
rst_n_i <= 1'b0;
else
rst_n_i <= 1'b1;
always @(posedge clk or negedge rst_n_i)
if (~rst_n_i)
cnt <= 0;
else
cnt <= cnt + 1;
assign uo_out = ui_in[0] ? cnt : uio_in;
assign uio_out = ui_in[0] ? cnt : 8'h00;
assign uio_oe = ui_in[0] ? 8'hff : 8'h00;
endmodule |
module spicontroller (
input wire clk,
input wire rst,
output reg cs0,
output reg cs1,
output reg spiclk,
output reg mosi,
input wire miso,
input wire addr15, input wire read_notwrite, input wire addr, input wire data,
output reg shiftaddr, output reg shiftdataread, output reg shiftdatawrite, output reg presetcarry, output reg endofphase, output reg prepoutput
);
reg [6:0] spiphase;
always @(posedge clk) begin
if (rst)
spiphase <= 0;
else if (spiphase == 83)
spiphase <= 0;
else
spiphase <= spiphase + 1;
end
always @(posedge clk) begin
if (spiphase <= 1) begin
cs0 <= 1;
cs1 <= 1;
spiclk <= 0;
mosi <= 0;
end else begin
cs0 <= csreg;
cs1 <= !csreg;
if (spiphase <= 81)
spiclk <= spiphase[0];
else
spiclk <= 0;
if (spiphase <= 13)
mosi <= 0;
else if (spiphase <= 15)
mosi <= 1;
else if (spiphase <= 17) begin
if (spiphase[0] == 0)
mosi <= read_notwrite;
end else if (spiphase <= 47) begin
if (spiphase[0] == 0)
mosi <= addr;
end else if (spiphase <= 49)
mosi <= 0;
else begin
if (read_notwrite)
mosi <= 0;
else begin
if (spiphase[0] == 0)
mosi <= data;
end
end
end
end
always @(posedge clk) begin
shiftaddr <= ((spiphase >= 18) && (spiphase <= 48) && (spiphase[0] == 0));
shiftdataread <= ((spiphase >= 51) && (spiphase <= 81) && (spiphase[0] == 1) && read_notwrite);
shiftdatawrite <= ((spiphase >= 50) && (spiphase <= 80) && (spiphase[0] == 0) && !read_notwrite);
presetcarry <= (spiphase == 17);
endofphase <= (spiphase == 83);
prepoutput <= (spiphase == 49);
end
reg csreg;
always @(posedge clk) begin
if (spiphase == 1)
csreg <= addr15;
end
endmodule |
module f_2 (
input wire porta,
output wire out
);
assign out =
(porta == 0);
endmodule |
module f_20k (
input wire portb,
input wire porta,
output wire out
);
assign out =
(portb == 1 & porta == 0) |
(portb == 0 & porta == 1);
endmodule |
Subsets and Splits