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alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.ip_user_files/bd/design_1/ip/design_1_dec_to_fir_mux_0_0/sim/design_1_dec_to_fir_mux_0_0.vhd | 1 | 3,444 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: noah-huesser:user:dec_to_fir_mux:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dec_to_fir_mux_0_0 IS
PORT (
DecRate : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Mux3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END design_1_dec_to_fir_mux_0_0;
ARCHITECTURE design_1_dec_to_fir_mux_0_0_arch OF design_1_dec_to_fir_mux_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dec_to_fir_mux_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dec_to_fir_mux IS
PORT (
DecRate : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Mux3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Mux0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT dec_to_fir_mux;
BEGIN
U0 : dec_to_fir_mux
PORT MAP (
DecRate => DecRate,
Mux3 => Mux3,
Mux2 => Mux2,
Mux1 => Mux1,
Mux0 => Mux0
);
END design_1_dec_to_fir_mux_0_0_arch;
| mit | bfd139839c31dba46cbfc5bde3fa283b | 0.723577 | 3.792952 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_1_0/synth/RAT_FlagReg_1_0.vhd | 2 | 3,920 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_1_0 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_1_0;
ARCHITECTURE RAT_FlagReg_1_0_arch OF RAT_FlagReg_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "FlagReg,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_FlagReg_1_0_arch : ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "RAT_FlagReg_1_0,FlagReg,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=FlagReg,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_1_0_arch;
| mit | 643c938637de9c7f09376553197b718f | 0.72551 | 3.888889 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_1/sim/design_1_cic_compiler_0_1.vhd | 2 | 7,237 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_1;
ARCHITECTURE design_1_cic_compiler_0_1_arch OF design_1_cic_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_1",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 125,
C_INPUT_WIDTH => 14,
C_OUTPUT_WIDTH => 42,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 125,
C_MAX_RATE => 125,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 42,
C_C2 => 42,
C_C3 => 42,
C_C4 => 42,
C_C5 => 0,
C_C6 => 0,
C_I1 => 42,
C_I2 => 42,
C_I3 => 42,
C_I4 => 42,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 48,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_1_arch;
| mit | cf69bc88aa6afc53d03dab9be77cdfb3 | 0.651237 | 3.327356 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_0/sim/RAT_Mux4x1_8_0_0.vhd | 2 | 3,384 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_8_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux4x1_8_0_0;
ARCHITECTURE RAT_Mux4x1_8_0_0_arch OF RAT_Mux4x1_8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux4x1_8;
BEGIN
U0 : Mux4x1_8
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_8_0_0_arch;
| mit | 02b0fe5b5470546eb995e1067245bfa7 | 0.71247 | 3.751663 | false | false | false | false |
David-Estevez/spaceinvaders | src/edgeDetectorDebounce.vhd | 1 | 3,323 | ----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector with debounce integrated
--
-- Detects raising edges and ouputs a one-period pulse from a physical switch.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity edgeDetectorDebounce is
generic( debounceTime: integer := 100 );
port( clk: in STD_LOGIC;
reset: in STD_LOGIC;
clear : in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC );
end edgeDetectorDebounce;
architecture Behavioral of edgeDetectorDebounce is
-- Description of the states:
-- Not detected: edge not detected, input is '0'
-- Edge detected: edge detection
-- Disabled: state transition will not be possible
-- until timer timeout, to avoid bouncing
-- Waiting: timer timeout has ocurred, but the input
-- is still '1'. It will remain here until
-- the input is '0'
type State is ( notDetected, edgeDetected, Disabled, waiting );
signal currentState, nextState: State;
signal counterEnabled: std_logic;
signal timeout: std_logic;
component timer is
generic ( t: integer);
port (clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
en : in std_logic;
q : out std_logic);
end component;
begin
-- Instantiate the timer:
tim0 : timer generic map ( t => debounceTime )
port map ( clk => clk,
reset => reset,
clear => clear,
en => counterEnabled,
q => timeout );
-- Process for changing states:
process( clk, reset)
begin
-- Reset
if reset = '1' then
currentState <= notDetected;
-- Update State
elsif clk'Event and clk = '1' then
if clear = '1' then
currentState <= notDetected;
elsif enable = '1' then
currentState <= nextState;
end if;
end if;
end process;
-- Process for modelling the transitions / outputs
-- of the state machine
process( currentState, input, timeout )
begin
nextState <= currentState;
case currentState is
when notDetected =>
-- Set outputs
detected <= '0';
counterEnabled <= '0';
-- Define transitions
if input = '0' then
nextState <= notDetected;
else
nextState <= edgeDetected;
end if;
when edgeDetected =>
-- Set outputs
detected <= '1';
counterEnabled <= '0';
-- Define transitions
nextState <= Disabled;
when Disabled =>
-- Set outputs
detected <= '0';
counterEnabled <= '1';
-- Define transitions
if timeout = '1' then
if input = '0' then
nextState <= notDetected;
else
nextState <= waiting;
end if;
else
nextState <= Disabled;
end if;
when waiting =>
-- Set outputs
detected <= '0';
counterEnabled <= '0';
-- Define transitions
if input = '0' then
nextState <= notDetected;
else
nextState <= waiting;
end if;
end case;
end process;
end Behavioral;
| gpl-3.0 | cf30793333db6b99ce9a6ce75ab1199b | 0.56988 | 3.933649 | false | false | false | false |
open-power/snap | hardware/hdl/core/ctrl_mgr.vhd | 1 | 11,322 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.snap_core_types.ALL;
ENTITY ctrl_mgr IS
PORT (
--
-- pervasive
ha_pclock : IN std_logic;
--
-- PSL IOs
ha_j_i : IN HA_J_T;
ah_j_o : OUT AH_J_T;
--
-- Global Resets
afu_reset_o : OUT std_logic;
--
-- DMA IOs
cd_c_o : OUT CD_C_T;
--
-- MMIO IOs
mmc_c_i : IN MMC_C_T;
mmc_d_i : IN MMC_D_T;
mmc_e_i : IN MMC_E_T;
cmm_c_o : OUT CMM_C_T;
cmm_e_o : OUT CMM_E_T
);
END ctrl_mgr;
ARCHITECTURE ctrl_mgr OF ctrl_mgr IS
--
-- CONSTANT
--
-- TYPE
TYPE CTRL_FSM_T IS (ST_FSM_ERROR, ST_ERROR, ST_IDLE, ST_SEND_RDONE, ST_SEND_JDONE);
--
-- ATTRIBUTE
ATTRIBUTE syn_encoding : string;
ATTRIBUTE syn_encoding OF CTRL_FSM_T : TYPE IS "safe";
--
-- SIGNAL
SIGNAL ctrl_fsm_q : CTRL_FSM_T := ST_IDLE;
SIGNAL ha_j_q : HA_J_T;
SIGNAL ha_j_llcmd_code_q : std_logic_vector(LLCMD_CMD_L DOWNTO LLCMD_CMD_R);
SIGNAL ha_j_context_id_q : std_logic_vector(CONTEXT_BITS-1 DOWNTO 0);
SIGNAL ah_j_q : AH_J_T := ('0', '0', '0', (OTHERS => '0'), '0');
SIGNAL afu_reset_q : std_logic := '1';
-- SIGNAL dma_reset_m : std_logic := '1';
-- SIGNAL dma_reset_q : std_logic := '1';
-- SIGNAL gen_dma_reset : std_logic := '0';
-- SIGNAL gen_app_reset : std_logic;
-- SIGNAL app_reset_m : std_logic;
-- SIGNAL app_reset_v : std_logic;
SIGNAL llcmd_req_q : std_logic;
SIGNAL llcmd_ack_q : std_logic;
SIGNAL terminate_req_q : std_logic;
SIGNAL terminate_ongoing_q : std_logic;
SIGNAL terminate_context_id_q : std_logic_vector(CONTEXT_BITS-1 DOWNTO 0);
-- Ctrl Mgr Error record:
SIGNAL cmm_e_q : CMM_E_T := (OTHERS => '0');
BEGIN
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- ******************************************************
-- ***** JOB CONTROL INTERFACE HANDLING *****
-- ******************************************************
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Reset handling
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
generate_afu_reset : PROCESS (ha_pclock)
BEGIN
IF (rising_edge(ha_pclock)) THEN
IF (ha_j_q.valid = '1') AND (ha_j_q.com = RESET) THEN
afu_reset_q <= '1';
ELSE
afu_reset_q <= '0';
END IF;
END IF;
END PROCESS generate_afu_reset;
-- gen_dma_reset <= afu_reset_q; -- OR dma_err_reset_q;
-- generate_dma_reset : PROCESS (ha_pclock, gen_dma_reset)
-- BEGIN
-- IF gen_dma_reset = '1' THEN
-- dma_reset_q <= '1';
-- dma_reset_m <= '1';
-- ELSIF (rising_edge(ha_pclock)) THEN
-- dma_reset_m <= '0';
-- dma_reset_q <= dma_reset_m;
-- END IF;
-- END PROCESS generate_dma_reset;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Control FSM
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
ctrl_fsm : PROCESS (ha_pclock)
BEGIN
IF (rising_edge(ha_pclock)) THEN
ah_j_q <= (ah_j_q.running, '0',
llcmd_ack_q,
ah_j_q.error, '0');
llcmd_req_q <= '0';
terminate_req_q <= '0';
terminate_ongoing_q <= terminate_ongoing_q AND NOT mmc_c_i.action_reset_done;
llcmd_ack_q <= mmc_c_i.action_reset_done AND terminate_ongoing_q;
cmm_e_q.ctrl_fsm_err <= '0';
--
-- Handle START Command
--
IF (ha_j_q.valid = '1') AND (ha_j_q.com = START) THEN
ah_j_q.running <= '1';
END IF;
--
-- Handle LLCMD
--
IF (ha_j_q.valid = '1') AND (ha_j_q.com = LLCMD) THEN
llcmd_req_q <= '1';
IF ha_j_llcmd_code_q = LLCMD_CODES(TERMINATE_ELEMENT) AND mmc_d_i.attached_contexts(to_integer(unsigned(ha_j_context_id_q))) = '1' THEN
terminate_req_q <= '1';
terminate_ongoing_q <= '1';
terminate_context_id_q <= ha_j_context_id_q;
ELSE
llcmd_ack_q <= '1';
END IF;
END IF;
--
-- F S M
--
CASE ctrl_fsm_q IS
--
-- STATE: SEND JOB DONE -- TODO: currently not reachable
--
WHEN ST_SEND_JDONE =>
--
-- make sure 'job running' is set to '0' prior to 'job done' set to '1'
IF ah_j_q.running = '1' THEN
ah_j_q.running <= '0';
ELSE
ah_j_q.running <= '0'; -- swallow concurrent 'START'
ah_j_q.done <= '1';
ctrl_fsm_q <= ST_IDLE;
END IF;
--
-- STATE: SEND RESET DONE
--
WHEN ST_SEND_RDONE =>
IF mmc_c_i.reset_done = '1' THEN
ah_j_q.done <= '1';
ctrl_fsm_q <= ST_IDLE;
END IF;
--
-- STATE: IDLE
--
WHEN ST_IDLE =>
ctrl_fsm_q <= ST_IDLE;
--
-- STATE: ERROR (incoming FIR)
--
WHEN ST_ERROR =>
NULL;
--
-- STATE: FSM ERROR
--
WHEN ST_FSM_ERROR =>
cmm_e_q.ctrl_fsm_err <= '1';
END CASE;
--
-- Handle FIR
--
IF (or_reduce(mmc_e_i.error) = '1') AND (ah_j_q.running = '1') THEN
ah_j_q.error <= mmc_e_i.error;
ah_j_q.running <= '0';
ah_j_q.done <= '1';
ctrl_fsm_q <= ST_ERROR;
END IF;
IF afu_reset_q = '1' THEN
ah_j_q.running <= '0';
ah_j_q.error <= (OTHERS => '0');
llcmd_ack_q <= '0';
terminate_ongoing_q <= '0';
terminate_context_id_q <= (OTHERS => '0');
--
-- send DONE after reset
ctrl_fsm_q <= ST_SEND_RDONE;
END IF; -- afu_reset_q
END IF; -- rising_edge(ha_pclock)
END PROCESS ctrl_fsm;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Error Handling
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
handle_errors : PROCESS (ha_pclock)
BEGIN -- PROCESS
IF rising_edge(ha_pclock) THEN
cmm_e_q.com_parity_err <= '0';
cmm_e_q.ea_parity_err <= '0';
IF (ha_j_q.valid = '1') THEN
IF COM_CODES_PARITY(ha_j_q.com) /= ha_j_q.compar THEN
cmm_e_q.com_parity_err <= '1';
END IF;
IF parity_gen_odd(ha_j_q.ea) /= ha_j_q.eapar THEN
cmm_e_q.ea_parity_err <= '1';
END IF;
END IF;
END IF;
END PROCESS handle_errors;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- ******************************************************
-- ***** MISC *****
-- ******************************************************
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- RAS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- ERROR OUTPUT
--
-- cmm_e_q <= (0 => ctrl_fsm_err,
-- OTHERS => '0');
--
-- FIR ASSERTS
--
assert cmm_e_q.ctrl_fsm_err = '0' report "FIR: Ctrl Mgr ctrl fsm error" severity FIR_MSG_LEVEL;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Output Connection
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- AH_J
ah_j_o <= ah_j_q;
-- reset signals
afu_reset_o <= afu_reset_q;
-- app_reset_o <= app_reset_v;
-- dma_reset_o <= dma_reset_q;
-- CD_C
cd_c_o.quiesce_request <= terminate_req_q;
cd_c_o.quiesce_release <= mmc_c_i.action_reset_done;
cd_c_o.quiesce_context_id <= terminate_context_id_q;
-- CMM_C
cmm_c_o.terminate_request <= terminate_req_q;
cmm_c_o.terminate_context_id <= terminate_context_id_q;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Interface Input
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
interfaces : PROCESS (ha_pclock)
BEGIN
IF (rising_edge(ha_pclock)) THEN
-- AFU Control Interface from host
ha_j_q <= ha_j_i;
ha_j_llcmd_code_q <= ha_j_i.ea(LLCMD_CMD_L DOWNTO LLCMD_CMD_R);
ha_j_context_id_q <= ha_j_i.ea(LLCMD_PE_HANDLE_R+CONTEXT_BITS-1 DOWNTO LLCMD_PE_HANDLE_R);
END IF;
END PROCESS interfaces;
END ARCHITECTURE;
| apache-2.0 | 8ccd5e97234bba3b6296f9e17dffd334 | 0.364865 | 4.12459 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_KCU105.vhdl | 1 | 11,687 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_KCU105 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 300.0 MHz
);
port (
ClockIn_300MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_300MHz : out STD_LOGIC;
Clock_300MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_Stable_300MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC
);
end entity;
-- MMCM - Clock Wizard Report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 300.000 0.000 50.0 81.568 77.836
-- CLK_OUT1 200.000 0.000 50.0 88.351 77.836
-- CLK_OUT2 100.000 0.000 50.0 101.278 77.836
--
architecture rtl of clknet_ClockNetwork_KCU105 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 300 MHz
-- slowest output clock: 100 Mhz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (300 MHz / 100 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 100 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0) := (others => '0');
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_300MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_300MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_300MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock : entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset NOR MMCM_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= NOT MMCM_Locked_d AND MMCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
Locked <= MMCM_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_300MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 300 MHz BUFG
BUFG_Clock_300MHz : BUFG
port map (
I => MMCM_Clock_300MHz,
O => MMCM_Clock_300MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCME3_ADV
generic map (
STARTUP_WAIT => "FALSE",
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 4.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => "FALSE",
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 4.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => "FALSE",
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => "FALSE",
CLKOUT2_DIVIDE => 12,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => "FALSE",
CLKOUT3_DIVIDE => 120,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => "FALSE"
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_300MHz,
CLKIN2 => ClockIn_300MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_300MHz_BUFG,
CLKFBSTOPPED => open,
CDDCREQ => '0',
CDDCDONE => open,
CLKOUT0 => MMCM_Clock_300MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_200MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_100MHz,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
Control_Clock_300MHz <= Control_Clock_BUFR;
Clock_300MHz <= MMCM_Clock_300MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncLocked300MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_300MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_300MHz -- synchronized data
);
syncLocked200MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked100MHz : entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
end architecture;
| apache-2.0 | a8928c3df8440befacd6ae937208b4f3 | 0.487893 | 4.23442 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/synth/RAT_Counter10bit_0_0.vhd | 2 | 4,153 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Counter10bit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Counter10bit_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END RAT_Counter10bit_0_0;
ARCHITECTURE RAT_Counter10bit_0_0_arch OF RAT_Counter10bit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "Counter10bit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Counter10bit_0_0_arch : ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Counter10bit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END RAT_Counter10bit_0_0_arch;
| mit | adedd5183ae75ba303f4da42fe189f79 | 0.732723 | 3.834718 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/RAT_Wrapper.vhd | 1 | 6,993 | ----------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT CPU. This model provides a template to interfaces
-- the RAT CPU to the Nexys2 development board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port (
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
BUTTONS : in STD_LOGIC_VECTOR (3 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GRN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC
);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-- INPUT PORT IDS -------------------------------------------------------------
-- Right now, the only possible inputs are the switches
-- In future labs you can add more port IDs, and you'll have
-- to add constants here for the mux below
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
-- In future labs you can add more port IDs
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
-------------------------------------------------------------------------------
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"81";
CONSTANT AN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT BUTTONS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"50";
component Clk_Divider is
port (
CLK : in std_logic;
S_CLK : out std_logic
);
end component;
component RAT_CPU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_OE : out STD_LOGIC;
RST : in STD_LOGIC;
INT_IN : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_CPU;
component sseg_dec is
Port ( ALU_VAL : in std_logic_vector(7 downto 0);
SIGN : in std_logic;
VALID : in std_logic;
CLK : in std_logic;
DISP_EN : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(7 downto 0));
end component;
-- Signals for connecting RAT_CPU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
signal s_clk : std_logic := '0';
signal s_interrupt : std_logic := '0';
signal temp_LEDS : std_logic_vector (7 downto 0);
signal temp_SEGMENTS : std_logic_vector (7 downto 0) := x"00";
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0);
-------------------------------------------------------------------------------`
begin
CLK_DIV : Clk_Divider port map (CLK, s_clk);
-- Instantiate RAT_CPU --------------------------------------------------------
CPU: RAT_CPU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RST => RST,
IO_OE => s_load,
INT_IN => s_interrupt,
CLK => S_CLK);
-------------------------------------------------------------------------------
sseg_decoder: sseg_dec
port map( ALU_VAL => temp_SEGMENTS,
SIGN => '0',
VALID => '1',
CLK => s_clk,
DISP_EN => AN,
SEGMENTS => SEGMENTS );
interrupt_gen: process(CLK)
variable cnt : integer := 0;
begin
if(rising_edge(CLK)) then
if(cnt = 1600000) then -- 30 Hz
s_interrupt <= not s_interrupt;
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- MUX for selecting what input to read ---------------------------------------
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES)
begin
case(s_port_id) is
when BUTTONS_ID =>
s_input_port <= "0000" & BUTTONS;
when others =>
s_input_port <= x"00";
end case;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for updating output registers ------------------------------------------
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
case(s_port_id) is
when LEDS_ID =>
temp_LEDS <= s_output_port;
when SEGMENTS_ID =>
temp_SEGMENTS <= s_output_port;
when others =>
end case;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= temp_LEDS;
end Behavioral;
| mit | cbc8694024f38cf10db894adb4c1ca97 | 0.395967 | 4.866388 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_1/sim/RAT_xlslice_0_1.vhd | 1 | 3,202 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_xlslice_0_1 IS
PORT (
Din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_xlslice_0_1;
ARCHITECTURE RAT_xlslice_0_1_arch OF RAT_xlslice_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 10,
DIN_FROM => 7,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_xlslice_0_1_arch;
| mit | 709ac4689f930839196a248f21807a85 | 0.722986 | 4.105128 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_Nexys4DDR.vhdl | 1 | 11,719 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_Nexys4DDR is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- MMCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0
-- CLK_OUT1
-- CLK_OUT2
-- CLK_OUT3
-- CLK_OUT4
architecture rtl of clknet_ClockNetwork_Nexys4DDR is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (200 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_10MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_125MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_10MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_125MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset NOR MMCM_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= NOT MMCM_Locked_d AND MMCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
Locked <= MMCM_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_100MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => MMCM_Clock_10MHz,
O => MMCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => MMCM_Clock_125MHz,
O => MMCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCME2_ADV
generic map (
STARTUP_WAIT => FALSE,
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 10.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => FALSE,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 5.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_DIVIDE => 4,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => 0.0,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_100MHz,
CLKIN2 => ClockIn_100MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_100MHz_BUFG,
CLKFBSTOPPED => open,
CLKOUT0 => MMCM_Clock_200MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_100MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_125MHz,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => MMCM_Clock_10MHz,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
Control_Clock_100MHz <= Control_Clock_BUFR;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_125MHz <= MMCM_Clock_125MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
Clock_10MHz <= MMCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | 4478b1ca02ddd4f3bf130aea31aba8a1 | 0.523253 | 3.649642 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/mem/sdram/memtest_de0_pll.vhd | 1 | 18,187 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: memtest_de0_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memtest_de0_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END memtest_de0_pll;
ARCHITECTURE SYN OF memtest_de0_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
clk2_divide_by => 3,
clk2_duty_cycle => 50,
clk2_multiply_by => 8,
clk2_phase_shift => "-1640",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=memtest_de0_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "66.666664"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "133.333328"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "133.333328"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.64000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_de0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1640"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memtest_de0_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| apache-2.0 | 24842a808984148e87ffdb73dadd9e81 | 0.7005 | 3.279892 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/Multiplicador.vhd | 1 | 3,732 | ----------------------------------------------------------------------------------
-- Create Date: 15:41:26 04/11/2017
-- Module Name: Multiplicador - Behavioral
-- x3y0 x2y0 x1y0 x0y0
-- x3y1 x2y1 x1y1 x0y1
-- x3y2 x2Y2 x1Y2 x0y2
-- + x3y3 x2y3 x1y3 x0y3
-- --------------------------------------------
-- Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplicador is
port( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Z : out std_logic_vector (7 downto 0)
);
end Multiplicador;
architecture Behavioral of Multiplicador is
component Somador1bit
port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC
);
end component;
signal CoutVectorNivel1: STD_LOGIC_VECTOR(2 downto 0);
signal CoutVectorNivel2: STD_LOGIC_VECTOR(2 downto 0);
signal CoutVectorNivel3: STD_LOGIC_VECTOR(2 downto 0);
signal auxSomaNivel1: STD_LOGIC_VECTOR(3 downto 0);
signal auxSomaNivel2: STD_LOGIC_VECTOR(3 downto 0);
signal auxANDS: STD_LOGIC_VECTOR(14 downto 0);
begin
auxANDS(0) <= A(1) and B(0);
auxANDS(1) <= A(0) and B(1);
auxANDS(2) <= A(2) and B(0);
auxANDS(3) <= A(1) and B(1);
auxANDS(4) <= A(3) and B(0);
auxANDS(5) <= A(2) and B(1);
auxANDS(6) <= A(3) and B(1);
auxANDS(7) <= A(0) and B(2);
auxANDS(8) <= A(1) and B(2);
auxANDS(9) <= A(2) and B(2);
auxANDS(10) <= A(3) and B(2);
auxANDS(11) <= A(0) and B(3);
auxANDS(12) <= A(1) and B(3);
auxANDS(13) <= A(2) and B(3);
auxANDS(14) <= A(3) and B(3);
Z(0) <= A(0) and B(0); -- R0
S1: Somador1bit port map(auxANDS(0), auxANDS(1), '0', CoutVectorNivel1(0), Z(1), p => open, g => open); -- R1
S2: Somador1bit port map(auxANDS(2), auxANDS(3), CoutVectorNivel1(0), CoutVectorNivel1(1), auxSomaNivel1(0), p => open, g => open); -- Soma parcial do R2 //primeiro nível da soma;
S3: Somador1bit port map(auxANDS(4), auxANDS(5), CoutVectorNivel1(1), CoutVectorNivel1(2), auxSomaNivel1(1), p => open, g => open); -- Somap parcial do R3//primeiro nível de soma;
S4: Somador1bit port map(auxANDS(6), '0', CoutVectorNivel1(2), auxSomaNivel1(2), auxSomaNivel1(3), p => open, g => open); -- Soma parcial do R4 e do R5//primeiro nível de soma;
S5: Somador1bit port map(auxANDS(7), auxSomaNivel1(0), '0', CoutVectorNivel2(0), Z(2), p => open, g => open);--R2// segundo nível de soma;
S6: Somador1Bit port map(auxANDS(8), auxSomaNivel1(1), CoutVectorNivel2(0), CoutVectorNivel2(1), auxSomaNivel2(0), p => open, g => open);--Soma parciel do R3//segundo nível de soma;
S7: Somador1Bit port map(auxANDS(9), auxSomaNivel1(2), CoutVectorNivel2(1), CoutVectorNivel2(2), auxSomaNivel2(1), p => open, g => open);--Soma parcial do R4//segundo nível de soma;
S8: Somador1Bit port map(auxANDS(10), auxSomaNivel1(3), CoutVectorNivel2(2), auxSomaNivel2(3), auxSomaNivel2(2), p => open, g => open); --Soma Parcial do R5// segundo nível de soma;
S9: Somador1Bit port map(auxANDS(11), auxSomaNivel2(0), '0', CoutVectorNivel3(0),Z(3), p => open, g => open);--R3//terceiro nível de soma;
S10:Somador1Bit port map(auxANDS(12), auxSomaNivel2(1), CoutVectorNivel3(0), CoutVectorNivel3(1),Z(4), p => open, g => open);--R4//terceiro nível de soma;
S11:Somador1Bit port map(auxANDS(13), auxSomaNivel2(2), CoutVectorNivel3(1), CoutVectorNivel3(2),Z(5), p => open, g => open);--R5//terceiro nível de soma;
S12:Somador1Bit port map(auxANDS(14), '0', CoutVectorNivel3(2), Z(7), Z(6), p => open, g => open);--R6 e R7//terceiro nível de soma;
end Behavioral;
| gpl-3.0 | 99bbc17b3d29637f689a6a66cc3d1fae | 0.61522 | 2.881853 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/ULA_MODULO.vhd | 1 | 4,660 | ----------------------------------------------------------------------------------
-- Create Date: 15:42:12 04/18/2017
-- Module Name: ULA_MODULO - Behavioral
-- 000 - And
-- 001 - Or
-- 010 - Not
-- 011 - Xor
-- 100 - Soma
-- 101 - Subtração
-- 110 - Multiplicação
-- 111 - Incrementação
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ULA_MODULO is
Port ( A: in STD_LOGIC_VECTOR (3 downto 0); -- Entrada1
B: in STD_LOGIC_VECTOR (3 downto 0); -- Entrada2
Controle : in STD_LOGIC_VECTOR (2 downto 0); -- Vetor de Controle(S2S1S0)
Z: out STD_LOGIC_VECTOR(7 downto 0) -- Saída
);
end ULA_MODULO;
architecture Behavioral of ULA_MODULO is
component AND_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component OR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Inversor is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component XOR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Somador4bits
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Ov : out STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Subtrator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0);
Ov : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
component Multiplicador is
port( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Z : out std_logic_vector (7 downto 0)
);
end component;
component incrementador is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal SaidaAux: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux1: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux2: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux3: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux4: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux5: STD_LOGIC_VECTOR(3 downto 0);
signal SaidaAux6: STD_LOGIC_VECTOR(7 downto 0);
signal SaidaAux7: STD_LOGIC_VECTOR(3 downto 0);
signal FlagCarrySoma, FlagOvSoma: STD_LOGIC;
signal FlagCarrySub, FlagOvSub: STD_LOGIC;
begin
Operacao1: AND_BitABit port map(A, B, SaidaAux);
Operacao2: OR_BitABit port map(A, B, SaidaAux1);
Operacao3: Inversor port map(A, SaidaAux2);
Operacao4: XOR_BitABit port map(A, B, SaidaAux3);
Operacao5: Somador4bits port map( A, B, Cin => '0', Cout => FlagCarrySoma, Ov => FlagOvSoma, Z => SaidaAux4); -- Z(4): Flag Cout / Z(5): Flag Overflow
Operacao6: Subtrator port map(A, B,O => SaidaAux5, Ov => FlagOvSub, Cout => FlagCarrySub); -- Z(4): Flag Borrow / Z(5): Flag Overflow
Operacao7: Multiplicador port map( A, B, SaidaAux6);
Operacao8: Incrementador port map( A, SaidaAux7);
process(Controle, SaidaAux, SaidaAux1, SaidaAux2, SaidaAux3, SaidaAux4, SaidaAux5, SaidaAux6, SaidaAux7,
FlagCarrySoma, FlagOvSoma, FlagCarrySub, FlagOvSub)
begin
case Controle is
when "000" => Z(7 downto 4) <= "0000"; -- 000 - And
Z(3 downto 0) <= SaidaAux;
when "001" => Z(7 downto 4) <= "0000"; -- 001 - Or
Z(3 downto 0) <= SaidaAux1;
when "010" => Z(7 downto 4) <= "0000"; -- 010 - Not
Z(3 downto 0) <= SaidaAux2;
when "011" => Z(7 downto 4) <= "0000"; -- 011 - Xor
Z(3 downto 0) <= SaidaAux3;
when "100" => Z(3 downto 0) <= SaidaAux4; -- 100 - Soma
Z(5 downto 4) <= "00";
Z(7) <= FlagCarrySoma;
Z(6) <= FlagOvSoma;
when "101" => Z(3 downto 0) <= SaidaAux5; -- 101 - Subtração
Z(5 downto 4) <= "00";
Z(7) <= NOT(FlagCarrySub);
Z(6) <= FlagOvSub;
when "110" => Z <= SaidaAux6; -- 110 - Multiplicação
when "111" => Z(7 downto 4) <= "0000"; -- 111 - Incrementação
Z(3 downto 0) <= SaidaAux7;
when others => Z <= "00000000";
end case;
end process;
end Behavioral;
| gpl-3.0 | 868c34d0e59505d008c743ae5f0d38d3 | 0.577039 | 3.312011 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_0/RAT_FlagReg_0_0_sim_netlist.vhdl | 2 | 2,920 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:34 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_0_0/RAT_FlagReg_0_0_sim_netlist.vhdl
-- Design : RAT_FlagReg_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_FlagReg_0_0_FlagReg is
port (
OUT_FLAG : out STD_LOGIC;
IN_FLAG : in STD_LOGIC;
SET : in STD_LOGIC;
LD : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_FlagReg_0_0_FlagReg : entity is "FlagReg";
end RAT_FlagReg_0_0_FlagReg;
architecture STRUCTURE of RAT_FlagReg_0_0_FlagReg is
signal \^out_flag\ : STD_LOGIC;
signal OUT_FLAG_i_1_n_0 : STD_LOGIC;
begin
OUT_FLAG <= \^out_flag\;
OUT_FLAG_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACAC"
)
port map (
I0 => IN_FLAG,
I1 => SET,
I2 => LD,
I3 => CLR,
I4 => \^out_flag\,
O => OUT_FLAG_i_1_n_0
);
OUT_FLAG_reg: unisim.vcomponents.FDRE
port map (
C => CLK,
CE => '1',
D => OUT_FLAG_i_1_n_0,
Q => \^out_flag\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_FlagReg_0_0 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_FlagReg_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_FlagReg_0_0 : entity is "RAT_FlagReg_0_0,FlagReg,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_FlagReg_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_FlagReg_0_0 : entity is "FlagReg,Vivado 2016.4";
end RAT_FlagReg_0_0;
architecture STRUCTURE of RAT_FlagReg_0_0 is
begin
U0: entity work.RAT_FlagReg_0_0_FlagReg
port map (
CLK => CLK,
CLR => CLR,
IN_FLAG => IN_FLAG,
LD => LD,
OUT_FLAG => OUT_FLAG,
SET => SET
);
end STRUCTURE;
| mit | b53369d34a8d2b47871e9db7fef6d2ea | 0.606849 | 3.447462 | false | false | false | false |
BBN-Q/VHDL-Components | src/PCG_XSH_RR.vhd | 1 | 3,048 | ----
-- Original author: Blake Johnson
-- Copyright 2017, Raytheon BBN Technologies
--
-- A pseudorandom number generator of the PCG family (M.E. O'Neill 2017).
-- The specific version we choose is the "PGC-XSH-RR" generator which combines
-- a simple LCG with a permutation function composed of an xorshift and a bit
-- rotation. The implementation is pipelined to allow it to run at high clock
-- speeds.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity PCG_XSH_RR is
port (
rst : in std_logic;
clk : in std_logic;
seed : in std_logic_vector(63 downto 0);
rand : out std_logic_vector(31 downto 0);
valid : out std_logic
);
end entity;
architecture arch of PCG_XSH_RR is
signal state : unsigned(63 downto 0);
signal oldstate : unsigned(63 downto 0);
type permutation_state_t is (LCG, XORSHIFT_STATE, ROTATION_STATE);
signal perm_state : permutation_state_t := XORSHIFT_STATE;
-- process signals
signal xorshift : unsigned(31 downto 0);
signal tmp1 : unsigned(63 downto 0);
signal tmp2 : unsigned(63 downto 0);
signal tmp3 : unsigned(63 downto 0);
signal tmp4 : unsigned(63 downto 0);
begin
pcg : process(clk)
-- multiplicative constant comes from PCG basic implementation
-- https://github.com/imneme/pcg-c-basic
constant LCG_MULT : unsigned(63 downto 0) := 64d"6364136223846793005";
constant LCG_ADD : unsigned(63 downto 0) := 64d"2531011"; -- can be any odd number
variable rotation : natural range 0 to 31 := 0;
begin
if rising_edge(clk) then
if rst = '1' then
state <= unsigned(seed);
valid <= '0';
perm_state <= LCG;
else
case (perm_state) is
when LCG =>
oldstate <= state;
-- break down computation of LCG_MULT * state into 3 pieces:
tmp1 <= LCG_MULT(63 downto 32) * state(31 downto 0);
tmp2 <= LCG_MULT(31 downto 0) * state(63 downto 32);
tmp3 <= LCG_MULT(31 downto 0) * state(31 downto 0);
valid <= '0';
perm_state <= XORSHIFT_STATE;
when XORSHIFT_STATE =>
-- compute 32-bit xorshift
-- xorshift := (state ^ (state >> 18)) >> 27
xorshift <= oldstate(58 downto 27) xor (13x"0000" & oldstate(63 downto 45));
rotation := to_integer(oldstate(63 downto 59));
-- finish LCG_MULT * state calculation
tmp4 <= shift_left(tmp1, 32) + shift_left(tmp2, 32) + tmp3;
valid <= '0';
perm_state <= ROTATION_STATE;
when ROTATION_STATE =>
rand <= std_logic_vector(rotate_right(xorshift, rotation));
valid <= '1';
-- finish LCG update
state <= tmp4 + LCG_ADD;
perm_state <= LCG;
end case;
end if;
end if;
end process;
end architecture;
| mpl-2.0 | 9553e5a374fcaaa222fc7535505ffd48 | 0.586286 | 3.912709 | false | false | false | false |
open-power/snap | actions/hdl_nvme_example/hw/action_axi_nvme.vhd | 1 | 10,701 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
USE ieee.numeric_std.all;
ENTITY action_axi_nvme IS
GENERIC (
-- Thread ID Width
C_M_AXI_ID_WIDTH : INTEGER := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : INTEGER := 32;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : INTEGER := 1
);
PORT (
nvme_cmd_valid_i : IN STD_LOGIC;
nvme_cmd_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
nvme_mem_addr_i : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
nvme_lba_addr_i : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
nvme_lba_count_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
nvme_busy_o : OUT STD_LOGIC;
nvme_complete_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BUSER : IN STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RUSER : IN STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 DOWNTO 0);
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC
);
END action_axi_nvme;
ARCHITECTURE action_axi_nvme OF action_axi_nvme IS
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
FUNCTION clogb2 (bit_depth : INTEGER) RETURN INTEGER IS
VARIABLE depth : INTEGER := bit_depth;
VARIABLE count : INTEGER := 1;
BEGIN
FOR clogb2 IN 1 TO bit_depth LOOP -- Works for up to 32 bit integers
IF (bit_depth <= 2) THEN
count := 1;
ELSE
IF (depth <= 1) THEN
count := count;
ELSE
depth := depth / 2;
count := count + 1;
END IF;
END IF;
END LOOP;
RETURN(count);
END;
FUNCTION or_reduce (SIGNAL arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result : STD_LOGIC;
BEGIN
result := '0';
FOR i IN arg'low TO arg'high LOOP
result := result OR arg(i);
END LOOP; -- i
RETURN result;
END or_reduce;
SIGNAL axi_awaddr : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_awvalid : STD_LOGIC;
SIGNAL axi_wdata : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL axi_wlast : STD_LOGIC;
SIGNAL axi_wvalid : STD_LOGIC;
SIGNAL axi_wstrb : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL axi_bready : STD_LOGIC;
SIGNAL axi_araddr : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_arvalid : STD_LOGIC;
SIGNAL axi_rready : STD_LOGIC;
SIGNAL axi_awlen : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL axi_arlen : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL continue_polling : STD_LOGIC;
SIGNAL start_polling : STD_LOGIC;
SIGNAL cmd_complete : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wr_count : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL index : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
M_AXI_AWID <= (OTHERS => '0');
M_AXI_AWADDR <= axi_awaddr;
M_AXI_AWLEN <= axi_awlen;
M_AXI_AWSIZE <= STD_LOGIC_VECTOR( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= "00";
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (OTHERS => '0');
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= (OTHERS => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (OTHERS => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (OTHERS => '0');
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARLEN <= axi_arlen;
M_AXI_ARSIZE <= STD_LOGIC_VECTOR( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= "00";
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (OTHERS => '0');
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
-- data for NVMe host write burst
WITH wr_count SELECT axi_wdata <=
nvme_mem_addr_i(31 DOWNTO 0) WHEN x"5",
nvme_mem_addr_i(63 DOWNTO 32) WHEN x"4",
nvme_lba_addr_i(31 DOWNTO 0) WHEN x"3",
nvme_lba_addr_i(63 DOWNTO 32) WHEN x"2",
nvme_lba_count_i(31 DOWNTO 0) WHEN x"1",
(31 DOWNTO 12 => '0') & nvme_cmd_i WHEN OTHERS ;
axi_wlast <= '1' WHEN wr_count = x"0" ELSE '0';
axi_awaddr <= (OTHERS => '0');
axi_awlen <= x"05";
axi_w: PROCESS(M_AXI_ACLK)
BEGIN
IF (rising_edge (M_AXI_ACLK)) THEN
-- wait for valid command
IF nvme_cmd_valid_i = '1' THEN
-- send command to NVMe host
axi_awvalid <= '1';
wr_count <= x"5";
axi_wvalid <= '1';
nvme_busy_o <= '1';
END IF;
IF axi_awvalid = '1' AND M_AXI_AWREADY = '1' THEN
axi_awvalid <= '0';
axi_bready <= '1';
END IF;
start_polling <= '0';
-- wait until command has been send to NVMe host
-- and then start polling for completion
IF M_AXI_BVALID = '1' AND axi_bready = '1' THEN
axi_bready <= '0';
nvme_busy_o <= '0';
IF wr_count = x"f" THEN
start_polling <= '1';
END IF;
END IF;
IF axi_wvalid = '1' AND M_AXI_WREADY = '1' THEN
wr_count <= wr_count - '1';
IF wr_count = x"0" THEN
axi_wvalid <= '0';
END IF;
END IF;
IF M_AXI_ARESETN = '0' THEN
axi_awvalid <= '0';
axi_bready <= '0';
axi_wvalid <= '0';
nvme_busy_o <= '0';
END IF;
END IF;
END PROCESS;
axi_arlen <= x"00";
-- poll NVMe host Action Track register until
-- bit 0 (command complete) or
-- bit 1 (error) is set
axi_r: PROCESS(M_AXI_ACLK)
VARIABLE polling_started : STD_LOGIC;
BEGIN
IF (rising_edge (M_AXI_ACLK)) THEN
continue_polling <= '0';
nvme_complete_o(1 DOWNTO 0) <= "00";
IF polling_started = '0' AND start_polling = '1' THEN
continue_polling <= '1';
polling_started := '1';
END IF;
IF continue_polling = '1' THEN
axi_arvalid <= '1';
END IF;
IF axi_arvalid = '1' AND M_AXI_ARREADY = '1' THEN
axi_arvalid <= '0';
axi_rready <= '1';
END IF;
index <= axi_araddr(6 DOWNTO 0) - x"4";
IF M_AXI_RVALID = '1' AND axi_rready = '1' THEN
continue_polling <= '1';
IF axi_araddr(6 DOWNTO 0) = "0000000" THEN
FOR i IN 16 TO 31 LOOP
IF M_AXI_RDATA(i) = '1' THEN
axi_araddr(7 DOWNTO 0) <= x"00" + STD_LOGIC_VECTOR(to_unsigned(i-15,5))* "100";
END IF;
END LOOP; -- i
ELSE
nvme_complete_o <= index(5 DOWNTO 2) & "00" & M_AXI_RDATA(1 DOWNTO 0);
axi_araddr(6 DOWNTO 0) <= "0000000";
END IF;
END IF;
IF (M_AXI_ARESETN = '0' ) THEN
axi_arvalid <= '0';
axi_rready <= '0';
axi_araddr <= x"0000_0000";
polling_started := '0';
END IF;
END IF;
END PROCESS;
END action_axi_nvme;
| apache-2.0 | 59cb46b31df8499b1997a4634c7be79a | 0.551444 | 3.188617 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/programCounter.vhd | 1 | 1,054 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity programCounter is
Port ( D_IN : in STD_LOGIC_VECTOR (9 downto 0);
PC_OE : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_INC : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
PC_COUNT : out STD_LOGIC_VECTOR (9 downto 0);
PC_TRI : out STD_LOGIC_VECTOR (9 downto 0));
end programCounter;
architecture Behavioral of programCounter is
signal pcCountSig : STD_LOGIC_VECTOR (9 downto 0);
begin
process (PC_LD, PC_INC, pcCountSig, CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
pcCountSig <= "0000000000";
elsif (PC_LD = '1') then
pcCountSig <= D_IN;
elsif (PC_INC = '1') then
pcCountSig <= pcCountSig + 1;
end if;
end if;
end process;
PC_COUNT <= pcCountSig;
PC_TRI <= pcCountSig when PC_OE = '1'
else (others => 'Z');
end Behavioral;
| mit | c6f2ca583a780f35ba7f409080153117 | 0.544592 | 3.75089 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment4-AsmLangIntro/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000082004A10CA038A142A586B026AFE3440";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "00000000000000000000000000003A3F00000000000000000000000000000000";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000082004A10CA038A142A586B026AFE3440",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000003A3F00000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | 98894e222893ffe40094a61f32b03904 | 0.735725 | 6.466168 | false | false | false | false |
ErikAndren/SG90-PWM | ClkDiv.vhd | 1 | 996 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Types.all;
use ieee.std_logic_unsigned.all;
entity ClkDiv is
generic (
SourceFreq : positive;
SinkFreq : positive
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end;
architecture Behavioral of ClkDiv is
signal temporal: STD_LOGIC;
constant Period : positive := SourceFreq / SinkFreq;
constant HalfPeriod : positive := Period / 2;
signal counter : word(bits(HalfPeriod)-1 downto 0);
begin
freq_divider: process (reset, clk) begin
if (reset = '0') then
temporal <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if (counter = HalfPeriod-1) then
temporal <= not temporal;
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | gpl-2.0 | 705b603db4218427b12621e4777c23b7 | 0.565261 | 3.875486 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Somador/bcd_adder.vhd | 2 | 649 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bcd_adder IS
PORT (
a, b : IN unsigned(3 DOWNTO 0); -- input numbers.
carry_in : IN unsigned (3 DOWNTO 0);
sum : OUT unsigned(3 DOWNTO 0);
carry : OUT unsigned(3 DOWNTO 0)
);
END bcd_adder;
ARCHITECTURE arch OF bcd_adder IS
BEGIN
PROCESS (a, b, carry_in)
VARIABLE sum_temp : unsigned(4 DOWNTO 0);
BEGIN
sum_temp := (('0' & a) + ('0' & b)) + ('0' & carry_in);
IF (sum_temp > 9) THEN
carry <= "0001";
sum <= resize((sum_temp + "00110"), 4);
ELSE
carry <= "0000";
sum <= sum_temp(3 DOWNTO 0);
END IF;
END PROCESS;
END arch; | gpl-3.0 | 936a7d304b0e58ff66241209eb16d733 | 0.599384 | 2.715481 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/debounce_one_shot_FSM.vhd | 1 | 4,585 | --------------------------------------------------------------------------
--
-- Engineer: Jeff Gerfen
-- Create Date: 2016.02.26
-- Design Name: db_1shot_fsm
-- Module Name: db_1shot_fsm
--
-- DESCRIPTION:
-- FSM-based debouncer with integrated one-shot output.
-- One-shot output directly follows successfull completion of debouncing
-- the rising edge and then the falling edged of the input signal.
--
-- CONFIGURABLE PARAMETERS:
-- c_LOW_GOING_HIGH_CLOCKS = minimum # clocks for stable high input
-- c_HIGH_GOING_LOW_CLOCKS = minimum # clocks for stable low input
-- c_ONE_SHOT_CLOCKS = length of one shot output pulse in clk cycles
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity db_1shot_FSM is
Port ( A : in STD_LOGIC;
CLK : in STD_LOGIC;
A_DB : out STD_LOGIC);
end db_1shot_FSM;
architecture Behavioral of db_1shot_FSM is
constant c_LOW_GOING_HIGH_CLOCKS : std_logic_vector := x"19"; -- 25 clks
constant c_HIGH_GOING_LOW_CLOCKS : std_logic_vector := x"33"; -- 50 clks
constant c_ONE_SHOT_CLOCKS : std_logic_vector := x"03"; -- 3 clks
component db_1shot_counter is
Port ( RST : in STD_LOGIC;
CLK : in STD_LOGIC;
INC : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (7 downto 0));
end component;
type state_type is (ST_init,
ST_A_low,
ST_A_low_to_high,
ST_A_high,
ST_A_high_to_low,
ST_one_shot);
signal PS,NS : state_type;
signal s_db_count: std_logic_vector (7 downto 0) := x"00";
signal s_count_rst : std_logic := '0';
signal s_count_inc : std_logic := '0';
begin
bounce_counter: db_1shot_counter
port map (RST => s_count_rst,
CLK => CLK,
INC => s_count_inc,
COUNT => s_db_count);
sync_p: process (CLK, PS, NS)
begin
if (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
comb_p: process (PS, A, s_db_count)
begin
-- default values for signals
--s_db_count <= x"00";
NS <= ST_init;
A_DB <= '0';
s_count_rst <= '0';
s_count_inc <= '0';
case PS is
-- INITIALIZATION
when ST_init =>
NS <= ST_A_low;
A_DB <= '0';
s_count_rst <= '1'; -- reset the bounce counter
-- input is low, waiting for a one
when ST_A_low =>
if (A = '1') then
NS <= ST_A_low_to_high;
s_count_inc <= '1';
else
NS <= ST_A_low;
s_count_rst <= '1';
end if;
-- waiting for a sufficient number of 1s for bouncing to be complete
when ST_A_low_to_high =>
if (A = '1') then
if (s_db_count = c_LOW_GOING_HIGH_CLOCKS) then
NS <= ST_A_high;
s_count_rst <= '1';
else
NS <= ST_A_low_to_high;
s_count_inc <= '1';
end if;
else
NS <= ST_A_low;
s_count_rst <= '1';
end if;
-- input has gone high
when ST_A_high =>
if (A = '1') then
NS <= ST_A_high;
else
NS <= ST_A_high_to_low;
s_count_rst <= '1';
end if;
-- waiting for a sufficient number of 0s for bouncing to be complete
when ST_A_high_to_low =>
if (A = '0') then
if (s_db_count = c_HIGH_GOING_LOW_CLOCKS) then
NS <= ST_one_shot;
s_count_rst <= '1';
else
NS <= ST_A_high_to_low;
s_count_inc <= '1';
end if;
else
NS <= ST_A_high;
s_count_rst <= '1';
end if;
-- first clock of one shot
when ST_one_shot =>
if(s_db_count = c_ONE_SHOT_CLOCKS) then -- done generating the one shot pulse out
NS <= ST_init;
s_count_rst <= '1';
A_DB <= '0';
else
NS <= ST_one_shot;
s_count_inc <= '1';
A_DB <= '1';
end if;
when others =>
s_count_rst <= '0';
s_count_rst <= '0';
NS <= ST_init;
A_DB <= '0';
end case;
end process comb_p;
end Behavioral;
| mit | 3b99a219bba9526665258ad6624e33dc | 0.46434 | 3.565319 | false | false | false | false |
stefanct/aua | hw/if/sim/tb.vhd | 1 | 1,933 | library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity if_tb is
end if_tb;
architecture if_test of if_tb is
component ent_if is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register outputs
opcode : out opcode_t;
dest : out reg_t;
pc_out : out word_t;
rega : out reg_t;
regb : out reg_t;
imm : out std_logic_vector(7 downto 0);
-- asynchron register outputs
async_rega : out reg_t;
async_regb : out reg_t;
-- branches (from ID)
pc_in : in word_t;
branch : in std_logic;
-- mmu
instr_addr : out word_t;
instr_data : in word_t
);
end component;
signal clk : std_logic;
signal reset : std_logic;
-- pipeline register outputs
signal opcode : opcode_t;
signal dest : reg_t;
signal pc_out : word_t;
signal rega : reg_t;
signal regb : reg_t;
signal imm : std_logic_vector(7 downto 0);
signal async_rega : reg_t;
signal async_regb : reg_t;
-- branches (from ID)
signal pc_in : word_t;
signal branch : std_logic;
-- mmu
signal instr_addr : word_t;
signal instr_data : word_t;
begin
if1: ent_if
port map(clk, reset, opcode, dest, pc_out, rega, regb, imm, async_rega, async_regb, pc_in, branch, instr_addr, instr_data);
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset <= '1';
pc_in <= "1111111111111111";
branch <= '0';
instr_data <= "1100110010101010";
icwait(2);
--
reset <= '0';
icwait(1);
--
branch <= '1';
icwait(1);
--
branch <= '0';
instr_data <= "0000110010101010";
icwait(100);
--
end process TEST;
end if_test; | gpl-3.0 | 988d0708cc66a5130299c120daf95313 | 0.579928 | 2.876488 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_0/sim/design_1_cic_compiler_0_0.vhd | 2 | 7,234 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 14,
C_OUTPUT_WIDTH => 33,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 33,
C_C2 => 33,
C_C3 => 33,
C_C4 => 33,
C_C5 => 0,
C_C6 => 0,
C_I1 => 33,
C_I2 => 33,
C_I3 => 33,
C_I4 => 33,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
| mit | 3f1d8c82a2edaceb360ecbf8e7b937df | 0.651092 | 3.325977 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/CarryLookAhead.vhd | 1 | 1,021 | ----------------------------------------------------------------------------------
-- Create Date: 16:21:45 03/28/2017
-- Module Name: CarryLookAhead - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CarryLookAhead is
Port ( P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC;
CLH : out STD_LOGIC_VECTOR (4 downto 0));
end CarryLookAhead;
architecture Behavioral of CarryLookAhead is
signal Aux2: STD_LOGIC_VECTOR (4 downto 0); -- Para o vetor de carry
begin
Aux2(0) <= C;
Aux2(1)<= G(0) or (P(0) and Aux2(0));
Aux2(2)<= G(1) or (P(1) and Aux2(1));
Aux2(3)<= G(2) or (P(2) and Aux2(2));
Aux2(4)<= G(3) or (P(3) and Aux2(3));
-- process(G, P, Aux2)
-- Aux2(0) <= C;
-- GEN_CARRY: for I in 1 to generate
-- Aux2(I)<= G(I-1) or (P(I-1) and Aux2(I-1));
-- end generate GEN_CARRY;
-- end process;
CLH <= Aux2;
end Behavioral;
| gpl-3.0 | b03f8072684c30c1ba6754ee95ebdc7c | 0.503428 | 2.942363 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/RTL/ControlUnit.vhd | 1 | 11,112 | ----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 20:59:29 02/04/2013
-- Design Name:
-- Module Name: RAT_CPU - Behavioral
-- Project Name: RAT MCU
-- Target Devices:
-- Tool versions:
-- Description: This is the control unit of the RAT MCU.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ControlUnit is
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC);
end ControlUnit;
architecture Behavioral of ControlUnit is
-- State machine signals
type state_type is (ST_init, ST_fet, ST_exec, ST_int);
signal PS,NS : state_type;
-- Opcode
signal sig_OPCODE_7: std_logic_vector (6 downto 0);
begin
-- Assign next state
sync_p: process (CLK, NS, RST)
begin
if (RST = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
-- Translate instruction to signals
comb_p: process (OPCODE_HI_5, OPCODE_LO_2, sig_OPCODE_7, C, Z, PS, NS, INT) begin
sig_OPCODE_7 <= OPCODE_HI_5 & OPCODE_LO_2;
case PS is
-- STATE: the init cycle ------------------------------------
when ST_init =>
NS <= ST_fet;
-- Initialize all control outputs to non-active states and reset the PC and SP to all zeros.
PC_LD <= '1'; PC_MUX_SEL <= "00"; PC_RESET <= '1'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '1';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the fetch cycle -----------------------------------
when ST_fet =>
NS <= ST_exec;
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '1';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if (INT = '1') then
NS <= ST_int;
else
NS <= ST_fet;
end if;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000"; ALU_OPY_SEL <= '0';
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
if (sig_OPCODE_7 = "0010000") then -- BRN
PC_LD <= '1';
elsif (sig_OPCODE_7 = "0000010") then -- EXOR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10010" ) then -- EXOR reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
ALU_OPY_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11001" ) then -- IN
RF_WR <= '1';
RF_WR_SEL <= "11";
elsif (sig_OPCODE_7 = "0001001") then -- MOV reg-reg
RF_WR <= '1';
ALU_SEL <= "1110";
elsif (OPCODE_HI_5 = "11011" ) then -- MOV reg-immed
RF_WR <= '1';
ALU_SEL <= "1110";
ALU_OPY_SEL <= '1';
elsif (OPCODE_HI_5 = "11010" ) then -- OUT
RF_OE <= '1';
IO_OE <= '1';
else
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end if;
when ST_int =>
NS <= ST_fet;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '1'; PC_MUX_SEL <= "10"; PC_RESET <= '0'; PC_OE <= '1'; PC_INC <= '0';
SP_LD <= '1'; SP_MUX_SEL <= "10"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '1'; SCR_OE <= '0'; SCR_ADDR_SEL <= "11";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '1'; IO_OE <= '0';
when others =>
NS <= ST_fet;
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end case;
end process comb_p;
end Behavioral; | mit | e284239e3cc61af1f78167a19a8e1302 | 0.37968 | 3.316025 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/synth/RAT_Mux4x1_8_0_1.vhd | 1 | 3,970 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_8_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux4x1_8_0_1;
ARCHITECTURE RAT_Mux4x1_8_0_1_arch OF RAT_Mux4x1_8_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_8_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux4x1_8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux4x1_8_0_1_arch: ARCHITECTURE IS "Mux4x1_8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux4x1_8_0_1_arch : ARCHITECTURE IS "RAT_Mux4x1_8_0_1,Mux4x1_8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux4x1_8_0_1_arch: ARCHITECTURE IS "RAT_Mux4x1_8_0_1,Mux4x1_8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux4x1_8,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux4x1_8
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_8_0_1_arch;
| mit | 87c8caf76e496951b484c8363223010d | 0.719144 | 3.532028 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment3-Program_Counter/IPI-BD/Program_Counter/hdl/Program_Counter_wrapper.vhd | 1 | 1,842 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Oct 16 23:04:57 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target Program_Counter_wrapper.bd
--Design : Program_Counter_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Program_Counter_wrapper is
port (
CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
PC_INC : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
RST : in STD_LOGIC
);
end Program_Counter_wrapper;
architecture STRUCTURE of Program_Counter_wrapper is
component Program_Counter is
port (
PC_LD : in STD_LOGIC;
PC_INC : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component Program_Counter;
begin
Program_Counter_i: component Program_Counter
port map (
CLK => CLK,
FROM_IMMED(9 downto 0) => FROM_IMMED(9 downto 0),
FROM_STACK(9 downto 0) => FROM_STACK(9 downto 0),
PC_COUNT(0 to 9) => PC_COUNT(0 to 9),
PC_INC => PC_INC,
PC_LD => PC_LD,
PC_MUX_SEL(1 downto 0) => PC_MUX_SEL(1 downto 0),
RST => RST
);
end STRUCTURE;
| mit | 09e722ebe01ff763daa8b883194ab9a4 | 0.580347 | 3.555985 | false | false | false | false |
open-power/snap | actions/hdl_nvme_example/hw/action_nvme_example.vhd | 1 | 48,421 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
USE ieee.numeric_std.all;
ENTITY action_nvme_example IS
GENERIC (
-- Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to on-card SDRAM
C_AXI_CARD_MEM0_ID_WIDTH : INTEGER := 2;
C_AXI_CARD_MEM0_ADDR_WIDTH : INTEGER := 33;
C_AXI_CARD_MEM0_DATA_WIDTH : INTEGER := 512;
C_AXI_CARD_MEM0_AWUSER_WIDTH : INTEGER := 1;
C_AXI_CARD_MEM0_ARUSER_WIDTH : INTEGER := 1;
C_AXI_CARD_MEM0_WUSER_WIDTH : INTEGER := 1;
C_AXI_CARD_MEM0_RUSER_WIDTH : INTEGER := 1;
C_AXI_CARD_MEM0_BUSER_WIDTH : INTEGER := 1;
-- Parameters of Axi Slave Bus Interface AXI_CTRL_REG
C_AXI_CTRL_REG_DATA_WIDTH : INTEGER := 32;
C_AXI_CTRL_REG_ADDR_WIDTH : INTEGER := 32;
-- Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
C_AXI_HOST_MEM_ID_WIDTH : INTEGER := 2;
C_AXI_HOST_MEM_ADDR_WIDTH : INTEGER := 64;
C_AXI_HOST_MEM_DATA_WIDTH : INTEGER := 512;
C_AXI_HOST_MEM_AWUSER_WIDTH : INTEGER := 1;
C_AXI_HOST_MEM_ARUSER_WIDTH : INTEGER := 1;
C_AXI_HOST_MEM_WUSER_WIDTH : INTEGER := 1;
C_AXI_HOST_MEM_RUSER_WIDTH : INTEGER := 1;
C_AXI_HOST_MEM_BUSER_WIDTH : INTEGER := 1;
INT_BITS : INTEGER := 3;
CONTEXT_BITS : INTEGER := 8
);
PORT (
action_clk : IN STD_LOGIC;
action_rst_n : IN STD_LOGIC;
int_req_ack : IN STD_LOGIC;
int_req : OUT STD_LOGIC;
int_src : OUT STD_LOGIC_VECTOR(INT_BITS-2 DOWNTO 0);
int_ctx : OUT STD_LOGIC_VECTOR(CONTEXT_BITS-1 DOWNTO 0);
-- Ports of Axi Master Bus Interface AXI_CARD_MEM0
-- to on-card SDRAM
axi_card_mem0_awaddr : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0);
axi_card_mem0_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_card_mem0_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awvalid : OUT STD_LOGIC;
axi_card_mem0_awready : IN STD_LOGIC;
axi_card_mem0_wdata : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0);
axi_card_mem0_wstrb : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_DATA_WIDTH/8-1 DOWNTO 0);
axi_card_mem0_wlast : OUT STD_LOGIC;
axi_card_mem0_wvalid : OUT STD_LOGIC;
axi_card_mem0_wready : IN STD_LOGIC;
axi_card_mem0_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_bvalid : IN STD_LOGIC;
axi_card_mem0_bready : OUT STD_LOGIC;
axi_card_mem0_araddr : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0);
axi_card_mem0_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_card_mem0_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arvalid : OUT STD_LOGIC;
axi_card_mem0_arready : IN STD_LOGIC;
axi_card_mem0_rdata : IN STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0);
axi_card_mem0_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_rlast : IN STD_LOGIC;
axi_card_mem0_rvalid : IN STD_LOGIC;
axi_card_mem0_rready : OUT STD_LOGIC;
axi_card_mem0_arid : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_aruser : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ARUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_awid : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_awuser : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_AWUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_bid : IN STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_buser : IN STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_BUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_rid : IN STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_ruser : IN STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_RUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_wuser : OUT STD_LOGIC_VECTOR(C_AXI_CARD_MEM0_WUSER_WIDTH-1 DOWNTO 0);
--
-- Ports for NVMe control Interface
axi_nvme_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_nvme_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_nvme_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awvalid : OUT STD_LOGIC;
axi_nvme_awready : IN STD_LOGIC;
axi_nvme_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_nvme_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_wlast : OUT STD_LOGIC;
axi_nvme_wvalid : OUT STD_LOGIC;
axi_nvme_wready : IN STD_LOGIC;
axi_nvme_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_bvalid : IN STD_LOGIC;
axi_nvme_bready : OUT STD_LOGIC;
axi_nvme_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_nvme_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_nvme_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arvalid : OUT STD_LOGIC;
axi_nvme_arready : IN STD_LOGIC;
axi_nvme_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
axi_nvme_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_rlast : IN STD_LOGIC;
axi_nvme_rvalid : IN STD_LOGIC;
axi_nvme_rready : OUT STD_LOGIC;
axi_nvme_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_nvme_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-- Ports of Axi Slave Bus Interface AXI_CTRL_REG
axi_ctrl_reg_awaddr : IN STD_LOGIC_VECTOR(C_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_awvalid : IN STD_LOGIC;
axi_ctrl_reg_awready : OUT STD_LOGIC;
axi_ctrl_reg_wdata : IN STD_LOGIC_VECTOR(C_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_wstrb : IN STD_LOGIC_VECTOR((C_AXI_CTRL_REG_DATA_WIDTH/8)-1 DOWNTO 0);
axi_ctrl_reg_wvalid : IN STD_LOGIC;
axi_ctrl_reg_wready : OUT STD_LOGIC;
axi_ctrl_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_bvalid : OUT STD_LOGIC;
axi_ctrl_reg_bready : IN STD_LOGIC;
axi_ctrl_reg_araddr : IN STD_LOGIC_VECTOR(C_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_arvalid : IN STD_LOGIC;
axi_ctrl_reg_arready : OUT STD_LOGIC;
axi_ctrl_reg_rdata : OUT STD_LOGIC_VECTOR(C_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_rvalid : OUT STD_LOGIC;
axi_ctrl_reg_rready : IN STD_LOGIC;
-- Ports of Axi Master Bus Interface AXI_HOST_MEM
-- to HOST memory
axi_host_mem_awaddr : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awvalid : OUT STD_LOGIC;
axi_host_mem_awready : IN STD_LOGIC;
axi_host_mem_wdata : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_wstrb : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_DATA_WIDTH/8-1 DOWNTO 0);
axi_host_mem_wlast : OUT STD_LOGIC;
axi_host_mem_wvalid : OUT STD_LOGIC;
axi_host_mem_wready : IN STD_LOGIC;
axi_host_mem_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_bvalid : IN STD_LOGIC;
axi_host_mem_bready : OUT STD_LOGIC;
axi_host_mem_araddr : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arvalid : OUT STD_LOGIC;
axi_host_mem_arready : IN STD_LOGIC;
axi_host_mem_rdata : IN STD_LOGIC_VECTOR(C_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_rlast : IN STD_LOGIC;
axi_host_mem_rvalid : IN STD_LOGIC;
axi_host_mem_rready : OUT STD_LOGIC;
axi_host_mem_arid : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_aruser : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ARUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_awid : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_awuser : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_AWUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_bid : IN STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_buser : IN STD_LOGIC_VECTOR(C_AXI_HOST_MEM_BUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_rid : IN STD_LOGIC_VECTOR(C_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_ruser : IN STD_LOGIC_VECTOR(C_AXI_HOST_MEM_RUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_wuser : OUT STD_LOGIC_VECTOR(C_AXI_HOST_MEM_WUSER_WIDTH-1 DOWNTO 0)
);
END action_nvme_example;
ARCHITECTURE action_nvme_example OF action_nvme_example IS
CONSTANT MAX_REQ_BUFFER : INTEGER := 15;
CONSTANT MAX_SLOT : INTEGER := 15;
TYPE FSM_APP_t IS (IDLE, WAIT_FOR_MEMCOPY_DONE, ILLEGAL_OPERATION);
TYPE FSM_DMA_WR_t IS (IDLE, DMA_WR_REQ);
TYPE FSM_DMA_RD_t IS (IDLE, DMA_RD_REQ, DMA_RD_REQ_2);
SUBTYPE REQ_BUFFER_RANGE_t IS INTEGER RANGE 0 TO (MAX_REQ_BUFFER*2)+1;
SUBTYPE SLOT_RANGE_t IS INTEGER RANGE 0 TO MAX_SLOT;
SUBTYPE REQ_ADDR_TYPE_t IS STD_LOGIC_VECTOR(63 DOWNTO 0);
SUBTYPE REQ_SIZE_TYPE_t IS STD_LOGIC_VECTOR(13 DOWNTO 0);
SUBTYPE SLOT_TYPE_t IS STD_LOGIC_VECTOR( 3 DOWNTO 0);
SUBTYPE SLOT_BITFIELD_TYPE_t IS STD_LOGIC_VECTOR(MAX_SLOT DOWNTO 0);
TYPE NVME_CMD_TYPE_t IS (NVME_READ, NVME_WRITE);
TYPE ADDR_BUFFER_t IS ARRAY (0 TO MAX_SLOT) OF REQ_ADDR_TYPE_t;
TYPE SIZE_BUFFER_t IS ARRAY (0 TO MAX_SLOT) OF REQ_SIZE_TYPE_t;
TYPE CMD_TYPE_BUFFER_t IS ARRAY (0 TO MAX_SLOT) OF NVME_CMD_TYPE_t;
TYPE SLOT_BUFFER_t IS ARRAY (0 TO MAX_REQ_BUFFER) OF SLOT_TYPE_t;
TYPE SLOT_ID_BUFFER_t IS ARRAY (0 TO MAX_REQ_BUFFER) OF SLOT_RANGE_t;
TYPE REQ_ID_FIFO_t IS RECORD
slot : SLOT_ID_BUFFER_t;
head : REQ_BUFFER_RANGE_t;
tail : REQ_BUFFER_RANGE_t;
END RECORD REQ_ID_FIFO_t;
TYPE COMPLETION_FIFO_t IS RECORD
slot : SLOT_BUFFER_t;
head : REQ_BUFFER_RANGE_t;
tail : REQ_BUFFER_RANGE_t;
END RECORD COMPLETION_FIFO_t;
TYPE REQ_BUFFER_t IS RECORD
dest_addr : ADDR_BUFFER_t;
src_addr : ADDR_BUFFER_t;
size : SIZE_BUFFER_t;
cmd_type : CMD_TYPE_BUFFER_t;
rnw : SLOT_BITFIELD_TYPE_t;
busy : SLOT_BITFIELD_TYPE_t;
done : SLOT_BITFIELD_TYPE_t; -- done flag is active for one cycle (turning off busy flag)
END RECORD REQ_BUFFER_t ;
SIGNAL fsm_app_q : fsm_app_t;
SIGNAL fsm_dma_wr : FSM_DMA_WR_t;
SIGNAL fsm_dma_rd : FSM_DMA_RD_t;
SIGNAL req_buffer : REQ_BUFFER_t;
SIGNAL dma_rd_req_fifo : REQ_ID_FIFO_t;
SIGNAL dma_wr_req_fifo : REQ_ID_FIFO_t;
SIGNAL dma_wr_cpl_fifo : REQ_ID_FIFO_t;
SIGNAL nvme_rd_req_fifo : REQ_ID_FIFO_t;
SIGNAL nvme_wr_req_fifo : REQ_ID_FIFO_t;
SIGNAL rd_cpl_fifo : COMPLETION_FIFO_t;
SIGNAL wr_cpl_fifo : COMPLETION_FIFO_t;
SIGNAL completion_fifo : COMPLETION_FIFO_T;
SIGNAL reg_0x20 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x30 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x34 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x38 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x3c : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x40 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x44 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x48 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x50 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL reg_0x54 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL app_start : STD_LOGIC;
SIGNAL app_done : STD_LOGIC;
SIGNAL app_ready : STD_LOGIC;
SIGNAL app_idle : STD_LOGIC;
SIGNAL int_enable : STD_LOGIC;
SIGNAL read_complete_int : BOOLEAN;
SIGNAL write_complete_int : BOOLEAN;
SIGNAL card_mem_wvalid : STD_LOGIC;
SIGNAL host_mem_wvalid : STD_LOGIC;
SIGNAL dma_wr_size : REQ_SIZE_TYPE_t;
SIGNAL nvme_req_arbiter_read : BOOLEAN;
SIGNAL nvme_cmd_valid : STD_LOGIC;
SIGNAL nvme_cmd : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL nvme_mem_addr : STD_LOGIC_VECTOR (63 DOWNTO 0) := X"0000_0002_0000_0000";
SIGNAL nvme_lba_addr : STD_LOGIC_VECTOR (63 DOWNTO 0) := (OTHERS => '0');
SIGNAL nvme_lba_count : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"0000_0007";
SIGNAL nvme_busy : STD_LOGIC;
SIGNAL nvme_complete : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL completion_arbiter_read : BOOLEAN;
SIGNAL host_mem_awvalid : STD_LOGIC;
SIGNAL host_mem_arvalid : STD_LOGIC;
SIGNAL host_mem_awaddr : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL card_mem_arvalid : STD_LOGIC;
SIGNAL card_mem_awvalid : STD_LOGIC;
SIGNAL card_mem_araddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL dma_wr_count : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL reg_0x48_nvme_rd_error : std_logic_vector(MAX_SLOT DOWNTO 0);
SIGNAL reg_0x48_nvme_wr_error : std_logic_vector(MAX_SLOT DOWNTO 0);
SIGNAL reg_0x4c_req_error : STD_LOGIC_VECTOR(MAX_SLOT DOWNTO 0);
SIGNAL reg_0x4c_nvme_error : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL reg_0x4c_completion : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL reg_0x4c_rd_strobe : STD_LOGIC;
SIGNAL reg_0x54_nvme_req : STD_LOGIC_VECTOR(MAX_SLOT DOWNTO 0);
SIGNAL reg_0x54_nvme_rsp : STD_LOGIC_VECTOR(MAX_SLOT DOWNTO 0);
FUNCTION MODFIFO (value : INTEGER) RETURN INTEGER IS
BEGIN -- MODFIFO
RETURN (value MOD (MAX_REQ_BUFFER+1));
END MODFIFO;
FUNCTION INCRPTR (ptr : INTEGER) RETURN INTEGER IS
BEGIN
RETURN MODFIFO(ptr+1);
END INCRPTR;
FUNCTION clogb2 (bit_depth : INTEGER) RETURN INTEGER IS
VARIABLE depth : INTEGER := bit_depth;
VARIABLE count : INTEGER := 1;
BEGIN
FOR clogb2 IN 1 TO bit_depth LOOP -- Works for up to 32 bit integers
IF (bit_depth <= 2) THEN
count := 1;
ELSE
if(depth <= 1) THEN
count := count;
ELSE
depth := depth / 2;
count := count + 1;
END IF;
END IF;
END LOOP;
RETURN(count);
END;
FUNCTION or_reduce (SIGNAL arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result : STD_LOGIC;
begin
result := '0';
FOR i IN arg'low TO arg'high LOOP
result := result or arg(i);
END LOOP; -- i
RETURN result;
END or_reduce;
BEGIN
-- Instantiation of Axi Bus Interface AXI_NVME
action_axi_nvme_inst : ENTITY work.action_axi_nvme
PORT MAP (
nvme_cmd_valid_i => nvme_cmd_valid,
nvme_cmd_i => nvme_cmd,
nvme_mem_addr_i => nvme_mem_addr,
nvme_lba_addr_i => nvme_lba_addr,
nvme_lba_count_i => nvme_lba_count,
nvme_busy_o => nvme_busy,
nvme_complete_o => nvme_complete,
M_AXI_ACLK => action_clk,
M_AXI_ARESETN => action_rst_n,
M_AXI_AWID => axi_nvme_awid,
M_AXI_AWADDR => axi_nvme_awaddr,
M_AXI_AWLEN => axi_nvme_awlen,
M_AXI_AWSIZE => axi_nvme_awsize,
M_AXI_AWBURST => axi_nvme_awburst,
M_AXI_AWLOCK => axi_nvme_awlock,
M_AXI_AWCACHE => axi_nvme_awcache,
M_AXI_AWPROT => axi_nvme_awprot,
M_AXI_AWQOS => axi_nvme_awqos,
M_AXI_AWUSER => axi_nvme_awuser,
M_AXI_AWVALID => axi_nvme_awvalid,
M_AXI_AWREADY => axi_nvme_awready,
M_AXI_WDATA => axi_nvme_wdata,
M_AXI_WSTRB => axi_nvme_wstrb,
M_AXI_WLAST => axi_nvme_wlast,
M_AXI_WUSER => axi_nvme_wuser,
M_AXI_WVALID => axi_nvme_wvalid,
M_AXI_WREADY => axi_nvme_wready,
M_AXI_BID => axi_nvme_bid,
M_AXI_BRESP => axi_nvme_bresp,
M_AXI_BUSER => axi_nvme_buser,
M_AXI_BVALID => axi_nvme_bvalid,
M_AXI_BREADY => axi_nvme_bready,
M_AXI_ARID => axi_nvme_arid,
M_AXI_ARADDR => axi_nvme_araddr,
M_AXI_ARLEN => axi_nvme_arlen,
M_AXI_ARSIZE => axi_nvme_arsize,
M_AXI_ARBURST => axi_nvme_arburst,
M_AXI_ARLOCK => axi_nvme_arlock,
M_AXI_ARCACHE => axi_nvme_arcache,
M_AXI_ARPROT => axi_nvme_arprot,
M_AXI_ARQOS => axi_nvme_arqos,
M_AXI_ARUSER => axi_nvme_aruser,
M_AXI_ARVALID => axi_nvme_arvalid,
M_AXI_ARREADY => axi_nvme_arready,
M_AXI_RID => axi_nvme_rid,
M_AXI_RDATA => axi_nvme_rdata,
M_AXI_RRESP => axi_nvme_rresp,
M_AXI_RLAST => axi_nvme_rlast,
M_AXI_RUSER => axi_nvme_ruser,
M_AXI_RVALID => axi_nvme_rvalid,
M_AXI_RREADY => axi_nvme_rready
);
axi_card_mem0_awid <= (OTHERS => '0');
axi_card_mem0_awsize <= std_logic_vector( to_unsigned(clogb2((C_AXI_CARD_MEM0_DATA_WIDTH/8)-1), 3) );
axi_card_mem0_awburst <= "01";
axi_card_mem0_awlock <= "00";
axi_card_mem0_awcache <= "0010";
axi_card_mem0_awprot <= "000";
axi_card_mem0_awqos <= "0000";
axi_card_mem0_awuser <= (OTHERS => '0');
axi_card_mem0_arid <= (OTHERS => '0');
axi_card_mem0_arsize <= STD_LOGIC_VECTOR( to_unsigned(clogb2((C_AXI_CARD_MEM0_DATA_WIDTH/8)-1), 3) );
axi_card_mem0_arburst <= "01";
axi_card_mem0_arlock <= "00";
axi_card_mem0_arcache <= "0010";
axi_card_mem0_arprot <= "000";
axi_card_mem0_arqos <= "0000";
axi_card_mem0_aruser <= (OTHERS => '0');
axi_host_mem_awid <= (OTHERS => '0');
axi_host_mem_awsize <= STD_LOGIC_VECTOR( to_unsigned(clogb2((C_AXI_HOST_MEM_DATA_WIDTH/8)-1), 3) );
axi_host_mem_awburst <= "01";
axi_host_mem_awlock <= "00";
axi_host_mem_awcache <= "0010";
axi_host_mem_awprot <= "000";
axi_host_mem_awqos <= "0000";
axi_host_mem_awuser <= (OTHERS => '0');
axi_host_mem_arid <= (OTHERS => '0');
axi_host_mem_arsize <= STD_LOGIC_VECTOR( to_unsigned(clogb2((C_AXI_HOST_MEM_DATA_WIDTH/8)-1), 3) );
axi_host_mem_arburst <= "01";
axi_host_mem_arlock <= "00";
axi_host_mem_arcache <= "0010";
axi_host_mem_arprot <= "000";
axi_host_mem_arqos <= "0000";
axi_host_mem_aruser <= (OTHERS => '0');
int_ctx <= reg_0x20(CONTEXT_BITS - 1 DOWNTO 0);
int_src <= "00";
-- Instantiation of Axi Bus Interface AXI_CTRL_REG
action_axi_slave_inst : ENTITY work.action_axi_slave
GENERIC MAP (
C_S_AXI_DATA_WIDTH => C_AXI_CTRL_REG_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_AXI_CTRL_REG_ADDR_WIDTH
)
PORT MAP (
-- config reg ; bit 0 => disable dma and
-- just count down the length regsiter
reg_0x10_i => x"1014_0001", -- action type
reg_0x14_i => x"0000_0000", -- action version
reg_0x20_o => reg_0x20,
reg_0x30_o => reg_0x30,
-- low order source address
reg_0x34_o => reg_0x34,
-- high order source address
reg_0x38_o => reg_0x38,
-- low order destination address
reg_0x3c_o => reg_0x3c,
-- high order destination address
reg_0x40_o => reg_0x40,
-- number of bytes to copy
reg_0x44_o => reg_0x44,
reg_0x48_i => reg_0x48,
reg_0x4c_req_error_i => reg_0x4c_req_error,
reg_0x4c_nvme_error_i => reg_0x4c_nvme_error,
reg_0x4c_completion_i => reg_0x4c_completion,
reg_0x4c_rd_strobe_o => reg_0x4c_rd_strobe,
reg_0x50_i => reg_0x50,
reg_0x54_i => reg_0x54,
int_enable_o => int_enable,
app_start_o => app_start,
app_done_i => app_done,
app_ready_i => app_ready,
app_idle_i => app_idle,
-- User ports ends
S_AXI_ACLK => action_clk,
S_AXI_ARESETN => action_rst_n,
S_AXI_AWADDR => axi_ctrl_reg_awaddr,
S_AXI_AWVALID => axi_ctrl_reg_awvalid,
S_AXI_AWREADY => axi_ctrl_reg_awready,
S_AXI_WDATA => axi_ctrl_reg_wdata,
S_AXI_WSTRB => axi_ctrl_reg_wstrb,
S_AXI_WVALID => axi_ctrl_reg_wvalid,
S_AXI_WREADY => axi_ctrl_reg_wready,
S_AXI_BRESP => axi_ctrl_reg_bresp,
S_AXI_BVALID => axi_ctrl_reg_bvalid,
S_AXI_BREADY => axi_ctrl_reg_bready,
S_AXI_ARADDR => axi_ctrl_reg_araddr,
S_AXI_ARVALID => axi_ctrl_reg_arvalid,
S_AXI_ARREADY => axi_ctrl_reg_arready,
S_AXI_RDATA => axi_ctrl_reg_rdata,
S_AXI_RRESP => axi_ctrl_reg_rresp,
S_AXI_RVALID => axi_ctrl_reg_rvalid,
S_AXI_RREADY => axi_ctrl_reg_rready
);
reg_0x48(31 DOWNTO 16) <= reg_0x48_nvme_rd_error;
reg_0x48(15 DOWNTO 0) <= reg_0x48_nvme_wr_error;
reg_0x50(31 DOWNTO 16) <= req_buffer.busy;
reg_0x50(15 DOWNTO 0) <= req_buffer.rnw;
reg_0x54(31 DOWNTO 16) <= reg_0x54_nvme_req;
reg_0x54(15 DOWNTO 0) <= reg_0x54_nvme_rsp;
-- READ and WRITE requests:
-- Application request FSM
app_request:
PROCESS(action_clk) IS
ALIAS dma_rd_head : REQ_BUFFER_RANGE_t IS dma_rd_req_fifo.head;
ALIAS nvme_rd_head : REQ_BUFFER_RANGE_t IS nvme_rd_req_fifo.head;
VARIABLE slot_id : SLOT_RANGE_t;
VARIABLE src_addr : REQ_ADDR_TYPE_t;
VARIABLE dest_addr : REQ_ADDR_TYPE_t;
VARIABLE size : REQ_SIZE_TYPE_t;
VARIABLE req_valid : BOOLEAN;
VARIABLE cmd_type : NVME_CMD_TYPE_t;
BEGIN
IF (rising_edge(action_clk)) THEN
app_done <= '0';
app_idle <= '0';
app_ready <= '1';
req_valid := FALSE;
slot_id := to_integer(unsigned(reg_0x30(11 DOWNTO 8)));
CASE fsm_app_q IS
WHEN IDLE =>
app_idle <= '1';
IF app_start = '1' THEN
src_addr := reg_0x38 & reg_0x34;
dest_addr := reg_0x40 & reg_0x3c;
size := reg_0x44(13 + 12 downto 12);
CASE reg_0x30(3 DOWNTO 0) IS
WHEN x"3" =>
-- memcopy host to NVMe
req_valid := TRUE;
cmd_type := NVME_WRITE;
req_buffer.rnw(slot_id) <= '0';
dma_rd_req_fifo.slot(MODFIFO(dma_rd_head)) <= slot_id;
IF dma_rd_head = (MAX_REQ_BUFFER*2)+1 THEN
dma_rd_head <= 0;
ELSE
dma_rd_head <= dma_rd_head + 1;
END IF;
WHEN x"4" =>
-- memcopy NVMe to host
req_valid := TRUE;
cmd_type := NVME_READ;
req_buffer.rnw(slot_id) <= '1';
nvme_rd_req_fifo.slot(MODFIFO(nvme_rd_head)) <= slot_id;
IF nvme_rd_head = (MAX_REQ_BUFFER*2)+1 THEN
nvme_rd_head <= 0;
ELSE
nvme_rd_head <= nvme_rd_head + 1;
END IF;
WHEN OTHERS =>
fsm_app_q <= ILLEGAL_OPERATION;
END CASE;
END IF ;
WHEN WAIT_FOR_MEMCOPY_DONE =>
IF app_start = '0' THEN
fsm_app_q <= IDLE;
app_done <= '1';
END IF;
WHEN ILLEGAL_OPERATION =>
fsm_app_q <= IDLE;
app_done <= '1';
WHEN OTHERS => NULL;
END CASE;
req_buffer.busy <= req_buffer.busy AND NOT req_buffer.done;
IF req_valid THEN
req_buffer.src_addr(slot_id) <= src_addr;
req_buffer.dest_addr(slot_id) <= dest_addr;
req_buffer.size(slot_id) <= size;
req_buffer.cmd_type(slot_id) <= cmd_type;
fsm_app_q <= WAIT_FOR_MEMCOPY_DONE;
IF (req_buffer.busy(slot_id) AND NOT req_buffer.done(slot_id)) = '1' THEN
reg_0x4c_req_error(slot_id) <= '1';
END IF;
req_buffer.busy(slot_id) <= '1';
END IF;
IF ( action_rst_n = '0' ) THEN
fsm_app_q <= IDLE;
app_ready <= '0';
app_idle <= '0';
dma_rd_head <= 0;
nvme_rd_head <= 0;
req_buffer.busy <= (OTHERS => '0');
req_buffer.rnw <= (OTHERS => '0');
FOR i IN 0 TO MAX_REQ_BUFFER LOOP
dma_rd_req_fifo.slot(i) <= 0;
nvme_rd_req_fifo.slot(i) <= 0;
END LOOP; -- i
-- Reset debug registers
reg_0x4c_req_error <= (OTHERS => '0');
END IF;
END IF;
END PROCESS app_request;
-- WRITE request:
-- DMA read handling (Host to SDRAM)
axi_host_mem_arvalid <= host_mem_arvalid;
axi_card_mem0_awvalid <= card_mem_awvalid;
dma_read:
PROCESS(action_clk) IS
ALIAS dma_rd_tail : REQ_BUFFER_RANGE_t IS dma_rd_req_fifo.tail;
ALIAS dma_rd_head : REQ_BUFFER_RANGE_t IS dma_rd_req_fifo.head;
ALIAS nvme_wr_head : REQ_BUFFER_RANGE_t IS nvme_wr_req_fifo.head;
VARIABLE slot_id : SLOT_RANGE_t;
VARIABLE req_slot : SLOT_TYPE_t;
BEGIN
IF (rising_edge(action_clk)) THEN
IF axi_host_mem_arready = '1' AND host_mem_arvalid = '1' THEN
host_mem_arvalid <= '0';
END IF;
IF axi_card_mem0_awready = '1' AND card_mem_awvalid = '1' THEN
card_mem_awvalid <= '0';
END IF;
slot_id := dma_rd_req_fifo.slot(MODFIFO(dma_rd_tail));
req_slot := std_logic_vector(to_unsigned(slot_id,4));
CASE fsm_dma_rd IS
WHEN IDLE =>
IF dma_rd_tail /= dma_rd_head THEN
card_mem_awvalid <= '1';
host_mem_arvalid <= '1';
fsm_dma_rd <= DMA_RD_REQ;
END IF;
axi_host_mem_araddr <= req_buffer.src_addr(dma_rd_req_fifo.slot(MODFIFO(dma_rd_tail)));
axi_card_mem0_awaddr <= x"00" & "000" & req_slot & "0" & x"0000";
WHEN DMA_RD_REQ =>
IF axi_card_mem0_bvalid = '1' THEN
IF req_buffer.size(slot_id)(1) = '0' THEN
-- IF all data is written into SDRAM,
-- we can initiate the NVMe write transfer
nvme_wr_req_fifo.slot(MODFIFO(nvme_wr_head)) <= slot_id;
fsm_dma_rd <= IDLE;
IF nvme_wr_head = (MAX_REQ_BUFFER*2)+1 THEN
nvme_wr_head <= 0;
ELSE
nvme_wr_head <= nvme_wr_head + 1;
END IF;
IF dma_rd_tail = (MAX_REQ_BUFFER*2)+1 THEN
dma_rd_tail <= 0;
ELSE
dma_rd_tail <= dma_rd_tail + 1;
END IF;
ELSE
-- 2nd 4 k request
card_mem_awvalid <= '1';
host_mem_arvalid <= '1';
axi_host_mem_araddr <= req_buffer.src_addr(slot_id) + x"1000";
axi_card_mem0_awaddr <= x"00" & "000" & req_slot & "0" & x"1000";
fsm_dma_rd <= DMA_RD_REQ_2;
END IF;
END IF;
WHEN DMA_RD_REQ_2 =>
IF axi_card_mem0_bvalid = '1' THEN
-- initiate the NVMe data transfer
nvme_wr_req_fifo.slot(MODFIFO(nvme_wr_head)) <= slot_id;
fsm_dma_rd <= IDLE;
IF nvme_wr_head = (MAX_REQ_BUFFER*2)+1 THEN
nvme_wr_head <= 0;
ELSE
nvme_wr_head <= nvme_wr_head + 1;
END IF;
IF dma_rd_tail = (MAX_REQ_BUFFER*2)+1 THEN
dma_rd_tail <= 0;
ELSE
dma_rd_tail <= dma_rd_tail + 1;
END IF;
END IF;
WHEN OTHERS => null;
END CASE;
IF action_rst_n = '0' THEN
card_mem_awvalid <= '0';
host_mem_arvalid <= '0';
dma_rd_tail <= 0;
nvme_wr_head <= 0;
fsm_dma_rd <= IDLE;
FOR i IN 0 TO MAX_REQ_BUFFER LOOP
nvme_wr_req_fifo.slot(i) <= 0;
END LOOP; -- i
END IF; -- end reset
END IF; -- end clk
END PROCESS dma_read;
-- READ and WRITE requests:
-- NVMe request handling
nvme_req:
PROCESS(action_clk) IS
ALIAS nvme_rd_head : REQ_BUFFER_RANGE_t IS nvme_rd_req_fifo.head;
ALIAS nvme_rd_tail : REQ_BUFFER_RANGE_t IS nvme_rd_req_fifo.tail;
-- ALIAS nvme_rd_slot : SLOT_RANGE_t IS nvme_rd_req_fifo.slot(MODFIFO(nvme_rd_req_fifo.tail));
ALIAS nvme_wr_head : REQ_BUFFER_RANGE_t IS nvme_wr_req_fifo.head;
ALIAS nvme_wr_tail : REQ_BUFFER_RANGE_t IS nvme_wr_req_fifo.tail;
-- ALIAS nvme_wr_slot : SLOT_RANGE_t IS nvme_wr_req_fifo.slot(MODFIFO(nvme_wr_req_fifo.tail));
VARIABLE nvme_rd_slot : SLOT_RANGE_t;
VARIABLE nvme_wr_slot : SLOT_RANGE_t;
VARIABLE req_slot : SLOT_TYPE_t;
VARIABLE lba_count_dec : STD_LOGIC_VECTOR(16 DOWNTO 0);
BEGIN
IF (rising_edge(action_clk)) THEN
nvme_cmd_valid <= '0';
reg_0x54_nvme_req <= reg_0x54_nvme_req AND NOT req_buffer.done;
IF (nvme_busy OR nvme_cmd_valid) = '0' THEN
-- handle nvme rd requests triggered by mmio
IF nvme_req_arbiter_read AND (nvme_rd_tail /= nvme_rd_head) THEN
nvme_rd_slot := nvme_rd_req_fifo.slot(MODFIFO(nvme_rd_tail));
req_slot := std_logic_vector(to_unsigned(nvme_rd_slot,4));
nvme_cmd_valid <= '1';
nvme_cmd <= req_slot & x"10";
nvme_mem_addr <= x"0000_0002_00" & "000" & req_slot & "0" & x"0000";
nvme_lba_addr <= req_buffer.src_addr(nvme_rd_slot);
lba_count_dec := (req_buffer.size(nvme_rd_slot) & "000") - 1;
nvme_lba_count <= x"0000" & lba_count_dec(15 DOWNTO 0);
IF nvme_rd_tail = (MAX_REQ_BUFFER*2)+1 THEN
nvme_rd_tail <= 0;
ELSE
nvme_rd_tail <= nvme_rd_tail + 1;
END IF;
IF reg_0x54_nvme_req(nvme_rd_slot) = '1' THEN
reg_0x48_nvme_rd_error(nvme_rd_slot) <= '1';
reg_0x4c_nvme_error(0) <= '1';
END IF;
reg_0x54_nvme_req(nvme_rd_slot) <= '1';
-- handle NVMe write triggered by completion of DMA read
ELSIF nvme_wr_tail /= nvme_wr_head THEN
nvme_wr_slot := nvme_wr_req_fifo.slot(MODFIFO(nvme_wr_tail));
req_slot := std_logic_vector(to_unsigned(nvme_wr_slot,4));
nvme_cmd_valid <= '1';
nvme_cmd <= req_slot & x"11";
nvme_mem_addr <= x"0000_0002_00" & "000" & req_slot & "0" & x"0000";
nvme_lba_addr <= req_buffer.dest_addr(nvme_wr_slot);
nvme_lba_count <= x"0000_000" & req_buffer.size(nvme_wr_slot)(1) & "111";
IF nvme_wr_tail = (MAX_REQ_BUFFER*2)+1 THEN
nvme_wr_tail <= 0;
ELSE
nvme_wr_tail <= nvme_wr_tail + 1;
END IF;
IF reg_0x54_nvme_req(nvme_wr_slot) = '1' THEN
reg_0x48_nvme_wr_error(nvme_wr_slot) <= '1';
reg_0x4c_nvme_error(0) <= '1';
END IF;
reg_0x54_nvme_req(nvme_wr_slot) <= '1';
END IF;
END IF;
nvme_req_arbiter_read <= NOT nvme_req_arbiter_read;
IF action_rst_n = '0' THEN
nvme_rd_tail <= 0;
nvme_wr_tail <= 0;
nvme_req_arbiter_read <= FALSE;
-- Reset debug registers
reg_0x48_nvme_rd_error <= (OTHERS => '0');
reg_0x48_nvme_wr_error <= (OTHERS => '0');
reg_0x4c_nvme_error(0) <= '0';
reg_0x54_nvme_req <= (OTHERS => '0');
END IF; -- end reset
END IF; -- end clk
END PROCESS nvme_req;
-- READ and WRITE requests:
-- NVMe completion handling
nvme_cpl:
PROCESS(action_clk) is
ALIAS dma_wr_head : REQ_BUFFER_RANGE_t IS dma_wr_req_fifo.head;
ALIAS wr_cpl_head : REQ_BUFFER_RANGE_t IS wr_cpl_fifo.head;
VARIABLE nvme_done_index : REQ_BUFFER_RANGE_t;
BEGIN
IF (rising_edge(action_clk)) THEN
write_complete_int <= FALSE;
reg_0x54_nvme_rsp <= reg_0x54_nvme_rsp AND NOT req_buffer.done;
-- handle completion of an NVMe request
nvme_done_index := to_integer(unsigned(nvme_complete(7 DOWNTO 4)));
IF nvme_complete(1 DOWNTO 0) /= "00" THEN
-- IF index = 0, a NVMe write has completed
IF req_buffer.cmd_type(nvme_done_index) = NVME_READ THEN
-- NVMe read has been completed
-- say that the data is ready to be sent to the host
dma_wr_req_fifo.slot(MODFIFO(dma_wr_head)) <= nvme_done_index;
IF dma_wr_head = (MAX_REQ_BUFFER*2)+1 THEN
dma_wr_head <= 0;
ELSE
dma_wr_head <= dma_wr_head + 1;
END IF;
ELSE
write_complete_int <= TRUE;
wr_cpl_fifo.slot(MODFIFO(wr_cpl_head)) <= nvme_complete(7 DOWNTO 4);
IF wr_cpl_head = (MAX_REQ_BUFFER*2)+1 THEN
wr_cpl_head <= 0;
ELSE
wr_cpl_head <= wr_cpl_head + 1;
END IF;
END IF;
IF reg_0x54_nvme_req(nvme_done_index) = '0' THEN
reg_0x4c_nvme_error(1) <= '1';
END IF;
IF reg_0x54_nvme_rsp(nvme_done_index) = '1' THEN
reg_0x4c_nvme_error(2) <= '1';
END IF;
reg_0x54_nvme_rsp(nvme_done_index) <= '1';
END IF;
IF action_rst_n = '0' THEN
dma_wr_head <= 0;
wr_cpl_head <= 0;
reg_0x54_nvme_rsp <= (OTHERS => '0');
reg_0x4c_nvme_error(2 DOWNTO 1) <= (OTHERS => '0');
END IF; -- end reset
END IF; -- end clk
END PROCESS nvme_cpl;
-- READ requests:
-- DMA write request handling (SDRAM to Host)
axi_host_mem_awvalid <= host_mem_awvalid;
axi_host_mem_awaddr <= host_mem_awaddr;
axi_card_mem0_arvalid <= card_mem_arvalid;
axi_card_mem0_araddr <= card_mem_araddr;
dma_write:
PROCESS(action_clk) IS
ALIAS dma_wr_tail : REQ_BUFFER_RANGE_t IS dma_wr_req_fifo.tail;
ALIAS dma_wr_head : REQ_BUFFER_RANGE_t IS dma_wr_req_fifo.head;
-- ALIAS dma_wr_slot : SLOT_RANGE_t IS dma_wr_req_fifo.slot(MODFIFO(dma_wr_req_fifo.tail));
ALIAS dma_cpl_head : REQ_BUFFER_RANGE_t IS dma_wr_cpl_fifo.head;
-- ALIAS dma_cpl_slot : SLOT_RANGE_t IS dma_wr_cpl_fifo.slot(MODFIFO(dma_wr_cpl_fifo.head));
VARIABLE dma_wr_slot : SLOT_TYPE_t;
VARIABLE slot_id : SLOT_RANGE_t;
BEGIN
IF (rising_edge(action_clk)) THEN
-- reset requests when acknowledged
IF axi_host_mem_awready = '1' and host_mem_awvalid = '1' THEN
host_mem_awvalid <= '0';
END IF;
IF axi_card_mem0_arready = '1' and card_mem_arvalid = '1' THEN
card_mem_arvalid <= '0';
END IF;
CASE fsm_dma_wr is
WHEN IDLE =>
IF dma_wr_tail /= dma_wr_head THEN
-- determine host and card memory address on buffer postion
slot_id := dma_wr_req_fifo.slot(MODFIFO(dma_wr_tail));
dma_wr_slot := std_logic_vector(to_unsigned(slot_id,4));
host_mem_awaddr <= req_buffer.dest_addr(slot_id);
card_mem_araddr <= x"00" & "000" & dma_wr_slot & "0" & x"0000";
dma_wr_count <= req_buffer.size(slot_id) - '1';
host_mem_awvalid <= '1';
card_mem_arvalid <= '1';
dma_wr_cpl_fifo.slot(MODFIFO(dma_cpl_head)) <= dma_wr_req_fifo.slot(MODFIFO(dma_wr_tail));
fsm_dma_wr <= DMA_WR_REQ;
IF dma_cpl_head = (MAX_REQ_BUFFER*2)+1 THEN
dma_cpl_head <= 0;
ELSE
dma_cpl_head <= dma_cpl_head + 1;
END IF;
END IF;
WHEN DMA_WR_REQ =>
-- initiate SDRAM to host memory data transfer
IF host_mem_awvalid = '0' and card_mem_arvalid = '0' THEN
IF or_reduce(dma_wr_count) = '1' THEN
dma_wr_count <= dma_wr_count - '1';
host_mem_awaddr <= host_mem_awaddr + x"1000";
card_mem_araddr <= card_mem_araddr + x"1000";
host_mem_awvalid <= '1';
card_mem_arvalid <= '1';
fsm_dma_wr <= DMA_WR_REQ;
ELSE
fsm_dma_wr <= IDLE;
IF dma_wr_tail = (MAX_REQ_BUFFER*2)+1 THEN
dma_wr_tail <= 0;
ELSE
dma_wr_tail <= dma_wr_tail + 1;
END IF;
END IF;
END IF;
WHEN OTHERS => null;
END CASE;
IF action_rst_n = '0' THEN
fsm_dma_wr <= IDLE;
host_mem_awvalid <= '0';
card_mem_arvalid <= '0';
dma_wr_tail <= 0;
dma_cpl_head <= 0;
FOR i IN 0 TO MAX_REQ_BUFFER LOOP
dma_wr_cpl_fifo.slot(i) <= 0; -- initial values may be required in process dma_wr_cpl
END LOOP; -- i
END IF; -- end reset
END IF; -- end clk
END PROCESS dma_write;
-- READ requests:
-- Process DMA write request completion
dma_wr_cpl:
PROCESS(action_clk) is
ALIAS dma_cpl_tail : REQ_BUFFER_RANGE_t IS dma_wr_cpl_fifo.tail;
ALIAS dma_cpl_head : REQ_BUFFER_RANGE_t IS dma_wr_cpl_fifo.head;
ALIAS rd_cpl_head : REQ_BUFFER_RANGE_t IS rd_cpl_fifo.head;
VARIABLE dma_cpl_slot : SLOT_RANGE_t;
VARIABLE size : REQ_SIZE_TYPE_t;
BEGIN
IF (rising_edge(action_clk)) THEN
read_complete_int <= FALSE;
dma_cpl_slot := dma_wr_cpl_fifo.slot(MODFIFO(dma_cpl_tail));
IF (or_reduce(dma_wr_size) = '0') AND (dma_cpl_tail /= dma_cpl_head) THEN
dma_wr_size <= req_buffer.size(dma_cpl_slot);
END IF;
IF axi_host_mem_bvalid = '1' THEN
-- when dma to host has finished
IF dma_wr_size = "00" & x"001" THEN
read_complete_int <= TRUE;
-- we are done with this id
-- point to the next entry in the queue
rd_cpl_fifo.slot(MODFIFO(rd_cpl_head)) <= std_logic_vector(to_unsigned(dma_cpl_slot,4));
dma_wr_size <= req_buffer.size(dma_wr_cpl_fifo.slot(INCRPTR(dma_cpl_slot)));
IF dma_cpl_tail = (MAX_REQ_BUFFER*2)+1 THEN
dma_cpl_tail <= 0;
ELSE
dma_cpl_tail <= dma_cpl_tail + 1;
END IF;
IF rd_cpl_head = (MAX_REQ_BUFFER*2)+1 THEN
rd_cpl_head <= 0;
ELSE
rd_cpl_head <= rd_cpl_head + 1;
END IF;
END IF;
dma_wr_size <= dma_wr_size - 1;
END IF;
IF action_rst_n = '0' THEN
dma_cpl_tail <= 0;
rd_cpl_head <= 0;
dma_wr_size <= (OTHERS => '0');
END IF; -- end reset
END IF; -- end clk
END PROCESS dma_wr_cpl;
-- READ and WRITE requests:
-- Request completion handling
app_req_cpl:
PROCESS(action_clk) is
ALIAS rd_cpl_tail : REQ_BUFFER_RANGE_t IS rd_cpl_fifo.tail;
ALIAS rd_cpl_head : REQ_BUFFER_RANGE_t IS rd_cpl_fifo.head;
ALIAS wr_cpl_tail : REQ_BUFFER_RANGE_t IS wr_cpl_fifo.tail;
ALIAS wr_cpl_head : REQ_BUFFER_RANGE_t IS wr_cpl_fifo.head;
ALIAS cpl_tail : REQ_BUFFER_RANGE_t IS completion_fifo.tail;
ALIAS cpl_head : REQ_BUFFER_RANGE_t IS completion_fifo.head;
BEGIN
IF (rising_edge(action_clk)) THEN
-- Fill completion fifo with read and write completions
IF completion_arbiter_read AND (rd_cpl_tail /= rd_cpl_head) THEN
completion_fifo.slot(MODFIFO(cpl_head)) <= rd_cpl_fifo.slot(MODFIFO(rd_cpl_tail));
IF cpl_head = (MAX_REQ_BUFFER*2)+1 THEN
cpl_head <= 0;
ELSE
cpl_head <= cpl_head + 1;
END IF;
IF rd_cpl_tail = (MAX_REQ_BUFFER*2)+1 THEN
rd_cpl_tail <= 0;
ELSE
rd_cpl_tail <= rd_cpl_tail + 1;
END IF;
ELSIF wr_cpl_tail /= wr_cpl_head THEN
completion_fifo.slot(MODFIFO(cpl_head)) <= wr_cpl_fifo.slot(MODFIFO(wr_cpl_tail));
IF cpl_head = (MAX_REQ_BUFFER*2)+1 THEN
cpl_head <= 0;
ELSE
cpl_head <= cpl_head + 1;
END IF;
IF wr_cpl_tail = (MAX_REQ_BUFFER*2)+1 THEN
wr_cpl_tail <= 0;
ELSE
wr_cpl_tail <= wr_cpl_tail + 1;
END IF;
END IF;
completion_arbiter_read <= NOT completion_arbiter_read;
-- On an MMIO read to the status/completion register
-- return a pending completion from the completion fifo
req_buffer.done <= (OTHERS => '0');
IF reg_0x4c_rd_strobe = '1' THEN
IF cpl_tail /= cpl_head THEN
req_buffer.done(to_integer(unsigned(completion_fifo.slot(MODFIFO(cpl_tail))))) <= '1';
IF cpl_tail = (MAX_REQ_BUFFER*2)+1 THEN
cpl_tail <= 0;
ELSE
cpl_tail <= cpl_tail + 1;
END IF;
END IF;
END IF;
IF action_rst_n = '0' THEN
rd_cpl_tail <= 0;
wr_cpl_tail <= 0;
cpl_head <= 0;
cpl_tail <= 0;
completion_arbiter_read <= TRUE;
END IF; -- end reset
END IF; -- end clk
END PROCESS app_req_cpl;
-- MMIO readback data of the completion queue
read_data:
PROCESS(completion_fifo.head, completion_fifo.tail)
ALIAS cpl_head : REQ_BUFFER_RANGE_t IS completion_fifo.head;
ALIAS cpl_tail : REQ_BUFFER_RANGE_t IS completion_fifo.tail;
BEGIN
-- IF a NVMe write has completed, put it always in front of the
-- completion fifo
IF cpl_tail /= cpl_head THEN
reg_0x4c_completion <= "1" & completion_fifo.slot(MODFIFO(cpl_tail));
ELSE
reg_0x4c_completion <= (OTHERS => '0');
END IF;
END PROCESS read_data;
-- Interrupt generation (if enabled)
generate_interrupt:
PROCESS(action_clk) is
BEGIN
IF (rising_edge(action_clk)) THEN
int_req <= '0';
IF action_rst_n = '1' THEN
IF read_complete_int OR write_complete_int THEN
-- generate interrupt when the request has been completed
int_req <= '1' AND int_enable;
END IF;
END IF;
END IF;
END PROCESS generate_interrupt;
-- host to on-card SDRAM data path
axi_card_mem0_wvalid <= card_mem_wvalid;
axi_card_mem0_wstrb <= (OTHERS => '1');
axi_card_mem0_awlen <= x"3f";
axi_card_mem0_bready <= '1';
axi_host_mem_arlen <= x"3f";
host_to_sdram:
PROCESS(action_clk, card_mem_wvalid, axi_card_mem0_wready) is
BEGIN
IF (rising_edge(action_clk)) THEN
IF axi_card_mem0_wready = '1' OR card_mem_wvalid = '0' THEN
card_mem_wvalid <= axi_host_mem_rvalid;
axi_card_mem0_wdata <= axi_host_mem_rdata;
axi_card_mem0_wlast <= axi_host_mem_rlast;
END IF;
IF action_rst_n = '0' THEN
card_mem_wvalid <= '0';
END IF;
END IF;
axi_host_mem_rready <= '0';
IF card_mem_wvalid = '0' OR axi_card_mem0_wready = '1' THEN
axi_host_mem_rready <= '1';
END IF;
END PROCESS host_to_sdram;
-- on-card SDRAM to host data path
axi_host_mem_wvalid <= host_mem_wvalid;
axi_host_mem_wstrb <= (OTHERS => '1');
axi_host_mem_awlen <= x"3f";
axi_host_mem_bready <= '1';
axi_card_mem0_arlen <= x"3f";
sdram_to_host:
PROCESS(action_clk, host_mem_wvalid, axi_host_mem_wready) IS
BEGIN
IF (rising_edge(action_clk)) THEN
IF axi_host_mem_wready = '1' OR host_mem_wvalid = '0' THEN
host_mem_wvalid <= axi_card_mem0_rvalid ;
axi_host_mem_wdata <= axi_card_mem0_rdata;
axi_host_mem_wlast <= axi_card_mem0_rlast;
axi_card_mem0_rready <= '1';
END IF;
IF (action_rst_n = '0') THEN
host_mem_wvalid <= '0';
END IF;
END IF;
axi_card_mem0_rready <= '0';
IF host_mem_wvalid = '0'OR axi_host_mem_wready = '1' THEN
axi_card_mem0_rready <= '1';
END IF;
END PROCESS sdram_to_host;
END action_nvme_example;
| apache-2.0 | 7f328d8c16ae3bc167d474beac6c0211 | 0.552653 | 3.15899 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/incrementador.vhd | 1 | 1,037 | ----------------------------------------------------------------------------------
-- Create Date: 15:31:16 04/11/2017
-- Module Name: incrementador - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity incrementador is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end incrementador;
architecture Behavioral of incrementador is
component Somador4bits
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Ov : out STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal Out1: STD_LOGIC_VECTOR(3 downto 0);
signal Cout: STD_LOGIC;
signal Ov: STD_LOGIC;
begin
O1: Somador4bits port map( X => A,
Y => "0001",
Cin => '0',
Cout => open,
Ov => open,
Z => Out1);
O <= Out1;
end Behavioral;
| gpl-3.0 | c4c2d3e6f3ef85114b7eb80d99215e6d | 0.496625 | 3.757246 | false | false | false | false |
VLSI-EDA/PoC-Examples | tb/mem/mem_model.vhdl | 1 | 5,008 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Model of pipelined memory with "mem" interface.
--
-- Description:
-- ------------------------------------
-- To be used for simulation as a replacement for a real memory controller.
--
-- Generic parameters:
--
-- * A_BITS: number of word address bits.
-- * D_BTIS: width of data bus.
-- * LATENCY: the latency of the pipelined read.
--
-- License:
-- ============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
-------------------------------------------------------------------------------
-- Naming Conventions:
-- (Based on: Keating and Bricaud: "Reuse Methodology Manual")
--
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: all UPPERCASE
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- output of a register: "*_r"
-- asynchronous signal: "*_a"
-- pipelined or register delay signals: "*_p#"
-- data before being registered into register with the same name: "*_nxt"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- tristate internal signal "*_z"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_model is
generic (
A_BITS : positive;
D_BITS : positive;
LATENCY : positive
);
port (
clk : in std_logic;
rst : in std_logic;
mem_req : in std_logic;
mem_write : in std_logic;
mem_addr : in unsigned(A_BITS-1 downto 0);
mem_wdata : in std_logic_vector(D_BITS-1 downto 0);
mem_rdy : out std_logic;
mem_rstb : out std_logic;
mem_rdata : out std_logic_vector(D_BITS-1 downto 0));
end entity mem_model;
architecture sim of mem_model is
-- data types
type RAM_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal ram : RAM_T(0 to 2**A_BITS-1);
-- read pipeline
type RDATA_T is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal rdata_p : RDATA_T(1 to LATENCY);
signal rstb_p : std_logic_vector(1 to LATENCY) := (others => '0');
-- ready control logic
type FSM_TYPE is (RESET, READY);
signal fsm_cs : FSM_TYPE;
begin -- architecture sim
-- TODO: implement some logic / FSM which introduces wait states
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
fsm_cs <= RESET;
else
fsm_cs <= READY;
end if;
end if;
end process;
-- Memory and Read Pipeline
process(clk)
begin
if rising_edge(clk) then
rstb_p(1) <= '0'; -- default
-- access memory only when ready, ignore requests otherwise
if fsm_cs = READY then
if mem_req = '1' then
if mem_write = '1' then
if Is_X(std_logic_vector(mem_addr)) then
report "Invalid address during write." severity error;
else
ram(to_integer(mem_addr)) <= mem_wdata;
end if;
elsif mem_write = '0' then -- read
if Is_X(std_logic_vector(mem_addr)) then
report "Invalid address during read." severity error;
else
rdata_p(1) <= ram(to_integer(mem_addr));
rstb_p(1) <= '1';
end if;
else
report "Invalid write/read command." severity error;
end if;
elsif mem_req /= '0' then
report "Invalid request." severity error;
end if;
end if;
-- read pipeline
if LATENCY > 1 then
rstb_p (2 to LATENCY) <= rstb_p (1 to LATENCY-1);
rdata_p(2 to LATENCY) <= rdata_p(1 to LATENCY-1);
end if;
-- reset only read strobe
if rst = '1' then
rstb_p <= (others => '0');
end if;
end if;
end process;
-- Read Pipeline
--gReadPipe: if LATENCY > 1 generate
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- end if;
-- end process;
--end generate gReadPipe;
-- Outputs
mem_rdy <= '1' when fsm_cs = READY else '0';
mem_rdata <= rdata_p(LATENCY);
mem_rstb <= rstb_p (LATENCY);
end architecture sim;
| apache-2.0 | 50eb5eac84d00e793ded4d84167c00a8 | 0.589058 | 3.463347 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/sim/RAT_ControlUnit_0_0.vhd | 1 | 6,757 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_ControlUnit_0_0 IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END RAT_ControlUnit_0_0;
ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ControlUnit IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END COMPONENT ControlUnit;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST";
BEGIN
U0 : ControlUnit
PORT MAP (
CLK => CLK,
C => C,
Z => Z,
INT => INT,
RST => RST,
OPCODE_HI_5 => OPCODE_HI_5,
OPCODE_LO_2 => OPCODE_LO_2,
PC_LD => PC_LD,
PC_INC => PC_INC,
PC_RESET => PC_RESET,
PC_OE => PC_OE,
PC_MUX_SEL => PC_MUX_SEL,
SP_LD => SP_LD,
SP_MUX_SEL => SP_MUX_SEL,
SP_RESET => SP_RESET,
RF_WR => RF_WR,
RF_WR_SEL => RF_WR_SEL,
RF_OE => RF_OE,
REG_IMMED_SEL => REG_IMMED_SEL,
ALU_SEL => ALU_SEL,
ALU_OPY_SEL => ALU_OPY_SEL,
SCR_WR => SCR_WR,
SCR_OE => SCR_OE,
SCR_ADDR_SEL => SCR_ADDR_SEL,
C_FLAG_SEL => C_FLAG_SEL,
C_FLAG_LD => C_FLAG_LD,
C_FLAG_SET => C_FLAG_SET,
C_FLAG_CLR => C_FLAG_CLR,
SHAD_C_LD => SHAD_C_LD,
Z_FLAG_SEL => Z_FLAG_SEL,
Z_FLAG_LD => Z_FLAG_LD,
Z_FLAG_SET => Z_FLAG_SET,
Z_FLAG_CLR => Z_FLAG_CLR,
SHAD_Z_LD => SHAD_Z_LD,
I_FLAG_SET => I_FLAG_SET,
I_FLAG_CLR => I_FLAG_CLR,
IO_OE => IO_OE
);
END RAT_ControlUnit_0_0_arch;
| mit | e76f09b4559fc3004e873a84a53896c4 | 0.644961 | 3.288078 | false | false | false | false |
marcoep/MusicBoxNano | ip/EnvelopeROM.vhd | 1 | 5,880 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: EnvelopeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY EnvelopeROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END EnvelopeROM;
ARCHITECTURE SYN OF enveloperom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/Envelope_256.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/Envelope_256.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/Envelope_256.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvelopeROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvelopeROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvelopeROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvelopeROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvelopeROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 5aad5e4ffdd652e1df7b66068da87420 | 0.678401 | 3.761996 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/sim/RAT_Counter10bit_0_0.vhd | 2 | 3,531 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Counter10bit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Counter10bit_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END RAT_Counter10bit_0_0;
ARCHITECTURE RAT_Counter10bit_0_0_arch OF RAT_Counter10bit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END RAT_Counter10bit_0_0_arch;
| mit | 943c8a824da217f237d2e7d99e1c01c3 | 0.723308 | 3.976351 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.vhdl | 1 | 8,939 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:02 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.vhdl
-- Design : RAT_Counter10bit_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Counter10bit_0_0_Counter10bit is
port (
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR ( 0 to 9 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Counter10bit_0_0_Counter10bit : entity is "Counter10bit";
end RAT_Counter10bit_0_0_Counter10bit;
architecture STRUCTURE of RAT_Counter10bit_0_0_Counter10bit is
signal \^count\ : STD_LOGIC_VECTOR ( 0 to 9 );
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \s_COUNT[0]_i_1_n_0\ : STD_LOGIC;
signal \s_COUNT[0]_i_3_n_0\ : STD_LOGIC;
signal \s_COUNT[1]_i_2_n_0\ : STD_LOGIC;
signal \s_COUNT[4]_i_2_n_0\ : STD_LOGIC;
signal \s_COUNT[5]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_COUNT[0]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_COUNT[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_COUNT[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_COUNT[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_COUNT[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \s_COUNT[9]_i_1\ : label is "soft_lutpair2";
begin
COUNT(0 to 9) <= \^count\(0 to 9);
\s_COUNT[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => LOAD,
I1 => INC,
O => \s_COUNT[0]_i_1_n_0\
);
\s_COUNT[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(0),
I1 => LOAD,
I2 => \s_COUNT[0]_i_3_n_0\,
I3 => \^count\(1),
I4 => \^count\(0),
O => p_0_in(9)
);
\s_COUNT[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^count\(2),
I1 => \s_COUNT[1]_i_2_n_0\,
I2 => \^count\(3),
O => \s_COUNT[0]_i_3_n_0\
);
\s_COUNT[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BBBBBBBB8888888"
)
port map (
I0 => Din(1),
I1 => LOAD,
I2 => \^count\(3),
I3 => \s_COUNT[1]_i_2_n_0\,
I4 => \^count\(2),
I5 => \^count\(1),
O => p_0_in(8)
);
\s_COUNT[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^count\(4),
I1 => \^count\(6),
I2 => \^count\(8),
I3 => \^count\(9),
I4 => \^count\(7),
I5 => \^count\(5),
O => \s_COUNT[1]_i_2_n_0\
);
\s_COUNT[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(2),
I1 => LOAD,
I2 => \s_COUNT[1]_i_2_n_0\,
I3 => \^count\(3),
I4 => \^count\(2),
O => p_0_in(7)
);
\s_COUNT[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(3),
I1 => LOAD,
I2 => \s_COUNT[1]_i_2_n_0\,
I3 => \^count\(3),
O => p_0_in(6)
);
\s_COUNT[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(4),
I1 => LOAD,
I2 => \s_COUNT[4]_i_2_n_0\,
I3 => \^count\(4),
O => p_0_in(5)
);
\s_COUNT[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^count\(5),
I1 => \^count\(7),
I2 => \^count\(9),
I3 => \^count\(8),
I4 => \^count\(6),
O => \s_COUNT[4]_i_2_n_0\
);
\s_COUNT[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(5),
I1 => LOAD,
I2 => \s_COUNT[5]_i_2_n_0\,
I3 => \^count\(5),
O => p_0_in(4)
);
\s_COUNT[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^count\(6),
I1 => \^count\(8),
I2 => \^count\(9),
I3 => \^count\(7),
O => \s_COUNT[5]_i_2_n_0\
);
\s_COUNT[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BBBBBBBB8888888"
)
port map (
I0 => Din(6),
I1 => LOAD,
I2 => \^count\(8),
I3 => \^count\(9),
I4 => \^count\(7),
I5 => \^count\(6),
O => p_0_in(3)
);
\s_COUNT[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(7),
I1 => LOAD,
I2 => \^count\(9),
I3 => \^count\(8),
I4 => \^count\(7),
O => p_0_in(2)
);
\s_COUNT[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(8),
I1 => LOAD,
I2 => \^count\(9),
I3 => \^count\(8),
O => p_0_in(1)
);
\s_COUNT[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Din(9),
I1 => LOAD,
I2 => \^count\(9),
O => p_0_in(0)
);
\s_COUNT_reg[0]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(9),
Q => \^count\(0)
);
\s_COUNT_reg[1]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(8),
Q => \^count\(1)
);
\s_COUNT_reg[2]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(7),
Q => \^count\(2)
);
\s_COUNT_reg[3]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(6),
Q => \^count\(3)
);
\s_COUNT_reg[4]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(5),
Q => \^count\(4)
);
\s_COUNT_reg[5]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(4),
Q => \^count\(5)
);
\s_COUNT_reg[6]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(3),
Q => \^count\(6)
);
\s_COUNT_reg[7]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(2),
Q => \^count\(7)
);
\s_COUNT_reg[8]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(1),
Q => \^count\(8)
);
\s_COUNT_reg[9]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(0),
Q => \^count\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Counter10bit_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Counter10bit_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Counter10bit_0_0 : entity is "RAT_Counter10bit_0_0,Counter10bit,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Counter10bit_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Counter10bit_0_0 : entity is "Counter10bit,Vivado 2016.4";
end RAT_Counter10bit_0_0;
architecture STRUCTURE of RAT_Counter10bit_0_0 is
begin
U0: entity work.RAT_Counter10bit_0_0_Counter10bit
port map (
CLK => CLK,
COUNT(0 to 9) => COUNT(0 to 9),
Din(0 to 9) => Din(0 to 9),
INC => INC,
LOAD => LOAD,
RESET => RESET
);
end STRUCTURE;
| mit | 13dabf4848aab4bbcaa33c0f186fa4d4 | 0.505649 | 2.851356 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd | 5 | 10,812 | `protect begin_protected
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| mit | 05ec88630b9587e83913c1a0ea7ea56c | 0.923603 | 1.93037 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_7_0_0/synth/RAT_slice_7_0_0.vhd | 2 | 3,808 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_7_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_7_0_0;
ARCHITECTURE RAT_slice_7_0_0_arch OF RAT_slice_7_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_7_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_7_0_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_7_0_0_arch : ARCHITECTURE IS "RAT_slice_7_0_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_7_0_0_arch: ARCHITECTURE IS "RAT_slice_7_0_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=12,DIN_TO=8}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 12,
DIN_TO => 8
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_7_0_0_arch;
| mit | 2aaeac983aff951eeddd0363538b8c3d | 0.727153 | 3.827136 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/RAT_ScratchRam_0_0_sim_netlist.vhdl | 1 | 5,645 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:19:56 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/RAT_ScratchRam_0_0_sim_netlist.vhdl
-- Design : RAT_ScratchRam_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ScratchRam_0_0_ScratchRam is
port (
DATA_OUT : out STD_LOGIC_VECTOR ( 9 downto 0 );
CLK : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR ( 9 downto 0 );
WE : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_ScratchRam_0_0_ScratchRam : entity is "ScratchRam";
end RAT_ScratchRam_0_0_ScratchRam;
architecture STRUCTURE of RAT_ScratchRam_0_0_ScratchRam is
begin
RAM_reg_0_255_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(0),
O => DATA_OUT(0),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(1),
O => DATA_OUT(1),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(2),
O => DATA_OUT(2),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(3),
O => DATA_OUT(3),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(4),
O => DATA_OUT(4),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(5),
O => DATA_OUT(5),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(6),
O => DATA_OUT(6),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(7),
O => DATA_OUT(7),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(8),
O => DATA_OUT(8),
WCLK => CLK,
WE => WE
);
RAM_reg_0_255_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => ADDR(7 downto 0),
D => DATA_IN(9),
O => DATA_OUT(9),
WCLK => CLK,
WE => WE
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ScratchRam_0_0 is
port (
DATA_IN : in STD_LOGIC_VECTOR ( 9 downto 0 );
DATA_OUT : out STD_LOGIC_VECTOR ( 9 downto 0 );
ADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
WE : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_ScratchRam_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_ScratchRam_0_0 : entity is "RAT_ScratchRam_0_0,ScratchRam,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_ScratchRam_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_ScratchRam_0_0 : entity is "ScratchRam,Vivado 2016.4";
end RAT_ScratchRam_0_0;
architecture STRUCTURE of RAT_ScratchRam_0_0 is
begin
U0: entity work.RAT_ScratchRam_0_0_ScratchRam
port map (
ADDR(7 downto 0) => ADDR(7 downto 0),
CLK => CLK,
DATA_IN(9 downto 0) => DATA_IN(9 downto 0),
DATA_OUT(9 downto 0) => DATA_OUT(9 downto 0),
WE => WE
);
end STRUCTURE;
| mit | d82fdaa9ca5858873050a6646a49a58d | 0.610983 | 3.701639 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/counter_for_one_shot.vhd | 1 | 1,445 | --------------------------------------------------------------------------
--
-- Engineer: Jeff Gerfen
-- Create Date: 2016.02.26
-- Design Name: counter
-- Module Name: counter
--
-- DESCRIPTION:
-- Simple up counter with synchronous load and synchronous reset controls.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity db_1shot_counter is
Port ( RST : in STD_LOGIC;
CLK : in STD_LOGIC;
INC : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (7 downto 0));
end db_1shot_counter;
architecture Behavioral of db_1shot_counter is
signal s_count : std_logic_vector (7 downto 0) := "00000000";
begin
proc: process(CLK, RST, INC, s_count)
begin
if(rising_edge(CLK)) then
if(RST = '1') then -- synchronous reset
s_count <= "00000000";
elsif(INC = '1') then
s_count <= s_count + '1';
end if;
end if;
end process proc;
COUNT <= s_count;
end Behavioral;
| mit | 824ef5cd5a027b335504906f0193abb7 | 0.564706 | 4.070423 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_1_0_0/synth/RAT_slice_1_0_0.vhd | 2 | 3,806 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_1_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_slice_1_0_0;
ARCHITECTURE RAT_slice_1_0_0_arch OF RAT_slice_1_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_1_0_0_arch : ARCHITECTURE IS "RAT_slice_1_0_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "RAT_slice_1_0_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=7,DIN_TO=0}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 7,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_1_0_0_arch;
| mit | a149bd81c20f31aa583f0135fee644a9 | 0.72701 | 3.825126 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_ArtyA7.vhdl | 1 | 10,395 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_ArtyA7 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 100.000 0.000 50.0 200.000 150.000
-- CLK_OUT1 200.000 0.000 50.0 300.000 150.000
-- CLK_OUT2 125.000 0.000 50.0 360.000 150.000
-- CLK_OUT3 10.000 0.000 50.0 300.000 150.000
--
architecture rtl of clknet_ClockNetwork_ArtyA7 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 24 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal DCM_Reset : STD_LOGIC;
signal DCM_Reset_clr : STD_LOGIC;
signal DCM_ResetState : STD_LOGIC := '0';
signal DCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 DOWNTO 0);
signal DCM_Locked_async : STD_LOGIC;
signal DCM_Locked : STD_LOGIC;
signal DCM_Locked_d : STD_LOGIC := '0';
signal DCM_Locked_re : STD_LOGIC;
signal DCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFG : STD_LOGIC;
signal DCM_Clock_10MHz : STD_LOGIC;
signal DCM_Clock_100MHz : STD_LOGIC;
signal DCM_Clock_125MHz : STD_LOGIC;
signal DCM_Clock_200MHz : STD_LOGIC;
signal DCM_Clock_10MHz_BUFG : STD_LOGIC;
signal DCM_Clock_100MHz_BUFG : STD_LOGIC;
signal DCM_Clock_125MHz_BUFG : STD_LOGIC;
signal DCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of DCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) DCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => DCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => DCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
DCM_Reset_clr <= ClkNet_Reset nor DCM_Locked;
-- detect rising edge on CMB locked signals
DCM_Locked_d <= DCM_Locked when rising_edge(Control_Clock);
DCM_Locked_re <= not DCM_Locked_d and DCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
DCM_ResetState <= ffrs(q => DCM_ResetState, rst => DCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
DCM_LockedState <= ffrs(q => DCM_LockedState, rst => DCM_Reset, set => DCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
DCM_Reset_delayed <= shreg_left(DCM_Reset_delayed, DCM_ResetState) when rising_edge(Control_Clock);
DCM_Reset <= DCM_Reset_delayed(DCM_Reset_delayed'high);
Locked <= DCM_LockedState and '1'; --PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFG
port map (
I => ClockIn_100MHz,
O => Control_Clock_BUFG
);
Control_Clock <= Control_Clock_BUFG;
-- 10 MHz BUFG
BUFG_DCM_Clock_10MHz : BUFG
port map (
I => DCM_Clock_10MHz,
O => DCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_DCM_Clock_100MHz : BUFG
port map (
I => DCM_Clock_100MHz,
O => DCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_DCM_Clock_125MHz : BUFG
port map (
I => DCM_Clock_125MHz,
O => DCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_DCM_Clock_200MHz : BUFG
port map (
I => DCM_Clock_200MHz,
O => DCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (DCM)
-- ==================================================================
System_DCM : DCM_SP
generic map (
STARTUP_WAIT => false,
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS"
PHASE_SHIFT => 0,
CLKIN_PERIOD => to_real(to_time(CLOCK_IN_FREQ), 1.0 ns),
CLKIN_DIVIDE_BY_2 => FALSE,
CLK_FEEDBACK => "1X",
CLKOUT_PHASE_SHIFT => "NONE",
CLKDV_DIVIDE => 10.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5
)
port map (
RST => DCM_Reset,
CLKIN => ClockIn_100MHz,
CLKFB => DCM_Clock_100MHz_BUFG,
CLK0 => DCM_Clock_100MHz,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => DCM_Clock_200MHz,
CLK2X180 => open,
CLKFX => DCM_Clock_125MHz,
CLKFX180 => open,
CLKDV => DCM_Clock_10MHz,
-- DCM status
LOCKED => DCM_Locked_async,
STATUS => open,
-- Dynamic Phase Shift Port
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
DSSEN => '0'
);
Control_Clock_100MHz <= Control_Clock_BUFG;
Clock_200MHz <= DCM_Clock_200MHz_BUFG;
Clock_125MHz <= DCM_Clock_125MHz_BUFG;
Clock_100MHz <= DCM_Clock_100MHz_BUFG;
Clock_10MHz <= DCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | c08a89408a968b315f50b705104fdeb3 | 0.535931 | 3.630807 | false | false | false | false |
open-power/snap | actions/hdl_example/hw/action_axi_master.vhd | 1 | 12,078 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity action_axi_master is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Thread ID Width
C_M_AXI_ID_WIDTH : integer := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : integer := 64;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : integer := 512;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : integer := 0;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : integer := 0;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : integer := 0;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : integer := 0;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
dma_rd_req_i : in std_logic;
dma_rd_addr_i : in std_logic_vector(C_M_AXI_ADDR_WIDTH -1 downto 0);
dma_rd_len_i : in std_logic_vector( 7 downto 0);
dma_rd_req_ack_o : out std_logic;
dma_rd_data_o : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
dma_rd_data_valid_o : out std_logic;
dma_rd_data_last_o : out std_logic;
dma_rd_data_taken_i : in std_logic;
dma_rd_context_id : in std_logic_vector(C_M_AXI_ARUSER_WIDTH - 1 downto 0);
dma_wr_req_i : in std_logic;
dma_wr_addr_i : in std_logic_vector( C_M_AXI_ADDR_WIDTH - 1 downto 0);
dma_wr_len_i : in std_logic_vector( 7 downto 0);
dma_wr_req_ack_o : out std_logic;
dma_wr_data_i : in std_logic_vector(C_M_AXI_DATA_WIDTH -1 downto 0);
dma_wr_data_strobe_i: in std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
dma_wr_data_last_i : in std_logic;
dma_wr_ready_o : out std_logic;
dma_wr_bready_i : in std_logic;
dma_wr_done_o : out std_logic;
dma_wr_context_id : in std_logic_vector(C_M_AXI_AWUSER_WIDTH - 1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end action_axi_master;
architecture action_axi_master of action_axi_master is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
function or_reduce (signal arg : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for i in arg'low to arg'high loop
result := result or arg(i);
end loop; -- i
return result;
end or_reduce;
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
signal axi_awlen : std_logic_vector(7 downto 0);
signal axi_arlen : std_logic_vector(7 downto 0);
signal wr_req_wait_cycle : std_logic;
signal rd_req_wait_cycle : std_logic;
signal rd_req_ack : std_logic;
signal wr_req_ack : std_logic;
begin
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= axi_awaddr;
M_AXI_AWLEN <= axi_awlen;
M_AXI_AWSIZE <= std_logic_vector( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= (others => '0');
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= dma_wr_context_id;
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= axi_wstrb;
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARLEN <= axi_arlen;
M_AXI_ARSIZE <= std_logic_vector( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= (others => '0');
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= dma_rd_context_id;
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
axi_w: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
dma_wr_req_ack_o <= '0';
dma_wr_done_o <= '0';
if M_AXI_ARESETN = '0' then
axi_awvalid <= '0';
axi_bready <= '0';
wr_req_wait_cycle <= '0';
else
wr_req_wait_cycle <= '0';
if dma_wr_req_i = '1' and wr_req_wait_cycle = '0' then
axi_awaddr <= dma_wr_addr_i;
axi_awlen <= dma_wr_len_i;
axi_awvalid <= '1';
end if;
if axi_awvalid = '1' and M_AXI_AWREADY = '1' then
dma_wr_req_ack_o <= '1';
axi_awvalid <= '0';
wr_req_wait_cycle <= '1';
end if;
axi_bready <= dma_wr_bready_i;
if M_AXI_BVALID = '1' then
dma_wr_done_o <= '1';
end if;
end if;
end if;
end process;
axi_rready <= dma_rd_data_taken_i;
dma_rd_data_last_o <= M_AXI_RLAST;
dma_rd_data_valid_o <= M_AXI_RVALID;
dma_rd_data_o <= M_AXI_RDATA;
axi_write_buffer:
process(M_AXI_ACLK,M_AXI_WREADY, axi_wvalid )
begin
if (rising_edge (M_AXI_ACLK)) then
if M_AXI_ARESETN = '0' then
axi_wvalid <= '0';
else
if M_AXI_WREADY = '1' or axi_wvalid = '0' then
axi_wdata <= dma_wr_data_i;
axi_wvalid <= or_reduce(dma_wr_data_strobe_i);
axi_wstrb <= dma_wr_data_strobe_i;
axi_wlast <= dma_wr_data_last_i;
end if;
end if;
end if;
dma_wr_ready_o <= '1';
if M_AXI_WREADY = '0' and axi_wvalid = '1' then
dma_wr_ready_o <= '0';
end if;
end process;
axi_r: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
dma_rd_req_ack_o <= '0';
if (M_AXI_ARESETN = '0' ) then
axi_arvalid <= '0';
rd_req_wait_cycle <= '0';
else
rd_req_wait_cycle <= '0';
if dma_rd_req_i = '1' and rd_req_wait_cycle = '0' then
axi_arvalid <= '1';
axi_araddr <= dma_rd_addr_i;
axi_arlen <= dma_rd_len_i;
end if;
if axi_arvalid = '1' and M_AXI_ARREADY = '1' then
axi_arvalid <= '0';
dma_rd_req_ack_o <= '1';
rd_req_wait_cycle <= '1';
end if;
end if;
end if;
end process;
end action_axi_master;
| apache-2.0 | 9cb6135664cd6849fb9f843a65f04ed8 | 0.491141 | 3.305419 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/RTL/CLK_DIV_FS.vhd | 1 | 2,296 | ----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: bryan mealy
--
-- Create Date: 15:27:40 04/27/2007
-- Design Name:
-- Module Name: CLK_DIV_FS
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This divides the input clock frequency into two slower
-- frequencies. The frequencies are set by the the MAX_COUNT
-- constant in the declarative region of the architecture.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock
-----------------------------------------------------------------------
entity clk_div_fs is
Port ( CLK : in std_logic;
FCLK,SCLK : out std_logic);
end clk_div_fs;
architecture my_clk_div of clk_div_fs is
constant MAX_COUNT_SLOW : integer := (10000000); -- clock divider
constant MAX_COUNT_FAST : integer := (22000000); -- clock divider
signal tmp_clks : std_logic := '0';
signal tmp_clkf : std_logic := '0';
begin
my_div_slow: process (clk,tmp_clks)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT_SLOW) then
tmp_clks <= not tmp_clks;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
SCLK <= tmp_clks;
end process my_div_slow;
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT_FAST) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
FCLK <= tmp_clkf;
end process my_div_fast;
end my_clk_div;
| mit | 2ddc92df0be485d14f1db926716827b1 | 0.456446 | 4.25974 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment3-Program_Counter/RTL/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000080804A308A012A40";
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000003B00000000";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"00000000000000000000000000000000000000000000000080804A308A012A40",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000003B00000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | c199cd5b415a7f50840d9c89c94447ef | 0.735725 | 6.5 | false | false | false | false |
alpenwasser/pitaya | doc/report/sandbox/code-listings/code/trigger.vhd | 1 | 11,711 | ----------------------------------------------------------------------------------
--
-- trigger.vhd
--
-- (c) 2015 - 2016
-- L. Schrittwieser
-- N. Huesser
-- D. Walser
--
----------------------------------------------------------------------------------
--
-- Trigger logic piece which compares two values
-- and triggers if it matches the configuration (higher, lower).
-- The module has programmable comparison values and modes (higher, lower)
-- The module also features pulse-width triggering
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trigger is
generic (
DataWidth : integer := 14;
TimeStampWidth : integer := 48;
TimerWidth : integer := 14
);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DataxDI : in unsigned(DataWidth - 1 downto 0);
TimexDI : in unsigned(TimeStampWidth - 1 downto 0);
Word1xDI : in unsigned(DataWidth - 1 downto 0);
Mode1xSI : in std_logic; -- 1 => higher, 0 => lower
Word2xDI : in unsigned(TimerWidth - 1 downto 0);
Mode2xSI : in unsigned(1 downto 0); -- 00 => none, 01 => pulse-width-longer, 10 => pulse-width-shorter
HysterxDI : in unsigned(DataWidth - 1 downto 0);
ArmxSI : in std_logic;
StrobexSI : in std_logic;
StrobexSO : out std_logic := '0';
FirexSO : out std_logic := '0';
DataxDO : out unsigned(DataWidth - 1 downto 0) := (others => '0');
TimexDO : out unsigned(TimeStampWidth - 1 downto 0) := (others => '0')
);
end trigger;
architecture Behavioral of trigger is
constant TIMER_MAX : unsigned(TimerWidth - 1 downto 0) := (others => '1');
signal DataxDP, DataxDN : unsigned(DataWidth - 1 downto 0) := (others => '0');
signal TimexDP, TimexDN : unsigned(TimeStampWidth - 1 downto 0) := (others => '0');
signal Word1xDN, Word1xDP : unsigned(DataWidth - 1 downto 0) := (others => '0');
signal Mode1xSN, Mode1xSP : std_logic := '0';
signal Word2xDN, Word2xDP : unsigned(TimerWidth - 1 downto 0) := (others => '0');
signal Mode2xSN, Mode2xSP : unsigned(1 downto 0) := (others => '0');
signal HysterxDN, HysterxDP : unsigned(DataWidth - 1 downto 0) := (others => '0');
signal FirexS : std_logic := '0';
signal FirexSN : std_logic := '0';
signal StrobexSN, StrobexSP : std_logic := '0';
signal ArmedxSP, ArmedxSN : std_logic := '0';
signal FiredxSN, FiredxSP : std_logic := '0';
signal TmrCntxDN, TmrCntxDP : unsigned(TimerWidth - 1 downto 0) := (others => '0');
signal WasFulfilledxSN, WasFulfilledxSP : std_logic := '0';
signal RuntStatexSN, RuntStatexSP : unsigned(2 downto 0) := (others => '0');
signal Greater1xS : std_logic := '0';
signal Lower1xS : std_logic := '0';
signal Greater2xS : std_logic := '0';
signal Lower2xS : std_logic := '0';
begin
FirexSO <= FirexS;
DataxDO <= DataxDP;
TimexDO <= TimexDP;
StrobexSN <= StrobexSI;
StrobexSO <= StrobexSP;
-- TODO: Map system time to TimexDN
COMP1 : entity work.schmitttrigger
generic map(
Width => DataWidth
)
port map(
SigxDI => DataxDP,
DeltaxDI => HysterxDP,
BotxDI => Word1xDP,
GreaterxSO => Greater1xS,
LowerxSO => Lower1xS
);
COMP2 : entity work.schmitttrigger
generic map(
Width => DataWidth
)
port map(
SigxDI => DataxDP,
DeltaxDI => HysterxDP,
BotxDI => Word2xDP,
GreaterxSO => Greater2xS,
LowerxSO => Lower2xS
);
process(ArmedxSP, ArmxSI, Word1xDI, Word1xDP, Mode1xSI, Mode1xSP, Mode2xSI,
Mode2xSP, Word2xDI, Word2xDP, HysterxDI, HysterxDP)
begin
ArmedxSN <= ArmedxSP; -- default: do nothing
Word2xDN <= Word2xDP;
Word1xDN <= Word1xDP;
Mode1xSN <= Mode1xSP;
Mode2xSN <= Mode2xSP;
HysterxDN <= HysterxDP;
if ArmxSI = '1' then
ArmedxSN <= '1';
Word1xDN <= Word1xDI;
Mode1xSN <= Mode1xSI;
Word2xDN <= Word2xDI;
Mode2xSN <= Mode2xSI;
HysterxDN <= HysterxDI;
end if;
end process;
process(ClkxCI)
begin
if rising_edge(ClkxCI) then
DataxDP <= DataxDN;
if RstxRI = '1' then
StrobexSP <= StrobexSN;
Mode1xSP <= '0';
Mode2xSP <= (others => '0');
Word1xDP <= (others => '0');
TimexDP <= (others => '0');
TmrCntxDP <= (others => '0');
Word2xDP <= (others => '0');
HysterxDP <= (others => '0');
ArmedxSP <= '0';
FiredxSP <= '0';
WasFulfilledxSP <= '0';
RuntStatexSP <= (others => '0');
else
StrobexSP <= StrobexSN;
Mode1xSP <= Mode1xSN;
Mode2xSP <= Mode2xSN;
Word1xDP <= Word1xDN;
TimexDP <= TimexDN;
TmrCntxDP <= TmrCntxDN;
Word2xDP <= Word2xDN;
HysterxDP <= HysterxDN;
ArmedxSP <= ArmedxSN;
FiredxSP <= FiredxSN;
WasFulfilledxSP <= WasFulfilledxSN;
RuntStatexSP <= RuntStatexSN;
end if;
end if;
end process;
process(ArmedxSP, DataxDI, DataxDP, FiredxSP, Greater1xS, Lower1xS, Greater2xS, Lower2xS, Mode1xSP,
Mode2xSP, StrobexSP, Word2xDP, TmrCntxDP, HysterxDP, WasFulfilledxSP, RuntStatexSP)
begin
FirexS <= '0';
FiredxSN <= FiredxSP;
TmrCntxDN <= TmrCntxDP;
WasFulfilledxSN <= WasFulfilledxSP;
RuntStatexSN <= RuntStatexSP;
DataxDN <= DataxDP;
if StrobexSP = '1' then
DataxDN <= DataxDI;
end if;
-- if trigger is active and has not yet triggered
if ArmedxSP = '1' and FiredxSP = '0' then
-- if Slope timer is running and precondition for a slope was fulfilled
if Mode2xSP = "00" and Word2xDP > 0 and WasFulfilledxSP = '1' then
if Word2xDP <= TmrCntxDP then -- Fire Slope trigger
FirexS <= '1';
FiredxSN <= '1';
end if;
end if;
-- Runt / OoW Trigger
if Mode2xSP = "11" then
-- Out of Window
if Word2xDP <= Word1xDP and (Greater1xS = '1' or Lower2xS = '1') then
FirexS <= '1';
FiredxSN <= '1';
-- Runt Trigger Logic
else
case RuntStatexSP is
when "000" => -- not armed yet
if Lower1xS = '1' then -- below low level => ready for positive runt pulse
RuntStatexSN <= "101";
elsif Greater2xS = '1' then -- above high level => ready for negative runt pulse
RuntStatexSN <= "100";
end if;
when "101" => -- ready for positive runt pulse
if Greater1xS = '1' then -- passing low level for positive runt pulse => ready to fire trigger
RuntStatexSN <= "111";
end if;
when "100" => -- ready for negative runt pulse
if Lower2xS = '1' then -- passing high level for negative runt pulse => ready to fire trigger
RuntStatexSN <= "110";
end if;
when "111" => -- ready to fire trigger for positive runt pulse
if Lower1xS = '1' then -- below low level => we have a positive runt pulse!
if Mode1xSP = '1' then -- we are indeed looking for a positive runt pulse
FirexS <= '1';
FiredxSN <= '1';
else -- ignore it and be ready for an additional positive runt pulse
RuntStatexSN <= "101";
end if;
elsif Greater2xS = '1' then -- above high level => was no positive runt pulse => be ready for negative runt pulse
RuntStatexSN <= "100";
end if;
when "110" => -- ready to fire trigger for negative runt pulse
if Greater2xS = '1' then -- above high level => we have a negative runt pulse!
if Mode1xSP = '0' then -- we are indeed looking for a negative runt pulse
FirexS <= '1';
FiredxSN <= '1';
else -- ignore it and be ready for an additional negative runt pulse
RuntStatexSN <= "100";
end if;
elsif Lower1xS = '1' then -- below low level => was no negative runt pulse => be ready for positive runt pulse
RuntStatexSN <= "101";
end if;
when others => null;
end case;
end if;
-- Signal stays in between levels for slope measurement
elsif Mode2xSP = "00" and Lower1xS = '0' and Greater1xS = '0' then
-- count for slope if possible
if TmrCntxDP < TIMER_MAX then
TmrCntxDN <= TmrCntxDP + 1;
end if;
-- other Trigger
elsif (Mode1xSP = '1' and Greater1xS = '1') or (Mode1xSP = '0' and Lower1xS = '1') then
-- count for pulse-width if possible
if (Mode2xSP = "10" or Mode2xSP = "01") and TmrCntxDP < TIMER_MAX then
TmrCntxDN <= TmrCntxDP + 1;
end if;
-- Edge trigger
if Mode2xSP = "00" then
if Word2xDP > 0 then -- slope timer mode active
TmrCntxDN <= (others => '0'); -- "reset" trigger to restart slope timer at next edge and do not! fire the trigger yet
WasFulfilledxSN <= '0'; -- it has to start a new edge first
elsif WasFulfilledxSP = '1' then -- usual edge Trigger
FirexS <= '1';
FiredxSN <= '1';
end if;
-- pulse width longer
elsif Mode2xSP = "01" then
if Word2xDP <= TmrCntxDP then
FirexS <= '1';
FiredxSN <= '1';
end if;
-- pulse width shorter
elsif Mode2xSP = "10" then
WasFulfilledxSN <= '1'; -- start of pulse was reached
end if;
-- no Trigger
elsif (Mode1xSP = '0' and Greater1xS = '1') or (Mode1xSP = '1' and Lower1xS = '1') then
TmrCntxDN <= (others => '0'); -- reset pulse-width timer and set slope timer to zero for start as soon as intended
if Mode2xSP = "00" then -- Signal is ready to start an edge
WasFulfilledxSN <= '1';
end if;
-- pulse width shorter
if Mode2xSP = "10" then
if Word2xDP > TmrCntxDP and WasFulfilledxSP = '1' then -- pulse was indeed shorter!
FirexS <= '1';
FiredxSN <= '1';
else -- (reset counter and) demand a new pulse
WasFulfilledxSN <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | a08a301ccb063fcc7d5aca50c0e84697 | 0.508326 | 4.32779 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/hdl/RAT.vhd | 1 | 33,092 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Fri Oct 27 14:48:24 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target RAT.bd
--Design : RAT
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ALU_imp_CAYOB2 is
port (
ALU_OPY_SEL : in STD_LOGIC;
ALU_Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
C_FLAG : out STD_LOGIC;
C_IN : in STD_LOGIC;
IMMED : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_X : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_Y : in STD_LOGIC_VECTOR ( 7 downto 0 );
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
Z_FLAG : out STD_LOGIC
);
end ALU_imp_CAYOB2;
architecture STRUCTURE of ALU_imp_CAYOB2 is
component RAT_Mux2x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Mux2x1_8_0_0;
component RAT_alu_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC
);
end component RAT_alu_0_0;
signal A_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal B_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal C_IN_1 : STD_LOGIC;
signal Mux2x1_8_0_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal REGOUT_Y_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SEL_1 : STD_LOGIC;
signal Sel_2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal alu_0_C_FLAG : STD_LOGIC;
signal alu_0_SUM : STD_LOGIC_VECTOR ( 7 downto 0 );
signal alu_0_Z_FLAG : STD_LOGIC;
begin
A_1(7 downto 0) <= REGOUT_X(7 downto 0);
B_1(7 downto 0) <= IMMED(7 downto 0);
C_FLAG <= alu_0_C_FLAG;
C_IN_1 <= C_IN;
REGOUT_Y_1(7 downto 0) <= REGOUT_Y(7 downto 0);
SEL_1 <= ALU_OPY_SEL;
SUM(7 downto 0) <= alu_0_SUM(7 downto 0);
Sel_2(3 downto 0) <= ALU_Sel(3 downto 0);
Z_FLAG <= alu_0_Z_FLAG;
Mux2x1_8_0: component RAT_Mux2x1_8_0_0
port map (
A(7 downto 0) => REGOUT_Y_1(7 downto 0),
B(7 downto 0) => B_1(7 downto 0),
SEL => SEL_1,
X(7 downto 0) => Mux2x1_8_0_X(7 downto 0)
);
alu_0: component RAT_alu_0_0
port map (
A(7 downto 0) => A_1(7 downto 0),
B(7 downto 0) => Mux2x1_8_0_X(7 downto 0),
C_FLAG => alu_0_C_FLAG,
C_IN => C_IN_1,
SUM(7 downto 0) => alu_0_SUM(7 downto 0),
Sel(3 downto 0) => Sel_2(3 downto 0),
Z_FLAG => alu_0_Z_FLAG
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FlagRegisters_imp_9QD03I is
port (
CLK : in STD_LOGIC;
C_CLR : in STD_LOGIC;
C_IN_FLAG : in STD_LOGIC;
C_LD : in STD_LOGIC;
C_OUT_FLAG : out STD_LOGIC;
C_SET : in STD_LOGIC;
EXT_INTERRUPT : in STD_LOGIC_VECTOR ( 0 to 0 );
INTERRUPT : out STD_LOGIC_VECTOR ( 0 to 0 );
I_CLR : in STD_LOGIC;
I_SET : in STD_LOGIC;
Z_CLR : in STD_LOGIC;
Z_IN_FLAG : in STD_LOGIC;
Z_LD : in STD_LOGIC;
Z_OUT_FLAG : out STD_LOGIC;
Z_SET : in STD_LOGIC
);
end FlagRegisters_imp_9QD03I;
architecture STRUCTURE of FlagRegisters_imp_9QD03I is
component RAT_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component RAT_util_vector_logic_0_0;
component RAT_FlagReg_0_0 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_0_0;
component RAT_FlagReg_0_1 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_0_1;
component RAT_FlagReg_1_0 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_1_0;
signal CLR1_1 : STD_LOGIC;
signal CLR_1 : STD_LOGIC;
signal CLR_2 : STD_LOGIC;
signal IN_FLAG_1 : STD_LOGIC;
signal IN_FLAG_2 : STD_LOGIC;
signal I_OUT_FLAG : STD_LOGIC;
signal LD_1 : STD_LOGIC;
signal LD_2 : STD_LOGIC;
signal Net : STD_LOGIC;
signal Op2_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal SET1_1 : STD_LOGIC;
signal SET_1 : STD_LOGIC;
signal SET_2 : STD_LOGIC;
signal VECTOR_AND_Res : STD_LOGIC_VECTOR ( 0 to 0 );
begin
CLR1_1 <= Z_CLR;
CLR_1 <= C_CLR;
CLR_2 <= I_CLR;
INTERRUPT(0) <= VECTOR_AND_Res(0);
IN_FLAG_1 <= C_IN_FLAG;
IN_FLAG_2 <= Z_IN_FLAG;
LD_1 <= C_LD;
LD_2 <= Z_LD;
Net <= CLK;
Op2_1(0) <= EXT_INTERRUPT(0);
SET1_1 <= Z_SET;
SET_1 <= C_SET;
SET_2 <= I_SET;
C: component RAT_FlagReg_0_1
port map (
CLK => Net,
CLR => CLR_1,
IN_FLAG => IN_FLAG_1,
LD => LD_1,
OUT_FLAG => C_OUT_FLAG,
SET => SET_1
);
I: component RAT_FlagReg_0_0
port map (
CLK => Net,
CLR => CLR_2,
IN_FLAG => '0',
LD => '0',
OUT_FLAG => I_OUT_FLAG,
SET => SET_2
);
VECTOR_AND: component RAT_util_vector_logic_0_0
port map (
Op1(0) => I_OUT_FLAG,
Op2(0) => Op2_1(0),
Res(0) => VECTOR_AND_Res(0)
);
Z: component RAT_FlagReg_1_0
port map (
CLK => Net,
CLR => CLR1_1,
IN_FLAG => IN_FLAG_2,
LD => LD_2,
OUT_FLAG => Z_OUT_FLAG,
SET => SET1_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ProgramCounter_imp_FFPXUZ is
port (
ADDRESS : out STD_LOGIC_VECTOR ( 0 to 9 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
INC : in STD_LOGIC;
LOAD : in STD_LOGIC;
RESET : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end ProgramCounter_imp_FFPXUZ;
architecture STRUCTURE of ProgramCounter_imp_FFPXUZ is
component RAT_Mux4x1_10_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_Mux4x1_10_0_0;
component RAT_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_xlconstant_0_0;
component RAT_Counter10bit_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
end component RAT_Counter10bit_0_0;
signal A_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal B_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal CLK_1 : STD_LOGIC;
signal Counter10bit_0_COUNT : STD_LOGIC_VECTOR ( 0 to 9 );
signal INC_1 : STD_LOGIC;
signal LOAD_1 : STD_LOGIC;
signal Mux4x1_10_0_X : STD_LOGIC_VECTOR ( 9 downto 0 );
signal RESET_1 : STD_LOGIC;
signal SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
ADDRESS(0 to 9) <= Counter10bit_0_COUNT(0 to 9);
A_1(9 downto 0) <= FROM_IMMED(9 downto 0);
B_1(9 downto 0) <= B(9 downto 0);
CLK_1 <= CLK;
INC_1 <= INC;
LOAD_1 <= LOAD;
RESET_1 <= RESET;
SEL_1(1 downto 0) <= SEL(1 downto 0);
Counter10bit_0: component RAT_Counter10bit_0_0
port map (
CLK => CLK_1,
COUNT(0 to 9) => Counter10bit_0_COUNT(0 to 9),
Din(0) => Mux4x1_10_0_X(9),
Din(1) => Mux4x1_10_0_X(8),
Din(2) => Mux4x1_10_0_X(7),
Din(3) => Mux4x1_10_0_X(6),
Din(4) => Mux4x1_10_0_X(5),
Din(5) => Mux4x1_10_0_X(4),
Din(6) => Mux4x1_10_0_X(3),
Din(7) => Mux4x1_10_0_X(2),
Din(8) => Mux4x1_10_0_X(1),
Din(9) => Mux4x1_10_0_X(0),
INC => INC_1,
LOAD => LOAD_1,
RESET => RESET_1
);
Mux4x1_10_0: component RAT_Mux4x1_10_0_0
port map (
A(9 downto 0) => A_1(9 downto 0),
B(9 downto 0) => B_1(9 downto 0),
C(9 downto 0) => xlconstant_0_dout(9 downto 0),
D(9 downto 0) => B"0000000000",
SEL(1 downto 0) => SEL_1(1 downto 0),
X(9 downto 0) => Mux4x1_10_0_X(9 downto 0)
);
xlconstant_0: component RAT_xlconstant_0_0
port map (
dout(9 downto 0) => xlconstant_0_dout(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ProgramROM_SLICED_imp_MYEMEW is
port (
ADDRESS : in STD_LOGIC_VECTOR ( 0 to 9 );
ADDRX : out STD_LOGIC_VECTOR ( 4 downto 0 );
ADDRY : out STD_LOGIC_VECTOR ( 4 downto 0 );
CLK : in STD_LOGIC;
IMMED : out STD_LOGIC_VECTOR ( 9 downto 0 );
IMMED_VAL : out STD_LOGIC_VECTOR ( 7 downto 0 );
OPCODE_HI_5 : out STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end ProgramROM_SLICED_imp_MYEMEW;
architecture STRUCTURE of ProgramROM_SLICED_imp_MYEMEW is
component RAT_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_xlslice_0_0;
component RAT_slice_12_3_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_12_3_0;
component RAT_slice_17_13_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component RAT_slice_17_13_0;
component RAT_slice_1_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_slice_1_0_0;
component RAT_slice_7_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_7_0_0;
component RAT_slice_12_8_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_12_8_0;
component RAT_prog_rom_0_0 is
port (
ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 );
INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 );
CLK : in STD_LOGIC
);
end component RAT_prog_rom_0_0;
signal ADDRESS_1 : STD_LOGIC_VECTOR ( 0 to 9 );
signal CLK_1 : STD_LOGIC;
signal prog_rom_0_INSTRUCTION : STD_LOGIC_VECTOR ( 17 downto 0 );
signal slice_12_3_Dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal slice_12_8_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
signal slice_17_13_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
signal slice_1_0_Dout : STD_LOGIC_VECTOR ( 1 downto 0 );
signal slice_7_0_Dout : STD_LOGIC_VECTOR ( 7 downto 0 );
signal slice_7_3_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
ADDRESS_1(0 to 9) <= ADDRESS(0 to 9);
ADDRX(4 downto 0) <= slice_12_8_Dout(4 downto 0);
ADDRY(4 downto 0) <= slice_7_3_Dout(4 downto 0);
CLK_1 <= CLK;
IMMED(9 downto 0) <= slice_12_3_Dout(9 downto 0);
IMMED_VAL(7 downto 0) <= slice_7_0_Dout(7 downto 0);
OPCODE_HI_5(4 downto 0) <= slice_17_13_Dout(4 downto 0);
OPCODE_LO_2(1 downto 0) <= slice_1_0_Dout(1 downto 0);
prog_rom_0: component RAT_prog_rom_0_0
port map (
ADDRESS(9) => ADDRESS_1(0),
ADDRESS(8) => ADDRESS_1(1),
ADDRESS(7) => ADDRESS_1(2),
ADDRESS(6) => ADDRESS_1(3),
ADDRESS(5) => ADDRESS_1(4),
ADDRESS(4) => ADDRESS_1(5),
ADDRESS(3) => ADDRESS_1(6),
ADDRESS(2) => ADDRESS_1(7),
ADDRESS(1) => ADDRESS_1(8),
ADDRESS(0) => ADDRESS_1(9),
CLK => CLK_1,
INSTRUCTION(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0)
);
slice_12_3: component RAT_xlslice_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(9 downto 0) => slice_12_3_Dout(9 downto 0)
);
slice_12_8: component RAT_slice_7_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_12_8_Dout(4 downto 0)
);
slice_17_13: component RAT_slice_12_3_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_17_13_Dout(4 downto 0)
);
slice_1_0: component RAT_slice_17_13_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(1 downto 0) => slice_1_0_Dout(1 downto 0)
);
slice_7_0: component RAT_slice_1_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(7 downto 0) => slice_7_0_Dout(7 downto 0)
);
slice_7_3: component RAT_slice_12_8_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_7_3_Dout(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Registers_imp_1M200Q6 is
port (
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 );
ALU_RESULT : in STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
DIN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
FROM_SCR : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_SP : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_X : out STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_Y : out STD_LOGIC_VECTOR ( 7 downto 0 );
REG_WRSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
WE : in STD_LOGIC
);
end Registers_imp_1M200Q6;
architecture STRUCTURE of Registers_imp_1M200Q6 is
component RAT_RegisterFile_0_0 is
port (
D_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
DX_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
DY_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 );
WE : in STD_LOGIC;
CLK : in STD_LOGIC
);
end component RAT_RegisterFile_0_0;
component RAT_Mux4x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Mux4x1_8_0_0;
component RAT_xlslice_0_1 is
port (
Din : in STD_LOGIC_VECTOR ( 9 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_xlslice_0_1;
signal ADRX_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ADRY_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal A_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CLK_1 : STD_LOGIC;
signal C_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal D_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal FROM_SCR_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal Mux4x1_8_0_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RegisterFile_0_DX_OUT : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RegisterFile_0_DY_OUT : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal WE_1 : STD_LOGIC;
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
ADRX_1(4 downto 0) <= ADRX(4 downto 0);
ADRY_1(4 downto 0) <= ADRY(4 downto 0);
A_1(7 downto 0) <= ALU_RESULT(7 downto 0);
CLK_1 <= CLK;
C_1(7 downto 0) <= FROM_SP(7 downto 0);
D_1(7 downto 0) <= DIN_PORT(7 downto 0);
FROM_SCR_1(9 downto 0) <= FROM_SCR(9 downto 0);
REGOUT_X(7 downto 0) <= RegisterFile_0_DX_OUT(7 downto 0);
REGOUT_Y(7 downto 0) <= RegisterFile_0_DY_OUT(7 downto 0);
SEL_1(1 downto 0) <= REG_WRSEL(1 downto 0);
WE_1 <= WE;
Mux4x1_8_0: component RAT_Mux4x1_8_0_0
port map (
A(7 downto 0) => A_1(7 downto 0),
B(7 downto 0) => xlslice_0_Dout(7 downto 0),
C(7 downto 0) => C_1(7 downto 0),
D(7 downto 0) => D_1(7 downto 0),
SEL(1 downto 0) => SEL_1(1 downto 0),
X(7 downto 0) => Mux4x1_8_0_X(7 downto 0)
);
RegisterFile_0: component RAT_RegisterFile_0_0
port map (
ADRX(4 downto 0) => ADRX_1(4 downto 0),
ADRY(4 downto 0) => ADRY_1(4 downto 0),
CLK => CLK_1,
DX_OUT(7 downto 0) => RegisterFile_0_DX_OUT(7 downto 0),
DY_OUT(7 downto 0) => RegisterFile_0_DY_OUT(7 downto 0),
D_IN(7 downto 0) => Mux4x1_8_0_X(7 downto 0),
WE => WE_1
);
xlslice_0: component RAT_xlslice_0_1
port map (
Din(9 downto 0) => FROM_SCR_1(9 downto 0),
Dout(7 downto 0) => xlslice_0_Dout(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ScratchRAM_imp_1YU4LB9 is
port (
CLK : in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_PORTID : in STD_LOGIC_VECTOR ( 7 downto 0 );
FROM_STACK_POINTER : in STD_LOGIC_VECTOR ( 7 downto 0 );
PC_IN : in STD_LOGIC_VECTOR ( 0 to 9 );
REG_ADDR_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
REG_DATA_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
SCR_ADDR_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
SCR_DATA_SEL : in STD_LOGIC;
WE : in STD_LOGIC
);
end ScratchRAM_imp_1YU4LB9;
architecture STRUCTURE of ScratchRAM_imp_1YU4LB9 is
component RAT_ScratchRam_0_0 is
port (
DATA_IN : in STD_LOGIC_VECTOR ( 9 downto 0 );
DATA_OUT : out STD_LOGIC_VECTOR ( 9 downto 0 );
ADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
WE : in STD_LOGIC;
CLK : in STD_LOGIC
);
end component RAT_ScratchRam_0_0;
component RAT_Mux2x1_10_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_Mux2x1_10_0_0;
component RAT_Mux4x1_8_0_1 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Mux4x1_8_0_1;
component RAT_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
In1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_xlconcat_0_0;
component RAT_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component RAT_xlconstant_0_1;
component RAT_Decrementer_0_0 is
port (
I : in STD_LOGIC_VECTOR ( 7 downto 0 );
O : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Decrementer_0_0;
signal A_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal B_1 : STD_LOGIC_VECTOR ( 0 to 9 );
signal B_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CLK_1 : STD_LOGIC;
signal C_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Decrementer_0_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Mux2x1_10_0_X : STD_LOGIC_VECTOR ( 9 downto 0 );
signal Mux4x1_8_0_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal REG_IN_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SEL1_1 : STD_LOGIC;
signal SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ScratchRam_0_DATA_OUT : STD_LOGIC_VECTOR ( 9 downto 0 );
signal WE_1 : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
A_1(7 downto 0) <= REG_ADDR_IN(7 downto 0);
B_1(0 to 9) <= PC_IN(0 to 9);
B_2(7 downto 0) <= FROM_PORTID(7 downto 0);
CLK_1 <= CLK;
C_1(7 downto 0) <= FROM_STACK_POINTER(7 downto 0);
DATA_OUT(9 downto 0) <= ScratchRam_0_DATA_OUT(9 downto 0);
REG_IN_1(7 downto 0) <= REG_DATA_IN(7 downto 0);
SEL1_1 <= SCR_DATA_SEL;
SEL_1(1 downto 0) <= SCR_ADDR_SEL(1 downto 0);
WE_1 <= WE;
Decrementer_0: component RAT_Decrementer_0_0
port map (
I(7 downto 0) => C_1(7 downto 0),
O(7 downto 0) => Decrementer_0_O(7 downto 0)
);
Mux2x1_10_0: component RAT_Mux2x1_10_0_0
port map (
A(9 downto 0) => xlconcat_0_dout(9 downto 0),
B(9) => B_1(0),
B(8) => B_1(1),
B(7) => B_1(2),
B(6) => B_1(3),
B(5) => B_1(4),
B(4) => B_1(5),
B(3) => B_1(6),
B(2) => B_1(7),
B(1) => B_1(8),
B(0) => B_1(9),
SEL => SEL1_1,
X(9 downto 0) => Mux2x1_10_0_X(9 downto 0)
);
Mux4x1_8_0: component RAT_Mux4x1_8_0_1
port map (
A(7 downto 0) => A_1(7 downto 0),
B(7 downto 0) => B_2(7 downto 0),
C(7 downto 0) => C_1(7 downto 0),
D(7 downto 0) => Decrementer_0_O(7 downto 0),
SEL(1 downto 0) => SEL_1(1 downto 0),
X(7 downto 0) => Mux4x1_8_0_X(7 downto 0)
);
ScratchRam_0: component RAT_ScratchRam_0_0
port map (
ADDR(7 downto 0) => Mux4x1_8_0_X(7 downto 0),
CLK => CLK_1,
DATA_IN(9 downto 0) => Mux2x1_10_0_X(9 downto 0),
DATA_OUT(9 downto 0) => ScratchRam_0_DATA_OUT(9 downto 0),
WE => WE_1
);
xlconcat_0: component RAT_xlconcat_0_0
port map (
In0(7 downto 0) => REG_IN_1(7 downto 0),
In1(1 downto 0) => xlconstant_0_dout(1 downto 0),
dout(9 downto 0) => xlconcat_0_dout(9 downto 0)
);
xlconstant_0: component RAT_xlconstant_0_1
port map (
dout(1 downto 0) => xlconstant_0_dout(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RATCPU_imp_157ITB6 is
port (
CLK : in STD_LOGIC;
DIN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
EXT_INTERRRUPT : in STD_LOGIC_VECTOR ( 0 to 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
end RATCPU_imp_157ITB6;
architecture STRUCTURE of RATCPU_imp_157ITB6 is
component RAT_StackPointer_0_0 is
port (
DATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC;
LD : in STD_LOGIC;
INCR : in STD_LOGIC;
DECR : in STD_LOGIC;
CLK : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_StackPointer_0_0;
component RAT_ControlUnit_0_0 is
port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
SP_RESET : out STD_LOGIC;
SP_INCR : out STD_LOGIC;
SP_DECR : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SCR_DATA_SEL : out STD_LOGIC;
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC
);
end component RAT_ControlUnit_0_0;
signal ADDRESS_1 : STD_LOGIC_VECTOR ( 0 to 9 );
signal ADRX_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ADRY_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ALU_C_FLAG : STD_LOGIC;
signal ALU_OPY_SEL_1 : STD_LOGIC;
signal ALU_RESULT_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ALU_Sel_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ALU_Z_FLAG : STD_LOGIC;
signal CLK_1 : STD_LOGIC;
signal C_CLR_1 : STD_LOGIC;
signal C_LD_1 : STD_LOGIC;
signal C_SET_1 : STD_LOGIC;
signal ControlUnit_0_PC_INC : STD_LOGIC;
signal ControlUnit_0_PC_LD : STD_LOGIC;
signal ControlUnit_0_PC_MUX_SEL : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ControlUnit_0_PC_RESET : STD_LOGIC;
signal ControlUnit_0_SCR_ADDR_SEL : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ControlUnit_0_SCR_DATA_SEL : STD_LOGIC;
signal ControlUnit_0_SCR_WR : STD_LOGIC;
signal ControlUnit_0_SP_DECR : STD_LOGIC;
signal ControlUnit_0_SP_INCR : STD_LOGIC;
signal ControlUnit_0_SP_LD : STD_LOGIC;
signal ControlUnit_0_SP_RESET : STD_LOGIC;
signal DIN_PORT_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal FlagRegisters_C_OUT_FLAG : STD_LOGIC;
signal FlagRegisters_INTERRUPT : STD_LOGIC_VECTOR ( 0 to 0 );
signal FlagRegisters_Z_OUT_FLAG : STD_LOGIC;
signal I_CLR_1 : STD_LOGIC;
signal I_SET_1 : STD_LOGIC;
signal Op2_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ProgramROM_SLICED_IMMED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ProgramROM_SLICED_IMMED_VAL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ProgramROM_SLICED_OPCODE_HI_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ProgramROM_SLICED_OPCODE_LO_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal REG_WRSEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal RST_1 : STD_LOGIC;
signal Registers_REGOUT_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Registers_REGOUT_Y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ScratchRAM_DATA_OUT : STD_LOGIC_VECTOR ( 9 downto 0 );
signal StackPointer_0_DOUT : STD_LOGIC_VECTOR ( 7 downto 0 );
signal WE_1 : STD_LOGIC;
signal Z_CLR_1 : STD_LOGIC;
signal Z_LD_1 : STD_LOGIC;
signal Z_SET_1 : STD_LOGIC;
signal NLW_ControlUnit_0_C_FLAG_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_IO_OE_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SHAD_C_LD_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SHAD_Z_LD_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_Z_FLAG_SEL_UNCONNECTED : STD_LOGIC;
begin
CLK_1 <= CLK;
DIN_PORT_1(7 downto 0) <= DIN_PORT(7 downto 0);
OUT_PORT(7 downto 0) <= Registers_REGOUT_X(7 downto 0);
Op2_1(0) <= EXT_INTERRRUPT(0);
PORT_ID(7 downto 0) <= ProgramROM_SLICED_IMMED_VAL(7 downto 0);
RST_1 <= RST;
ALU: entity work.ALU_imp_CAYOB2
port map (
ALU_OPY_SEL => ALU_OPY_SEL_1,
ALU_Sel(3 downto 0) => ALU_Sel_1(3 downto 0),
C_FLAG => ALU_C_FLAG,
C_IN => FlagRegisters_C_OUT_FLAG,
IMMED(7 downto 0) => ProgramROM_SLICED_IMMED_VAL(7 downto 0),
REGOUT_X(7 downto 0) => Registers_REGOUT_X(7 downto 0),
REGOUT_Y(7 downto 0) => Registers_REGOUT_Y(7 downto 0),
SUM(7 downto 0) => ALU_RESULT_1(7 downto 0),
Z_FLAG => ALU_Z_FLAG
);
ControlUnit_0: component RAT_ControlUnit_0_0
port map (
ALU_OPY_SEL => ALU_OPY_SEL_1,
ALU_SEL(3 downto 0) => ALU_Sel_1(3 downto 0),
C => FlagRegisters_C_OUT_FLAG,
CLK => CLK_1,
C_FLAG_CLR => C_CLR_1,
C_FLAG_LD => C_LD_1,
C_FLAG_SEL => NLW_ControlUnit_0_C_FLAG_SEL_UNCONNECTED,
C_FLAG_SET => C_SET_1,
INT => FlagRegisters_INTERRUPT(0),
IO_OE => NLW_ControlUnit_0_IO_OE_UNCONNECTED,
I_FLAG_CLR => I_CLR_1,
I_FLAG_SET => I_SET_1,
OPCODE_HI_5(4 downto 0) => ProgramROM_SLICED_OPCODE_HI_5(4 downto 0),
OPCODE_LO_2(1 downto 0) => ProgramROM_SLICED_OPCODE_LO_2(1 downto 0),
PC_INC => ControlUnit_0_PC_INC,
PC_LD => ControlUnit_0_PC_LD,
PC_MUX_SEL(1 downto 0) => ControlUnit_0_PC_MUX_SEL(1 downto 0),
PC_RESET => ControlUnit_0_PC_RESET,
RF_WR => WE_1,
RF_WR_SEL(1 downto 0) => REG_WRSEL_1(1 downto 0),
RST => RST_1,
SCR_ADDR_SEL(1 downto 0) => ControlUnit_0_SCR_ADDR_SEL(1 downto 0),
SCR_DATA_SEL => ControlUnit_0_SCR_DATA_SEL,
SCR_WR => ControlUnit_0_SCR_WR,
SHAD_C_LD => NLW_ControlUnit_0_SHAD_C_LD_UNCONNECTED,
SHAD_Z_LD => NLW_ControlUnit_0_SHAD_Z_LD_UNCONNECTED,
SP_DECR => ControlUnit_0_SP_DECR,
SP_INCR => ControlUnit_0_SP_INCR,
SP_LD => ControlUnit_0_SP_LD,
SP_RESET => ControlUnit_0_SP_RESET,
Z => FlagRegisters_Z_OUT_FLAG,
Z_FLAG_CLR => Z_CLR_1,
Z_FLAG_LD => Z_LD_1,
Z_FLAG_SEL => NLW_ControlUnit_0_Z_FLAG_SEL_UNCONNECTED,
Z_FLAG_SET => Z_SET_1
);
FlagRegisters: entity work.FlagRegisters_imp_9QD03I
port map (
CLK => CLK_1,
C_CLR => C_CLR_1,
C_IN_FLAG => ALU_C_FLAG,
C_LD => C_LD_1,
C_OUT_FLAG => FlagRegisters_C_OUT_FLAG,
C_SET => C_SET_1,
EXT_INTERRUPT(0) => Op2_1(0),
INTERRUPT(0) => FlagRegisters_INTERRUPT(0),
I_CLR => I_CLR_1,
I_SET => I_SET_1,
Z_CLR => Z_CLR_1,
Z_IN_FLAG => ALU_Z_FLAG,
Z_LD => Z_LD_1,
Z_OUT_FLAG => FlagRegisters_Z_OUT_FLAG,
Z_SET => Z_SET_1
);
ProgramCounter: entity work.ProgramCounter_imp_FFPXUZ
port map (
ADDRESS(0 to 9) => ADDRESS_1(0 to 9),
B(9 downto 0) => ScratchRAM_DATA_OUT(9 downto 0),
CLK => CLK_1,
FROM_IMMED(9 downto 0) => ProgramROM_SLICED_IMMED(9 downto 0),
INC => ControlUnit_0_PC_INC,
LOAD => ControlUnit_0_PC_LD,
RESET => ControlUnit_0_PC_RESET,
SEL(1 downto 0) => ControlUnit_0_PC_MUX_SEL(1 downto 0)
);
ProgramROM_SLICED: entity work.ProgramROM_SLICED_imp_MYEMEW
port map (
ADDRESS(0 to 9) => ADDRESS_1(0 to 9),
ADDRX(4 downto 0) => ADRX_1(4 downto 0),
ADDRY(4 downto 0) => ADRY_1(4 downto 0),
CLK => CLK_1,
IMMED(9 downto 0) => ProgramROM_SLICED_IMMED(9 downto 0),
IMMED_VAL(7 downto 0) => ProgramROM_SLICED_IMMED_VAL(7 downto 0),
OPCODE_HI_5(4 downto 0) => ProgramROM_SLICED_OPCODE_HI_5(4 downto 0),
OPCODE_LO_2(1 downto 0) => ProgramROM_SLICED_OPCODE_LO_2(1 downto 0)
);
Registers: entity work.Registers_imp_1M200Q6
port map (
ADRX(4 downto 0) => ADRX_1(4 downto 0),
ADRY(4 downto 0) => ADRY_1(4 downto 0),
ALU_RESULT(7 downto 0) => ALU_RESULT_1(7 downto 0),
CLK => CLK_1,
DIN_PORT(7 downto 0) => DIN_PORT_1(7 downto 0),
FROM_SCR(9 downto 0) => ScratchRAM_DATA_OUT(9 downto 0),
FROM_SP(7 downto 0) => StackPointer_0_DOUT(7 downto 0),
REGOUT_X(7 downto 0) => Registers_REGOUT_X(7 downto 0),
REGOUT_Y(7 downto 0) => Registers_REGOUT_Y(7 downto 0),
REG_WRSEL(1 downto 0) => REG_WRSEL_1(1 downto 0),
WE => WE_1
);
ScratchRAM: entity work.ScratchRAM_imp_1YU4LB9
port map (
CLK => CLK_1,
DATA_OUT(9 downto 0) => ScratchRAM_DATA_OUT(9 downto 0),
FROM_PORTID(7 downto 0) => ProgramROM_SLICED_IMMED_VAL(7 downto 0),
FROM_STACK_POINTER(7 downto 0) => StackPointer_0_DOUT(7 downto 0),
PC_IN(0 to 9) => ADDRESS_1(0 to 9),
REG_ADDR_IN(7 downto 0) => Registers_REGOUT_Y(7 downto 0),
REG_DATA_IN(7 downto 0) => Registers_REGOUT_X(7 downto 0),
SCR_ADDR_SEL(1 downto 0) => ControlUnit_0_SCR_ADDR_SEL(1 downto 0),
SCR_DATA_SEL => ControlUnit_0_SCR_DATA_SEL,
WE => ControlUnit_0_SCR_WR
);
StackPointer_0: component RAT_StackPointer_0_0
port map (
CLK => CLK_1,
DATA(7 downto 0) => Registers_REGOUT_X(7 downto 0),
DECR => ControlUnit_0_SP_DECR,
DOUT(7 downto 0) => StackPointer_0_DOUT(7 downto 0),
INCR => ControlUnit_0_SP_INCR,
LD => ControlUnit_0_SP_LD,
RST => ControlUnit_0_SP_RESET
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT is
port (
CLK : in STD_LOGIC;
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RAT : entity is "RAT,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=RAT,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=34,numReposBlks=27,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=2,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=16,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of RAT : entity is "RAT.hwdef";
end RAT;
architecture STRUCTURE of RAT is
signal CLK_1 : STD_LOGIC;
signal DIN_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Op2_2 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ProgramROM_SLICED_Dout3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RATCPU_REGOUT_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RST_1 : STD_LOGIC;
begin
CLK_1 <= CLK;
DIN_1(7 downto 0) <= IN_PORT(7 downto 0);
OUT_PORT(7 downto 0) <= RATCPU_REGOUT_X(7 downto 0);
Op2_2(0) <= INT_IN(0);
PORT_ID(7 downto 0) <= ProgramROM_SLICED_Dout3(7 downto 0);
RST_1 <= RST;
RATCPU: entity work.RATCPU_imp_157ITB6
port map (
CLK => CLK_1,
DIN_PORT(7 downto 0) => DIN_1(7 downto 0),
EXT_INTERRRUPT(0) => Op2_2(0),
OUT_PORT(7 downto 0) => RATCPU_REGOUT_X(7 downto 0),
PORT_ID(7 downto 0) => ProgramROM_SLICED_Dout3(7 downto 0),
RST => RST_1
);
end STRUCTURE;
| mit | 5993c7fa75227355572b238dec61f0cc | 0.608244 | 2.887609 | false | false | false | false |
stefanct/aua | hw/alu/src/alu_old.vhd | 1 | 8,141 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
architecture old of alu is
signal carry: std_logic;
signal carry_nxt: std_logic;
--constant max_value : integer := 2**word_t'length - 1;
--constant min_value : integer := -2**(word_t'length-1); --so irgendwas halt... falls dus ueberhaupt brauchst
constant max_value: integer := 2**15-1;
constant min_value: integer := -2**15;
-- function calc_overflow(a: in word_t; b: in word_t) return bit is
-- begin
-- if signed(a) > (max_value - signed(b)) and signed(b) > 0 then
-- return '1';
-- elsif signed(a) < (min_value - signed(b)) and signed(b) < 0 then
-- return '1';
-- else
-- return '0';
-- end if;
-- end function;
begin
sync_carry: process (clk, reset)
begin
if reset = '1' then
carry <= '0';
elsif rising_edge(clk) then
carry <= carry_nxt;
end if;
end process;
process(opcode, opa, opb, carry)
variable tmp: word_t;
variable tmp_carry: std_logic_vector(16 downto 0);
variable tmp_mul: std_logic_vector(31 downto 0);
begin
carry_nxt <= carry;
case opcode(5 downto 0) is
when "011000" => --addi
result <= std_logic_vector(signed(opa) + signed(opb));
when "011001" => --addi
result <= std_logic_vector(signed(opa) + signed(opb));
when "011010" => --addi
result <= std_logic_vector(signed(opa) + signed(opb));
when "011011" => --addi
result <= std_logic_vector(signed(opa) + signed(opb));
when "011100" => --muli
if opb(6) = '1' then
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '0')&opb(5 downto 0))));
else
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '0')&opb(5 downto 0))));
end if;
result <= tmp_mul(15 downto 0);
when "011101" => --muli
if opb(6) = '1' then
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '1')&opb(5 downto 0))));
else
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '0')&opb(5 downto 0))));
end if;
result <= tmp_mul(15 downto 0);
when "011110" => --muli
if opb(6) = '1' then
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '1')&opb(5 downto 0))));
else
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '0')&opb(5 downto 0))));
end if;
result <= tmp_mul(15 downto 0);
when "011111" => --muli
if opb(6) = '1' then
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '1')&opb(5 downto 0))));
else
tmp_mul := std_logic_vector(signed(opa) * signed(std_logic_vector'((15 downto 6 => '0')&opb(5 downto 0))));
end if;
result <= tmp_mul(15 downto 0);
when "100000" => -- add
tmp_carry := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)) );
carry_nxt <= tmp_carry(16);
result <= tmp_carry(15 downto 0);
when "100001" => -- addc
tmp_carry := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)) + (x"0000"&carry));
carry_nxt <= tmp_carry(16);
result <= tmp_carry(15 downto 0);
when "100010" => --sub
tmp_carry := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)));
carry_nxt <= tmp_carry(16);
result <= tmp_carry(15 downto 0);
when "100011" => -- subc
tmp_carry := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)) - (x"0000"&carry));
carry_nxt <= tmp_carry(16);
result <= tmp_carry(15 downto 0);
when "100100" => -- mul
tmp_mul := std_logic_vector(signed(opa) * signed(opb));
result <= tmp_mul(15 downto 0);
when "100101" => -- mulu
tmp_mul := std_logic_vector(unsigned(opa) * unsigned(opb));
result <= tmp_mul(15 downto 0);
when "100110" => -- mulh
tmp_mul := std_logic_vector(signed(opa) * signed(opb));
result <= tmp_mul(31 downto 16);
when "100111" => -- mulhu
tmp_mul := std_logic_vector(unsigned(opa) * unsigned(opb));
result <= tmp_mul(31 downto 16);
when "101000" => -- or
result <= opa or opb;
when "101001" => -- and
result <= opa and opb;
when "101010" => -- xor
result <= opa xor opb;
when "101011" => -- not
result <= not opb;
when "101100" => -- neg
result <= std_logic_vector(unsigned(not opb) + 1);
when "101101" => -- asr
result <= to_stdlogicvector(to_bitvector(opb) sra 1);
when "101110" => -- lsl
result <= std_logic_vector(unsigned(opb) sll 1);
when "101111" => -- lsr
result <= std_logic_vector(unsigned(opb) srl 1);
when "110000" => -- lsli
result <= std_logic_vector(unsigned(opa) sll to_integer(unsigned(opb(3 downto 0))));
when "110001" => -- lsri
result <= std_logic_vector(unsigned(opa) srl to_integer(unsigned(opb(3 downto 0))));
when "110010" => -- scb
tmp := x"0001";
tmp := std_logic_vector(unsigned(tmp) sll to_integer(unsigned(opb(3 downto 0))));
if opb(4) = '1' then
result <= opa or tmp;
else
result <= opa and (not tmp);
end if;
when "110011" => -- roti
if opb(4) = '0' then -- rotl
result <= std_logic_vector(unsigned(opa) rol to_integer(unsigned(opb(3 downto 0))));
else -- rotr
result <= std_logic_vector(unsigned(opa) ror to_integer(unsigned(opb(3 downto 0))));
end if;
-- when "110100" => -- cmpv
-- if V = '1' then
-- result <= x"0001";
-- else
-- result <= x"0000";
-- end if;
when "110101" => -- cmplt
if signed(opa) < signed(opb) then
result <= x"0001";
else
result <= x"0000";
end if;
when "110110" => -- cmpltu
if opa < opb then
result <= x"0001";
else
result <= x"0000";
end if;
when "110111" => -- cmplte
if signed(opa) <= signed(opb) then
result <= x"0001";
else
result <= x"0000";
end if;
when "111000" => -- cmplteu
if opa <= opb then
result <= x"0001";
else
result <= x"0000";
end if;
when "111001" => -- cmpe
if opa = opb then
result <= x"0001";
else
result <= x"0000";
end if;
when "111010" => -- cmpei
-- wie gehtn das richtig?
if opa = (("00000000000") & opb(4 downto 0)) then
result <= x"0001";
else
result <= x"0000";
end if;
when "000000" => -- ldi
result <= opa(15 downto 8) & opb(7 downto 0);
when "000001" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000010" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000011" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000100" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000101" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000110" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "000111" => result <= opa(15 downto 8) & opb(7 downto 0);-- ldi
when "001101" => result <= x"0000";-- jmpl
when "001110" => result <= x"0000";-- brez
when "001111" => result <= x"0000";-- brnez
when "010000" => result <= x"0000";-- brezi
when "010001" => result <= x"0000";-- brezi
when "010010" => result <= x"0000";-- brezi
when "010011" => result <= x"0000";-- brezi
when "010100" => result <= x"0000";-- brnezi
when "010101" => result <= x"0000";-- brnezi
when "010110" => result <= x"0000";-- brnezi
when "010111" => result <= x"0000";-- brnezi
when "111011" => result <= opb;-- mov
when "111100" => result <= x"0000";-- ld
when "111101" => result <= x"0000";-- ldb
when "111110" => result <= x"0000";-- st
when "111111" => result <= x"0000";-- stb
when "110100" => result <= x"0000";-- cmpv
when others => result <= x"0000";
end case;
end process;
end old;
| gpl-3.0 | aa1df186067dcfc69295494973bba5ab | 0.549073 | 3.074396 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/MaquinaDeEstadosPrincipal.vhd | 1 | 8,669 | -- Bibliotecas Utilizadas
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
--Declaracao da Entidade
ENTITY MaquinaDeEstadosPrincipal IS
--Generic();
PORT --Entradas e Saidas da entidade
(
CLK_50M : IN std_logic; --Clock dado pela Spartan3 em Hz
PS2_CLK1 : IN std_logic; --Sinal de clock interno do teclado
PS2_DATA1 : IN std_logic; --Sinal de dados interno do teclado
ENTRADAA : OUT std_logic_vector(19 DOWNTO 0);
ENTRADAB : OUT std_logic_vector(19 DOWNTO 0);
FINISH : OUT std_logic;
MDDRESET : OUT std_logic
);
END MaquinaDeEstadosPrincipal;
--Declaracao da arquitetura da entidade
ARCHITECTURE ArcMaquinaDeEstadosPrincipal OF MaquinaDeEstadosPrincipal IS
--Declaracao de tipos
TYPE recebeNumero IS
(
PrimeiroDigA, SegundoDigA, TerceiroDigA, QuartoDigA, QuintoDigA, EsperandoSinal,
PrimeiroDigB, SegundoDigB, TerceiroDigB, QuartoDigB, QuintoDigB, EsperandoEnter, Enviar
);
--Declaracao dos sinais utilizados
signal ascii_start, prev_ascii_start : std_logic ; --Sinal para mapeamento de componente
signal getting_number : recebeNumero := PrimeiroDigA;
signal internal_ascii_code : std_logic_vector(6 downto 0); --Sinal para mapeamento de componente
signal internal_number : integer; --Sinal para mapeamento de componente
signal operandoB : std_logic_vector(7 downto 0); --Operador
signal operandoA : std_logic_vector(7 downto 0); --Operador
--Componente que traduz de codigo entendido pelo teclado para codigo ascii
begin
--Mapeamento dos componentes
ps2_keyboard_to_ascii: entity work.ps2_keyboard_to_ascii port map
(CLK_50M, PS2_CLK1,PS2_DATA1, ascii_start, internal_ascii_code);
--Processo onde os operandos sao obtidos do teclado
Carregar_Dados: process(CLK_50M, ascii_start, internal_ascii_code)
variable entradaA_aux : std_logic_vector(7 downto 0) := (others => '0');
variable entradaA_obtida : std_logic_vector(19 downto 0) := (others => '0');
variable entradaB_aux : std_logic_vector(7 downto 0) := (others => '0');
variable entradaB_obtida : std_logic_vector(19 downto 0) := (others => '0');
variable quocienteCalculado : std_logic_vector(7 downto 0) := "00000000";
variable restoCalculado : std_logic_vector(7 downto 0) := "00000000";
-- variable numBin : std_logic_vector(7 downto 0) := "00000000";
variable finishAuxiliar : std_logic;
begin
if (CLK_50M'event and CLK_50M='1') then
prev_ascii_start <= ascii_start;
case getting_number is
when PrimeiroDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= PrimeiroDigA;
elsif (internal_ascii_code = "0011011") then
getting_number <= PrimeiroDigA;
else
finishAuxiliar := '0';
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(3 downto 0) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= SegundoDigA;
end if;
else
getting_number <= PrimeiroDigA;
end if;
when SegundoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(7 downto 4) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= TerceiroDigA;
end if;
else
getting_number <= SegundoDigA;
end if;
when TerceiroDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(11 downto 8) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= QuartoDigA;
end if;
else
getting_number <= TerceiroDigA;
end if;
when QuartoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then --enter
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(15 downto 12) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= QuintoDigA;
end if;
else
getting_number <= QuartoDigA;
end if;
when QuintoDigA =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= EsperandoSinal;
else
entradaA_aux := "0" & internal_ascii_code;
entradaA_obtida(19 downto 16) := entradaA_aux(3 downto 0);
-- numBin := entradaA_obtida;
getting_number <= EsperandoSinal;
end if;
else
getting_number <= QuintoDigA;
end if;
when EsperandoSinal =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= PrimeiroDigB;
else
getting_number <= EsperandoSinal;
end if;
else
getting_number <= EsperandoSinal;
end if;
when PrimeiroDigB =>
if (prev_ascii_start= '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= PrimeiroDigB;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(3 downto 0) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= SegundoDigB;
end if;
else
getting_number <= PrimeiroDigB;
end if;
when SegundoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(7 downto 4) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= TerceiroDigB;
end if;
else
getting_number <= SegundoDigB;
end if;
when TerceiroDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(11 downto 8) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= QuartoDigB;
end if;
else
getting_number <= TerceiroDigB;
end if;
when QuartoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(15 downto 12) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= QuintoDigB;
end if;
else
getting_number <= QuartoDigB;
end if;
when QuintoDigB =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
else
entradaB_aux := "0" & internal_ascii_code;
entradaB_obtida(19 downto 16) := entradaB_aux(3 downto 0);
-- numBin := entradaB_obtida;
getting_number <= EsperandoEnter;
end if;
else
getting_number <= QuintoDigB;
end if;
when EsperandoEnter =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0001101") then
getting_number <= Enviar;
else
getting_number <= EsperandoEnter;
end if;
else
getting_number <= esperandoEnter;
end if;
when Enviar =>
if (prev_ascii_start = '0' and ascii_start = '1') then
if (internal_ascii_code = "0011011") then
getting_number <= PrimeiroDigA;
MDDreset <= '1';
FINISH <='0';
else
getting_number <= enviar;
MDDreset<='0';
end if;
else
getting_number <= enviar;
entradaB <= entradaB_obtida;
entradaA <= entradaA_obtida;
finishAuxiliar := '1';
MDDreset <= '0';
end if;
end case;
end if;
FINISH <= finishAuxiliar;
end process Carregar_Dados;
end ArcMaquinaDeEstadosPrincipal; | gpl-3.0 | 0780f002705eff1f3f2e9afb0a4ad4a0 | 0.620371 | 3.433267 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/Somador4bits.vhd | 1 | 2,514 | ----------------------------------------------------------------------------------
-- Create Date: 15:52:42 03/28/2017
-- Module Name: Somador4bits - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Somador4bits is
Port ( X : in STD_LOGIC_VECTOR (3 downto 0); --Vetor de bis de entrada;
Y : in STD_LOGIC_VECTOR (3 downto 0); --Vetor de bis de entrada;
Cin : in STD_LOGIC; --Carry de entrada externo;
Cout : out STD_LOGIC; --Flag de carry/borrow;
Ov : out STD_LOGIC; --Flag de overflow;
Z : out STD_LOGIC_VECTOR (3 downto 0));--Saida com soma realziada;
end Somador4bits;
architecture Behavioral of Somador4bits is
component Somador1bit
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC);
end component;
component CarryLookAhead
Port ( P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC;
CLH : out STD_LOGIC_VECTOR (4 downto 0));
end component;
signal C: STD_LOGIC_VECTOR (4 downto 0); -- Vetor com os carry a serem propagados (Ci+1 = Gi + Pi.Ci);
signal P: STD_LOGIC_VECTOR (3 downto 0); -- Operador da soma para propagação de carry (X xor Y);
signal G: STD_LOGIC_VECTOR (3 downto 0); -- Vetor auxiliar para o carrylookahead (X and Y);
signal auxCarry: STD_LOGIC_VECTOR (4 downto 0); -- Carry propagados;
signal auxCarry2: STD_LOGIC_VECTOR (4 downto 0); -- Carry propagados;
begin
C0: CarryLookAhead port map(P => P, G => G, C => Cin, CLH => auxCarry2);
AuxCarry <= AuxCarry2;
-- Z0: Somador1bit port map (X(0),Y(0),Cin, C(0), Z(0), P(0), G(0));
-- Z1: Somador1bit port map (X(1),Y(1),C(0), auxCarry(0), Z(1), P(1), G(1));
-- Z2: Somador1bit port map (X(2),Y(2),C(1), auxCarry(1), Z(2), P(2), G(2));
-- Z3: Somador1bit port map (X(3),Y(3),C(2), auxCarry(2), Z(3), P(3), G(3));
Z0: Somador1bit port map (X(0), Y(0), Cin, C(0), Z(0), P => open, G => open);
Z1: Somador1bit port map (X(1), Y(1), C(0), C(1), Z(1), P => open, G => open);
Z2: Somador1bit port map (X(2), Y(2), C(1), C(2), Z(2), P => open, G => open);
Z3: Somador1bit port map (X(3), Y(3), C(2), C(3), Z(3), P => open, G => open);
Cout <= C(3);
Ov <= C(2) xor C(3);
end Behavioral;
| gpl-3.0 | ee3900395a7c073d9e8f7d2fd0ec2738 | 0.542164 | 2.947245 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_sim_netlist.vhdl | 1 | 4,781 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:20:39 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_sim_netlist.vhdl
-- Design : RAT_Mux4x1_8_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_1_Mux4x1_8 is
port (
X : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
A : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Mux4x1_8_0_1_Mux4x1_8 : entity is "Mux4x1_8";
end RAT_Mux4x1_8_0_1_Mux4x1_8;
architecture STRUCTURE of RAT_Mux4x1_8_0_1_Mux4x1_8 is
begin
\X[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(0),
I1 => B(0),
I2 => C(0),
I3 => SEL(1),
I4 => A(0),
I5 => SEL(0),
O => X(0)
);
\X[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(1),
I1 => B(1),
I2 => C(1),
I3 => SEL(1),
I4 => A(1),
I5 => SEL(0),
O => X(1)
);
\X[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(2),
I1 => B(2),
I2 => C(2),
I3 => SEL(1),
I4 => A(2),
I5 => SEL(0),
O => X(2)
);
\X[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(3),
I1 => B(3),
I2 => C(3),
I3 => SEL(1),
I4 => A(3),
I5 => SEL(0),
O => X(3)
);
\X[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(4),
I1 => B(4),
I2 => C(4),
I3 => SEL(1),
I4 => A(4),
I5 => SEL(0),
O => X(4)
);
\X[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(5),
I1 => B(5),
I2 => C(5),
I3 => SEL(1),
I4 => A(5),
I5 => SEL(0),
O => X(5)
);
\X[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(6),
I1 => B(6),
I2 => C(6),
I3 => SEL(1),
I4 => A(6),
I5 => SEL(0),
O => X(6)
);
\X[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(7),
I1 => B(7),
I2 => C(7),
I3 => SEL(1),
I4 => A(7),
I5 => SEL(0),
O => X(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_1 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Mux4x1_8_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Mux4x1_8_0_1 : entity is "RAT_Mux4x1_8_0_1,Mux4x1_8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Mux4x1_8_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Mux4x1_8_0_1 : entity is "Mux4x1_8,Vivado 2016.4";
end RAT_Mux4x1_8_0_1;
architecture STRUCTURE of RAT_Mux4x1_8_0_1 is
begin
U0: entity work.RAT_Mux4x1_8_0_1_Mux4x1_8
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
C(7 downto 0) => C(7 downto 0),
D(7 downto 0) => D(7 downto 0),
SEL(1 downto 0) => SEL(1 downto 0),
X(7 downto 0) => X(7 downto 0)
);
end STRUCTURE;
| mit | d90f5f361356fdd7487189b8f353caaa | 0.526877 | 2.917023 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_12_3_0/synth/RAT_slice_12_3_0.vhd | 2 | 3,821 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_12_3_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_12_3_0;
ARCHITECTURE RAT_slice_12_3_0_arch OF RAT_slice_12_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_12_3_0_arch : ARCHITECTURE IS "RAT_slice_12_3_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "RAT_slice_12_3_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=17,DIN_TO=13}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 17,
DIN_TO => 13
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_12_3_0_arch;
| mit | cc27948289fcf6c2bb032f638b59a65c | 0.728082 | 3.840201 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_1/sim/design_1_cic_compiler_0_1.vhd | 2 | 7,237 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_1;
ARCHITECTURE design_1_cic_compiler_0_1_arch OF design_1_cic_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_1",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 125,
C_INPUT_WIDTH => 16,
C_OUTPUT_WIDTH => 44,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 125,
C_MAX_RATE => 125,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 44,
C_C2 => 44,
C_C3 => 44,
C_C4 => 44,
C_C5 => 0,
C_C6 => 0,
C_I1 => 44,
C_I2 => 44,
C_I3 => 44,
C_I4 => 44,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 48,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_1_arch;
| mit | 7cab4ae88a6c1bc5929056b80ad8f731 | 0.651237 | 3.327356 | false | false | false | false |
David-Estevez/spaceinvaders | src/vga.vhd | 1 | 2,675 | ----------------------------------------------------------------------------------
--
-- Lab session #1: vga controller
--
-- Author: David Estévez Fernández
-- David Estévez Fernández
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
RGB : in STD_LOGIC_VECTOR (2 downto 0);
HSync : out STD_LOGIC;
VSync : out STD_LOGIC;
R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (9 downto 0));
end vga;
architecture Behavioral of vga is
begin
process(reset, clk)
-- XCount -> holds the count for the X dimension ( monitor resolution is 640x480 )
variable HCount: integer range 0 to 800:= 0;
variable VCount: integer range 0 to 521 := 0;
variable prescaler: std_logic := '0';
begin
-- When resetting, set all outputs to 0
if reset = '1' then
HSync <= '1';
VSync <= '1';
R <= '0';
G <= '0';
B <= '0';
X <= "0000000000";
Y <= "0000000000";
elsif clk'event and clk = '1' then
-- Prescaler
if prescaler = '1' then
prescaler := '0';
else
prescaler := '1';
end if;
-- Counters:
if prescaler = '0' then
if HCount = 800 then
HCount := 0;
if VCount = 521 then
VCount := 0;
else
VCount := VCount + 1;
end if;
else
HCount := HCount + 1;
end if;
end if;
-- HSync:
if HCount >= 654 and HCount < 752 then
HSync <= '0';
else
HSync <= '1';
end if;
-- VSync:
if VCount >= 490 and VCount < 492 then
VSync <= '0';
else
VSync <= '1';
end if;
-- X / Y position:
if HCount < 640 then
X <= std_logic_vector( to_unsigned( HCount, 10) );
end if;
if VCount < 480 then
Y <= std_logic_vector( to_unsigned( VCount, 10) );
end if;
-- Color:
if VCount < 480 and HCount < 640 then
R <= RGB(2);
G <= RGB(1);
B <= RGB(0);
else
R <= '0';
G <= '0';
B <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 95dc8681f4e49de4f802e3a7d40aabc4 | 0.462374 | 3.689227 | false | false | false | false |
David-Estevez/spaceinvaders | src/toneGenerator.vhd | 1 | 7,326 | ----------------------------------------------------------------------------------
-- TONE GENERATOR
-- Sergio Vilches
-- David Estevez
-- Outputs audio sweep tones
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity toneGenerator is
port (clk : in std_logic;
reset : in std_logic;
p1_posShip : in std_logic;
p2_posShip : in std_logic;
p1_BulletActive : in std_logic;
p2_BulletActive : in std_logic;
inv_Hit1 : in std_logic;
inv_Hit2 : in std_logic;
specialScreen : in std_logic_vector( 2 downto 0);
toneOutput : out std_logic
);
end toneGenerator;
architecture behavioral of toneGenerator is
-- Tone generation
signal count : integer range 0 to 1000000; -- Used for tone generation (20 bits)
signal clkCycles : integer range 0 to 1000000; -- Clock cycles (50 MHz) per period
signal toneEnable : std_logic;
signal toneStart : std_logic;
signal q : std_logic;
-- Sweep Parameters
signal startPeriod : integer range 0 to 20000; -- Period of sound in microseconds (Minimum frequency of 50 Hz = 20,000 microseconds)
signal endPeriod : integer range 0 to 20000; -- Period of sound in microseconds (Minimum frequency of 50 Hz = 20,000 microseconds)
signal step : integer range 0 to 31 := 0; -- For period sweep
signal deltaPeriod : integer range -524288 to 524287; -- Period change in each step
signal tick : std_logic; -- Signal from timer
-- Glue logic signals
signal p1_posShip_detected : std_logic;
signal p2_posShip_detected : std_logic;
signal p1_bulletActive_detected : std_logic;
signal p2_bUlletActive_detected : std_logic;
signal fsm_win : std_logic;
signal fsm_loose : std_logic;
signal fsm_win_detected : std_logic;
signal fsm_loose_detected : std_logic;
-- The following logic decodes which sound is needed for each situation, analyzing signals already present in spaceInv
component edgeDetector is
port(
clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
end component;
component edgeDetectorRiseFall is
port(
clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
end component;
component timer is
generic ( t: integer := 1); -- Period in ms
port (clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
en : in std_logic;
q : out std_logic
);
end component;
begin
stepTimer: timer
generic map (33) -- 33 ms steps
port map (
clk => clk,
reset => reset,
clear => '0',
en => '1',
q => tick
);
p1_posShip_edgeDetector: edgeDetectorRiseFall
port map(
clk => clk,
reset => reset,
enable => '1',
input => p1_posShip,
detected => p1_posShip_detected
);
p2_posShip_edgeDetector: edgeDetectorRiseFall
port map(
clk => clk,
reset => reset,
enable => '1',
input => p2_posShip,
detected => p2_posShip_detected
);
p1_BulletActive_edgeDetector: edgeDetector
port map(
clk => clk,
reset => reset,
enable => '1',
input => p1_BulletActive,
detected => p1_BulletActive_detected
);
p2_BulletActive_edgeDetector: edgeDetector
port map(
clk => clk,
reset => reset,
enable => '1',
input => p2_BulletActive,
detected => p2_BulletActive_detected
);
fsm_win_edgeDetector: edgeDetector
port map(
clk => clk,
reset => reset,
enable => '1',
input => fsm_win,
detected => fsm_win_detected
);
fsm_loose_edgeDetector: edgeDetector
port map(
clk => clk,
reset => reset,
enable => '1',
input => fsm_loose,
detected => fsm_loose_detected
);
-- State decoding
process (specialScreen)
begin
case specialScreen is
when "001" =>
fsm_win <= '1';
fsm_loose <= '0';
when "010" =>
fsm_win <= '0';
fsm_loose <= '1';
when others =>
fsm_win <= '0';
fsm_loose <= '0';
end case;
end process;
-- Sound selection. Selects the boundaries of the frequency sweep
process (reset, clk)
begin
if reset = '1' then
startPeriod <= 1000;
endPeriod <= 1000;
toneStart <= '0';
elsif clk'event and clk = '1' then
if ((p1_posShip_detected or p2_posShip_detected) = '1') then
startPeriod <= 10000;
endPeriod <= 2000;
toneStart <= '1';
elsif ((p1_BulletActive_detected or p2_BulletActive_detected) = '1') then
startPeriod <= 100;
endPeriod <= 1000;
toneStart <= '1';
elsif ((inv_Hit1 or inv_Hit2) = '1') then
startPeriod <= 1000;
endPeriod <= 10000;
toneStart <= '1';
elsif (fsm_win_detected = '1') then
startPeriod <= 10000;
endPeriod <= 100;
toneStart <= '1';
elsif (fsm_loose_detected = '1') then
startPeriod <= 15000;
endPeriod <= 20000;
toneStart <= '1';
else
toneStart <= '0';
end if;
end if;
end process;
-- Tone generation. Just a simple variable square wave generator
process (reset, clk, q)
begin
if reset = '1' then
count <= 0;
q <= '0';
elsif clk'event and clk = '1' then
if count = 0 then
count <= clkCycles/2;
q <= not q;
elsif toneEnable = '1' then
count <= count - 1;
else
q <= '0';
end if;
end if;
toneOutput <= q;
end process;
-- Sweep. Creates a ramp of frequencies
process (reset, clk)
begin
if reset = '1' then
step <= 0;
toneEnable <= '0';
elsif clk'event and clk = '1' then
deltaPeriod <= (endPeriod - startPeriod)/32;
if toneStart = '1' then
step <= 0;
toneEnable <= '1';
elsif (tick = '1' and step < 31) then
step <= step + 1;
elsif (tick = '1' and step = 31) then
toneEnable <= '0';
end if;
clkCycles <= 50 * (startPeriod + deltaPeriod * step); -- The '50' factor converts from microseconds to clock cycles
end if;
end process;
end behavioral;
| gpl-3.0 | 2e586b05440832b08198c0947b0e303b | 0.499181 | 4.176739 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment3-Program_Counter/IPI-BD/Program_Counter/hdl/Program_Counter-BEAUTIFY.vhd | 1 | 6,774 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed Sep 20 12:35:57 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target Program_Counter.bd
--Design : Program_Counter
--Purpose : IP block netlist
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--Implement Program Counter
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Program_Counter_imp is
port ( CLK : in STD_LOGIC;
IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
INC : in STD_LOGIC;
LOAD : in STD_LOGIC;
MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
RESET : in STD_LOGIC;
STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 ) );
end Program_Counter_imp;
architecture STRUCTURE of Program_Counter_imp is
--Instantiate Components
component Program_Counter_Counter10bit_0_0 is
port ( Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 ) );
end component Program_Counter_Counter10bit_0_0;
component Program_Counter_Constant_0_0 is
port ( dout : out STD_LOGIC_VECTOR ( 9 downto 0 ) );
end component Program_Counter_Constant_0_0;
component Program_Counter_Mux4x1_0_0 is
port ( A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 ) );
end component Program_Counter_Mux4x1_0_0;
--Instantiate Signals
signal s_A : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s_B : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s_CLK : STD_LOGIC;
signal Counter10bit_0_COUNT : STD_LOGIC_VECTOR ( 0 to 9 );
signal s_INC : STD_LOGIC;
signal s_LOAD : STD_LOGIC;
signal s_Mux4x1_Output : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s_RESET : STD_LOGIC;
signal s_SEL : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s_xlconstant_Output : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
s_A(9 downto 0) <= IMMED(9 downto 0);
s_B(9 downto 0) <= STACK(9 downto 0);
s_CLK <= CLK;
COUNT(0 to 9) <= Counter10bit_0_COUNT(0 to 9);
s_INC <= INC;
s_LOAD <= LOAD;
s_RESET <= RESET;
s_SEL(1 downto 0) <= MUX_SEL(1 downto 0);
Constant_0: component Program_Counter_Constant_0_0
port map ( dout(9 downto 0) => s_xlconstant_Output(9 downto 0) );
Counter10bit_0: component Program_Counter_Counter10bit_0_0
port map ( CLK => s_CLK,
COUNT(0 to 9) => Counter10bit_0_COUNT(0 to 9),
Din(0) => s_Mux4x1_Output(9),
Din(1) => s_Mux4x1_Output(8),
Din(2) => s_Mux4x1_Output(7),
Din(3) => s_Mux4x1_Output(6),
Din(4) => s_Mux4x1_Output(5),
Din(5) => s_Mux4x1_Output(4),
Din(6) => s_Mux4x1_Output(3),
Din(7) => s_Mux4x1_Output(2),
Din(8) => s_Mux4x1_Output(1),
Din(9) => s_Mux4x1_Output(0),
INC => s_INC,
LOAD => s_LOAD,
RESET => s_RESET );
Mux4x1_0: component Program_Counter_Mux4x1_0_0
port map ( A(9 downto 0) => s_A(9 downto 0),
B(9 downto 0) => s_B(9 downto 0),
C(9 downto 0) => s_xlconstant_Output(9 downto 0),
D(9 downto 0) => B"0000000000",
SEL(1 downto 0) => s_SEL(1 downto 0),
X(9 downto 0) => s_Mux4x1_Output(9 downto 0) );
end STRUCTURE;
----------------------------------------------------------------------------------
--Program Counter Block Wrapper
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Program_Counter is
port ( CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
PC_INC : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
RST : in STD_LOGIC );
--Vivado Block Diagram Auto-Generated Attributes
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of Program_Counter : entity is "Program_Counter,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Program_Counter,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=3,numNonXlnxBlks=0,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of Program_Counter : entity is "Program_Counter.hwdef";
end Program_Counter;
architecture STRUCTURE of Program_Counter is
signal s_CLK : STD_LOGIC;
signal s_FROM_IMMED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s_FROM_STACK : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s_PC_INC : STD_LOGIC;
signal s_PC_LD : STD_LOGIC;
signal s_PC_MUX_SEL : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Program_Counter_COUNT : STD_LOGIC_VECTOR ( 0 to 9 );
signal s_RST : STD_LOGIC;
begin
s_CLK <= CLK;
s_FROM_IMMED(9 downto 0) <= FROM_IMMED(9 downto 0);
s_FROM_STACK(9 downto 0) <= FROM_STACK(9 downto 0);
PC_COUNT(0 to 9) <= Program_Counter_COUNT(0 to 9);
s_PC_INC <= PC_INC;
s_PC_LD <= PC_LD;
s_PC_MUX_SEL(1 downto 0) <= PC_MUX_SEL(1 downto 0);
s_RST <= RST;
Program_Counter: entity work.Program_Counter_imp
port map ( CLK => s_CLK,
COUNT(0 to 9) => Program_Counter_COUNT(0 to 9),
IMMED(9 downto 0) => s_FROM_IMMED(9 downto 0),
INC => s_PC_INC,
LOAD => s_PC_LD,
MUX_SEL(1 downto 0) => s_PC_MUX_SEL(1 downto 0),
RESET => s_RST,
STACK(9 downto 0) => s_FROM_STACK(9 downto 0) );
end STRUCTURE;
| mit | 11684dac6c1e32df7b8ab9943c5e646c | 0.536906 | 3.517134 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/hdl/RAT_wrapper.vhd | 1 | 1,534 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Fri Oct 27 14:48:24 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target RAT_wrapper.bd
--Design : RAT_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_wrapper is
port (
CLK : in STD_LOGIC;
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
end RAT_wrapper;
architecture STRUCTURE of RAT_wrapper is
component RAT is
port (
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component RAT;
begin
RAT_i: component RAT
port map (
CLK => CLK,
INT_IN(0) => INT_IN(0),
IN_PORT(7 downto 0) => IN_PORT(7 downto 0),
OUT_PORT(7 downto 0) => OUT_PORT(7 downto 0),
PORT_ID(7 downto 0) => PORT_ID(7 downto 0),
RST => RST
);
end STRUCTURE;
| mit | 9af2390f87f2f33346fa9a5a270f02e3 | 0.556714 | 3.567442 | false | false | false | false |
99yen/vhdl-snake | lfsr15.vhd | 1 | 547 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LFSR15 is
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(14 downto 0)
);
end LFSR15;
architecture RTL of LFSR15 is
signal FEEDBACK : std_logic;
signal SR : std_logic_vector(14 downto 0);
begin
RAND <= SR;
FEEDBACK <= SR(14) xor SR(13);
process (CLK, RST) begin
if (RST = '0') then
SR <= "000000000000001";
elsif(CLK'event and CLK = '1') then
SR <= SR(13 downto 0) & FEEDBACK;
end if;
end process;
end RTL;
| gpl-2.0 | 089e29f0bc89b3a4e99b57b6c4a64a99 | 0.659963 | 2.707921 | false | false | false | false |
S0obi/SY23 | counter/counter_test.vhdl | 1 | 2,464 | LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity counter_test is
end counter_test;
architecture behavior of counter_test is
-- Component Declaration for the Unit Under Test (UUT)
component counter
GENERIC (
Nbits: integer := 4;
Nmax: integer := 9
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
Q : OUT std_logic_vector(Nbits-1 downto 0)
);
end component;
signal tb_clk, tb_reset: STD_LOGIC;
signal tb_Q : STD_LOGIC_VECTOR(3 downto 0);
signal clk_te : STD_LOGIC;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant clk_te_period : time := 20 ns;
constant dT : real := 2.0; --ns
constant separator: String(1 to 1) := ";"; -- CSV separator
begin
-- Instantiate the Unit Under Test (UUT)
uut: counter PORT MAP (
clk => tb_clk,
reset => tb_reset,
Q => tb_Q
);
-- Clock process definitions
clk_process: process
begin
tb_clk <= '0';
wait for clk_period/2;
tb_clk <= '1';
wait for clk_period/2;
end process clk_process;
-- Clock process definitions
clk_te_process: process
begin
clk_te <= '0';
wait for clk_te_period/2;
clk_te <= '1';
wait for clk_te_period/2;
end process clk_te_process;
-- Stimulus process
stim_proc: process
begin
--wait for 100ms;
tb_reset <= '1';
wait for clk_period*10;
tb_reset <= '0';
-- insert stimulus here
wait;
end process stim_proc;
result: process(clk_te)
file filedatas: text open WRITE_MODE is "counter.csv";
variable s : line;
variable temps : real := 0.0;
variable sdata, sbardata : integer := 0;
variable olddata : std_logic_vector(3 downto 0) := x"0";
begin
--if rising_edge(clk_te) then
write(s, temps); write(s, separator);
write(s, clk_te); write(s, separator);
write(s, tb_reset); write(s, separator);
if olddata /= tb_Q then
sdata := 1 - sdata;
else
sdata := sdata;
end if;
sbardata := 1 - sdata;
write(s, sdata); write(s, separator);
write(s, sbardata); write(s, separator);
writeline(filedatas,s);
temps := temps + dT;
olddata := tb_Q;
--end if;
end process result;
end architecture behavior;
| gpl-2.0 | 50916185eb966d911b23ec4db6b554cb | 0.592938 | 3.45098 | false | false | false | false |
hubmartin/FPGA-LVDS-LCD-Hack | lvds_test.vhd | 1 | 11,479 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- modulo
use IEEE.NUMERIC_STD.ALL;
--use work.fontRom.all;
entity sync_test is
Port ( clkExtOsc : in STD_LOGIC;
ledOut : out STD_LOGIC_VECTOR(7 downto 0);
sw : in STD_LOGIC_VECTOR (2 downto 0);
-- ODD columns
CK1IN : out STD_LOGIC;
RXIN2 : out STD_LOGIC;
RXIN1 : out STD_LOGIC;
RXIN0 : out STD_LOGIC;
-- Even columns
ECK1IN : out STD_LOGIC;
ERXIN2 : out STD_LOGIC;
ERXIN1 : out STD_LOGIC;
ERXIN0 : out STD_LOGIC;
-- Logic analyzer debug outputs
LCK1IN : out STD_LOGIC;
LRXIN2 : out STD_LOGIC;
LRXIN1 : out STD_LOGIC;
LRXIN0 : out STD_LOGIC;
LTRIG : out STD_LOGIC;
LTRIG2 : out STD_LOGIC;
clkOut : out STD_LOGIC );
end sync_test;
architecture Behavioral of sync_test is
SIGNAL clk : STD_LOGIC;
signal led : STD_LOGIC_VECTOR (7 downto 0);
signal CLK_DIV : std_logic_vector (8 downto 0);
-- colors
signal red : std_logic_vector(5 downto 0) := "000000";
signal green : std_logic_vector(5 downto 0) := "000000";
signal blue : std_logic_vector(5 downto 0) := "000000";
signal nextColor : std_logic_vector(17 downto 0) := "000000000000000000";
-- which slot are we in right now?
signal slot : integer range 0 to 6;
-- control signals
signal hsync : std_logic := '0';
signal vsync : std_logic := '0';
signal dataenable : std_logic := '0';
-- display parameters
constant htotal : integer := 980; -- screen size, with back porch ;1920+40 / 2
constant hfront : integer := 12; -- front porch 24 / 2
constant hactive : integer := 960; -- display size 1920/2
signal hcurrent : integer range 0 to htotal := 0;
constant vtotal : integer := 1226; -- screen size, with back porch 1200+26
constant vfront : integer := 3; -- front porch 3
constant vactive : integer := 1200; -- display size
signal vcurrent : integer range 0 to vtotal := 0;
-- the signals holding the data to be sent to the lcd on each slot.
-- this is hardwired on the RGB, hsync and vsync signals.
signal RX0DATA : std_logic_vector(0 to 6) := "0000000";
signal RX1DATA : std_logic_vector(0 to 6) := "0000000";
signal RX2DATA : std_logic_vector(0 to 6) := "0000000";
constant CK1DATA : std_logic_vector(0 to 6) := "1100011"; -- this is per spec, the clock
-- is always the same
-- Moving green bar
signal gbarpos : integer range 0 to vtotal := 0;
--signal color_cur : integer range 0 to 2 := 0;
subtype subCharacterItem is integer range 0 to 1200;
type typeCharArray is array (integer range 0 to 3) of subCharacterItem;
--CONSTANT characterArray: typeCharArray := (
shared variable segmentOffsetX: typeCharArray := (20, 230, 500, 710);
-- 7 segment decoder array
--subtype subSevenSegType is std_logic_vector(6 downto 0);
--type typeSevenSeg is array (integer range 0 to 9) of subSevenSegType;
--shared variable sevenSegment: typeSevenSeg := ("0000001","1001111","0010010","0000110","1001100","0100100","0100000","0001111","0000000","0000100");
-- Color output from every segment
subtype subColorOutType is std_logic_vector(17 downto 0);
type typeColorOut is array (integer range 0 to 3) of subColorOutType;
shared variable colorOut: typeColorOut;
-- array of 4 number on display
subtype subDisplayNumberType is integer range 0 to 9;
type typeDisplayNumber is array (integer range 0 to 3) of subDisplayNumberType;
shared variable displayNumber: typeDisplayNumber := (0,8,3,0);
-- divider 200MHz to 1 second
signal clockMinute: STD_LOGIC;
signal clockSecond: STD_LOGIC;
signal counterMinute : integer range 0 to 8000000*61 := 0;
signal counterSecond : integer range 0 to 8000000+1 := 0;
-- parameterized module component declaration
component ROM
port (Address: in std_logic_vector(3 downto 0);
OutClock: in std_logic; OutClockEn: in std_logic;
Reset: in std_logic; Q: out std_logic_vector(7 downto 0));
end component;
component pll
port (CLKI: in std_logic; CLKOP: out std_logic);
end component;
COMPONENT debounce
PORT( clk : IN std_logic; button : IN std_logic; result : OUT std_logic );
END COMPONENT;
COMPONENT digit7seg
PORT( hcurrent : IN integer; vcurrent : IN integer; offsetX : IN integer; offsetY : IN integer; dispNumber : IN integer; display : OUT std_logic ; colorIn : in std_logic_vector(17 downto 0); colorOut : out std_logic_vector(17 downto 0));
END COMPONENT;
-- Clock multiplexer
component DCMA
port( CLK0 : in std_logic;
CLK1 : in std_logic;
SEL : in std_logic;
DCMOUT : out std_logic);
end component;
--internal oscillator
COMPONENT OSCH
GENERIC(
NOM_FREQ: string := "2.08");
PORT(
STDBY : IN STD_LOGIC;
OSC : OUT STD_LOGIC;
SEDSTDBY : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clkRC : STD_LOGIC;
SIGNAL clkPLL : STD_LOGIC;
signal swDebounced : STD_LOGIC_VECTOR (2 downto 0);
signal romAddr : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal romOut : STD_LOGIC_VECTOR (7 downto 0);
signal tempRomAddr : STD_LOGIC_VECTOR (9 downto 0);
signal tempGbarPos : STD_LOGIC_VECTOR (9 downto 0);
signal tempFlag : STD_LOGIC_VECTOR (9 downto 0);
signal digitDisplay : std_logic_vector(3 downto 0);
begin
MyROM : ROM
port map (Address(3 downto 0)=> romAddr, OutClock=>clkPLL, OutClockEn=>'1',
Reset=> '0', Q(7 downto 0)=> romOut);
-- Clock multiplexer
--I1: DCMA
--port map (CLK0 => clkRC, CLK1 => clkPLL, SEL => '1', DCMOUT => clk);
--internal oscillator
OSCInst0: OSCH
GENERIC MAP (NOM_FREQ => "2.08")
PORT MAP (STDBY => '0', OSC => clkRC, SEDSTDBY => OPEN);
myPll : pll port map (CLKI=>clkExtOsc, CLKOP=> clkPLL);
clk <= clkPLL;
Inst_debounce: debounce PORT MAP( clk => clkExtOsc, button => sw(0), result => swDebounced(0) );
Inst_debounc2: debounce PORT MAP( clk => clkExtOsc, button => sw(1), result => swDebounced(1) );
digit0: digit7seg PORT MAP(vcurrent => vcurrent, hcurrent => hcurrent, offsetX => 20 , offsetY => 50, dispNumber => displayNumber(0), display => digitDisplay(0), colorIn => "100000111111000000", colorOut => colorOut(0));
digit1: digit7seg PORT MAP(vcurrent => vcurrent, hcurrent => hcurrent, offsetX => 230, offsetY => 50, dispNumber => displayNumber(1), display => digitDisplay(1), colorIn => "000000111111100000", colorOut => colorOut(1));
digit2: digit7seg PORT MAP(vcurrent => vcurrent, hcurrent => hcurrent, offsetX => 500, offsetY => 50, dispNumber => displayNumber(2), display => digitDisplay(2), colorIn => "100000111111100000", colorOut => colorOut(2));
digit3: digit7seg PORT MAP(vcurrent => vcurrent, hcurrent => hcurrent, offsetX => 710, offsetY => 50, dispNumber => displayNumber(3), display => digitDisplay(3), colorIn => "000000111111000000", colorOut => colorOut(3));
--led(2 downto 0) <= sw(2 downto 0);
--led(3) <= swDebounced(0);
--led(4) <= swDebounced(2);
ledOut <= not led;
--clkOut <= CLK_DIV(8);
--led(5) <= CLK_DIV(8);
--led <= std_logic_vector( to_unsigned(gbarpos, 8) );
-- data enable: should be high when the data is valid for display
dataenable <= vsync and hsync;
-- RX2DATA is (DE, vsync, hsync, blue[5:2])
RX2DATA(0) <= dataenable;
RX2DATA(1) <= vsync;
RX2DATA(2) <= hsync;
RX2DATA(3 to 6) <= blue(5 downto 2);-- when dataenable else "0000";
-- RX1DATA is (blue[1:0], green[5:1])
RX1DATA(0 to 1) <= blue(1 downto 0);-- when dataenable else "00";
RX1DATA(2 to 6) <= green(5 downto 1);-- when dataenable else "00000";
-- RX1DATA is (green[0], red[5:0])
RX0DATA(0) <= green(0);-- when dataenable else '0';
RX0DATA(1 to 6) <= red(5 downto 0);-- when dataenable else "000000";
-- RX2DATA synchro data
-- connect signals with the appropriate slot
RXIN0 <= RX0DATA(slot);
RXIN1 <= RX1DATA(slot);
RXIN2 <= RX2DATA(slot);
CK1IN <= CK1DATA(slot);
-- dual channel output
ERXIN0 <= RXIN0;
ERXIN1 <= RXIN1;
ERXIN2 <= RXIN2;
ECK1IN <= CK1IN;
-- debug logic analyzer
LCK1IN <= CK1IN;
LRXIN2 <= RXIN2;
LRXIN1 <= RXIN1;
LRXIN0 <= RXIN0;
LTRIG <= vsync;
LTRIG2 <= hsync;
led(0) <= clockSecond;
led(1) <= clockMinute;
process (slot) is
variable offsetX : integer range 0 to 1200;
variable digitValue : std_logic_vector(6 downto 0);
variable actColor : std_logic_vector(17 downto 0);
begin
if (slot = 5) then
nextColor <= "000000000000000000";
if vcurrent = gbarpos then
nextColor <= "000000111111000000";
end if;
actColor := "000000111111000000";
--nextColor <= colorOut(0) OR colorOut(1) OR colorOut(2) OR colorOut(3);
if( not (digitDisplay = "0000") ) then
nextColor <= actColor;
--nextColor <= colorOut(0) OR colorOut(1) OR colorOut(2) OR colorOut(3);
end if;
end if;
end process;
process (clkExtOsc, sw(0)) is
begin
if( sw(0) = '1' ) then
counterMinute <= 0;
counterSecond <= 0;
clockSecond <= '0';
clockMinute <= '0';
else
if rising_edge(clkExtOsc) then
if (counterMinute = 8000000*60) then
clockMinute <= NOT(clockMinute);
counterMinute <= 0;
else
counterMinute <= counterMinute + 1;
end if;
if (counterSecond = 8000000) then
clockSecond <= NOT(clockSecond);
counterSecond <= 0;
else
counterSecond <= counterSecond + 1;
end if;
end if;
end if;
end process;
process (clockMinute, sw(0)) is
begin
if( sw(0) = '1' ) then
displayNumber(0) := 0;
displayNumber(1) := 8;
displayNumber(2) := 3;
displayNumber(3) := 0;
else
if rising_edge(clockMinute) then
if( displayNumber(3) = 0 ) then -- minuty
if( displayNumber(2) = 0 ) then -- desitky minut
if( displayNumber(1) = 0 ) then -- hodiny
else
displayNumber(1) := displayNumber(1) - 1; --dec hodiny
displayNumber(2) := 5; --desitky minut
displayNumber(3) := 9; --minuty
end if;
else
-- sub minuty
displayNumber(3) := 9;
displayNumber(2) := displayNumber(2) - 1;
end if;
else
-- sub minuty
displayNumber(3) := displayNumber(3) - 1;
end if;
end if;
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
if hcurrent < hfront or (hcurrent >= (hfront+hactive)) then
hsync <= '0';
else
hsync <= '1';
end if;
if vcurrent < vfront or (vcurrent >= (vfront+vactive)) then
vsync <= '0';
else
vsync <= '1';
end if;
if slot = 6 then
-- this is the last slot, wrap around
slot <= 0;
green <= nextColor(17 downto 12);
red <= nextColor(11 downto 6);
blue <= nextColor(5 downto 0);
-- if this is the last pixel in the line, wrap around
if hcurrent = htotal then
hcurrent <= 0;
-- if this is the last line in the screen, wrap around.
if vcurrent = vtotal then
vcurrent <= 0;
if swDebounced(0) = '1' then
gbarpos <= gbarpos + 1;
end if;
if swDebounced(1) = '1' then
gbarpos <= gbarpos - 1;
end if;
else
vcurrent <= vcurrent + 1;
end if;
else
hcurrent <= hcurrent + 1;
end if;
else
slot <= slot + 1;
end if;
end if;
end process;
end Behavioral; | mit | 5b1bc9f14e240144acb613e268e65d99 | 0.632895 | 3.237169 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/ethernet/ethernet_add_header.vhd | 1 | 5,185 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: ethernet_add_header - Behavioral
--
-- Description: Add the Ethernet header to a data frame
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ethernet_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_type : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ether_dst_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end ethernet_add_header;
architecture Behavioral of ethernet_add_header is
type a_data_delay is array(0 to 14) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
-------------------------------------------------------
-- Note: Set the initial state to pass the data through
-------------------------------------------------------
signal count : unsigned(3 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
case count is
when "0000" => data_out <= ether_dst_mac( 7 downto 0); data_valid_out <= '1';
when "0001" => data_out <= ether_dst_mac(15 downto 8); data_valid_out <= '1';
when "0010" => data_out <= ether_dst_mac(23 downto 16); data_valid_out <= '1';
when "0011" => data_out <= ether_dst_mac(31 downto 24); data_valid_out <= '1';
when "0100" => data_out <= ether_dst_mac(39 downto 32); data_valid_out <= '1';
when "0101" => data_out <= ether_dst_mac(47 downto 40); data_valid_out <= '1';
when "0110" => data_out <= ether_src_mac( 7 downto 0); data_valid_out <= '1';
when "0111" => data_out <= ether_src_mac(15 downto 8); data_valid_out <= '1';
when "1000" => data_out <= ether_src_mac(23 downto 16); data_valid_out <= '1';
when "1001" => data_out <= ether_src_mac(31 downto 24); data_valid_out <= '1';
when "1010" => data_out <= ether_src_mac(39 downto 32); data_valid_out <= '1';
when "1011" => data_out <= ether_src_mac(47 downto 40); data_valid_out <= '1';
when "1100" => data_out <= ether_type(15 downto 8); data_valid_out <= '1';
when "1101" => data_out <= ether_type( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "1111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "1111" then
count <= count + 1;
end if;
end if;
data_valid_in_last <= data_valid_in;
end if;
end process;
end Behavioral;
| mit | b1de99bf6867a58a686070d96644343c | 0.525362 | 4.013158 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/ddr3/testbench/top_tb.vhdl | 1 | 5,334 | --
-- Xilinx ml605 DDR3 Testbench
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Behavioral of Top_tb is
constant nCS_PER_RANK : integer := 1;
constant BANK_WIDTH : integer := 3;
constant CK_WIDTH : integer := 1;
constant CKE_WIDTH : integer := 1;
constant CS_WIDTH : integer := 1;
constant DM_WIDTH : integer := 8;
constant DQ_WIDTH : integer := 64;
constant DQS_WIDTH : integer := 8;
constant ROW_WIDTH : integer := 13;
constant MEMORY_WIDTH : integer := 16;
constant NUM_COMP : integer := DQ_WIDTH/MEMORY_WIDTH;
signal sys_clk : std_logic;
signal sys_rst : std_logic;
signal clk_ref : std_logic;
signal stop : boolean;
signal sys_clk_p, sys_clk_n : std_logic;
signal clk_ref_p, clk_ref_n : std_logic;
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_reset_n : std_logic;
component ddr3_model
port(
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
ba : in std_logic_vector(BANK_WIDTH-1 downto 0);
addr : in std_logic_vector(ROW_WIDTH-1 downto 0);
dq : inout std_logic_vector(MEMORY_WIDTH-1 downto 0);
dqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
dqs_n : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
tdqs_n : out std_logic_vector((MEMORY_WIDTH/16) downto 0);
odt : in std_logic
);
end component ddr3_model;
begin
do_clk_ref: Clock
generic map(PERIOD => 5 ns)
port map(clk_o => clk_ref, rst_o => sys_rst, stop_i => stop);
do_sys_clk: Clock
generic map(PERIOD => 5 ns)
port map(clk_o => sys_clk, rst_o => open, stop_i => stop);
sys_clk_p <= sys_clk;
sys_clk_n <= not sys_clk;
clk_ref_p <= clk_ref;
clk_ref_n <= not clk_ref;
-- Memory model instantiation as in the generated coregen example
mem_rank : for r in 0 to CS_WIDTH-1 generate
gen_mem : for i in 0 to NUM_COMP-1 generate
ddr3_inst : ddr3_model
port map(
rst_n => ddr3_reset_n,
ck => ddr3_ck_p((i*MEMORY_WIDTH)/72),
ck_n => ddr3_ck_n((i*MEMORY_WIDTH)/72),
cke => ddr3_cke(((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)),
cs_n => ddr3_cs_n(((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm((2*(i+1)-1) downto (2*i)),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq(16*(i+1)-1 downto 16*(i)),
dqs => ddr3_dqs_p((2*(i+1)-1) downto (2*i)),
dqs_n => ddr3_dqs_n((2*(i+1)-1) downto (2*i)),
tdqs_n => open,
odt => ddr3_odt(((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r))
);
end generate gen_mem;
end generate mem_rank;
dut_inst : entity work.top
generic map(
SIM_BYPASS_INIT_CAL=> "SKIP"
)
port map(
sys_clk_p_i => sys_clk_p,
sys_clk_n_i => sys_clk_n,
clk_ref_p_i => clk_ref_p,
clk_ref_n_i => clk_ref_n,
sys_rst_i => sys_rst,
ddr3_ck_p_o => ddr3_ck_p,
ddr3_ck_n_o => ddr3_ck_n,
ddr3_addr_o => ddr3_addr,
ddr3_ba_o => ddr3_ba,
ddr3_ras_n_o => ddr3_ras_n,
ddr3_cas_n_o => ddr3_cas_n,
ddr3_we_n_o => ddr3_we_n,
ddr3_cs_n_o => ddr3_cs_n,
ddr3_cke_o => ddr3_cke,
ddr3_odt_o => ddr3_odt,
ddr3_reset_n_o => ddr3_reset_n,
ddr3_dm_o => ddr3_dm,
ddr3_dq_io => ddr3_dq,
ddr3_dqs_p_io => ddr3_dqs_p,
ddr3_dqs_n_io => ddr3_dqs_n
);
end architecture Behavioral;
| bsd-3-clause | ebd75c7b1904420a7f9018b961ffe9b4 | 0.514998 | 3.053234 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/testbench/top_testoutput_tb.vhd | 1 | 7,611 | ---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2009-06-08
-- File : Top_testoutput_tb.vhd
--
-- Abstract :
-- insert a description here
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
--
-- Defines communication functions between imx and fpga:
--
-- write procedures
-- procedure imx_write
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
-- read procedures
-- procedure imx_read
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
use work.apf27_test_pkg.all;
entity top_testoutput_tb is
end entity top_testoutput_tb;
architecture RTL of top_testoutput_tb is
CONSTANT HALF_PERIODE : time := 3.75939849624 ns; -- Half clock period
CONSTANT OUTPUT_CTRL_DATA : std_logic_vector := x"0000";
CONSTANT OUTPUT_ID : std_logic_vector := x"0002";
CONSTANT WSC : natural := 4;
signal imx27_wb16_wrapper00_imx_cs_n : std_logic;
signal imx27_wb16_wrapper00_imx_data : std_logic_vector(15 downto 0);
signal rstgen_syscon00_ext_clk : std_logic;
signal imx27_wb16_wrapper00_imx_eb3_n : std_logic;
signal imx27_wb16_wrapper00_imx_oe_n : std_logic;
signal imx27_wb16_wrapper00_imx_address : std_logic_vector(11 downto 0);
signal output_ser : std_logic;
signal output_qh : std_logic;
signal output_reset_n : std_logic;
signal output_rclk : std_logic;
signal output_srclk : std_logic;
component top_testoutput
port (
imx27_wb16_wrapper00_imx_cs_n : in std_logic;
imx27_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
rstgen_syscon00_ext_clk : in std_logic;
imx27_wb16_wrapper00_imx_eb3_n : in std_logic;
imx27_wb16_wrapper00_imx_oe_n : in std_logic;
imx27_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
output_ser : out std_logic;
output_qh : in std_logic;
output_reset_n : out std_logic;
output_rclk : out std_logic;
output_srclk : out std_logic
);
end component top_testoutput;
component deserializer
port (
rclr_n : in std_logic ;
rclk : in std_logic ;
srclr_n : in std_logic ;
srclk : in std_logic ;
ser : in std_logic ;
q : out std_logic_vector(7 downto 0);
qh : out std_logic
);
end component deserializer;
signal value : std_logic_vector( 15 downto 0) ;
signal output: std_logic_vector(7 downto 0);
begin
top : top_testoutput
port map(
imx27_wb16_wrapper00_imx_cs_n => imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_data => imx27_wb16_wrapper00_imx_data,
rstgen_syscon00_ext_clk => rstgen_syscon00_ext_clk,
imx27_wb16_wrapper00_imx_eb3_n => imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_oe_n => imx27_wb16_wrapper00_imx_oe_n,
imx27_wb16_wrapper00_imx_address => imx27_wb16_wrapper00_imx_address,
output_ser => output_ser,
output_qh => output_qh,
output_reset_n => output_reset_n,
output_rclk => output_rclk,
output_srclk => output_srclk
);
deserializer_p : deserializer
port map (
rclr_n => output_reset_n,
rclk => output_rclk,
srclr_n => output_reset_n,
srclk => output_srclk,
ser => output_ser,
q => output,
qh => output_qh
);
stimulis : process
begin
imx27_wb16_wrapper00_imx_cs_n <= '1';
imx27_wb16_wrapper00_imx_eb3_n <= '1';
imx27_wb16_wrapper00_imx_oe_n <= '1';
imx27_wb16_wrapper00_imx_address <= (others => '0');
imx27_wb16_wrapper00_imx_data <= (others => 'Z');
output_qh <= '0';
wait for 1 us;
-- read data
imx_read(OUTPUT_CTRL_DATA,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
report "data read :"&integer'image(to_integer(unsigned(value)))
severity note;
-- read id
imx_read(OUTPUT_ID,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
report "ID read :"&integer'image(to_integer(unsigned(value)))
severity note;
value <= x"00ca";
wait for 1 fs;
imx_write(OUTPUT_CTRL_DATA,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
wait for 20 us;
assert value(7 downto 0) = output
report "Wrong value on output :"&integer'image(to_integer(unsigned(output)))&" instead of "&integer'image(to_integer(unsigned(value(7 downto 0))))
severity warning;
value <= x"00AC";
wait for 1 fs;
imx_write(OUTPUT_CTRL_DATA,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
imx_write(OUTPUT_CTRL_DATA,x"00ff",
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
wait for 20 us;
assert value(7 downto 0) = output
report "Wrong value on output :"&integer'image(to_integer(unsigned(output)))&" instead of "&integer'image(to_integer(unsigned(value(7 downto 0))))
severity warning;
assert false report "End of test" severity error;
end process stimulis;
clockp : process
begin
rstgen_syscon00_ext_clk <= '1';
wait for HALF_PERIODE;
rstgen_syscon00_ext_clk <= '0';
wait for HALF_PERIODE;
end process clockp;
end architecture RTL;
| lgpl-2.1 | abc861fef75c64625b94c9ee95d48db7 | 0.551307 | 3.436117 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_tcp_engine_add_data.vhd | 1 | 7,335 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20.06.2016 06:22:11
-- Design Name:
-- Module Name: tb_tcp_engine_add_data - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_tcp_engine_add_data is
end tb_tcp_engine_add_data;
architecture Behavioral of tb_tcp_engine_add_data is
component tcp_engine_add_data is
Port ( clk : in STD_LOGIC;
read_en : out std_logic := '0';
empty : in std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
out_hdr_valid : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_valid : out std_logic := '0';
out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal clk : STD_LOGIC;
signal read_en : std_logic := '0';
signal empty : std_logic := '1';
signal count : integer := 0;
signal in_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal in_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal in_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal in_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal in_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal in_window : std_logic_vector(15 downto 0) := (others => '0');
signal in_flag_urg : std_logic := '0';
signal in_flag_ack : std_logic := '0';
signal in_flag_psh : std_logic := '0';
signal in_flag_rst : std_logic := '0';
signal in_flag_syn : std_logic := '0';
signal in_flag_fin : std_logic := '0';
signal in_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal in_data_addr : std_logic_vector(15 downto 0) := (others => '0');
signal in_data_len : std_logic_vector(10 downto 0) := (others => '0');
signal out_hdr_valid : std_logic := '0';
signal out_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal out_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal out_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal out_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal out_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal out_window : std_logic_vector(15 downto 0) := (others => '0');
signal out_flag_urg : std_logic := '0';
signal out_flag_ack : std_logic := '0';
signal out_flag_psh : std_logic := '0';
signal out_flag_rst : std_logic := '0';
signal out_flag_syn : std_logic := '0';
signal out_flag_fin : std_logic := '0';
signal out_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal out_data_valid : std_logic := '0';
signal out_data : std_logic_vector(7 downto 0) := (others => '0');
begin
process
begin
wait for 5 ns;
clk <= '1';
wait for 5 ns;
clk <= '0';
end process;
clk_proc: process(clk)
begin
if rising_edge(clk) then
if count = 49 then
empty <= '0';
count <= 0;
else
count <= count + 1;
end if;
if read_en = '1' and empty = '0' then
in_src_port <= std_logic_vector(unsigned(in_src_port)+1);
in_dst_port <= std_logic_vector(unsigned(in_dst_port)+1);
in_data_len <= "00000010000";
empty <= '1';
end if;
end if;
end process;
uut: tcp_engine_add_data port map (
clk => clk,
read_en => read_en,
empty => empty,
in_src_port => in_dst_port,
in_dst_ip => in_dst_ip,
in_dst_port => in_dst_port,
in_seq_num => in_seq_num,
in_ack_num => in_ack_num,
in_window => in_window,
in_flag_urg => in_flag_urg,
in_flag_ack => in_flag_ack,
in_flag_psh => in_flag_psh,
in_flag_rst => in_flag_rst,
in_flag_syn => in_flag_syn,
in_flag_fin => in_flag_fin,
in_urgent_ptr => in_urgent_ptr,
in_data_addr => in_data_addr,
in_data_len => in_data_len,
out_hdr_valid => out_hdr_valid,
out_src_port => out_src_port,
out_dst_ip => out_dst_ip,
out_dst_port => out_dst_port,
out_seq_num => out_seq_num,
out_ack_num => out_ack_num,
out_window => out_window,
out_flag_urg => out_flag_urg,
out_flag_ack => out_flag_ack,
out_flag_psh => out_flag_psh,
out_flag_rst => out_flag_rst,
out_flag_syn => out_flag_syn,
out_flag_fin => out_flag_fin,
out_urgent_ptr => out_urgent_ptr,
out_data => out_data,
out_data_valid => out_data_valid);
end Behavioral;
| mit | be038d5642c95bbc73aebacafd430790 | 0.484935 | 3.268717 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_add_udp_header.vhd | 1 | 7,834 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: udp_add_udp_header - Behavioral
--
-- Description: Add the UDP header to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_add_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
udp_src_port : in std_logic_vector(15 downto 0);
udp_dst_port : in std_logic_vector(15 downto 0);
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end udp_add_udp_header;
architecture Behavioral of udp_add_udp_header is
type a_data_delay is array(0 to 8) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
----------------------------------------------------------------
-- Note: Set the initial state to pass the data striaght through
----------------------------------------------------------------
signal count : unsigned(3 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
signal udp_length : std_logic_vector(15 downto 0);
signal udp_checksum_u1a : unsigned(19 downto 0);
signal udp_checksum_u1b : unsigned(19 downto 0);
signal udp_checksum_u2 : unsigned(16 downto 0);
signal udp_checksum_u3 : unsigned(15 downto 0);
signal udp_checksum : std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- UDP checksum is calculated based on a pseudo header that includes
-- the source and destination IP addresses
--------------------------------------------------------------------
signal pseudohdr_0 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_2 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_3 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_4 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_5 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_6 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_7 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_8 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_9 : std_logic_vector(15 downto 0) := (others => '0');
begin
udp_length <= std_logic_vector(unsigned(data_length)+8);
pseudohdr_0 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
pseudohdr_1 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
pseudohdr_2 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
pseudohdr_3 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
pseudohdr_4 <= x"0011"; -- UDP Protocol
pseudohdr_5 <= udp_length;
pseudohdr_6 <= udp_src_port;
pseudohdr_7 <= udp_dst_port;
pseudohdr_8 <= udp_length;
pseudohdr_9 <= udp_checksum;
process(clk)
begin
if rising_edge(clk) then
case count is
when "0000" => data_out <= udp_src_port(15 downto 8); data_valid_out <= '1';
when "0001" => data_out <= udp_src_port( 7 downto 0); data_valid_out <= '1';
when "0010" => data_out <= udp_dst_port(15 downto 8); data_valid_out <= '1';
when "0011" => data_out <= udp_dst_port( 7 downto 0); data_valid_out <= '1';
when "0100" => data_out <= udp_length(15 downto 8); data_valid_out <= '1';
when "0101" => data_out <= udp_length( 7 downto 0); data_valid_out <= '1';
when "0110" => data_out <= udp_checksum(15 downto 8); data_valid_out <= '1';
when "0111" => data_out <= udp_checksum( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "1111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "1111" then
count <= count + 1;
end if;
end if;
data_valid_in_last <= data_valid_in;
-- Pipelined checksum calculation
udp_checksum_u1a <= to_unsigned(0,20) + unsigned(pseudohdr_0) + unsigned(pseudohdr_1)
+ unsigned(pseudohdr_2) + unsigned(pseudohdr_3)
+ unsigned(pseudohdr_4);
udp_checksum_u1b <= to_unsigned(0,20) + unsigned(pseudohdr_5)
+ unsigned(pseudohdr_6) + unsigned(pseudohdr_7)
+ unsigned(pseudohdr_8) + unsigned(data_checksum);
udp_checksum_u2 <= to_unsigned(0,17) + udp_checksum_u1a(15 downto 0) + udp_checksum_u1a(19 downto 16)
+ udp_checksum_u1b(15 downto 0) + udp_checksum_u1b(19 downto 16);
udp_checksum_u3 <= udp_checksum_u2(15 downto 0) + udp_checksum_u2(16 downto 16);
udp_checksum <= not std_logic_vector(udp_checksum_u3);
end if;
end process;
end Behavioral; | mit | cc6503ea3308adef5f8b17f6c9e87036 | 0.52387 | 3.978669 | false | false | false | false |
xcthulhu/periphondemand | src/platforms/unioc_v11/simulation/atmega_emi_pkg.vhd | 1 | 4,319 | ---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 23/04/2008
-- File : atmega_pkg.vhd
--
-- Abstract : Simulate atmega128 read and write
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
package atmega_emi_pkg is
procedure atmega_write(
Address : in std_logic_vector( 15 downto 0);
value : in std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
);
procedure atmega_read(
Address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
);
end package atmega_emi_pkg;
package body atmega_emi_pkg is
CONSTANT TCLCL : time :=62 ns; -- 16 MHz
--Write value
procedure atmega_write(
Address : in std_logic_vector( 15 downto 0);
value : in std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
) is
begin
WR <= '1';
RD <= '1';
wait until falling_edge(clk);
ALE <= '1';
wait until rising_edge(clk);
Address_H <= Address(14 downto 8);
DA <= Address(7 downto 0);
wait until falling_edge(clk);
ALE <= '0';
wait for 5 ns;
DA <= (others => 'Z');
wait until rising_edge(clk);
DA <= value;
-- 0.5TCLCL - 20 ns
wait for 0.5*TCLCL - 20 ns;
WR <= '0';
wait until falling_edge(clk);
wait until rising_edge(clk);
if wait_states >= 0 then
for n in 1 to wait_states loop
wait until rising_edge(clk);
end loop;
end if;
WR <= '1';
wait until falling_edge(clk);
DA <= (others => 'Z');
Address_H <= (others => 'Z');
end procedure atmega_write;
--Read value
procedure atmega_read(
Address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
) is
begin
RD <= '1';
WR <= '1';
wait until falling_edge(clk);
ALE <= '1';
wait until rising_edge(clk);
Address_H <= Address(14 downto 8);
DA <= Address(7 downto 0);
wait until falling_edge(clk);
ALE <= '0';
wait for 5 ns;
DA <= (others => 'Z');
wait until rising_edge(clk);
wait for 0.5*TCLCL - 20 ns;
RD <= '0';
wait until rising_edge(clk); -- 0 wait states
if wait_states >= 0 then
for n in 1 to wait_states loop
wait until rising_edge(clk);
end loop;
end if;
assert DIR_buffer = '1' report "buffer direction error" severity error;
value <= DA;
RD <= '1';
wait until falling_edge(clk);
DA <= (others => 'Z');
Address_H <= (others => 'Z');
end procedure atmega_read;
end package body atmega_emi_pkg;
| lgpl-2.1 | 999470770ba1680bcae5ab17a50b4c2a | 0.51887 | 3.908597 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_handler.vhd | 1 | 7,897 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: udp_handler - Behavioral
--
-- Description: Provide the processing for UDP packets.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end udp_handler;
architecture Behavioral of udp_handler is
component udp_rx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
component udp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port( clk : in STD_LOGIC;
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal i_packet_out_valid : std_logic := '0';
begin
--==============================================
-- Start of UDP RX processing
--==============================================
i_udp_rx_packet: udp_rx_packet generic map (
our_ip => our_ip,
our_mac => our_mac,
our_broadcast => our_broadcast
) port map (
clk => clk,
packet_in_valid => packet_in_valid,
packet_in_data => packet_in_data,
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port);
--==============================================
-- End of UDP RX processing
--==============================================
-- Start of UDP TX processing
--==============================================
i_udp_tx_packet : udp_tx_packet generic map (
our_ip => our_ip,
our_mac => our_mac
) port map (
clk => clk,
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
--==============================================
-- End of UDP TX processing
--==============================================
--i_ila_0: ila_0 port map (
-- clk => clk,
-- probe0(0) => udp_extracted_data_valid,
-- probe1 => udp_extracted_data,
-- probe2(0) => ether_extracted_data_valid,
-- probe3(0) => ip_extracted_data_valid,
-- probe4(0) => udp_extracted_data_valid,
-- probe5(0) => i_packet_out_valid);
end Behavioral; | mit | 837fde6fae1bbbbcde3ac1d28cd231b3 | 0.499557 | 3.756898 | false | false | false | false |
freecores/hilbert_transformer | vhdl/complex_fsf_filter_c_90.vhd | 1 | 3,194 | -- This is the implementation of the complex filter C_90(z)=1/(1-j*z^-1)
-- which creates a single pole at e^j90 [deg]
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package complex_fsf_filter_c_90_pkg is
component complex_fsf_filter_c_90
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i_i : in std_logic_vector(data_width-1 downto 0);
data_q_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end complex_fsf_filter_c_90_pkg;
package body complex_fsf_filter_c_90_pkg is
end complex_fsf_filter_c_90_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.resize_tools_pkg.all;
entity complex_fsf_filter_c_90 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i_i : in std_logic_vector(data_width-1 downto 0);
data_q_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end complex_fsf_filter_c_90;
architecture complex_fsf_filter_c_90_arch of complex_fsf_filter_c_90 is
signal xi : std_logic_vector(data_width-1 downto 0);
signal xq : std_logic_vector(data_width-1 downto 0);
signal yi : std_logic_vector(data_width-1 downto 0);
signal yq : std_logic_vector(data_width-1 downto 0);
signal xisyq : std_logic_vector(data_width-1 downto 0);
signal xqayi : std_logic_vector(data_width-1 downto 0);
begin
xi <= data_i_i;
xq <= data_q_i;
data_i_o <= yi;
data_q_o <= yq;
xisyq <= resize_to_msb_round(std_logic_vector(signed(xi) - signed(yq)),data_width);
xqayi <= resize_to_msb_round(std_logic_vector(signed(xq) + signed(yi)),data_width);
process (clk_i, rst_i)
begin
if rst_i = '1' then
yi <= (others => '0');
yq <= (others => '0');
data_str_o <= '0';
elsif clk_i'EVENT and clk_i = '1' then
data_str_o <= data_str_i;
if data_str_i='1' then
yi <= xisyq;
yq <= xqayi;
end if;
end if;
end process;
end complex_fsf_filter_c_90_arch;
| gpl-3.0 | a010bd246ef044ff22d5c28610e730bb | 0.662179 | 2.829052 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/uart16750/hdl/uart_16750.vhd | 2 | 52,009 | --
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.4
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity uart_16750 is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end uart_16750;
architecture rtl of uart_16750 is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iCSWR : std_logic; -- Chipselect and write
signal iCSRD : std_logic; -- Chipselect and read
signal iWriteFE : std_logic; -- Write falling edge
signal iReadFE : std_logic; -- Read falling edge
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iA : std_logic_vector(2 downto 0); -- UART register address
signal iDIN : std_logic_vector(7 downto 0); -- UART data input
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iCSWR <= '1' when CS = '1' and WR = '1' else '0';
iCSRD <= '1' when CS = '1' and RD = '1' else '0';
UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
iWrite <= '1' when iWriteFE = '1' else '0';
iRead <= '1' when iReadFE = '1' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and iA = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0';
iLSRRead <= '1' when iRead = '1' and iA = "101" else '0';
iMSRRead <= '1' when iRead = '1' and iA = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
-- Sync. input synchronization
UART_SIS: process (CLK, RST)
begin
if (RST = '1') then
iA <= (others => '0');
iDIN <= (others => '0');
elsif (CLK'event and CLK = '1') then
iA <= A;
iDIN <= DIN;
end if;
end process;
-- Divisor latch register
UART_DLR: process (CLK, RST)
begin
if (RST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= iDIN;
end if;
if (iDLMWrite = '1') then
iDLM <= iDIN;
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, RST)
begin
if (RST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= iDIN(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => RST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, RST)
begin
if (RST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, RST)
begin
if (RST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, RST)
begin
if (RST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= iDIN(0);
iFCR_DMAMode <= iDIN(3);
iFCR_RXTrigger <= iDIN(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= iDIN(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, RST)
begin
if (RST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= iDIN;
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, RST)
begin
if (RST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= iDIN(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, RST)
begin
if (RST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRE;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, RST)
begin
if (RST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, RST)
begin
if (RST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= iDIN;
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => RST,
CE => BAUDCE,
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => RST,
D => RCLK,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => iDIN,
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => RST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => RST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, RST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, RST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, RST)
begin
if (RST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, RST)
begin
if (RST = '1') then
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
elsif (CLK'event and CLK = '1') then
-- Default values
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- DDIS
if (CS = '0' or RD = '0') then
DDIS <= '1';
end if;
-- BAUDOUTN
if (iBaudtick16x = '0') then
BAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case A is
when "000" => if (iLCR_DLAB = '0') then
DOUT <= iRBR;
else
DOUT <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
DOUT <= iIER;
else
DOUT <= iDLM;
end if;
when "010" => DOUT <= iIIR;
when "011" => DOUT <= iLCR;
when "100" => DOUT <= iMCR;
when "101" => DOUT <= iLSR;
when "110" => DOUT <= iMSR;
when "111" => DOUT <= iSCR;
when others => DOUT <= iRBR;
end case;
end process;
end rtl;
| lgpl-2.1 | 34ffce342c8787dae5a513be8cddcc0e | 0.427099 | 4.682121 | false | false | false | false |
S0obi/SY23 | state_machine/state_machine_test.vhdl | 1 | 2,401 | LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity state_machine_test is
end state_machine_test;
architecture behavior of state_machine_test is
-- Component Declaration for the Unit Under Test (UUT)
component state_machine
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
state_input : in STD_LOGIC;
tc : out STD_LOGIC);
end component;
signal tb_clk, tb_reset, tb_state_input, tb_tc: STD_LOGIC;
signal clk_te : STD_LOGIC;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant clk_te_period : time := 20 ns;
constant dT : real := 2.0; --ns
constant separator: String(1 to 1) := ";"; -- CSV separator
begin
-- Instantiate the Unit Under Test (UUT)
uut: state_machine PORT MAP (
clk => tb_clk,
reset => tb_reset,
state_input => tb_state_input,
tc => tb_tc
);
-- Clock process definitions
clk_process: process
begin
tb_clk <= '0';
wait for clk_period/2;
tb_clk <= '1';
wait for clk_period/2;
end process clk_process;
-- Clock process definitions
clk_te_process: process
begin
clk_te <= '0';
wait for clk_te_period/2;
clk_te <= '1';
wait for clk_te_period/2;
end process clk_te_process;
-- Stimulus process
stim_proc: process
begin
-- apply the reset signal
tb_reset <= '1';
wait for clk_period*10;
tb_reset <= '0';
-- apply the first input
wait for clk_period*10;
tb_state_input <= '1';
wait for clk_period*10;
tb_state_input <= '0';
-- apply the second input
wait for clk_period*20;
tb_state_input <= '1';
wait for clk_period*10;
tb_state_input <= '0';
wait;
end process stim_proc;
result: process(clk_te)
file filedatas: text open WRITE_MODE is "state_machine.csv";
variable s : line;
variable temps : real := 0.0;
begin
write(s, temps); write(s, separator);
write(s, clk_te); write(s, separator);
write(s, tb_state_input); write(s, separator);
write(s, tb_reset); write(s, separator);
write(s, tb_tc); write(s, separator);
writeline(filedatas,s);
temps := temps + dT;
end process result;
end architecture behavior;
| gpl-2.0 | dc5b68bafbc9899d43ea2d72548d8549 | 0.607663 | 3.449713 | false | true | false | false |
hamsternz/FPGA_Webserver | hdl/clocking.vhd | 1 | 4,180 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net>
--
-- Module Name: clocking - Behavioral
--
-- Description: Generate a 125MHz clock and 125MHz a clock with 90 degrees of
-- phase shift.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clocking is
Port ( clk100MHz : in STD_LOGIC;
clk125MHz : out STD_LOGIC;
clk125MHz90 : out STD_LOGIC);
end clocking;
architecture Behavioral of clocking is
signal clk100MHz_buffered : std_logic := '0';
signal clkfb : std_logic := '0';
signal clk125MHz_unbuffered : STD_LOGIC;
signal clk125MHz90_unbuffered : STD_LOGIC;
begin
bufg_100: BUFG
port map (
i => clk100MHz,
o => clk100MHz_buffered
);
-------------------------------------------------------
-- Generate a 125MHz clock from the 100MHz
-- system clock
-------------------------------------------------------
pll_clocking : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 10,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 10.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 8, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 40,
CLKOUT3_DIVIDE => 8, CLKOUT4_DIVIDE => 16, CLKOUT5_DIVIDE => 16,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => -270.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.0,
STARTUP_WAIT => "FALSE"
)
port map (
CLKIN1 => CLK100MHz_buffered,
CLKOUT0 => CLK125MHz_unbuffered, CLKOUT1 => open, CLKOUT2 => open,
CLKOUT3 => CLK125MHz90_unbuffered, CLKOUT4 => open, CLKOUT5 => open,
LOCKED => open,
PWRDWN => '0',
RST => '0',
CLKFBOUT => clkfb,
CLKFBIN => clkfb
);
bufg_125Mhz: BUFG
port map (
i => clk125MHz_unbuffered,
o => clk125MHz
);
bufg_125Mhz90: BUFG
port map (
i => clk125MHz90_unbuffered,
o => clk125MHz90
);
end Behavioral;
| mit | 2121eb199a64510b2cbf51aecdcfa5c9 | 0.566507 | 4.082031 | false | false | false | false |
sneakypete81/atom-vhdl-entity-converter | spec/fixture/instance/adder_indent_3spaces.vhd | 1 | 137 | add_i : add
generic map (
WIDTH => WIDTH,
HEIGHT => HEIGHT
)
port map (
clk => clk,
in => in,
output => output
);
| gpl-3.0 | 1741d15d707bb574c94d83dab80c9fc4 | 0.49635 | 3.113636 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/cpu.vhd | 1 | 2,675 | -------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-- Date : 12-May-14
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
bus_in : in t_bus2cpu;
bus_out : out t_cpu2bus
);
end cpu;
architecture rtl of cpu is
signal addr_cnt : unsigned(5 downto 0);
type t_reg is array (0 to 1) of std_logic_vector(DW-1 downto 0);
signal reg_arr : t_reg;
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY
-- ... To be replaced ...
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
addr_cnt <= (others => '0');
bus_out.addr <= (others => '0');
bus_out.data <= (others => '0');
bus_out.r_w <= '0';
bus_out.data <= (others => '0');
elsif rising_edge(clk) then
addr_cnt <= addr_cnt + 1;
if addr_cnt = 0 then
-- read from ROM address 0
bus_out.addr <= HBA(ROM) & std_logic_vector(addr_cnt);
bus_out.r_w <= '0';
elsif addr_cnt = 1 then
-- read from ROM address 1
bus_out.addr <= HBA(ROM) & std_logic_vector(addr_cnt);
bus_out.r_w <= '0';
elsif addr_cnt = 2 then
-- read from ROM address 2
bus_out.addr <= HBA(ROM) & std_logic_vector(addr_cnt);
bus_out.r_w <= '0';
-- store value from ROM address 0
reg_arr(0) <= bus_in.data;
elsif addr_cnt = 3 then
-- read from ROM address 3
bus_out.addr <= HBA(ROM) & std_logic_vector(addr_cnt);
bus_out.r_w <= '0';
-- store value from ROM address 1
reg_arr(1) <= bus_in.data;
elsif addr_cnt = 4 then
-- store value to RAM address 0
bus_out.addr <= HBA(RAM) & std_logic_vector(addr_cnt-4);
bus_out.r_w <= '1';
bus_out.data <= reg_arr(0);
elsif addr_cnt = 5 then
-- store value to RAM address 1
bus_out.addr <= HBA(RAM) & std_logic_vector(addr_cnt-4);
bus_out.r_w <= '1';
bus_out.data <= reg_arr(1);
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 047acb2d0d0ecaf3e7c727134aba7ce9 | 0.442617 | 3.674451 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_zc706/gtx/top.vhdl | 1 | 1,710 | --
-- Top level of gtx example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
sysclk_p_i : in std_logic;
sysclk_n_i : in std_logic;
gtxclk_p_i : in std_logic;
gtxclk_n_i : in std_logic;
rx_p_i : in std_logic;
rx_n_i : in std_logic;
tx_p_o : out std_logic;
tx_n_o : out std_logic;
pbc_i : in std_logic;
dips_i : in std_logic_vector(3 downto 0);
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of top is
signal gtxclk, sysclk : std_logic;
signal ready, loopback : std_logic;
-- GBT data
signal rx_data, tx_data : std_logic_vector(39 downto 0);
begin
gtxclk_i : IBUFGDS
port map (O => gtxclk, I => gtxclk_p_i, IB => gtxclk_n_i);
sysclk_i : IBUFGDS
port map (I => sysclk_p_i, IB => sysclk_n_i, O => sysclk);
loopback <= '0';--not pbc_i;
gbt_i: entity work.Wrapper
port map (
gtxclk_i => gtxclk,
sysclk_i => sysclk,
rst_i => '0',
--
rxp_i => rx_p_i,
rxn_i => rx_n_i,
txp_o => tx_p_o,
txn_o => tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
tx_data_i => tx_data,
ready_o => ready
);
tx_data <= dips_i & dips_i & dips_i & dips_i & dips_i &
dips_i & dips_i & dips_i & dips_i & dips_i
when ready='1' else X"AAAAAAAAAA";
leds_o <= rx_data(3 downto 0) when ready='1' else "0000";
end architecture RTL;
| bsd-3-clause | f0559648d5e01015ceab002e830cdae0 | 0.538012 | 2.903226 | false | false | false | false |
qu1x/fsio | src/lib/fsio.vhd | 1 | 2,654 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
package fsio is
constant CAP: integer := 32;
constant LEN: integer := CAP;
component fsio_get is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output as feedback of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be read
dat: out std_logic_vector(len - 1 downto 0);
-- PS requests PL to read the data
-- Is set until acknowledged and the data has been fed back
req: out std_logic;
-- PL acknowledges when it has read the data
-- Must be kept set until request has been reset
ack: in std_logic
);
end component fsio_get;
component fsio_put is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input as feedback of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be written
dat: in std_logic_vector(len - 1 downto 0);
-- PS requests PL to write the data
-- Is set until acknowledged
req: out std_logic;
-- PL acknowledges when it has written the data
-- Must be set for exactly one clock cycle
ack: in std_logic
);
end component fsio_put;
end package;
| agpl-3.0 | 8d03bdb90f637d3699d5ea3b54053064 | 0.685757 | 3.519894 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/block_simple.vhd | 1 | 730 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fnord : block
constant f : natural := 11;
begin
foo : block
constant i : natural := 10;
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
end block foo;
end block fnord;
end beh;
| gpl-3.0 | 69f5e6c680ff2dcbb405461c10df509e | 0.563014 | 3.288288 | false | false | false | false |
sneakypete81/atom-vhdl-entity-converter | spec/fixture/instance/adder_signal_prefix.vhd | 1 | 138 | add_i : add
generic map (
WIDTH => WIDTH,
HEIGHT => HEIGHT
)
port map (
clk => s_clk,
in => s_in,
output => s_output
);
| gpl-3.0 | 4f28c66d1ec508b03608fcb3e714e8c8 | 0.514493 | 2.76 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/detect_speed_and_reassemble_bytes.vhd | 1 | 9,429 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <haster@snap.net.nz>
--
-- Module Name: detect_speed_and_reassemble_bytes - Behavioral
--
-- Description: Process the raw RGMII RX data to generate bytes and status signals
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity detect_speed_and_reassemble_bytes is
Port ( clk125Mhz : in STD_LOGIC;
-- Interface to input FIFO
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC := '0';
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
link_10mb : out STD_LOGIC := '0';
link_100mb : out STD_LOGIC := '0';
link_1000mb : out STD_LOGIC := '0';
link_full_duplex : out STD_LOGIC := '0';
output_data_enable : out STD_LOGIC := '0';
output_data : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
output_data_present : out STD_LOGIC := '0';
output_data_error : out STD_LOGIC := '0');
end detect_speed_and_reassemble_bytes;
architecture Behavioral of detect_speed_and_reassemble_bytes is
signal preamble_count : unsigned(4 downto 0) := (others => '0');
signal i_link_10mb : STD_LOGIC := '0';
signal i_link_100mb : STD_LOGIC := '0';
signal i_link_1000mb : STD_LOGIC := '0';
signal i_link_full_duplex : STD_LOGIC := '0';
signal fresh_data : STD_LOGIC := '0';
signal active_data : STD_LOGIC := '0';
signal phase : STD_LOGIC := '0';
signal last_nibble_data : std_logic_vector(3 downto 0) := "0000";
signal last_nibble_data_error : std_logic := '0';
signal last_nibble_data_present : std_logic := '0';
signal i_output_data_enable : STD_LOGIC := '0';
signal i_output_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal i_output_data_present : STD_LOGIC := '0';
signal i_output_data_error : STD_LOGIC := '0';
begin
link_10mb <= i_link_10mb;
link_100mb <= i_link_100mb;
link_1000mb <= i_link_1000mb;
link_full_duplex <= i_link_full_duplex;
output_data_enable <= i_output_data_enable;
output_data <= i_output_data;
output_data_present <= i_output_data_present;
output_data_error <= i_output_data_error;
input_read <= not input_empty;
detect_link_status: process(clk125Mhz)
begin
if rising_edge(clk125Mhz) then
if fresh_data = '1' and (input_data_present = '0') and (input_data_error = '0') and
input_data(3 downto 0) = input_data(7 downto 4) then
----------------------------------------------------
-- The idle sumbols have link status incoded in them
----------------------------------------------------
i_link_10mb <= '0';
i_link_100mb <= '0';
i_link_1000mb <= '0';
i_link_full_duplex <= '0';
case input_data(2 downto 0) is
when "001" => i_link_10mb <= '1'; i_link_full_duplex <= input_data(3);
when "011" => i_link_100mb <= '1'; i_link_full_duplex <= input_data(3);
when "101" => i_link_1000mb <= '1'; i_link_full_duplex <= input_data(3);
when others => NULL;
end case;
end if;
fresh_data <= not input_empty;
end if;
end process;
reassemble_data:process(clk125Mhz)
begin
if rising_edge(clk125Mhz) then
i_output_data_present <= '0';
i_output_data_enable <= '0';
i_output_data <= (others => '0');
if i_link_1000mb = '1' then
-- this is designs such that one idle symbol will be
-- emitted after the end of the contents of the packet
if fresh_data = '1' then
if active_data = '1' then
i_output_data_enable <= '1';
i_output_data <= input_data;
i_output_data_present <= input_data_present;
i_output_data_error <= input_data_error;
active_data <= input_data_present;
preamble_count <= (others => '0');
else
-- Check we see a valid preamble sequence
-- We see two nibbles of the preamble every
-- time we see a byte
if input_data_present = '1' then
if input_data = x"55" then
if preamble_count(4 downto 2) /= "111" then
preamble_count <= preamble_count+2;
end if;
elsif input_data = x"D5" and preamble_count(4 downto 2) /= "111" then
active_data <= '1';
end if;
else
preamble_count <= (others => '0');
end if;
end if;
end if;
else
----------------------------------------------
-- For 100Mb/s and 10Mb/s the data is received
-- as nibbles (4 bits) per transfer
-----------------------------------------------
if fresh_data = '1' then
if active_data = '1' then
-- Set the output but only assert output_data_enable every other cycle
i_output_data <= input_data(3 downto 0) & last_nibble_data;
i_output_data_present <= input_data_present and last_nibble_data_present;
i_output_data_error <= input_data_error or last_nibble_data_error;
i_output_data_enable <= phase;
phase <= not phase;
-- Only allow 'active data' to drop during second half of byte
if phase = '1' then
active_data <= input_data_present and last_nibble_data_present;
end if;
else
-- Check we see a valid preamble sequence
if input_data_present = '1' then
if input_data = x"55" then
if preamble_count (4) = '0' then
preamble_count <= preamble_count+1;
end if;
elsif input_data = x"DD" and preamble_count(4) = '0' then
active_data <= '1';
phase <= '0';
end if;
else
preamble_count <= (others => '0');
end if;
end if;
end if;
end if;
if fresh_data = '1' then
-- Remember the data in case we are running at
-- a slow data rate (where nibbles are transferred)
last_nibble_data <= input_data(3 downto 0);
last_nibble_data_present <= input_data_present;
last_nibble_data_error <= input_data_error;
last_nibble_data_present <= input_data_present;
end if;
end if;
end process;
end Behavioral;
| mit | ae82793fd101babde8fde9e7d94ef403 | 0.471418 | 4.475083 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/arp/arp_resolver.vhd | 1 | 8,993 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Module Name: arp_resolver - Behavioral
--
-- Description:
--
-- Dependencies:
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_resolver is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
--------------------------------------------------------------------
-- Interface for modules to attempt to resolve an IP to a MAC address
-- Fixed latency of less than 16 cycle.
--------------------------------------------------------------------
ch0_lookup_request : in std_logic;
ch0_lookup_ip : in std_logic_vector(31 downto 0);
ch0_lookup_mac : out std_logic_vector(47 downto 0);
ch0_lookup_found : out std_logic;
ch1_lookup_request : in std_logic;
ch1_lookup_ip : in std_logic_vector(31 downto 0);
ch1_lookup_mac : out std_logic_vector(47 downto 0);
ch1_lookup_found : out std_logic;
ch2_lookup_request : in std_logic;
ch2_lookup_ip : in std_logic_vector(31 downto 0);
ch2_lookup_mac : out std_logic_vector(47 downto 0);
ch2_lookup_found : out std_logic;
ch3_lookup_request : in std_logic;
ch3_lookup_ip : in std_logic_vector(31 downto 0);
ch3_lookup_mac : out std_logic_vector(47 downto 0);
ch3_lookup_found : out std_logic;
--------------------------------------------------------------------
-- Interface from the ARP packet receiving model to update the table
--------------------------------------------------------------------
update_valid : in std_logic;
update_ip : in std_logic_vector(31 downto 0);
update_mac : in std_logic_vector(47 downto 0);
--------------------------------------------------------------------
-- Interface to request a new ARP packet go out on the wire
--------------------------------------------------------------------
arp_queue_request : out std_logic;
arp_queue_request_ip : out std_logic_vector(31 downto 0));
end arp_resolver;
architecture Behavioral of arp_resolver is
signal counter : unsigned(1 downto 0) := (others => '0');
signal ch0_in_progress : std_logic := '0';
signal ch1_in_progress : std_logic := '0';
signal ch2_in_progress : std_logic := '0';
signal ch3_in_progress : std_logic := '0';
signal arp_lookup_ip : std_logic_vector(31 downto 0) := (others => '0');
type t_arp_table is array(0 to 255) of std_logic_vector(47 downto 0);
type t_arp_valid is array(0 to 255) of std_logic;
signal arp_table : t_arp_table := (255 => (others => '1'), others => (others => '0'));
signal arp_valid : t_arp_valid := (255 => '1', others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
case counter is
when "000" => if ch0_lookup_request = '1' then
arp_lookup_ip <= ch0_lookup_ip;
ch0_in_progress <= '1';
else
arp_lookup_ip <= (others => '0');
ch0_in_progress <= '0';
end if;
ch2_lookup_mac <= arp_lookup_mac;
ch2_lookup_ip <= arp_lookup_valid;
if ch2_in_progress = '1' and arp_lookup_valid = '0' and arp_last_asked_seconds < 10
then
arp_request <= '1';
arp_request_ip <= ch2_lookup_ip;
else
arp_request <= '0';
end if;
when "001" => if ch1_lookup_request = '1' then
arp_lookup_ip <= ch1_lookup_ip;
ch1_in_progress <= '1';
else
arp_lookup_ip <= (others => '0');
ch1_in_progress <= '0';
end if;
ch3_lookup_mac <= arp_lookup_mac;
ch3_lookup_ip <= arp_lookup_valid;
if ch3_in_progress = '1' and arp_lookup_valid = '0' and arp_last_asked_seconds < 10
then
arp_request <= '1';
arp_request_ip <= ch3_lookup_ip;
else
arp_request <= '0';
end if;
when "010" => if ch2_lookup_request = '1' then
arp_lookup_ip <= ch2_lookup_ip;
ch2_in_progress <= '1';
else
arp_lookup_ip <= (others => '0');
ch2_in_progress <= '0';
end if;
ch0_lookup_mac <= arp_lookup_mac;
ch0_lookup_ip <= arp_lookup_valid;
if ch0_in_progress = '1' and arp_lookup_valid = '0' and arp_last_asked_seconds < 10
then
arp_request <= '1';
arp_request_ip <= ch0_lookup_ip;
else
arp_request <= '0';
end if;
when others => if ch3_lookup_request = '1' then
arp_lookup_ip <= ch3_lookup_ip;
ch3_in_progress <= '1';
else
arp_lookup_ip <= (others => '0');
ch3_in_progress <= '0';
end if;
ch1_lookup_mac <= arp_lookup_mac;
ch1_lookup_ip <= arp_lookup_valid;
if ch1_in_progress = '1' and arp_lookup_valid = '0' and arp_last_asked_seconds < 10
then
arp_request <= '1';
arp_request_ip <= ch1_lookup_ip;
else
arp_request <= '0';
end if;
end case;
end if;
end process;
end Behavioral;
| mit | 4e19686535faf84c898149147681e187 | 0.403202 | 4.858455 | false | false | false | false |
xcthulhu/periphondemand | src/library/wrappers/imx27_wb16_wrapper/hdl/imx27_wb16_wrapper.vhd | 1 | 3,383 | -------------------------------------------------------------------------------
--
-- File : imx27_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : i.MX wrapper to Wishbone bus
--
-- Creation Date : 2007/01/19
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
-----
-- 2008/03/05
-- Fabien Marteau (fabien.marteau@armadeus.com)
-- adding comments and changing some signals names
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
Entity imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
port
(
-- i.MX Signals
imx_address : in std_logic_vector(11 downto 0);
imx_data : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb0_n : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(12 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(12 downto 0);
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
read <= '0';
strobe <= '0';
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb0_n);
write <= not (imx_cs_n or imx_eb0_n);
read <= not (imx_cs_n or imx_oe_n);
address <= imx_address & '0';
writedata <= imx_data;
end if;
end process;
wbm_address <= address when (strobe = '1') else (others => '0');
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_data <= wbm_readdata when (read = '1') else (others => 'Z');
end architecture RTL;
| lgpl-2.1 | 5e20b915b65c0fe32e0e1abe386eb9a6 | 0.435412 | 4.260705 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/ddr3/top.vhdl | 1 | 7,964 | --
-- DDR3 example Top-Level
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Verif.all;
entity Top is
generic (
SIM_BYPASS_INIT_CAL : string := "OFF";
DM_WIDTH : integer := 8;
DQ_WIDTH : integer := 64;
ROW_WIDTH : integer := 13;
RANK_WIDTH : integer := 1;
BANK_WIDTH : integer := 3;
CS_WIDTH : integer := 1;
nCS_PER_RANK : integer := 1;
CKE_WIDTH : integer := 1;
DQS_WIDTH : integer := 8;
CK_WIDTH : integer := 1
);
port (
-- Clock
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_rst_i : in std_logic;
clk_ref_p_i : in std_logic;
clk_ref_n_i : in std_logic;
-- DDR3
ddr3_dq_io : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_cs_n_o : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt_o : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke_o : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p_o : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(CK_WIDTH-1 downto 0);
-- App
rx_errors_o : out std_logic_vector(4 downto 0)
);
end entity Top;
architecture RTL of Top is
constant WRITE_CMD : std_logic_vector(2 downto 0):="000";
constant READ_CMD : std_logic_vector(2 downto 0):="001";
constant ADDR_WIDTH : integer := 27; -- RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant PAYLOAD_WIDTH : integer := 64;
constant APP_DATA_WIDTH : integer := PAYLOAD_WIDTH * 4;
signal sys_clk : std_logic := '0';
signal sys_rst : std_logic := '1';
signal clk_ref : std_logic := '0';
signal stop : boolean;
signal sys_clk_p, sys_clk_n : std_logic;
signal clk_ref_p, clk_ref_n : std_logic;
signal phy_init_done : std_logic;
signal app_clk : std_logic;
signal app_rst : std_logic;
--
signal app_en : std_logic;
signal app_cmd : std_logic_vector(2 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_rdy : std_logic;
--
signal app_wdf_wren : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_rdy : std_logic;
--
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_valid : std_logic;
signal rx_data, tx_data : std_logic_vector(7 downto 0);
signal rx_stb, tx_stb : std_logic;
type state_t is (IDLE_S, WR_LOW_S, WR_HIGH_S, COMMAND_S, RD_LOW_S, RD_HIGH_S, FINISH_S);
signal state : state_t:=IDLE_S;
begin
mig_inst : entity work.mig
generic map(
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
CLKFBOUT_MULT_F => 6,
DIVCLK_DIVIDE => 1, -- 2; -- Coregen assumes sys_clk = 400 MHz but we use 200 MHz
CLKOUT_DIVIDE => 3,
RST_ACT_LOW => 0
)
port map(
sys_clk_p => sys_clk_p_i,
sys_clk_n => sys_clk_n_i,
clk_ref_p => clk_ref_p_i,
clk_ref_n => clk_ref_n_i,
sys_rst => sys_rst_i,
ddr3_ck_p => ddr3_ck_p_o,
ddr3_ck_n => ddr3_ck_n_o,
ddr3_addr => ddr3_addr_o,
ddr3_ba => ddr3_ba_o,
ddr3_ras_n => ddr3_ras_n_o,
ddr3_cas_n => ddr3_cas_n_o,
ddr3_we_n => ddr3_we_n_o,
ddr3_cs_n => ddr3_cs_n_o,
ddr3_cke => ddr3_cke_o,
ddr3_odt => ddr3_odt_o,
ddr3_reset_n => ddr3_reset_n_o,
ddr3_dm => ddr3_dm_o,
ddr3_dq => ddr3_dq_io,
ddr3_dqs_p => ddr3_dqs_p_io,
ddr3_dqs_n => ddr3_dqs_n_io,
ui_clk => app_clk,
ui_clk_sync_rst => app_rst,
app_wdf_wren => app_wdf_wren,
app_wdf_data => app_wdf_data,
app_wdf_mask => (others => '0'),
app_wdf_end => app_wdf_end,
app_addr => app_addr,
app_en => app_en,
app_cmd => app_cmd,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_rd_data => app_rd_data,
app_rd_data_end => open,
app_rd_data_valid => app_rd_data_valid,
sda => '1',
scl => '1',
phy_init_done => phy_init_done
);
loop_i: LoopCheck
generic map (DWIDTH => 8)
port map(
-- TX side
tx_clk_i => app_clk,
tx_rst_i => app_rst,
tx_stb_i => tx_stb,
tx_data_i => (others => '0'),
tx_data_o => tx_data,
-- RX side
rx_clk_i => app_clk,
rx_rst_i => app_rst,
rx_stb_i => rx_stb,
rx_data_i => rx_data,
rx_errors_o => rx_errors_o
);
do_fsm: process(app_clk) is
begin
if rising_edge(app_clk) then
if app_rst='1' then
state <= IDLE_S;
app_addr <= (others => '0');
app_en <= '0';
app_wdf_wren <= '0';
app_wdf_data <= (others => '0');
else
app_en <= '0';
app_wdf_wren <= '0';
app_wdf_end <= '0';
case state is
when IDLE_S =>
if phy_init_done='1' then
state <= WR_LOW_S;
end if;
when WR_LOW_S =>
app_cmd <= WRITE_CMD;
app_wdf_wren <= '1';
app_wdf_data <= X"0123456789012345678901234567890123456789012345678901234567890123";
if app_wdf_rdy='1' then
state <= WR_HIGH_S;
end if;
when WR_HIGH_S =>
app_wdf_wren <= '1';
app_wdf_end <= '1';
app_wdf_data <= X"ABCDEFABCDEFABCDEFABCDEFABCDEFABCDEFABCDEFABCDEFABCDEFABCDEFABCD";
if app_wdf_rdy='1' then
state <= COMMAND_S;
end if;
when COMMAND_S =>
app_wdf_data <= (others => '0');
app_en <= '1';
if app_rdy='1' then
state <= RD_LOW_S;
--if app_en='1' then
-- app_en <= '0';
--end if;
end if;
when RD_LOW_S =>
app_cmd <= READ_CMD;
state <= RD_HIGH_S;
when RD_HIGH_S =>
app_en <= '1';
if app_rdy='1' then
state <= FINISH_S;
end if;
when FINISH_S =>
end case;
end if;
end if;
end process do_fsm;
end architecture RTL;
| bsd-3-clause | bce492f7fd4c8b030cadd12a1f276cf8 | 0.45103 | 3.323873 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/testbench/bascule_rs.vhd | 1 | 2,028 | --
-- Copyright (c) ARMadeus Project 2009
--
--
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : bascule_rs.vhd
-- Created on : 05/06/2009
-- Author : Fabien Marteau <fabien.marteau@armadeus.com>
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity bascule_rs is
---------------------------------------------------------------------------
port
(
r1 : in std_logic ;
r2 : in std_logic ;
clk : in std_logic ;
s : in std_logic;
q :out std_logic ;
q_n : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture bascule_rs_1 of bascule_rs is
---------------------------------------------------------------------------
signal q_s : std_logic ;
begin
process (clk)
begin
if rising_edge(clk) then
if (r1 or r2) = '1' then
q_s <= '0';
elsif s = '1' then
q_s <= '1';
else
q_s <= q_s;
end if;
end if;
end process;
q <= q_s;
q_n <= not q_s;
end architecture bascule_rs_1;
| lgpl-2.1 | 0f9f68a43ca9887994f0182d48ab140a | 0.481262 | 4.447368 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/rtl/mcb_raw_wrapper.vhd | 9 | 299,135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:04 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
-- Rev 1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
-- Rev 1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010
-- Rev 1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
-- CDC static timing issue. 2-14-2011
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
--CR 596422
constant allzero : std_logic_vector(127 downto 0) := (others => '0');
--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
----------------------------------------------------------------------------
-- signal Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal selfrefresh_mode_sig : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
signal uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
signal uo_done_cal_sig : std_logic;
signal wait_200us_counter : std_logic_vector(15 downto 0);
signal cke_train_reg : std_logic;
signal wait_200us_done_r1 : std_logic;
signal wait_200us_done_r2 : std_logic;
signal syn1_sys_rst : std_logic;
signal syn2_sys_rst : std_logic;
signal selfrefresh_enter_r1 : std_logic;
signal selfrefresh_enter_r2 : std_logic;
signal selfrefresh_enter_r3 : std_logic;
signal gated_pll_lock : std_logic;
signal soft_cal_selfrefresh_req : std_logic;
signal normal_operation_window : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Assign the output signals with corresponding intermediate signals
uo_done_cal <= uo_done_cal_sig;
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
syn_uiclk_pll_lock <= pll_lock;
end if;
end if;
end process;
-- logic to determine if Memory is SELFREFRESH mode operation or NORMAL mode.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
normal_operation_window <= '1';
elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
normal_operation_window <= '0';
elsif ((selfrefresh_enter_r2 = '0') and (selfrefresh_mode_sig = '0')) then
normal_operation_window <= '1';
else
normal_operation_window <= normal_operation_window;
end if;
end if;
end process;
process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
begin
if (normal_operation_window = '1') then
gated_pll_lock <= pll_lock;
else
gated_pll_lock <= syn_uiclk_pll_lock;
end if;
end process;
-- int_sys_rst will be asserted if pll lose lock during normal operation.
-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
-- reset will not be generated.
int_sys_rst <= sys_rst or not(gated_pll_lock);
-- synchronize the selfrefresh_enter
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
selfrefresh_enter_r1 <= '0';
selfrefresh_enter_r2 <= '0';
selfrefresh_enter_r3 <= '0';
else
selfrefresh_enter_r1 <= selfrefresh_enter;
selfrefresh_enter_r2 <= selfrefresh_enter_r1;
selfrefresh_enter_r3 <= selfrefresh_enter_r2;
end if;
end if;
end process;
-- The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
-- It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
-- This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
soft_cal_selfrefresh_req <= '0';
elsif (selfrefresh_enter_r3 = '1') then
soft_cal_selfrefresh_req <= '1';
elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then
soft_cal_selfrefresh_req <= '0';
else
soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
end if;
end if;
end process;
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(7 downto 4);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
--process(ui_clk)
--begin
--if (ui_clk'event and ui_clk = '1') then
-- syn1_sys_rst <= sys_rst;
-- syn2_sys_rst <= syn1_sys_rst;
--end if;
--end process;
uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
--RST => syn2_sys_rst,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
--PLL_LOCK => pll_lock,
PLL_LOCK => gated_pll_lock,
--SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_REQ => soft_cal_selfrefresh_req, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode_sig, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
selfrefresh_mode_sig <= '0';
-- synthesis translate_off
init_sequence: if (C_SIMULATION = "FALSE") generate
-- synthesis translate_on
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
wait_200us_counter <= (others => '0');
elsif (ui_clk'event and ui_clk = '1') then -- UI_CLK maximum is up to 100 MHz
if (wait_200us_counter(15) = '1') then
wait_200us_counter <= wait_200us_counter;
else
wait_200us_counter <= wait_200us_counter + '1';
end if;
end if;
end process;
-- synthesis translate_off
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
wait_200us_counter <= X"FFFF";
process
begin
report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
wait;
end process;
end generate;
-- synthesis translate_on
gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
process (ui_clk)
begin
-- When wait_200us_[13] and wait_200us_[14] are both asserted,
-- 200 us wait should have been passed.
if (ui_clk'event and ui_clk = '1') then
if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
wait_200us_done_r1 <= '1';
else
wait_200us_done_r1 <= '0';
end if;
wait_200us_done_r2 <= wait_200us_done_r1;
end if;
end process;
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
cke_train_reg <= '0';
elsif (ui_clk'event and ui_clk = '1') then
if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
cke_train_reg <= '1';
elsif (uo_done_cal_sig = '1') then
cke_train_reg <= '0';
end if;
end if;
end process;
cke_train <= cke_train_reg;
end generate;
gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
cke_train <= '0';
end generate;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
selfrefresh_mode <= selfrefresh_mode_sig;
end aarch;
| cc0-1.0 | 0854918734d75618cc62e3b9bf3c26f0 | 0.423755 | 3.324978 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/for_loop_nested.vhd | 1 | 857 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ForLoop is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ForLoop;
architecture behaviour of ForLoop is
signal result : std_logic_vector(n downto 0);
begin
forLoopProc : process
variable M : natural := 42;
variable F : natural := 10;
begin
for I in 1 to 2 loop
for J in 1 to 2 loop
for F in 1 to 2 loop
F := I + J;
end loop;
for M in 1 to 2 loop
M := I + J;
end loop;
end loop;
end loop;
end process forLoopProc;
end behaviour;
| gpl-3.0 | 47f4b945bad64eed03daac3eb29872aa | 0.556593 | 3.556017 | false | false | false | false |
S0obi/SY23 | clock_divider/clock_divider_test.vhdl | 1 | 1,960 | LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity clock_divider_test is
end clock_divider_test;
architecture behavior of clock_divider_test is
-- Component Declaration for the Unit Under Test (UUT)
component divider
GENERIC (
N: integer := 10
);
PORT(
clk : IN std_logic;
tc : OUT std_logic
);
end component;
signal tb_clk, tb_tc: STD_LOGIC;
signal clk_te : STD_LOGIC;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant clk_te_period : time := 20 ns;
constant dT : real := 2.0; --ns
constant separator: String(1 to 1) := ";"; -- CSV separator
begin
-- Instantiate the Unit Under Test (UUT)
uut: divider PORT MAP (
clk => tb_clk,
tc => tb_tc
);
-- Clock process definitions
clk_process: process
begin
tb_clk <= '0';
wait for clk_period/2;
tb_clk <= '1';
wait for clk_period/2;
end process clk_process;
-- Clock process definitions
clk_te_process: process
begin
clk_te <= '0';
wait for clk_te_period/2;
clk_te <= '1';
wait for clk_te_period/2;
end process clk_te_process;
-- Stimulus process
stim_proc: process
begin
--wait for 100ms;
--tb_reset <= '1';
--wait for clk_period*10;
--tb_reset <= '0';
-- insert stimulus here
wait;
end process stim_proc;
result: process(clk_te)
file filedatas: text open WRITE_MODE is "clock_divider.csv";
variable s : line;
variable temps : real := 0.0;
begin
--if rising_edge(clk_te) then
write(s, temps); write(s, separator);
write(s, tb_clk); write(s, separator);
write(s, tb_tc); write(s, separator);
writeline(filedatas,s);
temps := temps + dT;
--end if;
end process result;
end architecture behavior;
| gpl-2.0 | a3e757b20afc0f28c6511c1edad4bf8a | 0.608673 | 3.420593 | false | true | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx/top.vhdl | 1 | 1,902 | --
-- Top level of gtx example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
rst_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
sma_rx_p_i : in std_logic;
sma_rx_n_i : in std_logic;
sma_tx_p_o : out std_logic;
sma_tx_n_o : out std_logic;
pbc_i : in std_logic;
dips_i : in std_logic_vector(7 downto 0);
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of top is
signal reset, sysclk : std_logic;
signal locked, ready : std_logic;
signal loopback : std_logic;
-- GBT data
signal rx_data, tx_data : std_logic_vector(15 downto 0);
signal rx_isk, tx_isk : std_logic_vector(1 downto 0);
begin
mmcm_inst: entity work.mmcm200to150
port map (
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
CLK_OUT1 => sysclk,
RESET => rst_i,
LOCKED => locked
);
reset <= not locked;
loopback <= not pbc_i;
gbt_i: entity work.Wrapper
port map (
clk_i => sysclk,
rst_i => reset,
clk_o => open,
--
rxp_i => sma_rx_p_i,
rxn_i => sma_rx_n_i,
txp_o => sma_tx_p_o,
txn_o => sma_tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
rx_isk_o => rx_isk,
tx_data_i => tx_data,
tx_isk_i => tx_isk,
ready_o => ready
);
tx_data <= dips_i & x"BC" when ready='1' else (others => '0');
tx_isk <= "01" when ready='1' else (others => '0');
leds_o <= rx_data(15 downto 8) when ready='1' else "10101010";
end architecture RTL;
| bsd-3-clause | d7659af7128a2f0b6b643a8218b6360d | 0.521556 | 2.939722 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine_add_data.vhd | 1 | 7,302 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_add_data - Behavioral
--
-- Description: Add the data stream alongsude the packet header
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_add_data is
Port ( clk : in STD_LOGIC;
read_en : out std_logic := '0';
empty : in std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
out_hdr_valid : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_valid : out std_logic := '0';
out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end tcp_engine_add_data;
architecture Behavioral of tcp_engine_add_data is
type t_state is (waiting, reading, new_packet, first_data, adding_data, no_data);
signal state : t_state := waiting;
signal address : std_logic_vector(15 downto 0) := (others => '0');
signal data_left_to_go : unsigned(10 downto 0) := (others => '0');
component tcp_engine_content_memory is
port (
clk : in std_logic;
address : in std_logic_vector(15 downto 0);
data : out std_logic_vector(7 downto 0));
end component;
begin
process(clk)
begin
if rising_edge(clk) then
read_en <= '0';
out_hdr_valid <= '0';
out_data_valid <= '0';
address <= std_logic_vector(unsigned(address)+1);
data_left_to_go <= data_left_to_go-1;
case state is
when waiting =>
if empty = '0' then
read_en <= '1';
state <= reading;
end if;
when reading =>
state <= new_packet;
when new_packet =>
out_src_port <= in_src_port;
out_dst_ip <= in_dst_ip;
out_dst_port <= in_dst_port;
out_seq_num <= in_seq_num;
out_ack_num <= in_ack_num;
out_window <= in_window;
out_flag_urg <= in_flag_urg;
out_flag_ack <= in_flag_ack;
out_flag_psh <= in_flag_psh;
out_flag_rst <= in_flag_rst;
out_flag_syn <= in_flag_syn;
out_flag_fin <= in_flag_fin;
out_urgent_ptr <= in_urgent_ptr;
if unsigned(in_data_len) = 0 then
state <= no_data;
else
state <= first_data;
address <= in_data_addr;
data_left_to_go <= unsigned(in_data_len)-1;
end if;
when first_data =>
out_hdr_valid <= '1';
out_data_valid <= '1';
if data_left_to_go = 0 then
state <= waiting;
else
state <= adding_data;
end if;
when adding_data =>
out_data_valid <= '1';
if data_left_to_go = 0 then
state <= waiting;
else
state <= adding_data;
end if;
when no_data =>
out_hdr_valid <= '1';
state <= waiting;
when others =>
state <= waiting;
end case;
end if;
end process;
i_tcp_engine_content_memory: tcp_engine_content_memory port map (
clk => clk,
address => address,
data => out_data );
end Behavioral;
| mit | 50a22e5384befff276511e5660513826 | 0.475075 | 4.018712 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/i2cocore/hdl/i2c_ocore.vhd | 1 | 23,200 | --
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues
--
--
-- Changes compared to simple_i2c
-- 1) WISHBONE interface
-- 2) added start/stop detection
-- 3) added busy bit
-- 4) removed automatic tri-state buffer insertion (for ASIC support)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity wishbone_i2c_master is
port (
-- wishbone signals
CLK_I : in std_logic; -- master clock input
RST_I : in std_logic := '0'; -- synchronous active high reset
nRESET: in std_logic := '1'; -- asynchronous active low reset
ADR_I : in std_logic_vector(1 downto 0); -- lower address bits
DAT_I : in std_logic_vector(15 downto 0); -- Databus input
DAT_O : out std_logic_vector(15 downto 0); -- Databus output
SEL_I : in std_logic_vector(1 downto 0); -- Byte select signals
WE_I : in std_logic; -- Write enable input
STB_I : in std_logic; -- Strobe signals / core select signal
CYC_I : in std_logic; -- Valid bus cycle input
ACK_O : out std_logic; -- Bus cycle acknowledge output
INTA_O : out std_logic; -- interrupt request output signal
-- I2C signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end entity wishbone_i2c_master;
architecture structural of wishbone_i2c_master is
component byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
ena,
start,
stop,
read,
write,
ack_in : std_logic;
Din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
Dout : out std_logic_vector(7 downto 0);
i2c_busy : out std_logic;
-- i2c signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end component byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
-- core enable signal
signal core_en : std_logic;
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- bus busy (start signal detected)
begin
-- generate acknowledge output signal
ACK_O <= STB_I; -- since timing is always honored
-- assign DAT_O
assign_dato : process(ADR_I, prer, ctr, txr, cr, rxr, sr)
begin
case ADR_I is
when "00" =>
DAT_O <= std_logic_vector(prer);
when "01" =>
DAT_O <= (x"00" & ctr);
when "10" =>
DAT_O <= (txr & cr);
when "11" =>
DAT_O <= (rxr & sr);
when others =>
DAT_O <= (others => 'X'); -- for simulation only
end case;
end process assign_dato;
-- registers block
regs_block: block
-- address decode signals
signal we_a0, we_a1, we_a2, we_a3 : std_logic;
begin
-- decode address lines
we_a0 <= CYC_I and STB_I and WE_I and not ADR_I(1) and not ADR_I(0); -- 00
we_a1 <= CYC_I and STB_I and WE_I and not ADR_I(1) and ADR_I(0); -- 01
we_a2 <= CYC_I and STB_I and WE_I and ADR_I(1) and not ADR_I(0); -- 10
we_a3 <= CYC_I and STB_I and WE_I and ADR_I(1) and ADR_I(0); -- 11
-- store data in writeable registers
-- prescale register
write_prer: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
prer <= (others => '1');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
prer <= (others => '1');
else
if ( (we_a0 and SEL_I(1)) = '1') then
prer(15 downto 8) <= unsigned(DAT_I(15 downto 8));
end if;
if ( (we_a0 and SEL_I(0)) = '1') then
prer(7 downto 0) <= unsigned(DAT_I(7 downto 0));
end if;
end if;
end if;
end process write_prer;
-- control register
write_ctr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
ctr <= (others => '0');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
ctr <= (others => '0');
else
if ( (we_a1 and SEL_I(0)) = '1') then
ctr <= DAT_I(7 downto 0);
end if;
end if;
end if;
end process write_ctr;
-- transmit register
write_txr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
txr <= (others => '0');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
txr <= (others => '0');
else
if ( (we_a2 and SEL_I(1)) = '1') then
txr <= DAT_I(15 downto 8);
end if;
end if;
end if;
end process write_txr;
-- command register
write_cr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
cr <= (others => '0'); -- asynchronous clear
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
cr <= (others => '0'); -- synchronous clear
else
if ( (we_a2 and SEL_I(0)) = '1') then
if (core_en = '1') then
cr <= DAT_I(7 downto 0); -- only take new commands when I2C core is enabled, pending commands are finished
end if;
else
if (done = '0') then
cr(7 downto 4) <= cr(7 downto 4);
else
cr(7 downto 0) <= (others => '0'); -- clear command_bits when command completed
end if;
cr(2 downto 1) <= cr(2 downto 1);
cr(0) <= cr(0) and irq_flag; -- automatically clear when irq_flag is cleared
end if;
end if;
end if;
end process write_cr;
end block regs_block;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
-- hookup byte controller block
u1: byte_ctrl port map (clk => CLK_I,
rst => RST_I,
nReset => nRESET,
clk_cnt => prer,
ena => core_en,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
Din => txr,
cmd_ack => done,
ack_out => irxack,
Dout => rxr, -- note: maybe store rxr in registers ??
SCLi => SCLi,
SCLo => SCLo,
SDAi => SDAi,
SDAo => SDAo);
-- status register block + interrupt request signal
st_block : block
begin
-- generate status register bits
gen_sr_bits: process (CLK_I, nRESET)
begin
if (nRESET = '0') then
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
rxack <= irxack;
tip <= ( rd or wr );
irq_flag <= (done or irq_flag) and not iack; -- interrupt request flag is always generated
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (CLK_I, nRESET)
begin
if (nRESET = '0') then
INTA_O <= '0';
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
INTA_O <= '0';
else
INTA_O <= irq_flag and ctr(6); -- interrupt signal is only generated when IEN (interrupt enable bit) is set
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
ena,
start,
stop,
read,
write,
ack_in : std_logic;
Din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
Dout : out std_logic_vector(7 downto 0);
i2c_busy : out std_logic;
-- i2c signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end entity byte_ctrl;
architecture structural of byte_ctrl is
component bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(2 downto 0);
cmd_ack : out std_logic;
busy : out std_logic;
Din : in std_logic;
Dout : out std_logic;
SCLin : in std_logic; -- I2C clock line
SCLout : out std_logic;
SDAin : in std_logic; -- I2C data line
SDAout : out std_logic
);
end component bit_ctrl;
-- commands for i2c_core
constant CMD_NOP : std_logic_vector(2 downto 0) := "000";
constant CMD_START : std_logic_vector(2 downto 0) := "010";
constant CMD_STOP : std_logic_vector(2 downto 0) := "011";
constant CMD_READ : std_logic_vector(2 downto 0) := "100";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "101";
-- signals for bit_controller
signal core_cmd : std_logic_vector(2 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
begin
-- hookup bit_controller
u1: bit_ctrl port map (clk, rst, nReset, clk_cnt, ena, core_cmd, core_ack, i2c_busy, core_txd, core_rxd, SCLi, SCLo, SDAi, SDAo);
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write) and not host_ack;
-- assign Dout output to shift-register
Dout <= sr;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
-- generate shift register
shift_register: process(clk)
begin
if (clk'event and clk = '1') then
if (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal state : states;
signal dcnt : unsigned(2 downto 0);
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset, state)
variable nxt_state : states;
variable idcnt : unsigned(2 downto 0);
variable ihost_ack : std_logic;
variable icore_cmd : std_logic_vector(2 downto 0);
variable icore_txd : std_logic;
variable ishift, iload : std_logic;
begin
-- 8 databits (1byte) of data to shift-in/out
idcnt := dcnt;
-- no acknowledge (until command complete)
ihost_ack := '0';
icore_txd := core_txd;
-- keep current command to bit_controller
icore_cmd := core_cmd;
-- no shifting or loading of shift-register
ishift := '0';
iload := '0';
-- keep current state;
nxt_state := state;
case state is
when st_idle =>
if (go = '1') then
if (start = '1') then
nxt_state := st_start;
icore_cmd := CMD_START;
elsif (read = '1') then
nxt_state := st_read;
icore_cmd := CMD_READ;
idcnt := "111";
else
nxt_state := st_write;
icore_cmd := CMD_WRITE;
idcnt := "111";
iload := '1';
end if;
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
nxt_state := st_read;
icore_cmd := CMD_READ;
idcnt := "111";
else
nxt_state := st_write;
icore_cmd := CMD_WRITE;
idcnt := "111";
iload := '1';
end if;
end if;
when st_write =>
if (core_ack = '1') then
idcnt := dcnt -1; -- count down Data_counter
icore_txd := sr(7);
if (dcnt = 0) then
nxt_state := st_ack;
icore_cmd := CMD_READ;
else
ishift := '1';
-- icore_txd := sr(7);
end if;
end if;
when st_read =>
if (core_ack = '1') then
idcnt := dcnt -1; -- count down Data_counter
ishift := '1';
if (dcnt = 0) then
nxt_state := st_ack;
icore_cmd := CMD_WRITE;
icore_txd := ack_in;
end if;
end if;
when st_ack =>
if (core_ack = '1') then
-- generate command acknowledge signal
ihost_ack := '1';
-- Perform an additional shift, needed for 'read' (store last received bit in shift register)
ishift := '1';
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
nxt_state := st_stop;
icore_cmd := CMD_STOP;
else
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end if;
end if;
when st_stop =>
if (core_ack = '1') then
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end if;
when others => -- illegal states
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end case;
-- generate registers
if (nReset = '0') then
core_cmd <= CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
dcnt <= "111";
host_ack <= '0';
state <= st_idle;
elsif (clk'event and clk = '1') then
if (rst = '1') then
core_cmd <= CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
dcnt <= "111";
host_ack <= '0';
state <= st_idle;
else
state <= nxt_state;
dcnt <= idcnt;
shift <= ishift;
ld <= iload;
core_cmd <= icore_cmd;
core_txd <= icore_txd;
host_ack <= ihost_ack;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~\____
-- SDA ~~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ____/~~~~\___
-- SDA __/~~~\______
-- x | A | B | C | D | i
--
-- stop SCL ____/~~~~~~~~
-- SDA ==\____/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ____/~~~~\____
-- SDA ==X=========X=
-- x | A | B | C | D | i
--
--- read SCL ____/~~~~\____
-- SDA XXXX=====XXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(2 downto 0);
cmd_ack : out std_logic;
busy : out std_logic;
Din : in std_logic;
Dout : out std_logic;
-- i2c lines
SCLin : in std_logic; -- I2C clock line
SCLout : out std_logic;
SDAin : in std_logic; -- I2C data line
SDAout : out std_logic
);
end entity bit_ctrl;
architecture structural of bit_ctrl is
constant CMD_NOP : std_logic_vector(2 downto 0) := "000";
constant CMD_START : std_logic_vector(2 downto 0) := "010";
constant CMD_STOP : std_logic_vector(2 downto 0) := "011";
constant CMD_READ : std_logic_vector(2 downto 0) := "100";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "101";
type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal state : cmds;
signal SCLo, SDAo : std_logic; -- internal I2C lines
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal txd : std_logic; -- transmit bit
signal clk_en, slave_wait :std_logic; -- clock generation signals
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- synchronize SCL and SDA inputs
synch_SCL_SDA: process(clk)
begin
if (clk'event and clk = '1') then
sSCL <= SCLin;
sSDA <= SDAin;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
slave_wait <= '1' when ( (SCLo = '1') and (sSCL = '0') ) else '0';
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
else
if ( (cnt = 0) or (ena = '0') ) then
clk_en <= '1';
cnt <= clk_cnt;
else
if (slave_wait = '0') then
cnt <= cnt -1;
end if;
clk_en <= '0';
end if;
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal dSDA : std_logic;
signal sta_condition : std_logic;
signal sto_condition : std_logic;
signal ibusy : std_logic;
begin
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
det_sta_sto: process(clk)
begin
if (clk'event and clk = '1') then
dSDA <= sSDA; -- generate a delayed version of sSDA
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end process det_sta_sto;
-- generate bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
-- assign output
busy <= ibusy;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, state, cmd)
variable nxt_state : cmds;
variable icmd_ack, store_sda : std_logic;
variable itxd : std_logic;
begin
nxt_state := state;
icmd_ack := '0'; -- default no acknowledge
store_sda := '0';
itxd := txd;
case (state) is
-- idle
when idle =>
case cmd is
when CMD_START =>
nxt_state := start_a;
icmd_ack := '1'; -- command completed
when CMD_STOP =>
nxt_state := stop_a;
icmd_ack := '1'; -- command completed
when CMD_WRITE =>
nxt_state := wr_a;
icmd_ack := '1'; -- command completed
itxd := Din;
when CMD_READ =>
nxt_state := rd_a;
icmd_ack := '1'; -- command completed
when others =>
nxt_state := idle;
-- don't acknowledge NOP command icmd_ack := '1'; -- command completed
end case;
-- start
when start_a =>
nxt_state := start_b;
when start_b =>
nxt_state := start_c;
when start_c =>
nxt_state := start_d;
when start_d =>
nxt_state := idle;
-- stop
when stop_a =>
nxt_state := stop_b;
when stop_b =>
nxt_state := stop_c;
when stop_c =>
nxt_state := idle;
-- read
when rd_a =>
nxt_state := rd_b;
when rd_b =>
nxt_state := rd_c;
when rd_c =>
nxt_state := rd_d;
store_sda := '1';
when rd_d =>
nxt_state := idle;
-- write
when wr_a =>
nxt_state := wr_b;
when wr_b =>
nxt_state := wr_c;
when wr_c =>
nxt_state := wr_d;
when wr_d =>
nxt_state := idle;
end case;
-- generate regs
if (nReset = '0') then
state <= idle;
cmd_ack <= '0';
txd <= '0';
Dout <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
state <= idle;
cmd_ack <= '0';
txd <= '0';
Dout <= '0';
else
if (clk_en = '1') then
state <= nxt_state;
txd <= itxd;
if (store_sda = '1') then
Dout <= sSDA;
end if;
end if;
cmd_ack <= icmd_ack and clk_en;
end if;
end if;
end process nxt_state_decoder;
--
-- convert states to SCL and SDA signals
--
output_decoder: process (clk, nReset, state)
variable iscl, isda : std_logic;
begin
case (state) is
when idle =>
iscl := SCLo; -- keep SCL in same state
isda := sSDA; -- keep SDA in same state
-- start
when start_a =>
iscl := SCLo; -- keep SCL in same state (for repeated start)
isda := '1'; -- set SDA high
when start_b =>
iscl := '1'; -- set SCL high
isda := '1'; -- keep SDA high
when start_c =>
iscl := '1'; -- keep SCL high
isda := '0'; -- sel SDA low
when start_d =>
iscl := '0'; -- set SCL low
isda := '0'; -- keep SDA low
-- stop
when stop_a =>
iscl := '0'; -- keep SCL disabled
isda := '0'; -- set SDA low
when stop_b =>
iscl := '1'; -- set SCL high
isda := '0'; -- keep SDA low
when stop_c =>
iscl := '1'; -- keep SCL high
isda := '1'; -- set SDA high
-- write
when wr_a =>
iscl := '0'; -- keep SCL low
isda := Din;
when wr_b =>
iscl := '1'; -- set SCL high
isda := Din;
when wr_c =>
iscl := '1'; -- keep SCL high
isda := Din;
when wr_d =>
iscl := '0'; -- set SCL low
isda := Din;
-- read
when rd_a =>
iscl := '0'; -- keep SCL low
isda := '1'; -- tri-state SDA
when rd_b =>
iscl := '1'; -- set SCL high
isda := '1'; -- tri-state SDA
when rd_c =>
iscl := '1'; -- keep SCL high
isda := '1'; -- tri-state SDA
when rd_d =>
iscl := '0'; -- set SCL low
isda := '1'; -- tri-state SDA
end case;
-- generate registers
if (nReset = '0') then
SCLo <= '1';
SDAo <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
SCLo <= '1';
SDAo <= '1';
else
if (clk_en = '1') then
SCLo <= iscl;
SDAo <= isda;
end if;
end if;
end if;
end process output_decoder;
-- assign outputs
SCLout <= SCLo;
SDAout <= SDAo;
end architecture structural;
| lgpl-2.1 | ea05923b1c87d5b12a902a159e808cd5 | 0.567457 | 2.923019 | false | false | false | false |
daniw/ecs | vhdl/sw10/calc/tb_calc.vhd | 1 | 5,989 | -------------------------------------------------------------------------------
-- Entity: Tb_Calc
-- Author: Waj
-- Date : 15-May-11, 13-May-12, 14-Apr-2013, 14-Apr-2014
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 7)
-- Testbench for "Taschenrechner".
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Tb_Calc is
generic(
CLK_FRQ : integer := 50_000 -- use 50 kHz instead of 50 MHz for simulation
-- in order to cut simulation time (only
-- 1/1000 clock events are generated per second)
);
end Tb_Calc;
architecture TB of Tb_Calc is
component Calc is
generic(
CLK_FRQ : integer := CLK_FRQ
);
port(
rst : in std_ulogic; -- BTN_SOUTH
clk : in std_ulogic;
ROT_C : in std_ulogic;
BTN_EAST : in std_ulogic;
BTN_WEST : in std_ulogic;
BTN_NORTH : in std_ulogic;
SW : in std_ulogic_vector(3 downto 0);
LED : out std_ulogic_vector(7 downto 0)
);
end component Calc;
signal rst : std_ulogic := '1';
signal clk : std_ulogic := '0';
signal ROT_C : std_ulogic := '0';
signal BTN_EAST : std_ulogic := '0';
signal BTN_WEST : std_ulogic := '0';
signal BTN_NORTH: std_ulogic := '0';
signal SW : std_ulogic_vector(3 downto 0) := (others => '0');
signal LED : std_ulogic_vector(7 downto 0);
constant opA_add : integer range -8 to 7 := -7;
constant opB_add : integer range -8 to 7 := 7;
constant opA_sub : integer range -8 to 7 := -8;
constant opB_sub : integer range -8 to 7 := -7;
constant opA_mul : integer range -8 to 7 := -8;
constant opB_mul : integer range -8 to 7 := 5;
begin
-- instantiate MUT
MUT : Calc
port map(
rst => rst,
clk => clk,
ROT_C => ROT_C,
BTN_EAST => BTN_EAST,
BTN_WEST => BTN_WEST,
BTN_NORTH => BTN_NORTH,
SW => SW,
LED => LED
);
-- clock generation
p_clk: process
begin
wait for 1 sec / CLK_FRQ/2;
clk <= not clk;
end process;
-- stimuli generation and response checking
p_stim: process
begin
-- apply stimuli and gather responses between active clock edges
wait until falling_edge(clk);
-- reset generation
wait for 5*( 1 sec / CLK_FRQ); -- 5 clock cycles
rst <= '0';
---------------------------------------------------------------------------
-- test Addition
---------------------------------------------------------------------------
-- provide 1. operand
wait for 5*( 1 sec / CLK_FRQ);
SW <= std_ulogic_vector(to_signed(opA_add,4));
wait for 5*( 1 sec / CLK_FRQ);
ROT_C <= '1', '0' after 2*( 1 sec / CLK_FRQ),
'1' after 5*( 1 sec / CLK_FRQ),
'0' after 7*( 1 sec / CLK_FRQ); -- bouncing
-- check display of operand A in result format
wait for 50*( 1 sec / CLK_FRQ);
assert LED(7 downto 0) = std_ulogic_vector(to_signed(8*opA_add,8))
report "ERROR: Operand A not displayed correctly!" severity failure;
-- wait for blank time to expire
wait for 5000*( 1 sec / CLK_FRQ); -- 5000 clock cycles (100 ms)
-- provide 2. operand
wait for 50*( 1 sec / CLK_FRQ);
SW <= std_ulogic_vector(to_signed(opB_add,4));
wait for 20*( 1 sec / CLK_FRQ);
ROT_C <= '1', '0' after 20*( 1 sec / CLK_FRQ);
-- check display of operand B in result format
wait for 50*( 1 sec / CLK_FRQ);
assert LED(7 downto 0) = std_ulogic_vector(to_signed(2*opB_add,8))
report "ERROR: Operand B not displayed correctly!" severity failure;
-- select operation
wait for 50*( 1 sec / CLK_FRQ);
BTN_WEST <= '1', '0' after 2*( 1 sec / CLK_FRQ),
'1' after 5*( 1 sec / CLK_FRQ),
'0' after 7*( 1 sec / CLK_FRQ); -- bouncing
-- check result of operation
wait for 5 *( 1 sec / CLK_FRQ);
assert LED = std_ulogic_vector(to_signed(2*(4*opA_add+opB_add),8))
report "ERROR: Wrong result of + operation!" severity failure;
---------------------------------------------------------------------------
-- test reset
---------------------------------------------------------------------------
wait for 20*( 1 sec / CLK_FRQ);
-- reset generation
rst <= '1';
wait for 5*( 1 sec / CLK_FRQ); -- 5 clock cycles
rst <= '0';
assert LED = "00000000"
report "ERROR: LED not dark after Reset!" severity failure;
wait for 20*( 1 sec / CLK_FRQ);
---------------------------------------------------------------------------
-- test Subtraction
---------------------------------------------------------------------------
--**** ToDo ****
---------------------------------------------------------------------------
-- test reset
---------------------------------------------------------------------------
wait for 20*( 1 sec / CLK_FRQ);
-- reset generation
rst <= '1';
wait for 5*( 1 sec / CLK_FRQ); -- 5 clock cycles
rst <= '0';
assert LED = "00000000"
report "ERROR: LED not dark after Reset!" severity failure;
wait for 20*( 1 sec / CLK_FRQ);
---------------------------------------------------------------------------
-- test Multiplication
---------------------------------------------------------------------------
--**** ToDo ****
---------------------------------------------------------------------------
-- end of simulation
wait for 20*( 1 sec / CLK_FRQ);
report "OK! Normal end of simulation, no errors found!" severity failure;
end process;
end TB;
| gpl-2.0 | 403bc064f1f6b9c086a3fa2852c47a95 | 0.442144 | 4.26871 | false | false | false | false |
wifidar/wifidar_fpga | src/preamp_config.vhd | 1 | 2,483 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity preamp_config is
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end preamp_config;
architecture Behavioral of preamp_config is
type spi_state is (reset,sending,waiting);
signal curr_state: spi_state;
signal divide_count: integer range 0 to 10;
signal divided_clk: std_logic;
signal spi_count: integer range 0 to 9;
signal spi_clk_sig: std_logic := '0';
begin
clk_div: process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
divided_clk <= '0';
divide_count <= 0;
when sending =>
divided_clk <= '0';
divide_count <= divide_count + 1;
if(divide_count = 10) then
divide_count <= 0;
divided_clk <= '1';
end if;
when waiting =>
end case;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
curr_state <= waiting;
when sending =>
busy <= '1';
if(divided_clk = '1') then
if(spi_count <= 9) then
spi_clk_sig <= not spi_clk_sig;
end if;
if(spi_clk_sig = '1') then
if(spi_count <= 9) then
spi_count <= spi_count + 1;
preamp_done <= '0';
spi_clk_sig <= '0';
else
preamp_done <= '1';
end if;
case spi_count is
when 0 =>
--amp_cs <= '1';
when 1 =>
--amp_cs <= '0';
spi_mosi <= '1';
when 2 =>
spi_mosi <= '0';
when 3 =>
spi_mosi <= '0';
when 4 =>
spi_mosi <= '0';
when 5 =>
spi_mosi <= '0';
when 6 =>
spi_mosi <= '0';
when 7 =>
spi_mosi <= '1';
when 8 =>
spi_mosi <= '0';
when others =>
spi_mosi <= '0';
--amp_cs <= '1';
preamp_done <= '1';
curr_state <= waiting;
spi_clk_sig <= '0';
end case;
end if;
end if;
when waiting =>
spi_clk_sig <= '0';
spi_count <= 0;
spi_mosi <= '0';
busy <= '0';
if(send_data = '1') then
curr_state <= sending;
end if;
end case;
end if;
end process;
spi_sck <= spi_clk_sig;
end Behavioral;
| mit | ae6c07050eaa102edb87ee9a80f9bafd | 0.518325 | 2.995175 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_main_design_tcp.vhd | 1 | 25,082 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_main_design_tcp is
end tb_main_design_tcp;
architecture Behavioral of tb_main_design_tcp is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_checksum : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal udp_rx_valid : std_logic := '0';
signal udp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal udp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal udp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_dst_broadcast : std_logic := '0';
signal udp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_valid_last : std_logic := '0';
signal udp_tx_busy : std_logic := '0';
signal udp_tx_valid : std_logic := '0';
signal udp_tx_data : std_logic_vector(7 downto 0) := (others => '0');
signal udp_tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal udp_tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal udp_tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
signal tcp_rx_data_valid : std_logic := '0';
signal tcp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_hdr_valid : std_logic := '0';
signal tcp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_flag_urg : std_logic := '0';
signal tcp_rx_flag_ack : std_logic := '0';
signal tcp_rx_flag_psh : std_logic := '0';
signal tcp_rx_flag_rst : std_logic := '0';
signal tcp_rx_flag_syn : std_logic := '0';
signal tcp_rx_flag_fin : std_logic := '0';
signal tcp_rx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
signal tcp_tx_busy : std_logic := '0';
signal tcp_tx_data_valid : std_logic := '0';
signal tcp_tx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_tx_hdr_valid : std_logic := '0';
signal tcp_tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_flag_urg : std_logic := '0';
signal tcp_tx_flag_ack : std_logic := '0';
signal tcp_tx_flag_psh : std_logic := '0';
signal tcp_tx_flag_rst : std_logic := '0';
signal tcp_tx_flag_syn : std_logic := '0';
signal tcp_tx_flag_fin : std_logic := '0';
signal tcp_tx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"A0B3CC4CF9EF";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"000000000000";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
constant our_mac : std_logic_vector(47 downto 0) := x"AB_89_67_45_23_02"; -- NOTE this is 02:23:45:67:89:AB
constant our_ip : std_logic_vector(31 downto 0) := x"0A_00_00_0A";
constant our_netmask : std_logic_vector(31 downto 0) := x"00_FF_FF_FF";
component tcp_engine is
port ( clk : in STD_LOGIC;
-- data received over TCP/IP
tcp_rx_data_valid : in std_logic := '0';
tcp_rx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : in std_logic := '0';
tcp_rx_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : in std_logic := '0';
tcp_rx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : in std_logic := '0';
tcp_rx_flag_ack : in std_logic := '0';
tcp_rx_flag_psh : in std_logic := '0';
tcp_rx_flag_rst : in std_logic := '0';
tcp_rx_flag_syn : in std_logic := '0';
tcp_rx_flag_fin : in std_logic := '0';
tcp_rx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TP
tcp_tx_busy : in std_logic := '0';
tcp_tx_data_valid : out std_logic := '0';
tcp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : out std_logic := '0';
tcp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : out std_logic := '0';
tcp_tx_flag_ack : out std_logic := '0';
tcp_tx_flag_psh : out std_logic := '0';
tcp_tx_flag_rst : out std_logic := '0';
tcp_tx_flag_syn : out std_logic := '0';
tcp_tx_flag_fin : out std_logic := '0';
tcp_tx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip
) port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
-- data received over UDP
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
-- data received over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_checksum => tcp_tx_checksum,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
i_tcp_engine: tcp_engine port map (
clk => clk125MHz,
-- data received over TCP/IP
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 86 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 2000 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 87 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= x"02";
when 9 => input_data <= x"23";
when 10 => input_data <= x"45";
when 11 => input_data <= x"67";
when 12 => input_data <= x"89";
when 13 => input_data <= x"ab";
-- Source MAC address
when 14 => input_data <= x"A0";
when 15 => input_data <= x"B3";
--
when 16 => input_data <= x"CC";
when 17 => input_data <= x"4C";
when 18 => input_data <= x"F9";
when 19 => input_data <= x"EF";
-- Ether Type 08:06 << ARP!
when 20 => input_data <= x"08";
when 21 => input_data <= x"00";
------------------------
-- TCP packet
------------------------
-- IP Header
when 22 => input_data <= x"45";
when 23 => input_data <= x"00";
--
when 24 => input_data <= x"00";
when 25 => input_data <= x"34";
when 26 => input_data <= x"23";
when 27 => input_data <= x"93";
when 28 => input_data <= x"40";
when 29 => input_data <= x"00";
when 30 => input_data <= x"80";
when 31 => input_data <= x"06";
--
when 32 => input_data <= x"00";
when 33 => input_data <= x"00";
when 34 => input_data <= x"0a";
when 35 => input_data <= x"00";
when 36 => input_data <= x"00";
when 37 => input_data <= x"01";
when 38 => input_data <= x"0a";
when 39 => input_data <= x"00";
--
when 40 => input_data <= x"00";
when 41 => input_data <= x"0a";
-- TCP Header
when 42 => input_data <= x"c5";
when 43 => input_data <= x"81";
when 44 => input_data <= x"00";
when 45 => input_data <= x"50";
when 46 => input_data <= x"6f";
when 47 => input_data <= x"22";
--
when 48 => input_data <= x"be";
when 49 => input_data <= x"2c";
when 50 => input_data <= x"00";
when 51 => input_data <= x"00";
when 52 => input_data <= x"00";
when 53 => input_data <= x"00";
when 54 => input_data <= x"80";
when 55 => input_data <= x"02";
when 56 => input_data <= x"20";
when 57 => input_data <= x"00";
when 58 => input_data <= x"48";
when 59 => input_data <= x"1F";
when 60 => input_data <= x"00";
when 61 => input_data <= x"00";
when 62 => input_data <= x"02";
when 63 => input_data <= x"04";
when 64 => input_data <= x"05";
when 65 => input_data <= x"b4";
when 66 => input_data <= x"01";
when 67 => input_data <= x"03";
when 68 => input_data <= x"03";
when 69 => input_data <= x"08";
when 70 => input_data <= x"01";
when 71 => input_data <= x"01";
when 72 => input_data <= x"04";
when 73 => input_data <= x"02";
-- Misc padding
when 74 => input_data <= x"FF";
when 75 => input_data <= x"FF";
when 76 => input_data <= x"FF";
when 77 => input_data <= x"FF";
when 78 => input_data <= x"FF";
when 79 => input_data <= x"FF";
when 80 => input_data <= x"FF";
when 81 => input_data <= x"FF";
--- FCS
when 82 => input_data <= x"01";
when 83 => input_data <= x"01";
when 84 => input_data <= x"04";
when 85 => input_data <= x"02";
when 86 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral;
| mit | 87cb74a903de9d25f11bc6c263526610 | 0.433658 | 3.563797 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/bram/hdl/xilinx_one_port_ram_async.vhd | 1 | 9,117 | ---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 19/10/2008
-- File : xilinx_one_port_ram_async.vhd
--
-- Abstract : Xilinx behavioural template for ram
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- For bram
Library UNISIM;
use UNISIM.vcomponents.all;
---------------------------------------------------------------------------
Entity xilinx_one_port_ram_async is
---------------------------------------------------------------------------
generic
(
ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 16
);
port
(
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector( ADDR_WIDTH - 1 downto 0);
din : in std_logic_vector( DATA_WIDTH - 1 downto 0);
dout : out std_logic_vector( DATA_WIDTH - 1 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture xilinx_one_port_ram_async_1 of xilinx_one_port_ram_async is
---------------------------------------------------------------------------
-- type ram_type is array (2**ADDR_WIDTH-1 downto 0)
-- of std_logic_vector( DATA_WIDTH-1 downto 0);
-- signal ram: ram_type;
-- signal addr_reg : std_logic_vector( ADDR_WIDTH-1 downto 0);
begin
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (we='1') then
-- ram(to_integer(unsigned(addr)))<= din;
-- end if;
-- addr_reg <= addr;
-- end if;
-- end process;
-- dout <= ram(to_integer(unsigned(addr_reg)));
-- RAMB16_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Single-Port RAM
-- Xilinx HDL Language Template, version 10.1.3
RAMB16_S18_inst : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => dout, -- 16-bit Data Output
DOP => open, -- 2-bit parity Output
ADDR => addr, -- 10-bit Address Input
CLK => clk, -- Clock
DI => din, -- 16-bit Data Input
DIP => "00", -- 2-bit parity Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => we -- Write Enable Input
);
end architecture xilinx_one_port_ram_async_1;
| lgpl-2.1 | 049a7db72c76f82a00b76327c9e3e0b9 | 0.722496 | 6.415904 | false | false | false | false |
hubmartin/FPGA-LVDS-LCD-Hack | pll.vhd | 1 | 7,854 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
-- Module Version: 5.7
--C:\lscc\diamond\3.4_x64\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 16 -fclkop 200 -fclkop_tol 10.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 5 -fracn 2731
-- Mon Jun 15 19:24:17 2015
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
-- synopsys translate_on
entity pll is
port (
CLKI: in std_logic;
CLKOP: out std_logic);
attribute dont_touch : boolean;
attribute dont_touch of pll : entity is true;
end pll;
architecture Structure of pll is
-- internal signal declarations
signal LOCK: std_logic;
signal CLKOP_t: std_logic;
signal CLKFB_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VLO
port (Z: out std_logic);
end component;
component EHXPLLJ
generic (INTFB_WAKE : in String; DDRST_ENA : in String;
DCRST_ENA : in String; MRST_ENA : in String;
PLLRST_ENA : in String; DPHASE_SOURCE : in String;
STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
OUTDIVIDER_MUXC2 : in String;
OUTDIVIDER_MUXB2 : in String;
OUTDIVIDER_MUXA2 : in String;
PREDIVIDER_MUXD1 : in Integer;
PREDIVIDER_MUXC1 : in Integer;
PREDIVIDER_MUXB1 : in Integer;
PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
PLL_LOCK_MODE : in Integer;
CLKOS_TRIM_DELAY : in Integer;
CLKOS_TRIM_POL : in String;
CLKOP_TRIM_DELAY : in Integer;
CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
FRACN_ENABLE : in String; FEEDBK_PATH : in String;
CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
port (CLKI: in std_logic; CLKFB: in std_logic;
PHASESEL1: in std_logic; PHASESEL0: in std_logic;
PHASEDIR: in std_logic; PHASESTEP: in std_logic;
LOADREG: in std_logic; STDBY: in std_logic;
PLLWAKESYNC: in std_logic; RST: in std_logic;
RESETM: in std_logic; RESETC: in std_logic;
RESETD: in std_logic; ENCLKOP: in std_logic;
ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
ENCLKOS3: in std_logic; PLLCLK: in std_logic;
PLLRST: in std_logic; PLLSTB: in std_logic;
PLLWE: in std_logic; PLLADDR4: in std_logic;
PLLADDR3: in std_logic; PLLADDR2: in std_logic;
PLLADDR1: in std_logic; PLLADDR0: in std_logic;
PLLDATI7: in std_logic; PLLDATI6: in std_logic;
PLLDATI5: in std_logic; PLLDATI4: in std_logic;
PLLDATI3: in std_logic; PLLDATI2: in std_logic;
PLLDATI1: in std_logic; PLLDATI0: in std_logic;
CLKOP: out std_logic; CLKOS: out std_logic;
CLKOS2: out std_logic; CLKOS3: out std_logic;
LOCK: out std_logic; INTLOCK: out std_logic;
REFCLK: out std_logic; CLKINTFB: out std_logic;
DPHSRC: out std_logic; PLLACK: out std_logic;
PLLDATO7: out std_logic; PLLDATO6: out std_logic;
PLLDATO5: out std_logic; PLLDATO4: out std_logic;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic);
end component;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "192.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "16.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "9";
attribute LPF_RESISTOR of PLLInst_0 : label is "8";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLJ
generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 2,
PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 2731,
FRACN_ENABLE=> "ENABLED", OUTDIVIDER_MUXD2=> "DIVD",
PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
CLKOS_DIV=> 1, CLKOP_DIV=> 3, CLKFB_DIV=> 12, CLKI_DIV=> 1,
FEEDBK_PATH=> "INT_DIVA")
port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open, PLLACK=>open,
PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
PLLDATO1=>open, PLLDATO0=>open);
CLKOP <= CLKOP_t;
end Structure;
-- synopsys translate_off
library MACHXO2;
configuration Structure_CON of pll is
for Structure
for all:VLO use entity MACHXO2.VLO(V); end for;
for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
end for;
end Structure_CON;
-- synopsys translate_on
| mit | 793979f0f768f39bf26e61e45f54e3f2 | 0.59893 | 3.642857 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/arp/arp_send_packet.vhd | 1 | 9,146 | -----------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: arp_send_packet.vhd - Behavioral
--
-- Description: Send outbound ARP packets
--
-- When it needs to send a packet packet_req is asserted
--
-- When packet grant is asserted, the data is emitted.
-- Once all data is emitted, packet_req is no longer asserted
--
-- The expectation is that if the interface is running slower than
-- 8x the clock rate (e.g. in 100BaseT mode) then this will stream into
-- a FIFO, which will then be sent out at a slower rate.
--
-- The src hardware address and protocol address will most likely
-- be constants, so it should be a lot smaller than you would expect.
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_send_packet is
Port ( clk : in STD_LOGIC;
-- Interface to the outgoing ARP queue
arp_fifo_empty : in std_logic;
arp_fifo_read : out std_logic := '0';
arp_op_request : in std_logic;
arp_src_hw : in std_logic_vector(47 downto 0);
arp_src_ip : in std_logic_vector(31 downto 0);
arp_tgt_hw : in std_logic_vector(47 downto 0);
arp_tgt_ip : in std_logic_vector(31 downto 0);
-- Interface into the Ethernet TX subsystem
packet_request : out std_logic := '0';
packet_granted : in std_logic := '0';
packet_valid : out std_logic := '0';
packet_data : out std_logic_vector(7 downto 0) := (others =>'0'));
end arp_send_packet;
architecture Behavioral of arp_send_packet is
signal counter : unsigned(7 downto 0) := (others => '0');
begin
generate_fifo_read: process(counter, arp_fifo_empty, packet_granted)
begin
arp_fifo_read <= '0';
-- Read from the FIFO the same cycle that we are granted to use the output data bus.
if counter = 0 and arp_fifo_empty = '0' then
-- As soon as granted, the counter will be incremented,
-- so there will only be a one cycle pulse.
arp_fifo_read <= packet_granted;
end if;
end process;
generate_data: process (clk)
begin
if rising_edge(clk) then
-- Do we need to request the output interface
if counter = x"00" and arp_fifo_empty = '0' then
packet_request <= '1';
end if;
-- Are we in the middle of a packet?
if counter /= x"00" then
counter <= counter + 1;
end if;
-- Have we just been allowed to start sending the packet?
if counter = x"00" and packet_granted = '1' then
counter <= counter + 1;
end if;
-- Note, this uses the current value of counter, not the one assigned above!
case to_integer(counter) is
when 0 => packet_data <= "00000000"; -- We pause at 0 count when idle
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 1 => packet_data <= arp_tgt_hw( 7 downto 0); packet_valid <= '1';
when 2 => packet_data <= arp_tgt_hw(15 downto 8);
when 3 => packet_data <= arp_tgt_hw(23 downto 16);
when 4 => packet_data <= arp_tgt_hw(31 downto 24);
when 5 => packet_data <= arp_tgt_hw(39 downto 32);
when 6 => packet_data <= arp_tgt_hw(47 downto 40);
-- Source MAC address
when 7 => packet_data <= arp_src_hw( 7 downto 0);
when 8 => packet_data <= arp_src_hw(15 downto 8);
when 9 => packet_data <= arp_src_hw(23 downto 16);
when 10 => packet_data <= arp_src_hw(31 downto 24);
when 11 => packet_data <= arp_src_hw(39 downto 32);
when 12 => packet_data <= arp_src_hw(47 downto 40);
------------------------
-- ARP packet
------------------------
when 13 => packet_data <= x"08"; -- Ether Type 08:06 << ARP!
when 14 => packet_data <= x"06";
when 15 => packet_data <= x"00"; -- Media type
when 16 => packet_data <= x"01";
when 17 => packet_data <= x"08"; -- Protocol (IP)
when 18 => packet_data <= x"00";
when 19 => packet_data <= x"06"; -- Hardware address length
when 20 => packet_data <= x"04"; -- Protocol address length
-- Operation
when 21 => packet_data <= x"00";
when 22 => if arp_op_request = '1' then
packet_data <= x"01"; -- request
else
packet_data <= x"02"; -- reply
end if;
-- Source MAC
when 23 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw( 7 downto 0);
end if;
when 24 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw(15 downto 8);
end if;
when 25 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw(23 downto 16);
end if;
when 26 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw(31 downto 24);
end if;
when 27 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw(39 downto 32);
end if;
when 28 => if arp_op_request = '1' then
packet_data <= x"FF";
else
packet_data <= arp_src_hw(47 downto 40);
end if;
-- Source IP
when 29 => packet_data <= arp_src_ip( 7 downto 0);
when 30 => packet_data <= arp_src_ip(15 downto 8);
when 31 => packet_data <= arp_src_ip(23 downto 16);
when 32 => packet_data <= arp_src_ip(31 downto 24);
-- Target MAC
when 33 => packet_data <= arp_tgt_hw( 7 downto 0);
when 34 => packet_data <= arp_tgt_hw(15 downto 8);
when 35 => packet_data <= arp_tgt_hw(23 downto 16);
when 36 => packet_data <= arp_tgt_hw(31 downto 24);
when 37 => packet_data <= arp_tgt_hw(39 downto 32);
when 38 => packet_data <= arp_tgt_hw(47 downto 40);
-- Target IP
when 39 => packet_data <= arp_tgt_ip( 7 downto 0);
when 40 => packet_data <= arp_tgt_ip(15 downto 8);
when 41 => packet_data <= arp_tgt_ip(23 downto 16);
when 42 => packet_data <= arp_tgt_ip(31 downto 24);
-- Padding
when 43 => packet_data <= x"00";
when 44 => packet_data <= x"00";
when 45 => packet_data <= x"00";
when 46 => packet_data <= x"00";
when 47 => packet_data <= x"00";
when 48 => packet_data <= x"00";
when 49 => packet_data <= x"00";
when 50 => packet_data <= x"00";
when 51 => packet_data <= x"00";
when 52 => packet_data <= x"00";
when 53 => packet_data <= x"00";
when 54 => packet_data <= x"00";
when 55 => packet_data <= x"00";
when 56 => packet_data <= x"00";
when 57 => packet_data <= x"00";
when 58 => packet_data <= x"00";
when 59 => packet_data <= x"00";
when 60 => packet_data <= x"00";
-- We can release the bus now and go back to the idle state.
when 61 => counter <= (others => '0'); packet_valid <= '0'; packet_request <= '0';
when others => NULL;
end case;
end if;
end process;
end Behavioral; | mit | 233dfeb91e95e71e18371b1a3133079e | 0.537175 | 3.780901 | false | false | false | false |
freecores/hilbert_transformer | vhdl/real_pole_filter_shift_reg.vhd | 1 | 3,192 | -- This filter produces a pole pair at +/-zp=sqrt(2^-shift_value) on the real axis
-- A shift register is used instead of a multiplier
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package real_pole_filter_shift_reg_pkg is
component real_pole_filter_shift_reg
generic(
data_width : integer;
internal_data_width : integer;
shift_value : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end real_pole_filter_shift_reg_pkg;
package body real_pole_filter_shift_reg_pkg is
end real_pole_filter_shift_reg_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.resize_tools_pkg.all;
entity real_pole_filter_shift_reg is
generic(
data_width : integer := 16;
internal_data_width : integer := 16;
shift_value : integer := 1
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end real_pole_filter_shift_reg;
architecture real_pole_filter_shift_reg_arch of real_pole_filter_shift_reg is
signal x_res : std_logic_vector(internal_data_width-1 downto 0);
signal xaydmb0 : std_logic_vector(internal_data_width-1 downto 0);
signal ydmb0 : std_logic_vector(internal_data_width-1 downto 0);
signal y : std_logic_vector (internal_data_width-1 downto 0);
signal yd : std_logic_vector (internal_data_width-1 downto 0);
begin
x_res <= resize_to_msb_round(data_i,internal_data_width);
xaydmb0 <= resize_to_msb_round(std_logic_vector(signed(x_res) + signed(ydmb0)),internal_data_width);
ydmb0 <= resize_to_msb_round(std_logic_vector(shift_right(signed(yd),shift_value)),internal_data_width);
process (clk_i, rst_i)
begin
if rst_i = '1' then
y <= (others => '0');
yd <= (others => '0');
data_str_o <= '0';
data_o <= (others => '0');
elsif clk_i'EVENT and clk_i = '1' then
data_str_o <= data_str_i;
data_o <= y;
if data_str_i='1' then
y <= xaydmb0;
yd <= y;
end if;
end if;
end process;
end real_pole_filter_shift_reg_arch;
| gpl-3.0 | b8d71154567d75e955706759dbe5361e | 0.672932 | 2.977612 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/elsif_eliminator_test.vhd | 1 | 1,008 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fooProc : process is
variable baz : natural := 4711;
begin
-- without else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
end if;
-- with else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
else
baz := 100000;
end if;
end process fooProc;
end beh;
| gpl-3.0 | aef1699186611d6700cfb06d5fc23100 | 0.505952 | 3.337748 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/irq_mngr/hdl/irq_mngr.vhd | 1 | 5,374 | -------------------------------------------------------------------------------
--
-- File : irq_mnrg.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : Wishbone Interruption Manager
--
-- Creation Date : 2007/01/05
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
-- 20/10/2008 : Detected rising edge instead of high state
-- Fabien Marteau <fabien.marteau@armadeus.com>
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
Entity irq_mngr is
-- ----------------------------------------------------------------------------
generic
(
id : natural := 0;
irq_count : integer := 16; -- always 16 default
irq_level : std_logic := '1'
);
port
(
-- Global Signals
gls_clk : in std_logic;
gls_reset : in std_logic;
-- Wishbone interface signals
wbs_s1_address : in std_logic_vector(1 downto 0); -- Address bus
wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
wbs_s1_ack : out std_logic; -- Access acknowledge
wbs_s1_strobe : in std_logic; -- Strobe
wbs_s1_cycle : in std_logic ; -- Cycle
wbs_s1_write : in std_logic; -- Write access
-- irq from other IP
irqport : in std_logic_vector(irq_count-1 downto 0);
-- Component external signals
gls_irq : out std_logic -- IRQ request
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of irq_mngr is
-- ----------------------------------------------------------------------------
signal irq_r : std_logic_vector(irq_count-1 downto 0);
signal irq_old : std_logic_vector(irq_count-1 downto 0);
signal irq_pend : std_logic_vector(irq_count-1 downto 0);
signal irq_ack : std_logic_vector(irq_count-1 downto 0);
signal irq_mask : std_logic_vector(irq_count-1 downto 0);
signal readdata : std_logic_vector(15 downto 0);
signal rd_ack : std_logic;
signal wr_ack : std_logic;
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
irq_r <= (others => '0');
irq_old <= (others => '0');
elsif(rising_edge(gls_clk)) then
irq_r <= irqport;
irq_old <= irq_r;
end if;
end process;
-- ----------------------------------------------------------------------------
-- Interruption requests latching process on rising edge
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
irq_pend <= (others => '0');
elsif(rising_edge(gls_clk)) then
irq_pend <= (irq_pend or ((irq_r and (not irq_old))and irq_mask)) and (not irq_ack);
end if;
end process;
-- ----------------------------------------------------------------------------
-- Register reading process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
rd_ack <= '0';
readdata <= (others => '0');
elsif(rising_edge(gls_clk)) then
rd_ack <= '0';
if(wbs_s1_strobe = '1' and wbs_s1_write = '0' and wbs_s1_cycle = '1') then
rd_ack <= '1';
if(wbs_s1_address = "00") then
readdata(irq_count-1 downto 0) <= irq_mask;
elsif(wbs_s1_address="01") then
readdata(irq_count-1 downto 0) <= irq_pend;
elsif(wbs_s1_address="10") then
readdata <= std_logic_vector(to_unsigned(id,16));
else
readdata <= (others => '0');
end if;
end if;
end if;
end process;
-- ----------------------------------------------------------------------------
-- Register update process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
irq_ack <= (others => '0');
wr_ack <= '0';
irq_mask <= (others => '0');
elsif(rising_edge(gls_clk)) then
irq_ack <= (others => '0');
wr_ack <= '0';
if(wbs_s1_strobe = '1' and wbs_s1_write = '1' and wbs_s1_cycle = '1') then
wr_ack <= '1';
if(wbs_s1_address = "00") then
irq_mask <= wbs_s1_writedata(irq_count-1 downto 0);
elsif(wbs_s1_address = "01") then
irq_ack <= wbs_s1_writedata(irq_count-1 downto 0);
end if;
end if;
end if;
end process;
gls_irq <= irq_level when(unsigned(irq_pend) /= 0 and gls_reset = '0') else
not irq_level;
wbs_s1_ack <= rd_ack or wr_ack;
wbs_s1_readdata <= readdata when (wbs_s1_strobe = '1' and wbs_s1_write = '0' and wbs_s1_cycle = '1') else (others => '0');
end architecture RTL;
| lgpl-2.1 | 9e30e221b824ae37135cf9986522d3fd | 0.450316 | 3.891383 | false | false | false | false |
B-George/ECEGR_4220_MIPS_PROC | Mips_Proc.vhd | 1 | 9,097 | -----------------------------------------------------------------------------------
--Begin Mips_Proc
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY Mips_Proc IS
PORT( clk_50 : IN STD_LOGIC; -- 50 MHz Clock in
clk : BUFFER STD_LOGIC; -- 1 Hz Clock out
clk_tmp : IN STD_LOGIC;
ledG8 : OUT STD_LOGIC; -- Clock display
ledR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- Red LEDs, displays instruction at current address
sw : IN STD_LOGIC_VECTOR(17 DOWNTO 0); -- switches 0-17
sevD0, sevD1, sevD2, sevD3,
sevD4, sevD5, sevD6, sevD7
: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- 7-segment digits 0-7
-- sram access
sram_addr : BUFFER STD_LOGIC_VECTOR(19 DOWNTO 0);
sram_dq : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sram_we, sram_ce, sram_oe, sram_lb, sram_ub
: OUT STD_LOGIC);
END Mips_Proc;
ARCHITECTURE behavior OF Mips_Proc IS
-- signals & variables
-- these are for dealing with instruction memory
SIGNAL PC : STD_LOGIC_VECTOR(19 DOWNTO 0) := X"00000"; -- Program counter
SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); -- for output to 7seg display
SIGNAL instruction : STD_LOGIC_VECTOR(31 DOWNTO 0); -- complete instruction input to 32-bit register
SIGNAL inst32 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- complete instruction output from 32-bit register
SIGNAL output_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000"; -- display sram data on red LEDs
SIGNAL dMDi : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DataMemdatain
SIGNAL dMDo : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DataMemdataout
SIGNAL dMAd : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DataMemAddr
SIGNAL dMRd : STD_LOGIC; -- DataMemRead
SIGNAL dMWr : STD_LOGIC; -- DataMemWrite .
SIGNAL procClk : STD_LOGIC; -- clock for processor
SHARED VARIABLE regEnable : STD_LOGIC := '0'; -- toggle write enable for processor registers
SIGNAL sram_wein : STD_LOGIC := '1'; -- toggle write enable for SRAM
-- variables for LW and SW ops
SHARED VARIABLE dMRdTmp : STD_LOGIC;
SHARED VARIABLE dMWrTmp : STD_LOGIC;
SIGNAL displayVector : STD_LOGIC_VECTOR(31 DOWNTO 0); -- vector for 7-segment display
TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6); -- typedef and signals for state machine
SIGNAL current_state, next_state : STATE_TYPE;
SIGNAL inst_we: STD_LOGIC;
SIGNAL data_SRAM :STD_LOGIC_VECTOR(31 DOWNTO 0);
-- components
COMPONENT clock
GENERIC(n: INTEGER := 50*(10**6));
PORT( clk_in_50MHz: IN STD_LOGIC;
clk_out : BUFFER STD_LOGIC);
END COMPONENT clock;
COMPONENT sev_seg_drv
PORT( seven_input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
seven_output: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT sev_seg_drv;
COMPONENT register16
PORT( datain : IN STD_LOGIC_vector(15 DOWNTO 0);
enout16, enout8 : IN STD_LOGIC;
writein16, writein8 : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(15 DOWNTO 0));
END COMPONENT register16;
COMPONENT register32
PORT( datain : IN STD_LOGIC_vector(31 DOWNTO 0);
enout32,enout16,enout8 : IN STD_LOGIC;
writein32, writein16,writein8 : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0));
END COMPONENT register32;
COMPONENT Processor
PORT( instruction : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemdatain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemdataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemAddr : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemRead : OUT STD_LOGIC;
DataMemWrite : OUT STD_LOGIC;
clock : IN STD_LOGIC);
END COMPONENT Processor;
-- Begin logic for Mips_Proc
BEGIN
ledG8 <= clk;
sram_we <= sram_wein;
sram_ce <= '0';
sram_oe <= '0';
sram_lb <= '0';
sram_ub <= '0';
output_1 <= sram_dq;
ledR(15 DOWNTO 0) <= output_1;
-- port map components
ck : clock PORT MAP(clk_50, clk); -- system clock
inst : register32 PORT MAP(instruction(31 DOWNTO 0), '0','0','0',inst_we,'0','0', inst32(31 DOWNTO 0)); -- instruction register
proc : processor PORT MAP(inst32(31 DOWNTO 0),dMDI(31 DOWNTO 0),dMDo(31 DOWNTO 0), -- processor
dMAd(31 DOWNTO 0),dMRd, dMWr, procClk); -- processor
-- seven segment display
digit0 : sev_seg_drv PORT MAP(displayVector(3 DOWNTO 0),sevD0);
digit1 : sev_seg_drv PORT MAP(displayVector(7 DOWNTO 4),sevD1);
digit2 : sev_seg_drv PORT MAP(displayVector(11 DOWNTO 8),sevD2);
digit3 : sev_seg_drv PORT MAP(displayVector(15 DOWNTO 12),sevD3);
digit4 : sev_seg_drv PORT MAP(displayVector(19 DOWNTO 16),sevD4);
digit5 : sev_seg_drv PORT MAP(displayVector(23 DOWNTO 20),sevD5);
digit6 : sev_seg_drv PORT MAP(displayVector(27 DOWNTO 24),sevD6);
digit7 : sev_seg_drv PORT MAP(displayVector(31 DOWNTO 28),sevD7);
--sev_seg_drv switching --
WITH sw(17 DOWNTO 15) SELECT
displayVector <= X"EEEE" & sram_dq WHEN "000",
address WHEN "001",
instruction WHEN "010",
dMDo WHEN "011",
dMAd WHEN "100",
dMDi WHEN "101",
X"EEE" & sram_addr WHEN "110",
X"EEE" & PC WHEN "111",
X"FFFFFFFF" WHEN OTHERS;
-- state machine
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk = '1' AND sw(0) = '1') THEN
CASE current_state IS
WHEN s0=> -- load program counter to address
sram_addr <= PC;
current_state <= s1;
address <= X"EEEEEEE1";
WHEN s1=> -- push lower half of instruction to register, increment sram address
instruction(15 DOWNTO 0) <= sram_dq;
sram_addr <= sram_addr + 1;
current_state <= s2;
address <= X"EEEEEEE2";
WHEN s2=> -- push upper half of instruction to register, increment PC, enable processor register write
instruction(31 DOWNTO 16) <= sram_dq;
PC <= PC + 2;
inst_we <= '1';
current_state <= s3;
procClk <= '1';
address <= X"EEEEEEE3";
WHEN s3=> -- are we doing LW or SW op?
inst_we <= '0';
IF (dMRd = '1') THEN -- LW, read from SRAM
sram_addr <= dMAd(19 DOWNTO 0);
END IF;
IF (dMWr = '1') THEN -- SW, write to SRAM
sram_wein <= '1';
sram_addr <= dMAd(19 DOWNTO 0);
END IF;
current_state <= s4;
procClk <= '0';
address <= X"EEEEEEE4";
WHEN s4=>
IF (dMRd = '1') THEN -- read from SRAM
dMDi(15 DOWNTO 0) <= sram_dq;
sram_addr <= sram_addr + 1;
END IF;
IF (dMWr = '1') THEN -- write to SRAM
sram_dq <= dMDo(15 DOWNTO 0);
sram_addr <= sram_addr + 1;
END IF;
current_state <= s5;
address <= X"EEEEEEE5";
WHEN s5=>
IF (dMRd = '1') THEN
dMDi(31 DOWNTO 16) <= sram_dq;
END IF;
IF (dMWr = '1') THEN -- write to SRAM
sram_dq <= dMDo(31 DOWNTO 16);
sram_addr <= PC;
END IF;
current_state <= s6;
address <= X"EEEEEEE6";
WHEN s6=>
IF (dMRd = '1') THEN
dMDi <= data_SRAM;
sram_addr <= PC;
END IF;
current_state <= s0;
address <= X"EEEEEEE0";
END CASE;
END IF;
END PROCESS;
END behavior;
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-- Begin Clock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY clock IS
GENERIC(n : INTEGER := 25*(10**6));
PORT(clk_in_50MHz : IN STD_LOGIC;
clk_out : BUFFER STD_LOGIC := '0');
END clock;
ARCHITECTURE behavior OF clock IS
--SIGNAL ASSIGNMENTS
--Creates a SIGNAL with a frequency of 1/(2n) of clock_in_50MHz
--set n = 10**7 for an input clock frequency of 25MHz
SIGNAL count : integer range 0 to n; --n IS half the period
BEGIN
--Takes 50MHz clock input, reduces to 1/(2n) for system clock
PROCESS (clk_in_50MHz)
BEGIN
IF (clk_in_50MHz'event AND clk_in_50MHz = '1') THEN
count <= count + 1;
IF (count = n-1) THEN
clk_out <= NOT clk_out;
count <= 0;
END IF;
END IF;
END PROCESS;
END behavior;
-- End Clock
----------------------------------------------------------------------------
-- Begin seven segment driver
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY sev_seg_drv IS
PORT( -- The hex value to be displayed
seven_input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- The seven segment display code.
seven_output : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY sev_seg_drv;
ARCHITECTURE behavior OF sev_seg_drv IS
BEGIN
WITH seven_input SELECT seven_output <=
"1000000" WHEN x"0", -- '0'
"1111001" WHEN x"1", -- '1'
"0100100" WHEN x"2", -- '2'
"0110000" WHEN x"3", -- '3'
"0011001" WHEN x"4", -- '4'
"0010010" WHEN x"5", -- '5'
"0000010" WHEN x"6", -- '6'
"1111000" WHEN x"7", -- '7'
"0000000" WHEN x"8", -- '8'
"0011000" WHEN x"9", -- '9'
"0001000" WHEN x"A", -- ‘A’
"0000011" WHEN x"B", -- ‘b’
"1000110" WHEN x"C", -- ‘C’
"0100001" WHEN x"D", -- ‘d’
"0000110" WHEN x"E", -- ‘E’
"0001110" WHEN x"F"; -- ‘F’
END behavior;
-- End seven segment driver
-----------------------------------------------------------------------------
-- EOF | mit | e241b6f2e1c3ac1ab9f6af4b1be3efde | 0.614791 | 2.977683 | false | false | false | false |
wifidar/wifidar_fpga | src/spi_arbitrator.vhd | 2 | 2,577 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_arbitrator is
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end spi_arbitrator;
architecture Behavioral of spi_arbitrator is
type arbitration_type is (waiting,adc,amp);
signal curr_state: arbitration_type := waiting;
signal amp_requested: std_logic;
signal adc_requested: std_logic;
signal delay: std_logic;
begin
dac_proc: process(clk,rst)
begin
if(rst = '1') then
dac_send_data <= '0';
elsif(rising_edge(clk)) then
if(dac_ready = '1') then
delay <= '1';
if(delay = '1') then
dac_send_data <= '1';
end if;
else
delay <= '0';
dac_send_data <= '0';
end if;
end if;
end process;
process(clk,rst)
begin
if(rst = '1') then
curr_state <= waiting;
adc_send_data <= '0';
amp_send_data <= '0';
elsif(rising_edge(clk)) then
if(spi_controller_busy = '1') then
adc_send_data <= '0';
amp_send_data <= '0';
curr_state <= waiting;
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
else
case curr_state is
when waiting =>
AMP_CS <= '1';
--AD_CONV <= '0';
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
if(amp_requested = '1') then
curr_state <= amp;
amp_requested <= '0';
elsif(adc_requested = '1') then
curr_state <= adc;
adc_requested <= '0';
end if;
when adc =>
AMP_CS <= '1';
--AD_CONV <= '1';
adc_send_data <= '1';
when amp =>
AMP_CS <= '0';
--AD_CONV <= '0';
amp_send_data <= '1';
when others =>
end case;
end if;
end if;
end process;
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
AMP_SHDN <= '0';
end Behavioral;
| mit | e58504f12631f3bb47bd07f6dc252a2f | 0.56655 | 2.732768 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/tb_mcu.vhd | 2 | 928 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal GPIO_0 : std_logic_vector(DW-1 downto 0);
signal GPIO_1 : std_logic_vector(DW-1 downto 0);
signal GPIO_2 : std_logic_vector(DW-1 downto 0);
signal GPIO_3 : std_logic_vector(DW-1 downto 0);
signal LCD : std_logic_vector(LCD_PW-1 downto 0);
begin
-- instantiate MUT
MUT : entity work.mcu
port map(
rst => rst,
clk => clk,
GPIO_0 => GPIO_0,
GPIO_1 => GPIO_1,
GPIO_2 => GPIO_2,
GPIO_3 => GPIO_3,
LCD => LCD
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / CF/2;
clk <= not clk;
end process;
end TB;
| gpl-2.0 | 3c2b94352e96e3f1e300551597853188 | 0.559267 | 3.072848 | false | false | false | false |
xcthulhu/periphondemand | src/library/syscons/rstext_syscon/hdl/rstext_syscon.vhd | 1 | 1,460 | ---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 20/07/2008
-- File : rstext_syscon.vhd
--
-- Abstract : wishbone syscon with external reset
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity rstext_syscon is
---------------------------------------------------------------------------
generic(
invert_reset : std_logic := '0' -- 0 : not invert, 1: invert
);
port
(
-- external signals
ext_clk : in std_logic ;
ext_rst_n : in std_logic ;
--internal signals
gls_clk : out std_logic ;
gls_reset : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture rstext_syscon_1 of rstext_syscon is
---------------------------------------------------------------------------
signal rff1 : std_logic ;
begin
gls_clk <= ext_clk;
reset_synchroniser : process (ext_clk,ext_rst_n)
begin
if ext_rst_n = not invert_reset then
rff1 <= '1';
gls_reset <= '1';
elsif rising_edge(ext_clk) then
rff1 <= '0';
gls_reset <= rff1;
end if;
end process reset_synchroniser;
end architecture rstext_syscon_1;
| lgpl-2.1 | be7378352a85456f0e234dadb724e682 | 0.417808 | 4.492308 | false | false | false | false |
Subsets and Splits