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alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.ip_user_files/bd/design_1/ip/design_1_FIR_0/sim/design_1_FIR_0.vhd | 2 | 10,372 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END design_1_FIR_0;
ARCHITECTURE design_1_FIR_0_arch OF design_1_FIR_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_0",
C_COEF_FILE => "design_1_FIR_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 24,
C_OUTPUT_PATH_WIDTHS => "24",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_0_arch;
| mit | e649342f27c2a5b2b2f493582fbd8940 | 0.632183 | 3.263688 | false | true | false | false |
VLSI-EDA/PoC-Examples | src/common/my_config_ArtyA7_35.vhdl | 1 | 1,585 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Digilent ArtyA7-35 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ArtyA7-35"; -- Digilent ArtyA7-35 - Xilinx Artix-7: XC7A35T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| apache-2.0 | 001fe2e4fefb7f12a3a40639bee2405f | 0.570978 | 4.439776 | false | true | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/ULA/XOR_BitABit.vhd | 1 | 716 | ----------------------------------------------------------------------------------
-- Create Date: 21:52:35 04/10/2017
-- Module Name: XOR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end XOR_BitABit;
architecture Behavioral of XOR_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) XOR B(0);
Zout(1) <= A(1) XOR B(1);
Zout(2) <= A(2) XOR B(2);
Zout(3) <= A(3) XOR B(3);
Z <= Zout;
end Behavioral;
| gpl-3.0 | 71254683ed5f13228542413edb217752 | 0.47067 | 3.442308 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/Decoder3x8.vhd | 1 | 1,442 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/29/2017 11:06:31 AM
-- Design Name:
-- Module Name: Decoder2x4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder3x8 is Port ( D_IN : in STD_LOGIC_VECTOR(3 downto 0);
nD_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end Decoder3x8;
architecture Behavioral of Decoder3x8 is begin
process (D_IN) begin
case D_IN is
when "000" => nD_OUT <= "11111110";
when "001" => nD_OUT <= "11111101";
when "010" => nD_OUT <= "11111011";
when "011" => nD_OUT <= "11110111";
when "100" => nD_OUT <= "11101111";
when "101" => nD_OUT <= "11011111";
when "110" => nD_OUT <= "10111111";
when "111" => nD_OUT <= "01111111";
when others => nD_OUT <= "00000000";
end case;
end process;
end Behavioral;
| mit | 0511bdaf9fa7d5c01d4b126d67114e1b | 0.568655 | 3.392941 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/MultBcd_5Dig.vhd | 2 | 5,364 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_5x5Dig IS
PORT (
EntradaA : IN unsigned (19 DOWNTO 0); -- Entrada1 com 5 digitos BCD
EntradaB : IN unsigned (19 DOWNTO 0); -- Entrada2 com 5 digitos BCD
SaidaZ : OUT unsigned (39 DOWNTO 0) -- Saída com 10 digitos BCD
);
END MultBcd_5x5Dig;
ARCHITECTURE Behavioral OF MultBcd_5x5Dig IS
COMPONENT MultBcd_1xNDig -- Multiplicador de 1 digito por N
PORT (
A : IN unsigned(3 DOWNTO 0);
B : IN unsigned(19 DOWNTO 0);
Z : OUT unsigned(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT Adder IS -- Somador para produtos parciais
PORT (
CarryIn : IN unsigned (3 DOWNTO 0);
Entrada1 : IN unsigned (3 DOWNTO 0);
Entrada2 : IN unsigned (3 DOWNTO 0);
Entrada3 : IN unsigned (3 DOWNTO 0);
Entrada4 : IN unsigned (3 DOWNTO 0);
Entrada5 : IN unsigned (3 DOWNTO 0);
Saida : OUT unsigned (3 DOWNTO 0);
CarryOut : OUT unsigned (3 DOWNTO 0)
);
END COMPONENT;
SIGNAL ProdParcial0 : unsigned(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL ProdParcial1 : unsigned(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL ProdParcial2 : unsigned(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL ProdParcial3 : unsigned(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL ProdParcial4 : unsigned(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL carryAux : unsigned(35 DOWNTO 0) := (OTHERS => '0');
SIGNAL SaidaAux : unsigned(39 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Calculo das multiplicações parciais
MULT0 : MultBcd_1xNDig -- A(1) x B
PORT MAP(
A => EntradaA(3 DOWNTO 0),
B => EntradaB,
Z => ProdParcial0
);
MULT1 : MultBcd_1xNDig -- A(2) x B
PORT MAP(
A => EntradaA(7 DOWNTO 4),
B => EntradaB,
Z => ProdParcial1
);
MULT2 : MultBcd_1xNDig -- A(3) x B
PORT MAP(
A => EntradaA(11 DOWNTO 8),
B => EntradaB,
Z => ProdParcial2
);
MULT3 : MultBcd_1xNDig -- A(4) x B
PORT MAP(
A => EntradaA(15 DOWNTO 12),
B => EntradaB,
Z => ProdParcial3
);
MULT4 : MultBcd_1xNDig -- A(5) x B
PORT MAP(
A => EntradaA(19 DOWNTO 16),
B => EntradaB,
Z => ProdParcial4
);
-- ------ Calculo das Somas parciais
SaidaAux(3 DOWNTO 0) <= ProdParcial0(3 DOWNTO 0);
adder0 : Adder
PORT MAP(
CarryIn => "0000",
Entrada1 => ProdParcial0(7 DOWNTO 4),
Entrada2 => ProdParcial1(3 DOWNTO 0),
Entrada3 => "0000",
Entrada4 => "0000",
Entrada5 => "0000",
Saida => SaidaAux(7 DOWNTO 4),
CarryOut => carryAux(3 DOWNTO 0)
);
adder1 : Adder
PORT MAP(
CarryIn => carryAux(3 DOWNTO 0),
Entrada1 => ProdParcial0(11 DOWNTO 8),
Entrada2 => ProdParcial1(7 DOWNTO 4),
Entrada3 => ProdParcial2(3 DOWNTO 0),
Entrada4 => "0000",
Entrada5 => "0000",
Saida => SaidaAux(11 DOWNTO 8),
CarryOut => carryAux(7 DOWNTO 4)
);
adder2 : Adder
PORT MAP(
CarryIn => carryAux(7 DOWNTO 4),
Entrada1 => ProdParcial0(15 DOWNTO 12),
Entrada2 => ProdParcial1(11 DOWNTO 8),
Entrada3 => ProdParcial2(7 DOWNTO 4),
Entrada4 => ProdParcial3(3 DOWNTO 0),
Entrada5 => "0000",
Saida => SaidaAux(15 DOWNTO 12),
CarryOut => carryAux(11 DOWNTO 8)
);
adder3 : Adder
PORT MAP(
CarryIn => carryAux(11 DOWNTO 8),
Entrada1 => ProdParcial0(19 DOWNTO 16),
Entrada2 => ProdParcial1(15 DOWNTO 12),
Entrada3 => ProdParcial2(11 DOWNTO 8),
Entrada4 => ProdParcial3(7 DOWNTO 4),
Entrada5 => ProdParcial4(3 DOWNTO 0),
Saida => SaidaAux(19 DOWNTO 16),
CarryOut => carryAux(15 DOWNTO 12));
adder4 : Adder
PORT MAP(
CarryIn => carryAux(15 DOWNTO 12),
Entrada1 => ProdParcial0(23 DOWNTO 20),
Entrada2 => ProdParcial1(19 DOWNTO 16),
Entrada3 => ProdParcial2(15 DOWNTO 12),
Entrada4 => ProdParcial3(11 DOWNTO 8),
Entrada5 => ProdParcial4(7 DOWNTO 4),
Saida => SaidaAux(23 DOWNTO 20),
CarryOut => carryAux(19 DOWNTO 16));
adder5 : Adder
PORT MAP(
CarryIn => carryAux(19 DOWNTO 16),
Entrada1 => "0000",
Entrada2 => ProdParcial1(23 DOWNTO 20),
Entrada3 => ProdParcial2(19 DOWNTO 16),
Entrada4 => ProdParcial3(15 DOWNTO 12),
Entrada5 => ProdParcial4(11 DOWNTO 8),
Saida => SaidaAux(27 DOWNTO 24),
CarryOut => carryAux(23 DOWNTO 20));
adder6 : Adder
PORT MAP(
CarryIn => carryAux(23 DOWNTO 20),
Entrada1 => "0000",
Entrada2 => "0000",
Entrada3 => ProdParcial2(23 DOWNTO 20),
Entrada4 => ProdParcial3(19 DOWNTO 16),
Entrada5 => ProdParcial4(15 DOWNTO 12),
Saida => SaidaAux(31 DOWNTO 28),
CarryOut => carryAux(27 DOWNTO 24));
adder7 : Adder
PORT MAP(
CarryIn => carryAux(27 DOWNTO 24),
Entrada1 => "0000",
Entrada2 => "0000",
Entrada3 => "0000",
Entrada4 => ProdParcial3(23 DOWNTO 20),
Entrada5 => ProdParcial4(19 DOWNTO 16),
Saida => SaidaAux(35 DOWNTO 32),
CarryOut => carryAux(31 DOWNTO 28));
adder8 : Adder
PORT MAP(
CarryIn => carryAux(31 DOWNTO 28),
Entrada1 => "0000",
Entrada2 => "0000",
Entrada3 => "0000",
Entrada4 => "0000",
Entrada5 => ProdParcial4(23 DOWNTO 20),
Saida => SaidaAux(39 DOWNTO 36),
CarryOut => carryAux(35 DOWNTO 32)
);
SaidaZ <= SaidaAux;
END Behavioral; | gpl-3.0 | 6dd626757aebbd1106477564a450933e | 0.607755 | 3.22938 | false | false | false | false |
marcoep/MusicBoxNano | hdl/DDSAddressGenerator.vhd | 1 | 6,227 | -------------------------------------------------------------------------------
-- Title : DDS Address Generator
-- Project :
-------------------------------------------------------------------------------
-- File : DDSAddressGenerator.vhd
-- Author : Marco Eppenberger <marco@Pierce.home>
-- Company :
-- Created : 2016-07-30
-- Last update: 2016-07-30
-- Platform : ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generator for DDS and Evelope ROM address.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Marco Eppenberger
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-30 1.0 marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Helpers_Pkg.all;
entity DDSAddressGenerator is
generic (
ENV_DECAY_SPEED : integer := 500; -- 500 is one second for the whole envelope (min 1, max 2^16-1)
DDS_COUNTER_WIDTH : integer := 29); -- min 12
port (
Clk_CI : in std_logic;
Reset_SI : in std_logic;
Increment_DI : in std_logic_vector(DDS_COUNTER_WIDTH-1 downto 0);
IncrementValid_SI : in std_logic;
FreqTick_SI : in std_logic;
DDSAddr_DO : out std_logic_vector(11 downto 0);
EnvAddr_DO : out std_logic_vector(7 downto 0));
end entity DDSAddressGenerator;
architecture RTL of DDSAddressGenerator is
-- the last 1/8th of the wave table is the sustain part
constant SUSTAIN_BEGIN_ADDR : integer := (2**(DDS_COUNTER_WIDTH-3))*7;
-- Envelope Address Generation
signal EnvTickCounter_DN : unsigned(15 downto 0) := (others => '0');
signal EnvTickCounter_DP : unsigned(15 downto 0) := (others => '0');
signal EnvTick_S : std_logic := '0';
signal EnvAddr_DN : unsigned(7 downto 0) := (others => '0');
signal EnvAddr_DP : unsigned(7 downto 0) := (others => '0');
signal EnvelopeDone_S : std_logic := '0';
-- DDS Address Generation
signal DDSAddr_DN, DDSAddr_DP : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0');
signal IncrementBuf_D : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0');
signal SustainFlag_SN, SustainFlag_SP : std_logic := '0';
begin -- architecture RTL
-----------------------------------------------------------------------------
-- DDS (Waveform) Address Generator
-----------------------------------------------------------------------------
-- next DDS addr logic
next_dds_addr : process (DDSAddr_DP, FreqTick_SI, IncrementBuf_D,
IncrementValid_SI, SustainFlag_SP) is
variable addr_tmp : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0');
variable dds_in_sustain : boolean := false;
begin
-- defaults
DDSAddr_DN <= DDSAddr_DP;
SustainFlag_SN <= SustainFlag_SP;
-- add increment to address and check if in sustain region
addr_tmp := DDSAddr_DP + IncrementBuf_D;
dds_in_sustain := addr_tmp >= SUSTAIN_BEGIN_ADDR;
-- get next DDS addr when frequency ticks
if FreqTick_SI = '1' then
if SustainFlag_SP = '1' and not(dds_in_sustain) then
DDSAddr_DN <= addr_tmp + SUSTAIN_BEGIN_ADDR;
else
DDSAddr_DN <= addr_tmp;
end if;
end if;
-- sustain flag is set from 0 to 1 when the address reaches the sustain
-- part the first time
if dds_in_sustain then
SustainFlag_SN <= '1';
end if;
-- reset when we get a new increment
if IncrementValid_SI = '1' then
SustainFlag_SN <= '0';
DDSAddr_DN <= (others => '0');
end if;
end process next_dds_addr;
-- DDS generator flipflop
DDSAddrGen : process (Clk_CI) is
begin -- process DDSAddrGen
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
IncrementBuf_D <= (others => '0');
SustainFlag_SP <= '0';
DDSAddr_DP <= (others => '0');
else
if IncrementValid_SI = '1' then
IncrementBuf_D <= unsigned(Increment_DI);
end if;
SustainFlag_SP <= SustainFlag_SN;
DDSAddr_DP <= DDSAddr_DN;
end if;
end if;
end process DDSAddrGen;
-- output
DDSAddr_DO <= std_logic_vector(DDSAddr_DP(DDS_COUNTER_WIDTH-1 downto DDS_COUNTER_WIDTH-12));
-----------------------------------------------------------------------------
-- Envelope Address Generator
-----------------------------------------------------------------------------
-- envelope tick if counter reaches out of bounds
EnvTick_S <= bool2sl(EnvTickCounter_DP >= ENV_DECAY_SPEED);
-- next tick logic
env_tick : process (EnvTickCounter_DP, EnvTick_S, FreqTick_SI) is
begin
EnvTickCounter_DN <= EnvTickCounter_DP;
if FreqTick_SI = '1' then
if EnvTick_S = '1' then
EnvTickCounter_DN <= (others => '0');
else
EnvTickCounter_DN <= EnvTickCounter_DP + 1;
end if;
end if;
end process env_tick;
-- address done
EnvelopeDone_S <= bool2sl(EnvAddr_DP = 255);
-- next address logic
next_addr_logic : process (EnvAddr_DP, EnvTick_S, EnvelopeDone_S) is
begin
EnvAddr_DN <= EnvAddr_DP;
if EnvTick_S = '1' and EnvelopeDone_S = '0' then
EnvAddr_DN <= EnvAddr_DP + 1;
end if;
end process next_addr_logic;
-- envelope address flipflops, also reset when new increment comes in
EnvAddrGen : process (Clk_CI) is
begin
if Clk_CI'event and Clk_CI = '1' then
if (Reset_SI = '1' or IncrementValid_SI = '1') then
EnvAddr_DP <= (others => '0');
EnvTickCounter_DP <= (others => '0');
else
EnvAddr_DP <= EnvAddr_DN;
EnvTickCounter_DP <= EnvTickCounter_DN;
end if;
end if;
end process EnvAddrGen;
-- output
EnvAddr_DO <= std_logic_vector(EnvAddr_DP);
end architecture RTL;
| gpl-3.0 | 6dad8babed51a43cf1fda1e99e4c14d7 | 0.52979 | 4.104812 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/Adder.vhd | 2 | 2,044 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity Adder is
Port ( CarryIn : in unsigned (3 downto 0);
Entrada1 : in unsigned (3 downto 0);
Entrada2 : in unsigned (3 downto 0);
Entrada3 : in unsigned (3 downto 0);
Entrada4 : in unsigned (3 downto 0);
Entrada5 : in unsigned (3 downto 0);
Saida : out unsigned (3 downto 0);
CarryOut: out unsigned (3 downto 0));
end Adder;
architecture Behavioral of Adder is
signal sum_temp : unsigned(7 downto 0) := (others => '0');
signal sum : unsigned(7 downto 0) := (others => '0');
signal carry : unsigned(3 downto 0) := (others => '0');
begin
PROCESS (Entrada1, Entrada2, Entrada3, Entrada4, Entrada5, CarryIn, sum, sum_temp, carry)
BEGIN
sum_temp <= (("0000" & Entrada1) + ("0000" & Entrada2) + ("0000" & Entrada3) + ("0000" & Entrada4) + ("0000" & Entrada5) + ("0000" & CarryIn));
IF ((sum_temp >= "00000000") AND (sum_temp < "00001010")) THEN -- Entre 0 e 9?
carry <= "0000";
sum <= sum_temp;
ELSIF ((sum_temp >= "00001010") AND (sum_temp < "00010100")) THEN -- Entre 10 e 19?
carry <= "0001";
sum <= (sum_temp - "00001010");
ELSIF ((sum_temp >= "00010100") AND (sum_temp < "00011110")) THEN
carry <= "0010";
sum <= (sum_temp - "00010100");
ELSIF ((sum_temp >= "00011110") AND (sum_temp < "00101000")) THEN
carry <= ("0011");
sum <= (sum_temp - "00011110");
ELSIF ((sum_temp >= "00101000") AND (sum_temp < "00110010")) THEN
carry <= ("0100");
sum <= (sum_temp - "00101000");
ELSIF ((sum_temp >= "00110010") AND (sum_temp < "00111100")) THEN
carry <= ("0101");
sum <= (sum_temp - "00110010");
ELSIF ((sum_temp >= "00111100") AND (sum_temp < "01000110")) THEN
carry <= ("0110");
sum <= (sum_temp - "00111100");
ELSE
sum <= sum_temp;
END IF;
END PROCESS;
Saida <= sum(3 downto 0);
CarryOut <= carry(3 downto 0);
end Behavioral;
| gpl-3.0 | 464f46adc603e17900ffbf70fabd28f6 | 0.559198 | 3.291465 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_12_8_0/synth/RAT_slice_12_8_0.vhd | 2 | 3,817 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_12_8_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_12_8_0;
ARCHITECTURE RAT_slice_12_8_0_arch OF RAT_slice_12_8_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_8_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_12_8_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_12_8_0_arch : ARCHITECTURE IS "RAT_slice_12_8_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_12_8_0_arch: ARCHITECTURE IS "RAT_slice_12_8_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=7,DIN_TO=3}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 7,
DIN_TO => 3
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_12_8_0_arch;
| mit | 70114d4bcb545bf5e556c09614952936 | 0.727797 | 3.836181 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/common/my_config_VC707.vhdl | 1 | 1,787 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx VC707 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
| apache-2.0 | 5451f206c315fb1bca377dad1d593fd6 | 0.571349 | 4.690289 | false | true | false | false |
VLSI-EDA/PoC-Examples | src/io/FanControl/top_FanControl_KC705.vhdl | 1 | 7,203 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Top-Module: FanControl example design for a KC705 board
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library PoC;
use PoC.physical.all;
entity top_FanControl_KC705 is
port (
KC705_SystemClock_200MHz_p : in STD_LOGIC;
KC705_SystemClock_200MHz_n : in STD_LOGIC;
KC705_GPIO_LED : out STD_LOGIC_VECTOR(7 downto 0);
KC705_FanControl_PWM : out STD_LOGIC;
KC705_FanControl_Tacho : in STD_LOGIC
);
end entity;
architecture top of top_FanControl_KC705 is
attribute KEEP : BOOLEAN;
-- ===========================================================================
-- configurations
-- ===========================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant SYS_CLOCK_FREQ : FREQ := 200 MHz;
-- ClockNetwork configuration
-- ===========================================================================
constant SYSTEM_CLOCK_FREQ : FREQ := SYS_CLOCK_FREQ / 2;
-- ===========================================================================
-- signal declarations
-- ===========================================================================
-- clock and reset signals
signal System_RefClock_200MHz : STD_LOGIC;
signal ClkNet_Reset : STD_LOGIC;
signal ClkNet_ResetDone : STD_LOGIC;
signal SystemClock_200MHz : STD_LOGIC;
signal SystemClock_100MHz : STD_LOGIC;
signal SystemClock_Stable_200MHz : STD_LOGIC;
signal SystemClock_Stable_100MHz : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_Reset : STD_LOGIC;
attribute KEEP of System_Clock : signal is TRUE;
attribute KEEP of System_Reset : signal is TRUE;
begin
-- ===========================================================================
-- assert statements
-- ===========================================================================
assert FALSE report "FanControl configuration:" severity NOTE;
assert FALSE report " SYS_CLOCK_FREQ: " & to_string(SYS_CLOCK_FREQ, 3) severity note;
-- ===========================================================================
-- Input/output buffers
-- ===========================================================================
IBUFGDS_SystemClock : IBUFGDS
port map (
I => KC705_SystemClock_200MHz_p,
IB => KC705_SystemClock_200MHz_n,
O => System_RefClock_200MHz
);
-- ==========================================================================================================================================================
-- ClockNetwork
-- ==========================================================================================================================================================
ClkNet_Reset <= '0';
ClkNet : entity PoC.clknet_ClockNetwork_KC705
generic map (
CLOCK_IN_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockIn_200MHz => System_RefClock_200MHz,
ClockNetwork_Reset => ClkNet_Reset,
ClockNetwork_ResetDone => ClkNet_ResetDone,
Control_Clock_200MHz => open,
Clock_250MHz => open,
Clock_200MHz => SystemClock_200MHz,
Clock_125MHz => open,
Clock_100MHz => SystemClock_100MHz,
Clock_10MHz => open,
Clock_Stable_250MHz => open,
Clock_Stable_200MHz => SystemClock_Stable_200MHz,
Clock_Stable_125MHz => open,
Clock_Stable_100MHz => SystemClock_Stable_100MHz,
Clock_Stable_10MHz => open
);
-- system signals
System_Clock <= SystemClock_100MHz;
System_Reset <= not SystemClock_Stable_100MHz;
-- ==========================================================================================================================================================
-- General Purpose I/O
-- ==========================================================================================================================================================
blkGPIO : block
signal GPIO_LED : STD_LOGIC_VECTOR(7 downto 0);
signal GPIO_LED_d : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
GPIO_LED <= "0000000" & ClkNet_ResetDone;
GPIO_LED_d <= GPIO_LED when rising_edge(System_Clock);
KC705_GPIO_LED <= GPIO_LED_d;
end block;
-- ==========================================================================================================================================================
-- Fan Control
-- ==========================================================================================================================================================
blkFanControl : block
signal FanControl_PWM : STD_LOGIC;
signal FanControl_PWM_d : STD_LOGIC := '0';
signal FanControl_Tacho_async : STD_LOGIC;
signal FanControl_Tacho_sync : STD_LOGIC;
begin
FanControl_Tacho_async <= KC705_FanControl_Tacho;
sync : entity PoC.sync_Bits
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => FanControl_Tacho_async, -- Data to be synchronized
Output(0) => FanControl_Tacho_sync -- synchronized data
);
Fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ -- 100 MHz
)
port map (
Clock => System_Clock,
Reset => System_Reset,
Fan_PWM => FanControl_PWM,
Fan_Tacho => FanControl_Tacho_sync,
TachoFrequency => open
);
-- IOB-FF
FanControl_PWM_d <= FanControl_PWM when rising_edge(System_Clock);
KC705_FanControl_PWM <= FanControl_PWM_d;
end block;
end architecture;
| apache-2.0 | d50b7ca7510245ea6c5919d055432211 | 0.451756 | 4.704768 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/io/FanControl/top_FanControl_VC707.vhdl | 1 | 4,580 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Top-Module: FanControl example design for a VC707 board
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library PoC;
use PoC.physical.all;
entity top_FanControl_VC707 is
port (
VC707_SystemClock_200MHz_p : in STD_LOGIC;
VC707_SystemClock_200MHz_n : in STD_LOGIC;
VC707_FanControl_PWM : out STD_LOGIC;
VC707_FanControl_Tacho : in STD_LOGIC
);
end entity;
architecture top of top_FanControl_VC707 is
attribute KEEP : BOOLEAN;
-- ===========================================================================
-- configurations
-- ===========================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant SYSTEM_CLOCK_FREQ : FREQ := 200 MHz;
-- ===========================================================================
-- signal declarations
-- ===========================================================================
signal System_Clock_ibufgds : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_Reset : STD_LOGIC;
begin
-- ===========================================================================
-- assert statements
-- ===========================================================================
assert FALSE report "FanControl configuration:" severity NOTE;
assert FALSE report " SYSTEM_CLOCK_FREQ: " & to_string(SYSTEM_CLOCK_FREQ, 3) severity note;
-- ===========================================================================
-- Input/output buffers
-- ===========================================================================
IBUFGDS_SystemClock : IBUFGDS
port map (
I => VC707_SystemClock_200MHz_p,
IB => VC707_SystemClock_200MHz_n,
O => System_Clock_ibufgds
);
BUFG_SystemClock : BUFG
port map (
I => System_Clock_ibufgds,
O => System_Clock);
System_Reset <= '0';
-- ===========================================================================
-- Fan Control
-- ===========================================================================
blkFanControl : block
signal FanControl_PWM : STD_LOGIC;
signal FanControl_PWM_d : STD_LOGIC := '0';
signal FanControl_Tacho_async : STD_LOGIC;
signal FanControl_Tacho_sync : STD_LOGIC;
begin
FanControl_Tacho_async <= VC707_FanControl_Tacho;
sync : entity PoC.sync_Bits
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => FanControl_Tacho_async, -- Data to be synchronized
Output(0) => FanControl_Tacho_sync -- synchronized data
);
Fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ -- 200 MHz
)
port map (
Clock => System_Clock,
Reset => System_Reset,
Fan_PWM => FanControl_PWM,
Fan_Tacho => FanControl_Tacho_sync,
TachoFrequency => open
);
-- IOB-FF
FanControl_PWM_d <= FanControl_PWM when rising_edge(System_Clock);
VC707_FanControl_PWM <= FanControl_PWM_d;
end block;
end architecture;
| apache-2.0 | ebbad7f4ba86fffdfdc394e71ea3d49d | 0.478384 | 4.570858 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd | 5 | 10,054 | `protect begin_protected
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
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`protect end_protected
| mit | bbf52f4dbdb76153b9522206ec69ff3f | 0.919236 | 1.932347 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 5 | 73,491 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
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Hdr9
`protect end_protected
| mit | b11d43d83925cd0109ace0f7b7b42f31 | 0.951273 | 1.833425 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "75028A6964188A69641675018A696418750065FF84A100000000000000000000";
attribute INIT_02 of ram_1024_x_18 : label is "640F8A69640B75038A6964238A6964228A6964158A6964148A69640D8A69640C";
attribute INIT_03 of ram_1024_x_18 : label is "8A69640A8A6964018A69640075048A6964238A6964228A6964158A6964148A69";
attribute INIT_04 of ram_1024_x_18 : label is "64108A69640E8A69640A8A6964018A69640075058A6964158A6964148A696410";
attribute INIT_05 of ram_1024_x_18 : label is "640B75078A6964188A6964108A69640A75068A6964188A6964168A6964118A69";
attribute INIT_06 of ram_1024_x_18 : label is "00038439835A000020206500740160008A69640D8A69640C75088A69640F8A69";
attribute INIT_07 of ram_1024_x_18 : label is "710071007100710071007100710071007100710071007200730083588399835A";
attribute INIT_08 of ram_1024_x_18 : label is "82018A3988918472020084F9610062007500800283A313FF930183AB12FF9201";
attribute INIT_09 of ram_1024_x_18 : label is "6380800284B3151E950184BB042884018A6964007500650080028891844B021E";
attribute INIT_0A of ram_1024_x_18 : label is "03018101172104188821866977006380850B0301810116210418882186697600";
attribute INIT_0B of ram_1024_x_18 : label is "192104188821866979006380859B030181011821041888218669780063808553";
attribute INIT_0C of ram_1024_x_18 : label is "4611450964008002862B030181011A210418882186697A00638085E303018101";
attribute INIT_0D of ram_1024_x_18 : label is "84018702070087E18501840186DA070087E18501840186B2070087E1C601C501";
attribute INIT_0E of ram_1024_x_18 : label is "878A070087E18601C5028401875A070087E1850284018732070087E18601C502";
attribute INIT_0F of ram_1024_x_18 : label is "80022793469045918002840187DA070087E18501840187B2070087E185018401";
attribute INIT_10 of ram_1024_x_18 : label is "888864FF88830403888088720403887204028862050088018002259342904191";
attribute INIT_11 of ram_1024_x_18 : label is "46196500638088A3030184018A69650388CA06D8461965006400638080026400";
attribute INIT_12 of ram_1024_x_18 : label is "030184018A696503896A06E846196500638088F3030184018A696503891A06E0";
attribute INIT_13 of ram_1024_x_18 : label is "8A0A06F84619650063808993030184018A69650389BA06F04619650063808943";
attribute INIT_14 of ram_1024_x_18 : label is "45925590449180025FD15EC95DC15CB95BB18002950189E3030184018A696503";
attribute INIT_15 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000A00360018A888002";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "8A90000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "FFFFFFC0C3FF33CCF333CCCCCCCCF333333CCCCCCF333333CCF3F00000000000";
attribute INITP_01 of ram_1024_x_18 : label is "7F6328CA32A328CA8CA328CA0D1803C600F1803C600F1803D38E3F4380CFD38E";
attribute INITP_02 of ram_1024_x_18 : label is "000000000000000000000071FD00186303C6303C6303C6303C6303F7330CCC7F";
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attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"75028A6964188A69641675018A696418750065FF84A100000000000000000000",
INIT_02 => X"640F8A69640B75038A6964238A6964228A6964158A6964148A69640D8A69640C",
INIT_03 => X"8A69640A8A6964018A69640075048A6964238A6964228A6964158A6964148A69",
INIT_04 => X"64108A69640E8A69640A8A6964018A69640075058A6964158A6964148A696410",
INIT_05 => X"640B75078A6964188A6964108A69640A75068A6964188A6964168A6964118A69",
INIT_06 => X"00038439835A000020206500740160008A69640D8A69640C75088A69640F8A69",
INIT_07 => X"710071007100710071007100710071007100710071007200730083588399835A",
INIT_08 => X"82018A3988918472020084F9610062007500800283A313FF930183AB12FF9201",
INIT_09 => X"6380800284B3151E950184BB042884018A6964007500650080028891844B021E",
INIT_0A => X"03018101172104188821866977006380850B0301810116210418882186697600",
INIT_0B => X"192104188821866979006380859B030181011821041888218669780063808553",
INIT_0C => X"4611450964008002862B030181011A210418882186697A00638085E303018101",
INIT_0D => X"84018702070087E18501840186DA070087E18501840186B2070087E1C601C501",
INIT_0E => X"878A070087E18601C5028401875A070087E1850284018732070087E18601C502",
INIT_0F => X"80022793469045918002840187DA070087E18501840187B2070087E185018401",
INIT_10 => X"888864FF88830403888088720403887204028862050088018002259342904191",
INIT_11 => X"46196500638088A3030184018A69650388CA06D8461965006400638080026400",
INIT_12 => X"030184018A696503896A06E846196500638088F3030184018A696503891A06E0",
INIT_13 => X"8A0A06F84619650063808993030184018A69650389BA06F04619650063808943",
INIT_14 => X"45925590449180025FD15EC95DC15CB95BB18002950189E3030184018A696503",
INIT_15 => X"000000000000000000000000000000000000000000000000A00360018A888002",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"8A90000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"FFFFFFC0C3FF33CCF333CCCCCCCCF333333CCCCCCF333333CCF3F00000000000",
INITP_01 => X"7F6328CA32A328CA8CA328CA0D1803C600F1803C600F1803D38E3F4380CFD38E",
INITP_02 => X"000000000000000000000071FD00186303C6303C6303C6303C6303F7330CCC7F",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | 25ec3704e760e22cb38311339e62065f | 0.735725 | 4.946989 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/vga_clk_div.vhd | 1 | 794 | --
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic := '0';
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 0) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
end process my_div_fast;
clkout <= tmp_clkf;
end Behavioral;
| mit | d1a3c80a6bebc842500b732b4ee1fb99 | 0.574307 | 3.308333 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/io/lcd/lcd_test.vhdl | 1 | 4,734 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: LCD Test Application designed for the
-- Spartan-3 Evaluation Kit.
--
-- Authors: Thomas B. Preußer <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity lcd_test is
generic(
CLOCK_FREQ : freq := 100 MHz;
DATA_WIDTH : positive := 8
);
port(
-- Global Reset / Clock
rst, clk : in std_logic;
-- LCD Control Signals
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_dat : inout std_logic_vector(7 downto 0)
);
end entity lcd_test;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.lcd.all;
architecture rtl of lcd_test is
----------------------------------------------------------------------------
-- Transmission Sequence
type tSeq is array (natural range<>) of std_logic_vector(8 downto 0);
constant OutSeq : tSeq := (
'1' & lcd_functionset(DATA_WIDTH, 2, 0), -- two line, 5x8 font
'1' & lcd_displayctrl(true, false, false),-- on, no cursor, no blink
"100000001", -- Display Clear: "00000001"
'1' & lcd_entrymode(true, false), -- inc, no shift
"10000001-", -- Return Home: "0000001-"
"001010000", -- P
"001100001", -- a
"001110011", -- s
"001110011", -- s
"111000000", -- Goto 0x40
"001010100", -- T
"001100101", -- e
"001110011", -- s
"001110100", -- t
"011011010" -- v
);
signal SeqCnt : unsigned(3 downto 0) := (others => '0');
signal Step : std_logic;
-- Synchronized Inputs
signal rst_i : std_logic;
-- LCD Connectivity
signal rdy : std_logic;
signal dat : std_logic_vector(7 downto 0);
signal stb : std_logic;
signal cmd : std_logic;
begin
-- Synchronization of Inputs
process(clk)
begin
if clk'event and clk = '1' then
rst_i <= rst;
end if;
end process;
-- Instantiate LCD Bit Level Module
blkLCD: block
signal lcd_rw_l : std_logic;
signal lcd_dat_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal lcd_dat_o : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lcd : lcd_dotmatrix
generic map (
CLOCK_FREQ => CLOCK_FREQ,
DATA_WIDTH => DATA_WIDTH
)
port map(
clk => clk,
rst => rst_i,
rdy => rdy,
stb => stb,
cmd => cmd,
dat => dat,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw_l,
lcd_dat_i => lcd_dat_i,
lcd_dat_o => lcd_dat_o
);
lcd_rw <= lcd_rw_l;
lcd_dat_i <= lcd_dat(DATA_WIDTH-1 downto 0);
process(lcd_rw_l, lcd_dat_o)
begin
if lcd_rw_l = '1' then
lcd_dat <= (others => 'Z');
else
lcd_dat <= (others => '0');
lcd_dat(7 downto 8-DATA_WIDTH) <= lcd_dat_o;
end if;
end process;
end block;
-- Sequence Counter
process(clk)
begin
if clk'event and clk = '1' then
if rst_i = '1' then
SeqCnt <= (others => '0');
elsif Step = '1' then
SeqCnt <= SeqCnt + 1;
end if;
end if;
end process;
Step <= rdy when (SeqCnt and to_unsigned(OutSeq'length, SeqCnt'length))
/= to_unsigned(OutSeq'length, SeqCnt'length) else '0';
-- LCD Feed
process(SeqCnt, Step)
variable w : std_logic_vector(8 downto 0);
begin
--w := OutSeq(to_integer(SeqCnt))
w := (others => '0');
for i in OutSeq'range loop
if i = to_integer(SeqCnt) then
w := w or OutSeq(i);
end if;
end loop;
stb <= Step;
cmd <= w(8);
dat <= w(7 downto 0);
end process;
end rtl;
| apache-2.0 | 6400fa81cd01f8d338b8d86c652e0b67 | 0.546915 | 3.601218 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_1_0/sim/RAT_FlagReg_1_0.vhd | 2 | 3,343 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_1_0 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_1_0;
ARCHITECTURE RAT_FlagReg_1_0_arch OF RAT_FlagReg_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_1_0_arch;
| mit | a6098fbf395824fed24fd3dd1d6147ab | 0.717918 | 4.022864 | false | false | false | false |
ErikAndren/SG90-PWM | Servo_pwm.vhd | 1 | 1,130 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity servo_pwm is
generic (
ResW : positive := 7
);
port (
Clk : in bit1; -- Must be 64 kHz
RstN : in bit1;
--
Pos : in word(ResW-1 downto 0);
--
Servo : out bit1
);
end Servo_pwm;
architecture Behavioral of Servo_pwm is
constant MaxCnt : positive := 1279;
constant MaxCntW : positive := bits(MaxCnt);
-- Counter, from 0 to 1279.
signal Cnt_D : word(MaxCntW-1 downto 0);
-- Temporal signal used to generate the PWM pulse.
signal pwmi : word(8-1 downto 0);
begin
-- Minimum value should be 0.5ms.
pwmi <= ('0' & Pos) + 32;
-- Counter process, from 0 to 1279.
counter : process (RstN, Clk)
begin
if (RstN = '0') then
Cnt_D <= (others => '0');
elsif rising_edge(Clk) then
if Cnt_D = MaxCnt then
Cnt_D <= (others => '0');
else
Cnt_D <= Cnt_D + 1;
end if;
end if;
end process;
-- Output signal for the Servomotor.
Servo <= '1' when Cnt_D < pwmi else '0';
end Behavioral;
| gpl-2.0 | cf24f6c8d955350e96b1cb0f71c2ebcf | 0.593805 | 3.165266 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 5 | 24,644 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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KyYpUZ9Ey4oU/9TPLlu32FhGeJWJ9oIycalf7+86Hh9xIzjCYJ5MEB7VszgG7sUMi2a/4D/uMMQg
o5q5fstDXJulSIq5m/7uLYDtDISbpHw9VzF1d5JCGkpky+OR1KPuyhSEcTABi/YdhmfSa5giLbIS
RsZQLfBpjT6YylaIRjVvcR2d7wWotU0F9F7D8c/tAmsjGHmtkgu0rKOSGPHxGqKL2OhGYR2/daZe
p0YldMKHqsotwdifAwpv4vddVAtEvRzyYj6j4K4SNUhnpeNtEuFnmEykZMSqfqkUG7Omo5mH3zrr
WbqvbScxSDN1YWWfgcrvnbCJMxPJBGGsH16pYt2FqmjmfwAw/DZqCvzUL0JY9h/N0gfm8IGSlRu4
qEjYuyfuKgxAWrht7m5XMcAOYYbJRq/aZNY5NP93A1+L8EX/BZvE/4biwHya7kJ8ElpGAsP539ex
M6oiALzDeQpDMVkhTxtxrkA2H7vHtGkIiZNIkssp6J7RaEQf8pvAP3VmfEQCbLUX6ML/ZdShNLBz
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AYycDoAlU4xUIK9uEsLw4dpdx4yBW67BKrTWF/k60QaRupyKgM+26f6PeYdXtoOFWEaKTD3Le+EI
RczwTfCF//de3hJN41i27+i2m9ggzIulY3ZMIvpRMH0cHICGbXj9fE+FBFP+5ZdtdDXkZf/a6Zgl
u0ZvDZ495GxsBXbCd2sTGshaK5X+tmBrWe2xrNwGIfRkTzQ45mErITXiXLshC2aDWCiGyBnTRwix
UaKZykCjch9tBIuTsop1bx9APU9Rsd5DYFxnxu2s6LKpC1Kr+B4=
`protect end_protected
| mit | 9b5c6f686fde106b5b4e1dcb6d08e06f | 0.940635 | 1.880934 | false | false | false | false |
stefanct/aua | hw/sim/tb.vhd | 1 | 3,445 | library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity aua_tb is
end aua_tb;
architecture aua_test of aua_tb is
component aua
port (
clk_in : in std_logic;
reset_pin : in std_logic;
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0);
digit0_pins : out std_logic_vector(6 downto 0);
digit1_pins : out std_logic_vector(6 downto 0);
digit2_pins : out std_logic_vector(6 downto 0);
digit3_pins : out std_logic_vector(6 downto 0);
digit4_pins : out std_logic_vector(6 downto 0);
digit5_pins : out std_logic_vector(6 downto 0);
sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
sram_dq : inout word_t;
sram_we : out std_logic;
-- sram_oe : out std_logic;
sram_ub : out std_logic;
sram_lb : out std_logic;
-- sram_ce : out std_logic
txd : out std_logic;
rxd : in std_ulogic
--~ ncts : in std_logic;
--~ nrts : out std_logic
);
end component;
signal clk : std_logic;
signal reset_pin : std_logic;
signal switch_pins : std_logic_vector(15 downto 0);
signal led_pins : std_logic_vector(15 downto 0);
signal digit0_pins : std_logic_vector(6 downto 0);
signal digit1_pins : std_logic_vector(6 downto 0);
signal digit2_pins : std_logic_vector(6 downto 0);
signal digit3_pins : std_logic_vector(6 downto 0);
signal digit4_pins : std_logic_vector(6 downto 0);
signal digit5_pins : std_logic_vector(6 downto 0);
signal sram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
signal sram_dq : word_t;
signal sram_we : std_logic;
signal sram_ub : std_logic;
signal sram_lb : std_logic;
signal txd : std_logic;
signal rxd : std_logic;
constant freq: natural := 70000000;
constant clk_tick: natural := 1000000000/freq;
constant uart_baud: natural := 115200;
constant uart_clks: natural := freq/uart_baud;
begin
uart: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks);
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks*2);
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks*2);
end process;
aua1: configuration work.aua_cache
port map (
clk_in => clk,
reset_pin => reset_pin,
switch_pins => switch_pins,
led_pins => led_pins,
digit0_pins => digit0_pins,
digit1_pins => digit1_pins,
digit2_pins => digit2_pins,
digit3_pins => digit3_pins,
digit4_pins => digit4_pins,
digit5_pins => digit5_pins,
sram_addr => sram_addr,
sram_dq => sram_dq,
sram_we => sram_we,
sram_ub => sram_ub,
sram_lb => sram_lb,
txd => txd,
rxd => rxd
);
CLKGEN: process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset_pin <= '0';
switch_pins <= x"ffff";
sram_dq <= (others => '0');
--~ rxd <= '0';
icwait(2);
reset_pin <= '1';
icwait(9000);
assert false report "sim finish" SEVERITY failure;
end process TEST;
end aua_test;
| gpl-3.0 | 993a8ca5ece3e60752c115c3bc7cac78 | 0.606676 | 2.854184 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/hdl/RAT.vhd | 1 | 26,439 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Fri Oct 27 00:01:59 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target RAT.bd
--Design : RAT
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ALU_imp_CAYOB2 is
port (
ALU_OPY_SEL : in STD_LOGIC;
ALU_Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
C_FLAG : out STD_LOGIC;
C_IN : in STD_LOGIC;
IMMED : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_X : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_Y : in STD_LOGIC_VECTOR ( 7 downto 0 );
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
Z_FLAG : out STD_LOGIC
);
end ALU_imp_CAYOB2;
architecture STRUCTURE of ALU_imp_CAYOB2 is
component RAT_Mux2x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Mux2x1_8_0_0;
component RAT_alu_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC
);
end component RAT_alu_0_0;
signal A_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal B_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal C_IN_1 : STD_LOGIC;
signal Mux2x1_8_0_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal REGOUT_Y_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SEL_1 : STD_LOGIC;
signal Sel_2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal alu_0_C_FLAG : STD_LOGIC;
signal alu_0_SUM : STD_LOGIC_VECTOR ( 7 downto 0 );
signal alu_0_Z_FLAG : STD_LOGIC;
begin
A_1(7 downto 0) <= REGOUT_X(7 downto 0);
B_1(7 downto 0) <= IMMED(7 downto 0);
C_FLAG <= alu_0_C_FLAG;
C_IN_1 <= C_IN;
REGOUT_Y_1(7 downto 0) <= REGOUT_Y(7 downto 0);
SEL_1 <= ALU_OPY_SEL;
SUM(7 downto 0) <= alu_0_SUM(7 downto 0);
Sel_2(3 downto 0) <= ALU_Sel(3 downto 0);
Z_FLAG <= alu_0_Z_FLAG;
Mux2x1_8_0: component RAT_Mux2x1_8_0_0
port map (
A(7 downto 0) => REGOUT_Y_1(7 downto 0),
B(7 downto 0) => B_1(7 downto 0),
SEL => SEL_1,
X(7 downto 0) => Mux2x1_8_0_X(7 downto 0)
);
alu_0: component RAT_alu_0_0
port map (
A(7 downto 0) => A_1(7 downto 0),
B(7 downto 0) => Mux2x1_8_0_X(7 downto 0),
C_FLAG => alu_0_C_FLAG,
C_IN => C_IN_1,
SUM(7 downto 0) => alu_0_SUM(7 downto 0),
Sel(3 downto 0) => Sel_2(3 downto 0),
Z_FLAG => alu_0_Z_FLAG
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FlagRegisters_imp_9QD03I is
port (
CLK : in STD_LOGIC;
C_CLR : in STD_LOGIC;
C_IN_FLAG : in STD_LOGIC;
C_LD : in STD_LOGIC;
C_OUT_FLAG : out STD_LOGIC;
C_SET : in STD_LOGIC;
EXT_INTERRUPT : in STD_LOGIC_VECTOR ( 0 to 0 );
INTERRUPT : out STD_LOGIC_VECTOR ( 0 to 0 );
I_CLR : in STD_LOGIC;
I_SET : in STD_LOGIC;
Z_CLR : in STD_LOGIC;
Z_IN_FLAG : in STD_LOGIC;
Z_LD : in STD_LOGIC;
Z_OUT_FLAG : out STD_LOGIC;
Z_SET : in STD_LOGIC
);
end FlagRegisters_imp_9QD03I;
architecture STRUCTURE of FlagRegisters_imp_9QD03I is
component RAT_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component RAT_util_vector_logic_0_0;
component RAT_FlagReg_0_0 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_0_0;
component RAT_FlagReg_0_1 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_0_1;
component RAT_FlagReg_1_0 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
end component RAT_FlagReg_1_0;
signal CLR1_1 : STD_LOGIC;
signal CLR_1 : STD_LOGIC;
signal CLR_2 : STD_LOGIC;
signal IN_FLAG_1 : STD_LOGIC;
signal IN_FLAG_2 : STD_LOGIC;
signal I_OUT_FLAG : STD_LOGIC;
signal LD_1 : STD_LOGIC;
signal LD_2 : STD_LOGIC;
signal Net : STD_LOGIC;
signal Op2_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal SET1_1 : STD_LOGIC;
signal SET_1 : STD_LOGIC;
signal SET_2 : STD_LOGIC;
signal VECTOR_AND_Res : STD_LOGIC_VECTOR ( 0 to 0 );
begin
CLR1_1 <= Z_CLR;
CLR_1 <= C_CLR;
CLR_2 <= I_CLR;
INTERRUPT(0) <= VECTOR_AND_Res(0);
IN_FLAG_1 <= C_IN_FLAG;
IN_FLAG_2 <= Z_IN_FLAG;
LD_1 <= C_LD;
LD_2 <= Z_LD;
Net <= CLK;
Op2_1(0) <= EXT_INTERRUPT(0);
SET1_1 <= Z_SET;
SET_1 <= C_SET;
SET_2 <= I_SET;
C: component RAT_FlagReg_0_1
port map (
CLK => Net,
CLR => CLR_1,
IN_FLAG => IN_FLAG_1,
LD => LD_1,
OUT_FLAG => C_OUT_FLAG,
SET => SET_1
);
I: component RAT_FlagReg_0_0
port map (
CLK => Net,
CLR => CLR_2,
IN_FLAG => '0',
LD => '0',
OUT_FLAG => I_OUT_FLAG,
SET => SET_2
);
VECTOR_AND: component RAT_util_vector_logic_0_0
port map (
Op1(0) => I_OUT_FLAG,
Op2(0) => Op2_1(0),
Res(0) => VECTOR_AND_Res(0)
);
Z: component RAT_FlagReg_1_0
port map (
CLK => Net,
CLR => CLR1_1,
IN_FLAG => IN_FLAG_2,
LD => LD_2,
OUT_FLAG => Z_OUT_FLAG,
SET => SET1_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ProgramCounter_imp_FFPXUZ is
port (
ADDRESS : out STD_LOGIC_VECTOR ( 0 to 9 );
CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
INC : in STD_LOGIC;
LOAD : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end ProgramCounter_imp_FFPXUZ;
architecture STRUCTURE of ProgramCounter_imp_FFPXUZ is
component RAT_Counter10bit_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
end component RAT_Counter10bit_0_0;
component RAT_Mux4x1_10_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_Mux4x1_10_0_0;
component RAT_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_xlconstant_0_0;
signal A_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal CLK_1 : STD_LOGIC;
signal Counter10bit_0_COUNT : STD_LOGIC_VECTOR ( 0 to 9 );
signal INC_1 : STD_LOGIC;
signal LOAD_1 : STD_LOGIC;
signal Mux4x1_10_0_X : STD_LOGIC_VECTOR ( 9 downto 0 );
signal SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
ADDRESS(0 to 9) <= Counter10bit_0_COUNT(0 to 9);
A_1(9 downto 0) <= FROM_IMMED(9 downto 0);
CLK_1 <= CLK;
INC_1 <= INC;
LOAD_1 <= LOAD;
SEL_1(1 downto 0) <= SEL(1 downto 0);
Counter10bit_0: component RAT_Counter10bit_0_0
port map (
CLK => CLK_1,
COUNT(0 to 9) => Counter10bit_0_COUNT(0 to 9),
Din(0) => Mux4x1_10_0_X(9),
Din(1) => Mux4x1_10_0_X(8),
Din(2) => Mux4x1_10_0_X(7),
Din(3) => Mux4x1_10_0_X(6),
Din(4) => Mux4x1_10_0_X(5),
Din(5) => Mux4x1_10_0_X(4),
Din(6) => Mux4x1_10_0_X(3),
Din(7) => Mux4x1_10_0_X(2),
Din(8) => Mux4x1_10_0_X(1),
Din(9) => Mux4x1_10_0_X(0),
INC => INC_1,
LOAD => LOAD_1,
RESET => '0'
);
Mux4x1_10_0: component RAT_Mux4x1_10_0_0
port map (
A(9 downto 0) => A_1(9 downto 0),
B(9 downto 0) => B"0000000000",
C(9 downto 0) => xlconstant_0_dout(9 downto 0),
D(9 downto 0) => B"0000000000",
SEL(1 downto 0) => SEL_1(1 downto 0),
X(9 downto 0) => Mux4x1_10_0_X(9 downto 0)
);
xlconstant_0: component RAT_xlconstant_0_0
port map (
dout(9 downto 0) => xlconstant_0_dout(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ProgramROM_SLICED_imp_MYEMEW is
port (
ADDRESS : in STD_LOGIC_VECTOR ( 0 to 9 );
ADDRX : out STD_LOGIC_VECTOR ( 4 downto 0 );
ADDRY : out STD_LOGIC_VECTOR ( 4 downto 0 );
CLK : in STD_LOGIC;
IMMED : out STD_LOGIC_VECTOR ( 9 downto 0 );
IMMED_VAL : out STD_LOGIC_VECTOR ( 7 downto 0 );
OPCODE_HI_5 : out STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end ProgramROM_SLICED_imp_MYEMEW;
architecture STRUCTURE of ProgramROM_SLICED_imp_MYEMEW is
component RAT_prog_rom_0_0 is
port (
ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 );
INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 );
CLK : in STD_LOGIC
);
end component RAT_prog_rom_0_0;
component RAT_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component RAT_xlslice_0_0;
component RAT_slice_12_3_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_12_3_0;
component RAT_slice_17_13_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component RAT_slice_17_13_0;
component RAT_slice_1_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_slice_1_0_0;
component RAT_slice_7_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_7_0_0;
component RAT_slice_12_8_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component RAT_slice_12_8_0;
signal ADDRESS_1 : STD_LOGIC_VECTOR ( 0 to 9 );
signal CLK_1 : STD_LOGIC;
signal prog_rom_0_INSTRUCTION : STD_LOGIC_VECTOR ( 17 downto 0 );
signal slice_12_3_Dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal slice_12_8_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
signal slice_17_13_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
signal slice_1_0_Dout : STD_LOGIC_VECTOR ( 1 downto 0 );
signal slice_7_0_Dout : STD_LOGIC_VECTOR ( 7 downto 0 );
signal slice_7_3_Dout : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
ADDRESS_1(0 to 9) <= ADDRESS(0 to 9);
ADDRX(4 downto 0) <= slice_12_8_Dout(4 downto 0);
ADDRY(4 downto 0) <= slice_7_3_Dout(4 downto 0);
CLK_1 <= CLK;
IMMED(9 downto 0) <= slice_12_3_Dout(9 downto 0);
IMMED_VAL(7 downto 0) <= slice_7_0_Dout(7 downto 0);
OPCODE_HI_5(4 downto 0) <= slice_17_13_Dout(4 downto 0);
OPCODE_LO_2(1 downto 0) <= slice_1_0_Dout(1 downto 0);
prog_rom_0: component RAT_prog_rom_0_0
port map (
ADDRESS(9) => ADDRESS_1(0),
ADDRESS(8) => ADDRESS_1(1),
ADDRESS(7) => ADDRESS_1(2),
ADDRESS(6) => ADDRESS_1(3),
ADDRESS(5) => ADDRESS_1(4),
ADDRESS(4) => ADDRESS_1(5),
ADDRESS(3) => ADDRESS_1(6),
ADDRESS(2) => ADDRESS_1(7),
ADDRESS(1) => ADDRESS_1(8),
ADDRESS(0) => ADDRESS_1(9),
CLK => CLK_1,
INSTRUCTION(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0)
);
slice_12_3: component RAT_xlslice_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(9 downto 0) => slice_12_3_Dout(9 downto 0)
);
slice_12_8: component RAT_slice_7_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_12_8_Dout(4 downto 0)
);
slice_17_13: component RAT_slice_12_3_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_17_13_Dout(4 downto 0)
);
slice_1_0: component RAT_slice_17_13_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(1 downto 0) => slice_1_0_Dout(1 downto 0)
);
slice_7_0: component RAT_slice_1_0_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(7 downto 0) => slice_7_0_Dout(7 downto 0)
);
slice_7_3: component RAT_slice_12_8_0
port map (
Din(17 downto 0) => prog_rom_0_INSTRUCTION(17 downto 0),
Dout(4 downto 0) => slice_7_3_Dout(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Registers_imp_1M200Q6 is
port (
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 );
ALU_RESULT : in STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
DIN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_X : out STD_LOGIC_VECTOR ( 7 downto 0 );
REGOUT_Y : out STD_LOGIC_VECTOR ( 7 downto 0 );
REG_WRSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
WE : in STD_LOGIC
);
end Registers_imp_1M200Q6;
architecture STRUCTURE of Registers_imp_1M200Q6 is
component RAT_RegisterFile_0_0 is
port (
D_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
DX_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
DY_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 );
WE : in STD_LOGIC;
CLK : in STD_LOGIC
);
end component RAT_RegisterFile_0_0;
component RAT_Mux4x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component RAT_Mux4x1_8_0_0;
signal ADRX_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ADRY_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal A_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CLK_1 : STD_LOGIC;
signal D_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Mux4x1_8_0_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RegisterFile_0_DX_OUT : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RegisterFile_0_DY_OUT : STD_LOGIC_VECTOR ( 7 downto 0 );
signal SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal WE_1 : STD_LOGIC;
begin
ADRX_1(4 downto 0) <= ADRX(4 downto 0);
ADRY_1(4 downto 0) <= ADRY(4 downto 0);
A_1(7 downto 0) <= ALU_RESULT(7 downto 0);
CLK_1 <= CLK;
D_1(7 downto 0) <= DIN_PORT(7 downto 0);
REGOUT_X(7 downto 0) <= RegisterFile_0_DX_OUT(7 downto 0);
REGOUT_Y(7 downto 0) <= RegisterFile_0_DY_OUT(7 downto 0);
SEL_1(1 downto 0) <= REG_WRSEL(1 downto 0);
WE_1 <= WE;
Mux4x1_8_0: component RAT_Mux4x1_8_0_0
port map (
A(7 downto 0) => A_1(7 downto 0),
B(7 downto 0) => B"00000000",
C(7 downto 0) => B"00000000",
D(7 downto 0) => D_1(7 downto 0),
SEL(1 downto 0) => SEL_1(1 downto 0),
X(7 downto 0) => Mux4x1_8_0_X(7 downto 0)
);
RegisterFile_0: component RAT_RegisterFile_0_0
port map (
ADRX(4 downto 0) => ADRX_1(4 downto 0),
ADRY(4 downto 0) => ADRY_1(4 downto 0),
CLK => CLK_1,
DX_OUT(7 downto 0) => RegisterFile_0_DX_OUT(7 downto 0),
DY_OUT(7 downto 0) => RegisterFile_0_DY_OUT(7 downto 0),
D_IN(7 downto 0) => Mux4x1_8_0_X(7 downto 0),
WE => WE_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RATCPU_imp_157ITB6 is
port (
CLK : in STD_LOGIC;
DIN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
EXT_INTERRRUPT : in STD_LOGIC_VECTOR ( 0 to 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
end RATCPU_imp_157ITB6;
architecture STRUCTURE of RATCPU_imp_157ITB6 is
component RAT_ControlUnit_0_0 is
port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC
);
end component RAT_ControlUnit_0_0;
signal ADDRESS_1 : STD_LOGIC_VECTOR ( 0 to 9 );
signal ADRX_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ADRY_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ALU_C_FLAG : STD_LOGIC;
signal ALU_OPY_SEL_1 : STD_LOGIC;
signal ALU_RESULT_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ALU_Sel_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ALU_Z_FLAG : STD_LOGIC;
signal CLK_1 : STD_LOGIC;
signal C_CLR_1 : STD_LOGIC;
signal C_LD_1 : STD_LOGIC;
signal C_SET_1 : STD_LOGIC;
signal ControlUnit_0_PC_INC : STD_LOGIC;
signal ControlUnit_0_PC_LD : STD_LOGIC;
signal ControlUnit_0_PC_MUX_SEL : STD_LOGIC_VECTOR ( 1 downto 0 );
signal DIN_PORT_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal FlagRegisters_C_OUT_FLAG : STD_LOGIC;
signal FlagRegisters_INTERRUPT : STD_LOGIC_VECTOR ( 0 to 0 );
signal FlagRegisters_Z_OUT_FLAG : STD_LOGIC;
signal I_CLR_1 : STD_LOGIC;
signal I_SET_1 : STD_LOGIC;
signal Op2_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ProgramROM_SLICED_IMMED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ProgramROM_SLICED_IMMED_VAL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ProgramROM_SLICED_OPCODE_HI_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ProgramROM_SLICED_OPCODE_LO_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal REG_WRSEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal RST_1 : STD_LOGIC;
signal Registers_REGOUT_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Registers_REGOUT_Y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal WE_1 : STD_LOGIC;
signal Z_CLR_1 : STD_LOGIC;
signal Z_LD_1 : STD_LOGIC;
signal Z_SET_1 : STD_LOGIC;
signal NLW_ControlUnit_0_C_FLAG_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_IO_OE_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_PC_OE_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_PC_RESET_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_REG_IMMED_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_RF_OE_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SCR_OE_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SCR_WR_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SHAD_C_LD_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SHAD_Z_LD_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SP_LD_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SP_RESET_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_Z_FLAG_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_ControlUnit_0_SCR_ADDR_SEL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_ControlUnit_0_SP_MUX_SEL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
CLK_1 <= CLK;
DIN_PORT_1(7 downto 0) <= DIN_PORT(7 downto 0);
OUT_PORT(7 downto 0) <= Registers_REGOUT_X(7 downto 0);
Op2_1(0) <= EXT_INTERRRUPT(0);
PORT_ID(7 downto 0) <= ProgramROM_SLICED_IMMED_VAL(7 downto 0);
RST_1 <= RST;
ALU: entity work.ALU_imp_CAYOB2
port map (
ALU_OPY_SEL => ALU_OPY_SEL_1,
ALU_Sel(3 downto 0) => ALU_Sel_1(3 downto 0),
C_FLAG => ALU_C_FLAG,
C_IN => FlagRegisters_C_OUT_FLAG,
IMMED(7 downto 0) => ProgramROM_SLICED_IMMED_VAL(7 downto 0),
REGOUT_X(7 downto 0) => Registers_REGOUT_X(7 downto 0),
REGOUT_Y(7 downto 0) => Registers_REGOUT_Y(7 downto 0),
SUM(7 downto 0) => ALU_RESULT_1(7 downto 0),
Z_FLAG => ALU_Z_FLAG
);
ControlUnit_0: component RAT_ControlUnit_0_0
port map (
ALU_OPY_SEL => ALU_OPY_SEL_1,
ALU_SEL(3 downto 0) => ALU_Sel_1(3 downto 0),
C => FlagRegisters_C_OUT_FLAG,
CLK => CLK_1,
C_FLAG_CLR => C_CLR_1,
C_FLAG_LD => C_LD_1,
C_FLAG_SEL => NLW_ControlUnit_0_C_FLAG_SEL_UNCONNECTED,
C_FLAG_SET => C_SET_1,
INT => FlagRegisters_INTERRUPT(0),
IO_OE => NLW_ControlUnit_0_IO_OE_UNCONNECTED,
I_FLAG_CLR => I_CLR_1,
I_FLAG_SET => I_SET_1,
OPCODE_HI_5(4 downto 0) => ProgramROM_SLICED_OPCODE_HI_5(4 downto 0),
OPCODE_LO_2(1 downto 0) => ProgramROM_SLICED_OPCODE_LO_2(1 downto 0),
PC_INC => ControlUnit_0_PC_INC,
PC_LD => ControlUnit_0_PC_LD,
PC_MUX_SEL(1 downto 0) => ControlUnit_0_PC_MUX_SEL(1 downto 0),
PC_OE => NLW_ControlUnit_0_PC_OE_UNCONNECTED,
PC_RESET => NLW_ControlUnit_0_PC_RESET_UNCONNECTED,
REG_IMMED_SEL => NLW_ControlUnit_0_REG_IMMED_SEL_UNCONNECTED,
RF_OE => NLW_ControlUnit_0_RF_OE_UNCONNECTED,
RF_WR => WE_1,
RF_WR_SEL(1 downto 0) => REG_WRSEL_1(1 downto 0),
RST => RST_1,
SCR_ADDR_SEL(1 downto 0) => NLW_ControlUnit_0_SCR_ADDR_SEL_UNCONNECTED(1 downto 0),
SCR_OE => NLW_ControlUnit_0_SCR_OE_UNCONNECTED,
SCR_WR => NLW_ControlUnit_0_SCR_WR_UNCONNECTED,
SHAD_C_LD => NLW_ControlUnit_0_SHAD_C_LD_UNCONNECTED,
SHAD_Z_LD => NLW_ControlUnit_0_SHAD_Z_LD_UNCONNECTED,
SP_LD => NLW_ControlUnit_0_SP_LD_UNCONNECTED,
SP_MUX_SEL(1 downto 0) => NLW_ControlUnit_0_SP_MUX_SEL_UNCONNECTED(1 downto 0),
SP_RESET => NLW_ControlUnit_0_SP_RESET_UNCONNECTED,
Z => FlagRegisters_Z_OUT_FLAG,
Z_FLAG_CLR => Z_CLR_1,
Z_FLAG_LD => Z_LD_1,
Z_FLAG_SEL => NLW_ControlUnit_0_Z_FLAG_SEL_UNCONNECTED,
Z_FLAG_SET => Z_SET_1
);
FlagRegisters: entity work.FlagRegisters_imp_9QD03I
port map (
CLK => CLK_1,
C_CLR => C_CLR_1,
C_IN_FLAG => ALU_C_FLAG,
C_LD => C_LD_1,
C_OUT_FLAG => FlagRegisters_C_OUT_FLAG,
C_SET => C_SET_1,
EXT_INTERRUPT(0) => Op2_1(0),
INTERRUPT(0) => FlagRegisters_INTERRUPT(0),
I_CLR => I_CLR_1,
I_SET => I_SET_1,
Z_CLR => Z_CLR_1,
Z_IN_FLAG => ALU_Z_FLAG,
Z_LD => Z_LD_1,
Z_OUT_FLAG => FlagRegisters_Z_OUT_FLAG,
Z_SET => Z_SET_1
);
ProgramCounter: entity work.ProgramCounter_imp_FFPXUZ
port map (
ADDRESS(0 to 9) => ADDRESS_1(0 to 9),
CLK => CLK_1,
FROM_IMMED(9 downto 0) => ProgramROM_SLICED_IMMED(9 downto 0),
INC => ControlUnit_0_PC_INC,
LOAD => ControlUnit_0_PC_LD,
SEL(1 downto 0) => ControlUnit_0_PC_MUX_SEL(1 downto 0)
);
ProgramROM_SLICED: entity work.ProgramROM_SLICED_imp_MYEMEW
port map (
ADDRESS(0 to 9) => ADDRESS_1(0 to 9),
ADDRX(4 downto 0) => ADRX_1(4 downto 0),
ADDRY(4 downto 0) => ADRY_1(4 downto 0),
CLK => CLK_1,
IMMED(9 downto 0) => ProgramROM_SLICED_IMMED(9 downto 0),
IMMED_VAL(7 downto 0) => ProgramROM_SLICED_IMMED_VAL(7 downto 0),
OPCODE_HI_5(4 downto 0) => ProgramROM_SLICED_OPCODE_HI_5(4 downto 0),
OPCODE_LO_2(1 downto 0) => ProgramROM_SLICED_OPCODE_LO_2(1 downto 0)
);
Registers: entity work.Registers_imp_1M200Q6
port map (
ADRX(4 downto 0) => ADRX_1(4 downto 0),
ADRY(4 downto 0) => ADRY_1(4 downto 0),
ALU_RESULT(7 downto 0) => ALU_RESULT_1(7 downto 0),
CLK => CLK_1,
DIN_PORT(7 downto 0) => DIN_PORT_1(7 downto 0),
REGOUT_X(7 downto 0) => Registers_REGOUT_X(7 downto 0),
REGOUT_Y(7 downto 0) => Registers_REGOUT_Y(7 downto 0),
REG_WRSEL(1 downto 0) => REG_WRSEL_1(1 downto 0),
WE => WE_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT is
port (
CLK : in STD_LOGIC;
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RAT : entity is "RAT,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=RAT,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=25,numReposBlks=19,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=2,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=11,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of RAT : entity is "RAT.hwdef";
end RAT;
architecture STRUCTURE of RAT is
signal CLK_1 : STD_LOGIC;
signal DIN_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Op2_2 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ProgramROM_SLICED_Dout3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RATCPU_REGOUT_X : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RST_1 : STD_LOGIC;
begin
CLK_1 <= CLK;
DIN_1(7 downto 0) <= IN_PORT(7 downto 0);
OUT_PORT(7 downto 0) <= RATCPU_REGOUT_X(7 downto 0);
Op2_2(0) <= INT_IN(0);
PORT_ID(7 downto 0) <= ProgramROM_SLICED_Dout3(7 downto 0);
RST_1 <= RST;
RATCPU: entity work.RATCPU_imp_157ITB6
port map (
CLK => CLK_1,
DIN_PORT(7 downto 0) => DIN_1(7 downto 0),
EXT_INTERRRUPT(0) => Op2_2(0),
OUT_PORT(7 downto 0) => RATCPU_REGOUT_X(7 downto 0),
PORT_ID(7 downto 0) => ProgramROM_SLICED_Dout3(7 downto 0),
RST => RST_1
);
end STRUCTURE;
| mit | fca4ecc5638616e447bd434d22c5cbb7 | 0.613072 | 2.90347 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/noah-huesser/dec_to_fir_mux_v1_0/src/dec_to_fir_mux.vhd | 2 | 1,576 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity dec_to_fir_mux is
port (
DecRate: in std_logic_vector(31 downto 0);
Mux3: out std_logic_vector(1 downto 0);
Mux2: out std_logic_vector(1 downto 0);
Mux1: out std_logic_vector(1 downto 0);
Mux0: out std_logic_vector(1 downto 0)
);
end dec_to_fir_mux;
architecture V1 of dec_to_fir_mux is
begin
-- Persistent signal mappings
p_converter: process(DecRate)
begin
case to_integer(unsigned(DecRate)) is
when 5 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "00";
when 25 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "01";
Mux3 <= "00";
when 125 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "01";
when 625 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "01";
Mux3 <= "01";
when 1250 =>
Mux0 <= "01";
Mux1 <= "10";
Mux2 <= "00";
Mux3 <= "10";
when 2500 =>
Mux0 <= "01";
Mux1 <= "01";
Mux2 <= "00";
Mux3 <= "10";
when others =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "00";
end case;
end process;
end V1;
| mit | c499a334b0f5b068c80772c490330b0e | 0.378173 | 3.843902 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/synth/RAT_RegisterFile_0_0.vhd | 2 | 4,275 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:RegisterFile:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_RegisterFile_0_0 IS
PORT (
D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DY_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADRX : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ADRY : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END RAT_RegisterFile_0_0;
ARCHITECTURE RAT_RegisterFile_0_0_arch OF RAT_RegisterFile_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_RegisterFile_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT RegisterFile IS
PORT (
D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DY_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADRX : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ADRY : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END COMPONENT RegisterFile;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_RegisterFile_0_0_arch: ARCHITECTURE IS "RegisterFile,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_RegisterFile_0_0_arch : ARCHITECTURE IS "RAT_RegisterFile_0_0,RegisterFile,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_RegisterFile_0_0_arch: ARCHITECTURE IS "RAT_RegisterFile_0_0,RegisterFile,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=RegisterFile,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : RegisterFile
PORT MAP (
D_IN => D_IN,
DX_OUT => DX_OUT,
DY_OUT => DY_OUT,
ADRX => ADRX,
ADRY => ADRY,
WE => WE,
CLK => CLK
);
END RAT_RegisterFile_0_0_arch;
| mit | d0b86d330a10bb87504a810417ed2a9d | 0.727251 | 3.896992 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_sim_netlist.vhdl | 2 | 5,305 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_sim_netlist.vhdl
-- Design : RAT_Mux4x1_10_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_10_0_0_Mux4x1_10 is
port (
X : out STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
A : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Mux4x1_10_0_0_Mux4x1_10 : entity is "Mux4x1_10";
end RAT_Mux4x1_10_0_0_Mux4x1_10;
architecture STRUCTURE of RAT_Mux4x1_10_0_0_Mux4x1_10 is
begin
\X[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(0),
I1 => B(0),
I2 => C(0),
I3 => SEL(1),
I4 => A(0),
I5 => SEL(0),
O => X(0)
);
\X[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(1),
I1 => B(1),
I2 => C(1),
I3 => SEL(1),
I4 => A(1),
I5 => SEL(0),
O => X(1)
);
\X[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(2),
I1 => B(2),
I2 => C(2),
I3 => SEL(1),
I4 => A(2),
I5 => SEL(0),
O => X(2)
);
\X[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(3),
I1 => B(3),
I2 => C(3),
I3 => SEL(1),
I4 => A(3),
I5 => SEL(0),
O => X(3)
);
\X[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(4),
I1 => B(4),
I2 => C(4),
I3 => SEL(1),
I4 => A(4),
I5 => SEL(0),
O => X(4)
);
\X[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(5),
I1 => B(5),
I2 => C(5),
I3 => SEL(1),
I4 => A(5),
I5 => SEL(0),
O => X(5)
);
\X[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(6),
I1 => B(6),
I2 => C(6),
I3 => SEL(1),
I4 => A(6),
I5 => SEL(0),
O => X(6)
);
\X[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(7),
I1 => B(7),
I2 => C(7),
I3 => SEL(1),
I4 => A(7),
I5 => SEL(0),
O => X(7)
);
\X[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(8),
I1 => B(8),
I2 => C(8),
I3 => SEL(1),
I4 => A(8),
I5 => SEL(0),
O => X(8)
);
\X[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(9),
I1 => B(9),
I2 => C(9),
I3 => SEL(1),
I4 => A(9),
I5 => SEL(0),
O => X(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_10_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Mux4x1_10_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Mux4x1_10_0_0 : entity is "RAT_Mux4x1_10_0_0,Mux4x1_10,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Mux4x1_10_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Mux4x1_10_0_0 : entity is "Mux4x1_10,Vivado 2016.4";
end RAT_Mux4x1_10_0_0;
architecture STRUCTURE of RAT_Mux4x1_10_0_0 is
begin
U0: entity work.RAT_Mux4x1_10_0_0_Mux4x1_10
port map (
A(9 downto 0) => A(9 downto 0),
B(9 downto 0) => B(9 downto 0),
C(9 downto 0) => C(9 downto 0),
D(9 downto 0) => D(9 downto 0),
SEL(1 downto 0) => SEL(1 downto 0),
X(9 downto 0) => X(9 downto 0)
);
end STRUCTURE;
| mit | 124f9f618a1480f610f649dfc060c1de | 0.51574 | 2.903667 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/Testbenches/EXP_7_8_cpu_wrapper_tb.vhd | 2 | 1,803 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/07/2016 04:39:42 PM
-- Design Name:
-- Module Name: EXP8_wrrapper_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EXP8_wrapper_tb is
end EXP8_wrapper_tb;
architecture Behavioral of EXP8_wrapper_tb is
component RAT_Basys3_wrapper
Port( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
signal switches_tb : std_logic_vector(7 downto 0) :="00000000";
signal leds_tb : std_logic_vector(7 downto 0) :="00000000";
signal clk_tb : std_logic := '0';
signal rst_tb : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut: RAT_Basys3_wrapper PORT MAP (
LEDS => leds_tb,
SWITCHES => switches_tb,
RST => rst_tb,
CLK => clk_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst_tb <= '1';
switches_tb <= "10101010";
wait for 50 ns;
rst_tb <= '0';
wait;
end process;
end Behavioral;
| mit | d3b80e5790617600f66a500000b7cb96 | 0.489739 | 3.84435 | false | false | false | false |
BBN-Q/VHDL-Components | src/PhaseGenerator.vhd | 1 | 1,443 | -- Simple truncating phase generator with additional 90 degree shifted output
--
-- Original author Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator is
generic (
ACCUMULATOR_WIDTH : natural := 32;
OUTPUT_WIDTH : natural := 16
);
port (
clk : in std_logic;
rst : in std_logic;
phase_increment : in std_logic_vector(ACCUMULATOR_WIDTH-1 downto 0);
phase_offset : in std_logic_vector(ACCUMULATOR_WIDTH-1 downto 0);
phase : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
vld : out std_logic
);
end entity;
architecture arch of PhaseGenerator is
signal accum : unsigned(ACCUMULATOR_WIDTH-1 downto 0);
signal phase_int : unsigned(ACCUMULATOR_WIDTH-1 downto 0);
signal phase_offset_d : unsigned(ACCUMULATOR_WIDTH-1 downto 0);
begin
--Main accumulation process
main : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
accum <= (others => '0');
phase_offset_d <= (others => '0');
phase_int <= (others => '0');
else
accum <= accum + unsigned(phase_increment);
--register to align increment and offset updates
phase_offset_d <= unsigned(phase_offset);
phase_int <= accum + phase_offset_d;
end if;
end if;
end process;
--Truncate output
phase <= std_logic_vector(phase_int(accum'high downto accum'high-OUTPUT_WIDTH+1));
end architecture;
| mpl-2.0 | 9731dd7e000d8d3b9d99641a2ed0cf64 | 0.684685 | 3.348028 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/RTL/ControlUnit.vhd | 1 | 15,615 | ----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 20:59:29 02/04/2013
-- Design Name:
-- Module Name: RAT_CPU - Behavioral
-- Project Name: RAT MCU
-- Target Devices:
-- Tool versions:
-- Description: This is the control unit of the RAT MCU.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ControlUnit is
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_LD : out STD_LOGIC;
SP_RESET : out STD_LOGIC;
SP_INCR : out STD_LOGIC;
SP_DECR : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SCR_DATA_SEL : out STD_LOGIC;
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC);
end ControlUnit;
architecture Behavioral of ControlUnit is
-- State machine signals
type state_type is (ST_init, ST_fet, ST_exec, ST_int);
signal PS,NS : state_type;
-- Opcode
signal sig_OPCODE_7: std_logic_vector (6 downto 0);
begin
-- Assign next state
sync_p: process (CLK, NS, RST)
begin
if (RST = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
-- Translate instruction to signals
comb_p: process (OPCODE_HI_5, OPCODE_LO_2, sig_OPCODE_7, C, Z, PS, NS, INT) begin
sig_OPCODE_7 <= OPCODE_HI_5 & OPCODE_LO_2;
case PS is
-- STATE: the init cycle ------------------------------------
when ST_init =>
NS <= ST_fet;
-- Initialize all control outputs to non-active states and reset the PC and SP to all zeros.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '1'; PC_INC <= '0';
SP_LD <= '0'; SP_RESET <= '1'; SP_INCR <= '0'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "00"; SCR_DATA_SEL<= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the fetch cycle -----------------------------------
when ST_fet =>
NS <= ST_exec;
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_INC <= '1';
SP_LD <= '0'; SP_RESET <= '0'; SP_INCR <= '0'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "00"; SCR_DATA_SEL<= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if (INT = '1') then
NS <= ST_int;
else
NS <= ST_fet;
end if;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_RESET <= '0'; SP_INCR <= '0'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "00"; SCR_DATA_SEL<= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
if (sig_OPCODE_7 = "0000100") then -- ADD reg-reg
RF_WR <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10100" ) then -- ADD reg-immed
ALU_OPY_SEL <= '1';
RF_WR <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000101") then -- ADDC reg-reg
RF_WR <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10101" ) then -- ADDC reg-immed
ALU_OPY_SEL <= '1';
RF_WR <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000000") then -- AND reg-reg
RF_WR <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10000" ) then -- AND reg-immed
ALU_OPY_SEL <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100100") then -- ASR reg-reg
RF_WR <= '1';
ALU_SEL <= "1101";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0010101") then -- BRCC
if (c = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010100") then -- BRCS
if (c = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010010") then -- BREQ
if (Z = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010000") then -- BRN
PC_LD <= '1';
elsif (sig_OPCODE_7 = "0010011") then -- BRNE
if (Z = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010001") then -- CALL
PC_LD <= '1';
SP_LD <= '1';
SCR_ADDR_SEL <= "10";
SCR_ADDR_SEL <= "11";
SCR_WR <= '1';
elsif (sig_OPCODE_7 = "0110000") then -- CLC
C_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110101") then -- CLI (INT)
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0001000") then -- CMP reg-reg
ALU_SEL <= "0100";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11000" ) then -- CMP reg-immed
ALU_SEL <= "0100";
ALU_OPY_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000010") then -- EXOR reg-reg
RF_WR <= '1';
ALU_SEL <= "0111";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10010" ) then -- EXOR reg-immed
RF_WR <= '1';
ALU_SEL <= "0111";
ALU_OPY_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11001" ) then -- IN
RF_WR <= '1';
RF_WR_SEL <= "11";
elsif (sig_OPCODE_7 = "0001010") then -- LD reg-reg
SCR_ADDR_SEL <= "00";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (OPCODE_HI_5 = "11100" ) then -- LD reg-immed
SCR_ADDR_SEL <= "01";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (sig_OPCODE_7 = "0100000") then -- LSL
RF_WR <= '1';
ALU_SEL <= "1001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100001") then -- LSR
RF_WR <= '1';
ALU_SEL <= "1010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0001001") then -- MOV reg-reg
RF_WR <= '1';
ALU_SEL <= "1110";
elsif (OPCODE_HI_5 = "11011" ) then -- MOV reg-immed
RF_WR <= '1';
ALU_SEL <= "1110";
ALU_OPY_SEL <= '1';
elsif (sig_OPCODE_7 = "0000001") then -- OR reg-reg
RF_WR <= '1';
ALU_SEL <= "0110";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10001" ) then -- OR reg-immed
RF_WR <= '1';
ALU_SEL <= "0110";
ALU_OPY_SEL <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11010" ) then -- OUT
IO_OE <= '1';
elsif (sig_OPCODE_7 = "0100110") then -- POP
SCR_ADDR_SEL <= "10";
RF_WR <= '1';
RF_WR_SEL <= "01";
SCR_ADDR_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0100101") then -- PUSH
SCR_WR <= '1';
SCR_ADDR_SEL <= "11";
SCR_ADDR_SEL <= "10";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110010") then -- RET
SCR_ADDR_SEL <= "10";
PC_MUX_SEL <= "01";
PC_LD <= '1';
SCR_ADDR_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110110") then -- RETID (INT)
SCR_ADDR_SEL <= "10";
PC_MUX_SEL <= "01";
PC_LD <= '1';
SCR_ADDR_SEL <= "11";
SP_LD <= '1';
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110111") then -- RETIE (INT)
SCR_ADDR_SEL <= "10";
PC_MUX_SEL <= "01";
PC_LD <= '1';
SCR_ADDR_SEL <= "11";
SP_LD <= '1';
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0100010") then -- ROL
RF_WR <= '1';
ALU_SEL <= "1011";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100011") then -- ROR
RF_WR <= '1';
ALU_SEL <= "1100";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0110001") then -- SEC
C_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0110100") then -- SEI (INT)
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0001011") then -- ST reg-reg
SCR_WR <= '1';
elsif (OPCODE_HI_5 = "11101" ) then -- ST reg-immed
SCR_WR <= '1';
SCR_ADDR_SEL <= "01";
elsif (sig_OPCODE_7 = "0000110") then -- SUB reg-reg
RF_WR <= '1';
ALU_SEL <= "0010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10110" ) then -- SUB reg-immed
RF_WR <= '1';
ALU_SEL <= "0010";
ALU_OPY_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000111") then -- SUBC reg-reg
RF_WR <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10111" ) then -- SUBC reg-immed
ALU_OPY_SEL <= '1';
RF_WR <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000011") then -- TEST reg-reg
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10011" ) then -- TEST reg-immed
ALU_OPY_SEL <= '1';
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0101000") then -- WSP
SCR_ADDR_SEL <= "00";
SP_LD <= '1';
else
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_RESET <= '0'; SP_INCR <= '0'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "00"; SCR_DATA_SEL <= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end if;
-- STATE: the interrupt cycle -----------------------------------
when ST_int =>
NS <= ST_fet;
PC_LD <= '1'; PC_MUX_SEL <= "10"; PC_RESET <= '0'; PC_INC <= '0';
SP_LD <= '1'; SP_RESET <= '0'; SP_INCR <= '1'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "11"; SCR_DATA_SEL<= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '1'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
when others =>
NS <= ST_fet;
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '1'; PC_INC <= '0';
SP_LD <= '0'; SP_RESET <= '1'; SP_INCR <= '0'; SP_DECR <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_ADDR_SEL <= "00"; SCR_DATA_SEL<= '0';
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end case;
end process comb_p;
end Behavioral; | mit | c244183ab279aa3ca59c1bdc97ff69e9 | 0.40333 | 2.899721 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/src/Program_Counter_Mux4x1_0_1.vhd | 2 | 3,724 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "Mux4x1,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Program_Counter_Mux4x1_0_1_arch : ARCHITECTURE IS "Program_Counter_Mux4x1_0_1,Mux4x1,{}";
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
| mit | 453752b2ee78c5a8215975e4c743f1be | 0.720999 | 3.754032 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/ram2k_8.vhd | 1 | 1,210 | --
-- An array of 2048 bytes that works as a framebuffer for the vgaDriverBuffer
-- module. Holds the RGB pixel data for each location.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram2k_8 is
port(clk: in STD_LOGIC;
we: in STD_LOGIC;
ra, wa: in STD_LOGIC_VECTOR(10 downto 0);
wd: in STD_LOGIC_VECTOR(7 downto 0);
rd: out STD_LOGIC_VECTOR(7 downto 0);
pixelVal: out STD_LOGIC_VECTOR(7 downto 0)
);
end ram2k_8;
architecture Behavioral of ram2k_8 is
type ramtype is array (2047 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal mem: ramtype := (OTHERS => "11100000");
begin
-- three-ported register file
-- read two ports combinationally
-- write third port on rising edge of clock
process(clk) begin
if (clk'event and clk = '1') then
if we = '1' then mem(CONV_INTEGER(wa)) <= wd;
end if;
end if;
end process;
rd <= mem(CONV_INTEGER(ra));
pixelVal <= mem(CONV_INTEGER(wa));
end Behavioral;
| mit | bb2b29e5fc151982a08750e33faa1c08 | 0.628926 | 3.389356 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.vhdl | 1 | 8,939 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.vhdl
-- Design : RAT_Counter10bit_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Counter10bit_0_0_Counter10bit is
port (
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR ( 0 to 9 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Counter10bit_0_0_Counter10bit : entity is "Counter10bit";
end RAT_Counter10bit_0_0_Counter10bit;
architecture STRUCTURE of RAT_Counter10bit_0_0_Counter10bit is
signal \^count\ : STD_LOGIC_VECTOR ( 0 to 9 );
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \s_COUNT[0]_i_1_n_0\ : STD_LOGIC;
signal \s_COUNT[0]_i_3_n_0\ : STD_LOGIC;
signal \s_COUNT[1]_i_2_n_0\ : STD_LOGIC;
signal \s_COUNT[4]_i_2_n_0\ : STD_LOGIC;
signal \s_COUNT[5]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_COUNT[0]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_COUNT[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_COUNT[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_COUNT[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_COUNT[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \s_COUNT[9]_i_1\ : label is "soft_lutpair2";
begin
COUNT(0 to 9) <= \^count\(0 to 9);
\s_COUNT[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => LOAD,
I1 => INC,
O => \s_COUNT[0]_i_1_n_0\
);
\s_COUNT[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(0),
I1 => LOAD,
I2 => \s_COUNT[0]_i_3_n_0\,
I3 => \^count\(1),
I4 => \^count\(0),
O => p_0_in(9)
);
\s_COUNT[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^count\(2),
I1 => \s_COUNT[1]_i_2_n_0\,
I2 => \^count\(3),
O => \s_COUNT[0]_i_3_n_0\
);
\s_COUNT[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BBBBBBBB8888888"
)
port map (
I0 => Din(1),
I1 => LOAD,
I2 => \^count\(3),
I3 => \s_COUNT[1]_i_2_n_0\,
I4 => \^count\(2),
I5 => \^count\(1),
O => p_0_in(8)
);
\s_COUNT[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^count\(4),
I1 => \^count\(6),
I2 => \^count\(8),
I3 => \^count\(9),
I4 => \^count\(7),
I5 => \^count\(5),
O => \s_COUNT[1]_i_2_n_0\
);
\s_COUNT[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(2),
I1 => LOAD,
I2 => \s_COUNT[1]_i_2_n_0\,
I3 => \^count\(3),
I4 => \^count\(2),
O => p_0_in(7)
);
\s_COUNT[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(3),
I1 => LOAD,
I2 => \s_COUNT[1]_i_2_n_0\,
I3 => \^count\(3),
O => p_0_in(6)
);
\s_COUNT[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(4),
I1 => LOAD,
I2 => \s_COUNT[4]_i_2_n_0\,
I3 => \^count\(4),
O => p_0_in(5)
);
\s_COUNT[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^count\(5),
I1 => \^count\(7),
I2 => \^count\(9),
I3 => \^count\(8),
I4 => \^count\(6),
O => \s_COUNT[4]_i_2_n_0\
);
\s_COUNT[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(5),
I1 => LOAD,
I2 => \s_COUNT[5]_i_2_n_0\,
I3 => \^count\(5),
O => p_0_in(4)
);
\s_COUNT[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^count\(6),
I1 => \^count\(8),
I2 => \^count\(9),
I3 => \^count\(7),
O => \s_COUNT[5]_i_2_n_0\
);
\s_COUNT[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BBBBBBBB8888888"
)
port map (
I0 => Din(6),
I1 => LOAD,
I2 => \^count\(8),
I3 => \^count\(9),
I4 => \^count\(7),
I5 => \^count\(6),
O => p_0_in(3)
);
\s_COUNT[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBB888"
)
port map (
I0 => Din(7),
I1 => LOAD,
I2 => \^count\(9),
I3 => \^count\(8),
I4 => \^count\(7),
O => p_0_in(2)
);
\s_COUNT[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Din(8),
I1 => LOAD,
I2 => \^count\(9),
I3 => \^count\(8),
O => p_0_in(1)
);
\s_COUNT[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Din(9),
I1 => LOAD,
I2 => \^count\(9),
O => p_0_in(0)
);
\s_COUNT_reg[0]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(9),
Q => \^count\(0)
);
\s_COUNT_reg[1]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(8),
Q => \^count\(1)
);
\s_COUNT_reg[2]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(7),
Q => \^count\(2)
);
\s_COUNT_reg[3]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(6),
Q => \^count\(3)
);
\s_COUNT_reg[4]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(5),
Q => \^count\(4)
);
\s_COUNT_reg[5]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(4),
Q => \^count\(5)
);
\s_COUNT_reg[6]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(3),
Q => \^count\(6)
);
\s_COUNT_reg[7]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(2),
Q => \^count\(7)
);
\s_COUNT_reg[8]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(1),
Q => \^count\(8)
);
\s_COUNT_reg[9]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => \s_COUNT[0]_i_1_n_0\,
CLR => RESET,
D => p_0_in(0),
Q => \^count\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Counter10bit_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Counter10bit_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Counter10bit_0_0 : entity is "RAT_Counter10bit_0_0,Counter10bit,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Counter10bit_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Counter10bit_0_0 : entity is "Counter10bit,Vivado 2016.4";
end RAT_Counter10bit_0_0;
architecture STRUCTURE of RAT_Counter10bit_0_0 is
begin
U0: entity work.RAT_Counter10bit_0_0_Counter10bit
port map (
CLK => CLK,
COUNT(0 to 9) => COUNT(0 to 9),
Din(0 to 9) => Din(0 to 9),
INC => INC,
LOAD => LOAD,
RESET => RESET
);
end STRUCTURE;
| mit | 1b99ec9b1b19fdc4372a1915fe22a607 | 0.505761 | 2.853176 | false | false | false | false |
BBN-Q/VHDL-Components | src/ComplexMultiplier.vhd | 1 | 3,510 | -- Fully pipelined complex AXI stream multiplier with generic widths
--
-- Original author Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ComplexMultiplier is
generic (
A_WIDTH : natural := 16;
B_WIDTH : natural := 16;
PROD_WIDTH : natural := 16;
-- normally complex multiplication grows by one bit e.g. -1-1im * -1-1im = 0 + 2im
-- divide output by BIT_SHIFT if overflow not a concern e.g. multplying by e^i\theta
BIT_SHIFT : natural := 0
);
port (
clk : in std_logic;
rst : in std_logic;
a_data_re : in std_logic_vector(A_WIDTH-1 downto 0);
a_data_im : in std_logic_vector(A_WIDTH-1 downto 0);
a_vld : in std_logic;
a_last : in std_logic;
b_data_re : in std_logic_vector(B_WIDTH-1 downto 0);
b_data_im : in std_logic_vector(B_WIDTH-1 downto 0);
b_vld : in std_logic;
b_last : in std_logic;
prod_data_re : out std_logic_vector(PROD_WIDTH-1 downto 0);
prod_data_im : out std_logic_vector(PROD_WIDTH-1 downto 0);
prod_vld : out std_logic;
prod_last : out std_logic
);
end entity;
architecture arch of ComplexMultiplier is
signal a_reg_re, a_reg_im : signed(A_WIDTH-1 downto 0);
signal b_reg_re, b_reg_im : signed(B_WIDTH-1 downto 0);
constant PROD_WIDTH_INT : natural := A_WIDTH + B_WIDTH;
signal prod1, prod2, prod3, prod4 : signed(PROD_WIDTH_INT-1 downto 0);
signal sum_re, sum_im : signed(PROD_WIDTH_INT-1 downto 0);
--How to slice the output sum
subtype OUTPUT_SLICE is natural range (PROD_WIDTH_INT - 1 - BIT_SHIFT) downto (PROD_WIDTH_INT - BIT_SHIFT - PROD_WIDTH);
begin
main : process( clk )
begin
if rising_edge(clk) then
if rst = '1' then
a_reg_re <= (others => '0');
a_reg_im <= (others => '0');
b_reg_re <= (others => '0');
b_reg_im <= (others => '0');
prod1 <= (others => '0');
prod2 <= (others => '0');
prod3 <= (others => '0');
prod4 <= (others => '0');
sum_re <= (others => '0');
sum_im <= (others => '0');
prod_data_re <= (others => '0');
prod_data_im <= (others => '0');
else
--Register inputs
a_reg_re <= signed(a_data_re);
a_reg_im <= signed(a_data_im);
b_reg_re <= signed(b_data_re);
b_reg_im <= signed(b_data_im);
--Pipeline intermediate products
prod1 <= a_reg_re * b_reg_re;
prod2 <= a_reg_re * b_reg_im;
prod3 <= a_reg_im * b_reg_re;
prod4 <= a_reg_im * b_reg_im;
--don't have to worry about overflow because signed multiplication already has extra bit
sum_re <= prod1 - prod4;
sum_im <= prod2 + prod3;
--Slice output to truncate
prod_data_re <= std_logic_vector( sum_re(OUTPUT_SLICE) );
prod_data_im <= std_logic_vector( sum_im(OUTPUT_SLICE) );
end if;
end if;
end process; -- main
--Delay the valid and last for the pipelining through the multiplier
--Currently this is 4 clocks: input register; products; additions; output register
--Both inputs have to be valid
delayLine_vld : entity work.DelayLine
generic map(DELAY_TAPS => 4)
port map(clk => clk, rst => rst, data_in(0) => (a_vld and b_vld), data_out(0) => prod_vld);
--Either last -- unaligned lasts is not defined behaviour
delayLine_last : entity work.DelayLine
generic map(DELAY_TAPS => 4)
port map(clk => clk, rst => rst, data_in(0) => (a_last or b_last), data_out(0) => prod_last);
end architecture;
| mpl-2.0 | c4d2272162b59bdaa776980e7e6c6e46 | 0.61339 | 3.111702 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_sim_netlist.vhdl | 1 | 11,590 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_sim_netlist.vhdl
-- Design : RAT_prog_rom_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_prog_rom_0_0_prog_rom is
port (
INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 );
CLK : in STD_LOGIC;
ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_prog_rom_0_0_prog_rom : entity is "prog_rom";
end RAT_prog_rom_0_0_prog_rom;
architecture STRUCTURE of RAT_prog_rom_0_0_prog_rom is
signal NLW_ram_1024_x_18_DIBDI_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_ram_1024_x_18_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of ram_1024_x_18 : label is "INDEPENDENT";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ram_1024_x_18 : label is "RAMB16_S18";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of ram_1024_x_18 : label is "ADDR[0]:ADDRARDADDR[4] ADDR[1]:ADDRARDADDR[5] ADDR[2]:ADDRARDADDR[6] ADDR[3]:ADDRARDADDR[7] ADDR[4]:ADDRARDADDR[8] ADDR[5]:ADDRARDADDR[9] ADDR[6]:ADDRARDADDR[10] ADDR[7]:ADDRARDADDR[11] ADDR[8]:ADDRARDADDR[12] ADDR[9]:ADDRARDADDR[13] CLK:CLKARDCLK DI[0]:DIADI[0] DI[10]:DIADI[10] DI[11]:DIADI[11] DI[12]:DIADI[12] DI[13]:DIADI[13] DI[14]:DIADI[14] DI[15]:DIADI[15] DI[1]:DIADI[1] DI[2]:DIADI[2] DI[3]:DIADI[3] DI[4]:DIADI[4] DI[5]:DIADI[5] DI[6]:DIADI[6] DI[7]:DIADI[7] DI[8]:DIADI[8] DI[9]:DIADI[9] DIP[0]:DIPADIP[0] DIP[1]:DIPADIP[1] DO[0]:DOADO[0] DO[10]:DOADO[10] DO[11]:DOADO[11] DO[12]:DOADO[12] DO[13]:DOADO[13] DO[14]:DOADO[14] DO[15]:DOADO[15] DO[1]:DOADO[1] DO[2]:DOADO[2] DO[3]:DOADO[3] DO[4]:DOADO[4] DO[5]:DOADO[5] DO[6]:DOADO[6] DO[7]:DOADO[7] DO[8]:DOADO[8] DO[9]:DOADO[9] DOP[0]:DOPADOP[0] DOP[1]:DOPADOP[1] EN:ENARDEN SSR:RSTRAMARSTRAM WE:WEA[1],WEA[0]";
attribute box_type : string;
attribute box_type of ram_1024_x_18 : label is "PRIMITIVE";
begin
ram_1024_x_18: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"22CB22CB20B232C8F2CE3738DCE3738ECE3B38EF38E340E340E3038C0E30FFFC",
INITP_01 => X"3CE3038C38FCE30E30E30E34D34D35DDDDCE35DCE37DCE3DDCE3DFCE218B218B",
INITP_02 => X"488BBB42004FDD373AA833D3833CE0CF4E0CF38398C3A30E630EEF38FCE3CCE3",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000004EF0",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"44098BA154403401806B030A0310430962AA610F6B016A0074005E817E010000",
INIT_01 => X"06004A5846098BA15440340480DB05A5051245098BA15440340280A304AF0411",
INIT_02 => X"8C01544034E08BA154403410815B078707014A5847098BA154403408811B061F",
INIT_03 => X"6AAB8BA15F403F0281EB0AFF2AAA6A558BA15F403F0181B30A110ADB6A357F00",
INIT_04 => X"0A7F0A036AFE8BA15F403F08825B0AFE0A026A7F8BA15F403F0482230AFF4A54",
INIT_05 => X"047764778BA1810161008C015F403FE082CB0ADF2A006ABE8BA15F403F108293",
INIT_06 => X"8380C10483808BA1810441408350C102835304668BA1810241408318C101831A",
INIT_07 => X"8400C110A401841164778BA18110414083C0C108A3C0845564FF8BA181084140",
INIT_08 => X"8480C140A4808001C4118BA1814041408440C120A441800084FF8BA181204140",
INIT_09 => X"6011410061D18BA15F403F0184DB015081FF200160505F407F008C0141408180",
INIT_0A => X"5F403F04857B01222102A0FF6022410061FF8BA15F403F02852B011181D02001",
INIT_0B => X"603320016022200160118BA15F403F0885CB0142210220016042410061008BA1",
INIT_0C => X"0122210286AB0133210286AB0144210286AB0155210220016055200160442001",
INIT_0D => X"870B01888B118BA15F403F2086DB01778B018BA15F403F1086AB0111210286AB",
INIT_0E => X"8BA15440340187730A016A0174008C015F403F80873B00598B398BA15F403F40",
INIT_0F => X"4DAA7502AA028BA15440340487DB0C014C5A4A5B8BA15440340287A30B014B51",
INIT_10 => X"0C018F04AA048BA154403410885B0E018E034AB376038BA154403408881B0D01",
INIT_11 => X"800124028BA14140012188E30203820262012401640061008C01544034E08893",
INIT_12 => X"E203800124088BA141400121895B0205C20224048BA14140012189230207A203",
INIT_13 => X"80018BA14F402F0189EB4C506C092A586B046A058C01414021F0012189A30201",
INIT_14 => X"2F048A834C506C012A5A6B046A058BA14F402F028A3B4C506C0A2A596B046A05",
INIT_15 => X"8AF84F402F802F402F202F102F088AF34C506C022A5B6B026A0580018BA14F40",
INIT_16 => X"402141014409200880028B61630A610160018002618880028B29613080026177",
INIT_17 => X"80028BAB3D008BBB3C008BCBDB017B5EDC017CFFDD017DFF80028B618B9AC301",
INIT_18 => X"0000000000000000000000000000000080028BA15E819E015F407F008BA18BA1",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
READ_WIDTH_A => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_WIDTH_A => 18
)
port map (
ADDRARDADDR(13 downto 4) => ADDRESS(9 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => CLK,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"0000000000000000",
DIBDI(15 downto 0) => NLW_ram_1024_x_18_DIBDI_UNCONNECTED(15 downto 0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED(1 downto 0),
DOADO(15 downto 0) => INSTRUCTION(15 downto 0),
DOBDO(15 downto 0) => NLW_ram_1024_x_18_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => INSTRUCTION(17 downto 16),
DOPBDOP(1 downto 0) => NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_prog_rom_0_0 is
port (
ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 );
INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 );
CLK : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_prog_rom_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_prog_rom_0_0 : entity is "RAT_prog_rom_0_0,prog_rom,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_prog_rom_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_prog_rom_0_0 : entity is "prog_rom,Vivado 2016.4";
end RAT_prog_rom_0_0;
architecture STRUCTURE of RAT_prog_rom_0_0 is
begin
U0: entity work.RAT_prog_rom_0_0_prog_rom
port map (
ADDRESS(9 downto 0) => ADDRESS(9 downto 0),
CLK => CLK,
INSTRUCTION(17 downto 0) => INSTRUCTION(17 downto 0)
);
end STRUCTURE;
| mit | d7caf40b2f4c2c7c0461a8fd450ebae9 | 0.739085 | 3.748383 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_MUX0_0/sim/design_1_MUX0_0.vhd | 2 | 6,083 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX0_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX0_0;
ARCHITECTURE design_1_MUX0_0_arch OF design_1_MUX0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX0_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX0_0_arch;
| mit | 5e41f8d1ba7268fa9f64ca8878ee5714 | 0.71034 | 3.691141 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_ArtyS7.vhdl | 1 | 10,395 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_ArtyS7 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 100.000 0.000 50.0 200.000 150.000
-- CLK_OUT1 200.000 0.000 50.0 300.000 150.000
-- CLK_OUT2 125.000 0.000 50.0 360.000 150.000
-- CLK_OUT3 10.000 0.000 50.0 300.000 150.000
--
architecture rtl of clknet_ClockNetwork_ArtyS7 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 24 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal DCM_Reset : STD_LOGIC;
signal DCM_Reset_clr : STD_LOGIC;
signal DCM_ResetState : STD_LOGIC := '0';
signal DCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 DOWNTO 0);
signal DCM_Locked_async : STD_LOGIC;
signal DCM_Locked : STD_LOGIC;
signal DCM_Locked_d : STD_LOGIC := '0';
signal DCM_Locked_re : STD_LOGIC;
signal DCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFG : STD_LOGIC;
signal DCM_Clock_10MHz : STD_LOGIC;
signal DCM_Clock_100MHz : STD_LOGIC;
signal DCM_Clock_125MHz : STD_LOGIC;
signal DCM_Clock_200MHz : STD_LOGIC;
signal DCM_Clock_10MHz_BUFG : STD_LOGIC;
signal DCM_Clock_100MHz_BUFG : STD_LOGIC;
signal DCM_Clock_125MHz_BUFG : STD_LOGIC;
signal DCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of DCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) DCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => DCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => DCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
DCM_Reset_clr <= ClkNet_Reset nor DCM_Locked;
-- detect rising edge on CMB locked signals
DCM_Locked_d <= DCM_Locked when rising_edge(Control_Clock);
DCM_Locked_re <= not DCM_Locked_d and DCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
DCM_ResetState <= ffrs(q => DCM_ResetState, rst => DCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
DCM_LockedState <= ffrs(q => DCM_LockedState, rst => DCM_Reset, set => DCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
DCM_Reset_delayed <= shreg_left(DCM_Reset_delayed, DCM_ResetState) when rising_edge(Control_Clock);
DCM_Reset <= DCM_Reset_delayed(DCM_Reset_delayed'high);
Locked <= DCM_LockedState and '1'; --PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFG
port map (
I => ClockIn_100MHz,
O => Control_Clock_BUFG
);
Control_Clock <= Control_Clock_BUFG;
-- 10 MHz BUFG
BUFG_DCM_Clock_10MHz : BUFG
port map (
I => DCM_Clock_10MHz,
O => DCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_DCM_Clock_100MHz : BUFG
port map (
I => DCM_Clock_100MHz,
O => DCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_DCM_Clock_125MHz : BUFG
port map (
I => DCM_Clock_125MHz,
O => DCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_DCM_Clock_200MHz : BUFG
port map (
I => DCM_Clock_200MHz,
O => DCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (DCM)
-- ==================================================================
System_DCM : DCM_SP
generic map (
STARTUP_WAIT => false,
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS"
PHASE_SHIFT => 0,
CLKIN_PERIOD => to_real(to_time(CLOCK_IN_FREQ), 1.0 ns),
CLKIN_DIVIDE_BY_2 => FALSE,
CLK_FEEDBACK => "1X",
CLKOUT_PHASE_SHIFT => "NONE",
CLKDV_DIVIDE => 10.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5
)
port map (
RST => DCM_Reset,
CLKIN => ClockIn_100MHz,
CLKFB => DCM_Clock_100MHz_BUFG,
CLK0 => DCM_Clock_100MHz,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => DCM_Clock_200MHz,
CLK2X180 => open,
CLKFX => DCM_Clock_125MHz,
CLKFX180 => open,
CLKDV => DCM_Clock_10MHz,
-- DCM status
LOCKED => DCM_Locked_async,
STATUS => open,
-- Dynamic Phase Shift Port
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
DSSEN => '0'
);
Control_Clock_100MHz <= Control_Clock_BUFG;
Clock_200MHz <= DCM_Clock_200MHz_BUFG;
Clock_125MHz <= DCM_Clock_125MHz_BUFG;
Clock_100MHz <= DCM_Clock_100MHz_BUFG;
Clock_10MHz <= DCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | 278ca299ba68951f95264e73c4c77dac | 0.535931 | 3.630807 | false | false | false | false |
alpenwasser/pitaya | doc/report/sandbox/code-listings/code/comparator.vhd | 1 | 1,270 | ----------------------------------------------------------------------------------
--
-- comparator.vhd
--
-- (c) 2015
-- L. Schrittwieser
-- N. Huesser
--
----------------------------------------------------------------------------------
--
-- Old descision piece for the trigger units; obsolete
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comparator is
generic (
Width : integer := 14
);
port (
AxDI : in unsigned(Width - 1 downto 0);
BxDI : in unsigned(Width - 1 downto 0);
GreaterxSO : out std_logic;
EqualxSO : out std_logic;
LowerxSO : out std_logic
);
end comparator;
architecture Behavioral of comparator is
begin
process(AxDI, BxDI)
begin
GreaterxSO <= '0';
EqualxSO <= '0';
LowerxSO <= '0';
if AxDI > BxDI then
GreaterxSO <= '1';
elsif AxDI = BxDI then
EqualxSO <= '1';
else
LowerxSO <= '1';
end if;
end process;
end Behavioral;
| mit | 0606f49830a46528995c2b01c5ee93c3 | 0.476378 | 4.45614 | false | false | false | false |
stefanct/aua | hw/src/aua_types_de2.vhd | 1 | 3,161 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- used for address width calculation
use ieee.math_real.log2;
use ieee.math_real.ceil;
package aua_types is
constant ADDR_SIZE : natural := 16;
constant WORD_SIZE : natural := ADDR_SIZE;
subtype word_t is std_logic_vector(ADDR_SIZE-1 downto 0);
subtype pc_t is unsigned(ADDR_SIZE-1 downto 0);
subtype opcode_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
--
constant CLK_FREQ : natural := 70000000; -- main clock frequency
constant SRAM_RD_FREQ : natural := 50000000; -- ram clock when reading
constant SRAM_WR_FREQ : natural := 50000000; -- ram clock when writing
constant UART_RATE : natural := 115200; -- uart baud rate
constant RST_VECTOR : pc_t := x"8000";
constant RAM_ADDR_SIZE : natural := 14;
constant SC_SLAVE_CNT : natural := 4; -- count of simpcon slaves
constant SC_ADDR_SIZE : natural := ADDR_SIZE;
constant SC_DATA_SIZE : natural := 32;
constant SC_RDY_CNT_SIZE : natural := 2;
--
-- number of bits needed to address all slaves (2**SC_ADDR_BITS >= SLAVE_CNT)
constant SC_ADDR_BITS : integer := integer(ceil(log2(real(SC_SLAVE_CNT))));
--~ constant SC_ADDR_BITS : integer := integer(reqbits_for_choices(SC_SLAVE_CNT));
subtype sc_addr_t is std_logic_vector(SC_ADDR_SIZE-1 downto 0);
subtype sc_data_t is std_logic_vector(SC_DATA_SIZE-1 downto 0);
type sc_out_t is record
address : sc_addr_t;
wr_data : sc_data_t;
rd : std_logic;
wr : std_logic;
end record;
type sc_out_at is array (0 to SC_SLAVE_CNT-1) of sc_out_t;
subtype sc_rdy_cnt_t is unsigned(SC_RDY_CNT_SIZE-1 downto 0);
type sc_in_t is record
rd_data : sc_data_t;
rdy_cnt : sc_rdy_cnt_t;
end record;
type sc_in_at is array (0 to SC_SLAVE_CNT-1) of sc_in_t;
function max (L, R: real)
return real;
function bool2sl (arg : boolean)
return std_logic;
function sl2bool (arg : std_logic)
return boolean;
function reqbits_for_choices (choices : natural)
return positive;
function reqbitsZ_for_choices (choices : natural)
return natural;
end aua_types;
-- package body for aua on DE2
package body aua_types is
function max (L, R: real)
return real is begin
if L > R then
return L;
else
return R;
end if;
end function max;
function bool2sl (arg : boolean)
return std_logic is begin
if arg then
return '1';
else
return '0';
end if;
end function bool2sl;
function sl2bool (arg : std_logic)
return boolean is begin
if arg='1' then
return true;
else
return false;
end if;
end function sl2bool;
function reqbits_for_choices (choices : natural)
return positive is begin
if choices=1 then
return 1;
else
return positive(ceil(log2(real(choices))));
end if;
end function reqbits_for_choices;
function reqbitsZ_for_choices (choices : natural)
return natural is begin
return natural(ceil(log2(real(choices))));
end function reqbitsZ_for_choices;
end aua_types;
| gpl-3.0 | 6c182087156b4af3da8e3e2bfc26ac28 | 0.654856 | 3.151545 | false | false | false | false |
stefanct/aua | hw/io/sc_de2_switches/src/sc_de2_switches.vhd | 1 | 1,192 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity sc_de2_switches is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t;
-- pins
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0)
);
end sc_de2_switches;
architecture sat1 of sc_de2_switches is
signal switch_reg : std_logic_vector(15 downto 0);
signal led_reg : std_logic_vector(15 downto 0);
begin
rdy_cnt <= (others => '0'); -- no wait states
rd_data <= ((rd_data'length-1 downto switch_reg'length => '0')&switch_reg);
led_pins <= led_reg;
process(clk, reset)
begin
if (reset='1') then
switch_reg <= (others => '0');
led_reg <= (others => '0'); -- high active LEDs
elsif rising_edge(clk) then
if rd = '1' then
switch_reg <= switch_pins;
end if;
if wr = '1' then
led_reg <= not wr_data(15 downto 0);
end if;
end if;
end process;
end sat1;
| gpl-3.0 | 797ef8b80e8f9e880570044c127e13f0 | 0.603188 | 2.672646 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd | 5 | 8,323 | `protect begin_protected
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`protect end_protected
| mit | cb3ffe01b472d497ace327c3101875e4 | 0.916737 | 1.968078 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/sseg_dec.vhd | 1 | 9,071 | ------------------------------------------------------------------------
-- CPE 133 VHDL File: sseg_dec.vhd
-- Description: Special seven segment display driver;
--
-- two special inputs:
--
-- VALID: if valid = 0, four dashes will be display
-- if valid = 1, decimal number appears on display
--
-- SIGN: if sign = 1, a minus sign appears in left-most digit
-- if sign = 0, no minus sign appears
--
--
-- Author: bryan mealy (12-16-10)
--
-- revisions:
------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------
-- 4 digit seven-segment display driver. Outputs are active
-- low and configured ABCEDFG in "segment" output.
--------------------------------------------------------------
entity sseg_dec is
Port ( ALU_VAL : in std_logic_vector(7 downto 0);
SIGN : in std_logic;
VALID : in std_logic;
CLK : in std_logic;
DISP_EN : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(7 downto 0));
end sseg_dec;
-------------------------------------------------------------
-- description of ssegment decoder
-------------------------------------------------------------
architecture my_sseg of sseg_dec is
-- declaration of 8-bit binary to 2-digit BCD converter --
component bin2bcdconv
Port ( BIN_CNT_IN : in std_logic_vector(7 downto 0);
LSD_OUT : out std_logic_vector(3 downto 0);
MSD_OUT : out std_logic_vector(3 downto 0);
MMSD_OUT : out std_logic_vector(3 downto 0));
end component;
component clk_div
Port ( clk : in std_logic;
sclk : out std_logic);
end component;
-- intermediate signal declaration -----------------------
signal cnt_dig : std_logic_vector(1 downto 0);
signal digit : std_logic_vector (3 downto 0);
signal lsd,msd,mmsd : std_logic_vector(3 downto 0);
signal sclk : std_logic;
begin
-- instantiation of bin to bcd converter -----------------
my_conv: bin2bcdconv
port map ( BIN_CNT_IN => ALU_VAL,
LSD_OUT => lsd,
MSD_OUT => msd,
MMSD_OUT => mmsd);
my_clk: clk_div
port map (clk => clk,
sclk => sclk );
-- advance the count (used for display multiplexing) -----
process (SCLK)
begin
if (rising_edge(SCLK)) then
cnt_dig <= cnt_dig + 1;
end if;
end process;
-- select the display sseg data abcdefg (active low) -----
segments <= "00000011" when digit = "0000" else
"10011111" when digit = "0001" else
"00100101" when digit = "0010" else
"00001101" when digit = "0011" else
"10011001" when digit = "0100" else
"01001001" when digit = "0101" else
"01000001" when digit = "0110" else
"00011111" when digit = "0111" else
"00000001" when digit = "1000" else
"00001001" when digit = "1001" else
"11111101" when digit = "1110" else -- dash
"11111111" when digit = "1110" else -- blank
"11111111";
-- actuate the correct display --------------------------
disp_en <= "1110" when cnt_dig = "00" else
"1101" when cnt_dig = "01" else
"1011" when cnt_dig = "10" else
"0111" when cnt_dig = "11" else
"1111";
process (cnt_dig, lsd, msd, mmsd, sign, valid)
variable mmsd_v, msd_v : std_logic_vector(3 downto 0);
begin
mmsd_v := mmsd;
msd_v := msd;
-- do the lead zero blanking for two msb's
if (mmsd_v = X"0") then
if (msd_v = X"0") then
msd_v := X"F";
end if;
mmsd_v := X"F";
end if;
if (valid = '1') then
if (sign = '0') then
case cnt_dig is
when "00" => digit <= "1111";
when "01" => digit <= mmsd_v;
when "10" => digit <= msd_v;
when "11" => digit <= lsd;
when others => digit <= "0000";
end case;
else
case cnt_dig is
when "00" => digit <= "1110";
when "01" => digit <= mmsd_v;
when "10" => digit <= msd_v;
when "11" => digit <= lsd;
when others => digit <= "0000";
end case;
end if;
else digit <= "1110";
end if;
end process;
end my_sseg;
--------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------
-- interface description for bin to bcd converter
--------------------------------------------------------------------
entity bin2bcdconv is
Port ( BIN_CNT_IN : in std_logic_vector(7 downto 0);
LSD_OUT : out std_logic_vector(3 downto 0);
MSD_OUT : out std_logic_vector(3 downto 0);
MMSD_OUT : out std_logic_vector(3 downto 0));
end bin2bcdconv;
---------------------------------------------------------------------
-- description of 8-bit binary to 3-digit BCD converter
---------------------------------------------------------------------
architecture my_ckt of bin2bcdconv is
begin
process(bin_cnt_in)
variable cnt_tot : INTEGER range 0 to 255 := 0;
variable lsd,msd,mmsd : INTEGER range 0 to 9 := 0;
begin
-- convert input binary value to decimal
cnt_tot := 0;
if (bin_cnt_in(7) = '1') then cnt_tot := cnt_tot + 128; end if;
if (bin_cnt_in(6) = '1') then cnt_tot := cnt_tot + 64; end if;
if (bin_cnt_in(5) = '1') then cnt_tot := cnt_tot + 32; end if;
if (bin_cnt_in(4) = '1') then cnt_tot := cnt_tot + 16; end if;
if (bin_cnt_in(3) = '1') then cnt_tot := cnt_tot + 8; end if;
if (bin_cnt_in(2) = '1') then cnt_tot := cnt_tot + 4; end if;
if (bin_cnt_in(1) = '1') then cnt_tot := cnt_tot + 2; end if;
if (bin_cnt_in(0) = '1') then cnt_tot := cnt_tot + 1; end if;
-- initialize intermediate signals
msd := 0;
mmsd := 0;
lsd := 0;
-- calculate the MMSB
for I in 1 to 2 loop
exit when (cnt_tot >= 0 and cnt_tot < 100);
mmsd := mmsd + 1; -- increment the mmds count
cnt_tot := cnt_tot - 100;
end loop;
-- calculate the MSB
for I in 1 to 9 loop
exit when (cnt_tot >= 0 and cnt_tot < 10);
msd := msd + 1; -- increment the mds count
cnt_tot := cnt_tot - 10;
end loop;
lsd := cnt_tot; -- lsd is what is left over
-- convert lsd to binary
case lsd is
when 9 => lsd_out <= "1001";
when 8 => lsd_out <= "1000";
when 7 => lsd_out <= "0111";
when 6 => lsd_out <= "0110";
when 5 => lsd_out <= "0101";
when 4 => lsd_out <= "0100";
when 3 => lsd_out <= "0011";
when 2 => lsd_out <= "0010";
when 1 => lsd_out <= "0001";
when 0 => lsd_out <= "0000";
when others => lsd_out <= "0000";
end case;
-- convert msd to binary
case msd is
when 9 => msd_out <= "1001";
when 8 => msd_out <= "1000";
when 7 => msd_out <= "0111";
when 6 => msd_out <= "0110";
when 5 => msd_out <= "0101";
when 4 => msd_out <= "0100";
when 3 => msd_out <= "0011";
when 2 => msd_out <= "0010";
when 1 => msd_out <= "0001";
when 0 => msd_out <= "0000";
when others => msd_out <= "0000";
end case;
-- convert msd to binary
case mmsd is
when 2 => mmsd_out <= "0010";
when 1 => mmsd_out <= "0001";
when 0 => mmsd_out <= "0000";
when others => mmsd_out <= "0000";
end case;
end process;
end my_ckt;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock
-----------------------------------------------------------------------
entity clk_div is
Port ( clk : in std_logic;
sclk : out std_logic);
end clk_div;
architecture my_clk_div of clk_div is
constant max_count : integer := (2200);
signal tmp_clk : std_logic := '0';
begin
my_div: process (clk,tmp_clk)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT) then
tmp_clk <= not tmp_clk;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
sclk <= tmp_clk;
end process my_div;
end my_clk_div;
| mit | 457b867c006440ab817c1407ee1babd9 | 0.464227 | 3.759221 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_VC707.vhdl | 1 | 16,554 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_VC707 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 200 MHz
);
port (
ClockIn_200MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_200MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_175MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_175MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end;
-- MMCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 200.000 0.000 50.0 97.642 89.971
-- CLK_OUT1 100.000 0.000 50.0 111.850 89.971
-- CLK_OUT2 125.000 0.000 50.0 107.064 89.971
-- CLK_OUT3 250.000 0.000 50.0 93.464 89.971
-- CLK_OUT4 10.000 0.000 50.0 175.649 89.971
--
--
-- PLL - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT1 175.000 0.000 50.0 82.535 112.560
-- CLK_OUT2 125.000 0.000 50.0 87.158 112.560
architecture rtl of clknet_ClockNetwork_VC707 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 200 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (200 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal PLL_Reset : STD_LOGIC;
signal PLL_Reset_clr : STD_LOGIC;
signal PLL_ResetState : STD_LOGIC := '0';
signal PLL_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal PLL_Locked_async : STD_LOGIC;
signal PLL_Locked : STD_LOGIC;
signal PLL_Locked_d : STD_LOGIC := '0';
signal PLL_Locked_re : STD_LOGIC;
signal PLL_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_10MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_125MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_250MHz : STD_LOGIC;
signal MMCM_Clock_10MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_125MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_250MHz_BUFG : STD_LOGIC;
signal PLL_Clock_125MHz : STD_LOGIC;
signal PLL_Clock_175MHz : STD_LOGIC;
-- signal PLL_Clock_125MHz_BUFG : STD_LOGIC;
signal PLL_Clock_175MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_250MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 3 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Input(2) => PLL_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked, --
Output(2) => PLL_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset NOR MMCM_Locked;
PLL_Reset_clr <= ClkNet_Reset NOR PLL_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
PLL_Locked_d <= PLL_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= NOT MMCM_Locked_d AND MMCM_Locked;
PLL_Locked_re <= NOT PLL_Locked_d AND PLL_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
PLL_ResetState <= ffrs(q => PLL_ResetState, rst => PLL_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
PLL_LockedState <= ffrs(q => PLL_LockedState, rst => PLL_Reset, set => PLL_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
PLL_Reset_delayed <= shreg_left(PLL_Reset_delayed, PLL_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
PLL_Reset <= PLL_Reset_delayed(PLL_Reset_delayed'high);
Locked <= MMCM_LockedState AND PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_200MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => MMCM_Clock_10MHz,
O => MMCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => MMCM_Clock_125MHz,
O => MMCM_Clock_125MHz_BUFG
);
-- 175 MHz BUFG
BUFG_Clock_175MHz : BUFG
port map (
I => PLL_Clock_175MHz,
O => PLL_Clock_175MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 250 MHz BUFG
BUFG_Clock_250MHz : BUFG
port map (
I => MMCM_Clock_250MHz,
O => MMCM_Clock_250MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCME2_ADV
generic map (
STARTUP_WAIT => FALSE,
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => FALSE,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 5.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_DIVIDE => 4,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => 0.0,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_200MHz_BUFG,
CLKFBSTOPPED => open,
CLKOUT0 => MMCM_Clock_200MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_100MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_125MHz,
CLKOUT2B => open,
CLKOUT3 => MMCM_Clock_250MHz,
CLKOUT3B => open,
CLKOUT4 => MMCM_Clock_10MHz,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
System_PLL : PLLE2_ADV
generic map (
BANDWIDTH => "HIGH",
COMPENSATION => "BUF_IN",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048,
CLKFBOUT_MULT => 35,
CLKFBOUT_PHASE => 0.000,
DIVCLK_DIVIDE => 4,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 14,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500
)
port map (
RST => PLL_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKFBIN => PLL_Clock_175MHz_BUFG,
CLKFBOUT => open,
CLKOUT0 => PLL_Clock_175MHz,
CLKOUT1 => PLL_Clock_125MHz,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
-- Other control and status signals
PWRDWN => '0',
LOCKED => PLL_Locked_async
);
Control_Clock_200MHz <= Control_Clock_BUFR;
Clock_250MHz <= MMCM_Clock_250MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_175MHz <= PLL_Clock_175MHz_BUFG;
Clock_125MHz <= MMCM_Clock_125MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
Clock_10MHz <= MMCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncLocked250MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_250MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked175MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => PLL_Clock_175MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_175MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | 4b09d3fd15b24d9626f4aadc41019540 | 0.516673 | 3.51465 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/MultBcd_1Dig.vhd | 2 | 2,681 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_1Dig IS
PORT (
a_bcd_1dig : IN unsigned(3 DOWNTO 0);
b_bcd_1dig : IN unsigned(3 DOWNTO 0);
cin_bcd_1dig : IN unsigned(3 DOWNTO 0);
z_bcd_1dig : OUT unsigned(3 DOWNTO 0);
cout_bcd_1dig : OUT unsigned(3 DOWNTO 0)
);
END MultBcd_1Dig;
ARCHITECTURE behavior OF MultBcd_1Dig IS
SIGNAL signal_out_1dig : unsigned(7 DOWNTO 0) := (others => '0');
SIGNAL signal_out_1dig_aux : unsigned(7 DOWNTO 0) := (others => '0');
SIGNAL cout_bcd_1dig_aux : unsigned(3 DOWNTO 0) := (others => '0');
BEGIN
PROCESS (a_bcd_1dig, b_bcd_1dig, cin_bcd_1dig, signal_out_1dig, signal_out_1dig_aux, cout_bcd_1dig_aux)
BEGIN
-- Exemplo A = "0000 0111" B = "0000 0111" --< Saida = 1001 Cout = 0100
signal_out_1dig <= (a_bcd_1dig * b_bcd_1dig) + cin_bcd_1dig; -- Prod = (A * B) + Cin
IF ((signal_out_1dig >= "00000000") AND (signal_out_1dig < "00001010")) THEN -- Entre 0 e 9?
cout_bcd_1dig_aux <= "0000";
signal_out_1dig_aux <= signal_out_1dig;
ELSIF ((signal_out_1dig >= "00001010") AND (signal_out_1dig < "00010100")) THEN -- Entre 10 e 19?
cout_bcd_1dig_aux <= "0001";
signal_out_1dig_aux <= (signal_out_1dig - "00001010");
ELSIF ((signal_out_1dig >= "00010100") AND (signal_out_1dig < "00011110")) THEN
cout_bcd_1dig_aux <= "0010";
signal_out_1dig_aux <= (signal_out_1dig - "00010100");
ELSIF ((signal_out_1dig >= "00011110") AND (signal_out_1dig < "00101000")) THEN
cout_bcd_1dig_aux <= ("0011");
signal_out_1dig_aux <= (signal_out_1dig - "00011110");
ELSIF ((signal_out_1dig >= "00101000") AND (signal_out_1dig < "00110010")) THEN
cout_bcd_1dig_aux <= ("0100");
signal_out_1dig_aux <= (signal_out_1dig - "00101000");
ELSIF ((signal_out_1dig >= "00110010") AND (signal_out_1dig < "00111100")) THEN
cout_bcd_1dig_aux <= ("0101");
signal_out_1dig_aux <= (signal_out_1dig - "00110010");
ELSIF ((signal_out_1dig >= "00111100") AND (signal_out_1dig < "01000110")) THEN
cout_bcd_1dig_aux <= ("0110");
signal_out_1dig_aux <= (signal_out_1dig - "00111100");
ELSIF ((signal_out_1dig >= "01000110") AND (signal_out_1dig < "01010000")) THEN
cout_bcd_1dig_aux <= ("0111");
signal_out_1dig_aux <= (signal_out_1dig - "01000110");
ELSIF ((signal_out_1dig >= "01010000") AND (signal_out_1dig < "01011010")) THEN
cout_bcd_1dig_aux <= ("1000");
signal_out_1dig_aux <= (signal_out_1dig - "01010000");
ELSE
cout_bcd_1dig_aux <= ("1001");
signal_out_1dig_aux <= (signal_out_1dig - "01011010");
END IF;
z_bcd_1dig <= signal_out_1dig_aux(3 DOWNTO 0);
cout_bcd_1dig <= cout_bcd_1dig_aux;
end process;
END behavior; | gpl-3.0 | 0b23e43e955758c4ecf04922000f6b19 | 0.633346 | 2.65183 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment5-Ram_Reg/Programming Assignment/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "3F08820181E141A960077F00170F160F360036003600360057A156A134103510";
attribute INIT_02 of ram_1024_x_18 : label is "81E141B160043F0A81E141A960023F0A81E141A960033F0AA20081E141A96004";
attribute INIT_03 of ram_1024_x_18 : label is "800281E3C001010240095F313FB83F0A81E141B160013F0A81E141B160023F08";
attribute INIT_04 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000000000008002DF01";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "0000000000000000000000000000000649300C0C0C0C0C0300FA550F00000000";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"3F08820181E141A960077F00170F160F360036003600360057A156A134103510",
INIT_02 => X"81E141B160043F0A81E141A960023F0A81E141A960033F0AA20081E141A96004",
INIT_03 => X"800281E3C001010240095F313FB83F0A81E141B160013F0A81E141B160023F08",
INIT_04 => X"000000000000000000000000000000000000000000000000000000008002DF01",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000649300C0C0C0C0C0300FA550F00000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | a9773f2863aebb9f21685e0677bc4a30 | 0.735725 | 6.116 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconcat_0_0/synth/RAT_xlconcat_0_0.vhd | 1 | 8,802 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY RAT_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_xlconcat_0_0;
ARCHITECTURE RAT_xlconcat_0_0_arch OF RAT_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_xlconcat_0_0_arch : ARCHITECTURE IS "RAT_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_xlconcat_0_0_arch: ARCHITECTURE IS "RAT_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=8,IN1_WIDTH=2,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN" &
"25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=10,NUM_PORTS=2}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 8,
IN1_WIDTH => 2,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 10,
NUM_PORTS => 2
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END RAT_xlconcat_0_0_arch;
| mit | 07f53fd9ea98ac54d29480b043957dd3 | 0.645762 | 3.230092 | false | false | false | false |
David-Estevez/spaceinvaders | src/timer.vhd | 1 | 1,337 | ----------------------------------------------------------------------------------
-- GENERIC TIMER
-- David Estévez Fernández
-- Sergio Vilches
-- Gives a pulse of one clock cycle width with a period of t (in milliseconds)
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic ( t: integer := 1); -- Period in ms
port (clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
en : in std_logic;
q : out std_logic);
end timer;
architecture behavioral of timer is
constant clkFreq : integer := 50000; -- 50 MHz clock
constant max : integer := (t*clkFreq)-1;
signal count : integer range 0 to max;
begin
process (reset, clk, count)
begin
if reset = '1' then
count <= 0;
elsif clk'event and clk = '1' then
-- Sequential behaviors:
if clear ='1' then
count <= 0;
elsif en = '1' then
if count = max then
count <= 0;
else
count <= count + 1;
end if;
end if;
end if;
-- Concurrent behaviors:
if count = max then
q <= '1';
else
q <= '0';
end if;
end process;
end behavioral; | gpl-3.0 | bd6ba48a510340f569e4d4b67b822485 | 0.479401 | 3.973214 | false | false | false | false |
stefanct/aua | hw/mmu/src/mmu.vhd | 1 | 9,220 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.math_real.floor;
use work.aua_types.all;
entity mmu is
generic (
CLK_FREQ : natural;
SRAM_RD_FREQ : natural;
SRAM_WR_FREQ : natural
);
port (
clk : in std_logic;
reset : in std_logic;
-- IF stage/cache
instr_addr : in word_t;
instr_enable: in std_logic;
instr_data : out word_t;
instr_valid : out std_logic;
-- interface to EX stage
ex_address : in word_t;
ex_rd_data : out word_t;
ex_wr_data : in word_t;
ex_enable : in std_logic;
ex_opcode : in std_logic_vector(1 downto 0);
ex_done : out std_logic;
-- SimpCon interfaces to IO devices
sc_io_in : in sc_in_t;
sc_io_out : out sc_out_t;
-- interface to SRAM
sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
sram_dq : inout word_t;
sram_we : out std_logic; -- write enable, low active, 0=enable, 1=disable
--~ sram_oe : out std_logic; -- output enable, low active
sram_ub : out std_logic; -- upper byte, low active
sram_lb : out std_logic -- lower byte, low active
--~ sram_ce : out std_logic -- chip enable, low active
);
end mmu;
architecture sat1 of mmu is
-- constant io_devs_name : io_devs := ("bla", "blu");
constant SRAM_RD_RATIO : real := real(CLK_FREQ)/real(SRAM_RD_FREQ);
constant SRAM_WR_RATIO : real := real(CLK_FREQ)/real(SRAM_WR_FREQ);
-- constant SRAM_WAIT_WIDTH : integer := integer(ceil(log2(max(real(5), real(7)))));
constant SRAM_WAIT_WIDTH : integer := integer(ceil(log2(max(SRAM_RD_RATIO, SRAM_WR_RATIO)))) + 1;
signal sc_addr : sc_addr_t;
signal sc_addr_nxt : sc_addr_t;
signal sc_addr_out : sc_addr_t;
signal sc_wr_data : sc_data_t;
signal sc_rd, sc_wr : std_logic;
signal sc_rd_data : sc_data_t;
signal sc_rdy_cnt : sc_rdy_cnt_t;
type mmu_state_t is (mmu_idle, scst_init_rd, scst_rd, scst_init_wr, scst_wr, st_sram); -- Request selbst, Simpcon, kein Simpcon
signal mmu_state : mmu_state_t;
signal mmu_state_nxt : mmu_state_t;
--signal sc_rd_state : std_logic;
--signal sc_rd_state_nxt : std_logic;
signal address : word_t; -- Addresse zu lesen (gemuxt Ex - Instr)
signal write : std_logic; -- schreiben=1, lesen=0 (gemuxt Ex - Instr)
signal q : word_t;
signal done : std_logic;
signal sram_a : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
signal sram_d : word_t;
signal sram_w : std_logic;
signal sram_a_nxt : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
signal sram_d_nxt : word_t;
signal sram_w_nxt : std_logic;
signal sram_wait : unsigned(SRAM_WAIT_WIDTH-1 downto 0);
signal sram_wait_nxt : unsigned(SRAM_WAIT_WIDTH-1 downto 0);
signal sram_writing : std_logic;
signal sram_writing_nxt : std_logic;
signal sram_b_en : std_logic_vector(1 downto 0);
signal sram_b_en_nxt : std_logic_vector(1 downto 0);
component rom is
port (
clk : in std_logic;
address : in word_t;
q : out word_t
);
end component;
signal rom_addr : word_t;
signal rom_q : word_t;
begin
cmp_rom: rom
port map(clk, rom_addr, rom_q);
sc_io_out.address <= sc_addr_out;
sc_io_out.wr_data <= sc_wr_data;
sc_io_out.rd <= sc_rd;
sc_io_out.wr <= sc_wr;
sc_rd_data <= sc_io_in.rd_data;
sc_rdy_cnt <= sc_io_in.rdy_cnt;
-- Speicher 16bit Adressen
-- 0* --> SRAM
-- 10* --> non-Simpcon
-- 1000* --> ROM
-- 11* --> Simpcon 0xC000/2
mmu_get_addr: process(instr_addr, ex_address, ex_enable, ex_opcode)
begin
if(ex_enable = '1') then
address <= ex_address;
write <= ex_opcode(1);
else
address <= instr_addr;
write <= '0';
end if;
end process;
sc_addr_write: process(sc_addr, sc_addr_nxt)
begin
if sc_addr = x"0000" then
sc_addr_out <= sc_addr_nxt;
else
sc_addr_out <= sc_addr;
end if;
end process;
sram: process(sram_a_nxt, sram_w_nxt, sram_b_en_nxt)
begin
sram_addr <= sram_a_nxt;
sram_we <= sram_w_nxt;
sram_ub <= sram_b_en_nxt(0);
sram_lb <= sram_b_en_nxt(1);
end process;
mmu_load_store: process(address, write, ex_enable, ex_wr_data, sram_dq, sram_b_en, rom_q, sc_rd, sc_rdy_cnt, sc_rd_data, mmu_state, sc_addr, sram_wait, sram_a, sram_d, sram_w, sram_writing, ex_opcode)
begin
sram_a_nxt <= (others => '0');
sram_d_nxt <= (others => '0'); -- tri-state, 'Z' unless writing to SRAM
sram_w_nxt <= '1';
sram_wait_nxt <= TO_UNSIGNED(10, SRAM_WAIT_WIDTH);
sram_writing_nxt <= sram_writing;
sram_b_en_nxt <= "00";
sram_dq <= (others => 'Z');
sc_wr_data <= (others => '0');
sc_rd <= '0';
sc_wr <= '0';
rom_addr <= (others => '0');
q <= (others => '0');
done <= '0';
mmu_state_nxt <= mmu_state;
sc_addr_nxt <= x"0000";
case mmu_state is
when mmu_idle =>
if(address(15) = '0') then -- SRAM
sram_a_nxt(13 downto 0) <= address(14 downto 1); -- SRAM adressiert word, instr byte => shift
if(ex_opcode(1) = '1') and (ex_enable = '1') then
sram_b_en_nxt <= address(0) & not address(0);
--if(address(0) = '0') then
-- sram_b_en_nxt <= "01";
--else
-- sram_b_en_nxt <= "10";
--end if;
end if;
if(write = '1') then
sram_w_nxt <= '0';
if(ex_opcode(0) = '1' and (ex_enable = '1') and (address(0) = '0')) then
sram_d_nxt <= ex_wr_data(7 downto 0) & x"00";
sram_dq <= ex_wr_data(7 downto 0) & x"00";
else
sram_d_nxt <= ex_wr_data;
sram_dq <= ex_wr_data;
end if;
if(CLK_FREQ > SRAM_WR_FREQ) then
sram_wait_nxt <= TO_UNSIGNED(0, 2);--TO_UNSIGNED(natural(floor(SRAM_WR_RATIO)), SRAM_WAIT_WIDTH) - 1;
mmu_state_nxt <= st_sram;
sram_writing_nxt <= '1';
else
done <= '1';
end if;
else
if(CLK_FREQ > SRAM_RD_FREQ) then
sram_wait_nxt <= TO_UNSIGNED(0, 2);--TO_UNSIGNED(natural(floor(SRAM_RD_RATIO)), SRAM_WAIT_WIDTH) - 1;
mmu_state_nxt <= st_sram;
else
q <= sram_dq;
done <= '1';
end if;
end if;
else
if(address(14) = '0') then -- non-Simpcon
if(address(13) = '0') then -- ROM (write wird ignoriert)
rom_addr <= address(15 downto 1) & '0';
q <= rom_q;
done <= '1';
end if;
else -- Simpcon
sc_addr_nxt <= address;
if(write = '1') then
sc_wr <= '1';
sc_wr_data(15 downto 0) <= ex_wr_data;
mmu_state_nxt <= scst_init_rd;
else
sc_rd <= '1';
mmu_state_nxt <= scst_init_rd;
end if;
end if;
end if;
when st_sram =>
sram_a_nxt <= sram_a;
sram_d_nxt <= sram_d;
sram_w_nxt <= sram_w;
if sram_wait = 0 then
done <= '1';
mmu_state_nxt <= mmu_idle;
sram_writing_nxt <= '0';
if sram_writing = '0' then
q <= sram_dq;
end if;
else
sram_wait_nxt <= sram_wait - 1;
mmu_state_nxt <= st_sram;
sram_writing_nxt <= sram_writing;
end if;
sram_b_en_nxt <= sram_b_en;
when scst_init_rd =>
mmu_state_nxt <= scst_rd;
sc_addr_nxt <= sc_addr;
when scst_rd =>
if sc_rdy_cnt > 0 then
sc_addr_nxt <= sc_addr;
else
mmu_state_nxt <= mmu_idle;
done <= '1';
q <= sc_rd_data(15 downto 0);
end if;
when scst_init_wr =>
mmu_state_nxt <= scst_wr;
sc_addr_nxt <= sc_addr;
when scst_wr =>
if sc_rdy_cnt > 0 then
sc_addr_nxt <= sc_addr;
else
mmu_state_nxt <= mmu_idle;
done <= '1';
end if;
when others =>
mmu_state_nxt <= mmu_idle;
end case;
end process;
mmu_return_result: process(ex_enable, q, done, sram_a, ex_opcode)
begin
instr_data <= (others => '0');
ex_rd_data <= (others => '0');
instr_valid <= '0';
ex_done <= '0';
if(ex_enable = '1') then
if(ex_opcode(0) = '1' and sram_a(0) = '0') then
ex_rd_data <= x"00" & q(15 downto 8);
else
ex_rd_data <= q;
end if;
ex_done <= done;
else
instr_data <= q;
instr_valid <= done;
end if;
end process;
sync: process (clk, reset)
begin
if reset = '1' then
mmu_state <= mmu_idle;
sc_addr <= (others => '0');
sram_wait <= TO_UNSIGNED(0, SRAM_WAIT_WIDTH);
elsif rising_edge(clk) then
mmu_state <= mmu_state_nxt;
sc_addr <= sc_addr_nxt;
sram_a <= sram_a_nxt;
sram_d <= sram_d_nxt;
sram_w <= sram_w_nxt;
sram_writing <= sram_writing_nxt;
sram_wait <= sram_wait_nxt;
sram_b_en <= sram_b_en_nxt;
end if;
end process;
end sat1;
| gpl-3.0 | 7bdee991d92f49fbbd98f72e5c6b44ad | 0.528416 | 2.777945 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_17_13_0/sim/RAT_slice_17_13_0.vhd | 2 | 3,216 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
| mit | cfbd1e63c173b496c511235b42466ba1 | 0.722326 | 4.060606 | false | false | false | false |
David-Estevez/spaceinvaders | src/edgeDetector_tb.vhd | 1 | 2,031 | ----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector testbench
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity edgeDetector_tb is
end edgeDetector_tb;
architecture Behavioral of edgeDetector_tb is
-- Declare component:
component edgeDetector
port(
clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
end component;
-- Inputs
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal enable: std_logic := '0';
signal input: std_logic := '0';
-- Outputs
signal detected: std_logic;
-- clk period
constant clk_period: time := 20 ns;
begin
-- Instantiation of edgeDetector:
uut: edgeDetector
port map(
clk => clk,
reset => reset,
enable => enable,
input => input,
detected => detected
);
-- Clock signal
clk_process : process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-- Other stimulus
stim_process : process
begin
-- Reset circuit:
reset <= '0';
wait for 80 ns;
reset <= '1';
wait for 20 ns;
-- Test circuit with enable disabled:
enable <= '0';
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
-- Test circuit with enable enabled:
enable <= '1';
wait for 2*clk_period;
input <= '1';
wait for 2*clk_period;
input <= '0';
wait for 2*clk_period;
-- Test circuit with enable disabled again:
enable <= '0';
input <= '1';
wait for 3*clk_period;
input <= '0';
wait for clk_period;
wait;
end process;
end Behavioral;
| gpl-3.0 | 3293e7b88af37da207000bb6f599b839 | 0.543886 | 3.508651 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/cores/dec_to_fir_mux_v1_0/dec_to_fir_mux.vhd | 1 | 1,830 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity dec_to_fir_mux is
port (
DecRate: in std_logic_vector(31 downto 0);
Mux3: out std_logic_vector(1 downto 0);
Mux2: out std_logic_vector(1 downto 0);
Mux1: out std_logic_vector(1 downto 0);
Mux0: out std_logic_vector(1 downto 0);
MuxF: out std_logic_vector(1 downto 0)
);
end dec_to_fir_mux;
architecture V1 of dec_to_fir_mux is
begin
-- Persistent signal mappings
p_converter: process(DecRate)
begin
case to_integer(unsigned(DecRate)) is
when 5 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "00";
MuxF <= "00";
when 25 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "01";
Mux3 <= "00";
MuxF <= "00";
when 125 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "01";
MuxF <= "01";
when 625 =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "01";
Mux3 <= "01";
MuxF <= "01";
when 1250 =>
Mux0 <= "01";
Mux1 <= "10";
Mux2 <= "00";
Mux3 <= "10";
MuxF <= "01";
when 2500 =>
Mux0 <= "01";
Mux1 <= "01";
Mux2 <= "00";
Mux3 <= "10";
MuxF <= "01";
when others =>
Mux0 <= "00";
Mux1 <= "00";
Mux2 <= "00";
Mux3 <= "00";
MuxF <= "00";
end case;
end process;
end V1;
| mit | 1ad0f4b1c6116bd0f9d32b1d6408461d | 0.364481 | 3.927039 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/MaquinaDeDividir.vhd | 1 | 3,063 | --Bibliotecas Utilizadas
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--Declaração de entidade
entity MaquinaDeDividir is
GENERIC
(
n : NATURAL := 7 --Indica número de bits [0 --> 7]
);
port
(
clock: in std_logic; --Sinal de clock da Spartan3E
dividendo: in std_logic_vector(n downto 0); --Operador
divisor: in std_logic_vector(n downto 0); --Operador
resto: out std_logic_vector(n downto 0); --Resultado
quociente: out std_logic_vector(n downto 0); --Resultado
enable: in std_logic; --Habilita o funcionamento do módulo
finish: out std_logic;
reset: in std_logic
-- codigoErro: out integer --Flag de erro
);
end MaquinaDeDividir;
--Arquitetura da entidade BlocoDivisor
architecture ArcMaquinaDeDividir of MaquinaDeDividir is
begin
--Processo no qual a operação de divisão é realizada
Operacao : process (Dividendo, Divisor, clock)
--Declaração de variáveis
variable inicio: natural:= 0; --Marca o estágio da operação de divisão
variable numDiv: std_logic_vector(n downto 0);
variable UM : std_logic_vector(n downto 0) ;
variable Pquociente : std_logic_vector(n downto 0); --Resultado interno ao processo
variable Pdivisor : std_logic_vector(n downto 0); --Operador interno ao processo
variable Pdividendo : std_logic_vector(n downto 0); --Operador interno ao processo
variable Presto : std_logic_vector(n downto 0); --Resultado interno ao processo
variable numeroDividendo : std_logic_vector(n downto 0); --Vetor auxiliar
variable numeroQuociente: std_logic_vector(n downto 0);
variable t: std_logic_vector(n downto 0);
variable i: integer := n;
variable finishAuxiliar : std_logic := '0';
begin
if (rising_edge(clock) and enable = '1') then
if (inicio = 0) then
finishAuxiliar := '0';
Pdividendo := Dividendo;
Pdivisor := Divisor;
Pquociente := "00000000";
UM := "00000001"; --Variável que armazena o valor 1, em binário
inicio := 1;
elsif (inicio = 1) then
if (Pdivisor = "00000000") then
Resto <= "00000000";
Quociente <= "00000000";
inicio := 2;
else
varredorNumero: for i in n downto 0 loop
numeroDividendo := to_stdlogicvector(to_bitvector(pDividendo) srl i);
if (unsigned(numeroDividendo) >= unsigned(pDivisor))then
numeroQuociente := to_stdlogicvector(to_bitvector(um) sll i);
pQuociente := std_logic_vector(unsigned(pQuociente) + unsigned(numeroQuociente));
numDiv := to_stdlogicvector(to_bitvector(pDivisor) sll i);
t := pDividendo;
pDividendo := std_logic_vector(unsigned(t) - unsigned(numDiv));
end if;
end loop varredorNumero;
Resto <= pDividendo;
Quociente <= pQuociente;
inicio := 3;
end if;
end if;
if inicio = 3 then
finishAuxiliar := '1';
if (reset='1') then
inicio:=0;
end if;
else
finishAuxiliar := '0';
end if;
finish <= finishAuxiliar;
end if;
end process Operacao;
end ArcMaquinaDeDividir; | gpl-3.0 | 5c3fd07d0d535cfb4dc5817ab43fcbe3 | 0.672029 | 3.296537 | false | false | false | false |
stefanct/aua | hw/reg/src/reg.vhd | 1 | 1,455 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity reg is
port (
clk : in std_logic;
reset : in std_logic;
async_rega : in reg_t;
async_regb : in reg_t;
rega : in reg_t;
regb : in reg_t;
async_regr : in reg_t;
async_valr : in word_t;
vala : out word_t;
valb : out word_t
);
end reg;
architecture rtl of reg is
component ram is
port (
clock : in std_logic;
data : in word_t;
rdaddress : in reg_t;
wraddress : in reg_t;
wren : in std_logic;
q : out word_t
);
end component;
signal vala_ram : word_t;
signal valb_ram : word_t;
signal regr : reg_t;
signal valr : word_t;
begin
cmp_ram_a: ram
port map(clk, async_valr, async_rega, async_regr, '1', vala_ram);
cmp_ram_b: ram
port map(clk, async_valr, async_regb, async_regr, '1', valb_ram);
process(rega, regb, regr, valr, vala_ram, valb_ram)
begin
if(rega = regr) then
vala <= valr;
else
vala <= vala_ram;
end if;
if(regb = regr) then
valb <= valr;
else
valb <= valb_ram;
end if;
end process;
sync: process (clk, reset)
begin
if reset = '1' then
valr <= (others => '0');
regr <= (others => '0');
elsif rising_edge(clk) then
valr <= async_valr;
regr <= async_regr;
end if;
end process;
end rtl;
| gpl-3.0 | 01fbef3ae8971321afdc48cf2faf4933 | 0.549141 | 2.694444 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/ConversorBCD/bcd_converter.vhd | 1 | 3,280 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bcd_converter IS
PORT (
in_binary : IN std_logic_vector(31 DOWNTO 0);
digit_0 : OUT std_logic_vector(3 DOWNTO 0);
digit_1 : OUT std_logic_vector(3 DOWNTO 0);
digit_2 : OUT std_logic_vector(3 DOWNTO 0);
digit_3 : OUT std_logic_vector(3 DOWNTO 0);
digit_4 : OUT std_logic_vector(3 DOWNTO 0);
digit_5 : OUT std_logic_vector(3 DOWNTO 0);
digit_6 : OUT std_logic_vector(3 DOWNTO 0);
digit_7 : OUT std_logic_vector(3 DOWNTO 0);
digit_8 : OUT std_logic_vector(3 DOWNTO 0);
digit_9 : OUT std_logic_vector(3 DOWNTO 0)
);
END ENTITY bcd_converter;
-----------------------------------
ARCHITECTURE a OF bcd_converter IS
BEGIN
PROCESS (in_binary)
VARIABLE s_digit_0 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_1 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_2 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_3 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_4 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_5 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_6 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_7 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_8 : unsigned(3 DOWNTO 0);
VARIABLE s_digit_9 : unsigned(3 DOWNTO 0);
BEGIN
s_digit_9 := "0000";
s_digit_8 := "0000";
s_digit_7 := "0000";
s_digit_6 := "0000";
s_digit_5 := "0000";
s_digit_4 := "0000";
s_digit_3 := "0000";
s_digit_2 := "0000";
s_digit_1 := "0000";
s_digit_0 := "0000";
FOR i IN 31 DOWNTO 0 LOOP
IF (s_digit_9 >= 5) THEN
s_digit_9 := s_digit_9 + 3;
END IF;
IF (s_digit_8 >= 5) THEN
s_digit_8 := s_digit_8 + 3;
END IF;
IF (s_digit_7 >= 5) THEN
s_digit_7 := s_digit_7 + 3;
END IF;
IF (s_digit_6 >= 5) THEN
s_digit_6 := s_digit_6 + 3;
END IF;
IF (s_digit_5 >= 5) THEN
s_digit_5 := s_digit_5 + 3;
END IF;
IF (s_digit_4 >= 5) THEN
s_digit_4 := s_digit_4 + 3;
END IF;
IF (s_digit_3 >= 5) THEN
s_digit_3 := s_digit_3 + 3;
END IF;
IF (s_digit_2 >= 5) THEN
s_digit_2 := s_digit_2 + 3;
END IF;
IF (s_digit_1 >= 5) THEN
s_digit_1 := s_digit_1 + 3;
END IF;
IF (s_digit_0 >= 5) THEN
s_digit_0 := s_digit_0 + 3;
END IF;
s_digit_9 := s_digit_9 SLL 1;
s_digit_9(0) := s_digit_8(3);
s_digit_8 := s_digit_8 SLL 1;
s_digit_8(0) := s_digit_7(3);
s_digit_7 := s_digit_7 SLL 1;
s_digit_7(0) := s_digit_6(3);
s_digit_6 := s_digit_6 SLL 1;
s_digit_6(0) := s_digit_5(3);
s_digit_5 := s_digit_5 SLL 1;
s_digit_5(0) := s_digit_4(3);
s_digit_4 := s_digit_4 SLL 1;
s_digit_4(0) := s_digit_3(3);
s_digit_3 := s_digit_3 SLL 1;
s_digit_3(0) := s_digit_2(3);
s_digit_2 := s_digit_2 SLL 1;
s_digit_2(0) := s_digit_1(3);
s_digit_1 := s_digit_1 SLL 1;
s_digit_1(0) := s_digit_0(3);
s_digit_0 := s_digit_0 SLL 1;
s_digit_0(0) := in_binary(i);
END LOOP;
digit_0 <= std_logic_vector(s_digit_0);
digit_1 <= std_logic_vector(s_digit_1);
digit_2 <= std_logic_vector(s_digit_2);
digit_3 <= std_logic_vector(s_digit_3);
digit_4 <= std_logic_vector(s_digit_4);
digit_5 <= std_logic_vector(s_digit_5);
digit_6 <= std_logic_vector(s_digit_6);
digit_7 <= std_logic_vector(s_digit_7);
digit_8 <= std_logic_vector(s_digit_8);
digit_9 <= std_logic_vector(s_digit_9);
END PROCESS;
END ARCHITECTURE a; | gpl-3.0 | 1774544ad0fee2f4b2499ec326fa9631 | 0.584756 | 2.327892 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Multiplicador/mult_BCD_comb.vhd | 1 | 2,719 | ------------------------------------------------------------------
-- BCD multiplier N by M digits
-- Fully combiational
-- Simple version
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.my_package.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity mult_BCD_comb is
Generic (NDigit : natural:=5; MDigit : natural:=5);
Port ( a : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
b : in STD_LOGIC_VECTOR (MDigit*4-1 downto 0);
p : out STD_LOGIC_VECTOR ((NDigit+MDigit)*4-1 downto 0));
end mult_BCD_comb;
architecture Behavioral of mult_BCD_comb is
function log2sup (num: natural) return natural is
variable i,pw: natural;
begin
i := 0; pw := 1;
while(pw < num) loop i := i+1; pw := pw*2; end loop;
return i;
end log2sup;
component mult_Nx1_BCD is
Generic (NDigit : integer);
Port ( a : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
p : out STD_LOGIC_VECTOR ((NDigit+1)*4-1 downto 0));
end component;
component cych_adder_BCD_v2 is
Generic (NDigit : integer);
Port ( a, b : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (NDigit*4-1 downto 0));
end component;
--constant logM natural := log2sup(MDigit);
type partialSum is array (2*MDigit-2 downto 0) of STD_LOGIC_VECTOR ((NDigit+MDigit)*4-1 downto 0);
signal pp,pps: partialSum;
begin
GenM: for i in 0 to (MDigit-1) generate --Multiply one by N
mlt: mult_Nx1_BCD generic map (NDIGIT => NDigit) PORT MAP (
a => a, b => b((i+1)*4-1 downto i*4), p => pp(i)((NDigit+1)*4-1 downto 0) );
end generate;
GenOps: for i in 0 to log2sup(MDigit)-1 generate --Tree of adders
G_P: for j in ((2**i-1)*2**(log2sup(MDigit)-i)) to (((2**i-1)*2**(log2sup(MDigit)-i)) + 2**(log2sup(MDigit)-i-1) -1) generate
pps(2*j)((NDigit+MDigit)*4-1 downto (NDigit)*4) <= (others => '0');
pps(2*j)((NDigit)*4-1 downto 0) <= pp(2*j)((NDigit+2**i)*4-1 downto (2**i)*4);
adder: cych_adder_BCD_v2 generic map (NDIGIT => NDigit+2**i)
PORT MAP( a => pps(2*j)((NDigit+2**i)*4-1 downto 0), b => pp(2*j+1)((NDigit+2**i)*4-1 downto 0),
cin => '0', cout => open, s => pp(MDIGIT+j)((NDigit+2**i+2**i)*4-1 downto ((2**i)*4)));
pp(MDIGIT+j)((2**i)*4-1 downto 0) <= pp(2*j)((2**i)*4-1 downto 0);
end generate;
end generate;
p((NDigit+MDigit)*4-1 downto 0) <= pp(MDigit*2-2);
end Behavioral;
| gpl-3.0 | 828cfde7006384973ef759099e604c30 | 0.5605 | 3.037989 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment6-ALU/RTL/ALU.vhd | 1 | 2,734 | ----------------------------------------------------------------------------------
-- Company: PolySat
-- Engineer: Quinn Mikelson
--
-- Create Date: 10/02/2017 - 9:25AM
-- Design Name: RAT CPU
-- Module Name: ALU - Behavioral
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Generic ( data_width : integer := 8;
sel_width : integer := 4);
Port ( A : in STD_LOGIC_VECTOR (data_width-1 downto 0);
B : in STD_LOGIC_VECTOR (data_width-1 downto 0);
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (sel_width-1 downto 0);
SUM : out STD_LOGIC_VECTOR (data_width-1 downto 0);
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC);
end alu;
architecture Behavioral of alu is
signal temp_s : STD_LOGIC_VECTOR (8 downto 0);
begin
process (A, B, C_IN, SEL)
begin
case SEL is
when "0000" => temp_s <= ('0' & A) + B; -- add
when "0001" => temp_s <= ('0' & A) + B + C_IN; -- addc
when "0010" => temp_s <= ('0' & A) - B; -- sub
when "0011" => temp_s <= ('0' & A) - B - C_IN; -- subc
when "0100" => temp_s <= ('0' & A) - B; -- cmp
when "0101" => temp_s <= ('0' & A) and ('0' & B); -- and
when "0110" => temp_s <= ('0' & A) or ('0' & B); -- or
when "0111" => temp_s <= ('0' & A) xor ('0' & B); -- exor
when "1000" => temp_s <= ('0' & A) and ('0' & B); -- test
when "1001" => temp_s <= A & C_IN; -- lsl
when "1010" => temp_s <= A(0) & C_IN & A (7 downto 1); -- lsr
when "1011" => temp_s <= A(7 downto 0) & A(7); -- rol
when "1100" => temp_s <= A(0) & A(0) & A(7 downto 1); -- ror
when "1101" => temp_s <= A(0) & A(7) & A(7 downto 1); -- asr
when "1110" => temp_s <= '0' & B; -- mov
when "1111" => temp_s <= "000000000"; -- unused
when others => temp_s <= "000000000";
end case;
end process;
-- account for overflow during subtraction
SUM <= not(temp_s (data_width-1 downto 0)) + 1 when ((SEL = "0010" or SEL = "0011") and temp_s(data_width) = '1')
else temp_s(data_width-1 downto 0);
Z_FLAG <= '1' when (temp_s = "000000000" or temp_s = "100000000") else '0';
C_FLAG <= temp_s(8);
end Behavioral; | mit | e9a4ca26a9369b3b9ee1ef4e1ece4486 | 0.424287 | 3.358722 | false | false | false | false |
David-Estevez/spaceinvaders | src/SpaceInv.vhd | 1 | 15,861 | ----------------------------------------------------------------------------------
--
-- Lab session #2: Space Invaders
--
----------------------------------------------------------------------------------
-- Top level entity for the Space Invaders vga controller
-- Authors: David Estevez Fernandez
-- Sergio Vilches Exposito
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SpaceInv is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
Test: in STD_LOGIC;
left1, right1, start1, shoot1: in STD_LOGIC;
left2, right2, start2, shoot2: in STD_LOGIC;
LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7: out STD_LOGIC;
HSync : out STD_LOGIC;
VSync : out STD_LOGIC;
R,G,B : out STD_LOGIC;
speaker : out STD_LOGIC
);
end SpaceInv;
architecture Behavioral of SpaceInv is
-- Component declaration for vga controller:
COMPONENT vga
PORT(
clk : IN std_logic;
reset : IN std_logic;
RGB : IN std_logic_vector(2 downto 0);
HSync : OUT std_logic;
VSync : OUT std_logic;
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic;
X : OUT std_logic_vector(9 downto 0);
Y : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
-- Compoment declaration for screen format:
COMPONENT screenFormat
PORT (
VGAx : in std_logic_vector (9 downto 0);
VGAy : in std_logic_vector (9 downto 0);
test : in std_logic;
invArray: in std_logic_vector (39 downto 0);
invLine : in std_logic_vector (3 downto 0);
shipX1 : in std_logic_vector (4 downto 0);
bullX1 : in std_logic_vector (4 downto 0);
bullY1 : in std_logic_vector (3 downto 0);
bulletFlying1: in std_logic;
player2shown : in std_logic;
shipX2 : in std_logic_vector (4 downto 0);
bullX2 : in std_logic_vector (4 downto 0);
bullY2 : in std_logic_vector (3 downto 0);
bulletFlying2: in std_logic;
specialScreen: in std_logic_vector( 2 downto 0);
p1Score: in std_logic_vector(7 downto 0);
p2Score: in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(2 downto 0)
);
END COMPONENT;
component invaders is
port (
clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
start : in std_logic;
bullX1 : in std_logic_vector(4 downto 0);
bullY1 : in std_logic_vector(3 downto 0);
hit1 : out std_logic;
bullX2 : in std_logic_vector(4 downto 0);
bullY2 : in std_logic_vector(3 downto 0);
hit2 : out std_logic;
invArray : inout std_logic_vector(39 downto 0);
invLine : inout std_logic_vector(3 downto 0);
level : in std_logic_vector( 2 downto 0 )
);
end component;
-- Declaration of component player
component player is
port (
-- User controls
Right : in STD_LOGIC;
Left : in STD_LOGIC;
Start : in STD_LOGIC;
Shoot : in STD_LOGIC;
-- Control signals
clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Clear : in STD_LOGIC;
ScoreClear : in STD_LOGIC;
Enable : in STD_LOGIC;
-- Internal signals
hit : in STD_LOGIC;
posShip : out STD_LOGIC_VECTOR (4 downto 0);
startPulse : out STD_LOGIC;
BulletX : out STD_LOGIC_VECTOR (4 downto 0);
BulletY : out STD_LOGIC_VECTOR (3 downto 0);
BulletActive : out STD_LOGIC;
Score : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component toneGenerator is
port (clk : in std_logic;
reset : in std_logic;
p1_posShip : in std_logic;
p2_posShip : in std_logic;
p1_BulletActive : in std_logic;
p2_BulletActive : in std_logic;
inv_Hit1 : in std_logic;
inv_Hit2 : in std_logic;
specialScreen : in std_logic_vector( 2 downto 0);
toneOutput : out std_logic
);
end component;
-- Clear lines:
----------------------------------------------------
signal player1Clear: STD_LOGIC;
signal p1ScoreClear: STD_LOGIC;
signal player2Clear: STD_LOGIC;
signal p2ScoreClear: STD_LOGIC;
signal invadersClear: STD_LOGIC;
-- Inputs to ScreenFormat
----------------------------------------------------
signal RGB: STD_LOGIC_VECTOR (2 downto 0);
signal X, Y: STD_LOGIC_VECTOR (9 downto 0);
signal specialScreen: STD_LOGIC_VECTOR( 2 downto 0);
signal testEnable: STD_LOGIC;
signal invArray: std_logic_vector (39 downto 0);
signal invLine : std_logic_vector (3 downto 0);
-- Invaders trigger:
----------------------------------------------------
signal invadersStart: STD_LOGIC;
-- Player 1 signals:
----------------------------------------------------
-- User control signals
signal p1right: std_logic;
signal p1left: std_logic;
signal p1start: std_logic;
signal p1shoot: std_logic;
signal p1enable: std_logic;
-- Internal signals
signal p1startPulse: std_logic;
signal p1posH : std_logic_vector (4 downto 0);
signal p1hit : std_logic;
signal p1bullX : std_logic_vector (4 downto 0);
signal p1bullY : std_logic_vector (3 downto 0);
signal p1bulletFlying : std_logic;
signal p1Score: std_logic_vector (7 downto 0);
-- Player 2 signals
---------------------------------------------------
-- User control signals
signal p2right: std_logic;
signal p2left: std_logic;
signal p2start: std_logic;
signal p2shoot: std_logic;
signal p2enable: std_logic;
-- Internal signals
signal p2startPulse: std_logic;
signal p2posH : std_logic_vector (4 downto 0);
signal p2hit : std_logic;
signal p2bullX : std_logic_vector (4 downto 0);
signal p2bullY : std_logic_vector (3 downto 0);
signal p2bulletFlying : std_logic;
signal p2Score: std_logic_vector (7 downto 0);
-- State machine things:
------------------------------------------------------
type State is ( testState, Start, Playing, YouWin, YouLose, WinGame );
signal currentState, nextState: State;
-- Level control:
------------------------------------------------------
signal level: std_logic_vector( 2 downto 0 );
signal levelClear: std_logic;
signal levelUp: std_logic;
begin
vgaController: vga
PORT MAP(
clk => clk,
reset => reset,
RGB => RGB,
HSync => HSync,
VSync => VSync,
R => R,
G => G,
B => B,
X => X,
Y => Y
);
framebuffer: screenFormat
PORT MAP(
VGAx => X,
VGAy => Y,
test => testEnable,
invArray => invArray,
invLine => invLine,
shipX1 => p1posH,
bullX1 => p1bullX,
bullY1 => p1bullY,
bulletFlying1 => p1bulletFlying,
player2shown => p2Enable,
shipX2 => p2posH,
bullX2 => p2bullX,
bullY2 => p2bullY,
bulletFlying2 => p2bulletFlying,
specialScreen => specialScreen,
p1Score => p1Score,
p2Score => p2Score,
rgb => rgb
);
badGuys: invaders
PORT MAP(
clk => clk,
reset => Reset,
Clear => invadersClear,
start => invadersStart,
bullX1 => p1bullX,
bullY1 => p1bullY,
hit1 => p1hit,
bullX2 => p2bullX,
bullY2 => p2bullY,
hit2 => p2hit,
invArray => invArray,
invLine => invLine,
level => level
);
player1: player
PORT MAP (
Right => p1right,
Left => p1left,
Start => p1start,
Shoot => p1shoot,
clk => clk,
Reset => reset,
Clear => player1Clear,
ScoreClear => p1ScoreClear,
Enable => p1Enable,
hit => p1hit,
posShip => p1posH,
startPulse => p1startPulse,
BulletX => p1bullX,
BulletY => p1bullY,
BulletActive => p1bulletFlying,
Score => p1Score
);
player2: player
PORT MAP (
Right => p2right,
Left => p2left,
Start => p2start,
Shoot => p2shoot,
clk => clk,
Reset => reset,
Clear => player2Clear,
ScoreClear => p2ScoreClear,
Enable => p2Enable,
hit => p2hit,
posShip => p2posH,
startPulse => p2startPulse,
BulletX => p2bullX,
BulletY => p2bullY,
BulletActive => p2bulletFlying,
Score => p2Score
);
soundCard: toneGenerator
port map (
clk => clk,
reset => reset,
p1_posShip => p1posH(0),
p2_posShip => p2posH(0),
p1_BulletActive => p1bulletFlying,
p2_BulletActive => p2bulletFlying,
inv_Hit1 => p1hit,
inv_Hit2 => p2hit,
specialScreen => specialScreen,
toneOutput => speaker
);
-- Linking external I/O lines with players:
p1right <= right1;
p1left <= left1;
p1start <= start1;
p1shoot <= shoot1;
p2right <= right2;
p2left <= left2;
p2start <= start2;
p2shoot <= shoot2;
-- Process for changing states:
process( clk, reset)
begin
-- Reset
if reset = '1' then
currentState <= Start;
-- Update State
elsif clk'Event and clk = '1' then
currentState <= nextState;
end if;
end process;
-- Process for modelling the transitions / outputs
-- of the state machine
process( currentState, Test, invArray, invLine, p1startPulse, p2startPulse, level)
begin
nextState <= currentState;
case currentState is
when testState=>
-- Show checkerboard pattern
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '1';
specialScreen <= "000";
-- Invaders signals
invadersClear <= '1';
invadersStart <= '0';
-- Player signals
p1Enable <= '0';
player1Clear <= '1';
player2Clear <= '1';
-- Level control
levelUp <= '0';
-- Next state:
if ( Test = '0' ) then
nextState <= Start;
else
nextState <= currentState;
end if;
when Start =>
-- Wait for user to start the game
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '0';
specialScreen <= "000";
-- Invaders signals
invadersClear <= '1';
invadersStart <= '0';
-- Player signals
p1Enable <= '0';
player1Clear <= '1';
player2Clear <= '1';
-- Level control
levelUp <= '0';
-- Next state:
if ( Test = '1' ) then
nextState <= testState;
elsif ( p1startPulse = '1' ) then
nextState <= Playing;
else
nextState <= currentState;
end if;
when Playing =>
-- Playing the game
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '0';
specialScreen <= "000";
-- Invaders signals
invadersClear <= '0';
invadersStart <= '1';
-- Player signals
p1Enable <= '1';
player1Clear <= '0';
player2Clear <= '0';
-- Level control
levelUp <= '0';
-- Next state:
if ( Test = '1' ) then
nextState <= testState;
elsif ( invArray = "0000000000000000000000000000000000000000" ) then
nextState <= YouWin;
elsif ( invLine = "1110" ) then
nextState <= YouLose;
else
nextState <= currentState;
end if;
when YouWin =>
-- Winning screen
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '0';
specialScreen <= "001";
-- Invaders signals
invadersClear <= '1';
invadersStart <= '0';
-- Player signals
p1Enable <= '0';
player1Clear <= '0';
player2Clear <= '0';
-- Level control
levelUp <= '1';
-- Next state:
if ( Test = '1' ) then
nextState <= testState;
elsif ( (p1startPulse = '1') or (p2startPulse = '1')) and (level = "000" ) then
nextState <= WinGame;
elsif ( p1startPulse = '1') or (p2startPulse = '1') then
nextState <= Start;
else
nextState <= currentState;
end if;
when YouLose =>
-- Losing screen
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '0';
specialScreen <= "010";
-- Invaders signals
invadersClear <= '1';
invadersStart <= '0';
-- Player signals
p1Enable <= '0';
player1Clear <= '0';
player2Clear <= '0';
-- Level control
levelUp <= '0';
-- Next state:
if ( Test = '1' ) then
nextState <= testState;
elsif ( p1startPulse = '1') or (p2startPulse = '1') then
nextState <= Start;
else
nextState <= currentState;
end if;
when WinGame =>
-- Win game screen
-- Set outputs:
-----------------------------
-- Special signals
testEnable <= '0';
specialScreen <= "011";
-- Invaders signals
invadersClear <= '1';
invadersStart <= '0';
-- Player signals
p1Enable <= '0';
player1Clear <= '0';
player2Clear <= '0';
-- Level control
levelUp <= '0';
-- Next state:
if ( Test = '1' ) then
nextState <= testState;
elsif ( p1startPulse = '1') or (p2startPulse = '1') then
nextState <= Start;
else
nextState <= currentState;
end if;
end case;
end process;
-- Score and level clear control:
process( clk )
begin
if clk'event and clk = '1' then
if ((nextState = Start) and ( currentState = YouLose or currentState = WinGame)) or currentState = testState then
p1ScoreClear <= '1';
p2ScoreClear <= '1';
levelClear <= '1';
else
p1ScoreClear <= '0';
p2ScoreClear <= '0';
levelClear <= '0';
end if;
end if;
end process;
-- Latch for the player 2 enable signal
process( clk, Reset)
begin
if Reset = '1' then
p2Enable <= '0';
elsif clk'event and clk = '1' then
-- Player 2 enable:
-------------------------------------------------------------------------------------------------------
-- Enable player 2 if p2start is pressed on start screen
if ( currentState = Start ) and (p2startPulse = '1') then
p2Enable <= '1';
-- Disable player 2 when game is lost
elsif ( currentState = YouLose or currentState = WinGame ) and (p1startPulse = '1' or p2startPulse = '1') then
p2Enable <= '0';
end if;
end if;
end process;
-- Process controlling the level
process( clk, Reset)
variable intLevel : integer range 0 to 7;
variable previousLevelUp: std_logic;
begin
-- Counter for the level (counts edges)
-- Reset
if Reset = '1' then
intLevel := 0;
previousLevelUp := '0';
elsif clk'event and clk = '1' then
-- Clear
if levelClear = '1' then
intLevel := 0;
-- Up counter
elsif levelUp = '1' and previousLevelUp = '0' then
if intLevel = 7 then
intlevel := 0;
else
intLevel := intLevel + 1;
end if;
end if;
-- Store the last value
previousLevelUp := levelUp;
end if;
level <= std_logic_vector( to_unsigned( intLevel, 3));
end process;
-- Show score on the leds:
LED0 <= '1' when level = "000" else '0';
LED1 <= '1' when level = "001" else '0';
LED2 <= '1' when level = "010" else '0';
LED3 <= '1' when level = "011" else '0';
LED4 <= '1' when level = "100" else '0';
LED5 <= '1' when level = "101" else '0';
LED6 <= '1' when level = "110" else '0';
LED7 <= '1' when level = "111" else '0';
end Behavioral;
| gpl-3.0 | b766a2050bee7c34bc6338e4046c64ba | 0.531934 | 3.495152 | false | false | false | false |
David-Estevez/spaceinvaders | src/player.vhd | 1 | 4,316 | ----------------------------------------------------------------------------------
--
-- Lab session #4: Player
--
-- Block with everything needed for a player
--
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity player is
Port (
-- User controls
Right : in STD_LOGIC;
Left : in STD_LOGIC;
Start : in STD_LOGIC;
Shoot : in STD_LOGIC;
-- Control signals
clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Clear : in STD_LOGIC;
ScoreClear : in STD_LOGIC;
Enable: in STD_LOGIC;
-- Internal signals
hit : in STD_LOGIC;
posShip : out STD_LOGIC_VECTOR (4 downto 0);
startPulse : out STD_LOGIC;
BulletX : out STD_LOGIC_VECTOR (4 downto 0);
BulletY : out STD_LOGIC_VECTOR (3 downto 0);
BulletActive : out STD_LOGIC;
Score : out STD_LOGIC_VECTOR (7 downto 0));
end player;
architecture Structural of player is
-- Component declaration for player spaceship control block:
COMPONENT spaceship
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear: in STD_LOGIC;
left : in STD_LOGIC;
right : in STD_LOGIC;
enable : in STD_LOGIC;
posH : out STD_LOGIC_VECTOR (4 downto 0)
);
END COMPONENT;
-- Component declaration for button edge detector (without debouncing )
COMPONENT edgeDetector
PORT (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
clear: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
END COMPONENT;
-- Component declaration for button edge detector (with/ debouncing )
COMPONENT edgeDetectorDebounce
PORT (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
clear: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
END COMPONENT;
-- Component declaration for bullet shooting control
COMPONENT bullet
PORT (
clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
enable : in std_logic;
hit : in std_logic;
shoot : in std_logic;
posH : in std_logic_vector(4 downto 0);
flying : out std_logic;
bullX : out std_logic_vector(4 downto 0);
bullY : out std_logic_vector(3 downto 0)
);
END COMPONENT;
-- Signals to connect things internally
signal leftDetected: std_logic;
signal rightDetected: std_logic;
signal posHBus: std_logic_vector( 4 downto 0);
begin
spaceshipControl: spaceship
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
left => leftDetected,
right => rightDetected,
enable => enable,
posH => posHBus
);
leftEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
input => Left,
detected => leftDetected
);
rightEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
input => Right,
detected => rightDetected
);
startEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => '0',
enable => '1',
input => Start,
detected => startPulse
);
laserGun: bullet
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
hit => hit,
shoot => Shoot,
posH => posHBus,
flying => BulletActive,
bullX => BulletX,
bullY => BulletY
);
posShip <= posHBus;
process( clk, reset )
variable intScore: integer range 0 to 255;
begin
if Reset = '1' then
intScore := 0;
elsif clk'event and clk = '1' then
-- Erase score
if ScoreClear = '1' then
intScore := 0;
-- Increase score when alien is hit
elsif hit = '1' then
intScore := intScore + 1;
end if;
end if;
score <= std_logic_vector( to_unsigned( intScore, 8));
end process;
end Structural;
| gpl-3.0 | fc6d3ee0842fa97422ec1509938e93c8 | 0.554834 | 3.576285 | false | false | false | false |
BBN-Q/VHDL-Components | src/Synchronizer.vhd | 1 | 1,486 | -- 1 bit synchronizer based of n flip-flops for clock-domain crossings.
-- drive constant `data_in` to use as a reset synchronizer
--
-- Original author: Colm Ryan
--
-- Copyright (c) 2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
generic (
RESET_VALUE : std_logic := '0'; -- reset value of all flip-flops in the chain
NUM_FLIP_FLOPS : natural := 2 -- number of flip-flops in the synchronizer chain
);
port(
rst : in std_logic; -- asynchronous, high-active
clk : in std_logic; -- destination clock
data_in : in std_logic;
data_out : out std_logic
);
end synchronizer;
architecture arch of synchronizer is
--synchronizer chain of flip-flops
signal sync_chain : std_logic_vector(NUM_FLIP_FLOPS-1 downto 0) := (others => RESET_VALUE);
-- Xilinx XST: disable shift-register LUT (SRL) extraction
attribute shreg_extract : string;
attribute shreg_extract of sync_chain : signal is "no";
-- Vivado: set ASYNC_REG to specify registers receive asynchronous data
-- also acts as DONT_TOUCH
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_chain : signal is "TRUE";
begin
main : process(clk, rst)
begin
if rst = '1' then
sync_chain <= (others => RESET_VALUE);
elsif rising_edge(clk) then
sync_chain <= sync_chain(sync_chain'high-1 downto 0) & data_in;
end if;
end process;
data_out <= sync_chain(sync_chain'high);
end architecture;
| mpl-2.0 | 446141f44a5172b5573229918e52c752 | 0.683042 | 3.687345 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_FIR_resized4_0/sim/design_1_FIR_resized4_0.vhd | 2 | 10,444 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized4_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized4_0;
ARCHITECTURE design_1_FIR_resized4_0_arch OF design_1_FIR_resized4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized4_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized4_0",
C_COEF_FILE => "design_1_FIR_resized4_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized4_0_arch;
| mit | eb50f2abd4718c145b769c0ee1c01b6c | 0.633953 | 3.261711 | false | true | false | false |
David-Estevez/spaceinvaders | src/counter_tb.vhd | 1 | 1,863 | library ieee;
use ieee.std_logic_1164.all;
-- uncomment the following library declaration if using
-- arithmetic functions with signed or unsigned values
--use ieee.numeric_std.all;
entity counter_tb is
end counter_tb;
architecture behavior of counter_tb is
-- component declaration for the unit under test (uut)
component counter
generic ( n: integer;
max: integer );
port(
clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
enable: in STD_LOGIC;
count_out : out std_logic_vector(n-1 downto 0);
cout : out std_logic
);
end component;
--inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal clear : std_logic := '0';
signal enable: std_logic := '1';
--outputs
signal count_out_3 : std_logic_vector(2 downto 0);
signal cout: std_logic;
-- clock period definitions
constant clk_period : time := 40 ns;
begin
-- instantiate the unit under test (uut)
uut: counter
generic map (3,5) -- 4-bit counter
port map (
clk => clk,
reset => reset,
clear => clear,
enable => enable,
count_out => count_out_3,
cout => cout
);
-- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
clear <= '1';
wait for clk_period;
clear <= '0';
wait for clk_period*10;
enable <= '0';
wait for clk_period*2;
enable <= '1';
wait for clk_period*10;
wait;
end process;
end;
| gpl-3.0 | e2d5a6d6bff3995a863186e8a6e7999c | 0.565217 | 3.568966 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/sim/RAT_RegisterFile_0_0.vhd | 2 | 3,653 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:RegisterFile:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_RegisterFile_0_0 IS
PORT (
D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DY_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADRX : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ADRY : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END RAT_RegisterFile_0_0;
ARCHITECTURE RAT_RegisterFile_0_0_arch OF RAT_RegisterFile_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_RegisterFile_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT RegisterFile IS
PORT (
D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DX_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DY_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADRX : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ADRY : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END COMPONENT RegisterFile;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : RegisterFile
PORT MAP (
D_IN => D_IN,
DX_OUT => DX_OUT,
DY_OUT => DY_OUT,
ADRX => ADRX,
ADRY => ADRY,
WE => WE,
CLK => CLK
);
END RAT_RegisterFile_0_0_arch;
| mit | 2a97421c79ac900983bb4a5d8f63cbaa | 0.717219 | 3.970652 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/noah-huesser/axis_to_data_lanes_v1_0/src/axis_to_data_lanes.vhd | 5 | 2,362 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity axis_to_data_lanes is
generic (
Decimation: integer := 1;
Offset: integer := 32768
);
port (
ClkxCI: in std_logic;
RstxRBI: in std_logic;
AxiTDataxDI: in std_logic_vector(31 downto 0) := (others => '0');
AxiTValid: in std_logic := '0';
AxiTReady: out std_logic := '1';
Data0xDO: out std_logic_vector(15 downto 0);
Data1xDO: out std_logic_vector(15 downto 0);
DataStrobexDO: out std_logic
);
end axis_to_data_lanes;
architecture V1 of axis_to_data_lanes is
signal DataxDP, DataxDN : std_logic_vector(31 downto 0) := (others => '0');
signal StrobexDP, StrobexDN : std_logic := '0';
signal CntxDP, CntxDN: unsigned(16 downto 0) := (others => '0');
begin
-- Persistent signal mappings
Data0xDO <= DataxDP(15 downto 0);
Data1xDO <= DataxDP(31 downto 16);
DataStrobexDO <= StrobexDP;
-- FF logic
process(ClkxCI)
begin
if rising_edge(ClkxCI) then
if RstxRBI = '0' then
-- Reset Signals
DataxDP <= (others => '0');
StrobexDP <= '0';
CntxDP <= (others => '0');
AxiTReady <= '0';
else
-- Advance signals by 1
DataxDP <= DataxDN;
StrobexDP <= StrobexDN;
CntxDP <= CntxDN;
AxiTReady <= '1';
end if;
end if;
end process;
p_converter: process(AxiTValid, CntxDP, AxiTDataxDI)
variable X: std_logic_vector(16 downto 0);
variable Y: std_logic_vector(16 downto 0);
variable A: std_logic_vector(15 downto 0);
variable B: std_logic_vector(15 downto 0);
begin
if AxiTValid = '1' then
-- receive every nth sample
if CntxDP = Decimation - 1 then
A := AxiTDataxDI(15 downto 0);
B := AxiTDataxDI(31 downto 16);
X := std_logic_vector(resize(signed(A),17) + Offset);
Y := std_logic_vector(resize(signed(B),17) + Offset);
DataxDN <= Y(15 downto 0) & X(15 downto 0);
StrobexDN <= '1';
CntxDN <= (others => '0');
else
DataxDN <= DataxDP;
CntxDN <= CntxDP + 1;
StrobexDN <= '0';
end if;
else
DataxDN <= DataxDP;
CntxDN <= CntxDP;
StrobexDN <= '0';
end if;
end process;
end V1;
| mit | 2b2dd5ebcb2e79d59bb271e62d88ec30 | 0.563082 | 3.684867 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.vhdl | 1 | 13,218 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:43 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.vhdl
-- Design : RAT_ControlUnit_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ControlUnit_0_0_ControlUnit is
port (
ALU_OPY_SEL : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
IO_OE : out STD_LOGIC;
RF_OE : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 0 to 0 );
RF_WR : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR ( 2 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
\OPCODE_HI_5_4__s_port_]\ : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\OPCODE_LO_2_0__s_port_]\ : in STD_LOGIC;
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
INT : in STD_LOGIC;
\OPCODE_HI_5_2__s_port_\ : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_ControlUnit_0_0_ControlUnit : entity is "ControlUnit";
end RAT_ControlUnit_0_0_ControlUnit;
architecture STRUCTURE of RAT_ControlUnit_0_0_ControlUnit is
signal ALU_OPY_SEL_reg_i_1_n_0 : STD_LOGIC;
signal ALU_OPY_SEL_reg_i_2_n_0 : STD_LOGIC;
signal NS : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \OPCODE_HI_5_2__s_net_1\ : STD_LOGIC;
signal \OPCODE_HI_5_4__s_net_1\ : STD_LOGIC;
signal \OPCODE_LO_2_0__s_net_1\ : STD_LOGIC;
signal PS : STD_LOGIC_VECTOR ( 1 downto 0 );
signal RF_WR_INST_0_i_1_n_0 : STD_LOGIC;
signal RF_WR_INST_0_i_2_n_0 : STD_LOGIC;
signal \RF_WR_SEL[0]_INST_0_i_1_n_0\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ALU_OPY_SEL_reg : label is "LD";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ALU_OPY_SEL_reg_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of I_FLAG_CLR_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of PC_INC_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \PS[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of RF_WR_INST_0_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of RF_WR_INST_0_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \RF_WR_SEL[0]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of SP_RESET_INST_0 : label is "soft_lutpair1";
begin
\OPCODE_HI_5_2__s_net_1\ <= \OPCODE_HI_5_2__s_port_\;
\OPCODE_HI_5_4__s_net_1\ <= \OPCODE_HI_5_4__s_port_]\;
\OPCODE_LO_2_0__s_net_1\ <= \OPCODE_LO_2_0__s_port_]\;
ALU_OPY_SEL_reg: unisim.vcomponents.LDCE
generic map(
INIT => '0'
)
port map (
CLR => '0',
D => ALU_OPY_SEL_reg_i_1_n_0,
G => ALU_OPY_SEL_reg_i_2_n_0,
GE => '1',
Q => ALU_OPY_SEL
);
ALU_OPY_SEL_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"40000040"
)
port map (
I0 => OPCODE_HI_5(2),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(4),
I3 => OPCODE_HI_5(0),
I4 => OPCODE_HI_5(3),
O => ALU_OPY_SEL_reg_i_1_n_0
);
ALU_OPY_SEL_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => PS(1),
I1 => PS(0),
O => ALU_OPY_SEL_reg_i_2_n_0
);
\ALU_SEL[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF000820AA000820"
)
port map (
I0 => RF_WR_INST_0_i_1_n_0,
I1 => OPCODE_LO_2(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_HI_5(4),
I5 => RF_WR_INST_0_i_2_n_0,
O => ALU_SEL(1)
);
\ALU_SEL[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0C0000000000"
)
port map (
I0 => RF_WR_INST_0_i_2_n_0,
I1 => RF_WR_INST_0_i_1_n_0,
I2 => OPCODE_LO_2(1),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(4),
I5 => OPCODE_HI_5(1),
O => ALU_SEL(2)
);
IO_OE_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000080000"
)
port map (
I0 => \OPCODE_HI_5_4__s_net_1\,
I1 => OPCODE_HI_5(3),
I2 => OPCODE_HI_5(0),
I3 => OPCODE_HI_5(2),
I4 => PS(1),
I5 => PS(0),
O => IO_OE
);
I_FLAG_CLR_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => PC_OE
);
PC_INC_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => PC_INC
);
PC_LD_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000002FFFF"
)
port map (
I0 => \OPCODE_HI_5_2__s_net_1\,
I1 => OPCODE_LO_2(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(1),
I4 => PS(1),
I5 => PS(0),
O => PC_LD
);
\PS[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => PS(1),
I1 => PS(0),
O => NS(0)
);
\PS[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2C"
)
port map (
I0 => INT,
I1 => PS(0),
I2 => PS(1),
O => NS(1)
);
\PS_reg[0]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => '1',
CLR => RST,
D => NS(0),
Q => PS(0)
);
\PS_reg[1]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => '1',
CLR => RST,
D => NS(1),
Q => PS(1)
);
RF_OE_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"3030000000001000"
)
port map (
I0 => OPCODE_HI_5(3),
I1 => OPCODE_HI_5(0),
I2 => \RF_WR_SEL[0]_INST_0_i_1_n_0\,
I3 => \OPCODE_LO_2_0__s_net_1\,
I4 => OPCODE_HI_5(4),
I5 => OPCODE_HI_5(1),
O => RF_OE
);
RF_WR_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF028088880280"
)
port map (
I0 => RF_WR_INST_0_i_1_n_0,
I1 => OPCODE_HI_5(1),
I2 => OPCODE_LO_2(0),
I3 => OPCODE_LO_2(1),
I4 => OPCODE_HI_5(4),
I5 => RF_WR_INST_0_i_2_n_0,
O => RF_WR
);
RF_WR_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => OPCODE_HI_5(3),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_HI_5(2),
I3 => PS(1),
I4 => PS(0),
O => RF_WR_INST_0_i_1_n_0
);
RF_WR_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => OPCODE_HI_5(3),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_HI_5(2),
I3 => PS(1),
I4 => PS(0),
O => RF_WR_INST_0_i_2_n_0
);
\RF_WR_SEL[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => OPCODE_HI_5(1),
I1 => OPCODE_HI_5(4),
I2 => \RF_WR_SEL[0]_INST_0_i_1_n_0\,
I3 => OPCODE_HI_5(0),
I4 => OPCODE_HI_5(3),
O => RF_WR_SEL(0)
);
\RF_WR_SEL[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => PS(0),
I1 => PS(1),
I2 => OPCODE_HI_5(2),
O => \RF_WR_SEL[0]_INST_0_i_1_n_0\
);
SP_RESET_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => PC_RESET
);
Z_FLAG_LD_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"80828080"
)
port map (
I0 => RF_WR_INST_0_i_1_n_0,
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(4),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_LO_2(1),
O => ALU_SEL(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ControlUnit_0_0 is
port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_ControlUnit_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_ControlUnit_0_0 : entity is "RAT_ControlUnit_0_0,ControlUnit,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_ControlUnit_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_ControlUnit_0_0 : entity is "ControlUnit,Vivado 2016.4";
end RAT_ControlUnit_0_0;
architecture STRUCTURE of RAT_ControlUnit_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^alu_sel\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal IO_OE_INST_0_i_1_n_0 : STD_LOGIC;
signal PC_LD_INST_0_i_1_n_0 : STD_LOGIC;
signal \^pc_oe\ : STD_LOGIC;
signal \^pc_reset\ : STD_LOGIC;
signal RF_OE_INST_0_i_1_n_0 : STD_LOGIC;
signal \^rf_wr_sel\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of IO_OE_INST_0_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of PC_LD_INST_0_i_1 : label is "soft_lutpair4";
begin
ALU_SEL(3 downto 2) <= \^alu_sel\(3 downto 2);
ALU_SEL(1) <= \^alu_sel\(2);
ALU_SEL(0) <= \^alu_sel\(0);
C_FLAG_CLR <= \<const0>\;
C_FLAG_LD <= \^alu_sel\(0);
C_FLAG_SEL <= \<const0>\;
C_FLAG_SET <= \<const0>\;
I_FLAG_CLR <= \^pc_oe\;
I_FLAG_SET <= \<const0>\;
PC_MUX_SEL(1) <= \^pc_oe\;
PC_MUX_SEL(0) <= \<const0>\;
PC_OE <= \^pc_oe\;
PC_RESET <= \^pc_reset\;
REG_IMMED_SEL <= \<const0>\;
RF_WR_SEL(1) <= \^rf_wr_sel\(1);
RF_WR_SEL(0) <= \^rf_wr_sel\(1);
SCR_ADDR_SEL(1) <= \^pc_oe\;
SCR_ADDR_SEL(0) <= \^pc_oe\;
SCR_OE <= \<const0>\;
SCR_WR <= \^pc_oe\;
SHAD_C_LD <= \<const0>\;
SHAD_Z_LD <= \<const0>\;
SP_LD <= \^pc_oe\;
SP_MUX_SEL(1) <= \^pc_oe\;
SP_MUX_SEL(0) <= \<const0>\;
SP_RESET <= \^pc_reset\;
Z_FLAG_CLR <= \<const0>\;
Z_FLAG_LD <= \^alu_sel\(0);
Z_FLAG_SEL <= \<const0>\;
Z_FLAG_SET <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
IO_OE_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => OPCODE_HI_5(1),
I1 => OPCODE_HI_5(4),
O => IO_OE_INST_0_i_1_n_0
);
PC_LD_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => OPCODE_HI_5(3),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_HI_5(4),
I3 => OPCODE_HI_5(2),
O => PC_LD_INST_0_i_1_n_0
);
RF_OE_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => OPCODE_LO_2(1),
I1 => OPCODE_LO_2(0),
O => RF_OE_INST_0_i_1_n_0
);
U0: entity work.RAT_ControlUnit_0_0_ControlUnit
port map (
ALU_OPY_SEL => ALU_OPY_SEL,
ALU_SEL(2 downto 1) => \^alu_sel\(3 downto 2),
ALU_SEL(0) => \^alu_sel\(0),
CLK => CLK,
INT => INT,
IO_OE => IO_OE,
OPCODE_HI_5(4 downto 0) => OPCODE_HI_5(4 downto 0),
\OPCODE_HI_5_2__s_port_\ => PC_LD_INST_0_i_1_n_0,
\OPCODE_HI_5_4__s_port_]\ => IO_OE_INST_0_i_1_n_0,
OPCODE_LO_2(1 downto 0) => OPCODE_LO_2(1 downto 0),
\OPCODE_LO_2_0__s_port_]\ => RF_OE_INST_0_i_1_n_0,
PC_INC => PC_INC,
PC_LD => PC_LD,
PC_OE => \^pc_oe\,
PC_RESET => \^pc_reset\,
RF_OE => RF_OE,
RF_WR => RF_WR,
RF_WR_SEL(0) => \^rf_wr_sel\(1),
RST => RST
);
end STRUCTURE;
| mit | 02e07332b6690dc4be8057cda7f6c670 | 0.538886 | 2.709717 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment5-Ram_Reg/Testbenches/ScratchRamTestBench.vhd | 1 | 4,152 | --------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 18:59:22 01/11/2012
-- Design Name:
-- Module Name: F:/repos/cpe-233-test-benches/lab-4-arc/RegisterFileTestBench.vhd
-- Project Name: RAT CPU
-- Target Device: xc7a50tcsg324-1
-- Tool versions:
-- Description: Testbench for Scratch RAM component of RAT CPU.
--
-- VHDL Test Bench Created by ISE for module: RegisterFile
--
-- Dependencies: ScratchRAM
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Runtime must be set to 700ns for proper execution
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ScratchRamTestBench IS
END ScratchRamTestBench;
ARCHITECTURE behavior OF ScratchRamTestBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ScratchRam
PORT(
DATA_IN : IN std_logic_vector(9 downto 0);
DATA_OUT : OUT std_logic_vector(9 downto 0);
ADDR : IN std_logic_vector(7 downto 0);
WE : IN std_logic;
CLK : IN std_logic
);
END COMPONENT;
-- test signals
signal data_x_exp : std_logic_vector(9 downto 0) := "0000000000";
signal data_y_exp : std_logic_vector(9 downto 0) := "0000000000";
--Inputs
signal D_IN_tb : std_logic_vector(9 downto 0) := (others => '0');
signal ADRX_tb : std_logic_vector(7 downto 0) := (others => '0');
signal ADRY_tb : std_logic_vector(7 downto 0) := (others => '0');
signal DX_OE_tb : std_logic := '0';
signal WE_tb : std_logic := '0';
signal CLK_tb : std_logic := '0';
--Outputs
signal DX_OUT_tb : std_logic_vector(9 downto 0);
signal DY_OUT_tb : std_logic_vector(9 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ScratchRam PORT MAP (
DATA_IN => D_IN_tb,
DATA_OUT => DX_OUT_tb,
ADDR => ADRX_tb,
WE => WE_tb,
CLK => CLK_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- verify memory
VERIFY_process :process
variable I : integer range 0 to 32 := 0;
begin
--Write to RegisterFile
ADRX_tb<="00000000";
D_IN_tb<="0000000000";
wait for 4ns;
WE_tb <= '1'; --togle high before rising edge
wait for 1ns;
while( I < 32) loop
wait for 1ns;
WE_tb <= '0'; --drop after rising edge
wait for 1ns;
ADRX_tb <= ADRX_tb + 1; --prepare next address and data
wait for 1ns;
D_IN_tb <= D_IN_tb +2;
wait for 6ns;
I := I+1;
if(I <32) then
WE_tb <= '1';
end if;
wait for 1ns;
end loop;
WE_tb <= '0';
DX_OE_tb <= '1';
wait for 75ns; --no reason, just like to start at a nice number such as 400ns...
-- Read from RegisterFile
I := 0;
-- set initial values
data_x_exp <= "0000000000";
data_y_exp <= "0000000010";
ADRX_tb <= "00000000";
ADRY_tb <= "00000001";
-- loop through all memory locations. NOTE: can read two at once
while ( I < 16) loop
WE_tb <= '0';
wait for 1ns;
if not(DX_OUT_tb = data_x_exp) then
report "error with data X at t= " & time'image(now)
severity failure;
else
report "data X at t= " & time'image(now) & " is good"
severity note;
end if;
if not(DY_OUT_tb = data_y_exp) then
report "error with data Y at t= " & time'image(now)
severity failure;
else
report "data Y at t= " & time'image(now) & " is good"
severity note;
end if;
wait for 1ns;
--get new values
data_x_exp <= data_x_exp + 4 ; --add 4 because each location increases by 2, and you're increasing by 2 memory locations
data_y_exp <= data_y_exp + 4 ;
ADRX_tb <= ADRX_tb + 2;
ADRY_tb <= ADRY_tb + 2;
wait for 8ns;
I := I + 1;
end loop;
wait for 40ns; -- again, just lining up for a nice start time of 600ns.
end process;
END; | mit | 823e251dba9410269ceb7fcea85fafba | 0.586224 | 3.18894 | false | true | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_KC705.vhdl | 1 | 16,562 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_KC705 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 200 MHz
);
port (
ClockIn_200MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_200MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_175MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_175MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- MMCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 200.000 0.000 50.0 97.642 89.971
-- CLK_OUT1 100.000 0.000 50.0 111.850 89.971
-- CLK_OUT2 125.000 0.000 50.0 107.064 89.971
-- CLK_OUT3 250.000 0.000 50.0 93.464 89.971
-- CLK_OUT4 10.000 0.000 50.0 175.649 89.971
--
--
-- PLL - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT1 175.000 0.000 50.0 82.535 112.560
-- CLK_OUT2 125.000 0.000 50.0 87.158 112.560
architecture rtl of clknet_ClockNetwork_KC705 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 200 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (200 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal PLL_Reset : STD_LOGIC;
signal PLL_Reset_clr : STD_LOGIC;
signal PLL_ResetState : STD_LOGIC := '0';
signal PLL_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal PLL_Locked_async : STD_LOGIC;
signal PLL_Locked : STD_LOGIC;
signal PLL_Locked_d : STD_LOGIC := '0';
signal PLL_Locked_re : STD_LOGIC;
signal PLL_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_10MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_125MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_250MHz : STD_LOGIC;
signal MMCM_Clock_10MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_125MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_250MHz_BUFG : STD_LOGIC;
signal PLL_Clock_125MHz : STD_LOGIC;
signal PLL_Clock_175MHz : STD_LOGIC;
-- signal PLL_Clock_125MHz_BUFG : STD_LOGIC;
signal PLL_Clock_175MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_250MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 3 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Input(2) => PLL_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked, --
Output(2) => PLL_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset NOR MMCM_Locked;
PLL_Reset_clr <= ClkNet_Reset NOR PLL_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
PLL_Locked_d <= PLL_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= NOT MMCM_Locked_d AND MMCM_Locked;
PLL_Locked_re <= NOT PLL_Locked_d AND PLL_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
PLL_ResetState <= ffrs(q => PLL_ResetState, rst => PLL_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
PLL_LockedState <= ffrs(q => PLL_LockedState, rst => PLL_Reset, set => PLL_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
PLL_Reset_delayed <= shreg_left(PLL_Reset_delayed, PLL_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
PLL_Reset <= PLL_Reset_delayed(PLL_Reset_delayed'high);
Locked <= MMCM_LockedState AND PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_200MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => MMCM_Clock_10MHz,
O => MMCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => MMCM_Clock_125MHz,
O => MMCM_Clock_125MHz_BUFG
);
-- 175 MHz BUFG
BUFG_Clock_175MHz : BUFG
port map (
I => PLL_Clock_175MHz,
O => PLL_Clock_175MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 250 MHz BUFG
BUFG_Clock_250MHz : BUFG
port map (
I => MMCM_Clock_250MHz,
O => MMCM_Clock_250MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCME2_ADV
generic map (
STARTUP_WAIT => FALSE,
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => FALSE,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 5.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_DIVIDE => 4,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => 0.0,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_200MHz_BUFG,
CLKFBSTOPPED => open,
CLKOUT0 => MMCM_Clock_200MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_100MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_125MHz,
CLKOUT2B => open,
CLKOUT3 => MMCM_Clock_250MHz,
CLKOUT3B => open,
CLKOUT4 => MMCM_Clock_10MHz,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
System_PLL : PLLE2_ADV
generic map (
BANDWIDTH => "HIGH",
COMPENSATION => "BUF_IN",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048,
CLKFBOUT_MULT => 35,
CLKFBOUT_PHASE => 0.000,
DIVCLK_DIVIDE => 4,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 14,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500
)
port map (
RST => PLL_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKFBIN => PLL_Clock_175MHz_BUFG,
CLKFBOUT => open,
CLKOUT0 => PLL_Clock_175MHz,
CLKOUT1 => PLL_Clock_125MHz,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
-- Other control and status signals
PWRDWN => '0',
LOCKED => PLL_Locked_async
);
Control_Clock_200MHz <= Control_Clock_BUFR;
Clock_250MHz <= MMCM_Clock_250MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_175MHz <= PLL_Clock_175MHz_BUFG;
Clock_125MHz <= MMCM_Clock_125MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
Clock_10MHz <= MMCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked250MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_250MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked175MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => PLL_Clock_175MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_175MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | 3b15d61f8295e3ae7586d8f605786431 | 0.516846 | 3.515602 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_0/synth/RAT_Mux4x1_8_0_0.vhd | 2 | 3,970 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_8_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux4x1_8_0_0;
ARCHITECTURE RAT_Mux4x1_8_0_0_arch OF RAT_Mux4x1_8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux4x1_8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux4x1_8_0_0_arch: ARCHITECTURE IS "Mux4x1_8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux4x1_8_0_0_arch : ARCHITECTURE IS "RAT_Mux4x1_8_0_0,Mux4x1_8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux4x1_8_0_0_arch: ARCHITECTURE IS "RAT_Mux4x1_8_0_0,Mux4x1_8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux4x1_8,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux4x1_8
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_8_0_0_arch;
| mit | 3a1e1bea3c81c5397693eb1aac104702 | 0.719144 | 3.532028 | false | false | false | false |
blytkerchan/BrainF | BrainF_tb.vhdl | 1 | 6,889 | -- BrainF* interpreter - testbench
-- Version: 20141001
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.txt_util.all;
entity BrainF_tb is
end entity;
architecture behavior of BrainF_tb is
constant WARMUP_COUNTDOWN : integer := 4;
constant INITIAL_COUNTDOWN : integer := 10;
--constant PROGRAM : string := "++++++++";
--constant PROGRAM : string := "[.]";
--constant PROGRAM : string := "-+[-+][[-+]]";
--constant PROGRAM : string := "++[-][[-+]]";
--constant PROGRAM : string := ">+++++++++[<++++++++>-]<.>+++++++[<++++>-]<+.+++++++..+++.0>++++++++[<++++>-] <.>+++++++++++[<++++++++>-]<-.--------.+++.------.--------.0>++++++++[<++++>- ]<+.0++++++++++.";
constant PROGRAM : string := ">+++++++++[<++++++++>-]<.>+++++++[<++++>-]<+.+++++++..+++.[-]>++++++++[<++++>-] <.>+++++++++++[<++++++++>-]<-.--------.+++.------.--------.[-]>++++++++[<++++>- ]<+.[-]++++++++++.";
constant PROGRAM_TIMEOUT : Time := 138 ns;
component BrainF is
generic(
MAX_INSTRUCTION_COUNT : positive := 65536
; MEMORY_SIZE : positive := 65536
);
port(
resetN : in std_logic
; clock : in std_logic
; load_instructions : in std_logic
; instruction_octet : in std_logic_vector(7 downto 0)
; ack_instruction : out std_logic
; program_full : out std_logic
; read_memory : in std_logic
; memory_byte : out std_logic_vector(7 downto 0)
; memory_byte_ready : out std_logic
; memory_byte_read_ack : in std_logic
; done : out std_logic
);
end component;
type State is (warmup, initial, start_loading_program, loading_program, running_program, success);
function to_std_logic_vector(c : character) return std_logic_vector is
variable cc : integer;
begin
cc := character'pos(c);
return std_logic_vector(to_unsigned(cc, 8));
end to_std_logic_vector;
signal clock : std_logic := '0';
signal load_instructions : std_logic := '0';
signal instruction_octet : std_logic_vector(7 downto 0) := (others => '0');
signal ack_instruction : std_logic := '0';
signal program_full : std_logic := '0';
signal read_memory : std_logic := '0';
signal memory_byte : std_logic_vector(7 downto 0) := (others => '0');
signal memory_byte_ready : std_logic := '0';
signal memory_byte_read_ack : std_logic := '0';
signal done : std_logic := '0';
signal tb_state : State := warmup;
signal should_be_done : std_logic := '0';
signal end_of_simulation : std_logic := '0';
begin
interpreter : BrainF
port map(
resetN => '1'
, clock => clock
, load_instructions => load_instructions
, instruction_octet => instruction_octet
, ack_instruction => ack_instruction
, program_full => program_full
, read_memory => read_memory
, memory_byte => memory_byte
, memory_byte_ready => memory_byte_ready
, memory_byte_read_ack => memory_byte_read_ack
, done => done
);
-- generate the clock
clock <= not clock after 1 ps;
-- generate the time-out signal
should_be_done <= '1' after PROGRAM_TIMEOUT;
p_tb : process(clock)
variable countdown : integer := WARMUP_COUNTDOWN;
variable program_load_counter : integer := 0;
begin
if rising_edge(clock) then
case tb_state is
when warmup =>
assert done = '0' report "Cannot be done while warming up (pipe filling with halt instructions)" severity failure;
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
if countdown = 1 then
tb_state <= initial;
countdown := INITIAL_COUNTDOWN;
else
countdown := countdown - 1;
end if;
when initial =>
assert done = '1' report "Once warmed up, it should know it has no program and say it's done" severity failure;
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
if countdown = 1 then
tb_state <= start_loading_program;
else
countdown := countdown - 1;
end if;
when start_loading_program =>
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
instruction_octet <= to_std_logic_vector(program(1));
load_instructions <= '1';
tb_state <= loading_program;
program_load_counter := 2;
when loading_program =>
if program_load_counter <= program'length then
if ack_instruction = '1' then
instruction_octet <= to_std_logic_vector(program(program_load_counter));
program_load_counter := program_load_counter + 1;
end if;
else
load_instructions <= '0';
tb_state <= running_program;
end if;
when running_program =>
if should_be_done = '1' then
assert done = '1' report "Timeout!" severity failure;
end if;
if done = '1' then
tb_state <= success;
end if;
when success =>
end_of_simulation <= '1';
when others => null;
end case;
end if;
end process;
end behavior;
| lgpl-3.0 | b652f140b20fca81d8f72795da216eed | 0.514443 | 4.476283 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/RAT_CPU.vhd | 1 | 9,295 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/03/2016 10:45:34 AM
-- Design Name:
-- Module Name: RAT_CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAT_CPU is
Port (
IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
INT_IN : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_OE : out STD_LOGIC);
end RAT_CPU;
architecture Behavioral of RAT_CPU is
component ControlUnit
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC);
end component;
component counter
Port ( FROM_IMMED : in STD_LOGIC_VECTOR (9 downto 0);
FROM_STACK : in STD_LOGIC_VECTOR (9 downto 0);
INTERRUPT : in STD_LOGIC_VECTOR (9 downto 0);
PC_MUX_SEL : in STD_LOGIC_VECTOR (1 downto 0);
PC_OE : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_INC : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
PC_COUNT : out STD_LOGIC_VECTOR (9 downto 0);
PC_TRI : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component prog_rom
Port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end component;
component RegisterFile
Port ( D_IN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
ADRX : in STD_LOGIC_VECTOR (4 downto 0);
ADRY : in STD_LOGIC_VECTOR (4 downto 0);
DX_OE : in STD_LOGIC;
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
component alu
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (3 downto 0);
SUM : out STD_LOGIC_VECTOR (7 downto 0);
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC);
end component;
component FlagReg
Port ( IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC);
end component;
component ShadowFlagReg
port (
F_IN : in STD_LOGIC;
LD : in STD_LOGIC;
CLK : in STD_LOGIC;
FLAG : out STD_LOGIC
);
end component;
component StackPointer is
port (
D_IN_BUS : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
LD : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (7 downto 0);
D_OUT_DEC : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component scratchPad is
port (
Scr_Addr : in STD_LOGIC_VECTOR (7 downto 0);
Scr_Oe : in STD_LOGIC;
SCR_WE : in STD_LOGIC;
CLK : in STD_LOGIC;
SCR_DATA : inout STD_LOGIC_VECTOR (9 downto 0)
);
end component;
signal MULTI_BUS : STD_LOGIC_VECTOR (9 downto 0) := "ZZZZZZZZZZ";
-- Program counter signals
signal PC_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal PC_OE, PC_LD, PC_INC, PC_RST : STD_LOGIC;
signal PC_COUNT : STD_LOGIC_VECTOR (9 downto 0);
-- Prog-rom signal
signal Instruction : STD_LOGIC_VECTOR (17 downto 0);
-- Register file signals
signal RF_DATA_IN : STD_LOGIC_VECTOR (7 downto 0);
signal RF_WR_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal RF_OUT_X, RF_OUT_Y : STD_LOGIC_VECTOR (7 downto 0);
signal RF_OE, RF_WE : STD_LOGIC;
-- ALU signals
signal ALU_IN_B, ALU_OUT : STD_LOGIC_VECTOR (7 downto 0);
signal ALU_SEL : STD_LOGIC_VECTOR (3 downto 0);
signal REG_IMMED_SEL : STD_LOGIC;
signal ALU_OUT_C, ALU_OUT_Z : STD_LOGIC;
-- C Flag signals
signal C_FLAG, C_FLAG_SHAD, C_SET, C_CLR, C_LD, C_LD_SHAD, C_SEL : STD_LOGIC;
signal C_IN : STD_LOGIC;
-- Z Flag signals
signal Z_FLAG, Z_FLAG_SHAD, Z_SET, Z_CLR, Z_LD, Z_LD_SHAD, Z_SEL : STD_LOGIC;
signal Z_IN : STD_LOGIC;
-- Stack signals
signal SP_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal SP_LD, SP_RST : STD_LOGIC;
signal SP, SP_DEC : STD_LOGIC_VECTOR (7 downto 0);
-- ScratchPad signals
signal SCR_WR, SCR_OE : STD_LOGIC;
signal SCR_ADDR_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal SCR_ADDR : STD_LOGIC_VECTOR (7 downto 0);
-- Interrupt signals
signal I_FLAG, ISR_OUT, I_SET, I_CLR : STD_LOGIC;
begin
ISR : FlagReg port map (INT_IN, '0', I_SET, I_CLR, CLK, ISR_OUT);
I_FLAG <= INT_IN and ISR_OUT;
control : controlUnit PORT MAP (CLK, C_FLAG, Z_FLAG, I_FLAG, RST, Instruction (17 downto 13), Instruction (1 downto 0),
PC_LD, PC_INC, PC_RST, PC_OE, PC_MUX_SEL,
SP_LD, SP_MUX_SEL, SP_RST,
RF_WE, RF_WR_SEL, RF_OE, REG_IMMED_SEL,
ALU_SEL,
SCR_WR, SCR_OE, SCR_ADDR_SEL,
C_SEL, C_LD, C_SET, C_CLR,
Z_SEL, Z_LD, Z_SET, Z_CLR,
I_SET, I_CLR);
pc : counter PORT MAP (Instruction (12 downto 3), MULTI_BUS (9 downto 0), (others => '1'), PC_MUX_SEL, PC_OE, PC_LD, PC_INC, PC_RST, CLK, PC_COUNT, MULTI_BUS);
progRom : prog_rom PORT MAP (PC_COUNT, Instruction, CLK);
RF_DATA_IN <= ALU_OUT when RF_WR_SEL = "00"
else MULTI_BUS (7 downto 0) when RF_WR_SEL = "01"
else IN_PORT when RF_WR_SEL = "11"
else (others => '0');
regFile : RegisterFile PORT MAP (RF_DATA_IN, RF_OUT_X, RF_OUT_Y, Instruction (12 downto 8), Instruction (7 downto 3), RF_OE, RF_WE, CLK);
MULTI_BUS (7 downto 0) <= RF_OUT_X;
ALU_IN_B <= RF_OUT_Y when REG_IMMED_SEL = '0'
else Instruction (7 downto 0);
aluMod : alu PORT MAP (RF_OUT_X, ALU_IN_B, C_FLAG, ALU_SEL, ALU_OUT, ALU_OUT_C, ALU_OUT_Z);
C_IN <= ALU_OUT_C when C_SEL = '0'
else C_FLAG_SHAD;
Z_IN <= ALU_OUT_Z when Z_SEL = '0'
else Z_FLAG_SHAD;
cFlag : FlagReg PORT MAP (C_IN, C_LD, C_SET, C_CLR, CLK, C_FLAG);
zFlag : FlagReg PORT MAP (Z_IN, Z_LD, Z_SET, Z_CLR, CLK, Z_FLAG);
stack : StackPointer port map (MULTI_BUS (7 downto 0), SP_MUX_SEL, SP_LD, SP_RST, CLK, SP, SP_DEC);
SCR_ADDR <= RF_OUT_Y when (SCR_ADDR_SEL = "00")
else Instruction (7 downto 0) when (SCR_ADDR_SEL = "01")
else SP when (SCR_ADDR_SEL = "10")
else SP_DEC;
scratch : scratchPad port map (SCR_ADDR, SCR_OE, SCR_WR, CLK, MULTI_BUS);
PORT_ID <= Instruction (7 downto 0);
OUT_PORT <= MULTI_BUS (7 downto 0);
end Behavioral;
| mit | 688c2b35c7fa3c4e4ea0cd7fa28423c7 | 0.511027 | 3.441318 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/Inversor.vhd | 1 | 678 | ----------------------------------------------------------------------------------
-- Create Date: 15:15:27 04/04/2017
-- Module Name: Inversor - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Inversor is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0));
end Inversor;
architecture Behavioral of Inversor is
signal aux: STD_LOGIC_VECTOR (3 downto 0);
begin
aux(0)<= not A(0);
aux(1)<= not A(1);
aux(2)<= not A(2);
aux(3)<= not A(3);
B(0)<= aux(0);
B(1)<= aux(1);
B(2)<= aux(2);
B(3)<= aux(3);
end Behavioral;
| gpl-3.0 | f9447106d8490ca17e7ce413b7393fcd | 0.457227 | 3.39 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_sim_netlist.vhdl | 2 | 1,760 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_sim_netlist.vhdl
-- Design : RAT_xlconstant_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_xlconstant_0_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_xlconstant_0_0 : entity is "yes";
end RAT_xlconstant_0_0;
architecture STRUCTURE of RAT_xlconstant_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
dout(9) <= \<const1>\;
dout(8) <= \<const1>\;
dout(7) <= \<const1>\;
dout(6) <= \<const1>\;
dout(5) <= \<const1>\;
dout(4) <= \<const1>\;
dout(3) <= \<const1>\;
dout(2) <= \<const1>\;
dout(1) <= \<const1>\;
dout(0) <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 2e97913ae97df3f906f6d341cb005874 | 0.603409 | 3.801296 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/cpu_TB.vhd | 1 | 1,768 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/04/2016 11:46:58 PM
-- Design Name:
-- Module Name: cpu_TB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cpu_TB is
-- Port ( );
end cpu_TB;
architecture Behavioral of cpu_TB is
component RAT_WRAPPER
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end component;
signal BTN, RST, CLK : STD_LOGIC;
signal LEDS, SWITCHES : STD_LOGIC_VECTOR (7 downto 0);
begin
cpu : RAT_WRAPPER PORT MAP (LEDS, SWITCHES, BTN, RST, CLK);
process
begin
CLK <= '0';
wait for 20ns;
CLK <= '1';
wait for 20ns;
end process;
process
begin
RST <= '1';
SWITCHES <= x"09";
wait for 50ns;
RST <= '0';
wait for 10050ns;
BTN <= '1';
wait for 400ns;
BTN <= '0';
wait;
end process;
end Behavioral;
| mit | 3acc97709b0ff905d0a9e401abaefe0d | 0.50905 | 4.092593 | false | false | false | false |
BBN-Q/VHDL-Components | src/DelayLine.vhd | 1 | 1,185 | -- Shift register delay line with synchronous reset
--
-- Original authors Colm Ryan and Blake Johnson
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
entity DelayLine is
generic(
REG_WIDTH : natural := 1;
RESET_VALUE : std_logic := '0';
DELAY_TAPS : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(REG_WIDTH-1 downto 0);
data_out : out std_logic_vector(REG_WIDTH-1 downto 0)
);
end entity;
architecture arch of DelayLine is
type DELAY_LINE_t is array(DELAY_TAPS-1 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
shared variable delay_line : DELAY_LINE_t := (others => (others => RESET_VALUE));
attribute shreg_extract : string;
attribute shreg_extract of delay_line : variable is "TRUE";
begin
main : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
delay_line := (others => (others => RESET_VALUE));
data_out <= (others => RESET_VALUE);
else
delay_line := delay_line(delay_line'high-1 downto 0) & data_in;
data_out <= delay_line(delay_line'high);
end if;
end if;
end process;
end architecture;
| mpl-2.0 | f06f0d61a07081c4d0e3efe7a918ba5c | 0.665823 | 3.347458 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_alu_0_0/sim/RAT_alu_0_0.vhd | 2 | 3,525 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:alu:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_alu_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END RAT_alu_0_0;
ARCHITECTURE RAT_alu_0_0_arch OF RAT_alu_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_alu_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT alu IS
GENERIC (
data_width : INTEGER;
sel_width : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END COMPONENT alu;
BEGIN
U0 : alu
GENERIC MAP (
data_width => 8,
sel_width => 4
)
PORT MAP (
A => A,
B => B,
C_IN => C_IN,
Sel => Sel,
SUM => SUM,
C_FLAG => C_FLAG,
Z_FLAG => Z_FLAG
);
END RAT_alu_0_0_arch;
| mit | 1fa4df6fda5a7de6065291b7843fe85d | 0.697305 | 3.882159 | false | false | false | false |
marcoep/MusicBoxNano | hdl/CrossClockDomain.vhd | 1 | 1,888 | -------------------------------------------------------------------------------
-- Title : Simple Clock Domain Crossing for Single Bit Signals
-- Project :
-------------------------------------------------------------------------------
-- File : CrossClockDomain.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-28
-- Last update: 2016-07-28
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Clock Domain Crossing for std_logic signals with a 5-stage
-- synchronizer circuit.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Marco Eppenberger <mail@mebg.ch>
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-28 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CrossClockDomain is
port (
Clk_CI : in std_logic;
AsyncIn_SI : in std_logic;
SyncOut_SO : out std_logic);
end entity CrossClockDomain;
architecture RTL of CrossClockDomain is
signal clk_sync_0 : std_logic := '0';
signal clk_sync_1 : std_logic := '0';
signal clk_sync_2 : std_logic := '0';
signal clk_sync_3 : std_logic := '0';
begin -- architecture RTL
sync_clock_domain : process (Clk_CI) is
begin -- process sync_clock_domain
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
clk_sync_0 <= AsyncIn_SI;
clk_sync_1 <= clk_sync_0;
clk_sync_2 <= clk_sync_1;
clk_sync_3 <= clk_sync_2;
SyncOut_SO <= clk_sync_3;
end if;
end process sync_clock_domain;
end architecture RTL;
| gpl-3.0 | f0096745f657109d6b41fbff0227d8ab | 0.480932 | 4.195556 | false | false | false | false |
stefanct/aua | hw/io/sc_dummy/src/sc_dummy.vhd | 1 | 2,062 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity sc_test_slave is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t
);
end sc_test_slave;
architecture rtl of sc_test_slave is
signal cycle_cnt, cycle_cnt_nxt : unsigned(3 downto 0);
signal ready, ready_nxt : unsigned(3 downto 0);
signal reg, reg_nxt : sc_data_t;
signal sc_out, sc_out_nxt : sc_data_t;
type state_type is (st_done, st_wait);
signal state : state_type;
signal state_nxt : state_type;
begin
rd_data <= sc_out;
nxt: process(reset, state, cycle_cnt, reg, wr_data, address, wr, rd, ready, sc_out)
begin
cycle_cnt_nxt <= cycle_cnt;
reg_nxt <= reg;
sc_out_nxt <= sc_out;
rdy_cnt <= (others => '0');
ready_nxt <= ready;
state_nxt <= st_done;
if state=st_done then
if address(0)='0' then
if(wr='1') then
cycle_cnt_nxt <= unsigned(wr_data(3 downto 0));
end if;
if rd='1' then
sc_out_nxt <= (sc_out_nxt'length-1 downto cycle_cnt'length => '0')&std_logic_vector(cycle_cnt);
end if;
else
if(wr='1') then
reg_nxt <= wr_data;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
if(rd='1') then
sc_out_nxt <= reg;
state_nxt <= st_wait;
ready_nxt <= cycle_cnt;
end if;
end if;
else
ready_nxt <= ready-1;
sc_out_nxt <= reg;
if ready > 3 then
rdy_cnt <= "11";
else
rdy_cnt <= ready(1 downto 0);
end if;
if ready /= 0 then
state_nxt <= st_wait;
end if;
end if;
end process;
sync: process(clk, reset)
begin
if (reset='1') then
sc_out <= (others => '0');
cycle_cnt <= (others => '0');
reg <= (others => '0');
ready <= (others => '0');
state <= st_done;
elsif rising_edge(clk) then
sc_out <= sc_out_nxt;
cycle_cnt <= cycle_cnt_nxt;
reg <= reg_nxt;
ready <= ready_nxt;
state <= state_nxt;
end if;
end process;
end rtl;
| gpl-3.0 | 3c1d0903751e455fac69ed03fd51afa5 | 0.604268 | 2.472422 | false | false | false | false |
marcoep/MusicBoxNano | hdl/SongDB.vhd | 1 | 5,792 | -------------------------------------------------------------------------------
-- Title : Song ROM and Duration Counter
-- Project :
-------------------------------------------------------------------------------
-- File : SongDB.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-28
-- Last update: 2016-07-29
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements the song ROM and the duration counter to release the
-- next key.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-28 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Helpers_Pkg.all;
entity SongDB is
port (
Clk_CI : in std_logic;
Reset_SI : in std_logic;
KeyTick_SI : in std_logic;
NewKeyData_DO : out std_logic_vector(6 downto 0);
NewKeyValid_SO : out std_logic);
end entity SongDB;
architecture RTL of SongDB is
-- ROM constants (adapt to Quartus IP and generated .mif file)
constant SONG_ROM_ADDR_WIDTH : integer := 11; -- adapt to song ROM address width
constant MAX_SONG_ADDR : integer := 1067; -- adapt to song ROM depth
-- duration counter
constant DURATION_COUNTER_WIDTH : integer := 10; -- fixed in MATLAB
signal DurCounter_S : unsigned(DURATION_COUNTER_WIDTH-1 downto 0) := (others => '0');
signal DurationZero_S : std_logic := '0';
signal LoadNextDuration_S : std_logic := '0';
-- address counter
signal GenNextAddr_S : std_logic := '0';
signal AddrCounter_S : unsigned(SONG_ROM_ADDR_WIDTH-1 downto 0) := (others => '0');
-- song rom output
signal ROMout_D : std_logic_vector(16 downto 0) := (others => '0');
signal CurKey_D : std_logic_vector(6 downto 0) := (others => '0');
signal CurDuration_D : std_logic_vector(9 downto 0) := (others => '0');
-- fsm
type states_t is (INIT, WAITZERO, ADDRLAT1, ROMLAT1, ROMLAT2);
signal State_SN, State_SP : states_t;
begin -- architecture RTL
-- instantiate song rom (latency 2)
SongROM_i : entity work.SongROM
port map (
address => std_logic_vector(AddrCounter_S),
clock => Clk_CI,
q => ROMout_D);
CurKey_D <= ROMout_D(6 downto 0);
CurDuration_D <= ROMout_D(16 downto 7);
-- address counter
addr_gen : process (Clk_CI) is
begin -- process addr_gen
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
AddrCounter_S <= (others => '0');
else
if GenNextAddr_S = '1' then
if AddrCounter_S = MAX_SONG_ADDR then
AddrCounter_S <= (others => '0');
else
AddrCounter_S <= AddrCounter_S + 1;
end if;
end if;
end if;
end if;
end process addr_gen;
-- duration counter
dur_gen : process (Clk_CI) is
begin -- process addr_gen
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
DurCounter_S <= (others => '0');
else
if KeyTick_SI = '1' then
DurCounter_S <= DurCounter_S - 1;
end if;
if LoadNextDuration_S = '1' then
DurCounter_S <= unsigned(CurDuration_D);
end if;
end if;
end if;
end process dur_gen;
DurationZero_S <= bool2sl(DurCounter_S = 0);
-- outputs
NewKeyData_DO <= CurKey_D;
NewKeyValid_SO <= LoadNextDuration_S;
-----------------------------------------------------------------------------
-- FSM
-----------------------------------------------------------------------------
fsm_comb : process (DurationZero_S, State_SP) is
begin -- process fsm_comb
-- default assignments
State_SN <= State_SP;
LoadNextDuration_S <= '0';
GenNextAddr_S <= '0';
case State_SP is
when INIT =>
-- init state, duration does not matter, just load address 0 data for
-- the first note
State_SN <= ADDRLAT1;
-------------------------------------------------------------------------
when WAITZERO =>
if DurationZero_S = '1' then
GenNextAddr_S <= '1';
State_SN <= ADDRLAT1;
end if;
-------------------------------------------------------------------------
when ADDRLAT1 =>
State_SN <= ROMLAT1;
-------------------------------------------------------------------------
when ROMLAT1 =>
State_SN <= ROMLAT2;
-------------------------------------------------------------------------
when ROMLAT2 =>
LoadNextDuration_S <= '1';
State_SN <= WAITZERO;
-----------------------------------------------------------------------
when others =>
State_SN <= INIT;
end case;
end process fsm_comb;
fsm_reg : process (Clk_CI) is
begin -- process fsm_reg
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
State_SP <= INIT;
else
State_SP <= State_SN;
end if;
end if;
end process fsm_reg;
end architecture RTL;
| gpl-3.0 | d2d23e322fcc035c1273c18a189ace9a | 0.464088 | 4.184971 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_0/synth/design_1_cic_compiler_0_0.vhd | 2 | 8,480 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "cic_compiler_v4_0_10,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_cic_compiler_0_0_arch : ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMPONENT_NAME=design_1_cic_compiler_0_0,C_FILTER_TYPE=1,C_NUM_STAGES=4,C_DIFF_DELAY=1,C_RATE=25,C_INPUT_WIDTH=16,C_OUTPUT_WIDTH=35,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=25,C_MAX_RATE=25,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=" &
"zynq,C_XDEVICEFAMILY=zynq,C_C1=35,C_C2=35,C_C3=35,C_C4=35,C_C5=0,C_C6=0,C_I1=35,C_I2=35,C_I3=35,C_I4=35,C_I5=0,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=16,C_M_AXIS_DATA_TDATA_WIDTH=40,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 16,
C_OUTPUT_WIDTH => 35,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 35,
C_C2 => 35,
C_C3 => 35,
C_C4 => 35,
C_C5 => 0,
C_C6 => 0,
C_I1 => 35,
C_I2 => 35,
C_I3 => 35,
C_I4 => 35,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
| mit | 141bce9ab5e7a3cb34fa04bb5a2eaac7 | 0.665448 | 3.118794 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/lcd_controller.vhd | 3 | 8,014 | --------------------------------------------------------------------------------
--
-- FileName: lcd_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 6/2/2006 Scott Larson
-- Initial Public Release
-- Version 2.0 6/13/2012 Scott Larson
--
-- CLOCK FREQUENCY: to change system clock frequency, change Line 65
--
-- LCD INITIALIZATION SETTINGS: to change, comment/uncomment lines:
--
-- Function Set
-- 2-line mode, display on Line 93 lcd_data <= "00111100";
-- 1-line mode, display on Line 94 lcd_data <= "00110100";
-- 1-line mode, display off Line 95 lcd_data <= "00110000";
-- 2-line mode, display off Line 96 lcd_data <= "00111000";
-- Display ON/OFF
-- display on, cursor off, blink off Line 104 lcd_data <= "00001100";
-- display on, cursor off, blink on Line 105 lcd_data <= "00001101";
-- display on, cursor on, blink off Line 106 lcd_data <= "00001110";
-- display on, cursor on, blink on Line 107 lcd_data <= "00001111";
-- display off, cursor off, blink off Line 108 lcd_data <= "00001000";
-- display off, cursor off, blink on Line 109 lcd_data <= "00001001";
-- display off, cursor on, blink off Line 110 lcd_data <= "00001010";
-- display off, cursor on, blink on Line 111 lcd_data <= "00001011";
-- Entry Mode Set
-- increment mode, entire shift off Line 127 lcd_data <= "00000110";
-- increment mode, entire shift on Line 128 lcd_data <= "00000111";
-- decrement mode, entire shift off Line 129 lcd_data <= "00000100";
-- decrement mode, entire shift on Line 130 lcd_data <= "00000101";
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY lcd_controller IS
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reinitializes lcd
lcd_enable : IN STD_LOGIC; --latches data into lcd controller
lcd_bus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); --data and control signals
busy : OUT STD_LOGIC := '1'; --lcd controller busy/idle feedback
rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd
lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --data signals for lcd
END lcd_controller;
ARCHITECTURE controller OF lcd_controller IS
TYPE CONTROL IS(power_up, initialize, ready, send);
SIGNAL state : CONTROL;
CONSTANT freq : INTEGER := 50; --system clock frequency in MHz
BEGIN
PROCESS(clk)
VARIABLE clk_count : INTEGER := 0; --event counter for timing
BEGIN
IF(clk'EVENT and clk = '1') THEN
CASE state IS
--wait 50 ms to ensure Vdd has risen and required LCD wait is met
WHEN power_up =>
busy <= '1';
IF(clk_count < (50000 * freq)) THEN --wait 50 ms
clk_count := clk_count + 1;
state <= power_up;
ELSE --power-up complete
clk_count := 0;
rs <= '0';
rw <= '0';
lcd_data <= "00110000";
state <= initialize;
END IF;
--cycle through initialization sequence
WHEN initialize =>
busy <= '1';
clk_count := clk_count + 1;
IF(clk_count < (10 * freq)) THEN --function set
lcd_data <= "00111100"; --2-line mode, display on
--lcd_data <= "00110100"; --1-line mode, display on
--lcd_data <= "00110000"; --1-line mdoe, display off
--lcd_data <= "00111000"; --2-line mode, display off
e <= '1';
state <= initialize;
ELSIF(clk_count < (60 * freq)) THEN --wait 50 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (70 * freq)) THEN --display on/off control
lcd_data <= "00001100"; --display on, cursor off, blink off
--lcd_data <= "00001101"; --display on, cursor off, blink on
--lcd_data <= "00001110"; --display on, cursor on, blink off
--lcd_data <= "00001111"; --display on, cursor on, blink on
--lcd_data <= "00001000"; --display off, cursor off, blink off
--lcd_data <= "00001001"; --display off, cursor off, blink on
--lcd_data <= "00001010"; --display off, cursor on, blink off
--lcd_data <= "00001011"; --display off, cursor on, blink on
e <= '1';
state <= initialize;
ELSIF(clk_count < (120 * freq)) THEN --wait 50 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (130 * freq)) THEN --display clear
lcd_data <= "00000001";
e <= '1';
state <= initialize;
ELSIF(clk_count < (2130 * freq)) THEN --wait 2 ms
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (2140 * freq)) THEN --entry mode set
lcd_data <= "00000110"; --increment mode, entire shift off
--lcd_data <= "00000111"; --increment mode, entire shift on
--lcd_data <= "00000100"; --decrement mode, entire shift off
--lcd_data <= "00000101"; --decrement mode, entire shift on
e <= '1';
state <= initialize;
ELSIF(clk_count < (2200 * freq)) THEN --wait 60 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSE --initialization complete
clk_count := 0;
busy <= '0';
state <= ready;
END IF;
--wait for the enable signal and then latch in the instruction
WHEN ready =>
IF(lcd_enable = '1') THEN
busy <= '1';
rs <= lcd_bus(9);
rw <= lcd_bus(8);
lcd_data <= lcd_bus(7 DOWNTO 0);
clk_count := 0;
state <= send;
ELSE
busy <= '0';
rs <= '0';
rw <= '0';
lcd_data <= "00000000";
clk_count := 0;
state <= ready;
END IF;
--send instruction to lcd
WHEN send =>
busy <= '1';
IF(clk_count < (50 * freq)) THEN --do not exit for 50us
busy <= '1';
IF(clk_count < freq) THEN --negative enable
e <= '0';
ELSIF(clk_count < (14 * freq)) THEN --positive enable half-cycle
e <= '1';
ELSIF(clk_count < (27 * freq)) THEN --negative enable half-cycle
e <= '0';
END IF;
clk_count := clk_count + 1;
state <= send;
ELSE
clk_count := 0;
state <= ready;
END IF;
END CASE;
--reset
IF(reset_n = '0') THEN
state <= power_up;
END IF;
END IF;
END PROCESS;
END controller;
| gpl-3.0 | 4ce742a38ef7d4ca5b1129bc893424f7 | 0.51435 | 4.120308 | false | false | false | false |
endlos99/finalgrom99 | vhdl/src/basic.vhdl | 1 | 10,479 | -- FinalGROM 99
-- A cartridge for the TI 99 that allows for running ROM and GROM images
-- stored on an SD card
--
-- Copyright (c) 2017 Ralph Benzinger <r@0x01.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic is
Port ( -- TI99 bus connections
ROMS : in std_logic;
WE : in std_logic;
GS : in std_logic;
DBIN : in std_logic;
GC : in std_logic;
GR : out std_logic := 'Z';
BUS_DX : inout std_logic_vector(7 downto 0) := (others => 'Z');
BUS_AX : in std_logic_vector(12 downto 0);
-- RAM connections
RAM_DX : inout std_logic_vector(7 downto 0) := (others => 'Z');
RAM_AX : out std_logic_vector(19 downto 0); -- 1 MB
RAM_OE : out std_logic := '1';
RAM_WE : out std_logic := '1';
-- µC control connections
CCMD : in std_logic_vector(2 downto 0); -- actions
CCLK : in std_logic; -- load clock
CDX : inout std_logic_vector(7 downto 0) := (others => 'Z'); -- byte transfered
CX : inout std_logic -- ROM Write Enable (in) and Select Clock (out)
);
end logic;
-- Technical Data:
-- 128 banks of 8 KB
-- 5 usable GROMs
-- GROMs occupy banks 123-127, banks 120-122 reserved
-- Actions (CCMD2-CCDMD1-CCMD0):
-- 0-- RUN run normally, with active selection
-- 100 LOAD SETSIZE set ROM/GROM start address and mask
-- 101 LOAD SETCONF activate RAM or/and GRAM mode
-- 110 LOAD RDUMP dump current image
-- 111 LOAD RLOAD load new image
-- Set Size
-- 0xxxxxxx Set binary ROM bank mask
-- 10-xxxxx Set unary GROM mask
-- 11------ Reset GROM SRAM address
-- Configuration:
-- conf 0 RAM mode
-- conf 1 GRAM mode
architecture Behavioral of logic is
-- GROM Ready state
type grstate_t is (GR0, GRZ);
signal grstate : grstate_t;
-- current operation
type action_t is (RUN, LOAD);
signal action : action_t := LOAD; -- cart offline
type subaction_t is (RLOAD, RDUMP, SETSIZE, SETCONF);
signal subaction : subaction_t := RLOAD;
-- state change
signal ocmd2 : std_logic := '1'; -- LOAD
signal ocmd1 : std_logic := '1'; -- RLOAD
signal ocmd0 : std_logic := '1';
signal conf : std_logic_vector(1 downto 0) := (others => '0'); -- all inactive
-- GROM signals
signal grom : std_logic_vector(2 downto 0) := (others => '0'); -- 8 GROMs
signal gromAddr : std_logic_vector(12 downto 0); -- 6K/8K
signal gromMask : std_logic_vector(4 downto 0) := (others => '0'); -- 5 usable GROMs
signal gromSel : std_logic := '0';
signal delay : std_logic;
-- ROM signals
signal bank : std_logic_vector(6 downto 0); -- 128 banks
signal bankRam : std_logic_vector(6 downto 0); -- RAM banks
signal bankMask : std_logic_vector(6 downto 0); -- mask >00..>7F
-- image selection signals
signal selection : std_logic_vector(8 downto 0); -- clock & byte
signal romWrite : std_logic := '1';
-- address counters
signal loadAddr : std_logic_vector(19 downto 0); -- 1 MB
signal ramAddr : std_logic_vector(19 downto 0); -- (4 & 3) & 13
begin
-- data bus output
BUS_DX <= -- ROM read
RAM_DX when action = RUN and ROMS = '0' and DBIN = '1' else
-- GROM read
RAM_DX when action = RUN and GS = '0' and DBIN = '1' and
BUS_AX(1) = '0' and gromSel = '1' else -- remove BAX?
-- no read, don't touch data bus
(others => 'Z');
-- SRAM address
RAM_AX <= -- load address when loading/dumping ROM
loadAddr when action = LOAD else
-- current SRAM address for bus access
ramAddr;
ramAddr <= -- read from GROM == upper banks
"1111" & grom & gromAddr when GS = '0' else
-- read from RAM (if enabled)
bankRam & BUS_AX when conf(0) = '1' and BUS_AX(12) = '1' else -- RAM bank
-- read from ROM
bank & BUS_AX;
-- SRAM data
RAM_DX <= -- write external data when loading ROM
CDX when action = LOAD and subaction = RLOAD else
-- write bus data when writing to RAM bank
BUS_DX when action = RUN and WE = '0' else
-- otherwise read from SRAM
(others => 'Z');
-- read SRAM
RAM_OE <= -- disable SRAM output when loading image
'1' when action = LOAD and subaction = RLOAD else
-- disable SRAM output when updating RAM bank
'1' when action = RUN and WE = '0' else
-- else always output
'0';
-- write RAM
RAM_WE <= -- enable SRAM write when loading image
CX when action = LOAD and subaction = RLOAD and CCLK = '0' else -- CCLK for stability
-- enable SRAM write when updating RAM bank
'0' when action = RUN and ROMS = '0' and WE = '0'
and conf(0) = '1' and BUS_AX(12) = '1' else
-- enable GRAM write for all GROMs
'0' when action = RUN and GS = '0' and WE = '0'
and conf(1) = '1' and BUS_AX(1) = '0' else
-- else never write
'1';
-- data transfer to uC
CDX <= selection(7 downto 0) when action = RUN else -- image selection
RAM_DX when action = LOAD and subaction = RDUMP else -- dump image
(others => 'Z');
romWrite <= '0' when ROMS = '0' and WE = '0' else '1';
-- clock transfer to uC
CX <= selection(8) when action = RUN else
'Z';
-- GROM Ready logic
with grstate select
GR <= '0' when GR0,
'Z' when others;
-- GROM Ready state machine
PGRDY: process(GC, GS)
begin
if GS = '1' then
grstate <= GR0; -- no read -> not ready
elsif rising_edge(GC) then
case grstate is
when GR0 => grstate <= GRZ; -- wait at least one GROM clock ...
when GRZ => grstate <= GRZ; -- ... before being ready
end case;
end if;
end process;
-- GROM logic
PGROM: process(GS, action, subaction, CDX)
variable newGrom : std_logic_vector(2 downto 0);
begin
if action = LOAD and subaction = SETSIZE and CDX(7 downto 6) = "10" then
-- GSET command w/RESET
grom <= (others => '0');
gromAddr <= (others => '0');
gromSel <= '0';
elsif falling_edge(GS) then -- observe GROM addrs even when loading/dumping
if DBIN = '0' and BUS_AX(1) = '1' then
-- set GROM address
newGrom := gromAddr(7 downto 5);
grom <= newGrom;
gromAddr <= gromAddr(4 downto 0) & BUS_DX;
case newGrom is -- check if GROM is loaded
when "011" => gromSel <= gromMask(0); -- GROMs 3-7
when "100" => gromSel <= gromMask(1);
when "101" => gromSel <= gromMask(2);
when "110" => gromSel <= gromMask(3);
when "111" => gromSel <= gromMask(4);
when others => gromSel <= '0'; -- no GROMs 0-2
end case;
delay <= '0'; -- do not increment addr on first read
elsif BUS_AX(1) = '0' then
-- auto-increment GROM addr
gromAddr <= gromAddr + delay;
delay <= '1'; -- enable GROM auto increment after first read
end if;
end if;
end process;
-- bank switch logic
PBANK: process(WE, action, subaction)
begin
if action = LOAD and subaction = SETSIZE then
-- SET command (GSET precedes RSET)
bank <= (others => '0');
bankRam <= (others => '0');
elsif rising_edge(WE) then
if ROMS = '0' and BUS_AX(0) = '1' then -- fetch from first byte
-- could add action = RUN, but who writes to ROM while loading?
-- select bank
if conf(0) = '1' and BUS_AX(12 downto 11) = "01" then
-- switch RAM bank (needs to be enabled)
bankRam <= BUS_AX(7 downto 1) and bankMask;
elsif conf(0) = '0' or BUS_AX(12) = '0' then
-- switch ROM bank
bank <= BUS_AX(7 downto 1) and bankMask;
end if;
end if;
end if;
end process;
-- image selection
PSELC: process(action, romWrite, BUS_AX)
begin
if action = RUN and falling_edge(romWrite) then
-- select image
selection <= BUS_AX(12) & BUS_AX(8 downto 1);
end if;
end process;
-- image load and dump address logic
PLOAD: process(CCLK)
begin
if rising_edge(CCLK) then
if action = LOAD and subaction = SETSIZE then
-- set where to load
if CDX(7) = '0' then
-- load in ROM
loadAddr <= (others => '0');
bankMask <= CDX(6 downto 0); -- valid bank switches
else
-- load in GROM
loadAddr <= "1111011" & (BUS_AX'range => '0'); -- start at GROM 3
gromMask <= CDX(4 downto 0); -- valid GROMs
end if;
else
-- load each byte sequentially
loadAddr <= loadAddr + 1;
end if;
end if;
end process;
-- mode lock to filter out glitches in control lines
-- NOTE: it may take up to almost 3 GC cycles => 3 * 2,24 us < 7 us
-- a CPU cycle takes 1/3 us => 7 us = 21 CPU cycles
PMODE: process(GC)
begin
if rising_edge(GC) then
ocmd2 <= CCMD(2); -- action RUN or LOAD
ocmd1 <= CCMD(1); -- subaction
ocmd0 <= CCMD(0);
if ocmd2 = CCMD(2) and ocmd1 = CCMD(1) and ocmd0 = CCMD(0) then
if ocmd2 = '0' then
action <= RUN;
else
action <= LOAD;
end if;
if ocmd1 = '0' then
if ocmd0 = '0' then
subaction <= SETSIZE;
else
subaction <= SETCONF;
conf <= CDX(1 downto 0);
end if;
else
if ocmd0 = '0' then
subaction <= RDUMP;
else
subaction <= RLOAD;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 1a4773a48205d91a25aa4dad53a571ea | 0.568525 | 3.648329 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/sim/RAT_Mux4x1_10_0_0.vhd | 2 | 3,394 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
| mit | 804d9dd06d20b15d51d3e41994489ea4 | 0.713318 | 3.762749 | false | false | false | false |
cedd70/PID-ON-FPGA | PID_V3_1.vhd | 1 | 4,224 | --#######################################
--# Correcteur PID V.3.1 #
--#######################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_signed.all;
entity PID_V3_1 is
generic
(
------------ Coefficient ------------
Kp : integer range 0 to 255:=1;
Ki : integer range 0 to 255:=1;
Kd : integer range 0 to 255:=1
);
port
(
------------ Input ------------
clock,
reset : in std_logic;
difference_in : in std_logic_vector(31 downto 0 );
------------ Output ------------
consigne_end : out std_logic:='0';
commande_out : out std_logic_vector(31 downto 0 )
);
end entity;
architecture arch_PID of PID_V3_1 is
------------ accuracy ------------
constant accuracy : integer :=4;
------------ clipping_threshold and Saturation Value ------------
constant clipping_threshold : integer := 500;
constant value_saturation : integer := 500;
------------ output commande ------------
signal commande_buffer : integer range -2147483647 to 2147483647:=0;
signal commande : integer range -2147483647 to 2147483647:=0;
------------ difference between feedback and commande (PID) ------------
signal difference : integer range -2147483647 to 2147483647:=0;
signal cpt_integrator : integer range -2147483647 to 2147483647:=0;
signal previous_difference : integer range -2147483647 to 2147483647:=0;
------------ Signal temp ------------
signal temp_P : integer range -2147483647 to 2147483647:=0;
signal temp_I : integer range -2147483647 to 2147483647:=0;
signal temp_D : integer range -2147483647 to 2147483647:=0;
signal i : integer range 0 to 5 :=0;
begin
----------------------------------------------------------------------------------
computation : process(clock,reset)
begin
if rising_edge(clock) then
if reset = '0' then
commande <= 0;
else
--loi de commande PID ( Pipe)
for i in 0 to 1 loop
case i is
when 0 =>
temp_P <= (difference * Kp);
temp_I <= (cpt_integrator * Ki);
temp_D <= (difference - difference_previous) * Kd);
when 1 =>
commande_buffer <= temp_P + temp_I +temp_D;
when others => null;
end case;
end loop;
end if;
end if;
end process;
----------------------------------------------------------------------------------
integrate : process(clock,reset)
begin
if reset = '0' then
cpt_integrator <=0;
elseif rising_edge(clock) then
if(difference < accuracy and difference > - accuracy) then
cpt_integrator <= 0;
else
cpt_integrator <= cpt_integrator + difference;
end if;
end if;
end process;
----------------------------------------------------------------------------------
derivative: process(clock,reset)
begin
if reset = '0' then
previous_difference <= 0;
elseif rising_edge(clock) then
previous_difference <= difference;
end if;
end process;
----------------------------------------------------------------------------------
commande_process : process(clock,reset)
variable tempo : integer range 0 to 30000000:=0;
begin
if (reset = '0') then
commande <= 0;
elseif rising_edge(clock) then
------------ stop Tuning ------------
-- if ok for X time good position
if ((difference < accuracy) and (difference > - accuracy)) then
if tempo > 20000000 then
commande <= 0;
consigne_end <= '1';
else
tempo := tempo + 1 ;
end if;
------------ Clipping + ------------
elsif (commande > clipping_threshold) then
commande <= value_saturation;
consigne_end <= '0';
tempo := 0 ;
------------ Clipping - ------------
elsif (commande < - clipping_threshold) then
commande <= - value_saturation;
consigne_end <= '0';
tempo := 0 ;
------------ Tuning ------------
else
commande <= commande_buffer ;
consigne_end <= '0';
tempo := 0 ;
end if;
end if;
end process;
----------------------------------------------------------------------------------
difference <= to_integer(signed(difference_in ));
commande_out <= std_logic_vector(to_signed(commande,commande'length));
end arch_PID;
| mit | 8254ea0424016cc36e6789ae4d1af688 | 0.520597 | 3.57663 | false | false | false | false |
stefanct/aua | hw/caches/src/cache_direct.vhd | 1 | 6,609 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- used for address width calculation
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.aua_types.all;
--~ entity instr_cache is
--~ port (
--~ clk : in std_logic;
--~ reset : in std_logic;
--~
--~ -- cache/if
--~ id_instr_addr : in word_t;
--~ id_instr_valid : out std_logic;
--~ id_instr : out word_t;
--~ -- cache/mmu
--~ mmu_instr_addr : out word_t;
--~ mmu_enable : out std_logic;
--~ mmu_instr_valid : in std_logic;
--~ mmu_instr : in word_t
--~ );
--~ end instr_cache;
-- a direct mapped instruction cache for AUA
architecture cache_direct of instr_cache is
constant WORDS_PER_LINE : positive := 1;
constant NUMBER_OF_LINES : positive := 16;
--~ constant LINE_SIZE : positive := WORDS_PER_LINE * WORD_SIZE;
constant WORD_BITS : natural := reqbitsZ_for_choices(WORDS_PER_LINE); -- 0
--~ subtype word_index_r is natural range WORD_BITS downto 1; -- 2 downto 1, word aligned addresses only
constant LINE_BITS : positive := reqbits_for_choices(NUMBER_OF_LINES); -- 5
--~ subtype line_index_r is natural range LINE_BITS downto WORD_BITS+1; -- 7 downto 3
constant TAG_BITS : positive := WORD_SIZE-LINE_BITS-WORD_BITS-1; -- 16-5-2-1=8
subtype tag_r is natural range WORD_SIZE-1 downto WORD_SIZE-TAG_BITS; -- 15 downto 8
type line_t is array (natural range 0 to WORDS_PER_LINE-1) of word_t;
subtype tag_t is std_logic_vector(tag_r);
constant VEC_BITS : natural := TAG_BITS + 1 + WORDS_PER_LINE * WORD_SIZE;
type entry_t is record
tag : tag_t;
valid : boolean;
data : line_t;
end record;
type store_array_t is array(natural range 0 to NUMBER_OF_LINES-1) of entry_t;
function clear_entry return entry_t is
variable ret_e : entry_t;
begin
ret_e.tag := (others => '0');
ret_e.valid := false;
for j in ret_e.data'range loop
ret_e.data(j) := (others => '0');
end loop;
return ret_e;
end function;
function clear_array return store_array_t is
variable return_array : store_array_t;
begin
for i in return_array'range loop
return_array(i) := clear_entry;
end loop;
return return_array;
end function;
function get_word_idx (constant ADDR : word_t) return integer is
begin
if WORD_BITS = 0 then
return 0;
else
return to_integer(unsigned(ADDR(WORD_BITS downto 1)));
end if;
end function;
function get_line_idx (constant ADDR : word_t) return integer is
variable ret : integer;
begin
--~ if WORD_BITS = 0 then
--~ return to_integer(unsigned(ADDR(LINE_BITS downto WORD_BITS+1)));
--~ else
return to_integer(unsigned(ADDR(WORD_BITS+LINE_BITS downto WORD_BITS+1)));
end function;
-- encodes a cache entry (record) into a std_logic_vector
function entry2slv (constant E: in entry_t) return std_logic_vector is
constant WORD_CNT : natural := E.data'length;
constant TAG_SIZE : natural := E.tag'length;
constant WORD_SIZE : natural := E.data(0)'length;
constant VEC_BITS : natural := TAG_SIZE + 1 + WORD_CNT * WORD_SIZE;
variable ret_vec : std_logic_vector(VEC_BITS-1 downto 0);
variable vec_off : integer;
begin
ret_vec(VEC_BITS-1 downto VEC_BITS-TAG_SIZE) := E.tag;
ret_vec(VEC_BITS-TAG_SIZE-1) := bool2sl(E.valid);
vec_off := VEC_BITS-TAG_SIZE-2;
for i in E.data'range loop
ret_vec(vec_off downto vec_off-WORD_SIZE+1) := E.data(i);
vec_off := vec_off-WORD_SIZE;
end loop;
return ret_vec;
end function;
-- decodes the fields of a cache entry from a std_logic_vector
function slv2entry (constant V: in std_logic_vector) return entry_t is
variable ret_e : entry_t;
variable vec_off : integer;
begin
ret_e.tag := V(VEC_BITS-1 downto VEC_BITS-TAG_BITS);
ret_e.valid := sl2bool(V(VEC_BITS-TAG_BITS-1));
vec_off := VEC_BITS-TAG_BITS-2;
for i in 0 to WORDS_PER_LINE-1 loop
ret_e.data(i) := V(vec_off downto vec_off-WORD_SIZE+1);
vec_off := vec_off-WORD_SIZE;
end loop;
return ret_e;
end function;
--~ constant init_store : store_array_t := array_constructor;
signal store : store_array_t;
signal store_nxt : store_array_t;
signal in_cache : boolean;
signal cur_line : natural range 0 to NUMBER_OF_LINES-1;
signal cur_word : natural range 0 to WORDS_PER_LINE-1;
--~ signal test : std_logic_vector(VEC_BITS-1 downto 0);
--~ signal testr : entry_t;
begin
mmu_enable <= not bool2sl(in_cache);
mmu_instr_addr <= id_instr_addr;
in_cache <= store(cur_line).valid and (store(cur_line).tag = id_instr_addr(tag_r));
id_instr_valid <= '1' when in_cache else mmu_instr_valid;
cur_line <= get_line_idx(id_instr_addr);
cur_word <= get_word_idx(id_instr_addr);
--~ test <= entry2slv(store(0));
--~ testr <= slv2entry(test);
--~ id_instr <= store(cur_line).data(0) when in_cache='1' else mmu_instr;
mux_res: process (reset, in_cache, store, cur_line, cur_word, id_instr_addr, mmu_instr)
begin
if reset = '1' then
report "WORD_BITS="&integer'image(WORD_BITS)&", LINE_BITS="&integer'image(LINE_BITS)&", TAG_BITS="&integer'image(TAG_BITS);
id_instr <= (others => '0');
else
if in_cache then
id_instr <= store(cur_line).data(cur_word);
else
id_instr <= mmu_instr;
end if;
end if;
end process;
cache_update: process (reset, store, cur_line, cur_word, in_cache, id_instr_addr, mmu_instr, mmu_instr_valid)
begin
if reset = '1' then
--~ for i in store_nxt'range loop
--~ store_nxt(i).tag <= (others => '0');
--~ store_nxt(i).valid <= false;
--~ for j in store_nxt(i).data'range loop
--~ store_nxt(i).data(j) <= (others => '0');
--~ end loop;
--~ end loop;
store_nxt <= clear_array;
else
store_nxt <= store;
if mmu_instr_valid = '1' then
store_nxt(cur_line).data(cur_word) <= mmu_instr;
--~ store_nxt(cur_line).data(1) <= mmu_instr(7 downto 0)&mmu_instr(15 downto 8);
--~ store_nxt(cur_line).data(3) <= x"0123";
store_nxt(cur_line).valid <= true;
store_nxt(cur_line).tag <= id_instr_addr(tag_r);
end if;
end if;
end process;
sync: process (clk, reset)
begin
if reset = '1' then
--~ for i in store'range loop
--~ store(i).tag <= (others => '0');
--~ store(i).valid <= false;
--~ for j in store(i).data'range loop
--~ store(i).data(j) <= (others => '0');
--~ end loop;
--~ end loop;
store <= clear_array;
elsif rising_edge(clk) then
--~ for i in store'range loop
--~ store(i).tag <= store_nxt(i).tag;
--~ store(i).valid <= store_nxt(i).valid;
--~ for j in store(i).data'range loop
--~ store(i).data(j) <= store_nxt(i).data(j);
--~ end loop;
--~ end loop;
store <= store_nxt;
end if;
end process;
end cache_direct;
| gpl-3.0 | f776d91545522e64ab5c6a98c390f796 | 0.648964 | 2.768747 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_7_0_0/sim/RAT_slice_7_0_0.vhd | 2 | 3,205 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_7_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_7_0_0;
ARCHITECTURE RAT_slice_7_0_0_arch OF RAT_slice_7_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_7_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 12,
DIN_TO => 8
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_7_0_0_arch;
| mit | 4becb2df3ad9e77d1b46d683417d11e1 | 0.721373 | 4.046717 | false | false | false | false |
marcoep/MusicBoxNano | hdl/MusicBoxNano.vhd | 1 | 4,720 | -------------------------------------------------------------------------------
-- Title : Music Box Nano
-- Project :
-------------------------------------------------------------------------------
-- File : MusicBoxNano.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-28
-- Last update: 2016-08-01
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top-Level for the MusicBoxNano Project
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-28 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MusicBoxNano is
port (
CLOCK_50 : in std_logic;
Button_DI : in std_logic_vector(1 downto 0);
Led_DO : out std_logic_vector(7 downto 0);
PWMOut_DO : out std_logic);
end entity MusicBoxNano;
architecture RTL of MusicBoxNano is
-- global signals
signal ClkSys_C : std_logic := '0';
signal ResetSys_S : std_logic := '0';
signal ClkPWM_C : std_logic := '0';
signal ResetPWM_S : std_logic := '0';
-- frequency and key ticks
signal FreqTick_S : std_logic := '0';
signal KeyTick_S : std_logic := '0';
-- note data from Song ROM
signal KeyData_D : std_logic_vector(6 downto 0) := (others => '0');
signal KeyValid_S : std_logic := '0';
-- key to freq increment
signal FreqIncrement_D : std_logic_vector(28 downto 0) := (others => '0');
signal KeyValidShim_S : std_logic := '0';
signal FreqIncrValid_S : std_logic := '0';
-- dds to pwm
signal Waveform_D : std_logic_vector(9 downto 0) := (others => '0');
begin -- architecture RTL
-----------------------------------------------------------------------------
-- Clocking and Reset Resources
-----------------------------------------------------------------------------
MusicBoxClocking_i : entity work.MusicBoxClocking
port map (
CLOCK_50 => CLOCK_50,
RESET_RI => not(Button_DI(0)),
ClkSystem_CO => ClkSys_C,
ClkPWM_CO => ClkPWM_C,
ResetSystem_SO => ResetSys_S,
ResetPWM_SO => ResetPWM_S,
FreqInt_SO => FreqTick_S,
KeyInt_SO => KeyTick_S);
-----------------------------------------------------------------------------
-- Song ROM
-----------------------------------------------------------------------------
SongDB_i : entity work.SongDB
port map (
Clk_CI => ClkSys_C,
Reset_SI => ResetSys_S,
KeyTick_SI => KeyTick_S,
NewKeyData_DO => KeyData_D,
NewKeyValid_SO => KeyValid_S);
-- output LEDs
Led_DO <= '0' & KeyData_D;
-----------------------------------------------------------------------------
-- Key to Frequency Mapping
-----------------------------------------------------------------------------
-- latency 2
KeyToFreqROM_i : entity work.KeyToFreqROM
port map (
address => KeyData_D,
clock => ClkSys_C,
q => FreqIncrement_D);
shim_valid : process (ClkSys_C) is
begin -- process shim_valid
if ClkSys_C'event and ClkSys_C = '1' then -- rising clock edge
if ResetSys_S = '1' then -- synchronous reset (active high)
KeyValidShim_S <= '0';
FreqIncrValid_S <= '0';
else
KeyValidShim_S <= KeyValid_S;
FreqIncrValid_S <= KeyValidShim_S;
end if;
end if;
end process shim_valid;
-----------------------------------------------------------------------------
-- DDS and Envelope
-----------------------------------------------------------------------------
MusicBoxDDS_i : entity work.MusicBoxDDS
port map (
Clk_CI => ClkSys_C,
Reset_SI => ResetSys_S,
FreqTick_SI => FreqTick_S,
FreqIncrement_D => FreqIncrement_D,
FreqIncrValid_SI => FreqIncrValid_S,
Waveform_DO => Waveform_D);
-----------------------------------------------------------------------------
-- PWM Generator
-----------------------------------------------------------------------------
PWMGenerator_i : entity work.PWMGenerator
port map (
Clk_CI => ClkPWM_C,
Reset_SI => ResetPWM_S,
DutyCycle_DI => Waveform_D,
PulseOut_DO => PWMOut_DO);
end architecture RTL;
| gpl-3.0 | 9594030af4809ed255eb59bc4c200a61 | 0.422881 | 4.407096 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd | 5 | 9,340 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
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`protect end_protected
| mit | ae54e85d8fd66773e4ab66f7ea3eb7b8 | 0.919058 | 1.931748 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/cic_compiler_v4_0/hdl/cic_compiler_v4_0.vhd | 4 | 15,391 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9264)
`protect data_block
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VBUSsuG6HBipk3e8ennfiVGK2R5NDNTmsOT1B7GKqEietIGCsiYm+MmCd4zF6TK4p+yn18oRX8rO
z4CX74zcbeYbbwfPI31DE0DP4bfaaBgYRjY20GmrStb8DM/kmtrWnqAGkB5RShAtE9BAteKwATrf
JC2Lm/wMlv68EenU2vG17OAbM95dXzPPTNUtbBXdxcs5ekILCuz/V89kxWDXI/Z5fD0CzR1jY19F
Rzawuztp4745HkjpuEzXki25Lw7evm4rzxXY85HgrqfclbBz5kxG+Bv82i16TDlCkdW6hqqM7R6y
LW+7oajCd20aq2g/5pGpZdPVEwA1m0St1FpJqogPyVbfB0woE4rA9eIamOWUYmhHODIUktgEy35g
j9BqGA+8KDUgI9aliVxeA15TKKJuw8gtm9ACOM21OamCjRpexN4OVedmVrfQ9D4BOBEcLfBiSu07
NSGkOgQOj8LS7DpgWqs36NesM/qQIAIcibfB/mAbxxGjzBY+X544JHk10Ta1+D24P2WAV03nCxAT
Qw4Usqury5vhqvZb5n74xKoWFXNbpCxwFiJ3nFVv5QzO890+LIcUVLRwberC6VQF3k+K5kh+3KSA
LBoVwzDInm/JDUiy1f/Lz6TyAiGUxbKxx4t2zDik286kJmr8TARl18suNWilFKpRdBRpfxGaj0bX
9tuI2OpS8RDC/skcdtWo5GlLxlJyBdKfiu601BAiasVgYCdZwF+LG7sH1ANwmSWxflLgir6j+IkR
8AYREGExmbTOfRulP+i9eqtCGq/w5ol4Vk4kgTyR
`protect end_protected
| mit | b5425fa1bcc0f41d7b99f5e95d6d7aa7 | 0.934247 | 1.902707 | false | false | false | false |
qynvi/rtl-adders | sadder.vhd | 1 | 571 | -- William Fan
-- 2/19/2011
-- Generic Signed Adder RTL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Adder is
port (a,b: in std_logic_vector(7 downto 0);
sum: out std_logic_vector(7 downto 0);
co: out std_logic);
end Adder;
architecture sAdder of Adder is
signal a_sig,b_sig,sum_sig: signed(8 downto 0);
signal carry_out: unsigned(0 downto 0);
begin
a_sig <= signed("0" & a);
b_sig <= signed("0" & b);
sum_sig <= a_sig + b_sig;
sum <= std_logic_vector(sum_sig(7 downto 0));
co <= std_logic(sum_sig(8));
end sAdder;
| mit | b8762e814bca47f86eef53598f2a6707 | 0.654991 | 2.643519 | false | false | false | false |
marcoep/MusicBoxNano | ip/KeyToFreqROM.vhd | 1 | 5,848 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: KeyToFreqROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY KeyToFreqROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (28 DOWNTO 0)
);
END KeyToFreqROM;
ARCHITECTURE SYN OF keytofreqrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (28 DOWNTO 0);
BEGIN
q <= sub_wire0(28 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 29,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "29"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "29"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 29 0 OUTPUT NODEFVAL "q[28..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 29 0 @q_a 0 0 29 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | eea368efb9960a2ad97915832ed6eaf9 | 0.678694 | 3.785113 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.vhdl | 1 | 27,758 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:10 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.vhdl
-- Design : RAT_ControlUnit_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ControlUnit_0_0_ControlUnit is
port (
I_FLAG_CLR : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
PC_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
PC_INC : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
IO_OE : out STD_LOGIC;
ALU_OPY_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
Z_FLAG_LD : out STD_LOGIC;
SP_RESET : out STD_LOGIC;
\OPCODE_HI_5_4__s_port_]\ : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\OPCODE_HI_5_0__s_port_\ : in STD_LOGIC;
\OPCODE_HI_5_2__s_port_\ : in STD_LOGIC;
\OPCODE_LO_2[1]\ : in STD_LOGIC;
\OPCODE_HI_5[4]_0\ : in STD_LOGIC;
\OPCODE_HI_5[4]_1\ : in STD_LOGIC;
\OPCODE_HI_5[4]_2\ : in STD_LOGIC;
\OPCODE_HI_5[4]_3\ : in STD_LOGIC;
\OPCODE_LO_2[1]_0\ : in STD_LOGIC;
\OPCODE_HI_5[4]_4\ : in STD_LOGIC;
\OPCODE_HI_5[4]_5\ : in STD_LOGIC;
INT : in STD_LOGIC;
\OPCODE_HI_5[0]_0\ : in STD_LOGIC;
\OPCODE_HI_5[4]_6\ : in STD_LOGIC;
\OPCODE_HI_5[4]_7\ : in STD_LOGIC;
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
\OPCODE_LO_2[1]_1\ : in STD_LOGIC;
\OPCODE_HI_5[0]_1\ : in STD_LOGIC;
\OPCODE_HI_5[2]_0\ : in STD_LOGIC;
\OPCODE_HI_5[0]_2\ : in STD_LOGIC;
\OPCODE_HI_5[2]_1\ : in STD_LOGIC;
\OPCODE_HI_5[2]_2\ : in STD_LOGIC;
\OPCODE_HI_5[2]_3\ : in STD_LOGIC;
\OPCODE_HI_5[2]_4\ : in STD_LOGIC;
\OPCODE_LO_2_0__s_port_\ : in STD_LOGIC;
\OPCODE_HI_5[0]_3\ : in STD_LOGIC;
\OPCODE_HI_5[4]_8\ : in STD_LOGIC;
\OPCODE_HI_5[4]_9\ : in STD_LOGIC;
\OPCODE_HI_5[2]_5\ : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_ControlUnit_0_0_ControlUnit : entity is "ControlUnit";
end RAT_ControlUnit_0_0_ControlUnit;
architecture STRUCTURE of RAT_ControlUnit_0_0_ControlUnit is
signal \ALU_SEL[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal NS : STD_LOGIC_VECTOR ( 1 to 1 );
signal \OPCODE_HI_5_0__s_net_1\ : STD_LOGIC;
signal \OPCODE_HI_5_2__s_net_1\ : STD_LOGIC;
signal \OPCODE_HI_5_4__s_net_1\ : STD_LOGIC;
signal \OPCODE_LO_2_0__s_net_1\ : STD_LOGIC;
signal PS : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \PS[0]_i_1_n_0\ : STD_LOGIC;
signal RF_WR_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ALU_SEL[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \ALU_SEL[1]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of C_FLAG_CLR_INST_0 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of C_FLAG_SET_INST_0 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of I_FLAG_CLR_INST_0 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of I_FLAG_SET_INST_0 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of PC_INC_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \PC_MUX_SEL[0]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \PS[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \SCR_ADDR_SEL[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \SCR_ADDR_SEL[1]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of SP_INCR_INST_0 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of SP_LD_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of SP_RESET_INST_0 : label is "soft_lutpair4";
begin
\OPCODE_HI_5_0__s_net_1\ <= \OPCODE_HI_5_0__s_port_\;
\OPCODE_HI_5_2__s_net_1\ <= \OPCODE_HI_5_2__s_port_\;
\OPCODE_HI_5_4__s_net_1\ <= \OPCODE_HI_5_4__s_port_]\;
\OPCODE_LO_2_0__s_net_1\ <= \OPCODE_LO_2_0__s_port_\;
ALU_OPY_SEL_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0B000000"
)
port map (
I0 => \OPCODE_HI_5[2]_3\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => OPCODE_HI_5(4),
I4 => PS(1),
O => ALU_OPY_SEL
);
\ALU_SEL[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4F400000"
)
port map (
I0 => PS(0),
I1 => \OPCODE_HI_5[4]_7\,
I2 => OPCODE_HI_5(3),
I3 => \ALU_SEL[0]_INST_0_i_2_n_0\,
I4 => PS(1),
O => ALU_SEL(0)
);
\ALU_SEL[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F00F0201"
)
port map (
I0 => OPCODE_LO_2(0),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(0),
I4 => OPCODE_HI_5(4),
I5 => PS(0),
O => \ALU_SEL[0]_INST_0_i_2_n_0\
);
\ALU_SEL[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5_0__s_net_1\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5_2__s_net_1\,
I4 => PS(1),
O => ALU_SEL(1)
);
\ALU_SEL[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_LO_2[1]_1\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[0]_1\,
I4 => PS(1),
O => ALU_SEL(2)
);
\ALU_SEL[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5[2]_0\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[0]_2\,
I4 => PS(1),
O => ALU_SEL(3)
);
C_FLAG_CLR_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => PS(1),
I1 => \OPCODE_HI_5[4]_5\,
I2 => PS(0),
I3 => OPCODE_HI_5(3),
O => C_FLAG_CLR
);
C_FLAG_LD_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5[2]_4\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_LO_2_0__s_net_1\,
I4 => PS(1),
O => C_FLAG_LD
);
C_FLAG_SET_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => PS(1),
I1 => \OPCODE_HI_5[4]_0\,
I2 => PS(0),
I3 => OPCODE_HI_5(3),
O => C_FLAG_SET
);
IO_OE_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => PS(1),
I1 => OPCODE_HI_5(4),
I2 => \OPCODE_HI_5[2]_2\,
I3 => OPCODE_HI_5(0),
I4 => PS(0),
I5 => OPCODE_HI_5(3),
O => IO_OE
);
I_FLAG_CLR_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"F800"
)
port map (
I0 => \OPCODE_HI_5_4__s_net_1\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => PS(1),
O => I_FLAG_CLR
);
I_FLAG_SET_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => PS(1),
I1 => \OPCODE_HI_5[4]_4\,
I2 => PS(0),
I3 => OPCODE_HI_5(3),
O => I_FLAG_SET
);
PC_INC_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => PC_INC
);
PC_LD_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8FBF800000000"
)
port map (
I0 => \OPCODE_HI_5[4]_3\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_LO_2[1]_0\,
I4 => OPCODE_HI_5(4),
I5 => PS(1),
O => PC_LD
);
\PC_MUX_SEL[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => PS(1),
I1 => \OPCODE_HI_5[4]_3\,
I2 => PS(0),
I3 => OPCODE_HI_5(3),
O => PC_MUX_SEL(0)
);
\PS[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => PS(1),
I1 => PS(0),
O => \PS[0]_i_1_n_0\
);
\PS[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2C"
)
port map (
I0 => INT,
I1 => PS(0),
I2 => PS(1),
O => NS(1)
);
\PS_reg[0]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => '1',
CLR => RST,
D => \PS[0]_i_1_n_0\,
Q => PS(0)
);
\PS_reg[1]\: unisim.vcomponents.FDCE
port map (
C => CLK,
CE => '1',
CLR => RST,
D => NS(1),
Q => PS(1)
);
RF_WR_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"8B880000"
)
port map (
I0 => RF_WR_INST_0_i_1_n_0,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[2]_1\,
I4 => PS(1),
O => RF_WR
);
RF_WR_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000052520111"
)
port map (
I0 => OPCODE_HI_5(2),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(0),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(4),
I5 => PS(0),
O => RF_WR_INST_0_i_1_n_0
);
\RF_WR_SEL[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5[0]_3\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_8\,
I4 => PS(1),
O => RF_WR_SEL(0)
);
\RF_WR_SEL[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => PS(1),
I1 => OPCODE_HI_5(4),
I2 => \OPCODE_HI_5[2]_5\,
I3 => OPCODE_HI_5(0),
I4 => PS(0),
I5 => OPCODE_HI_5(3),
O => RF_WR_SEL(1)
);
\SCR_ADDR_SEL[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBF80000"
)
port map (
I0 => \OPCODE_LO_2[1]\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_0\,
I4 => PS(1),
O => SCR_ADDR_SEL(0)
);
\SCR_ADDR_SEL[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBF80000"
)
port map (
I0 => \OPCODE_HI_5[4]_1\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_0\,
I4 => PS(1),
O => SCR_ADDR_SEL(1)
);
SCR_WR_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5[0]_0\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_6\,
I4 => PS(1),
O => SCR_WR
);
SP_INCR_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => PC_MUX_SEL(1)
);
SP_LD_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"FBF80000"
)
port map (
I0 => \OPCODE_HI_5[4]_2\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_0\,
I4 => PS(1),
O => SP_LD
);
SP_RESET_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => PS(0),
I1 => PS(1),
O => SP_RESET
);
Z_FLAG_LD_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0B080000"
)
port map (
I0 => \OPCODE_HI_5[2]_4\,
I1 => OPCODE_HI_5(3),
I2 => PS(0),
I3 => \OPCODE_HI_5[4]_9\,
I4 => PS(1),
O => Z_FLAG_LD
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_ControlUnit_0_0 is
port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
OPCODE_LO_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SP_LD : out STD_LOGIC;
SP_RESET : out STD_LOGIC;
SP_INCR : out STD_LOGIC;
SP_DECR : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
ALU_SEL : out STD_LOGIC_VECTOR ( 3 downto 0 );
ALU_OPY_SEL : out STD_LOGIC;
SCR_WR : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
SCR_DATA_SEL : out STD_LOGIC;
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_ControlUnit_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_ControlUnit_0_0 : entity is "RAT_ControlUnit_0_0,ControlUnit,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_ControlUnit_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_ControlUnit_0_0 : entity is "ControlUnit,Vivado 2016.4";
end RAT_ControlUnit_0_0;
architecture STRUCTURE of RAT_ControlUnit_0_0 is
signal \<const0>\ : STD_LOGIC;
signal ALU_OPY_SEL_INST_0_i_1_n_0 : STD_LOGIC;
signal \ALU_SEL[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \ALU_SEL[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \ALU_SEL[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \ALU_SEL[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \ALU_SEL[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \ALU_SEL[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \ALU_SEL[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal C_FLAG_CLR_INST_0_i_1_n_0 : STD_LOGIC;
signal C_FLAG_LD_INST_0_i_1_n_0 : STD_LOGIC;
signal C_FLAG_LD_INST_0_i_2_n_0 : STD_LOGIC;
signal IO_OE_INST_0_i_1_n_0 : STD_LOGIC;
signal I_FLAG_CLR_INST_0_i_1_n_0 : STD_LOGIC;
signal I_FLAG_SET_INST_0_i_1_n_0 : STD_LOGIC;
signal PC_LD_INST_0_i_1_n_0 : STD_LOGIC;
signal PC_LD_INST_0_i_2_n_0 : STD_LOGIC;
signal PC_LD_INST_0_i_3_n_0 : STD_LOGIC;
signal PC_LD_INST_0_i_4_n_0 : STD_LOGIC;
signal \^pc_mux_sel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal RF_WR_INST_0_i_2_n_0 : STD_LOGIC;
signal \RF_WR_SEL[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \RF_WR_SEL[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \RF_WR_SEL[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \SCR_ADDR_SEL[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \SCR_ADDR_SEL[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal SCR_WR_INST_0_i_1_n_0 : STD_LOGIC;
signal SCR_WR_INST_0_i_2_n_0 : STD_LOGIC;
signal SP_LD_INST_0_i_1_n_0 : STD_LOGIC;
signal SP_LD_INST_0_i_2_n_0 : STD_LOGIC;
signal \^sp_reset\ : STD_LOGIC;
signal Z_FLAG_LD_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ALU_OPY_SEL_INST_0_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of IO_OE_INST_0_i_1 : label is "soft_lutpair7";
begin
C_FLAG_SEL <= \<const0>\;
PC_MUX_SEL(1 downto 0) <= \^pc_mux_sel\(1 downto 0);
PC_RESET <= \^sp_reset\;
SCR_DATA_SEL <= \<const0>\;
SHAD_C_LD <= \<const0>\;
SHAD_Z_LD <= \<const0>\;
SP_DECR <= \<const0>\;
SP_INCR <= \^pc_mux_sel\(1);
SP_RESET <= \^sp_reset\;
Z_FLAG_CLR <= \<const0>\;
Z_FLAG_SEL <= \<const0>\;
Z_FLAG_SET <= \<const0>\;
ALU_OPY_SEL_INST_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
O => ALU_OPY_SEL_INST_0_i_1_n_0
);
\ALU_SEL[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010101"
)
port map (
I0 => OPCODE_LO_2(0),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(0),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(4),
O => \ALU_SEL[0]_INST_0_i_1_n_0\
);
\ALU_SEL[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A000A000010004"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(0),
O => \ALU_SEL[1]_INST_0_i_1_n_0\
);
\ALU_SEL[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0A0A02C392D28"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_LO_2(1),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(2),
O => \ALU_SEL[1]_INST_0_i_2_n_0\
);
\ALU_SEL[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000883200008826"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_LO_2(0),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_HI_5(2),
I5 => OPCODE_LO_2(1),
O => \ALU_SEL[2]_INST_0_i_1_n_0\
);
\ALU_SEL[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222223232333"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(2),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_HI_5(0),
O => \ALU_SEL[2]_INST_0_i_2_n_0\
);
\ALU_SEL[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AA000155"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(0),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_HI_5(2),
O => \ALU_SEL[3]_INST_0_i_1_n_0\
);
\ALU_SEL[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A000A000040040"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(0),
O => \ALU_SEL[3]_INST_0_i_2_n_0\
);
C_FLAG_CLR_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(4),
O => C_FLAG_CLR_INST_0_i_1_n_0
);
C_FLAG_LD_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000001FF"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(0),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_HI_5(2),
O => C_FLAG_LD_INST_0_i_1_n_0
);
C_FLAG_LD_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AA22AA44AA23AA54"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_LO_2(0),
O => C_FLAG_LD_INST_0_i_2_n_0
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
IO_OE_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => OPCODE_HI_5(1),
I1 => OPCODE_HI_5(2),
O => IO_OE_INST_0_i_1_n_0
);
I_FLAG_CLR_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000002000800"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(1),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(4),
O => I_FLAG_CLR_INST_0_i_1_n_0
);
I_FLAG_SET_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000200"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(1),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(4),
O => I_FLAG_SET_INST_0_i_1_n_0
);
PC_LD_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020200020"
)
port map (
I0 => OPCODE_LO_2(1),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(0),
I5 => OPCODE_HI_5(4),
O => PC_LD_INST_0_i_1_n_0
);
PC_LD_INST_0_i_2: unisim.vcomponents.MUXF7
port map (
I0 => PC_LD_INST_0_i_3_n_0,
I1 => PC_LD_INST_0_i_4_n_0,
O => PC_LD_INST_0_i_2_n_0,
S => OPCODE_HI_5(0)
);
PC_LD_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00006F00"
)
port map (
I0 => Z,
I1 => OPCODE_LO_2(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_HI_5(1),
O => PC_LD_INST_0_i_3_n_0
);
PC_LD_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00000408"
)
port map (
I0 => OPCODE_LO_2(0),
I1 => OPCODE_HI_5(2),
I2 => OPCODE_HI_5(1),
I3 => C,
I4 => OPCODE_LO_2(1),
O => PC_LD_INST_0_i_4_n_0
);
RF_WR_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA2332CDDD"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_LO_2(1),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_HI_5(2),
O => RF_WR_INST_0_i_2_n_0
);
\RF_WR_SEL[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A000E00A000A0"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(0),
O => \RF_WR_SEL[0]_INST_0_i_1_n_0\
);
\RF_WR_SEL[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000100000"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(4),
O => \RF_WR_SEL[0]_INST_0_i_2_n_0\
);
\RF_WR_SEL[1]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => OPCODE_HI_5(1),
I1 => OPCODE_HI_5(2),
O => \RF_WR_SEL[1]_INST_0_i_1_n_0\
);
\SCR_ADDR_SEL[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000EF040000AA00"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_HI_5(0),
I2 => OPCODE_LO_2(0),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_HI_5(1),
I5 => OPCODE_LO_2(1),
O => \SCR_ADDR_SEL[0]_INST_0_i_1_n_0\
);
\SCR_ADDR_SEL[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000021220020"
)
port map (
I0 => OPCODE_LO_2(1),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_LO_2(0),
I4 => OPCODE_HI_5(0),
I5 => OPCODE_HI_5(4),
O => \SCR_ADDR_SEL[1]_INST_0_i_1_n_0\
);
SCR_WR_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A100A000000000"
)
port map (
I0 => OPCODE_HI_5(4),
I1 => OPCODE_LO_2(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(0),
O => SCR_WR_INST_0_i_1_n_0
);
SCR_WR_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001400000"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(1),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_HI_5(2),
I4 => OPCODE_LO_2(0),
I5 => OPCODE_HI_5(4),
O => SCR_WR_INST_0_i_2_n_0
);
SP_LD_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000031021004"
)
port map (
I0 => OPCODE_LO_2(0),
I1 => OPCODE_HI_5(1),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_LO_2(1),
I4 => OPCODE_HI_5(0),
I5 => OPCODE_HI_5(4),
O => SP_LD_INST_0_i_1_n_0
);
SP_LD_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => OPCODE_HI_5(0),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(2),
I3 => OPCODE_HI_5(1),
I4 => OPCODE_LO_2(1),
I5 => OPCODE_HI_5(4),
O => SP_LD_INST_0_i_2_n_0
);
U0: entity work.RAT_ControlUnit_0_0_ControlUnit
port map (
ALU_OPY_SEL => ALU_OPY_SEL,
ALU_SEL(3 downto 0) => ALU_SEL(3 downto 0),
CLK => CLK,
C_FLAG_CLR => C_FLAG_CLR,
C_FLAG_LD => C_FLAG_LD,
C_FLAG_SET => C_FLAG_SET,
INT => INT,
IO_OE => IO_OE,
I_FLAG_CLR => I_FLAG_CLR,
I_FLAG_SET => I_FLAG_SET,
OPCODE_HI_5(4 downto 0) => OPCODE_HI_5(4 downto 0),
\OPCODE_HI_5[0]_0\ => SCR_WR_INST_0_i_1_n_0,
\OPCODE_HI_5[0]_1\ => \ALU_SEL[2]_INST_0_i_2_n_0\,
\OPCODE_HI_5[0]_2\ => \ALU_SEL[3]_INST_0_i_2_n_0\,
\OPCODE_HI_5[0]_3\ => \RF_WR_SEL[0]_INST_0_i_1_n_0\,
\OPCODE_HI_5[2]_0\ => \ALU_SEL[3]_INST_0_i_1_n_0\,
\OPCODE_HI_5[2]_1\ => RF_WR_INST_0_i_2_n_0,
\OPCODE_HI_5[2]_2\ => IO_OE_INST_0_i_1_n_0,
\OPCODE_HI_5[2]_3\ => ALU_OPY_SEL_INST_0_i_1_n_0,
\OPCODE_HI_5[2]_4\ => C_FLAG_LD_INST_0_i_1_n_0,
\OPCODE_HI_5[2]_5\ => \RF_WR_SEL[1]_INST_0_i_1_n_0\,
\OPCODE_HI_5[4]_0\ => SP_LD_INST_0_i_2_n_0,
\OPCODE_HI_5[4]_1\ => \SCR_ADDR_SEL[1]_INST_0_i_1_n_0\,
\OPCODE_HI_5[4]_2\ => SP_LD_INST_0_i_1_n_0,
\OPCODE_HI_5[4]_3\ => PC_LD_INST_0_i_1_n_0,
\OPCODE_HI_5[4]_4\ => I_FLAG_SET_INST_0_i_1_n_0,
\OPCODE_HI_5[4]_5\ => C_FLAG_CLR_INST_0_i_1_n_0,
\OPCODE_HI_5[4]_6\ => SCR_WR_INST_0_i_2_n_0,
\OPCODE_HI_5[4]_7\ => \ALU_SEL[0]_INST_0_i_1_n_0\,
\OPCODE_HI_5[4]_8\ => \RF_WR_SEL[0]_INST_0_i_2_n_0\,
\OPCODE_HI_5[4]_9\ => Z_FLAG_LD_INST_0_i_1_n_0,
\OPCODE_HI_5_0__s_port_\ => \ALU_SEL[1]_INST_0_i_1_n_0\,
\OPCODE_HI_5_2__s_port_\ => \ALU_SEL[1]_INST_0_i_2_n_0\,
\OPCODE_HI_5_4__s_port_]\ => I_FLAG_CLR_INST_0_i_1_n_0,
OPCODE_LO_2(0) => OPCODE_LO_2(0),
\OPCODE_LO_2[1]\ => \SCR_ADDR_SEL[0]_INST_0_i_1_n_0\,
\OPCODE_LO_2[1]_0\ => PC_LD_INST_0_i_2_n_0,
\OPCODE_LO_2[1]_1\ => \ALU_SEL[2]_INST_0_i_1_n_0\,
\OPCODE_LO_2_0__s_port_\ => C_FLAG_LD_INST_0_i_2_n_0,
PC_INC => PC_INC,
PC_LD => PC_LD,
PC_MUX_SEL(1 downto 0) => \^pc_mux_sel\(1 downto 0),
RF_WR => RF_WR,
RF_WR_SEL(1 downto 0) => RF_WR_SEL(1 downto 0),
RST => RST,
SCR_ADDR_SEL(1 downto 0) => SCR_ADDR_SEL(1 downto 0),
SCR_WR => SCR_WR,
SP_LD => SP_LD,
SP_RESET => \^sp_reset\,
Z_FLAG_LD => Z_FLAG_LD
);
Z_FLAG_LD_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF05050515"
)
port map (
I0 => OPCODE_HI_5(2),
I1 => OPCODE_LO_2(0),
I2 => OPCODE_HI_5(1),
I3 => OPCODE_LO_2(1),
I4 => OPCODE_HI_5(0),
I5 => OPCODE_HI_5(4),
O => Z_FLAG_LD_INST_0_i_1_n_0
);
end STRUCTURE;
| mit | 93e79ac3cd62c104e4a652e0a6eb23e1 | 0.516608 | 2.511809 | false | false | false | false |
stefanct/aua | hw/src/aua_pll.vhd | 1 | 15,291 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: aua_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY aua_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END aua_pll;
ARCHITECTURE SYN OF aua_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 7,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=aua_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
areset => areset,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "70.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "aua_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll.ppf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL aua_pll_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | 864d66e8072d83ee6d0238ddd5f04654 | 0.683866 | 3.315481 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Decrementer_0_0/synth/RAT_Decrementer_0_0.vhd | 1 | 3,627 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Decrementer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Decrementer_0_0 IS
PORT (
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Decrementer_0_0;
ARCHITECTURE RAT_Decrementer_0_0_arch OF RAT_Decrementer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Decrementer IS
PORT (
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Decrementer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "Decrementer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Decrementer_0_0_arch : ARCHITECTURE IS "RAT_Decrementer_0_0,Decrementer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Decrementer_0_0_arch: ARCHITECTURE IS "RAT_Decrementer_0_0,Decrementer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Decrementer,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Decrementer
PORT MAP (
I => I,
O => O
);
END RAT_Decrementer_0_0_arch;
| mit | c2872e9f664d76c06edac1684dbda57b | 0.748553 | 4.043478 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/fifo/fifo_ic_assembly_hwtb.vhdl | 1 | 4,088 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench FIFO stream assembly: module fifo_ic_assembly.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo_ic_assembly_hwtb is
generic (
D_BITS : positive := 9; -- Data Width
A_BITS : positive := 9; -- Address Bits
G_BITS : positive := 1 -- Generation Guard Bits
);
port (
clk : in std_logic;
rst : in std_logic;
leds : out std_logic_vector(7 downto 0)
);
end entity fifo_ic_assembly_hwtb;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
architecture rtl of fifo_ic_assembly_hwtb is
constant SEQ : t_intvec := (1, 0, 2, 3, 5, 4, 7, 6, 8, 10, 9, 12, 11, 13, 15, 14);
-- DUT Connectivity
signal base : std_logic_vector(A_BITS-1 downto 0);
signal failed : std_logic;
signal addr : std_logic_vector(A_BITS-1 downto 0);
signal din : std_logic_vector(D_BITS-1 downto 0);
signal put : std_logic;
signal dout : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
signal got : std_logic;
-- Writer State
signal Ptr : unsigned(A_BITS-1 downto 0) := (others => '0');
alias Seg : unsigned(A_BITS-1 downto A_BITS-4) is Ptr(A_BITS-1 downto A_BITS-4);
alias Ofs : unsigned(A_BITS-5 downto 0) is Ptr(A_BITS-5 downto 0);
signal tmp : unsigned(A_BITS-1 downto 0);
-- Reader State
signal Count : unsigned(A_BITS-1 downto 0) := (others => '0');
signal Failure : std_logic_vector(1 downto 0) := "00";
begin
DUT: fifo_ic_assembly
generic map (
D_BITS => D_BITS,
A_BITS => A_BITS,
G_BITS => G_BITS
)
port map (
clk_wr => clk,
rst_wr => rst,
base => base,
failed => failed,
addr => addr,
din => din,
put => put,
clk_rd => clk,
rst_rd => rst,
dout => dout,
vld => vld,
got => got
);
-- Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ptr <= (others => '0');
elsif put = '1' then
Ptr <= Ptr + 1;
end if;
end if;
end process;
addr <= std_logic_vector(to_unsigned(SEQ(to_integer(Seg)), Seg'length) & Ofs);
din <= not addr(D_BITS-1 downto 0);
tmp <= unsigned(addr) - unsigned(base);
put <= '1' when tmp(A_BITS-1 downto A_BITS-G_BITS) = 0 else '0';
-- Reading Checker
got <= '1';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Count <= (others => '0');
Failure <= "00";
elsif vld = '1' then
if Count /= unsigned(not dout) then
Failure(0) <= '1';
end if;
if failed = '1' then
Failure(1) <= '1';
end if;
Count <= Count + 1;
end if;
end if;
end process;
-- Outputs
leds <= Failure & std_logic_vector(base(base'left downto base'left-5));
end rtl;
| apache-2.0 | 49c7b690f149b02be7546341641bf280 | 0.550636 | 3.438183 | false | false | false | false |
marcoep/MusicBoxNano | ip/WaveformROM.vhd | 1 | 5,897 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: WaveformROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY WaveformROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END WaveformROM;
ARCHITECTURE SYN OF waveformrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 12,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../GITROOT/MusicBoxNano/matlab/dds_mif_generator/WaveTable_4096.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveformROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 2f15573ea0e679d67b66d9637d4d7e7c | 0.679328 | 3.777707 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/raphael-frey/axis_multiplexer_v1_0/src/axis_multiplexer.vhd | 3 | 2,442 | ----------------------------------------------------------------------------------
--
-- axis_multiplexer.vhd
--
-- (c) 2017
-- N. Huesser
-- R. Frey
--
----------------------------------------------------------------------------------
--
-- A multiplexer for multiple AXI Streams.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity multiplexer is
generic (
C_AXIS_TDATA_WIDTH: integer := 32;
C_AXIS_NUM_SI_SLOTS: integer := 2
);
port (
ClkxCI: in std_logic;
RstxRBI: in std_logic;
SelectxDI: in std_logic_vector (1 downto 0) := (others => '0');
Data0xDI: in std_logic_vector(C_AXIS_TDATA_WIDTH - 1 downto 0) := (others => '0');
Data1xDI: in std_logic_vector(C_AXIS_TDATA_WIDTH - 1 downto 0) := (others => '0');
Data2xDI: in std_logic_vector(C_AXIS_TDATA_WIDTH - 1 downto 0) := (others => '0');
Data3xDI: in std_logic_vector(C_AXIS_TDATA_WIDTH - 1 downto 0) := (others => '0');
Valid0xSI: in std_logic := '0';
Valid1xSI: in std_logic := '0';
Valid2xSI: in std_logic := '0';
Valid3xSI: in std_logic := '0';
Ready0xSO: out std_logic := '0';
Ready1xSO: out std_logic := '0';
Ready2xSO: out std_logic := '0';
Ready3xSO: out std_logic := '0';
DataxDO: out std_logic_vector(C_AXIS_TDATA_WIDTH - 1 downto 0) := (others => '0');
ValidxSO: out std_logic := '0';
ReadyxSI: in std_logic := '0'
);
end multiplexer;
architecture V1 of multiplexer is
begin
p_converter: process(Data0xDI, Data1xDI, Data2xDI, Data3xDI, Valid0xSI, Valid1xSI, Valid2xSI, Valid3xSI, ReadyxSI ,SelectxDI)
begin
case SelectxDI is
when "00" =>
DataxDO <= Data0xDI;
ValidxSO <= Valid0xSI;
Ready0xSO <= ReadyxSI;
when "01" =>
DataxDO <= Data1xDI;
ValidxSO <= Valid1xSI;
Ready1xSO <= ReadyxSI;
when "10" =>
DataxDO <= Data2xDI;
ValidxSO <= Valid2xSI;
Ready2xSO <= ReadyxSI;
when "11" =>
DataxDO <= Data3xDI;
ValidxSO <= Valid3xSI;
Ready3xSO <= ReadyxSI;
when others =>
DataxDO <= Data0xDI;
ValidxSO <= Valid0xSI;
Ready0xSO <= ReadyxSI;
end case;
end process;
end V1;
| mit | 1e9ca23ab1b5ce3a9ed47f9f0303787f | 0.497952 | 3.768519 | false | false | false | false |
David-Estevez/spaceinvaders | src/edgeDetectorDebounce_tb.vhd | 1 | 2,506 | ----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector debounce testbench
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY edgeDetectorDebounce_tb IS
END edgeDetectorDebounce_tb;
ARCHITECTURE behavior OF edgeDetectorDebounce_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT edgeDetectorDebounce
PORT(
clk : IN std_logic;
reset : IN std_logic;
enable : IN std_logic;
input : IN std_logic;
detected : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal input : std_logic := '0';
--Outputs
signal detected : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: edgeDetectorDebounce PORT MAP (
clk => clk,
reset => reset,
enable => enable,
input => input,
detected => detected
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Reset
reset <= '0', '1' after 100ns;
enable <= '0', '1' after 200ns;
-- Other stimulus
stim_process : process
begin
wait for 15*clk_period;
input <= '1';
wait for 3*clk_period;
input <= '0';
wait for 5*clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '1';
wait for 1ms;
input <= '0';
wait for 5*clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait;
end process;
END;
| gpl-3.0 | a4c9e9a73c4788f8a48b16a422bf13ed | 0.517779 | 3.686303 | false | false | false | false |
BBN-Q/VHDL-Components | src/SinCosLUT.vhd | 1 | 4,139 | -- Simple sin/cos LUT
-- Register input/output to allow usual quarter-wave symmetry
--
-- Original author Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity SinCosLUT is
generic (
PHASE_WIDTH : natural := 14;
OUTPUT_WIDTH : natural := 14
);
port (
clk : in std_logic;
rst : in std_logic;
phase_tdata : in std_logic_vector(PHASE_WIDTH-1 downto 0);
phase_tvalid : in std_logic;
sin_tdata : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
cos_tdata : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
sincos_tvalid : out std_logic
);
end entity;
architecture arch of SinCosLUT is
--0 to pi/2 sin look up table
constant LUT_SIZE : natural := 2**(PHASE_WIDTH-2);
type lut_array is array(LUT_SIZE-1 downto 0) of signed(OUTPUT_WIDTH-1 downto 0);
function fill_lut return lut_array is
variable lut : lut_array;
variable tmp : integer;
constant SCALE : real := real(2**(OUTPUT_WIDTH-1)) - 1.0;
begin
for ct in 0 to LUT_SIZE-1 loop
tmp := integer( SCALE * sin((MATH_PI/2.0)*real(ct)/real(LUT_SIZE)) );
lut(ct) := to_signed(tmp, OUTPUT_WIDTH);
end loop;
return lut;
end function;
--seems this should be constant but then rom_style requires signal
signal lut : lut_array := fill_lut;
attribute rom_style : string;
attribute rom_style of lut : signal is "block";
signal sin_addr, cos_addr : natural range 0 to 2**(PHASE_WIDTH-2)-1;
subtype ADDR_SLICE is natural range PHASE_WIDTH-3 downto 0;
signal sin_tdata_reg, cos_tdata_reg : signed(OUTPUT_WIDTH-1 downto 0);
signal sign_bit : std_logic;
signal ones_complement_addr_bit : std_logic;
signal sin_sign_bit_d : std_logic := '0';
signal cos_sign_bit, cos_sign_bit_d : std_logic := '0';
begin
sign_bit <= phase_tdata(phase_tdata'high);
ones_complement_addr_bit <= phase_tdata(phase_tdata'high - 1);
sin_port : process(clk)
variable lut_data : signed(OUTPUT_WIDTH-1 downto 0);
begin
if rising_edge(clk) then
--register addr with possible ones complement
if ones_complement_addr_bit = '0' then
sin_addr <= to_integer(unsigned(phase_tdata(ADDR_SLICE)));
else
sin_addr <= to_integer(unsigned(not phase_tdata(ADDR_SLICE)));
end if;
--Register output data from BRAM
sin_tdata_reg <= lut_data;
lut_data := lut(sin_addr);
end if;
end process;
sin_sign_bit_delay : entity work.DelayLine
generic map ( DELAY_TAPS => 3)
port map( clk => clk, rst => rst, data_in(0) => sign_bit, data_out(0) => sin_sign_bit_d);
-- should be sin_tdata <= std_logic_vector(sin_tdata_reg) when sin_sign_bit_d = '0' else std_logic_vector(-sin_tdata_reg);
-- instead sign inversion as one's complement
-- could be off by 1 bit but just make OUTPUT_WIDTH wider to compensate
-- TODO: investigate skewing phase and LUT by 1/2 LSB see
sin_tdata <= std_logic_vector(sin_tdata_reg) when sin_sign_bit_d = '0' else not std_logic_vector(sin_tdata_reg);
-- cos(\theta) = sin(\pi/2 - \theta) = sin(\pi/2 + \theta)
-- pi/2 shift just adds 01 to sign/address inversion bits 00 -> 01; 01 -> 10; 10 -> 11; 11 -> 11
-- cos address inversion = not sin address inversion and cos sign inversion = sin sign inversion xor sin address inversion
cos_port : process(clk)
variable lut_data : signed(OUTPUT_WIDTH-1 downto 0);
begin
if rising_edge(clk) then
--register addr with possible ones complement
if ones_complement_addr_bit = '1' then
cos_addr <= to_integer(unsigned(phase_tdata(ADDR_SLICE)));
else
cos_addr <= to_integer(unsigned(not phase_tdata(ADDR_SLICE)));
end if;
--Register output data from BRAM
cos_tdata_reg <= lut_data;
lut_data := lut(cos_addr);
end if;
end process;
--sign inversion as ones complement
cos_sign_bit <= sign_bit xor ones_complement_addr_bit;
cos_sign_bit_delay : entity work.DelayLine
generic map ( DELAY_TAPS => 3)
port map( clk => clk, rst => rst, data_in(0) => cos_sign_bit, data_out(0) => cos_sign_bit_d);
cos_tdata <= std_logic_vector(cos_tdata_reg) when cos_sign_bit_d = '0' else not std_logic_vector(cos_tdata_reg);
end architecture;
| mpl-2.0 | d3ce921855c40df51d4af65f92dfcc8a | 0.686398 | 3.007994 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/OR.vhd | 1 | 718 | ----------------------------------------------------------------------------------
-- Create Date: 21:40:57 04/10/2017
-- Module Name: OR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)); -- Saida
end OR_BitABit;
architecture Behavioral of OR_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) OR B(0);
Zout(1) <= A(1) OR B(1);
Zout(2) <= A(2) OR B(2);
Zout(3) <= A(3) OR B(3);
Z <= Zout;
end Behavioral;
| gpl-3.0 | 0e34d71ea2eb49d3306df0e905944555 | 0.465181 | 3.402844 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/Main.vhd | 1 | 6,290 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY teste IS
PORT (
CLK_50M : IN std_logic; --Clock dado pela Spartan3 em Hz
PS2_CLK1 : IN std_logic; --Sinal de clock interno do teclado
PS2_DATA1 : IN std_logic; --Sinal de dados interno do teclado
seletorSaida: in std_logic; -- Switch utilizado para selecionar operacao a exibir
rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd
lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END teste;
ARCHITECTURE Arcteste OF teste IS
TYPE enviaAscii IS (resultSoma, DoisPontosS, Soma5, Soma4, Soma3, Soma2, Soma1, resultProd, Prod10, Prod9, Prod8, Prod7, Prod6, Prod5, Prod4, Prod3, Prod2, Prod1,
fim);
SIGNAL finishMaquina : std_logic;
SIGNAL entradaA : std_logic_vector(19 DOWNTO 0);
SIGNAL entradaB : std_logic_vector(19 DOWNTO 0);
SIGNAL saidaSomador : std_logic_vector(19 DOWNTO 0);
SIGNAL saidaMultiplicador : std_logic_vector(39 DOWNTO 0);
SIGNAL carryOut : std_logic;
SIGNAL MDDEnable, MDDfinish, MDDreset : std_logic;
SIGNAL reset_lcd, ativa_lcd, lcd_ocupado : std_logic;
SIGNAL receives_input : std_logic;
SIGNAL codigo_lcd : std_logic_vector(9 DOWNTO 0);
SIGNAL entradaA_S : unsigned(19 DOWNTO 0) := unsigned(entradaA);
SIGNAL entradaB_S : unsigned(19 DOWNTO 0) := unsigned(entradaB);
SIGNAL saidaSomador_S : unsigned(19 DOWNTO 0) := (others => '0');
SIGNAL carryOut_S : unsigned(3 DOWNTO 0) := (others => '0');
SIGNAL saidaMultiplicador_S : unsigned(39 DOWNTO 0) := (others => '0');
SIGNAL enviaLCD : enviaAscii := resultSoma;
BEGIN
Controlador_LCD : ENTITY work.lcd_controller
PORT MAP(CLK_50M, reset_lcd, ativa_lcd, codigo_lcd, lcd_ocupado, rw, rs, e, lcd_data);
MaquinaDeEstadosPrincipal : ENTITY work.MaquinaDeEstadosPrincipal
PORT MAP(CLK_50M, PS2_CLK1, PS2_DATA1, entradaA, entradaB, finishMaquina, MDDreset);
Multiplicador : ENTITY work.MultBcd_5x5Dig
PORT MAP(
EntradaA => entradaA_S,
EntradaB => entradaB_S,
saidaZ => saidaMultiplicador_S
);
Somador : ENTITY work.bcd_5_digit_adder
PORT MAP(
Entrada1 => entradaA_S,
Entrada2 => entradaB_S,
sum => saidaSomador_S,
carry => carryOut_S
);
PROCESS (CLK_50M, finishMaquina, MDDfinish, MDDreset)
BEGIN
IF (CLK_50M'EVENT AND CLK_50M = '1') THEN
IF (finishMaquina = '1') THEN
MDDenable <= '1';
ELSE
MDDenable <= '0';
END IF;
IF (MDDfinish = '1') THEN
receives_input <= '1';
ELSE
receives_input <= '0';
END IF;
IF (MDDreset = '1') THEN
reset_lcd <= '0';
enviaLCD <= resultSoma;
ELSE
reset_lcd <= '1';
END IF;
IF (lcd_ocupado = '0' AND ativa_lcd = '0') THEN
IF (seletorSaida = '0') THEN --Exibe soma
CASE (enviaLCD) IS
WHEN resultSoma => -- Exibe S
ativa_lcd <= '1';
codigo_lcd <= "10" & "0101" & "0011";
enviaLCD <= DoisPontosS;
WHEN DoisPontosS => -- Exibe :
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & "1010";
enviaLCD <= Soma5;
WHEN Soma5 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(19 downto 16);
enviaLCD <= Soma4;
WHEN Soma4 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(15 downto 12);
enviaLCD <= Soma3;
WHEN Soma3 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(11 downto 8);
enviaLCD <= Soma2;
WHEN Soma2 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(7 downto 4);
enviaLCD <= Soma1;
WHEN Soma1 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaSomador(3 downto 0);
enviaLCD <= fim;
WHEN fim =>
ativa_lcd <= '0';
WHEN others =>
ativa_lcd <= '0';
END CASE;
ELSE -- Exibe Produto
CASE enviaLCD IS
WHEN resultProd => -- Exibe P
ativa_lcd <= '1';
codigo_lcd <= "10" & "0101" & "0000";
enviaLCD <= DoisPontosS;
WHEN DoisPontosS => -- Exibe :
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & "1010";
enviaLCD <= Prod10;
WHEN Prod10 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(39 downto 36);
enviaLCD <= Prod9;
WHEN Prod9 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(35 downto 32);
enviaLCD <= Prod8;
WHEN Prod8 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(31 downto 28);
enviaLCD <= Prod7;
WHEN Prod7 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(27 downto 24);
enviaLCD <= Prod6;
WHEN Prod6 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(23 downto 20);
enviaLCD <= Prod5;
WHEN Prod5 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(19 downto 16);
enviaLCD <= Prod4;
WHEN Prod4 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(15 downto 12);
enviaLCD <= Prod3;
WHEN Prod3 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(11 downto 8);
enviaLCD <= Prod2;
WHEN Prod2 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(7 downto 4);
enviaLCD <= Prod1;
WHEN Prod1 =>
ativa_lcd <= '1';
codigo_lcd <= "10" & "0011" & saidaMultiplicador(3 downto 0);
enviaLCD <= fim;
WHEN fim =>
ativa_lcd <= '0';
WHEN others =>
ativa_lcd <= '0';
END CASE;
END IF; -- Fim: if(seletorSaida = '0')
ELSE
ativa_lcd <= '0';
END IF; -- Fim: if(lcd_ocupado = '0' AND ativa_lcd = '0')
END IF; -- Fim: if(CLK_50M'event and CLK_50M='1')
END PROCESS;
END Arcteste; | gpl-3.0 | c005e94886d031bd675ebf39e1e967cf | 0.544515 | 3.237262 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_axis_to_data_lanes_0_0/sim/design_1_axis_to_data_lanes_0_0.vhd | 4 | 4,426 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: noah-huesser:user:axis_to_data_lanes:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_to_data_lanes_0_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
AxiTDataxDI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
AxiTValid : IN STD_LOGIC;
AxiTReady : OUT STD_LOGIC;
Data0xDO : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
Data1xDO : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
DataStrobexDO : OUT STD_LOGIC
);
END design_1_axis_to_data_lanes_0_0;
ARCHITECTURE design_1_axis_to_data_lanes_0_0_arch OF design_1_axis_to_data_lanes_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_to_data_lanes_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_to_data_lanes IS
GENERIC (
Decimation : INTEGER;
Offset : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
AxiTDataxDI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
AxiTValid : IN STD_LOGIC;
AxiTReady : OUT STD_LOGIC;
Data0xDO : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
Data1xDO : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
DataStrobexDO : OUT STD_LOGIC
);
END COMPONENT axis_to_data_lanes;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF AxiTDataxDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI TDATA";
ATTRIBUTE X_INTERFACE_INFO OF AxiTValid: SIGNAL IS "xilinx.com:interface:axis:1.0 SI TVALID";
ATTRIBUTE X_INTERFACE_INFO OF AxiTReady: SIGNAL IS "xilinx.com:interface:axis:1.0 SI TREADY";
BEGIN
U0 : axis_to_data_lanes
GENERIC MAP (
Decimation => 1,
Offset => 32768
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
AxiTDataxDI => AxiTDataxDI,
AxiTValid => AxiTValid,
AxiTReady => AxiTReady,
Data0xDO => Data0xDO,
Data1xDO => Data1xDO,
DataStrobexDO => DataStrobexDO
);
END design_1_axis_to_data_lanes_0_0_arch;
| mit | b140b64a5bde356414b8b7028beb7d1b | 0.721193 | 3.896127 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/scratchPad.vhd | 1 | 1,526 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/20/2016 11:29:49 AM
-- Design Name:
-- Module Name: scratchPad - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity scratchPad is
Port ( Scr_Addr : in STD_LOGIC_VECTOR (7 downto 0);
Scr_Oe : in STD_LOGIC;
SCR_WE : in STD_LOGIC;
CLK : in STD_LOGIC;
SCR_DATA : inout STD_LOGIC_VECTOR (9 downto 0));
end scratchPad;
architecture Behavioral of scratchPad is
TYPE memory is array (0 to 255) of std_logic_vector(9 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
begin
process(clk)
begin
if (rising_edge(clk)) then
if (SCR_WE = '1') then
REG(conv_integer(Scr_Addr)) <= SCR_DATA;
end if;
end if;
end process;
SCR_DATA <= REG(conv_integer(Scr_Addr)) when Scr_Oe='1' else (others=>'Z');
end Behavioral;
| mit | 1a76f2bc0b440c4e8025630d322b6611 | 0.583879 | 3.703883 | false | false | false | false |
odeke-em/hdl-class | adders/fullAdderStructural.vhd | 1 | 1,268 | -- This example was provided by:
-- Bruce Cockburn and Jie Han
-- However it was a collaboration between Qiushi Jiang and myself
-- to modify it and fix up changes
library IEEE;
using IEEE.STD_LOGIC_1164.all;
entity NBitAdder is
generic(width: integer := 16);
Port (
A: in STD_LOGIC_VECTOR(width - 1 downto 0);
B: in STD_LOGIC_VECTOR(width - 1 downto 0);
Sum: out STD_LOGIC_VECTOR(width downto 0);
);
end NBitAdder;
architecture Behavioral of NBitAdder is
component fullAdder is
Port(
A: in STD_LOGIC;
B: in STD_LOGIC;
Sum: out STD_LOGIC;
Cout: out STD_LOGIC;
);
end component fullAdder;
signal carries: STD_LOGIC_VECTOR(width downto 0);
begin:
FAs: for i in 0 to width - 1 generate
aFA: fullAdder port map(
A => A(i),
B => B(i),
Cin => carries(i),
Sum => Sum(i);
Cout => carries(i+1)
);
end generate;
carries(0) <= '0';
sum(width) <= carries(width);
end Behavioral;
| mit | 04138f42b09faa5024180c140722e73e | 0.485016 | 4.184818 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/sim/Program_Counter_Counter10bit_0_1.vhd | 2 | 3,592 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Counter10bit:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Counter10bit_0_1 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END Program_Counter_Counter10bit_0_1;
ARCHITECTURE Program_Counter_Counter10bit_0_1_arch OF Program_Counter_Counter10bit_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Counter10bit_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END Program_Counter_Counter10bit_0_1_arch;
| mit | e2fd228b4046f626b7eef71e5bb5886e | 0.726893 | 4 | false | false | false | false |
Subsets and Splits