The present invention is directed to an apparatus for use with a computing device for generating a substitute acknowledgement to a first input signal when the computing device is in an operational hiatus. Specifically, the present invention is directed to an apparatus for generating an artificial hold acknowledge signal in response to a hold request signal on behalf of a computer processing unit when the computer processing unit is disabled or otherwise in an operational hiatus.
Generally, a hold acknowledge signal is required in response to a hold request signal before a computer processing unit will yield access to a data bus. If a computer processing unit is in an operational hiatus, such as responding to a disable signal, or experiencing a clock stoppage, or the like, then the computer processing unit cannot generate a hold acknowledge signal. Despite the fact that the computer processing unit cannot operate and, therefore, has no reason to maintain control of access to a data bus, the fact that no hold acknowledge signal can be issued by the computer processing unit in response to a hold request signal nevertheless precludes access to the data bus by another device.
Accordingly, it is important that there be a means for freeing access to a data bus by generating an artificial hold acknowledge signal during periods of operational hiatus by the computer processing unit. In such manner, monopolization of access to the data bus by a quiescent computer processing unit by default may be precluded.
Such a capability to allow access to a data bus during periods during which a computer processing unit is in operational hiatus is of particular importance where certain functions of the computer system must continue during such quiescent periods. For example, it is a common practice to save power by halting clock signals to a device which is normally clocked, thereby precluding repeated strobing to check status according to a clock signal when such repeated checking of status is not necessary. That is, to conserve power a device may be rendered quiescent. However, such devices often require refreshing of memory devices, especially dynamic random access memory (DRAM) devices, and certain other functions must continue despite the stoppage of clocking signals to the computer processing unit.
The present invention provides an apparatus for accommodating such continued operational requirements during times when a computer processing unit is quiescent.