1. Field of the Invention
The present invention relates to an image generation method and an apparatus, and more particularly to an image generation method and an apparatus comprising a plurality of DRAMs for storing data separately corresponding to respective pixels on a screen.
2. Description of the Invention
Hitherto, an image generation apparatus of this kind has a memory for storing data which correspond to respective pixels, and competence of memory interface for transferring the pixel data controls mainly the speed of the image generation. Therefore, from one aspect, it has been necessary to use the memory of a high transfer rate, but due to an expensive cost of the high speed memory, it has been required to use such as a DRAM which can be obtained at a lower price.
However, since the access speed of these DRAMs are slow, a new method is employed to meet the problem such that a screen is divided into rectangular areas to be obtained through 2.sup.x by 2.sup.y division of longitudinal and lateral ways, and assigns consecutive address numbers for pixels in the same low within a block, data corresponding to respective pixels are distributed to a plurality of DRAMs corresponding to a least significant bit of its low order address and then stored.
FIG. 1 is a partial block diagram showing an example of a structure of a conventional image generation apparatus at the write control time of the memory.
The conventional image generation apparatus comprises pixel processing unit 1, memories consisting of DRAMs 7 and 8, address FIFOs 3 and 4, data FIFOs 5 and 6, and memory controller 9, and memory controller 9 operates at the write control time of the memory.
Pixel processing unit 1 generates address signal 50 and data signal 51 for each block corresponding to each pixel in an image on a screen, and outputs thus generated signals pixel by pixel together with write request signal 52, and also outputs block processing completion signal 63 when the processing of one block is finished. DRAMs 7 and 8 receive address signals 59, 60 and data signals 61, 62 from address FIFOs 3, 4 and data FIFOs 5, 6, and then these signals are write-controlled at the same timing in accordance with DRAM control signals 57, 58.
Address FIFOs 3, 4 divide and temporarily hold address signal 50 in accordance with input control signals 54, 55, and output address signals 59, 60 to DRAMs 7, 8 at the same timing in accordance with output control signal 56 from memory controller 9.
Data FIFOs 5, 6 divide and temporarily hold data signal 51 in accordance with input control signals 54, 55, and output data signals 61, 62 to DRAMs 7, 8 in accordance with output control signal 56 from memory controller 9.
Memory controller 9 receives address signal 50 and write request signal 52, and outputs input control signal 54 when the least significant bit of address signal 50 is 0 and write request signal 52 becomes effective. On the other hand, memory controller 9 outputs input control signal 55 when the least significant bit of address signal 50 is 1 and write request signal 52 becomes effective. Memory controller 9 also outputs output control signal 56 and DRAM control signals 57, 58 when address FIFOs 3, 4 have data held therein and DRAMs 7, 8 are in writable conditions. Further, memory controller 9 outputs output control signal 56 and DRAM control signals 57, 58 so that data remained in address FIFOs 3, 4 and data FIFOs 5, 6 may be outputted to DRAMs 7, 8 when block processing completion signal 63 becomes effective.
The operation of the conventional image generation apparatus at the write control time of the memory is described hereinafter.
FIG. 2 is an arrangement diagram showing column-address arrangement example 1 in a block of the conventional image generation apparatus shown in FIG. 1. Here, a block is divided into rectangular segments through 2.sup.3 by 2.sup.3 division of longitudinal and lateral ways, a column address of the block has bus width of 3+3=6 bits, bisecting to a high order 3 bits and a low order 3 bits and they are assigned to a longitudinal address and a lateral address, respectively, and the least significant bit (the first bit) of the lateral address of the block is used as discrimination bit (the low order address) which selects DRAM 7 or 8. For explanation of the operation, we assume a case where address data of each segment of block 17 included in superposed image 16 are written on DRAMs 7, 8.
First, in pixel processing unit 1, address signals 50 which correspond to pixels in image 16 on the screen are produced from upper left in the order of 05h, 06h, 0Dh, 0Eh, 0Fh, 15h, 16h, - - - , 37h, 3Dh, 3Eh, 3Fh and are outputted pixel by pixel together with data signal 51 and write request signal 52.
At this time, in memory controller 9, input control signal 54 is outputted when the lateral least significant bit (the first bit) of address signal 50 is 0 such as 06h, 0Eh, - - - , 3Eh and also write request signal 52 becomes effective. Then address signal 50 and data signal 51 are temporarily retained in address FIFO 3, data FIFO 5 in the address order such as 06h, 0Ch, - - - , 3Eh. On the other hand, when the lateral least significant bit (the first bit) of address signal 50 is 1 such as 05h, 0Dh, 0Fh, - - - , 3Fh and also write request signal 52 becomes effective, input control signal 55 is outputted and address signal 50 and data signal 51 are temporarily held in address FIFO 4 and data FIFO 6 in the order of the address such as 05h, 0Dh, 0Fh, - - - , 3Fh.
Next, in memory controller 9, when there are data in FIFOs 3, 4 and at the same time DRAMs 7, 8 are in writable conditions, output control signal 56 and DRAM control signals 57, 58 are outputted. Now, when there is data in one of FIFOs 3, 4, then only one of DRAM control signals 57, 58 is outputted. Then, in accordance with output control signal 56, address signal 59 and data signal 61 are outputted in order from address FIFO 3 and data FIFO 5 to DRAM 7, and concurrently address signal 60 and data signal 62 are outputted in order from address FIFO 4 and data FIFO 6 to DRAM 8, and also DRAMs 7, 8 are write-controlled at the same timing according to DRAM control signals 57, 58.
Subsequently, in pixel processing unit 1, block processing completion signal 63 is outputted when the processing of one block is finished. When this block processing completion signal 63 becomes effective, output control signal 56 and DRAM control signals 57, 58 are outputted from memory controller 9, and data remained in address FIFOs 3, 4 and data FIFOs 5, 6 are outputted to DRAMs 7, 8 to be stored.
FIG. 3 is an explanation diagram showing an example of write access operation conducted to DRAMs 7, 8 under the column-address arrangement shown in FIG. 2, illustrating write access order to each DRAM 7, 8 and a column address of each DRAM 7, 8. Here, although columns for write access to DRAM 7 in ninth to fifteenth times are recorded as unused, this means that DRAM control signal 57 is not issued and any write operation is not conducted to DRAM 7 at the corresponding time.
FIG. 4 is an arrangement diagram showing column-address arrangement example 2 in a block of the conventional image generation apparatus of FIG. 1.
The image area is divided into rectangular areas through 2.sup.3 by 2.sup.3 division in longitudinal and lateral ways and column address of a lateral order address in a block has bus width of 3+3=6 bits, bisecting to the high order 3 bits and the low order 3 bits and they are assigned to a longitudinal address bits and a lateral address bits, respectively, and the least significant bit (the first bit) of the lateral address bits is used as discrimination bit (the low order address) which selects DRAM 7 or 8.
For explanation of the operation, we assume a case where address data of each pixel of block 19 included in superposed image 18 are written on DRAMs 7, 8.
First, in pixel processing unit 1, address signals 50 which correspond to pixels in image 18 on the screen are produced from upper left in the order of 01h, 02h, 03h, 04h, 05h, 06h, 07h, 08h, - - - , 14h, 15h, 16h, 17h and are outputted pixel by pixel together with data signal 51 and write request signal 52.
At this time, in memory controller 9, input control signals 54 are outputted when the longitudinal least significant bit (the fourth bit) of address signal 50 is 0 such as 01h, 02h, - - - , 06h, 07h, 10h, - - - , 17h and also write request signal 52 becomes effective. Then address signal 50 and data signal 51 are temporarily held in address FIFO 3, data FIFO 5 in the address order such as 01h, 02h, 03h, 04h, - - - , 17h. On the other hand, when the longitudinal least significant bit (the fourth bit) of address signal 50 is 1 such as 09h, 0Ah, 0Bh, - - - , 0Fh and also write request signal 52 becomes effective, input control signal 55 is outputted and address signal 50 and data signal 51 are temporarily held in address FIFO 4 and data FIFO 6 in the order of the address such as 09h, 0Ah, 0Bh, - - - , 0Fh.
Next, in memory controller 9, when there are data in FIFOs 3, 4 and at the same time DRAMs 7, 8 are in writable conditions, output control signal 56 and DRAM control signals 57, 58 are outputted. Now, when there is data in one of FIFOs 3, 4, then only one of DRAM control signals 57, 58 is outputted. Then, in accordance with output control signal 56, address signal 59 and data signal 61 are outputted in order from address FIFO 3 and data FIFO 5 to DRAM 7, and concurrently address signal 60 and data signal 62 are outputted in order from address FIFO 4 and data FIFO 6 to DRAM 8, and also DRAMs 7, 8 are write-controlled at the same timing according to DRAM control signals 57, 58.
Subsequently, in pixel processing unit 1, block processing completion signal 63 is outputted when the processing of one block is finished. When this block processing completion signal 63 becomes effective, output control signal 56 and DRAM control signals 57, 58 are outputted from memory controller 9, and data remained in address FIFOs 3, 4 and data FIFOs 5, 6 are outputted to DRAMs 7, 8 to be stored.
FIG. 5 is an explanation diagram showing an example of write access operation conducted to DRAMs 7, 8 under the column-address arrangement shown in FIG. 4, illustrating write access order to each DRAM 7, 8 and a column address of each DRAM 7, 8. Here, although columns for write access to DRAM 8 are recorded as unused in ninth to fifteenth times, this means that DRAM control signal 58 is not issued and any write operation is not conducted to DRAM 8 at the corresponding time.
In the conventional image generation apparatus, a longitudinal and a lateral address in a block are assigned to a column address of DRAM 7, DRAM 8, and according to the least significant bit of the longitudinal address or the lateral address, it is determined which of DRAM 7 or DRAM 8 is to be selected and assigned. Therefore, on the boundary of the block, there reside pixels which perform one-side access to either of DRAM 7 or DRAM 8, and hence some of columns of DRAM 7 or DRAM 8 remain unused. Consequently, when an image is produced on the address space on the DRAM demarcated by the block, a number of one-side access to DRAM 7 or DRAM 8 are generated resulting in a problem of unbalanced access frequency so that it makes a slow image generation during an extended time period.