1. Field of the Invention
The present invention relates to a microprocessor, and more particularly to a microprocessor having a translation lookaside buffer (TLB).
2. Description of the Related Art
In a virtual memory computer, it is necessary to translate a virtual address into a physical address (address translation) during program execution. A hardware mechanism for the address translation is called a dynamic address translator (DAT). The DAT refers to an address translation table (a table constituted of a segment table, a page table, and so on) to execute the address translation. The address translation table is in a main memory and managed by an operating system (OS). The address translation table shows, for example, which virtual page number corresponds to which physical page number.
If the DAT refers to the address translation table for every address translation, overhead for the address translation substantially increases. Therefore, in a general practice, previously used address translation information (a pair of the virtual page number and the physical page number) is registered in a high-speed memory with locality of the address reference taken into consideration. This memory is called a translation lookaside buffer (TLB) or an address translation buffer. The TLB has a plurality of entries in which the address translation information is registered.
If there is no address translation information corresponding to a virtual address in the TLB at the time the address translation is executed, it is necessary to substitute address translation information obtained by address translation using the address translation table for the address translation information registered in any one of the entries. In other words, the entry substitution is required to be executed. An entry to be substituted is chosen according to LRU (Least Recently Used) algorithm, for example. Specifically, an entry that was referred to least recently is chosen as a subject of substitution with locality of the address reference taken into consideration.
However, for example, in a case a frequently used program is executed after a less frequently used program in a time-slice OS, one entry substitution request made during the less frequently used program leads to occurrence of a lot of the entry substitution requests during the frequently used program. Therefore, the advantages of the TLB cannot be exerted.
In order to solve this problem, Japanese Unexamined Patent Application Publication No. Hei 4-338848, for example, proposes a TLB having a function of prohibiting the entry substitution (entry lock). In this kind of TLB, each entry has a substitution prohibition bit. The substitution prohibition bit is set in an entry having registered therein address translation information used for a frequently used program (such as a program needed to have a realtime property), i.e., information required to be resident in the TLB. The entry having the set substitution prohibition bit is excluded from candidates for the entry substitution.