1. Field of the Invention
The present invention relates to a method of making a trench capacitor. More particularly, the present invention relates to a process for fabricating a semiconductor trench capacitor within a dynamic random access memory (DRAM) cell.
2. Description of Related Art
Due to the extensive use and broad range of applications for integrated circuits, a wide variety of semiconductor memory devices have been developed. In these semiconductor memory devices, dynamic random access memory (DRAM) presently plays an important role. Today, most DRAM cells consist of at least a transistor and a capacitor. FIG. 1 shows a structure of a DRAM cell. A drain electrode of a NMOS transistor is connected to a storage electrode of a capacitor 20 and a gate of the NMOS transistor is connected to a word line WL. An opposed electrode of the capacitor 20 is connected to a voltage source supplying a constant voltage, and between the storage electrode and the opposed electrode exists a dielectric layer. By controlling the ON or OFF state of the NMOS transistor, the capacitor saves or releases electric charges to perform the level-memory function of the memory cell.
In DRAM with the capacity of one megabyte, a planar type capacitor is typically used to access electric data, i.e. to save or release electric charges. It is known that because the planar type capacitor has a two-dimensional structure, a large area of the semiconductor substrate is used to form the planar type capacitor to supply enough capacity for a DRAM cell. But there exists a continuing demand for inexpensive DRAM having increased memory and reduced chip size. The reduced-size chip limits the area available for forming the planar type capacitor and thus the capacity of planar type capacitor is reduced. Therefore, the planar type capacitor can not meet the requirements for DRAM with a higher and higher density of integrated circuits.
To improve the above drawback of the planar type capacitor, a three-dimension structure for DRAM capacitors is disclosed in the prior art. In U.S. Pat. No. 5,395,786, U.S. Pat. No. 5,658,816, and L. Nesbit, et al, "A 0.6 .mu.m 265 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)", 1993 IEDM, pp. 627-630 disclose relevant technologies for a trench type capacity used for DRAM cell. By using said semiconductor processes for the capacitors of DRAM cells, the area occupied by the capacitors on the substrate is significantly reduced to increase the density of integrated circuits. In the process to form trench capacitors, isolation layers (e.g. ON layer or ONO layer) and conduction layers (e.g. formed by n+ polysilicon) are deposited and etched many times. For general processes, a predetermined pattern on a mask is used to etch the photoresist layer and the substrate to form a trench. A charge storage portion (capacitor plate) and an insulating layer are formed along the side-wall of the trench. Finally, a conductive material is filled into the trench to form a trench capacitor.
FIGS. 2A.about.2F show a fabricating process for the trench capacitor disclosed in L. Nesbit, et al., "A 0.6 .mu.m 256 Mb trench DRAM cell With Selft-Aligned BuriEd STrap (BEST)", 1993 IEDM, pp. 627-630. As shown in FIG. 2A, an epi layer 210 is formed on a P- substrate 200. Then a silicon oxide layer 220 and a silicon nitride layer 221 are formed to protect the epi layer 210. A predetermined pattern is used to expose a photoresist layer (not shown in FIG. 2A) and a trench 230 is etched a predetermined depth into the P- substrate 200.
Next, as shown in FIG. 2B, a capacitor plate 240 for storing charges for the trench capacitor is formed in the substrate 200 by outdiffusing a N+ material, e.g. arsenic or phosphorus, from the lower portion of the trench 230. A dielectric layer 250, for example, an oxide nitride (ON) layer, is deposited on the capacitor plate 240 to form a trench 231.
After depositing N+ polysilicon as a conductive material through CMP (Chemical Mechanical Polishing), and then recess-etching the polysilicon and striping a portion of the oxide nitride (ON) layer, a first conductive portion 260 and a dielectric layer 250' are formed as shown in FIG. 2C. Then trench 231 in FIG. 2B changes into a trench 232.
In FIG. 2D, a collar silicon oxide layer 270 is deposited around on the side-wall of the trench 232 and a second conductive portion 261 is filled in the deposited trench (not shown in FIG. 2D) by well-known techniques for the semiconductor process. The collar silicon oxide layer 270 may be deposited by silicon oxide to insulate against leakage current. The second conductive portion 261 may be formed by depositing polysilicon heavily doped by arsenic or phosphorus.
Then the collar silicon oxide layer 270 and the second conductive portion 261 are recess-etched. The result is shown in FIG. 2E, wherein the collar silicon oxide layer 270 and the second conductive portion 261 become a collar silicon oxide layer 270' and a third conductive portion 261', respectively. It is noted that in the above step of forming a trench 233, to etch to the silicon oxide in collar silicon oxide layer 270 and the polysilicon in the second conductive portion 261 requires two depth decisions for two different materials and two selective etchings.
At last, as shown in FIG. 2F, N+ polysilicon is deposited in the trench 233 in FIG. 2E to form a fourth conductive portion 262, completing the trench capacitor for use in the next step of constructing a DRAM cell.
However, whether isotropic or anisotropic etching is used to perform the two selective etchings, two depth decisions have to be individually made with respect to two different materials, making the semiconductor process will become more difficult. Furthermore, before these two etchings, two associated photolithography processes are necessary. In addition, after depositing the fourth conductive portion 262, if the etching process of the collar silicon oxide layer 270 has failed, or the depth of the collar silicon oxide layer 270 in FIG. 2C is too small, a leakage current is caused between the capacitor plate 240 in FIG. 2 and the fourth conductive portion 262 since both of the charge storage areas are too close and therefore can short if operated under a high voltage. Thus, the charge storage performance of the trench capacitor will be negatively effected.