Typically the most common method by which combinatorial and sequential logic simulations occur are by traversal of logic networks as represented in a logic schematic. Such logic schematics include electrical circuit diagrams. The actual implementation of logic being simulated dictates how the simulator will traverse and schedule events during stabilization of signals in the logic network. This prior art method typically involves evaluation and conformation of sensitive and non-sensitive signals associated with logic in a given logic network. Sensitive signals are those that are dependent upon or affected by another signal. In many instances, the entire logic network or logic circuit must be evaluated even though some non-sensitive signals do not contribute to the signals of interest. The prior art method allows optimization to occur only in actual circuit implementation or internal algorithmic methods of the simulator's stabilizing mechanism. Neither of these options takes full advantage of the simulation environment.
The external information presented to a prior art logic simulator includes a definition of a circuit and the events causing propagation of signals through the defined circuit. This information may be provided as shown in the following example:
Signals: PA1 Relationships: PA1 Signals: PA1 Relationships:
Q, QBAR, S, R PA2 Q:=(S'* QBAR')', PA2 QBAR:=(R'* Q)' PA2 Q, S, QBAR, CLOCK PA2 Q:=((S * CLOCK)'* QBAR)'
In the above example, a functional sequential circuit is specified. As specified, the example logic circuit is sensitive to four signals: Q, QBAR, S, and R. Input signals `S` and `QBAR" will produce the product `Q`. Input signals `R` and `Q` will produce the product `QBAR`. Q and QBAR are generated by the prior art simulator whenever any of the sensitive factors or logic signals change state.
Given an instance where input signal `S` is the only signal changing state (for example toggling from a logic 0 state to logic 1 state), only the product `Q` needs to be computed by the simulator. Prior art systems, however group all four signals (Q, QBAR, S, and R) together. Thus, the prior art grouping of the sequential circuit contains unnecessary overhead.
To illustrate consider the following truth table:
______________________________________ R S Q QBAR Q(t) QBAR(t) ______________________________________ 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 ______________________________________
The truth table indicates signal dependencies and the relationships that may be optimized. In the prior art, the actual sequential logic under simulation is traced out and evaluated. All signal dependencies are propagated to reach the final resulting signal values. Thus, the traditional method is not efficient in optimizing for signal relationships.
Additionally, another problem exists in prior art logic simulators when modeling zero delay logic circuits or other circuits where the timing of signal state changes is critical. This problem is illustrated in the following examples.
Given a clocked sequential circuit, SR flipflop, as described below:
In the above example, if the input signals `S` and `CLOCK` are active at the same instant in time, the product `Q` will change state. This could possibly be valid in a real implementation as the input signal `CLOCK` may require a zero or negative setup and hold condition on input signal `S`. In that case, this level of precedence is still functionally valid without any constraints of a timing model imposed. However, if input signal `CLOCK` requires `S` to arrive before `CLOCK` is active, an incorrect behavior will be simulated in the above example, without any timing models or other solution imposed. Thus, prior art simulators are unable to properly and conveniently model time critical signal dependencies.
Thus, it is an object of the present invention to provide a logic simulation system including optimal configurability of combinatorial and sequential logic circuits in a behavioral form. It is a further object of the present invention to provide a logic simulation system allowing external definability of possible events which trigger combinatorial and sequential logic propagation. It is a further object of the present invention to provide a logic simulation system that eliminates unnecessary evaluations. It is a further object of the present invention to provide a logic simulation system that efficiently models time critical signal dependencies.