The present invention generally relates to the manufacture of printed wiring boards and more specifically to the filling of clearance patterns in conductive constraining core layers used in the construction of multilayer printed wiring board (PWB).
Computers and similar electronics products are pervasive in consumer, businesses, military, aerospace and governmental activities. The use of electronics in critical applications has created an increased demand for reliable electronics. Many applications specify electronics that will run longer with less down time than was expected in the past.
The increased emphasis on reliability amongst customers also extends to PWBs. PWBs can be used to establish electrical connections between devices. In some instances, the devices can be mounted on the printed wiring board. The manner in which the devices are mounted is typically dependent upon the packaging of the device. Applications for printed wiring boards can include challenges such as thermal management, expansion mismatch control, low stiffness or rigidity and higher weight. Materials that have been used in the past to address some of these issues include thick metal core, copper-Invar-copper (CIC), copper-Moly-copper (CMC). These metal core materials are electrically conductive and require special processing in order to be incorporated into printed wiring board structures. These special processes can include drilling clearance patterns, surface preparation, clearing pattern filling and additional lamination steps. Use of these materials and the associated additional processes are typically associated with a substantially lower manufacturing yield and additional labor cost. In addition, drilling small via holes or plated through holes (PTH) through thick metal cores can be problematic. An inability to drill small via holes through a material can limit the usefulness of the material in the construction of high density interconnects.
A variety of other materials can be used in place of the metal materials above to try and address reliability issues such as thermal management, expansion mismatch control, low stiffness or rigidity and higher weight. U.S. Pat. No. 6,869,664 to Vasoya et al., U.S. patent application Ser. No. 11/131,130 to Vasoya, U.S. patent application Ser. No. 11/376,806 to Vasoya and U.S. Provisional Patent Application Ser. No. 60/831,108 to Vasoya disclose techniques that can be used to manufacture printed wiring boards having a desired coefficient of thermal expansion (CTE) using layers incorporating carbon materials such as woven carbon fiber. The disclosure of U.S. Pat. No. 6,869,664 to Vasoya et al., U.S. patent application Ser. No. 11/131,130 to Vasoya, U.S. patent application Ser. No. 11/376,806 to Vasoya and U.S. Provisional Patent Application Ser. No. 60/831,108 to Vasoya is incorporated herein by reference in its entirety.