def generate_ports(self, definition, actor=None):
        is_component = actor is None
        actor = '.' if is_component else actor
        for port_dir in ['in', 'out']:
            target, target_port = self.twiddle_portrefs(is_component, port_dir)
            def_dir = 'inputs' if port_dir == 'in' else 'outputs'
            for p, _ in definition[def_dir]:
                yield((p, target, target_port, port_dir, actor))
This generator takes care of remapping src and dst with respect to programs and component definitions.
dataset/ETHPy150Open EricssonResearch/calvin-base/calvin/csparser/checker.py/Checker.generate_ports