Wireless HDL Toolbox


Wireless HDL Toolbox

Design and implement 5G and LTE communications subsystems for FPGAs, ASICs, and SoCs

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Reference Application Hardware Subsystems

Integrate prebuilt and FPGA-proven subsystems to improve your system design efficiency.

5G New Radio (NR) Cell Search and MIB Recovery

Perform primary and secondary signal (PSS and SSS) synchronization and master information block (MIB) recovery in accordance with the 5G NR standard with this hardware-proven subsystem. It includes a MATLAB algorithm reference for verification.

LTE Cell Search, MIB, and SIB1 Recovery

Use this subsystem to detect and demodulate eNodeB signals and to decode Master Information Block (MIB) and the System Information Block (SIB1) information for use in your FPGA or ASIC application. It supports FDD and TDD modes and has been proven in hardware to detect LTE signals on three different continents.

Configurable OFDM Transmitter and Receiver

Transmit and receive data using orthogonal frequency division multiplexing (OFDM). Configure parameters, symbol modulation types, and code rates. Model and configure impairments such as additive Gaussian white noise (AWGN). It includes a MATLAB algorithm reference for verification.

Waveform spectrum from the example F-OFDM transmitter.

5G, LTE, and Wireless IP Blocks

Design wireless communications subsystems more quickly with hardware-proven streaming algorithms.

5G NR Intellectual Property (IP) Blocks

Design 5G NR FPGA or ASIC applications more quickly using hardware-proven implementations of popular algorithms. Model and simulate hardware implementations of algorithms for low-density parity checking (LDPC) coding and decoding, polar coding and decoding, and symbol modulation and demodulation, together with your custom functionality. Then use HDL Coder™ to generate synthesizable VHDL or Verilog RTL.

Configuring the HDL-optimized NR Polar Decoder block.

LTE IP Blocks

Model and simulate efficient hardware implementations of LTE-specific algorithms, such as turbo, convolutional, and CRC encoders and decoders as well as OFDM demodulators. Then use HDL Coder to generate synthesizable VHDL or Verilog RTL for your entire subsystem.

HDL-optimized LTE turbo and CRC decoders with control signal bus.

Multistandard IP Blocks

Use hardware-proven building blocks, such as a digital pre-distortion (DPD), a Viterbi decoder, a depuncturer, and a variable-size FFT for your hardware implementation of wireless standards, including 5G NR,LTE, WLAN, digital video broadcast (DVB), WiMAX®, and HiperLAN as well as digital satellite communications.

Using Depuncturer and Viterbi Decoder blocks to decode samples encoded at WLAN code rates.

Verification Using Your 5G or LTE Golden Reference

Connect frame-based algorithms and test benches to streaming hardware implementations for efficient verification.

Conversion Between Frames and Samples

Convert frame-based waveforms from MATLAB® to a stream of samples with control signals for processing in hardware. Then convert the streaming hardware output to frames for verification against your golden reference algorithm.

Frame-to-sample conversion and control signal generation.

MATLAB and Simulink Verification Examples and Templates

Learn how to use your 5G Toolbox™ or LTE Toolbox™ algorithms and tests to verify your hardware implementation.

HDL and FPGA Cosimulation

Use HDL Verifier™ to verify your hardware subsystem via RTL simulation or on an FPGA development kit connected to your MATLAB or Simulink test environment.

Connect your FPGA prototype to Simulink with HDL Verifier hardware-based verification.

FPGA, ASIC, and SoC Deployment

Easily target your wireless application to FPGA hardware for testing with live over-the-air signals and reuse the same models for production deployment.

Software-Defined Radio (SDR) Platforms

Prototype your wireless application by downloading the Communications Toolbox™ hardware support packages for Zynq® SDR to set up and target popular SDR devices using HDL Coder.

Production Deployment

Use HDL Coder to generate high-quality, target-independent RTL and AXI interfaces from your hardware subsystem models.

Generate code with SoC interconnect interfaces.