@phdthesis{10624, abstract = {The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.}, author = {Beisel, Tobias}, isbn = {978-3-8325-4155-2}, pages = {183}, publisher = {Logos Verlag Berlin GmbH}, title = {{Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}}, year = {2015}, } @article{296, abstract = {FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.}, author = {Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, journal = {International Journal of Reconfigurable Computing (IJRC)}, publisher = {Hindawi}, title = {{Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}}, doi = {10.1155/2015/859425}, volume = {2015}, year = {2015}, } @inproceedings{4465, abstract = {The first year of studying has been extensively researched applying different theoretical lenses to better understand the transition into Higher Education (HE). It is of particular interest to investigate how students deal with frictions between themselves as individuals and what they perceive to be dominant features of the first-year culture of their studies. To tackle this question, a qualitative longitudinal study was conducted. Based on a sociocultural understanding of attitudes and motivations, its aim was to closely follow a relatively small but highly diverse sample of students throughout their first year at a business school in order to develop an in-depth understanding of each individual’s motivational and attitudinal development.}, author = {Jenert, Tobias and Brahm, Taiga}, keyword = {Enculturation, first-year students, beginning students, retention, drop-out}, location = {Chicago}, title = {{How Do They Find Their Place? A Longitudinal Study of Management Students' Attitudes and Motivations During Their First Year at Business School}}, year = {2015}, } @misc{5413, author = {Funke, Lukas}, publisher = {Universität Paderborn}, title = {{An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures}}, year = {2015}, } @article{1772, author = {Torresen, Jim and Plessl, Christian and Yao, Xin}, journal = {IEEE Computer}, keyword = {self-awareness, self-expression}, number = {7}, pages = {18--20}, publisher = {IEEE Computer Society}, title = {{Self-Aware and Self-Expressive Systems – Guest Editor's Introduction}}, doi = {10.1109/MC.2015.205}, volume = {48}, year = {2015}, } @misc{5419, author = {Wallaschek, Felix}, publisher = {Universität Paderborn}, title = {{Accelerating Programmable Logic Controllers with the use of FPGAs}}, year = {2015}, } @inproceedings{1773, author = {Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and Lehmann-Miotto, Giovanna and Levinson, L. and Narevicius, J. and Plessl, Christian and Roich, A. and Ryu, S. and P. Schreuder, F. and Vandelli, Wainer and Vermeulen, J. and Zhang, J.}, booktitle = {Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher = {ACM}, title = {{Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}}, doi = {10.1145/2675743.2771824}, year = {2015}, } @article{1779, author = {Giefers, Heiner and Plessl, Christian and Förstner, Jens}, issn = {0163-5964}, journal = {ACM SIGARCH Computer Architecture News}, keyword = {funding-maxup, tet_topic_hpc}, number = {5}, pages = {65--70}, publisher = {ACM}, title = {{Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}}, doi = {10.1145/2641361.2641372}, volume = {41}, year = {2014}, } @inproceedings{388, abstract = {In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.}, author = {Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, booktitle = {Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, pages = {144--155}, publisher = {Springer International Publishing}, title = {{Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}}, doi = {10.1007/978-3-319-05960-0_13}, volume = {8405}, year = {2014}, } @inproceedings{439, abstract = {Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.}, author = {Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, pages = {1--8}, publisher = {IEEE}, title = {{Deferring Accelerator Offloading Decisions to Application Runtime}}, doi = {10.1109/ReConFig.2014.7032509}, year = {2014}, } @inproceedings{377, abstract = {In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.}, author = {Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, booktitle = {Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, keyword = {coldboot}, pages = {222--229}, publisher = {IEEE}, title = {{Reconstructing AES Key Schedules from Decayed Memory with FPGAs}}, doi = {10.1109/FCCM.2014.67}, year = {2014}, } @article{365, abstract = {Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.}, author = {Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, number = {2}, publisher = {ACM}, title = {{Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}}, doi = {10.1145/2617596}, volume = {7}, year = {2014}, } @article{328, abstract = {The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications}, author = {Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, journal = {IEEE Micro}, number = {1}, pages = {60--71}, publisher = {IEEE}, title = {{ReconOS - An Operating System Approach for Reconfigurable Computing}}, doi = {10.1109/MM.2013.110}, volume = {34}, year = {2014}, } @inbook{335, abstract = {Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinﬂusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte diﬀerenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design ﬁndet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonﬁgurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer ﬂexiblen Software damit auf.}, author = {Platzner, Marco and Plessl, Christian}, booktitle = {Logiken strukturbildender Prozesse: Automatismen}, editor = {Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, isbn = {978-3-7705-5730-1}, pages = {123--144}, publisher = {Wilhelm Fink}, title = {{Verschiebungen an der Grenze zwischen Hardware und Software}}, year = {2014}, } @inproceedings{406, abstract = {Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.}, author = {Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, pages = {1--8}, publisher = {IEEE}, title = {{Kernel-Centric Acceleration of High Accuracy Stereo-Matching}}, doi = {10.1109/ReConFig.2014.7032535}, year = {2014}, } @inproceedings{1778, author = {C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, booktitle = {Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, pages = {142--149}, publisher = {IEEE}, title = {{Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}}, doi = {10.1109/ISPA.2014.27}, year = {2014}, } @inproceedings{1780, author = {C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, booktitle = {Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher = {Springer}, title = {{SAVE: Towards efficient resource management in heterogeneous system architectures}}, doi = {10.1007/978-3-319-05960-0_38}, year = {2014}, } @article{363, abstract = {Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.}, author = {Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, journal = {Microprocessors and Microsystems}, number = {8, Part B}, pages = {911--919}, publisher = {Elsevier}, title = {{Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}}, doi = {10.1016/j.micpro.2013.12.001}, volume = {38}, year = {2014}, } @inproceedings{528, abstract = {Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.}, author = {Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, booktitle = {Proceedings of the International Conference on Field-Programmable Technology (FPT)}, keyword = {coldboot}, pages = {386--389}, publisher = {IEEE}, title = {{FPGA-accelerated Key Search for Cold-Boot Attacks against AES}}, doi = {10.1109/FPT.2013.6718394}, year = {2013}, } @inproceedings{505, abstract = {In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.}, author = {Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, booktitle = {Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher = {IEEE}, title = {{On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}}, doi = {10.1109/ISORC.2013.6913232}, year = {2013}, }