EDIT 3 The correct solution is shown below, in TurboJ's answer in fact, this exact issue was mentioned in the LPC4300 errata ES_LPC43x0:

enter image description here

EDIT: Nope, sorry false alarm. The new board started doing the same thing:(

EDIT 2: I'm beginning to wonder if poor layout is to blame. The +3V3 rail is shown. Because the board is a 2 layer, I had to forego the traditional power plane and power is provided by a single 6 mil trace. I noticed that the problem never occurred on a board with no decoupling capacitors populated, but started to happen when I added the .1uF capacitors.

I have a board with a LPC NXP 4330 (ARM Cortex M4/M0 dual core) microcontroller, in a TBGA-100 form factor. The power situation is complicated because I have sensors which require precision 4V power, so the main supply needs to be a LDO drop above 4V, so it is powered in the following way:

3.7V Lipoly or USB (controlled through MAX1555 battery charger) -> 4.5V step up/down switcher (TPS63061 integrated switcher) -> 3.3V low-drop out linear (LP38691) -> LPC 4330

I have noticed that on startup, the micro will start up very hot (too hot to touch) for a second, before settling down to a more reasonable temperature. When it does this, I can communicate through the JTAG just fine and run my application. It will always start up like this when connected to a 4.5V bench power supply (bypassing the switching regulator completely). The surge current is very high, up to a couple hundred of mA, as the spike in temps confirms.

When connected to the switcher (fortunately it is on another board, so it is easy to bypass), sometimes it does not start up. I assume that this is because the surge current is causing the switcher to shutdown because it goes into some over-current mode. If I disconnect the switcher from the load, plug in the battery first, and then plug it back into the load, it will cause the micro to get hot (as usual) and then work.

Is this normal behavior for the LPC 4330? It seems fairly unusual that a microcontroller would take several hundred mA to startup (where is all that current going?) Is there a way to prevent this initial current inrush when the entire circuit is hooked up.

I've included a schematic, I will need to run tests on the supply ramp up on Monday.

schematic (main micro board) Main micro-controller board

schematic (power board) Power and USB connector board

layout showing +3V3 rail Layout showing +3V3 rail

  • \$\begingroup\$ A schematic and a scope trace of the 3.3V line at startup would be helpful. \$\endgroup\$ – DeathBySnuSnu Aug 17 '13 at 1:40
  • 2
    \$\begingroup\$ I hate this kind of schematics. You have to look all over the diagram to find what a net connects to. \$\endgroup\$ – Johan.A Aug 17 '13 at 11:24
  • \$\begingroup\$ It's hard to read unless you have the software, since then you can just type show <NET> into the command prompt. It's mostly to stay within freeware Eagle limitations (1 schematic page) \$\endgroup\$ – Zuofu Aug 17 '13 at 11:25
  • \$\begingroup\$ What happens if you hold the processor reset asserted as your power it up? \$\endgroup\$ – Chris Stratton Aug 17 '13 at 15:34
  • \$\begingroup\$ If I solder a wire to to ground in place of the resistor on !RESET, nothing happens. It does not get hot, but the processor cannot come out of reset either. I don't have a reset switch, so there is no way to physically assert !RESET after power on. \$\endgroup\$ – Zuofu Aug 17 '13 at 20:23

One possible source of latch-up is USB_VBUS. The datasheet of the LPC43xx allow VBUS to be 5 V only when VCC is present - but in your case this takes a small amount of time until the regulators are fired up. Consider adding a resistor in this path.

Another issue is the ON-Switch of the FPGAs 3V3 LDO. It will be enabled by default, as the GPIO pins are "weak high" when not configured. The resulting voltage level is high enough to switch the regulator on. The SNS pin must be connected to VOUT, if present. You should change the drawing in case they are not.

  • \$\begingroup\$ I tried testing it with just the battery (no USB connected at all) and it will still latch-up/get hot, but it does sound like this is a potential problem. I noticed that a lot of designs will use a LM3526-H (USB power switch), but it seems unnecessarily complicated since I don't need to do anything fancy with the USB (no OTG, for example). Would adding a resistor to VBUS simply limit the current, or is it to increase the rise time? \$\endgroup\$ – Zuofu Aug 17 '13 at 12:41
  • \$\begingroup\$ Also, there is no SNS pin on the package of the LDO that I'm using, oddly there's a N/C pin where the SNS exists on other packages. I've left the SNS in the schematic symbol because the alternative packages have it, but I guess I could rename it to SNS/NC. It should be ok that the FPGA LDO starts up on, that only exists to give the micro flexibility to power down the FPGA if needed to save power. \$\endgroup\$ – Zuofu Aug 17 '13 at 12:43
  • \$\begingroup\$ Sorry to resurrect an old thread, but this was totally it! I changed this to the accepted answer. \$\endgroup\$ – Zuofu Oct 1 '13 at 2:22

NXP 4330 in accordance with IEC 60134 absolute max current should not exceed 100mA. The device is rated at 80mA at 200MHz at 3.3V. It sounds like it is dissipating much more than this, so I would suspect

if have a slow startup ramp on the supply, internal instability may cause max frequency oscillations so a power on reset may help. Naturally if the chip starts oscillating from 2 to 3 V and there are interface voltages exceeding this level latchup faults may occur where the short circuit currents can exceed 150 mA per port, so check your power on sequence ramps on a scope with a current shunt. Check your interface switch is low enough resistance to switch quickly.

  • \$\begingroup\$ I wonder if the layout has something to do with this, since I had to use a 2-layer design (so even though the ground plane is mostly intact, there is no power plane, only traces which supply power). However, if slow ramp up is a problem, doesn't more capacitance (in the form of a power plane) actually make the problem worse? Would adding a capacitor to the !RESET signal (thereby delaying the program execution start) help? \$\endgroup\$ – Zuofu Aug 17 '13 at 1:11
  • \$\begingroup\$ If your power switches in a few uS, no problem. If it switches in 100mS, big problem. Even with 100 uF on board , a 0.05 ohm switch turns on in 5us. Check your rise time and voltage and suspect your switch. !RESET is always greater by design than worst case ramp up voltage. So yes. \$\endgroup\$ – test engineer Aug 17 '13 at 1:18

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