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An Analytical Framework for Evaluating the Error

Characteristics of Approximate Adders

Approximate adders have been considered as a potential alternative for errortolerant applications to trade off some accuracy for gains in other circuit-based
metrics, such as power, area and delay. Existing approximate adder designs have
shown substantial advantages in improving many of these operational features.
However, the error characteristics of the approximate adders still remain an issue
that is not very well understood. A simulation-based method requires both
programming efforts and a time-consuming execution for evaluating the effect of
errors. This method becomes particularly expensive when dealing with various
sizes and types of approximate adders. In this paper, a framework based on
analytical models is proposed for evaluating the error characteristics of
approximate adders. Error features such as the error rate and the mean error
distance are obtained using this framework without developing functional models
of the approximate adders for time-consuming simulation. As an example, the
estimate of peak signal-to-noise ratios (PSNRs) in image processing is considered
to show the potential application of the proposed analysis. This analytical
framework provides an efficient method to evaluate various designs of

approximate adders for meeting different figures of merit in error-tolerant


APPROXIMATE computing has become a promising technique to reduce the
power, area and delay constraints in VLSI design, albeit at the expense of a loss in
computational accuracy [1]. This technique is applicable to error tolerant
applications such as multimedia, mining and recognition [2]. Generally, there are
two methodologies for reducing accuracy by approximation. The first methodology
uses a voltage-over-scaling (VOS) technique for CMOS circuits to save power,
while also introducing errors into the circuit [3], [4], [5]. The second methodology
is based on redesigning a logic circuit into an approximate version. While the VOS
technique is applicable to most circuits for error-tolerant applications, an
approximate redesign requires to consider the different functionalities of logic
circuits. As one of the simplest, but key components of arithmetic circuits, adders
have attracted an extensive interest for redesigning and implementing approximate

Approximate adders have been proposed by using a reduced number of

transistors [6], [7] and by truncating the carry propagation chain for a speculationbased operation [8], [9], [10], [11], [12]. An approximate speculative designs
achieve a better performance in terms of area, power and delay compared to
conventional (exact) adders. New metrics and simulation- based approaches have
been proposed to model and evaluate approximate adders according to specific
computational features [2], [13], [14], [15]. Monte Carlo or exhaustive simulation
approaches have been employed to acquire data for analysis. This class of
approaches are however time-consuming and require building functional models of
the approximate designs. To improve efficiency, a mathematical characterization of
the arithmetic accuracy of approximate adders is then required for a better
understanding of the design prior to a simulation based evaluation.

In this paper, an analytical framework is proposed to assess the arithmetic
accuracy, i.e. the error rate and mean error distance (MED), of approximate adders.
Three types of approximate adders are considered and their error features are
compared using the proposed analysis. The revealed error characteristics provide
insights into the quality of an appropriate adder for achieving a desired operational
accuracy. As an example of ASMs, the PSNR in image processing is considered. A

model is presented for estimating the PSNR from the MED obtained from the
proposed framework; experimental results show that the estimated PSNRs are very
close to the PSNRs obtained by simulation. The utilization of the proposed
framework to PSNR estimate provides an analytical approach for assessing and
designing a feasible approximate image processing system based on approximate
adders. The major contributions of this paper are as follows:
An analytical framework is developed for modeling and evaluating
the error characteristics of three types of approximate adders found in



A comparative study is performed for various approximate adders

using different carry speculation schemes to gain an insight into the
qualitative features of a design with respect to several error metrics.
An analytical approach is developed to model the relationship
between the PSNR and the MED obtained from the proposed
framework in approximate adder-based image processing. This
approach can effectively estimate the PSNR from the approximate
adders used in an image precessing application.

Fig. 3. Block diagram of error-tolerant adder type II. n: the adder size; k: half of
the maximum carry chain length.

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