What's required for downgrading from 4 lane to 1 lane?


What's required for downgrading from 4 lane to 1 lane?

Postby mwayne » Tue May 21, 2019 7:24 pm


I have an ML605 Virtex 6 board and have used the Xillybus interface with it quite a bit. I want to try a 16X to 1X PCIe riser, which looks like it just takes any type PCIe up to 16X and downsizes it to one lane. Are there any modifications I need to make to the demo bundle to make something like this work? I was thinking I might have to remove some of the lanes in the .ucf file, but I seem to recall PCIe can auto detect how many lanes are active. Can Xillybus do the same?


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Re: What's required for downgrading from 4 lane to 1 lane?

Postby support » Tue May 21, 2019 8:45 pm


Xillybus works on top of Xilinx' PCIe block, so the question is not if Xillybus' IP core supports lane downsizing, but if the PCIe block does.

The PCIe spec requires a negotiation between the two link partners on the largest possible lane width. As far as I've seen so far, all Xilinx' PCIe blocks worked properly with the number of lanes available, even when the number of connected lanes were lower than those supported by the PCIe block. Which isn't a surprise, as they wouldn't be PCIe compliant otherwise.

So short answer: Yes, I would expect that just putting a 16x -> 1x PCIe riser will just work with PCIe 1x, with no need to change anything in the FPGA design.

However for a permanent solution, this is a waste of logic resources and power consumption. Should you want to reduce the lane count in the design, please refer to section 4.5 of the Getting Started guide for Xilinx:

http://xillybus.com/downloads/doc/xilly ... xilinx.pdf

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