Take the 2-minute tour ×

How can I call a function inside a module in verilog, with the function having parameters, and define the parameters to it?

For a trivial instance:

function automatic void inv();
  parameter W = 1;
  input logic [W:0] in;
  output logic [W:0] out;

  out = ~in;


How would I call this and define W in the call?

share|improve this question
In what context is the function called? We need a more complete example. –  Adam12 Aug 30 '12 at 3:52
add comment

2 Answers

You cannot override a parameter value when calling a function. There is no syntax for this specified in the IEEE Std (1800-2009).

share|improve this answer
Is there any way to pass in the width (W)? Also, is there any way in SystemVerilog? –  A J Aug 31 '12 at 0:16
I think you want to pass a bit mask into the function and as input. –  toolic Aug 31 '12 at 0:19
add comment

As stated parameters are constant and cannot be changed after design elaboration. The dimensions are part of the data type so they also must be constant during design elaboration. If all your function calls are outside procedural contexts you might be able to get away with passing in a constant as an argument. I don't recommend doing this.

share|improve this answer
add comment

Your Answer


