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Cameron and Tracey Hughes

Dr. Dobb's Bloggers

The Future of Microprocessors and the Potential Trick Bag for Developers

May 31, 2011

For those of you who pay attention to such things, you would have seen an article by Shekhar Borkar and Andrew Chien in the May 2011 edition of the Communications of the ACM journal prognosticating the "Future of Microprocessors." And for those of you who don't pay attention to such things, what are you waiting for? The Communications of the ACM is really top-shelf stuff. Borkar and Chien's article on the future of microprocessors is a fine piece of prophecy that we highly recommend for anybody who wants to know where all this multicore, parallelism, performance-speedup stuff is going.

The argument on energy efficiency as the new limiter of processor performance as opposed to the numbers of processors is worth the price of admission. What has me and Tracey in the trick bag from Borkar and Chien's predictions is the concept of multiple choice in organization for the 150-million logic transistors that will eventually make up the cores. It appears that chip architects will have numerous options for organizing tomorrow's microprocessors. Many of the options have to do with trade-offs between the size of the cores and the numbers of the cores on a single chip, or the types and complexity of the parallelism that the cores will or won't support. For example, they give three scenarios for the 150 million transistors:

  • Scenario One: 6 large cores with good single thread performance, but only a throughput of 6
  • Scenario Two: 30 small cores with poor single thread performance, throughput of 13
  • Scenario Three: Mixing large and small cores with good single-thread performance with the somewhat lower throughput of 11

And as it turns out, there are many more options for customization when it comes to the size, number, and sophistication of the cores. All of this is fine and dandy, but the burning question we have is will all of this customization be transparent to the software developer? Or will developers have to use some kind of cafeteria approach to parallel development driven by the flavor of cores' customization that we are presented with. It's already tricky enough dealing with numbers of cores and memory management schemes, could it be that we'll have to worry about sizes of cores and sophistication levels of cores on top of everything else? It just doesn't seem likely that we'll be able to use the "write once, run everywhere" notion if microprocessors are going to be that customizable in the future.

Somebody just tell us we're reading too much into it; otherwise, here comes the trick bag.

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