

Chegg Guided Solutions for CMOS Digital Integrated Circuits Analysis & Design 3rd Edition Chapter 9 Problem 2

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9.2 In logic design, complex gates such as AOI or OAI gates are often used to combine the functions of several gates into a single gate, thus reducing the chip area and parasitics of the circuit. Let us consider an OAI432 whose logic function is 6102-9-2I1.png Assume that only A, E, H inputs are high and other inputs are low. The device parameters are:

Cjsw = 250 pF/m

Cjo = 80 μF/m

Cox = 350 μF/m2

LD = 0.5 μm

Keq = 1.0 for worst-case capacitance

Cmatal = 2.0 pF/m

Cpoly = 2.2 pF/cm

Rpoly = 25 Ω/sq

Rmatal = 0.2 Ω/sq

Polysilicon line width = 2μm, metal line width = 2μm

k′n = 20 μA/A2

k′n = 10 μA/V2

|VT0| = 1.0V

(a) Draw a full CMOS circuit diagram for this OAI432.

(b) Draw a domino CMOS circuit implementation whose output is 6102-9-2I2.png.

(c). Draw an equivalent circuit for this case by using equivalent transistor sizes with W/L=30/2 (both for NMOS and PMOS).

(d). By assuming that the total parasitic capacitances at the precharging node and the output nodes are 0.2 pF,ealculate the delay from the end of precharging (clock signal is a rectangular pulse) to the time point at which output voltage reaches 2.5 V. For simple analysis, neglect the body effect. For approximate solution of this problem, first calculate the delay for the precharging node to fall to 2.5 V. Then use a rectangular pulse at that time point which falls from 5 V to 0 V to calculate the delay of the inverter gate. The total delay can be found by adding the two delay components. (A more accurate method is to approximate the precharging node voltage by a falling ramp function.)

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