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Class 708/632 - Feedback

Subclass of Class 708 - Electrical computers: arithmetic processing and calculating
Definition: Subject matter including means which involves feeding back
No. of patents: 33
Last issue date: 02/13/2007

NumberTitleIssue Date
7177421Authentication engine architecture and method
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in ...
7028068Alternate phase dual compression-tree multiplier
A multiplier includes a plurality of subunits. Each of the plurality of subunits is configured to perform a portion of a multiplication operation, and the plurality of subunits are coupled together to perform the multiplication operation. At least a first subunit of...
6993071Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers
A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied a...
6970994Executing partial-width packed data instructions
A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur...
6925553Staggering execution of a single packed data instruction using the same circuit
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ...
6609189Cycle segmented prefix circuits
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the...
6434586Narrow Wallace multiplier
A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M array of partial products representing low order bits, and a s...
6175912Accumulator read port arbitration logic
A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination....
6128726Accurate high speed digital signal processor
An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated a...
6052706Apparatus for performing fast multiplication
In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a s...
6035319Parallel-serial multiplier and accumulator
An improved parallel-serial multiplier and accumulator for multiplying a digital multiplicand and a multiplier resulting in a product that is added to an accumulator input. The parallel-serial multiplier and accumulator includes a parallel-serial multipli...
6004022Product sum operation apparatus
A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of bits to be operated is increased. A partial product gener...
5958000Two-bit booth multiplier with reduced data path width
A two-bit Booth multiplier circuit performs two-bit multiplication iterations using a single adder while retaining the same data path width and the multiplicand multiples of a single-bit Booth multiplier circuit. The two-bit Booth multiplier circuit halve...
5941942Method for multiplying a multiplicand and a multiplier according to the booth method in interactive steps
In a modified Booth's algorithm only one shift unit is required for multiplication of the partial products. This is based on the known coding prescriptions of the Booth's algorithm, which respectively determines from 3 bits of the multiplier how the parti...
5892699Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic
A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as th...
5889691Apparatus and method for a multiplier unit with high component utilization
In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multip...
5847981Multiply and accumulate circuit
A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corre...
5835393Integrated pre-adder for a multiplier
A preadder for a multiplier integrates a pre-adder and Booth encoder. The integrated pre-adder/Booth encoder comprises multiple stages, each of which adds and encodes multiple bits (usually two) of two numbers x and y. Each stage comprises three blocks, a...
5303178Multiplying system based on the Booth's algorithm and generating a positive or negative product in response to a mode signal
A multiplying system based on the Booth's algorithm, comprises a Booth's decoder having a first input receiving a multiplier "Y" and a second input receiving a mode signal designating either a first multiplication of "X×Y" (where "X" is a multiplicand) o...
5226003Multi-path multiplier
A low-cost high-speed multiplier comprises a first register for holding a multiplier; a second register for holding a multiplicand; a partial product generator for scanning the multiplier held in the first register to generate three partial products of th...
5220525Recoded iterative multiplier
A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to pro...
5138570Multiplier signed and unsigned overflow flags
When performing fixed point multiplication with 32 bit operands for example, the product is, in general, represented by a 64 bit number. However, a typical microprocessor may compute the product to only 32 bits. Therefore, the possibility of overflow exis...
5036482Method and circuitry for digital system multiplication
A method nad circuitry for multiplication in a digital system is described. The circuitry includes a partial product generator, a carry-save adder, a sum latch, a carry latch, an adder, a latch, circuitry for truncating, and coupling circuitry. A method a...
5008850Circuitry for multiplying binary numbers
A circuit for multiplying two binary numbers including apparatus for sorting one of the binary numbers into groups of variable lengths, each group including all contiguous ones beginning at the lowest order bit and all continguous zeroes beginning with th...
4972362Method and apparatus for implementing binary multiplication using booth type multiplication
In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-sa...
4807175Booth's multiplier
In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PPi (Yi, Yi+1, Yi+2); partial products PDi are formed separately in sequ...
4727507Multiplication circuit using a multiplier and a carry propagating adder
A multiplication circuit used for a high speed multiplier in a computer system is basically constituted by a multiplier and a carry propagating adder. The multiplier obtains a sum and carry per each bit by using carry save adder trees having a plurality o...
4679165Multiplication unit and method for the operation thereof
A multiplication unit for n-place binary numbers has a first register containing the multiplicand, and accumulator, and an arithmetic unit having operand inputs connected to the first register and to the accumulator. The operation to be undertaken by the ...
4597053Two-pass multiplier/accumulator circuit
A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations ar...
4546446Digital processing circuit having a multiplication function
In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the ...
4484301Array multiplier operating in one's complement format
A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate ...
4173789Multiplication control system
A multiplication control system comprising a multiplying circuit to which a binary-coded multiplier and a binary-coded multiplicand are supplied, a leading 0/1 decoder which detects the number of significant digits in the binary-coded multiplier, a divide...
4041292High speed binary multiplication system employing a plurality of multiple generator circuits
A multiplication apparatus comprises a plurality of multiple generator circuits, each of which simultaneously generates binary signals representative of a predetermined multiple of a multiplicand for different digits of a group of multiplier digits. A dif...
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