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  PCI Express Reference Guide (ver 2.1)

Author: Mungler
Editor: Agi

PCI-Express is a relatively new technology marketing buzz word that heralds the latest revolution for computer bus architecture. But how will this technological advance affect both the average end user and the avid enthusiast? This guide will take a look at the history of I/O busses, the basics of PCI Express as well as the implications it will have on the consumer.


Before discussing PCI Express, it is important to understand how far bus technology has come. Back in 1984, IBM shipped its PC AT. The CPU, memory, and I/O bus all shared a common 8MHz clock. This I/O bus became known as the ISA (Industry Standard Architecture) bus. ISA was a 16-bit interface, which meant that data could only be transferred two bytes at a time. More importantly, the ISA bus only operated at 8 MHz and typically required two or three clock signals to transfer those two bytes of data. This was not a problem for devices that were inherently slow (i.e. COM ports, printer ports, sound cards or CD-ROMs), however the ISA bus was too slow for high performance disk access and display adapters. When the ISA bus started running out of steam, other architectures were developed. Unfortunately, the Microchannel (MCA) bus, EISA and VESA Local Bus (VLB) architectures were insufficient and short lived. It was finally the PCI bus that successfully brought the much needed bandwidth to the system.

PCI is a 64 bit interface in a 32 bit package. Figuring this out requires a bit of arithmetic. The PCI bus runs at 33 MHz and can transfer 32 bits of data (four bytes) every clock tick. That sounds like a 32-bit bus. However, a clock tick at 33 MHz is 30 nanoseconds, and memory only has a speed of 70 nanoseconds. When the CPU fetches data from RAM, it has to wait at least three clock ticks for the data. By transferring data every clock tick, the PCI bus can deliver the same throughput on a 32 bit interface that other parts of the machine deliver through a 64 bit path.

While PCI was a savior when it was released, it too has run out of headroom. With faster hard drives, PCI-based sound cards, Ethernet controllers, etc., the PCI bus was beginning to act like New York City during rush hour! A new standard was needed to open up additional bandwidth.

PCI-Express (formerly 3GIO) was a development effort, led by the likes of Intel, to advance the I/O (input output) functionality of today's computers. With the ever greater demand for fast processing and with the CPU being bottlenecked by aging system busses, this development was designed to regain the balance between raw CPU speed and system speed.

Relative Bandwidth

As can be shown in the chart above, one can see the tremendous bandwidth benefits of PCI Express. Note: the 8GB/s shown for PCI Express takes into account full duplex (simultaneous traffic in both directions) operation. One way bandwidth is 4GB/s.

What is it?

PCI-Express is the industry's attempt to unify all of the current different types of I/O bus into a single "future proof" standard. Over the past ten years, PCI has handled the large and varying uses it has been given, most of which were never foreseen when the specification was made. Ports like the AGP, ATA and USB, were developed to cope with data transmissions that needed greater support for time dependant data. Things like video streaming and other real-time applications were not explicitly address in previous PCI specifications (PCI 2.2 and PCI-X included). Current PCI specifications are based on a multi-drop, parallel bus implementation that is coming very close to its performance limits. Those limits that cannot be stretched without spending a large amount of money for very little gain.

Fig1: PCI-Express system topology

PCI-Express takes a leaf out of the book of the LAN and adds a switch to the system topology. The switch replaces the multi-drop bus and is used to distribute I/O messages on a peer-to-peer basis. This means that if one PCI-Express device wants to send data to another, it doesn't necessarily need to go through the chipset (even though the switch may be part of the chipset). This reduces the amount of messages that the chipset has to process itself. Next, from the switch comes PCI-Express links. Each link can contain many 'lanes' making each device link individually scaleable, in turn, adding more bandwidth with the addition of each lane. This is where the term 1x, 2x 4x, 16x etc comes in. Standard add-in cards may be 1x (low bandwidth), graphics cards may be 16x (very high bandwidth), depending on the needs of the cards.

PCI and PCI Express Slots

Next Page
Table of Contents
Page 1: Introduction, Background and What is it
Page 2: What do I get, Cost and when can I get it
Page 3: PCMCIA, FAQ, Summary and Resources

      Posted by: , November 11, 2004, 6:00 pm  

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