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Three dimensional metallization for vertically integrated circuits


Societe Francaise du Vide -SFV-, Paris:
MAM '97. Abstracts booklet
Paris, 1997 (Le vide 283)
S.94-98 : Lit.
European Workshop on Materials for Advanced Metallization (MAM) <2, 1997, Villard de Lans>
Fraunhofer IFT; 2000 dem IZM eingegliedert
integrated circuit interconnections; integrated circuit metallisation; thermal analysis; wafer bonding

The mainstream planar technology is marked by physical and technological limitations, which have a severe impact on the system characteristics. The performance, the multifunctionality and the reliability of microelectronic systems will be mainly limited by the wiring between the IC's and subsystems. The "onchip" wiring also leads to a critical performance bottleneck for future IC generations which can be solved only temporarily by the introduction of additional metallization layers and innovative materials (copper, low- epsilon -dielectrics). 3D IC fabrication creates a basis to overcome these drawbacks and to pave the way for system approaches of an entirely new quality. We realized a three dimensional metallization for Vertically integrated Circuits (VIC) using a newly developed technology that allows stacking and vertical interchip wiring of completely processed and electrically tested wafers using available microelectronic processes. wafers are stacked by an aligned bonding process . Vertical electrical connections are formed between the uppermost metal levels of the bonded wafers by fabrication and metal refill of high aspect ratio interchip vias. This interchip via (ICV) concept allows the formation of multiple wafer stacks using CMOS compatible materials and process steps and avoids backside processes. The potential of the ICV technology is the realization of some 100 000 vertical interconnects per cm-2 with 1-4 mu m2 interchip vias, arbitrarily selectable.