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  2. Wanhedaking

    JTAG Logic Analyzer

    Hello everyone,, Ok, I went down the rabbit hole and am just now coming up for breath! After an epic week long battle that found me obsessed with this one task I have something pretty cool working on the Papilio. Let me start from the beginning, at the end of last week when I was working on the new board design I realized that there might be a huge problem with trying to connect the channel A UART pins from the FT2232 to FPGA I/O pins. I pulled out the trusty Papilio One and tested it out, sure enough, when the Papilio is being programmed all of the I/O pins go to 3.3V which will interfere with the TCK and TDO pins during jtag programming. So the way I had things wired up was not going to work. I started thinking about solutions, adding an IO switch would solve the problem but I'm not super thrilled about doing so. So I started thinking about why we need it connected and it really comes down to being able to use channel A for communications after the FPGA is programmed. Well, we already have an example of doing that, we use the bscan primitive to program SPI Flash... app marketing strategy So I thought, well before I commit to adding an IO switch to the board I should spend a couple days connecting the Sump Logic Analyzer to the bscan primitive so we can use the FT2232 channel A or logic analyzer debugging and use channel B for normal uart communications to our Soft Processor. It's going to be hard to do but I should be able to bang it out in a couple days... Famous last thoughts... Every day I made just enough progress to keep me completely obsessed for the next day, just a little bit more and it will be working... Well it dragged on way longer then I expected but I have a first working prototype! There are still some bugs to squash but it is working well enough to prove that we can use channel A for debugging and there is no need to add an IO switch to the new board
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  5. Hi there, i would like to reuse some of the Papilio Wings i bought over time (in particular i'm looking to reuse the Audio Wing BPW5020 this time around). Do anyone know where i can find the schematics for this wing? Has anyone ever tried to build a Papilio Wing to PMOD converter? Or any other "generic" bridge?
  6. ameetgandhare

    Bitcoin Miner Library

    Hello, Please let me know where can I get the Bitcoin Miner Library. -Regards, Ameet Gandhare
  7. mkarlsson


    ISE on Win10 is broken and wont work unless you takes a few steps. See this post:
  8. Michael Baseman


    I have Papillo Duo with Spartan 6 and I'm trying to get ISE to recognize the board. Each time I start ISE and click New Project, the app shuts down. It doesn't brick or stall, it just closes. Any ideas on how to fix this?
  9. AirPods Apple

    Mojo 3 or Papilio Duo as an entry level dev board?

    The Mojo v3 and Papilio Duo both use the exact same FPGA. There is no meaningful difference in their I/O capabilities. There are some differences in their peripherals, and they almost all point in favor of the Papilio: The Mojo v3 uses the AVR microcontroller to program the FPGA, as well as for communications with the FPGA. This is a bit strange, and locks you into using Mojo-specific tools for programming. The Papilio has a FT232H for programming and communications; the AVR is separate. This allows you to use more standard tools. The Papilio has a pretty large (512 or 1024 KB) external SRAM chip. The Mojo v3 has no external memory; you're limited to the 576 Kbit (~64 KB) block ram available on the FPGA. (There is an expansion board available, but it's kind of expensive.) The Papilio has an Arduino-compatible pinout. The Mojo v3 does its own thing. The Mojo v3 has a few more LEDs. So there's that, I guess. 9Apps Cartoon HD Vidmate APK
  10. mkarlsson

    SRAM timing

    Looks like you have the polarity of /OE wrong - it should be high when writing and low when reading. Magnus
  11. DJohn

    SRAM timing

    Answering my own question. Don't put stuff outside the process unless you want it to be horrible and glitchy. The simulation shows nice in-spec signals, but in reality it was getting occasional glitches that my logic analyser was having trouble seeing. It's still not working, in ways that I don't really understand, but at least I've got something to go on now.
  12. DJohn

    SRAM timing

    I have a 2MB Papilio Duo (Kickstarter edition), with the Classic Computing shield, that I'm using for my first serious FPGA project. I'm using it as a simple FPGA board, so not using the Arduino side, and doing everything myself in VHDL. I've run into a problem writing data to the SRAM. My design uses 4 cycles of a global clock for each memory access. Writes go like this: /OE <= 0, /WE <= 1, set address, tristate data /OE <= 0, /WE <= 0, assert data to write wait /WE <= 1 My test configuration follows this with a read: /OE <= 1, set address, tristate data wait read data wait Unless I've made a mistake (spoiler: I have almost certainly made a mistake), with a 160MHz global clock this should fit comfortably in the SRAM's timing requirements. At 80MHz it works fine. At 128MHz it's OK most of the time, with occasional errors. At 160MHz it's failing very frequently. I'm fairly sure that it's the writes that are failing: when it's connected to a larger design that copies a ROM into RAM and then displays the contents of RAM on VGA, I get a stable image with missing pixels here and there. But I can't see what I'm doing wrong. Can anyone help? I'll attach my stripped-down SRAM testbed. I'm very new to VHDL, so comments on style are welcome too. I'm probably doing everything wrong. LED1 blinks briefly when the data read back from SRAM doesn't match the data that was written. sram_test.ucf sram_test.vhd
  13. mkarlsson

    Unable to program FPGA on Duo

    No need to use the Oracle VM to run ISE on Win10, just follow these steps: 1) Install ISE14.7 for Windows (Embedded Edition) on your Win10 computer 2) Go to C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 (assuming 64-bit Win10) and rename libPortability.dll to libPortability_orig.dll 3) Make a copy of libPortabilityNOSH.dll and rename it libPortability.dll 4) Go to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 and rename libPortability.dll to libPortability_orig.dll 5) Copy libPortability.dll from C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 to C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64 6) Run ISE and install your license file etc. You should now have a working version of ISE on your Win10 computer. Magnus
  14. Kelly45324

    Unable to program FPGA on Duo

    Papilio Duo. Have Windows 10, for which the only ISE available is a virtual machine that runs on Oracle VM. I can run designLab on Win 10 and it will load AVR programs, but not FPGA. I cannot figure out how ISE on the VM would communicate with the DesignLab on Win 10. I have tried that VM, and cannot seem to get it to talk to the host machine USB interface. (some kind of libftdi problem) Can run DesignLab on Win 10 - but it won't load to the FPGA/ZPUino. Ran Windows 7 as a VM - it also will not talk to the USB-just hangs during upload. Has anyone found a combination that works for Windows 10, and allows FPGA to be loaded, (even just the Duo Quickstart example)?
  15. I have three Papilio Duo's 512k MB model and am unable to program the new one I have just received. When attempting to program the new Duo, Papilio loader displays "Could not read USB" message. The new papilio duo also does not show in device manager while the other boards do with the same cable and USB port used. I believe the issue to be with the new board I have just received as I have programmed many boards prior.
  16. benediktsch

    Logic levels from HardwareSerial

    Another Problem I found is, that the UART is dropping bytes in the beginning or at the end of a transmission randomly. Even thou everything is transmitted from the other Papilio Board. I just read data in my loop and print it, after it was transferred, so I don't really think I can make the program any shorter.
  17. benediktsch

    Logic levels from HardwareSerial

    Hello together, I was trying to get three HardwareSerials working on the DUO Board. When I was watching at the signals with my Logic Analyzer only the second UART seems to work fine. But as you can see in the attached image it seems like the first UART (Channel 0) is also sending data, but on a Logic Level of something around 0.35Volts. So why isn't this working like the second one, but going from low to high instead of from high to low and has such a low logic level? I also tried initalizing the Serials like in the given example withe the Wishbone Slot inserted, but I guess this got outdated in v2.0. Edit: In the schematic the TX RX are: SerialRed : RX = Arduino_0 ; TX = Arduino_1 SerialGreen : RX = Arduino_2; TX = Arduino_3 SerialBlue : RX = Arduino_4; TX = Arduino_5 I also tried using other PINs than the ones above but everywhere seems to be the same issue. This is my Code: HardwareSerial SerialRed(2); HardwareSerial SerialGreen(3); HardwareSerial SerialBlue(4); void setup() { Serial.begin(115200); delay(50); SerialRed.begin(57600); delay(50); SerialGreen.begin(57600); delay(50); SerialBlue.begin(57600); } void loop() { SerialSendData(TData); delay(1000); } void SerialSendData(uint8_t TData[3072]) { SerialRed.write(startsequence); for (int i = 0; i < 1024; i++) { SerialRed.write(TData[i]); } Serial.println("Red transmit"); SerialGreen.write(startsequence); for (int i = 1024; i < 2048; i++) { SerialGreen.write(TData[i]); } Serial.println("Green transmit"); SerialBlue.write(startsequence); for (int i = 2048; i < 3072; i++) { SerialBlue.write(TData[i]); } Serial.println("Blue transmit"); SerialRed.write(setFrame); SerialGreen.write(setFrame); SerialBlue.write(setFrame); }
  18. Brad Robinson

    Papilio Loader GUI

    For anyone who just wants the command line tool for linux x64, you can grab it here. To use it: 1. Extract to somewhere 2. Either add that somewhere to your path or create symlink in your path Run papilio-prog as usual. Also, I've made a small improvement. To burn to SPI instead of having to specify -b and the name of the appropriate bscan_spi_*.bit file, you can just specify "-b auto" and it'll work it out using the same approach as the GUI tool. eg: papilio-prog -f yourbitfile.bit -b auto -sa -r -v
  19. mdavidjohnson

    Wings & Megawings with Duo

    I just purchased the Duo 2MB + LogicStart Shield Combo. Two questions: 1. Which wings and megawings (if any) can I use with the Duo? 2. When (if ever) do you expect the Computing Shield to be back in stock?
  20. FIssiki

    Can't Write to SPI Flash

    I am also experiencing problem in writing SPI flash of Papilio Pro now, nevertheless it was all OK until April 10, a week ago. Writing to FPGA is still working correctly. The full log output on Papilio Loader 2.8 (on Windows 7) is: -- JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "C:\Program Files\Gadget Factory\Papilio Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0x79c7e6969e763cff Done. Programming time 1051.1 ms Programming External Flash Memory with "C:\FPGA\TimingMeas1\timingmeas1.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ......Ok Verifying : ...Error in Verify: first byte of data [0x00] .. Failed (@ Page: 515) Using devlist.txt Error occured. USB transactions: Write 709 read 541 retries 0 JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt ISC_Done = 1 ISC_Enabled = 0 House Cleaning = 1 DONE = 1 -- The strange points of those errors are that the page numbers of the error positions are changing every time, like: [ The 1st time ]: Failed (@ Page: 515) [ The 2nd time ]: Failed (@ Page: 936) [ The 3rd time ]: Failed (@ Page: 257) I hope those errors are not due to broken hardware. ======== [p.s. (April 22)] As far as I found having retried in various ways, it seems Windows 7/10 update around April 10-14 made bad effects on USB communication, since the log output on Papilio Loader was rarely like: -- Programming External Flash Memory with "C:\Users\Desktop\timingmeas1.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ....Error: SPI Write Check Status Register [0xFF] mismatch (Wrong device or device not ready).. ..Ok Verifying : Using devlist.txt .Error in Verify: first byte of data [0x00] .. Failed (@ Page: 39) Error occured. USB transactions: Write 234 read 66 retries 0 JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt ISC_Done = 1 ISC_Enabled = 0 House Cleaning = 1 DONE = 1 -- ..., showing the error was caused in "Partial Erase" phase, meaning USB communication errors are happening everywhere. This USB communication bug might be affected by Windows update, and can be found in an other person's tweet on Apr 14 (in Japanese), ..., meaning there are some strange points in FTDI VCP communication. My two Papilio Pro boards became unavailable with Papilio Loader now. I am wondering if I could use other JTAG tools to write flash without damaging the Papilio Pro boards.
  21. Hey All, I'm wondering if there's any plans for future development of the Papilio range of boards? I'm a big fan of Papilio Duo with the Classic Computing Shield - it's got everything I need for my typical projects which is primarily old retro machine emulation. Recently however I've become interested in playing around with some of the newer Xilinx chips (and perhaps the Intel/Altera FPGA's) but I'm having a hard time finding development boards like the Papilio with everything baked in: onboard RAM, SD card, VGA (or HDMI) output, audio output, PS2 etc... I guess this post is just wishful thinking, but curious if there's anything in the pipeline. Brad
  22. Vector22

    Can't Write to SPI Flash

    As my first project using the Papilio Pro and LogicStart MegaWing, I made LEDs turn on from the switches. When I use the Papilio Loader 2.8 to write to FPGA, it executes fine and I am able to turn on the LEDs. When I try to write to SPI Flash, however, it times out and displays the following error message: readusb: Timeout readusb terminate called after throwing an instance of 'io_exception' What am I doing wrong? Full Output: JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Using devlist.txt JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "C:\Program Files (x86)\Gadget Factory\Papilio Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0x39bd53c11674cfff Done. Programming time 698.6 ms Programming External Flash Memory with "C:\Users\Jay\Desktop\ISE_Projects\Switches_LEDS\Switches_LEDS.bit". Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits). Erasing : Doing Partial Erase ......Ok Verifying : ......Pass Programming : ......Ok Verifying : Using devlist.txt ......Pass Done. SPI execution time 17465.5 ms USB transactions: Write 6853 read 6684 retries 0 Using devlist.txt readusb: Timeout readusb terminate called after throwing an instance of 'io_exception'
  23. Funny enough, but the LED's have 330 ohms limiting resistors, but not the 7 segment., at least this is what I see on the Megawing schematic.. I checked the 7 segment notice, so it is said 20 mA, and 2.1 V typical, but nothing about a limiting resistor, which is always good to have in my opinion. I don't know why Jack did not provide these... Anyway, when I use a LED (anyone) with an ARDUINO, it is always safe to have a limiting resistor (330 ohms if you wish a bright glow, but 1 k should do the trick). More important: ARDUINO provides 3.3 or 5 V, so be sure not to overload the Megawing! Have fun. Gerard.
  24. Hi all, I have 2 question about 7 segments on Logic start Megawing: First: some segments are always "on", even if I do not use them (not always the same). I suppose that the FPGA pins are in some "random" state and that this could give some lighted segments. Also to light the segments, the anodes must be in a "high" state. I could switch them off in the code, but this is not a very elegant solution. Is it possible (for instance in the UCF file) to declare these pins as logical zero, or to say that the anodes (AN0...AN3) are to ground, so as to block the +3.3V supply? Second: in the schematics, the decimal points are on the bus and appear on the pins. But the colon and Apos are on the bus but do not appear on pins. Is there a possibility to light them? Thanks a lot for your help. Gerard.
  25. Hello everyone,, I got my Papilio DUO the other day and have been playing around with. Let me say I really like what I see. I only had a couple issues(drivers but got fixed), less than most development boards I have used. My main project for buying the DUO was for 3d printing. As I mentioned in an my intro post I think the DUO is a great platform for this. I have started working on splitting up the Teacup firmware for arduino. I put together a small document with my ideas on how a 3d printing firmware might work on the DUO. Looking fo﻿r others thoughts especially on the FPGA side of things as I am just starting out learning that side. Feel free to chime in on any thoughts. I broke it down into 2 phases just to make the coding a little easier on my end. The 1st phase is just moving all the motion planning and control over to the ZPUino. The later phase will be the better stuff, moving the stepper control out of the ZPUino and just plain fpga, but leaving the motion planning on the One of the areas I am especially looking for some input is how to bridge the atmega32U4 to the ZPUino. I need to send data (positions for each axis, estop, etc) to the ZPUino and possibly request data in return (current position) from also. My first thought is something like SPI or I2C over some of the shared pins. I would love to hear if there are some easier or faster or more efficient approaches. Another item I am looking for some feedback is in the Phase 2 area. I showed two possible configuration for how I think it might be done. Any feedback on those would be appreciated also.
  26. Hello everyone,, I recieved my LogicStart today so as I have a few hours spare I thought I'd get cracking wth Hamster's PDF of tutorials and info. I've just finished making a 4 bit adder using the swithces and LEDs of the board and would like to know if my code looks right. It seems to work.. From right to left, the switches in 2 groups of 4 seem to add up all the way to 15. The code is here: entity switches_leds is Port ( switches : in STD_LOGIC_VECTOR(7 downto 0);LEDs : out STD_LOGIC_VECTOR(7 downto 0));end switches_leds;architecture Behavioral of switches_leds issignal x : STD_LOGIC_VECTOR (3 downto 0);signal y : STD_LOGIC_VECTOR (3 downto 0);signal carry : STD_LOGIC_VECTOR (3 downto 0);signal result : STD_LOGIC_VECTOR (4 downto 0);beginLEDs <= "000" & result;x <= switches (3 downto 0);y <= switches ( 7 downto 4 );result(0) <= x(0) XOR y(0);carry(0) <= x(0) AND y(0);result(1) <= x(1) XOR y(1) XOR carry(0);carry(1) <= (x(1) AND y(1)) OR (carry(0) AND x(1)) OR (carry(0) AND y(1));result(2) <= x(2) XOR y(2) XOR carry(1);carry(2) <= (x(2) AND y(2)) OR (carry(
  27. Oskar STEPIEÑ

    Place:1108 in a XC6SLX16-CSG324

    Hi Magnus, I had some issues with some codes, but looking through other codes, I noticed the problem. I don't remember why using posedge on a button was a good idea in my head. Anyways, thanks a lot. I have fixed the issue the tuesday afternoon. Oskar
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