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Intel Corporation culminated the transition to the company’s award-winning “Nehalem” chip
flexible and reliable. Expandable to include from two to 256 chips per server, the new Intel Xeon
features. Nehalem-EX is Intel’s fastest processor to date, however, clock speeds are still mystery
but the company has said it will include 24MB of cache, and 2.3 billion transistors. The new
processor will be targeted for high-end servers especially to Cloud computing farms and one of
the first implementers would be IBM. Apart from that, the new architecture have some advanced
error-recovery mechanisms like MCA as far as the fabrication is concerned, it would use 45-
nanometer process, however, 32nm is very much work-in-progress.



industry’s migration away from proprietary architectures
Each combination of a Nehalem/Westmere processor die and package has both a separate
codename and a product code. Typically, the same dies are used for uniprocessor (UP) and dual-
processor (DP) servers, but using an extra Quick Path link for the inter-processor communication
in the DP server variant. Like the Core microarchitecture, Nehalem also uses four different
processor packages, one for each market segment. The high-end chips with eight cores are only
available in the MP server segment, while all others are used in at least two different packages.


Intel is also including new technologies like Machine Check Architecture (MCA) recovery error
correction that could make servers more fault tolerant and provide greater uptime. This added
capability is brand new to the Nehalem product family and will help businesses lower their total
cost of ownership. With MCA Recovery, errors can be isolated on a virtual machine and the
other machines can still run uninterrupted while that one is being restarted. The processor will be
working with the operating system. Intel will also offer four memory channels per processor,
simply said more channels provide more memory bandwidth to run programs faster. AMD‘s 12-
core Opteron server processors also offer same memory channels. But, Intel will build large
but AMD‘s Magny Cours beats Nehalem-EX when it comes to more physical cores per chip.

Intel started mass producing 45 nm chips in late 2007, and AMD started production of 45 nm
completed a common 45 nm process platform. Many critical feature sizes are smaller than the
wavelength of light used for lithography (i.e., 193 nm and/or 248 nm). A variety of techniques,
introduced by Intel to assist in shrinking distances between features, especially if dry lithography
difficulties with 193 nm photoresists.
Double Data Rate DDR memory controllers are used to drive DDR SDRAM, where data is
transferred on the rising and falling access of the memory clock of the system. DDR memory
controllers are significantly more complicated than Single Data Rate controllers, but allow for
twice the data to be transferred without increasing the clock rate or increasing the bus width to
the memory cell. Dual Channel memory controllers are memory controllers where the DRAM
devices are separated on to two different buses to allow two memory controllers to access them
in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more
channels can be built (a channel for every DRAM cell would be the ideal solution), but due to
wire count, line capacitance, and the need for parallel access lines to have identical lengths, more
channels are very difficult to add.


Fully buffered memory systems place a memory buffer device on every memory module (called
an FB-DIMM when Fully Buffered RAM is used), which unlike traditional memory controller
devices, use a serial data link to the memory controller instead of the parallel link used in
previous RAM designs. This decreases the number of the wires necessary to place the memory
devices on a motherboard (allowing for a smaller number of layers to be used, meaning more
memory devices can be placed on a single board), at the expense of increasing latency (the time
necessary to access a memory location). This increase is due to the time required to convert the
parallel information read from the DRAM cell to the serial format used by the FB-DIMM
controller, and back to a parallel form in the memory controller on the motherboard. In theory,
the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for
memory cell agnostic memory controller design, but this has not been demonstrated, as the
technology is in its infancy.

20 lanes when all 20 lanes are available or on 10 or 5 lanes when the QPI is reconfigured due to
a failure. The link layer is responsible for sending and receiving 80-bit flits. Each flit is sent to
coherence. In complex implementations of the Quick Path architecture, the link layer can be



minimize planned downtime.

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