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DMC_400 component

This section describes the DMC_400 component.

DMC_400 - about

This LISA+ component is a model of the ARM® CoreLink™ DMC-400 Dynamic Memory Controller. The configuration of this model, by setting the registers, does not generally affect accesses to main memory.

DMC_400 contains the following CADI targets:

  • DMC_400

DMC_400 contains the following MTI components:

DMC_400 - ports

This section describes the ports.

Table 4-54 DMC_400 ports

Name Protocol Type Description
apb_interface PVBus Slave Slave bus interface for register access
axi_if_in[4] PVBus Slave Slave bus for connecting to bus decoder
axi_if_out[4] PVBus Master Master to connect to DRAM

DMC_400 - parameters

This section describes the parameters.

Table 4-55 DMC _400 parameters

Name Type Allowed values Default value Description
diagnostics int 0-4 0 Report diagnostics, with increasing detail as the setting increases.
ECC_SUPPORT bool true/false true Changes the reset values of the ECC-related registers.
IF_CHIP0 int -1, 0 -1 0 if port axi_if_out[0] connects chip 0 to RAM, -1 if not.
IF_CHIP1 int -1, 0 -1 0 if port axi_if_out[1] connects chip 1 to RAM, -1 if not.
IF_CHIP2 int -1, 0 -1 0 if port axi_if_out[2] connects chip 2 to RAM, -1 if not.
IF_CHIP3 int -1, 0 -1 0 if port axi_if_out[3] connects chip 3 to RAM, -1 if not.
MEMORY_WIDTH int 16, 32, 64 32 Memory width in bits.
revision string r0p1, r1p0, r1p1, r1p2 r0p1 Sets the peripheral ID registers to correspond to the given revision, and also changes the permitted ranges for some of the timing registers because they changed between revisions.

DMC_400 - registers


This component has no timing information, so changing the values of the timing registers has no effect on behavior. The memory models do not attach to the component, and error checking does not update registers because the model does not include the possibility of errors.

DMC_400 - verification and testing

This component passes checks of the reset values for the registers against the TRM, as part of automated tests of a development system model.

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