Jump to content

All Activity

This stream auto-updates     

  1. Today
  2. Last week
  3. Eyck

    bind multi ports to other port.

    Another option would be to use a resolved signal and connect all output ports to it. But this is already about techincal implementation options. The question to me is: what would you like to model? Is this the right way to model the intend? Best regards
  4. maehne

    bind multi ports to other port.

    sc_core::sc_in<T> only allows binding of a single sc_core::sc_signal<T> (cf. to IEEE Std 1666-2011, clause 6.8). However, you may use for in_B a sc_core::sc_port<sc_core::sc_signal_in_if<T>, 3, SC_ONE_OR_MORE_BOUND> (cf. to IEEE Std 1666-2011, clause 5.12) that will accept binding of exactly three signals. The implementation of the OR relation of the three signals can be then handled inside an SC_METHOD of objB. To access the three different signal from in_B, you can use the operator[] implemented by the sc_port. By the way, you may also specify a different number of channels to be bound and also a different port binding policy.
  5. Hi all, I have 2 models, model A and model B Model A has an output port out_A (bool) Model B has an input port in_B (bool) when integrate, I will instance 3 objects of Model A, 1 object of Model B //file @connection.cpp ... void initializeENV(){ ... objA_1 = new ModelA("objA_1"); objA_2 = new ModelA("objA_2"); objA_3 = new ModelA("objA_3"); objB = new ModelB("objB"); ... } the value of in_B = objA_1->out_A or objA_2->out_A or objA_3->out_A I think that, if I bind as below . It is wrong. Because of when objA_1->out_A is change then affect to obj_2->out_A and objA_3->out_A. Is my understand correct? //file @connection.cpp ... sc_signal<bool> sig_1; sc_signal<bool> sig_2; sc_signal<bool> sig_3; void initializeENV(){ ... objA_1 = new ModelA("objA_1"); objA_2 = new ModelA("objA_2"); objA_3 = new ModelA("objA_3"); objB = new ModelB("objB"); objA_1->out_A(sig_1); objA_2->out_A(sig_2); objA_3->out_A(sig_3); objB->in_B(sig_1); objB->in_B(sig_2); objB->in_B(sig_3); ... } How to resolve it? How to bind 3 out_A ports to in_B port? .I can't use SC_METHOD in this case. Thank all.
  6. OK, I see, thanks. So the guideline is using TLM like way(Pure function call, no SystemC schedule related) to carry signals when using quantum, right?
  7. You have controversial requirements: a) put stored value when enable == 1 , which sounds like a dff with output_enable b) put input to output when enable == 1, which sounds more like a latch Anyway, in both cases you will need to make process sensitive to enable signal. And usually such low-level logic is modeled with SC_METHODs. In SystemC context "register" usually means some memory-mapped CSR on TLM bus 🙂
  8. I mean like an output register which can save a value for one clock cycle and than put the value on its output if the enable signal is high. and what do you mean by we can model a register in anyway we want? or do you mean if I make SC_THREAD sensitive to clock pos edge and than get an enable signal as an input to SC_THREAD and make an if condition if enable signal is high output = input than it will behave like a register and yes I am working with non-synthesizable high level model and just running systemC from command line as presented in forte design system series on youtube.
  9. What do you mean exactly by "modeling a register"? If you are working on synthesizable code (i.e. using Mentor/Cadence HLS tools), then it is not possible to have 0-delay communication between threads in synthesizable code, as you wanted in original post. At least it was not possible last time I've used these tools. If you are working on some non-synthesizable high-level model, then you can model "register" any way you like, you don't even have to use sc_signal<> for that purpose.
  10. Thank you very much for your helpful answer. Now I am trying to use SC_THREAD but confuse in one thing that how can I model a register in SC_THREAD. Because I know that if we declare a variable in SC_CTHREAD as sc_signal than it is modeled as a register but how can I do that in SC_THREAD. I can make SC_THREAD sensitive to a positive clock edge and a reset but I do not think that will model the registers where I want them.
  11. Earlier
  12. If you want immediate communications between threads, then you should use regular SC_THREADs and wait on event, like wait(some_signal.value_changed_event());
  13. You have 2 clocked processes. Any communication between them will take at least 1 clock cycle. If you need request and response, then you have at least 2 cycle latency.
  14. I am trying to model a direct mapped cache and there is main memory module which is an SC_CTHREAD and main memory state machine which also SC_CTHREAD. I am experiencing one clock cycle delay when I write to an output from main memory and read it from main memory state machine. But i thought i could read in the same clock cycle isnt it true?
  15. Can you add delete _scv_tr_stream﻿_core_p; at the end of the scv_tr_stream destructor in scv_tr.cpp, starting at line 736 and report if this solves the issue?
  16. the original compare_field_int() is plan to bit size <=64, you can use compare_field() instead.
  17. Well, your interrpt is set in a SC_THREAD or SC_METHOD and these are active when the ISS thread sleeps. In that sense the sensing is immediate when the ISS thread wakes up. But since the ISS thread is ahead of the SystemC simulation when the irq is activated in SystemC there is no way to have an immediate sensing. This is the accuracy you give up to gain simulation speed: the delay until the ISS acts on an external event is determined by the quantum. On solution could be to use a dynamic quantum which changes in the course of the simulation: you start with a large quantum until you reach a certain point in simulation (e.g. until you booted the system) and then you lower the quantum to get more accuracy.
  18. It seems scv_tr_stream destructor forgets to delete the pointer '_scv_tr_stream_core_p' which is allocated in its constructor. AddressSanitizer could capture this issue.
  19. For solution 2 "if your CPU writes into the register of your interrupt controller via TLM it carries the delay which is essentially the offset of the CPU local time to the SystemC kernel time. If you here just break the quantum and call a wait() so that the SystemC kernel can sync up and the signal change propagates", what if this interrupt is cleared by other models instead of my CPU model? How my CPU model can sense the external signal change(Interrupt value change) immediately?
  20. Frank Poppen

    Initial value port

  21. Philipp A Hartmann


    Hi Khushi, just adding to Eyck's answer, the "default" extensions in SystemC 2.3.3 are the following two implementation defined classes: tlm::tlm_endian_context tlm_utils::instance_specific_extension_carrier Greetings from Duisburg, Philipp
  22. Each type of extension has an automatically assigned ordinal number which is available per extension as ID in the base class tlm_extension. So in your case you have 2 tlm_extensions defined somewhere. Under the hood this ID is used as an index into the m_extension array of the tlm::generic_payload. Best
  23. based on your defined data_item, your monitor implementation is incorrect. the monitor shall sample the sample the in signal and than sample the corresponding out signal, give the encapsulation the two value in a data item, send it out.
  24. you can use the one monitor for the dut input and output. And i think the root case is not base on how mant input/ouput of dut you have, but the interface type the dut have. for exanple, if you have one axi input and one aix output, you can use one monitor to collect all input/outout axi transaction. So i think the number monitor is based on the types of interfaces.
  25. as you define a domain1 phase with the run_phase, so when the run_phase complete, extract phase will scheduled for last phase to run. at the same time, the domain1 phase also complete and schedule extract phase to next to run. So the there two phase to printed. for your second question, the run phase schedule extract phase and the domain1 phase schedule final phase and clean the pahse runining before the final so final phase run once.
  26. Hi I am trying to understand the max_num_extension() return value. When I create a payload object and use set_extension and then call max_num_extensions(), then it returns 2. I tried to debug and noticed that even if we didn't have any module, it still gives 2. The following piece of code prints 2. why it is so ? //#include "top.hpp" #include "tlm.h" #include "systemc.h" int sc_main(int argc, char** argv){ std::cout<<tlm::max_num_extensions()<<std::endl; sc_start(); return 0; } LRM@496 syas "The function max_num_extensions shall return the number of extension types, that is, the size of the extension array. As a consequence, the extension types shall be numbered from 0 to max_num_extensions()-1". Thanks Khushi
  27. Thanks. I was following the examples/tlm/lt_temporal_decouple example in SystemC package and there the global quantum is set in initiator constructor instead of main. This is why I asked this particular question whether the initiator is allowed to set the global quantum. May be we can update this example to put the global quantum setting in sc_main. Thanks Khushi
  28. sas73

    Cause of UVM Timeout

    @Taichi Ishitani That would certainly narrow the scope a bit but I would hoping for something that would pinpoint the wait statement. Is there a instrumentation mechanism in place? That would require me to add code manually but it would also be useful for other scenarios, for example to locate a loop that is stuck.
  1. Load more activity