def alterDataBit(bit, state):
 global dataReg
 if (state == 0):
  dataReg = (dataReg & (~ (2 ** bit)))
 else:
  dataReg = (dataReg | (2 ** bit))
 port.DlPortWritePortUchar(baseAddress, dataReg)

def alterDataBit ( bit , state ) : global dataReg if ( state == 0 ) : dataReg = ( dataReg & ( ~ ( 2 ** bit ) ) ) else : dataReg = ( dataReg | ( 2 ** bit ) ) port . DlPortWritePortUchar ( baseAddress , dataReg )
toggle any data register bit to the state given .