def pportD7(state):
 global dataReg
 if (state == 0):
  dataReg = (dataReg & (~ 128))
 else:
  dataReg = (dataReg | 128)
 port.DlPortWritePortUchar(baseAddress, dataReg)

def pportD7 ( state ) : global dataReg if ( state == 0 ) : dataReg = ( dataReg & ( ~ 128 ) ) else : dataReg = ( dataReg | 128 ) port . DlPortWritePortUchar ( baseAddress , dataReg )
toggle data register d7 bit .