1. Introduction {#sec1}
===============

Multilevel inverters have generally functioned as an AC voltage synthesizer to create a quasi-sinusoidal voltage i.e., rough sinusoidal waveform with desired steps using several DC power supplies \[[@bib1]\]. Hence, high number of switching components has let the multilevel inverter to render a quasi-sinusoidal voltage with high quality \[[@bib2]\]. The first multilevel inverter prototype has been constructed and analyzed by Nabae et al. \[[@bib3]\]. Since that time, these structures have been captivating more industrial and academic consideration in the various medium voltages that such these multilevel structures have investigated in several literatures to elucidate the rating problem related to voltage and current of switching components \[[@bib4], [@bib5], [@bib6], [@bib7], [@bib8]\].

One of the strongpoints of these structures other than creating a pertinent quasi-sinusoidal waveform is their feasibility to occupy them in transmission and sub-transmission levels for such these reasons: reduction of SPL, PIV, dV/dt and EMI \[[@bib9], [@bib10], [@bib11]\]. One more special strongpoint of these structures is their capability in harmonic alleviation, avoiding the high frequency of semiconductors\' switching either reduction of the inverter\'s output power \[[@bib12], [@bib13], [@bib14]\].

Multilevel inverter is known as one of the most advanced and prominent power electronic structures. They have been widely applied in manifold compensators and energy conversion systems e.g., HVDC, FACTS, PV, UPS and Industrial drive systems. The conventional multilevel inverters have been essentially divided into three categories that are CHB, NPC, FC \[[@bib15], [@bib16], [@bib17]\]. It is worth mentioning that, the conventional multilevel inverters have borne high switching elements such as: switches, capacitors, diodes and the suchlike toward producing high step number. Over the past several years, many different structures and technologies based on IJBT and MOSFET semiconductors with have been introduced \[[@bib18], [@bib19], [@bib20], [@bib21]\].

Apart from the beneficial advantages of multilevel inverters, existence of a large number of semiconductor switches is their most important disadvantage that consequently will bring such detriments: complexity of the circuit and control strategy, increase of the structure\'s cost-price, decrease of the reliability, and maintenance of the structure. Therefore, it is essential that the number of switching components to be decreased. Across the world, the scholars are attempting and venturing to improve and introduce high performance multilevel inverters with reduced components so that the aforementioned problems related to the conventional multilevel inverters to be obviated e.g.: \[[@bib22], [@bib23], [@bib24], [@bib25], [@bib26]\]. Such the reduced multilevel topologies have generally competed with each other over the: low THD, and number of switching components as well as high-step of quasi-sinusoidal voltage, in which case, an inventive AMLI has been designed and introduced in this paper so that not only low number of components to be applied, but also high-step quasi-sinusoidal voltage to be attained. The proposed sub-AMLI has been designed based on the ladder capacitor clamped to H-bridge by means of the bi-directional switches. Based on an innovative geometric progression for DC power supplies of AMLI, it can operate as so-called odd-nary AMLI. In recent years, the power electronics experts have been endeavoring to enhance the conventional multilevel inverter structures and voltage quality. Therefore, undesirable voltage harmonics of multilevel inverters with DC power supplies can be reduced by the advantageous modulation strategies such as PWM and SVPWM \[[@bib27], [@bib28]\].

It should be considered, these strategies cannot accurately reduce the relevant harmonic components. Another strategy has been functioned in accordance with selection of the triggering angles to reduce the lower order harmonics viz. third, fifth, seventh from the quasi-sinusoidal voltage which is recognized by SHE \[[@bib29], [@bib30], [@bib31]\]. A principal problem as regards of such these strategies is acquiring the arithmetic solution of nonlinear transcendental equations which include the trigonometric clauses. These relationships can be also solved by iterative methods including Newton--Raphson \[[@bib32]\]. Unfortunately, its dependency on the initial estimation points may cause trapping in local optima. Therefore, this approach can\'t be considered to unravel the SHE problem with various triggering angles whereas have no initial estimation points. One more strategy has been operated via converting the transcendental equations into the polynomial equations \[[@bib33], [@bib34]\]. If the step number of voltage to be increased, the computational burden is highly intensified. As for the capability of heuristic algorithms in solving the complex objective functions, they have been widely used to figure out the optimal triggering angles.

Toward this subject, PWM-based scission-style harmonic elimination has been designed and implemented to enhance voltage quality of AMLI. Hence, three prominent criterions related voltage quality i.e., desired fundamental component, elimination of third harmonic and Reduction of THD have been assigned as objective functions of optimization problem. Considering the multi-objective nature of the optimization problem, non-dominated sorting MOGWO has been implemented to solve the optimization problem, and then compared with NSGA-II. To sum up, the relevant analytical studies along with both the simulation and experimental results have transparently validated the performance of suggested AMLI. Also, the voltage quality problem using MOGWO-based scission-style harmonic elimination strategy has been well approved.

2. Suggested odd-nary multilevel inverter {#sec2}
=========================================

A new AMLI structure is proposed aimed to provide high-step quasi-sinusoidal with respect to few switch numbers. Suggested AMLI can feasibly act as both the symmetric and statuses. According to the [Figure 1](#fig1){ref-type="fig"}, sub-AMLI is composed using DC power supplies, capacitors along with unidirectional and bidirectional semiconductor switches. By cascading of these sub-multilevel inverters the overall construction of the proposed AMLI is revealed. The relevant components utilized in suggested AMLI are given as follows:$$N_{\text{uni-directional}} = 4.N_{Source}$$$$N_{\text{bi-directional}} = \left( {k - 1} \right).N_{Source}$$$$N_{\text{Switch}} = N_{\text{uni-directional}} + 2N_{\text{bi-directional}} = 2\left( {k + 1} \right).N_{Source}$$$$N_{\text{capacitor}} = k.N_{Source}$$Figure 1(a). Proposed cascaded multilevel inverter. (b). Prototype\'s photograph of suggested AMLI.Figure 1

Having said that, Based on an innovative geometric progression for DC power supplies with different ratios a pertinent sinusoidal voltage with uniform step has been provided. Both symmetric and asymmetric operations of suggested structure have been explained in detail in as follows.

To confirm the suggested AMLI concept, 25-level quasi-sinusoidal of [Figure 1 (a)](#fig1){ref-type="fig"} has been constructed and analyzed. Todd-nary AMLI can provide staircase sinusoidal voltage with maximum of 120 V on the output. For this case, a single-phase resistive-inductive load is considered as the test load with R = 170 ^Ω^ and L = 400 ^mH^.

The prototype\'s photograph has been provided and also presented in [Figure 1](#fig1){ref-type="fig"}(b). The prototype AMLI has been constructed by BUP403 (600 V, 42A) IGBTs as switching devices, IRS2113 as IGBT driver, and BYW (56 V) as fast-recovery diodes. The IC ATMega 64 microcontroller by ATMEL Company has been utilized in order to create the triggering scheme."

2.1. Multilevel symmetrical status {#sec2.1}
----------------------------------

Based on the formation of bidirectional switches, capacitors and module numbers accompanied by particular switching operation the quasi-sinusoidal voltage with requires steps can be provided. In symmetrical operation, the values of DC power supplies are equal in symmetric status i.e., V~dc~. It is obvious that the steps of quasi-sinusoidal voltage will be increased by adding bidirectional semiconductor switches along with capacitors, and subsequently with cascading them. In accordance with the triggering of the switches\' gates as well as the arrangement of components, different voltage levels are created. Sub-structure can be designed based on essential components, while, one bidirectional switch along with two capacitors (k = 2) provides five levels, two bidirectional switches along with three capacitors (k = 3) provides seven levels and in the same way k-1 bidirectional switch along with k capacitors provides 2k+1 levels. For better understanding, the switching strategy considering: two capacitors for each sub-structure and two sub-structure modules i.e. k = 2 and n = 2 are tabulated in [Table 1](#tbl1){ref-type="table"}. The output voltage of each module accompanied by overall output voltage of multilevel inverter for this condition is given in [Figure 2 (a)](#fig2){ref-type="fig"}. Furthermore, the relevant experimental results are presented in [Figure 2 (b)](#fig2){ref-type="fig"}.Table 1Relevant triggering mode of suggested multilevel inverter as symmetrical operation.Table 1ON SwitchesV~out_symmetric~ON SwitchesV~out_symmetric~H~4~^1^, S~1~^1^, H~1~^2^, H~2~^2^ (H~1~^1^, H~2~^1^, H~4~^2^, S~1~^2^)1S~1~^1^, H~2~^1^, H~3~^2^, H~4~^2^ (H~3~^1^, H~4~^1^, H~2~^2^, S~1~^2^)-1H~4~^1^, H~1~^1^, H~1~^2^, H~2~^2^ (H~4~^1^, S~1~^1^, H~4~^2^, S~1~^2^)2H~3~^1^, H~2~^1^, H~3~^2^, H~4~^2^ (S~1~^1^, H~2~^1^, H~2~^2^, S~1~^2^)-2H~4~^1^, H~1~^1^, H~4~^2^, S~1~^2^ (H~4~^1^, S~1~^1^, H~1~^2^, H~4~^2^)3H~3~^1^, H~2~^1^, S~1~^2^, H~1~^2^ (S~1~^1^, H~2~^1^, H~2~^2^, H~3~^2^)-3H~4~^1^, H~1~^1^, H~1~^2^, H~4~^2^4H~3~^1^, H~2~^1^, H~2~^2^, H~1~^2^-4H~2~^1^, H~1~^1^, H~1~^2^, H~2~^2^0H~3~^1^, H~4~^1^, H~2~^2^, H~3~^2^0Figure 2(a). quasi-sinusoidal voltage in symmetrical operation with respect to k = 2 and n = 2. b. Experimental results of quasi-sinusoidal voltage in symmetrical operation with respect to k = 2 and n = 2.Figure 2

If each module has k capacitors, all capacitors\' values should be the same. The DC power supplies\' values in terms of capacitors value can be written by:$$V_{in,sub - multlvel} = \sum\limits_{j = 1}^{k}V_{c,j}$$where, $= V_{c,1 =}V_{c,2 =}...V_{c,k} = V_{c}$ Thus:$$V_{in,sub - multlvel} = k.V_{c} = V_{dc}$$

Summing the modules\' outputs, the maximum voltage of multilevel inverter is attained:$$V_{o,\max,symmetric} = \sum\limits_{i = 1}^{n}{V_{in,sub - multlvel,i} =}N_{Source}.k.V_{c} = N_{Source}.V_{dc}$$

Also, voltage step number can be presented by:$$M_{\text{Level,symmetric}} = 2.\left( {k.V_{o,\max,symmetric}} \right)/V_{dc} + 1$$Here, M~Level~/N~Source~ is introduced to accurately inspect the utilization performance of Switches and DC Sources to create the step level. It can be given as follows:$$\frac{M_{\text{Level,symmetric}}}{N_{Source}} = 2\left( {k + \frac{\left( {k + 1} \right)}{N_{Switch}}} \right)$$

2.2. Multilevel asymmetrical status {#sec2.2}
-----------------------------------

For providing a high-step quasi-sinusoidal voltage without adding any components, occupation of asymmetrical multilevel inverters isn\'t avoidable. In the asymmetric structure, the values of DC power supplies are non-equal which are increased in accordance with the particular geometric progression assumed. In general, such these structures are engaged as an alternative approach to minimize the output voltages THD with available electric power components. If each module has k capacitors, DC power supplies\' values in terms of capacitors value can be written by:$$V_{in,sub - multlvel,1} = \sum\limits_{j = 1}^{k}V_{c,j}$$where, $V_{c,1 =}V_{c,2 =}...V_{c,k} = V_{c1}$ Thus:$$V_{in,sub - multlvel} = k.V_{c1} = V_{dc}$$

Also, DC power supply value of the each module is determined by:$$V_{in,sub - multlvel,i} = \left\lbrack {2j + 1} \right\rbrack^{i - 1}V_{dc}$$where, j = 2, 3... k and i = 1, 2... n

Summing the modules\' outputs, the maximum voltage of multilevel inverter is attained:$$V_{o,\max,asymmetric} = \sum\limits_{i = 1}^{n}{V_{in,sub - multlvel,i} =}\frac{\left( {\left( {2k + 1} \right)^{N_{Source}} - 1} \right)}{2}k.V_{c1} = \frac{\left( {\left( {2k + 1} \right)^{N_{Source}} - 1} \right)}{2}V_{dc}$$

Also, voltage step number can be presented by:$$M_{\text{Level,asymmetric}} = \frac{\left( {2V_{o,\max,asymmetric}} \right)}{V_{dc}} + 1$$

M~Level~/N~Source~ for asymmetric status can be given as follows:$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}} = \frac{2}{N_{Switch}}.\left( {k + 1} \right) + \left( {2k + 1} \right)^{\frac{N_{Switch}}{2{({k + 1})}}}$$

The advantage of proposed AMLI is its high ability to act the same as "Quinary" with respect to one bidirectional switch along with two capacitors (k = 2), "Septenary" with respect to two bidirectional switches along with three capacitors (k = 3), "Nonary" with respect to three bidirectional switches along with four capacitors (k = 4), "Undenary" with respect to four bidirectional switches along with five capacitors (k = 5), and also in the same way the suggested Odd-nary AMLI has been attained. To have better understanding of aforesaid explanations, the triggering mode of switches considering: two capacitors for each module and two modules i.e. k = 2 and n = 2 are tabulated in [Table 2](#tbl2){ref-type="table"}. Furthermore, the output voltage of each sub-multilevel inverter accompanied by overall output voltage of AMLI is presented in [Figure 3](#fig3){ref-type="fig"}(a). Furthermore, the relevant experimental results are presented in [Figure 3](#fig3){ref-type="fig"}(b).Table 2Relevant triggering mode of suggested multilevel inverter as asymmetrical operation.Table 2ON SwitchesV~out_symmetric~ON SwitchesV~out_symmetric~S~1~^1^, H~4~^1^, H~1~^2^, H~2~^2^1S~1~^1^, H~2~^1^, H~3~^2^, H~4~^2^-1H~1~^1^, H~4~^1^, H~1~^2^, H~2~^2^2H~3~^1^, H~2~^1^, H~3~^2^, H~4~^2^-2H~3~^1^, H~2~^1^, S~1~^2^, H~4~^2^3H~1~^1^, H~4~^1^, S~1~^2^, H~2~^2^-3S~1~^1^, H~2~^1^, S~1~^2^, H~4~^2^4S~1~^1^, H~4~^1^, S~1~^2^, H~2~^2^-4H~1~^1^, H~2~^1^, S~1~^2^, H~4~^2^5H~3~^1^, H~4~^1^, S~1~^2^, H~2~^2^-5S~1~^1^, H~4~^1^, S~1~^2^, H~4~^2^6S~1~^1^, H~2~^1^, S~1~^2^, H~2~^2^-6H~1~^1^, H~4~^1^, S~1~^2^, H~4~^2^7H~3~^1^, H~2~^1^, S~1~^2^, H~2~^2^-7H~3~^1^, H~2~^1^, H~1~^2^, H~4~^2^8H~1~^1^, H~4~^1^, H~3~^2^, H~2~^2^-8S~1~^1^, H~2~^1^, H~1~^2^, H~4~^2^9S~1~^1^, H~4~^1^, H~3~^2^, H~2~^2^-9H~1~^1^, H~2~^1^, H~1~^2^, H~4~^2^10H~3~^1^, H~4~^1^, H~3~^2^, H~2~^2^-10S~1~^1^, H~4~^1^, H~1~^2^, H~4~^2^11S~1~^1^, H~2~^1^, H~3~^2^, H~2~^2^-11H~1~^1^, H~4~^1^, H~1~^2^, H~4~^2^12H~2~^1^, H~3~^1^, H~3~^2^, H~2~^2^-12H~1~^1^, H~2~^1^, H~1~^2^, H~2~^2^0H~3~^1^, H~4~^1^, H~3~^2^, H~4~^2^0Figure 3(a). quasi-sinusoidal voltage in Asymmetrical operation with respect to k = 2 and n = 2. (b). Experimental results quasi-sinusoidal voltage in symmetrical operation with respect to k = 2 and n = 2.Figure 3

2.3. Comparison of proposed multilevel inverter with other conventional multilevel inverters {#sec2.3}
--------------------------------------------------------------------------------------------

The capability of proposed multilevel inverter has been compared with other conventional multilevel inverters. To validate its capability, it has been evaluated under both the symmetric and asymmetric operation and compared with the conventional and recently introduced symmetric and asymmetric structures. The relationships between switch numbers in CHB structure, proposed structure in \[[@bib35], [@bib36], [@bib37]\]: and \[[@bib38]\], and M~Level~/N~Source~ benchmark in symmetric status can be respectively given as follows:$$\frac{\text{M}_{\text{Level}}}{N_{Source}}\left\lbrack CHB \right\rbrack = 2 + \frac{1}{4N_{Switch}}$$$$\frac{\text{M}_{\text{Level}}}{N_{Source}}\left\lbrack 35 \right\rbrack = 2\left( {1 + \frac{1}{\left( {N_{Switch} - 2} \right)}} \right)$$$$\frac{\text{M}_{\text{Level}}}{N_{Source}}\left\lbrack 36 \right\rbrack = 2\left( {1 + \frac{1}{\left( {N_{Switch} - 4} \right)}} \right)$$$$\frac{\text{M}_{\text{Level}}}{N_{Source}}\left\lbrack 37 \right\rbrack = \frac{1}{3} + \frac{2}{N_{Switch}}$$$$\frac{\text{M}_{\text{Level}}}{N_{Source}}\left\lbrack 38 \right\rbrack = 2\left( {1 + \frac{3}{\left( {N_{Switch} - 4} \right)}} \right)$$

Also, the relationships between switch numbers in binary and trinary structures \[[@bib37], [@bib38], [@bib39]\]: and \[[@bib40]\], and M~Level~/N~Source~ benchmark in asymmetric status can be respectively given as follows:$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack Binary \right\rbrack = \left( \frac{4}{N_{Switch}} \right)\left( {2^{\lbrack{\frac{N_{Switch}}{4} + 1}\rbrack} + 1} \right)$$$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack Trinary \right\rbrack = \left( \frac{4}{N_{Switch}} \right)\left( 3^{\lbrack\frac{N_{Switch}}{4}\rbrack} \right)$$$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack 37 \right\rbrack = \left( \frac{2}{N_{Switch}} \right)\left( 5^{\lbrack\frac{N_{Switch}}{6}\rbrack} \right)$$$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack 38 \right\rbrack = 3 + \frac{2}{N_{Switch} - 4}$$$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack 39 \right\rbrack = \left( \frac{2}{\left( {N_{Switch} - 4} \right)} \right)\left( {2^{\lbrack\frac{N_{Switch} - 2}{2}\rbrack} - 1} \right)$$$$\frac{M_{\text{Level,asymmetric}}}{N_{Source}}\left\lbrack 40 \right\rbrack = \left( \frac{3n - 1}{n\left( {N_{Switch} - 4} \right)} \right)\left( {2\left( {n + 1} \right)^{\lbrack\frac{N_{Switch} - 4}{3n - 1}\rbrack} - 1} \right)$$

The variation of M~Level~/N~Source~ benchmark versus switch number varieties of suggested structure and others for symmetrical and asymmetrical statuses are depicted in [Figure 4 (a)](#fig4){ref-type="fig"} and (b).Figure 4(a). Variation of M~Level~/N~Source~ versus of switch numbers of suggested structure and others for symmetric statuses. (b). Variation of M~Level~/N~Source~ versus of switch numbers of suggested structure and others for asymmetric statuses.Figure 4

The portrayed curves in [Figure 4 (a)](#fig4){ref-type="fig"} and (b) validate the high capability of suggested multilevel inverter aimed to create high-step quasi-sinusoidal voltage against the low embedded switches and DC power supplies. Furthermore, the number of required components for suggested multilevel inverter and others are presented in [Table 3](#tbl3){ref-type="table"}. As consequence, the significant problems related to multilevel inverters such as voltage quality, low THD, structure\'s cost price have been attained.Table 3The comparison of the suggested multilevel inverter and other topologies.Table 3ParametersCHBRef. \[[@bib35]\]BinaryTrinaryRef. \[[@bib36]\]Ref. \[[@bib37]\]Ref. \[[@bib38]\]Ref. \[[@bib39]\]Ref. \[[@bib40]\]Suggested InverterNo. of DC SuppliesNNNNNNNNNNNo. of Switches4N2(N+1)4N4N2(N+2)3N2(N+2)2(N+2)3N-12(K+1) per Sub-MLINo. of Steps2N + 12N + 12^(N+1)^-13^N^2N + 13^N^3N-22^(N+1)^-12(n+1)^k^-1(2K + 1)^N^No. of Gate Driver4N2(N+1)4N4N2(N+2)2N2(N+2)2(N+2)3N-1K+3 per Sub-MLINo. of ON State Switches2NN+12N2NN+23/2NN+2N+2(3N-1)/22N + 1

3. Voltage quality improvement scheme based on harmonic elimination Pulse Width Modulation {#sec3}
==========================================================================================

3.1. Harmonic elimination principle {#sec3.1}
-----------------------------------

Increase of switches to unravel the voltage quality problem becomes paler because the multilevel inverter provides a quasi-sinusoidal voltage waveform with trivial THD. Toward this subject, voltage quality of the proposed structure has been improved taking into account of ten switches to earn three prominent criterions related voltage quality i.e., desired fundamental component, elimination of third harmonic and Reduction of THD. Hence, nine levels symmetric status of the suggested structure has been considered to better exhibit elimination and reduction of harmonic components.

As well, the created quasi-sinusoidal voltage waveform can be extended in Fourier series:$$\upsilon_{out}\left( \alpha \right) = A_{0} + \sum\limits_{n = 1}^{\infty}{A_{n}.\cos\left( {n\alpha} \right)} + B_{n}.\sin\left( {n\alpha} \right)$$where,$$\left\{ \begin{array}{l}
{A_{0} = \left( {2\pi} \right)^{- 1}{\int_{0}^{2\pi}{V_{out}\left( \alpha \right).d\alpha}}} \\
{A_{n} = \left( \pi \right)^{- 1}{\int_{0}^{2\pi}{V_{out}\left( \alpha \right).\cos\left( {n\alpha} \right).d\left( \alpha \right)}}} \\
{B_{n} = \left( \pi \right)^{- 1}{\int_{0}^{2\pi}{V_{out}\left( \alpha \right).\sin\left( {n\alpha} \right).d\alpha}}} \\
\end{array} \right.$$

Due to absence of the average value or DC component created by multilevel inverter A~0~ = 0. According to the general quasi-sinusoidal waveform of multilevel inverter presented in [Figure 5](#fig5){ref-type="fig"}\_a, due to being odd function along with quarter-wave symmetry, only sinusoidal part of Fourier series with presence of odd harmonics can be appeared:$$\upsilon_{out}\left( \alpha \right) = \sum\limits_{n = 1,3,5,...}^{\infty}{B_{n}.\sin\left( {n\alpha} \right)}$$Figure 5(a). General quasi-sinusoidal voltage of cascaded multilevel inverter. (b). General scission-style harmonic elimination in quarter cycle waveform of cascaded multilevel inverter.Figure 5

3.2. PWM-based harmonic elimination strategy {#sec3.2}
--------------------------------------------

Harmonic elimination strategies have been designed and formulated to eliminate destructive harmonics from the quasi-sinusoidal voltage which is recognized as a contractual approach among the scholars and scientists. It has been essentially employed to decrease the THD from the output of inverter \[[@bib41], [@bib42]\]. Conventional HEPWM method i.e. non-scission HEPWM triggering has some prominent disadvantages. The first, to eliminate or reduce all the harmonics, a number of voltage levels must be produced by multilevel inverter which required more switches. The second, as the suggested symmetric inverter module has been triggered just twice in each quarter cycle, the perfect performance of these switches (high frequency switches) couldn\'t be used. Toward this subject, the scission-style harmonic elimination based on PWM that can modulate a number of angles within specific level provides quasi-sinusoidal voltage waveform with several scissions in each level as shown in [Figure 5 (a)](#fig5){ref-type="fig"}. The significant feature of "this strategy is eliminating further harmonics of low-step quasi-sinusoidal voltage i.e. low switch numbers. Thus, scission-style harmonic elimination owing to more triggering of switches in each quarter cycle, their performance will reach to fullest potential. Moreover, unequal DC power supplies can more augment the performance of this approach aimed to reduce lower order harmonics. Anyhow, the optimization problem has been formulated with various values of: DC power supplies, pulses width of quasi-sinusoidal waveform and triggering angles in each level which can be perceived with envisaging the [Figure 5 (b)](#fig5){ref-type="fig"}.

Fourier series of steppes quasi-sinusoidal voltage with non-equal dc sources can be presented by (28):

Where, s is the number of DC power supplies, and the *V*~*k*~*V*~*DC*~ is amount of the *kth* DC power supply. If all of DC power supplies have the equal value therefore *V*~*1*~*=V*~*2*~*= ...=V*~*S*~ *= 1*. Also, α~1~... α~m1~ are the triggering transitions in the first level, α~m1+1~...α~m1+m2~ are the triggering transitions in the second level, and the same α~m1+m2+...+1~ +...+ α~m1+m2+...+ms~ are the triggering transitions in the last level. The solution set will be attained using maintaining the value of fundamental component of output voltage in desirable value, *V*~*f*~, and all the harmonics except first set to be zero as presented by (31)--(33), and also the modulation index can be determined by Eqs. [(34)](#fd34){ref-type="disp-formula"} and [(35)](#fd35){ref-type="disp-formula"}:$$\upsilon_{out}\left( {\omega t} \right) = \sum\limits_{n = 1,3,5,...}^{s}\left\langle {\frac{4V_{f}}{n\pi}.\left\lbrack {\upsilon_{1}\sum\limits_{i = 1}^{m_{1}}{\left( {- 1} \right)^{i + 1}\ \cos\ n\alpha_{i} \pm \upsilon_{2}\sum\limits_{i = m_{1} + 1}^{m_{2}}{\left( {- 1} \right)^{i + 1}\ \cos\ n\alpha_{i}}} \pm ... \pm \upsilon_{s}\sum\limits_{i = m_{({s - 1})} + 1}^{m_{s}}{\left( {- 1} \right)^{i + 1}\ \cos\ n\alpha_{i}}} \right\rbrack} \right\rangle\sin\left( {n\omega t} \right)$$$$\hslash_{1} = \left\lbrack {\sum\limits_{i = 1}^{m_{1}}{\left( {- 1} \right)^{i - 1}\ \cos\ \alpha_{i} + \sum\limits_{i = m_{1} + 1}^{m_{2}}{\left( {- 1} \right)^{i - {({m_{1} + 1})}}\ \cos\ \alpha_{i}}} + ... + \sum\limits_{i = m_{({S - 1})} + 1}^{m_{S}}{\left( {- 1} \right)^{i - {({m_{({S - 1})} + 1})}}\ \cos\ \alpha_{i}}} \right\rbrack = M$$$$\hslash_{2} = \left\lbrack {\sum\limits_{i = 1}^{m_{1}}{\left( {- 1} \right)^{i - 1}\ \cos\ 5\alpha_{i} + \sum\limits_{i = m_{1} + 1}^{m_{2}}{\left( {- 1} \right)^{i - {({m_{1} + 1})}}\ \cos\ 5\alpha_{i}}} + ... + \sum\limits_{i = m_{({S - 1})} + 1}^{m_{S}}{\left( {- 1} \right)^{i - {({m_{({S - 1})} + 1})}}\ \cos\ 5\alpha_{i}}} \right\rbrack$$$$\hslash_{m} = \left\lbrack {\sum\limits_{i = 1}^{m_{1}}{\left( {- 1} \right)^{i - 1}\ \cos\left( {3m - 2} \right)\alpha_{i} + \sum\limits_{i = m_{1} + 1}^{m_{2}}{\left( {- 1} \right)^{i - {({m_{1} + 1})}}\ \cos\left( {3m - 2} \right)\alpha_{i}}} + ...}{+ \sum\limits_{i = m_{({S - 1})} + 1}^{m_{S}}{\left( {- 1} \right)^{i - {({m_{({S - 1})} + 1})}}\ \cos\left( {3m - 2} \right)\alpha_{i}}} \right\rbrack$$$$M = \frac{\pi V_{f}}{4V_{DC}},\mspace{9mu} 0 \leq M \leq S$$$$M_{i} = \frac{M}{S},\mspace{9mu} 0 \leq M_{i} \leq 1$$

3.3. Multi-objective functions {#sec3.3}
------------------------------

To achieve both aforesaid prominent targets, objective functions are determined by (36), (37).

The optimal problem will be solved by minimizing both aforesaid equations by MOGWO which will be explained next section.$$F_{1} = THD = V_{f}^{- 1}.\sqrt{\sum\limits_{i = 2}^{\infty}\hslash_{i}^{2}}$$$$F_{2} = \left| {\hslash_{1} - M} \right|$$$$F_{3} = \hslash_{3}$$

For appropriately carrying out the scission-style harmonic elimination scheme, it is impressive that an accurate sequencing of the triggering angles to be presented; i.e.:$$0 \leq \alpha_{1} < \alpha_{2}... < \alpha_{m_{1}}... < \alpha_{m_{S}} \leq \frac{\pi}{2}$$

Also, in order to augment this approach regarding to further harmonics, it can be taken into account that DC power supplies have non-similar magnitudes, i.e.:$$0 < V_{1} \neq V_{2} \neq ... \neq V_{s} \leq 1$$

And same the prior created restriction, different pulse-widths can be considered as one more criterions to augment the scission-style harmonic elimination scheme. Its relevant constraint is given as follows:$$0 < \alpha_{m_{1}} < \alpha_{m_{2}} < ... < \alpha_{m_{S}} < \frac{\pi}{2}$$

The multi-objective problem will be unravelled with consideration (39)--(41).

4. Description of non-dominated sorting multi objective grey wolf optimization & non-dominated Sorting Genetic Algorithm II {#sec4}
===========================================================================================================================

Due to multi-objective nature of the harmonic elimination strategy, the optimization problem has been formulated based on MOGWO to precisely extract the triggering angles of IGBTs\' gates toward enhance the voltage quality of multilevel inverter. To apprise and confirm this optimization scheme, it has been compared with NSGA-II. Both the MOGWO and NSGA-II have been described in following subsections.

4.1. Non-dominated sorting multi objective grey wolf optimization {#sec4.1}
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### 4.1.1. Grey wolf optimization review {#sec4.1.1}

GWO is a novel and advanced swarm based optimization algorithm inspired by imitating the headship hierarchy and hunting strategy of grey wolves. The performance of GWO is demonstrated more suitable than other prevalent optimization algorithm such as genetic algorithm and particle swarm optimization \[[@bib43]\]. Moreover, GWO is a high performance optimization technique with respect to its fast convergence (due to its search mechanism) and perceptible mathematical structure \[[@bib44]\]. Better and more precise, all wolves are divided into four groups according to their fitness. GWO search mechanism has been conducted by the best three wolves in any iteration. This mechanism upgrades the exploration so that all engaged wolves to be attracted, then the best three wolves, as a result of that the fast convergence will be obtained.

### 4.1.2. Multi-objective optimization {#sec4.1.2}

Multi-objective optimization is functionally constructed for solution of a multi-dimensional problem. The optimization problem formulation as a multi-objective minimization problem can be given by \[[@bib45], [@bib46]\]:$$Minimize\quad F\left( \overset{\rightarrow}{x} \right) = f_{1}\left( \overset{\rightarrow}{x} \right),f_{2}\left( \overset{\rightarrow}{x} \right),...,f_{N}\left( \overset{\rightarrow}{x} \right)$$

Subject to:$$\begin{matrix}
{g_{i}\left( \overset{\rightarrow}{x} \right) \leq 0,} & {\text{i} = 1\text{,}2\text{,...,m}} \\
{h_{i}\left( \overset{\rightarrow}{x} \right) = 0,} & {\text{i} = 1\text{,}2\text{,...,p}} \\
{L_{i} \leq x_{i} \leq U_{i},} & {\text{i} = 1\text{,}2\text{,...,n}} \\
\end{matrix}$$Where n, m, p, N are respectively: the number of variables, inequality constraints, equality constraints and objective functions. *g*~*i*~ and *h*~*i*~ are respectively the *i-th* inequality and equality constraints, and \[*L*~*i*~,*U*~*i*~\] indicates the *i-th* variable boundaries. Optimized single-objective results can simply be compared because of the unique objective function. Whereas, the extracted results from a multi-objective space may not be compared according to the relational operators because of multi-criteria objective functions. Hence, multi-objective problem has been unravelled via storing a set of the best solutions in a decision space. This space saves an archival record which is provided for the non-dominated solutions during the search process. The archival space has been initialized and iteratively updated, then, the best solutions are figured out as non-dominated set or Pareto optimal front (surfaces) \[[@bib47]\].

The mathematical description of Pareto dominance is presented to acquire minimum solution:

**Statement 1.** Pareto Dominance:

Assume the existence of two vectors such as: $\overset{\rightarrow}{\text{x}} = \left( \text{x}_{1}\text{,}\ \text{x}_{2}\text{,}\text{…}\text{,}\ \text{x}_{\text{k}} \right)$ and $\overset{\rightarrow}{\text{y}} = \left( \text{y}_{1}\text{,}\ \text{y}_{2}\text{,}\text{…}\text{,}\ \text{y}_{\text{k}} \right)$.

Vector *x* dominates vector *y* i.e., *x*≻*y* if:$$\forall i \in \left\{ {1,2,...,k} \right\}\text{;}\left\lbrack {\text{f}\left( \text{x}_{\text{i}} \right) \geq \text{f}\left( \text{y}_{\text{i}} \right) \land \left\lbrack {\exists i \in 1,2,...,k:f\left( x_{i} \right)} \right\rbrack} \right\rbrack$$

Pareto front (surface) is stated by \[[@bib48]\]:

**Statement 2.** Pareto Optimality:

A solution $\overset{\rightarrow}{x}$ ε*X* is named Pareto optimal if:$$\left. \exists\overset{\rightarrow}{y} \in X \middle| F\left( \overset{\rightarrow}{y} \right) \succ F\left( \overset{\rightarrow}{x} \right) \right.$$

The non-dominated solutions set is named by Pareto optimal set which is stated by:

**Statement 3.** Pareto optimal set:

A Pareto-optimal solution set is named Pareto set by:$$P_{s} = \left\{ x,y \in X \middle| \exists F\left( y \right) \succ F\left( x \right) \right\}$$

A set including the relevant objective contents in Pareto optimal set is named Pareto optimal front (surface) which is states by:

**Statement 4.** Pareto optimal front (surface):

A set including the objective functions\' value with regard to Pareto solutions set:$$P_{f} = \left\{ F\left( x \right) \middle| x \in P_{s} \right\}$$

### 4.1.3. Grey wolf optimization {#sec4.1.3}

This algorithm is inspired by the gregarious headship and hunting strategy of grey wolves. The social hierarchy of wolves is mathematically designed with consideration of the best solution as α wolf. Also, the second and third appropriate solutions are respectively considered as β and $\delta$ wolves. Wolves that have are considered as $\omega$ wolves. Based on GWO, hunting or optimization has been carried out using α, β and $\delta$, withal the $\omega$ wolves have optimally pursued these three wolves.

As for the [Figure 6](#fig6){ref-type="fig"}, the siege strategy of grey wolves during the hunting can be presented by:$$\overset{\rightarrow}{D} = \left| {\overset{\rightarrow}{C}.{\overset{\rightarrow}{X}}_{p}\left( t \right) - \overset{\rightarrow}{X}\left( t \right)} \right|$$$$\overset{\rightarrow}{X}\left( {t + 1} \right) = {\overset{\rightarrow}{X}}_{p}\left( t \right) - \overset{\rightarrow}{A}.\overset{\rightarrow}{D}$$where, t, ${\overset{\rightarrow}{X}}_{p}$ and $\overset{\rightarrow}{X}$ are respectively the current generation, the hunt situation vector, and the grey wolf situation vector. $\overset{\rightarrow}{A}$ and $\overset{\rightarrow}{C}$ are coefficient vectors.Figure 6Updating strategy of search operators by the weight.Figure 6

$\overset{\rightarrow}{A}$ and $\overset{\rightarrow}{C}$ are mathematically presented by:$$\overset{\rightarrow}{A} = 2\overset{\rightarrow}{a}.{\overset{\rightarrow}{r}}_{1} - \overset{\rightarrow}{a}$$$$\overset{\rightarrow}{C} = 2{\overset{\rightarrow}{r}}_{2}$$where, $\overset{\rightarrow}{a}$ is linearly subsided from 2 to 0 through the increase of iterations and *r*~*1*~ and *r*~*2*~ indicate the random vectors in \[0,1\].

The first three best solutions are preserved which are attained yet, then other search operators considering the omegas are compelled to improve their situation according to them. The following equations have been continually performed for each search operator during the optimization to construct the hunting mechanism and finding the desirable areas of the search space:$${\overset{\rightarrow}{D}}_{\alpha} = \left| {{\overset{\rightarrow}{C}}_{1}.{\overset{\rightarrow}{X}}_{\alpha} - \overset{\rightarrow}{X}} \right|$$$${\overset{\rightarrow}{D}}_{\beta} = \left| {{\overset{\rightarrow}{C}}_{2}.{\overset{\rightarrow}{X}}_{\beta} - \overset{\rightarrow}{X}} \right|$$$${\overset{\rightarrow}{D}}_{\delta} = \left| {{\overset{\rightarrow}{C}}_{3}.{\overset{\rightarrow}{X}}_{\delta} - \overset{\rightarrow}{X}} \right|$$$${\overset{\rightarrow}{X}}_{1} = {\overset{\rightarrow}{X}}_{\alpha} - {\overset{\rightarrow}{A}}_{1}.\left( {\overset{\rightarrow}{D}}_{\alpha} \right)$$$${\overset{\rightarrow}{X}}_{2} = {\overset{\rightarrow}{X}}_{\beta} - {\overset{\rightarrow}{A}}_{2}.\left( {\overset{\rightarrow}{D}}_{\beta} \right)$$$${\overset{\rightarrow}{X}}_{3} = {\overset{\rightarrow}{X}}_{\delta} - {\overset{\rightarrow}{A}}_{3}.\left( {\overset{\rightarrow}{D}}_{\beta} \right)$$$$\overset{\rightarrow}{X}\left( {t + 1} \right) = \frac{{\overset{\rightarrow}{X}}_{1} + {\overset{\rightarrow}{X}}_{2} + {\overset{\rightarrow}{X}}_{3}}{3}$$

The finding process is approved using A^→^ with random values upper than 1 or lower than -1 that compels the search operator to split from the hunt. C^→^ as accelerating factors in finding operations is randomly created in \[0, 2\], where in random weights has been created for prey to stochastically strengthen (C \> 1) or weaken (C \< 1) to determine the distance using hunt quality. The C parameter is being essentially created a random value to strengthen the finding mechanism through the iterations. It is important factor to avoid getting involved in the local optima minima, particularly in the latest iterations. \|A\|\<1 means that the optimization exploitation initiates, whereas A^→^ is randomly created in \[-1, 1\]. Individuals are diverged from the hunt as \|A^→^\|\>1 and converged towards the hunt as \|A^→^\|\<1. The following situation is located in any situation between its current situation and the hunt situation that boost the search procedure to converge to figured out situation of hunt generated by α, β, and δ solutions. The situation and α solution are come back so that the best solutions to be attained and the satisfied end state to delivered. Finally, the concise computational sages for MOGWO, as flowchart form can be comprehended in [Figure 7](#fig7){ref-type="fig"}.Figure 7Flowchart of multi objective grey wolf optimization.Figure 7

4.2. Non-dominated Sorting Genetic Algorithm-II \[[@bib49]\] {#sec4.2}
------------------------------------------------------------

### 4.2.1. Non-dominated sorting {#sec4.2.1}

❖For each individual (p) in main population perform:➢Initialize *S*~*p*~*=Ø*. This set encompasses all the individuals which are dominated by p.➢Initialize *n*~*p*~*=0.* This is the number of individuals which dominate p.➢for each individual q in P✓if p dominated q then:•add q to the *S*~*p*~ i.e. *S*~*p*~ = *S*~*p*~ U {g}✓else if q dominates p then•increase the domination counter for p i.e. *n*~*p*~ *= n*~*p*~*+1*✓if *n*~*p*~*=0* i.e. no individuals dominate p therefore p belonging to the first front; adjust the rank of individual p to one i.e *p*~*rank*~*=1.* Improve the first front set via addition of p to front one i.e *F*~*1*~*=F*~*1*~ *U {p}*❖This is performed for all individuals in the main population.❖Initialize the front counter to one*. i=1*❖Subsequent is performed when the *ith* front is non-blank i.e. *F*~*i*~*=Ø*;➢*Q=Ø*; the set of storing the individuals for *(i+1) th* front.➢for each individual *p* in *front F*~*i*~✓for each individual q in *S*~*p*~ (*S*~*p*~ is the set of individuals dominated by *p*)•*n*~*q*~ *= n*~*q*~*-1*, decrease the domination counter for individual q.•if *n*~*q*~ *= 0 subsequently* there is no individuals in the following fronts would dominate *q.* Therefore, set *q*~*rank*~*=i+1.* Update the set *Q* with individual q i.e. *Q=Q U q.*➢Increase the front counter by one.➢Now the set *Q* is the next front and subsequently *F*~*i*~*=Q.*

### 4.2.2. Crowding distance {#sec4.2.2}

❖For each front *F*~*i*~*, n* is the number of individuals.➢For all the individuals, the initialized distance is zero i.e. *F*~*i*~*(d*~*j*~*)=0*, where *j* correlates to the *jth* individual in front *F*~*i*~*.*➢for each objective function m✓Sort the individuals in front *F*~*i*~ according to objective m i.e. *I=sort (F*~*i*~*, m).*✓The boundary values for each individual is defined infinite *F*~*i*~ i.e. *I(d*~*1*~*)=∞* and *I(d*~*n*~*)=∞*✓for *k=2 to (n-1):*$$I\left( d_{k} \right) = I\left( d_{k} \right) + \frac{I\left( k + 1 \right).m - I\left( k - 1 \right).m}{f_{m}^{\max} - f_{m}^{\min}}$$•*I(k).m* is *the* value of the *mth* objective function related to the *kth* individual in I.

### 4.2.3. Genetic operators {#sec4.2.3}

#### 4.2.3.1. Simulated binary crossover {#sec4.2.3.1}

Simulated binary crossover method is chosen which is presented as follows:$$c_{1,k} = \frac{1}{2}\left\lbrack {\left( {1 - \beta_{k}} \right)p_{1,k} + \left( {1 + \beta_{k}} \right)p_{2,k}} \right\rbrack$$$$c_{2,k} = \frac{1}{2}\left\lbrack {\left( {1 + \beta_{k}} \right)p_{1,k} + \left( {1 - \beta_{k}} \right)p_{2,k}} \right\rbrack$$where, *c*~*i,k*~ is the *ith* child with *kth* part, *p*~*i,k*~ is the chosen parent, and *β*~*k*~ (≥0) is randomly created.$$p\left( \beta \right) = \frac{1}{2}\left( {\eta_{c} + 1} \right)\beta^{\eta_{c}},\mspace{9mu} if\quad 0 \leq \beta \leq 1$$$$p\left( \beta \right) = \frac{1}{2}\left( {\eta_{c} + 1} \right)\frac{1}{\beta^{\eta_{c} + 2}},\mspace{9mu} if\quad 1 < \beta$$

The distribution index (*η*~*c*~) can be acquired using a uniform sampled random number u between (0, 1).$$\beta\left( u \right) = \left( {2u} \right)^{\frac{1}{({\eta + 1})}}$$$$\beta\left( u \right) = \frac{1}{\left\lbrack {2\left( {1 - u} \right)} \right\rbrack^{1/{({\eta + 1})}}}$$

#### 4.2.3.2. Polynomial mutation {#sec4.2.3.2}

The polynomial mutation is used which is identified as follows:$$c_{k} = p_{k} + \left( {p_{k}^{u} - p_{k}^{l}} \right)\delta_{k}$$where, *c*~*k*~ and *p*~*k*~ are child and parent, respectively, also $p_{k}^{l}$ and $p_{k}^{u}$ are the lower and upper bounds on the parent components, respectively. *δ*~*k*~ is the small deviation which is defined as follows:$$\delta_{k} = \left( {2r_{k}} \right)^{\frac{1}{({\eta_{m} + 1})}} - 1,\mspace{9mu} if\quad r_{k} < 0.5$$$$\delta_{k} = 1 - \left\lbrack {2\left( {1 - r_{k}} \right)} \right\rbrack^{1/{({\eta_{m} + 1})}},\mspace{9mu} if\quad r_{k} \geq 0.5$$where, *r*~*k*~ is randomly chosen between (0, 1) and *η*~*m*~ is mutation distribution index.

### 4.2.4. Trade-off solution {#sec4.2.4}

Choosing an appropriate trade-off solution from all non-inferior options depends on problem and determiner\'s distinction. Therefore, the ultimate solution will be revealed based on both the procedures of optimization and decision. For this study, a Fuzzy-based method is applied to choose the best tradeoff solution from the acquired Pareto set. The *jth* objective function of a solution in a Pareto set *f*~*i*~ is defined by a membership function *μ*~*j*~:$$\mu_{j}\left( x \right) = \begin{Bmatrix}
1 & {f_{j} \leq f_{j}^{\min}} \\
\frac{f_{j}^{\max} - f_{j}}{f_{j}^{\max} - f_{j}^{\min}} & {f_{j}^{\min} \leq f_{j} \leq f_{j}^{\max}} \\
0 & {f_{j} \geq f_{j}^{\max}} \\
\end{Bmatrix}$$where, *f*~*j*~^*min*^ and *f*~*j*~^*max*^ indicate the minimum and maximum values of the *jth* objective function, respectively. For each solution *i*, the membership function *μ*^*i*^ can be presented by:$$\mu^{i} = \frac{\sum\limits_{j = 1}^{n}\mu_{j}^{i}}{\sum\limits_{i = 1}^{m}{\sum\limits_{j = 1}^{n}\mu_{j}^{i}}}$$

5. Scission-style harmonic elimination analysis and results {#sec5}
===========================================================

This approach has been designed to enhance the quality voltage of odd-nary AMLI. Owing to three prominent voltage quality criterions i.e., desired fundamental component, elimination of third harmonic and reduction of THD, the problem formulation has been constructed based on multi-objective algorithm. Toward this subject, MOGWO method is employed so that both the mentioned targets (minimum value of (36)--(38)) to be acquired. It is worth mentioning that, MOGWO based Harmonic Elimination not only figures out the triggering angles of scission points in each level, but also incorporates the non-equality of DC power supplies\' magnitude and also different pulse-widths. Hereof, the flexibility of this strategy has been heightened using three salient criterions aimed to more acquisition of voltage quality improvement. The quasi-sinusoidal voltage waveform and reference-carriers waveforms that are created according to the scission-style harmonic elimination scheme are presented in [Figure 8](#fig8){ref-type="fig"}(a) and (b), respectively. However, this strategy has been solved in accordance with three following schemes:Figure 8(a). The proposed scission-style harmonic elimination scheme based on: different scission in each level, non-equality of DC sources and different pulse-widths. (b). Reference and carrier waveforms based on scission-style harmonic elimination scheme.Figure 8

Due to heavy computational burden of this approach, aforesaid schemes have been severally carried out.

5.1. Scission-style harmonic elimination scheme considering different scissions {#sec5.1}
-------------------------------------------------------------------------------

According to the relevant sequencing presented in (39), the search space of MOGWO is constricted for pre-defined area. Moreover, for scission-style harmonic elimination the angles should be accurately located between these levels. As can be seen in [Figure 5](#fig5){ref-type="fig"}(b) m~1~, m~2~ and m~s~ indicate the number of angles which are available in the first, the second and the latest level, respectively. The angle propagation index has been set as triggering angles to define a set angle in each step of quasi-sinusoidal voltage. This index is presented by m~1~/m~2~/.../m~s~; for example for angle propagation proportion of 6/4/7/5, it has indicated that first, second, third and fourth levels encompass 6, 4, 7 and 5 angles, respectively.

Computational burden of scission-style harmonic elimination with presence of the angle propagation index and sequencing has been highly heightened. Also, the number of scission in each step acts as critical function to define the performance of this computation, and accordingly value of THD. Meantime, as the number of scissions (in each level) to be increased, subsequently the value of fundamental component will decrease, and reversely. Thus, the maintenance of fundamental component is one of the prominent issues in this field. Due to destructive effects of third harmonic on normal operation of system, it must be considered as another function. That\'s why MOGWO is engaged to obtain three aforementioned objective functions. The optimization problem has unravelled twenty four angles in each quarter cycle of quasi-sinusoidal waveform of proposed multilevel inverter. Also, the propagation proportion is taken to be 3/5/9/11 along with the modulation index (2.68 \< M \< 3.03). Following that the optimization processes, the Pareto solution surfaces of the optimization problem performed by MOGWO and NSGA-II are portrayed in [Figure 9](#fig9){ref-type="fig"}(a), and the trajectory curve of twenty eight triggering angle are depicted in and 9 (b). As can be seen, the optimization scheme based on MOGWO has provided more accurate and optimum result than NSGA-II. Also, the quasi-sinusoidal voltage and the relevant harmonic spectrum are presented in [Figure 10 (a) and (b)](#fig10){ref-type="fig"}, respectively. To strictly validate these results, their relevant experimental results are presented in in [Figure 10](#fig10){ref-type="fig"}(c) and (d). As consequence, the performance of scission-style harmonic elimination aimed at reduction of the THD, elimination of third harmonic and maintenance of fundamental component (1.7^p.u.^) is proved.Figure 9(a). Pareto solution surfaces of the optimization problem by MOGWO and NSGA-II. (b). Triggering angle trajectories versus values modulation index.Figure 9Figure 10(a). Simulation result of quasi-sinusoidal voltage. (b). Simulation FFT of quasi-sinusoidal voltage. (c). Experimental result of quasi-sinusoidal voltage. (d). Experimental FFT of quasi-sinusoidal voltage.Figure 10

5.2. Scission-style harmonic elimination scheme considering non-equal DC power supplies {#sec5.2}
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In accordance with the sequence of (40), the constraint of non-equality of DC power supplies is assigned. Same the previous section, the MOGWO has optimized the magnitude of DC power supplies in order to minimize three defined objective functions. Excluding the effects of triggering angle to carry out the Harmonic Elimination, variety of the DC power sources\' magnitude can be considered as an important criterion for optimization problem. The quasi-sinusoidal voltage and its harmonic spectrum related to the optimum solution are presented in [Figure 11 (a)](#fig11){ref-type="fig"} and (b), respectively. Furthermore, their relevant experimental results are presented in in [Figure 11 (c) and (d)](#fig11){ref-type="fig"}. These figure have clearly shown that third objective-functions have been well-reduced and also fundamental component is held on pre-defined value1.9 ^p.u.^.Figure 11(a). Simulation result of quasi-sinusoidal voltage. (b). Simulation FFT of quasi-sinusoidal voltage. (c). Experimental result of quasi-sinusoidal voltage. (d). Experimental FFT of quasi-sinusoidal voltage.Figure 11

5.3. Scission-style harmonic elimination scheme considering different pulse-width values {#sec5.3}
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In this part, the width of all pulses of quasi-sinusoidal waveform is optimized by MOGWO so that three objective functions to be minimized. The performance of this item in the form of output voltage of inverter and harmonic spectrum are respectively shown in [Figure 12 (a)](#fig12){ref-type="fig"} and (b). Furthermore, their relevant experimental results are presented in in [Figure 12 (c) and (d)](#fig12){ref-type="fig"}. These figures have confirmed that, what accuracy of acquired results from two previous parts is also repeated for this analysis. The difference here is that: the magnitude of fundamental component in considered to be 1.8 ^p.u.^.Figure 12(a). Simulation result of quasi-sinusoidal voltage. (b). Simulation FFT of quasi-sinusoidal voltage. (c). Experimental result of quasi-sinusoidal voltage. (d). Experimental FFT of quasi-sinusoidal voltage.Figure 12

6. Conclusion {#sec6}
=============

An innovational cascaded AMLI has been designed and analyzed so that a high-step quasi-sinusoidal voltage with low harmonic components to be acquired. To validate the suggested AMLI capability, it has been thoroughly evaluated and compared with the conventional and recently introduced symmetric and asymmetric multilevel inverters. Sub-AMLI has been designed using the ladder capacitors of clamped to the H-bridge by several bi-directional switches. A creative geometric progression has been formulated for DC power supplies of AMLI to function as odd-nary AMLI. Meanwhile, three defined objective functions related to voltage quality i.e., desired fundamental component, elimination of third harmonic and reduction of THD have been optimally minimized using suggested MOGWO-based scission-style harmonic elimination scheme. To confirm the optimization scheme based on MOGWO, it has been compared with this scheme based on NSGA-II. Finally, the relevant analytical analysis has been essentially confirmed that suggested structure can provide high-step quasi sinusoidal voltage as compared with others. Also, both the simulation and experiment results have clearly corroborated the performance of odd-nary AMLI.

Declarations {#sec7}
============

Author contribution statement {#sec7.1}
-----------------------------

Ali Darvish Falehi: Conceived and designed the experiments; Performed the experiments; Analyzed and interpreted the data; Contributed reagents, materials, analysis tools or data; Wrote the paper.

Funding statement {#sec7.2}
-----------------

This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.

Competing interest statement {#sec7.3}
----------------------------

The authors declare no conflict of interest.

Additional information {#sec7.4}
----------------------

No additional information is available for this paper.
