1. Technical Field
The present invention relates to a semiconductor device that includes a multilayer interconnect structure.
2. Related Art
To cope with the recent growing demand for higher operating speed for semiconductor chips, various studies are being aggressively made on employing a material having a lower dielectric constant to form an interlayer dielectric in place of a silicon oxide film (dielectric constant K=approx. 4.3), to thereby reduce parasitic capacitance between interconnect lines. Examples of applicable low dielectric constant (hereinafter abbreviated as low-k) insulating material include HSQ, MSQ, and aromatic-containing organic resins, which have a dielectric constant of approx. 3. Besides, for achieving a still lower dielectric constant, porous materials that include minute pores are lately being developed. Employing such low-k materials to form the interlayer dielectric allows reducing crosstalk between the interconnect lines, thus achieving higher operating speed of the chips.
The low-k films, however, generally have low film strength, and insufficient adhesion properties. Besides, because of the lack of strength, the low-k film is prone to be scraped off during a CMP (Chemical Mechanical Polishing) process, in a region where interconnect lines are not densely distributed.
Now, when fabricating semiconductor chips, a plurality of circuit chips are first formed on a wafer, and then the wafer is diced into individual chips. By the dicing process, dicing sections of the semiconductor chips are exposed. Accordingly, a seal ring region is provided along the periphery of each circuit chip, so as to prevent intrusion of water or moisture through the dicing sections. JP-A 2004-297022 discloses a structure of a semiconductor chip provided with a seal ring constituted of vias and interconnects disposed along the outer periphery. In this structure, the seal ring is continuously disposed so as to be connected to all layers, including the lower layers and upper layers of the semiconductor chip, to thereby prevent the intrusion of water or moisture through the dicing sections (FIG. 2 of JP-A 2004-297022).
Generally, in a semiconductor device, upper layers are formed in an insulating layer constituted of silicon oxide film, which is sufficiently rigid, serving as the interlayer dielectric, while lower layers are formed in an interlayer dielectric constituted of a low-k film, for reducing the interconnect capacitance. The low-k film lacks in mechanical strength and adhesion properties, as stated above. Besides, the low-k film is prone to absorb moisture. Therefore, improvement in mechanical strength and moisture resistance with respect to the lower layers of the semiconductor device is an important issue to be addressed.
On the other hand, since the upper layers include the wider interconnects and the larger vias in general, the size of the seal ring region is determined according to the size of the interconnects and vias in the upper layers. Therefore, it is desirable to have the interconnects and vias in the upper layers disposed so as to prevent the seal ring region from excessively expanding.