1. Field of Invention
The present invention relates to an Identification (ID) configuration method and particularly to a method of ID configuration for advanced programmable interrupt controller (APIC) in a multiprocessor computer system.
2. Related Art
As the coming of the information era, the computer system has become one of the essential instruments of people's life. In order to improve the processing efficiency of the computer system, a symmetrical multiprocessor (SMP) system has been developed in the recent years. When the computer system processes a task, the speed of performing the processing task by two processors in parallel is much faster than that by one single processor, similarly, when the processing task is performed by four processors in parallel, its speed is faster than that by two processors. And even when one processor among them is failed, other processors can take over its task to maintain the stability of the computer system. In view of the above advantages, the multiprocessor architecture is adopted by most of the large workstations or server systems
For the system level, the multiprocessor system needs two advanced programmable interrupt controllers (APICs) to process the interrupt request (IRQ), in which one is a local APIC located in the central processor units (CPU), the other is an input/output APIC (I/O APIC) belonging to the I/O system, and the two may be connected to each other through an dedicated APIC bus. The local APIC is in charge of processing the local interrupts for the local processors, and may also accept and produce the interrupt request between the processors through the AIPC bus; and the I/O APIC uses a redirection table to redirect an interrupt request sending from one local APIC to another local APIC through the APIC bus.
However, the I/O APIC may also cause the system malfunction, and one of the causes is the ID assignment problem when there are a large number of processors.
When the computer system is powered on, the IDs stored in the register of each APIC will be set by a basic input output system (BIOS), and the APIC ID needs to be read from the MP configuration table to provide the information required by the operation to the operating system. The MP configuration table stored in the BIOS has its specific format convection, such as the MP configuration table following the Intel MP1.4 specification, i.e. using a specific multiprocessor and architecture.
Previously, in the BIOS, the parameter of the CPU's local APIC in the MP configuration table was set first, and its ID is set from 0, while the I/O APIC ID is arranged behind the last CPU's local APIC ID.
For example, when there are 8 dual-core CPUs in the computer system, IDs need to be assigned to 16 (8*2) local APICs, and IDs 0˜15 are occupied by each local APIC sequentially, therefore, the I/O APIC IDs should be arranged from 16, and stored in the register of the I/O APIC chipset. But generally, I/O APIC only support the register with limited bits, e.g. the registers of two I/O APICs in the AMD 8131 bridge chip only support 4 bits respectively, that is, it is only possible to be set to 15 (0˜15) at most. When the ID 16 is to be written into the first I/O APIC register, it will be written as 0000 (binary), the same with the first CPU's local APIC ID, as the entire 10000 (16 in the binary) can not be written into, and in that way, a conflict comes into being.
Therefore, how to provide an APIC ID configuration method becomes one of the problems to be solved by the researchers.