The present invention relates in general to semiconductor devices and their manufacture. More specifically, the present invention relates to the fabrication of vertically stacked nanosheet transistors having inner spacers and improved source to drain sheet resistance.
In contemporary semiconductor device fabrication, a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as vertical field effect transistors (VFETs) and nanosheet (a.k.a., nanowire) transistors, can provide increased device density and increased performance over planar transistors. In nanosheet transistors, in contrast to conventional planar FETs, the gate stack wraps around the full perimeter of multiple nanosheet channel regions, which enables fuller depletion in the channel regions and reduces short-channel effects.