1. Field of the Invention
The present invention relates to a wide lock range phase locked loop (PLL) type frequency synthesizer including a plurality of voltage controlled oscillators and its method for selecting an oscillation frequency.
2. Description of the Related Art
Generally, in a mobile telephone apparatus, a wide lock range PLL type frequency synthesizer having a plurality of voltage controlled oscillators is mounted as a local oscillator to cope with different frequencies.
In a prior art wide lock range PLL type frequency synthesizer (see: JP-A-10-200406) including a PLL circuit having a phase/frequency comparator, a charge pump circuit, a loop filter, a voltage controlled oscillator block formed by a plurality of voltage controlled oscillators and a plurality of switches connected to the voltage controlled oscillators, and a 1/N frequency divider where N is a positive integer, an unlock control circuit is provided. The unlock control circuit has an unlocked state detecting circuit, an up/down counter, and a selector for selecting one of the switches in accordance with the output signals of the up/down counter. In this case, the up/down counter is connected to the phase/frequency comparator. That is, in an unlocked state, the unlocked state detecting circuit passes the output signals of the phase/frequency comparator to the up/down counter. As a result, when the phase/frequency comparator generates a leading signal, the up/down counter is counted up. Therefore, when the value of the up/down counter reaches its maximum value, the up/down counter generates an overflow carry signal, so that the selector selects another switch. Contrary to this, when the phase/frequency comparator generates a lagging signal, the up/down counter is counted down. Therefore, when the value of the up/down counter reaches its minimum value, the up/down counter generates an underflow carry signal, so that the selector selects another switch. Thus, as the oscillation frequency of the voltage control oscillator block fluctuates due to a temperature fluctuation or power supply voltage fluctuation, the up/down counter and the selector and are operated to quickly move a phase unlocked state to a phase locked loop stage. This will be explained later in detail.
In the above-described prior art PLL type frequency synthesizer, however, since the up/down counter is operated by the output signals of the phase/frequency comparator, when the precision of the phase/frequency comparator is enhanced, the precision of the up/down counter also has to be enhanced. As a result, the switching from a phase unlocked state to a phase locked state is delayed which increases the lockup time.
Also, in the above-described prior art PLL type frequency synthesizer, since all the voltage controlled oscillators are always operated, the power consumption would be increased.