The present invention relates to semiconductor devices and fabrication processes, and more specifically to semiconductor gate electrode architectures which provide improved work function tuning.
In the conventional CMOS process, poly silicon is used as a gate electrode material up to 90 nm node. The conventional process has several advantages such as: (i) it is compatible with high temperature processing, (ii) well behaved poly-Si/thermal SiO2 interfaces, (iii) more reliable than metal gate electrode like Al, (iv) conformal deposition over steep topography (v) and most significantly it introduces self-aligned dual work function for both n-MOSFETs and p-MOSFETs by selection of proper dopant.
The polysilicon gate electrode, however, also represents a major challenge for near-term and long-term CMOS scaling. Some major limitations of the process include gate depletion, high gate resistance and boron penetration into the channel region. The poly depletion causes an effective increase in the gate dielectric thickness, which operates to reduce the current drive. Boron diffusion from p+ polysilicon gate to the channel degrades device performance significantly. Both the effective increase in the gate dielectric thickness associated with depletion and the channel autodoping associated with boron out-diffusion from the p+ polysilicon gate will eventually require the phase-out of polysilicon as gate material beyond the 45 nm technology node.
Metal gate electrodes offer a potential solution to the aforementioned problem. Metal gate electrodes provide advantages such as: (i) no boron penetration from polysilicon gate into channel through very thin gate dielectric, (ii) much lower gate resistance, (iii) and perhaps the most desirable advantage of reduced electrical thickness of gate dielectric. The last and most significant advantage is derived through elimination of depletion in heavily doped polysilicon gates, which can amount to a 3-5 Å reduction in equivalent oxide thickness (EOT)—the equivalent of ˜2 generation advancement.
A key requirement for gate electrode material in CMOS is that of dual work function. Gate metal for NMOS and PMOS devices should have work functions which closely correspond to conduction and valence band edge respectively for surface channel mode of operation. In conventionally fabricated CMOS devices, the dual work function of the polysilicon gate is achieved by implanting the polysilicon material with either n or p-type dopants (during deep S/D implantation) as mentioned above.
In the case of refractory metals or metal nitrides, work function is not a strong function of doping, and S/D implantation cannot be used for work function tuning. Further, conventional approaches of using two different bulk metals to fabricate NMOS and PMOS gate electrodes require the use of exotic metals and alloys to meet the work function requirements, which complicates CMOS processing and results in lower device yield.
What is needed is a gate electrode architecture capable of a dual work function, and which can be preferably fabricated using technology close to conventional CMOS fabrication.