This application claims the benefit of Korean Application No. 2000-46938, filed Aug. 14, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices, and more particularly, to duty cycle correction circuits.
Recently, the speed of semiconductor memory devices, for example, dynamic random access memories (DRAMs), has increased to improve the performance of existing systems. However, increasing demand for improved systems may require DRAMs that can process even more data at even higher speeds. Accordingly, synchronous dynamic random access memories (SDRAMs) that operate in synchronization with system clocks have been developed for a high-speed operation, thus significantly increasing data transmission speeds.
There are limitations on the amount of data that may be input to and/or output from a memory device per clock cycle of a system clock. To address these limitations, dual data rate (DDR) SDRAMs have been recently developed in order to further increase the transmission speed of data. DDR SDRAMS input and/or output data in synchronization with both the rising edge and the falling edge of a clock.
Reliable data transmission is possible when the duty cycle of a clock signal is equivalent at 50%, which is ideal, in a DDR SDRAM or a direct rambus dynamic random access memory (RDRAM). Thus, when a signal having a duty cycle that is not equivalent, i.e. greater than or less than 50%, is provided as an input, the signal typically does not perform very well as an input signal. Duty cycle correction circuits have been developed to address this problem.
A block diagram of a conventional duty cycle correction circuit is illustrated in FIG. 1. A duty cycle correction circuit includes a duty cycle corrector 10 and a detection circuit 13. The duty cycle corrector 10 generates a pair of complementary input signals IN and INB, from which distortion is typically removed, in response to first and second complementary clock signals CLK and CLKB, having distortion resulting from nonequivalent duty cycles. The detection circuit 13 feeds back first and second detection signals DETECT and DETECTB obtained by detecting distortion in the duty cycles of the complementary pair of input signals IN and INB of the correction circuit 10 in response to the pair of complementary input signals IN and INB.
Now referring to FIG. 2, a circuit diagram of a conventional detection circuit 13 of FIG. 1 will be discussed. When mismatching exists among diode-connected loads M1 and M4, cross-coupled loads M2 and M3, source coupled pairs M5 and M6, and/or the respective transistors in the detection circuit 13, increased distortion may occur in the duty cycles of the pair of complementary input signals IN and INB due to mismatching of the respective transistors, even though less distortion is present in the duty cycles of the complementary pair of clock signals CLK and CLKB.
Semiconductor devices according to embodiments of the present invention include a duty cycle correction circuit having a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.
In some embodiments of the present invention, the duty cycle corrector further generates a second input signal having a fourth duty cycle with a higher degree of equivalence than the third duty cycle in response to a second detection signal and a second control signal having a third duty cycle. The detection circuit, in other embodiments of the present invention, further generates the second detection signal in response to the second input signal.
In further embodiments of the present invention, the duty cycle correction circuit includes a load matching circuit that is electrically coupled to the first and second current sources and matches a load of the bias circuit in response to the second input signal.
In still further embodiments of the present invention, the first control signal is a true clock signal and the second control signal is a complementary clock signal. Furthermore, the first and second input signals are complementary signals and the first and second detection signals are complementary signals.
In some embodiments of the present invention, the duty cycle correction circuit further includes a first output driver circuit that pulls the first detection signal up or down in response to the first input signal and a second output driver circuit that pulls a second detection signal up or down in response to a second input signal. The current generated by the current source is supplied to the first output driver circuit, the second output driver circuit and the bias circuit responsive to a bias voltage. The bias voltage may be a voltage at a first node during a period and is calculated according to the equation VNODB+VNODCxe2x88x92VDDxe2x88x92GND. VNODB is the voltage at a second node, VNODC is the voltage at a third node, VDD is a source voltage, and GND is a ground voltage.