FIFO storages are well known in the art of electronic circuits and computers and are widely used for embodying interfacing circuits in many different applications.
They are particularly widely used, but not exclusively, in the field of image and video processing.
FIG. 1 reminds the general architecture of an interfacing circuit based on a FIFO memory which allows the transfer of data (such as audio samples or picture elements) FROM a “data producer device” 100 (such as audio or image sensor) via a lead 99 or we can consider that data are already available in a memory 150, TO, a “data consumer device” 299 (like a signal processor device for audio, video or image). The circuit comprises an interface 120 receiving data from memory 150 via a data bus 151. The interface 120 is used for proper formatting operation of the data before it is forwarded to a FIFO 100 through a data bus 101. The reading of the FIFO is controlled by the “data consumer device” 299 represented by an external circuit (image or audio signal processor) by means of a ENABLE lead 113 and a CLK_RD clock signal lead 112. On the other side, the writing of the FIFO by the “data producer” 100 is controlled by a (inverted) WR signal 103 under the clocking of a WR signal conveyed by a lead 102. Two additional FIFO_FULL and FIFO_empty signals, respectively on leads 121 and 122, are used for respectively reporting a situation of full storage and empty storage to the “data producer” 100 and “data consumer devices” 299.
The circuit which is represented in FIG. 1 is a typical example of a set of well known circuits and, therefore, does not need to elaborate any further introduction nor development to a skilled man.
Briefly, it suffices to recall that such circuit is widely used for achieving many different interfaces, such as image and video interface such as camera interface circuits.
However, one may recall the general trend to an increase of the resolution of image sensors which lead to a significant volume of data to be transferred between the sensors/memory to the video or image interface circuits.
This drastic increase in the volume of data clearly generates a significant pressure on the FIFO circuits which have to operate at very high speed clocks.
The continuous trend to higher speeds might result the designer to proceed with a new redesign of the analog interface and therefore the interfacing circuits comprising the FIFO. Such redesign would inevitably results in higher manufacturing costs which is not desirable.
Alternatively, one may wish to improve the design of the conventional FIFO based interfacing card so as to increase the efficiency even without increasing the frequency of the clocking circuits.
Such is the technical problem to be solved by the present invention.