With a semiconductor testing system (including so-called an IC tester, LSI tester, and so forth; hereinafter referred to merely as a tester), it is necessary to supply a device as a test subject {hereinafter referred to as a DUT (Device Under Test)} with a voltage with high precision in order to inspect and test the DUT with good precision. Accordingly, a tester is provided with a power supply assembly capable of outputting a voltage with high precision. Determination on whether or not a DUT is acceptable has been made by taking measurements on current flowing from the power supply assembly to the DUT. The DUT includes, for example, an IC, LSI, and so forth (refer to, for example, Patent Document 1).
FIG. 6 is a block diagram showing a configuration of a tester using a conventional power supply assembly.
In FIG. 6, a power supply assembly 100 is installed in a tester main body, and comprises a voltage buffer 1, a DAC 2, an error amplifier 3, an output amplifier 4, a current detection circuit 5, and a current measurement circuit 6, wherein the power supply assembly 100 outputs voltage and current to a DUT 7 while monitoring a level of a voltage applied to the DUT 7.
The DUT 7 is a load, and has a plurality of terminals for input/output, and a predetermined voltage Vout is applied from the power supply assembly 100 to a desired terminal (a DUT terminal). Further, the DUT 7 is placed on the top of a performance board (not shown) of a test head (not shown) of the tester.
The voltage buffer 1 has a noninverting input terminal, to which an applied voltage Vout to the DUT 7 is inputted. The DAC 2 is a kind of a voltage generation circuit, and outputs a predetermined set voltage Vout. An output voltage from the voltage buffer 1, and an output voltage from the DAC 2 are inputted to the error amplifier 3.
An error signal from the error amplifier 3 is inputted to the output amplifier 4, which either increase or decrease amperage to the DUT terminal of the DUT 7, thereby applying a voltage Vout as corrected by an error portion to the DUT 7. Further, with the output amplifier 4, an output terminal is connected to an inverting input terminal. Still further, the output amplifier 4 is driven by a power supply voltage (voltage level: VDD on the plus side, and VEE on the minus side) from a power supply unit U 1. In this case, the power supply unit U 1 constantly outputs a voltage at a given level regardless of an output voltage, and an output current of the output amplifier 4.
The current detection circuit 5 is provided between the output amplifier 4, and the DUT 7. The current measurement circuit 6 takes measurements on current by the agency of a signal from the current detection circuit 5. Further, the power supply voltage from the power supply unit U 1 is also fed to the voltage buffer 1, the DAC 2, the error amplifier 3, the current detection circuit 5, and so forth, although not shown in the figure.
Operation of the tester is described hereinafter.
The DAC 2 outputs the predetermined set voltage Vout. A voltage signal from the DAC 2 is inputted to a noninverting input terminal of the error amplifier 3, and a voltage being applied to the DUT 7 is inputted to an inverting input terminal of the error amplifier 3 via the voltage buffer 1, as being fed back.
Further, the error amplifier 3 amplifies an error within a amplifier 4. Then, the output amplifier 4 increases or decreases the amperage fed to the DUT 7 on the basis of the error signal from the error amplifier 3 so as to reduce a voltage error at the error amplifier 3. That is, the set voltage of the DAC 2 is used as a reference.
The applied voltage to the DUT 7, after varied by an increase or a decrease in amperage, is fed back again to the error amplifier 3 via the voltage buffer 1, and the error amplifier 3 detects an error. Further, the output amplifier 4 causes an increase or a decrease in amperage so as to reduce the error. Thus, a level of the voltage applied to the DUT 7 is finally rendered equivalent to that of the set voltage Vout of the DAC 2 to be subsequently maintained.
Meanwhile, the current detection circuit 5 converts current applied to the DUT 7 into voltage, and an ADC (not shown) of the current measurement circuit 6 executes A/D conversion of the voltage to be then outputted to a determination circuit (not shown) in a later stage, whereupon the determination circuit determines whether or not the DUT 7 is acceptable.
FIG. 7 is a block diagram showing a configuration of a tester with a plurality of channels of the power supply assemblies 100 mounted therein. The power supply assemblies 100 each apply a voltage to different terminals of a DUT 7, however, the power supply voltage (VDD, VEE) from the same power supply unit U 1 is supplied to respective output amplifiers 4.
Further, a primary cause for occurrence of the error between the set voltage of the DAC 2, and the applied voltage to the DUT 7 is occurrence of a potential difference between a preference potential of the DAC 2, and a reference potential of the DUT 7. The DUT 7 is normally connected to the ground at a reference potential of a whole tester (the reference potential of the DAC 2 as well is equivalent to the ground potential as the reference potential of the whole tester). Upon flow of current at a large amperage to the DUT 7, however, a voltage drop occurs to a signal line form the DUT 7 to the ground. Accordingly, the reference potential of a system ground differs from the reference potential of the DUT 7 (voltages at respective terminals of the DUT 7, at the reference potential thereof), thereby causing a difference between the reference potential of the DAC 2, and the reference potential of the DUT 7. Other causes for the error include, for example, a voltage drop accompanying resistance in flow paths up to the current detection circuit 5, and up to the DUT 7, respectively.
[Patent Document 1] JP 2005-98896 A
With the structure of the power supply assembly and semiconductor testing system using same, the output voltage of the power supply assembly 100 has a variable voltage level, that is, the set voltage that can be outputted by the DAC 2 is rendered variable so as to be able to cope with the kind of a device, and various test items. To give an example of a specification, the output voltage is set in a range of 0 to 10 V. The power supply voltage level of the output amplifier 4 need to have a potential difference equivalent to the output voltage outputted by the output amplifier 4 with a bias voltage added thereto. For example, there is the need for the potential difference ΔV=approx. 5 V. Accordingly, because the level of the power supply voltage (VDD, VEE) supplied to the output amplifier 4 is fixed, the level of the power supply voltage VDD on the plus side need be at least 15 V in order to meet the specification in respect of the output voltage of the power supply assembly 100.
Further, in the case where a plus current Iout is consumed at the DUT 7, the current lout is fed to the DUT 7 via a plus side power supply voltage terminal (the voltage level VDD side) of the output amplifier 4. In the case where a minus current Iout is consumed at the DUT 7, the current Iout is absorbed from the DUT 7 via a minus side power supply voltage terminal (the voltage level VEE side) of the output amplifier 4.
And, the power supply voltage levels VDD, VEE (that is, the respective levels of the voltages outputted by the power supply unit U 1) of the output amplifier 4 are under control by a constant voltage operation without depending on the set voltage of the DAC 2, and the current Iout consumed at the DUT 7.
Now, FIG. 8 is a conceptual view showing consumed power of the output amplifier 4, as a loss of a plus side output. Assuming by way of example that VDD=15 V, Vout=1 V, and Iout=5 A, power loss at the output amplifier 4 will be 70 W={(the power supply voltage level−the output voltage level)×the output current}. Further, if Vout=0 V, a loss of consumed power will be 75 W at the maximum. Then, the consumed power is released in the form of heat from the output amplifier 4.
FIG. 9 is a conceptual view showing the total current and output power which the power supply assemblies 100 in whole can output when the plurality of the channels of the power supply assemblies 100 are mounted as shown in FIG. 7. Assuming by way of example that Vout=10 V (the maximum output level), ΔV=5 V, and rated output power of the power supply unit U 1=150 W, the total current will be 10 A at the maximum regardless of the set voltage of the DAC 2, so that the lower the voltage level of the set voltage, the lower will be utilization efficiency of electric power.
In particular, there have lately been seen trends for lower voltage and lager amperage in the case of a device used as the DUT 7 to be measured by a semiconductor testing system. In the case of outputting a large amperage at such a low voltage to the device, a heat release problem with the conventional power supply assembly 100 has posed a very significant problem. Accordingly, a heat release design for the power supply assembly 100 becomes larger in scale, thereby creating causes for an increase in size as well as cost of the power supply assembly 100.
In addition, because the semiconductor testing system has a multitude of the power supply assemblies 100, magnitude of heat release becomes significant, and reduction in size of the power supply assembly is difficult to implement, so that there has arisen a problem of difficulty in checking the cost thereof.