Integrated circuit memories, such as static random access memories (SRAMs) require increasingly short access times. SRAMs are often used in the portion of a processing system where speed is very important, such as a cache memory for microprocessor. Address transition detection is one method that has been used to decrease access time by allowing a memory access to begin as soon as a change in an address is detected. ATD decreases memory access times, and may also reduce power consumption, by providing both preconditioning signals and activation signals in the memory. For example, ATD may be used for a word line driving, bit line driving and precharge, data line sensing, and for data outputting.
An address transition detector generates a pulse in response to an address change. It is typical to have a separate address transition detector for each address signal which transitions are to be detected. For example, if a transition of the row address is to be detected, then an address transition detector is commonly used for a row address signal. The output pulses of these detectors are then logically combined by logic gates to provide a single summation signal. This summation signal is then used to provide timing and control signals for the memory.
In the past, the summation of ATD pulses has been accomplished by using centrally located ATD summation logic circuitry. Metal lines have been used to route the ATD summation signal to portions of the memory where the ATD summation signal is to be used, such as to the word line drivers or to the bit line loads. However, as memories increase in size and density, the distance from the centrally located ATD summation circuitry to the most distant circuits of the memory increases, resulting in the need for longer metal lines. A problem with using longer metal lines to route the ATD pulses is the increased parasitic capacitance that the centrally located ATD summation logic circuit must drive, increasing power consumption, and requiring the use of larger drive transistors in the centrally located ATD summation logic circuitry. In addition, the timing signals may be excessively skewed from one another in different portions of the memory because the signals have to travel different distance across the memory. Excessively skewed timing signals may seriously degrade the performance and reliability of the memory.