This invention relates to a header processing engine for processing packet headers.
Computer systems on modern data packet networks typically exchange data in accordance with several different protocols operating at all layers of the network—from protocols governing the quality of service of data streams, to protocols determining the logical construction of data packets, to protocols determining the physical signaling of fully-formed data packets onto the fabric of the network. A typical network data packet will therefore have multiple headers formed in a nested arrangement as the data packet is built up at a computer system. Often data packets will include one or more headers at each of layers 2 to 5 of the Open System Interconnection (OSI) model.
For example, a TCP/IP data packet transmitted over an Ethernet network over which a logical VLAN has been established might have a nested header structure similar to the following:                Ethernet/VLAN/IP/TCPAdditionally the packet could have layer 5 headers within the above structure, such as a NetBIOS header.        
The headers of a data packet tell a computer system handling the data packet all of the information it needs to know in order to correctly route the payload data of the data packet to its destination and to respond appropriately to the originator of the data packet. Without the packet headers the payload data is simply a series of bits without any context and a computer system would not know how to handle the data. On receiving a data packet a computer system must therefore process the headers of the data packet in order to determine what it is going to do with the data packet.
Generally, some of the header processing is done in software in the end system and some of the header processing is done in hardware. Software processing usually follows the model of a layered protocol stack, with successive headers being stripped and processed in turn. In contrast, hardware processing may process only some headers, or handle combinations of headers as a single entity, in order perform the required operations. Header processing at hardware can be particularly useful for routing packet data, accelerating packet delivery, or for manipulating the header of a packet.
Header processing in hardware is generally performed at a network interface device. As each data packet is received, the network interface device parses the headers of the data packet and performs such operations as: performing checksums, extracting data and looking up the intended destination of the data packet using the address data in the headers. The operations performed generally depend on the type of headers present in the data packet. Since multiple operations are typically required for each data packet and there can be millions of data packets arriving over a network at a computer system every second it is important to ensure that the headers are processed as efficiently and with as little latency as possible.
Conventional header processing hardware uses a dedicated processor to parse the headers in a data packet and perform the processing required for each header as the headers are identified. Such a processor can be efficient in terms of the number of operations the hardware is required to perform, but often waste processor cycles as the same processor executes each operation in the necessary order. For example, the processor must read header data from the packet buffer, identify the headers in each data packet, request look-up operations in forwarding tables at the network interface device, and make calls to hash calculation units at the network interface device. Furthermore, the instruction set of the processor must be large enough to support the range of operations the processor is expected to perform. This can lead to complex processors being used to perform what are in essence a series of repetitive simple operations. Such processors are power inefficient, which is a particular concern in network interface devices for use in blade servers and data farms.
Furthermore, implementing header processing in hardware or firmware using the classic layered protocol stack model is very inefficient, requiring hardware configured to constantly process chains of if-then-else logic over sequences of headers.
There is therefore a need for an improved header processing engine for a network interface device which addresses the above problems.