1. Field of the Present Invention
The present invention relates to a semiconductor memory device, and more particularly to an array of flash memory cells, in which a unit cell includes a single transistor and to methods for programming and erasing the same.
2. Discussion of the Related Art
An ideal memory element allows for easy programming (writing), easy erasing, and retains a memory state even if power is removed, i.e., is nonvolatile. Nonvolatile semiconductor memories (NVSM) are classified into two typesxe2x80x94a floating gate type and a metal insulator semiconductor (MIS) type. The MIS type also may have two or more kinds of stacked dielectric films.
The floating gate type memory uses a potential well to implement memory functions. ETOX (EPROM Tunnel Oxide) structure, which has recently been the most applicable technology for the flash EEPROM (Electrically Erasable Read Only Memory), is typical of the floating gate type. The floating gate type structure can be used to implement a memory cell using a single transistor.
On the other hand, the MIS type memory function uses traps formed in a dielectric film bulk, a boundary layer between two dielectric films, or a boundary layer between a dielectric film and a semiconductor. The MONOS/SONOS (Metal/Poly Silicon Oxide Nitride Oxide Semiconductor) structure, which is used as a full-featured EEPROM, is typical.
To execute the program and erase operations in these memory cells, it is essential that selection transistors be included in addition to the transistors of MONOS/SONOS structure. In other words, each memory cell must include at least two transistors.
The array of conventional flash memory cells and the methods for programming and erasing the same are explained in detail by referring to the accompanying drawings FIGS. 1-2B. As seen in FIG. 1, a unit cell of the conventional flash memory cells includes two transistors.
FIG. 2A shows an array of conventional flash memory cells using the cell in FIG. 1 as the unit cell, and bias conditions for programming the cells. FIG. 2B shows the array of conventional flash memory cells using the cell in FIG. 1 as a unit cell and the bias conditions for erasing the cells.
As seen, the array of conventional flash memory cells is constructed by arranging unit cells in a form of matrix. Each cell includes two transistorsxe2x80x94a memory transistor having a MONOS/SONOS structure and a selection transistor for determining whether the cell is selected or not.
A plurality of word lines are constructed in a direction so that the gates memory transistors arranged in a row are commonly connected.
A plurality of word selection lines are constructed in a direction parallel to the word lines so that the gates of selection transistors arranged in a row are commonly connected.
A plurality of bit lines are constructed in a direction perpendicular to the word lines so that the drains of memory transistors arranged in a column are commonly connected.
A plurality of bit selection lines are constructed in a direction parallel to the bit lines so that the drains of selection transistors arranged in a column are commonly connected.
As mentioned above, the conventional unit cell includes a memory transistor having the MONOS/SONOS structure and a selection transistor. A cell is selected by selecting the selection transistor, and program and erase operations are performed on the associated memory transistor.
As shown in FIG. 1, the memory transistor has an ONO (Oxide Nitride Oxide) structure including a first oxide film 11, a nitride film 12, and a second oxide film 13 sequentially stacked on a portion of a semiconductor substrate 10. A first gate electrode 15a is formed on the oxide film 13.
The selection transistor includes a gate oxide film 14 and a second gate electrode 15b formed on the gate oxide film 14. The gate oxide film 14 of the selection transistor is thicker than the first and second oxide films 11 and 13 so that a portion of the selection transistor is isolated from the first gate electrode 15a. 
A common source region 16a is formed in a portion of the semiconductor substrate 10 between the memory transistor and the selection transistor. Drain regions 16b are formed in portions of the semiconductor substrate 10 at the outside of the memory and selection transistors.
In the conventional flash memory cell, programming is accomplished by applying a high positive voltage to the first gate electrode 15a. When the high voltage is so applied, electrons from the semiconductor substrate 10 tunnel through the first oxide film 11 and are injected into the nitride film 12. Thus, the first oxide film 11 is called a tunneling oxide.
The second oxide film 13 prevents electrons injected into the nitride film 12 from leaking into the first gate electrode 15a. The second oxide film 13 also prevents electrons from being injected from the first gate electrode 15a into the nitride film 12. Thus, the second oxide film 13 is called a blocking oxide.
Since the program operation uses traps in the boundary layer between the nitride film 12 and the second oxide film 13, electrons should be injected into or emitted from the entire region of a substrate channel to perform the program and erase operations.
When performing a programming operation, the array of cells is biased in a certain manner. The programming bias condition for the array of conventional flash memory cells is explained as follows.
Referring to FIG. 2A, a unit cell, among the plurality of flash memory cells, is selected for programming. Thereafter, a voltage Vp is applied to the word line connected to the gate of the selected memory transistor. Vp is also applied to the word selection line connected to the gate of the selection transistor of the selected cell. Due to the arrangement, the gates of memory transistors and selection transistors of other cells in the same row are also applied with the same Vp voltage.
However, a ground voltage is applied to the word lines of the non-selected rows. Also, the word selection lines of the non-selected rows have their voltages left floating.
For the bit line connected to a drain of the selected memory transistor, the ground voltage is applied. However, for the non-selected bit lines, a voltage Vi is applied. Similarly, for the bit selection line connected to the drain of the selected selection transistor, voltage is left floating, while the non-selected bit selections lines have ground voltages applied.
Finally, ground voltage is also applied to the well (semiconductor substrate) at the lower portion of all the cells regardless of whether that cell is selected or not. The aforementioned bias conditions are simultaneously applied.
Table 1 describes the bias conditions for the programming operation in a table form.
Note that multiple cells maybe selected at a time for programming, such as a byte at a time.
When performing an erasing operation, the array of cells is differently biased from the programming operation. The erasing bias condition for the array of conventional flash memory cells is explained as follows.
Referring to FIG. 2B, a unit cell is selected for erasing. Thereafter, the ground voltage is applied to the word line connected to the gate of the selected memory transistor. Also, Vp is applied to the word selection line connected to the gate of the selection transistor of the selected cell.
However, for the non-selected word lines, voltage Vp is applied, while the word selection lines are left floating.
For the bit line connected to a drain of the selected memory transistor, the ground voltage is applied. However, for the non-selected bit lines, a voltage Vi is applied. Similarly, for the bit selection line connected to the drain of the selected selection transistor, voltage is floating, while the non-selected bit selection lines have ground voltages applied.
Finally, as in the programming operation described above, ground voltage is applied to the well (semiconductor substrate) at the lower portion of all the cells regardless of whether that cell is selected or not. The aforementioned bias conditions are simultaneously applied.
The table 2 describes the bias conditions for the erasing operation in a table form.
Again, multiple cells may be selected for erasing, such as a byte at a time.
The array of conventional flash memory cells and the program and erase methods using the same have the following problems. First, because two transistors are used for a single cell, the area for a chip becomes large and it is difficult to isolate cells from each other. Second, programming the chip is complex.
It is therefore an object of the present invention to improve the integrity of a chip by using a single transistor for a single cell.
It is another object of the present invention to easily implement the program operation by the byte and the erase operation in bulk by providing an array whose single cell comprises a single transistor.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages in accordance with the purpose of the present invention, as embodied and broadly described, an array of flash memory cells according to the present invention comprises a plurality of flash memory cells, each of the cells having a MONOS/SONOS structure and being arranged in the form of a matrix, a plurality of word lines arranged in one line direction so that the gates of the flash memory cells arranged in one and the same row are commonly connected, a plurality of selection lines arranged in a direction perpendicular to the word lines so that the sources of the flash memory cells arranged in one and the same column are commonly connected, and a plurality of bit lines arranged in a direction parallel to the selection lines so that the drains of the flash memory cells arranged in one and the same column are commonly connected.
A data program method using the array of the flash memory cells according to the present invention, in a plurality of word lines, selection lines and bit lines respectively connected to the gates, sources and drains of a plurality of flash memory cells arranged in the form of a matrix and wells formed in the lower portion of each of the flash memory cells, comprises a first step for selecting one cell among a plurality of the flash memory cells; a second step for applying a power supply voltage Vcc to the word line connected to the gate of the selected cell and a voltage xe2x88x92Vpp to the well in the lower portion of the selected cell and to the selection and bit lines connected to the source and drain of the selected cell; a third step for performing the second step and at the same time applying a ground voltage to the selection and bit lines of the cells connected to the same word line as the selected cell and a voltage xe2x88x92Vpp to the wells; and a fourth step for performing the first and second steps and at the same time applying a ground voltage to the word lines of the cells not connected to the same word line as the selected cell and a voltage xe2x88x92Vpp to the wells and to the selection and bit lines of the cells not connected to the same word line as the selected cell.
A data erase method using the array of the flash memory cells according to the present invention, in a plurality of word lines, selection lines and bit lines which are connected, respectively, to the gates, the sources and the drains of a plurality of flash memory cells arranged in the form of a matrix and wells formed in the lower portion of each of the flash memory cell, comprises a first step for applying a voltage xe2x88x92Vpp to the word lines of the cells and a second step for performing the first step and at the same time applying a power supply voltage Vcc to the selection and bit lines of the cells and to the wells in the lower portion of the cells.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.