Some electronic components, such as circuit-level devices, integrated-circuit-level devices, board-level devices, and system-level devices, use a multi-phase clock signal. Typically, the multi-phase clock is generated by a ring oscillator, a delay locked loop (DLL), or logic dividers with an external reset or initialization.
However, the circuitry that generates the multi-phase clock generally do not operate at low voltage, have relatively narrow bandwidth support, do not have good noise characteristics, and consume a large amount of power. Moreover, an external reset or initialization for such circuitry does not provide adequate design robustness.