1. Technical Field
The present invention relates to a pipeline-type analog-to-digital converter.
2. Related Art
Conventionally, there has been known a pipeline-type analog-to-digital (A/D) converter in which an A/D converting stage (stage) of a small bit number is cascade-connected and digital values obtained in each stage are computed so as to obtain a final digital value. For example, refer to JP-A-2005-252326.
In each stage, an input analog signal is quantized by a sub A/D converter to be converted into a digital signal, and then the digital signal is digital-to analog converted by a sub D/A converter. The input analog signal and the analog signal produced by the sub D/A converter are subjected to a subtraction process. The resulting signal is amplified by an operational amplifier to be outputted to a subsequent stage.
In the pipeline-type A/D converter, a good linearity is required in which a relation between an analog input and a digital output shows a line. The linearity of the input and output signals, however, has not been thoroughly examined in known patents. Thus, improving the input-output linearity has been expected.