PLL circuits are well known in the art. The operation of providing a synchronized output clock signal with respect to an input reference clock is also well known. Prior art PLL circuits or circuit systems may have extended periods of time where no output clock is produced while the PLL circuit or circuits are re-locking. This can occur, for example, in a harsh operating environment such as a space environment wherein a single charged particle can temporarily or even permanently affect the performance of a single PLL. What is desired is a PLL circuit system that can reliably provide the desired synced output clock signal even though a single PLL in the circuit system may be temporarily or permanently made unavailable.