1. Field of the Invention
The present invention relates to a transmission gate and a semiconductor device.
2. Description of the Related Art
A conventional transmission gate is described. FIG. 8 is a circuit diagram illustrating the conventional transmission gate.
The transmission gate includes a PMOS transistor 91 and an NMOS transistor 92. In those transistors, gates thereof are controlled by complementary signals, and thus the transistors are turned ON/OFF simultaneously. When a low level voltage is input to the gate of the PMOS transistor 91, and a high level voltage is input to the gate of the NMOS transistor 92, electrical continuity of the transmission gate is established. Then, the transmission gate outputs an input voltage Vin as an output voltage Vout.
Here, a gate-to-source capacitance of the PMOS transistor 91 is represented by Cgsp, a gate-to-source capacitance of the NMOS transistor 92 is represented by Cgsn, a parasitic capacitance at an output terminal is represented by Ch, a threshold voltage of the PMOS transistor 91 is represented by −Vtp, and a threshold voltage of the NMOS transistor 92 is represented by Vtn. Further, a voltage magnitude applied to the gate of the PMOS transistor 91 is represented by V5, and a voltage magnitude applied to the gate of the NMOS transistor 92 is represented by V4. When the transmission gate is set so as to satisfy the following Expression (11), influence of clock feedthrough is reduced. Therefore, it is possible to attain high S/N characteristics (for example, see JP 07-169292 A).(V5−Vout−Vtp)·Cgsp/(Cgsp+Ch)=(V4−Vout−Vtn)·Cgsn/(Cgsn+Ch)  (11)
However, in the related art, Expression (11) is satisfied based on the presupposition that the input voltage Vin is a constant voltage (for example, (VDD+VSS)/2) and does not fluctuate. In other words, when the input voltage Vin fluctuates and therefore the output voltage Vout fluctuates, Expression (11) is not satisfied. Therefore, the S/N characteristics are degraded due to the influence of clock feedthrough.