1. Field of the Invention
This invention relates to a pipelined computer and methods in the same.
2. Description of the Prior Art
In a pipelined computer having instruction pipelines of different types, the instruction pipelines sometimes spend different respective times in execution of respective instructions. In such a case, although a slight change in the sequence of actual execution of instructions is allowed, the contents of registers in the computer are required to be updated in the same sequence as the sequence of execution of the instructions. Controlling the sequence of completion of execution of instructions referred to as establishing the synchronization between the pipelines.
Prior art methods of synchronization in a pipelined computer will be listed in the following.
1) Asynchronous: Controlled units are not synchronized with each other, and communication between the units is performed via flags and handshakes.
2) Horizontal Control: A composite instruction controls the operation of setting different units at respective clock periods. A long instruction is divided into a large number of fields. Processors are parallelly and independently controlled by the respective fields, and thereby the synchronization between the processors is established. When the degree of the parallel is low, the efficiency of bit use of the instruction is small. It is necessary to prepare a process of judging the possibility of parallel processing during the instruction execution, or a process of extracting the possibility of parallel processing during the instruction compiling. Thus, in the case where the controls of the processors are determined in accordance with the results of the processings by the processors respectively, the instruction is rearranged and then the instruction is required to be decoded, thereby necessitating expenditure of additional time.
3) Lockstep: A set of equal processors is synchronously controlled so that the processors will simultaneously execute equal processings.
4) Issue-When-Ready: As soon as a required unit or register becomes free, an instruction is transmitted to an execution unit.
The prior art methods 1)-3) have problems as follows. The prior art method 1) is unsuited to the realization of high-speed synchronization since a handshake spends a considerable time. In the case where an exception occurs in a controlled unit and simultaneously the execution of an instruction in another controlled unit needs to be interrupted, it is difficult for the prior art method 1) to realize a method of disabling the processing of the instruction at a high speed. In the prior art method 2), since all units are controlled by a common horizontal instruction, the units can not operate independently and also processors can not be operated independently. In the prior art method 2), since the execution times of the processors are sometimes different, the process of disabling the processing of the instruction tends to be complicated during the occurrence of an exception in one of the processors. The prior art method 3) requires units to be equal. The prior art method 3) can not be applied to the case where units independently execute different operations although the units are equal.