In recent years, non-volatile static random access memory has been widely used. Non-volatile static random access memory (nvSRAM) does not lose data stored therein, even when the power to the nvSRAM is interrupted.
A unit memory cell of an nvSRAM is described in U.S. Pat. No. 5,914,895. That unit memory cell includes a non-volatile circuit configured as a non-volatile memory element for maintaining non-volatile data. It also includes an SRAM configured as a volatile memory element for performing read and write operations of volatile data. FIG. 1 is a schematic equivalent circuit illustrating a unit memory cell 10 of the nvSRAM described in U.S. Pat. No. 5,914,895.
Referring to FIG. 1, the memory cell 10 includes an SRAM 12 and a pair of non-volatile memory circuits (hereinafter, referred to as NVM) 14. The SRAM 12 includes a pair of access transistors 30, 32 and a latch circuit 33. The latch circuit 33 includes two NMOS transistors and two PMOS transistors which are cross-coupled to each other.
A data true level signal and a data complement level signal are output to data nodes 20 and 22, respectively. The data nodes 20, 22 are located within the latch circuit 33. The data true level signal and the data complement level signal are opposite to each other.
The access transistor 30 is coupled between the data node 20 and a signal line BT. The access transistor 32 is coupled between the data node 22 and a signal line BC. The signal line BT is a bit line for the data true level. The signal line BC is a bit line for the data complement level. The bit lines BT and BC extend to all the stacked cells in a single vertical column in a memory cell array. Each vertical column of cells has a common pair of bit lines.
The access transistors 30, 32 are controlled by a signal applied to a signal line WL. The signal line WL is a word line connected in common to the gate terminals of the access transistors 30, 32 and to the gate terminals of all the other access transistors in all the stacked cells in a single low.
The NVM 14 is a circuit connected to each of the data nodes 20, 22 for storing data at the data nodes 20, 22 such that the stored data is not volatile.
The NVM 14 of FIG. 1 is configured as a pair of tri-gate transistors 41, 42 including recall transistors 41a and 42a, SONOS (silicon/oxide/nitride/oxide/silicon) transistors 41b and 42b, and pass transistors 41c and 42c. 
The SONOS transistors 41b, 42b, which are described in U.S. Pat. No. 5,914,895 and U.S. Pat. No. 6,770,950, have an ONO (oxide/nitride/oxide) structure. The SONOS transistors 41b, 42b store the data levels of the data nodes 20, 22 such that the data levels stored in the latch circuit 33 are not volatile. The data levels stored in the SONOS transistors 41b, 42b are removed when a control signal Vse is applied thereto.
The recall transistors 41a, 42a recall the data levels stored in the SONOS transistors 41b, 42b and write the data levels stored in the SONOS transistors 41b, 42b into the latch circuit 33 when a control signal Vrcl is applied to the recall transistors 41a, 42a. 
The pass transistors 41c, 42c read the state of the data true level signal and the complement level signal in the latch circuit 33, or write the data levels stored in the SONOS transistors 41b, 42b into the latch circuit 33 when a control signal Vpas is applied to the pass transistors 41c, 42c. 
The operation of the conventional nvSRAM 10 will now be described. When a power source is on and the nvSRAM operates normally, all of the voltages of the control signals Vrcl, Vpas and Vse are set to 0[V] so that all of the transistors of the tri-gate transistors 41, 42 are turned off. As a result, the SONOS transistors 41b and 42b are isolated from the latch circuit 33 and, thus, are not affected by state variations of the levels at the data nodes 20, 22 of the latch circuit 33.
However, when the power source is turned off, the nvSRAM 10 stores the levels at the data nodes 20, 22 of the latch circuit 33 in the SONOS transistor 41b, 42b, or erases the levels while passing through an erase mode and a program mode.
In the erase mode, a voltage of −10 to −15 [V] (depending on erase speed, erase time, the ONO structure, etc) is applied to the gate electrodes of the SONOS transistors 41b, 42b. Also, a voltage of 0 [V] is applied to the control signal line Vrcl and to the control signal line Vpas for a predetermined time. In general, the bias voltage is usually applied for less than 10 [msec] in the erase mode.
Under the bias conditions of the erase mode, the recall transistors 41a, 42a and the pass transistors 41c, 42c are held in an off state, and the SONOS transistors 41b, 42b are placed in an accumulation mode. Most of the electric field associated with the voltage applied to the gate electrodes of the SONOS transistors 41b, 42b is concentrated on the ONO layer.
As a result of the intensive electric field concentrated on the ONO layer, holes accumulated on a silicon substrate surface on which the gate electrodes of the SONOS transistors 41b, 42b are placed tunnel through the tunnel oxide film of the SONOS transistors 41b, 42b, and are trapped in traps which are present in the nitride film of the SONOS transistors 41b, 42b. Then, the electrons which have been trapped in the nitride films tunnel the tunnel oxide and escape into the silicon substrate, thereby resulting in erasure whereby a threshold voltage of the SONOS transistors 41b, 42b is lowered.
Next, in the program mode, a voltage of +10 to +15 [V] (depending on program speed, program time, the ONO stack structure, etc) is applied to the gate electrodes of the SONOS transistors 41b, 42b. Also, 0 [V] is applied to the control signal line Vrcl, and a voltage “H” (herein, “H” refers to a voltage representing a high logic state; typically 2.5 [V]) is applied to the control signal line Vpas for a predetermined time. In general, the bias voltage is usually applied for less than 10 [msec] in the program mode.
Under the bias conditions of the program mode, the recall transistors 41a, 42a are held in an off state, and accordingly, do not conduct current from the Vcc voltage. The conducting states of the pass transistors 41c, 42c are determined by the logic levels (“H” and “L”) stored in the data nodes 20, 22 of the latch circuit 33. For example, if we assume that a high voltage level “H” is stored in the data node 20 and a low voltage level “L” is stored in the data node 22, since a high level Vpas is applied to the gate electrode of the pass transistor 41c connected to the data node 20 and the data node 20 is connected to the source electrode of the pass transistor 41c, the voltage difference between the gate electrode and the source electrode becomes nearly 0 [V]. Accordingly, the pass transistor 41c does not conduct current. As a result, the silicon substrate below the gate electrode of the SONOS transistor 41b goes into a deep depletion state due to the positive voltage applied to the gate electrode of the SONOS transistor 41b. 
During this deep depletion, since the electric field caused by the positive voltage Vse applied to the gate electrode of the SONOS transistor 41b is mostly applied to a depletion region of the silicon substrate and, thus, is only slightly applied to the ONO layer, the program mode (where electrons tunnel the tunnel oxide film and are trapped into the traps of the nitride film) does not occur. This phenomenon is called a dynamic write inhibition (DWI).
Since this deep depletion occurs in a non-equilibrium state, it disappears over time as the non-equilibrium state turns to an equilibrium state. When the deep depletion condition disappears, DWI does not occur any longer. In other words, although programming is not conducted due to the DWI phenomenon occurring at the beginning of the program mode, programming is conducted as the DWI phenomenon disappears after a predetermined period of time elapses. The characteristic of the DWI phenomenon depends on the device structure. The DWI phenomenon typically lasts for 1 to 100 [msec].
On the other hand, since the voltage Vpas applied to the gate electrode of the pass transistor 42c has a high level “H, a low voltage level “L” is stored in the data node 22, and since the data node 22 is connected to the source electrode of the pass transistor 42c, a voltage difference between the gate electrode and the source electrode becomes nearly “H” [V]. Consequently, the pass transistor 42c is turned on.
As a result, the voltage applied to the silicon substrate below the gate electrode of the SONOS transistor 42b becomes nearly an “L” [V]. Thus, most of the program voltage applied to the gate electrode of the SONOS transistor 42b is applied to the ONO layer. Accordingly, electrons accumulated on the surface of the silicon substrate tunnel the tunnel oxide film, and the program mode is conducted to trap the electrons in the traps of the nitride film. The trapped electrons increase the threshold voltage of the SONOS transistor 42b. 
In other words, the SONOS transistor 41b maintains an erase state at the beginning of the program mode and, thus, has a low threshold voltage because the program mode is suppressed due to the DWI phenomenon. However, the SONOS transistor 42b has a high threshold voltage as the program mode is conducted.
When the power source is on, a recall mode for recalling data stored in the SONOS transistors 41b, 42b to the latch circuit 33 is performed. In the recall mode, a low voltage 0 [V] is applied to the control signal line Vse, and a high voltage “H” is applied to the control signal line Vrcl and to the control signal line Vpas.
Under the bias conditions of the recall mode, since the control signal line Vrcl and the control signal line Vpas are set to a logic high voltage “H”, the recall transistors 41a, 42a and the pass transistors 41c, 42c go into an on state. Since the SONOS transistor 41b is in an on state, current flows therethrough and the data node 20 goes into a logic high state “H”. Since the programmed SONOS transistor 42b is in an off state, it does not flow current therethrough and the data node 22 goes into a logic low state “L”.
Accordingly, even though a memory element configured by the nvSRAM is powered off while passing through the erase mode, the program mode and the recall mode, the data of SRAM can be securely stored in the NVM 14.
However, in an nvSRAM using conventional SONOS transistors 41b, 42b, due to the DWI phenomenon when data is stored, one data node is programmed and the other data node is not programmed depending on the states of the data nodes 20, 22 of the latch circuit 33. In such a selective program mode, it is important to improve the DWI characteristic and the programming speed.
However, it is very difficult to improve the DWI characteristic. Although programming time is prolonged when the selective program mode is conducted by a DWI mechanism, a threshold voltage window (i.e., a difference between a threshold voltage of a SONOS transistor to be programmed and a threshold voltage of a SONOS transistor in which the DWI phenomenon occurs) cannot be increased beyond a certain voltage.
In addition, since the thickness of the tunnel oxide film of the SONOS transistor is very small (typically about 20 Å), the retention characteristic of the SONOS transistor is very poor. Furthermore, since the programming speed of the SONOS transistor is relatively low, a significantly large capacitance is required to maintain a constant voltage required to store the data of the SRAM for a predetermined time when the power is off.
In the drawings and the following detailed description, the same or similar elements are denoted by the same reference.