1. Field of the Invention
The present invention relates to a microprocessor with a cache memory in which debugging operations are supported, and, in particular, to a microprocessor with a cache memory in which functions for implementing debugging operations are improved.
2. Description of the Background Art
Debugging operations are generally executed to debug in programming in a microprocessor applied system to develop the system.
In detail, a program stored in the system is actually executed before the debugging operations are executed. Thereafter, for example, pieces of data transmitted on an external bus connected to an external memory are monitored. The execution of the program is braked when arithmetic processing is advanced to a designated address or when designated conditions such as access to a piece of designated data are accomplished. After braking the execution of the program, contents of registers and memories are displayed. Also, instructions executed during the arithmetic processing are listed up. Therefore, an operator can debug the program stored in the program.
In this case, the system is generally provided with a plurality of microprocessors which are connected with a cache memory, an arithmetic unit and a control unit. In addition, the system is provided with an external memory connected with the microprocessors to store a large pieces of data, and external buses through which pieces of data, instructions or addresses are transmitted between the microprocessors and/or between the microprocessor and the external memory.
However, there are drawbacks to execute the debugging operations in cases where a program executed in a microprocessor with a cache memory is debugged.
That is, the debugging operations are initially executed according to normal operations.
In detail, in cases where a piece of data is stored at an address of the cache memory, an address hit occurs in the microprocessor when the address is accessed by the arithmetic unit during the execution of the program. Thereafter, under control of the control section, the data stored at the address is read out from the cache memory to utilize in the arithmetic unit or is rewritten to another piece of data which is made in the arithmetic unit. Therefore, an operation accessing to the external memory is not executed in the microprocessor. In other words, instructions or pieces of data transmitted between the cache memory and the arithmetic unit cannot be detected even though the operation accessed from the microprocessor to the external bus is monitored.
On the other hand, in cases where a piece of data is not stored at an address of the cache memory, a cache miss occurs in the microprocessor when the data is accessed by the arithmetic unit during the execution of the program. Thereafter, the data is fetched from the external memory through the external bus to store at the address of the cache memory.
The above debugging operations are executed in the same manner as the normal operations.
In this case, the data transmitted on the external bus is monitored by a data detector. Therefore, in cases where the arithmetic processing executed in the arithmetic unit is scheduled to be braked according to the debugging operations when a piece of data DA0 relating to the cache miss is fetched from the external memory, the data DA0 is detected when the data DA0 is transmitted on the external bus. This operation is one of the debugging operations and is not executed in the normal operation.
Accordingly, the arithmetic processing executed in the arithmetic unit can be braked to debug the program executed in the arithmetic unit.
However, it has been recently required to improve the speed of the arithmetic processing during the normal operation. Therefore, in cases where the cache miss occurs, a group of pieces of data is fetched in a block unit from the external memory to improve the speed of the arithmetic processing. The pieces of data fetched in a block unit are likely to be utilized in the arithmetic unit in serial order.
Therefore, as shown in FIG. 1, in cases where the arithmetic processing executed in the arithmetic unit is scheduled to be braked according to the debugging operations when a piece of data DA2 relating to the cache miss is fetched from the external memory, a data signal requiring a piece of data DA1 is, for example, transmitted to the external memory through an external bus when the data DA1 is accessed by the arithmetic unit in the microprocessor and a cache miss occurs. Thereafter, a group of sequential pieces of data DA1 to DA4 is fetched from the external memory into the cache memory in serial order. That is, the sequential pieces of data DA1 to DA4 are stored at addresses AD1 to AD4 of the cache memory. In this case, the data DA2 is not detected by a data detector because the data DA2 is not required by the data signal even though the data DA2 is fetched into the cache memory from the external memory.
Thereafter, the data DA1 stored at the address AD1 of the cache memory is read out from the cache memory to utilize for the arithmetic processing in the arithmetic unit. Thereafter, the data DA2 stored at the address AD2 of the cache memory is read out from the cache memory without the occurance of the cache miss.
Therefore, it is impossible to specify the data DA2 accessed by the arithmetic unit in the microprocessor even though data signals transmitted through the external bus are monitorred without monitorring a piece of data processed in the arithmetic unit.
Also, even though the data DA2 is detected by the data detector when the sequential pieces of data DA1 to DA4 are stored at addresses AD1 to AD4 of the cache memory, the data DA2 is not necessarily read out by the arithmetic unit after the data DA1 is read out by the arithmetic unit. Therefore, when the arithmetic processing is braked for the debugging operations, the program executed in the arithmetic unit is stopped at a step not relating to the data DA2.
As mentioned above, even though the arithmetic processing executed in the arithmetic unit is scheduled to be braked for the debugging operations when the data DA2 relating to the cache miss is read out from the cache memory to the arithmetic unit, it is impossible to specify the data DA2 because the sequential pieces of data including the data DA2 are fetched in a block unit.
Accordingly, the efficiency for specifying the data for the debugging operations deteriorates, and it is impossible to reliably specify which step is executed in the program.
Therefore, it is impossible to immediately brake the arithmetic processing according to an interruption operation of the debugging operations when the data DA2 relating to the cache miss is read out from the cache memory after the data DA2 is fetched from the external memory. That is, it is difficult to sufficiently execute the debugging operations.
On the other hand, there is another method that the microprocessor is operated according to simplified operations in which the cache memory is not used when the debugging operations are executed to prevent the efficiency for specifying the data DA2 from deteriorating.
However, the frequency that pieces of data are transmitted to the external bus according to the simplified operations is different from that in the normal operations in which the cache memory is used. In addition, the execution time of the program in the simplified operations is also different from that in the normal operations.
Therefore, there is a drawback that the debug operations cannot be efficiently executed while executing the normal operations.