In the development of integrated electronic circuits it is important to verify proper operation before committing a design to an expensive build process. Such verifications may include extracting parasitic circuit information such as capacitance, resistance and inductance. As chips become larger and more complex, time required for performing such extractions may also increase. Therefore, for advanced processes it may be desirable to be able to incrementally extract parasitic information. That is, if a designer changed only a portion of the design and a previous complete extraction exists, it may be desirable to extract only the portion of the design that is affected by the designer's change and merge these results with the previously existing complete extraction.
A potential problem of incremental extraction is that the relationship between the incremental portion and the rest of the chip may not be preserved. For instance, if only a few shapes of a net are changed and re-extracted, knowing where to insert the changed portion into the original circuit description/netlist of the changed net may be difficult. Similarly, if the new shapes capacitively couple to the old/existing shapes, exactly where to connect in the netlist of the old shapes may be difficult to determine.