This invention relates to a non-volatile semiconductor memory device.
A ROM capable of electrically erasing the stored contents and rewriting them is known as an EEPROM (Electrically Erasable Programmable ROM). Unlike EPROMs of the ultraviolet light erasable type, such EEPROMs mounted on a board can erase data by an electric signal alone. For this reason, EEPROMs are frequently used for various controls or memory cards.
FIG. 1 is a cross sectional view showing the device structure of a typical memory cell in the EEPROM, and FIG. 2 is an equivalent circuit diagram thereof. In FIG. 1, for example, on a P-type substrate 80, N-type diffused regions 91, 92 and 93 are provided. Between the diffused regions 91 and 92 on the substrate 80, a floating gate electrode 95 formed of a polycrystalline silicon layer of the first layer is provided on an insulating oxide film 94. This floating gate electrode 95 overlaps with the N-type diffused region 92 through a thin film portion 94A of the insulating oxide film 94. On the floating gate electrode 95, a gate electrode 97 formed of a polycrystalline silicon layer of the second layer is provided on an insulating oxide film 96. Further, between the diffused regions 92 and 93 on the substrate 80, a gate electrode 99 formed of a polycrystalline silicon layer is provided on an insulating oxide film 98.
The memory cell of FIG. 1 includes two transistors 1 and 2. Namely, one is a transistor 2 having a floating gate (called floating gate transistor hereinafter) as a non-volatile memory element having the N-type diffused region 91 as the source, the N-type diffused region 92 as the drain, the floating gate electrode 95 as the floating gate, and the gate electrode 97 as the control gate. The other is a select transistor 1 of enhancement type having the N-type diffused region 92 as the source, the N-type diffused region 93 as the drain, and the gate electrode 99 as the gate. These transistors 1 and 2 are connected in series. As indicated by the equivalent circuit of FIG. 2, the drain and the gate of the transistor 1 are used as the data line DL and the word line WL, respectively. The floating gate and the control gate of the floating gate transistor 2 are used as the floating gate FG and the control gate CG, respectively, and the source of the floating gate transistor 2 is used as the source S. It is to be noted that the memory cell of FIG. 1 constitutes a one bit data memory unit (memory element) for storing data of one bit.
In the memory cell using a floating gate transistor as described above, as long as data erasing is not conducted, data once written is permanently held from an ideal point of view. However, in the case of an actual memory cell, after erasing or writing of data is carried out, charges in the floating gate are discharged with the lapse of time, and the stored data disappears. Particularly in the case of a cell where there is some defect in an insulating oxide film, etc., this charge dissipation occurs to a considerable degree. According to these circumstances, the memory cell becomes defective when used.
Generally, as a technique for evaluating the holding characteristic of stored data, there is known a method of placing the memory cell in a high temperature state to accelerate the rate of occurrence of such deterioration. This method is called a high temperature shelf test. FIG. 3 is a characteristic curve showing changes in the threshold voltage (V.sub.th) of the floating gate transistor when the high temperature shelf test is conducted at 300.degree. C. The threshold voltage in an initial state is about 1 volt as indicated by a broken line.
The case where electrons are discharged from the floating gate to store data of the "0" level will be first described. At this time, the threshold voltage of the floating gate transistor takes a substantially negative value, e.g., -5 volts. For this reason, a current flows even if the potential on the control gate is zero volts.
The case where electrons are injected into the floating gate to store data of "1" level will now be described. The threshold voltage of the floating gate transistor takes a substantially high value, e.g., +10 volts.
At the time of readout of data, the potential on the control gate is set to zero volts. The judgment as to whether the data stored in the memory cell is "0" or "1" is carried out by setting the operating point of the sense amplifier circuit, i.e., sense potential so that a suitable current flows in the memory cell. This sense potential is set to about -1 volt as indicated by the single dotted lines.
In FIG. 3, in the case of the cell of "1" data, electrons in the floating gate are discharged with the lapse of time. Thus, the threshold voltage thereof lowers with the lapse of time to reach 1 volt, which is the threshold voltage in the initial state. On the other hand, in the case of the cell of "0" data, electrons are injected into the floating gate with the lapse of time. Thus, the threshold voltage rises with the lapse of time to reach 1 volt. At the time t.sub.N in the middle thereof, that threshold voltage goes through '1 volt, which is the sense potential of the sense amplifier circuit.
FIG. 4 shows the change of the cell current (I.sub.cell) at the time of the high temperature shelf test of the memory cell in which "0" level data is stored. With the lapse of time, the cell current decreases. When the cell current is below the sense level current Is in the sense amplifier circuit, the sense amplifier circuit erroneously judges data which has been originally at the "0" level to be "1" level data. It is only the memory cells in which "0" level data is stored, that data may be erroneously detected as stated above. The time when such an erroneous data is detected is now assumed to be t.sub.N. In the case of the normal memory cell, the time required for reaching the time t.sub.N is sufficiently long, and there is therefore no problem in view of actual use. However, in the case of the defective memory cell, the time required for reaching the time t.sub.N is small. For this reason, there are instances where memory cells may become inferior or defective while they are being used in a product. Particularly, if erasing and/or writing are frequently repeated, the insulating oxide film is considerably deteriorated, so inferiority is apt to occur.
FIG. 5 is a circuit diagram of a conventional typical EEPROM in which memory cells similar to the memory cell shown by the equivalent circuit of FIG. 2 are used to constitute a cell array. The control gates of the floating gate transistors 2 of memory cells MC-11 to MC-mn are connected to control gate select lines CGL1 to CGLn selected by column decoders 5-1 to 5-n through control gate select transistors 6. Further, the gate of the control gate select transistor 6 and the gate of the select transistor 1 in each same memory cell are both connected to one of the row lines WL1 to WLm selected by the row decoder 4. Drains of the select transistors 1 in respective memory cells are connected to column lines DL1 to DLn. Respective column lines DL1 to DLn are connected in common to a bus line 8 through column select transistors 7. The gates of the transistors 7 are connected to the corresponding column decoders 5 through column select lines CL1 to CLn, respectively. To the bus line 8, a data input circuit 9 and a sense amplifier circuit 10 are connected. The data input circuit 9 outputs data of "0" or "1" level depending on a write data signal Din inputted from the outside. The sense amplifier circuit 10 detects, as "0" or "1", the level of data stored in a selected memory cell MC. At the time of sensing the data level, the sense amplifier circuit 10 applies a bias voltage necessary for the readout of data to a corresponding data line DL. Namely, the sense amplifier circuit 10 includes a bias circuit.
The data sensed at the sense amplifier circuit 10 is inputted to a data output circuit 12. Readout data is outputted from the data output circuit 12 to the outside.
In EEPROMs of such a structure, in the case where erasing/writing were conducted about 10.sup.3 times with a device of a memory capacity of the order of 64K bits, the possibility that there takes place random cell inferiority in every bit due to defects as described above, etc., indicates a high value of about 0.1 to 0.2%. For this reason, there was the drawback that the reliability is low, leading to limited use from a viewpoint of the practical use.
To prevent lowering of the reliability due to cell inferiority, a technique is conceivable to constitute each storage unit with two memory cells. However, the memory cell corresponding to 1 bit becomes large, resulting in that such a technique is not suitable for implementation of large capacity memory devices.