import hdltools.vhdl_gen as vhdl_gen
import hdltools.pkgvhdl_gen as pkgvhdl_gen
import hdltools.regbank_gen as regbank_gen

BasicVHDL = vhdl_gen.BasicVHDL
PkgVHDL = pkgvhdl_gen.PkgVHDL
RegisterBank = regbank_gen.RegisterBank
import hdltools.vhdl_gen as vhdl_gen
import hdltools.pkgvhdl_gen as pkgvhdl_gen
import hdltools.regbank_gen as regbank_gen

BasicVHDL = vhdl_gen.BasicVHDL
PkgVHDL = pkgvhdl_gen.PkgVHDL
RegisterBank = regbank_gen.RegisterBank