<filename>HDPython/examples/axi_stream_delay.py

import unittest
import functools
import argparse
import os,sys,inspect
import copy

from HDPython.base import *
from HDPython.v_symbol import *
from HDPython.examples.axiStream import *
from HDPython.v_entity import *
from HDPython.v_list import *



class stream_delay_one(v_clk_entity):
    def __init__(self,clk=v_sl(),itype =v_slv(32),Index = 0):
        super().__init__(clk)
        self.Axi_in = port_Stream_Slave(axisStream(itype))
        self.Axi_out = port_Stream_Master(axisStream(itype))
        self.Index = Index
        self.architecture()

        
    def architecture(self):
        axiSalve = get_salve(self.Axi_in)
        axMaster = get_master(self.Axi_out) 

        @rising_edge(self.clk)
        def proc():
            if axiSalve and axMaster:
                axiSalve >> axMaster 
                axMaster.Send_end_Of_Stream( axiSalve.IsEndOfStream())


        end_architecture()


class stream_delay(v_clk_entity):
    def __init__(self,clk=None,itype =v_slv(32),depth=10):
        super().__init__(clk)
        self.Axi_in = port_Stream_Slave(axisStream(itype))
        self.Axi_out = port_Stream_Master(axisStream(itype))
        self.depth = v_const(v_int(depth))
        self.array_size  = v_const(v_int(2**value(depth) ))
        self.architecture()



    def architecture(self):
        
        pipe1 = self.Axi_in \
            |  stream_delay_one(self.clk,  self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            | \
        self.Axi_out

        end_architecture()


<filename>HDPython/examples/axi_stream_delay.py

import unittest
import functools
import argparse
import os,sys,inspect
import copy

from HDPython.base import *
from HDPython.v_symbol import *
from HDPython.examples.axiStream import *
from HDPython.v_entity import *
from HDPython.v_list import *



class stream_delay_one(v_clk_entity):
    def __init__(self,clk=v_sl(),itype =v_slv(32),Index = 0):
        super().__init__(clk)
        self.Axi_in = port_Stream_Slave(axisStream(itype))
        self.Axi_out = port_Stream_Master(axisStream(itype))
        self.Index = Index
        self.architecture()

        
    def architecture(self):
        axiSalve = get_salve(self.Axi_in)
        axMaster = get_master(self.Axi_out) 

        @rising_edge(self.clk)
        def proc():
            if axiSalve and axMaster:
                axiSalve >> axMaster 
                axMaster.Send_end_Of_Stream( axiSalve.IsEndOfStream())


        end_architecture()


class stream_delay(v_clk_entity):
    def __init__(self,clk=None,itype =v_slv(32),depth=10):
        super().__init__(clk)
        self.Axi_in = port_Stream_Slave(axisStream(itype))
        self.Axi_out = port_Stream_Master(axisStream(itype))
        self.depth = v_const(v_int(depth))
        self.array_size  = v_const(v_int(2**value(depth) ))
        self.architecture()



    def architecture(self):
        
        pipe1 = self.Axi_in \
            |  stream_delay_one(self.clk,  self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            |   stream_delay_one(self.clk, self.Axi_in.data) \
            | \
        self.Axi_out

        end_architecture()

