#!/usr/bin/python
import os
import sys
import getopt
import shutil


def printProgramBanner():
    print("--------------------------------")
    print("Starting Python runtest script")
    print("--------------------------------")


def printUsage():
    print("test.py -h -g -v -G <gatesim_Type> -t <testname>")


def createSimDir(directory):
    # run the verification model for the testcase to generate expected results and to create stimulus file
    testpath = os.path.join(os.curdir, directory)
    if (os.path.isdir(testpath)):
        print("Directory exists, deleteing old " + directory)
        shutil.rmtree(directory)

    print("Making new directory " + directory)
    os.mkdir(directory)


def convertBDF(testdir):
    RTL_FOLDER_PATH = os.path.join(os.curdir, "..", "firmware")
    RTL_SIM_FOLDER_PATH = os.path.join(
        os.curdir, testdir, "autogenerated_from_bdf_for_sim_only")
    QUARTUS_EXE_PATH = os.path.abspath(os.path.join(
        os.sep, "intelFPGA_lite", "18.1", "quartus", "bin64", "quartus_map.exe"))

    print("Copying BDF RTL files from RTL directory")
    for basename in os.listdir(RTL_FOLDER_PATH):
        if basename.endswith(".bdf"):
            pathname = os.path.join(RTL_FOLDER_PATH, basename)
            if os.path.isfile(pathname):
                shutil.copy2(pathname, RTL_SIM_FOLDER_PATH)

    os.chdir(RTL_SIM_FOLDER_PATH)
    for bdf_file in os.listdir(os.curdir):
        print("\n--------------------------------")
        print("Compiling " + bdf_file + " from bdf to VHDL...")
        os.system(QUARTUS_EXE_PATH +
                  " --read_settings_files=on --write_settings_files=off dco_synth -c dco_synth --convert_bdf_to_vhdl=" + bdf_file)
        print("--------------------------------\n")
    os.chdir(os.path.join("..", ".."))


def cleanTestDir(testcase):
    if os.path.isfile(testcase + ".FAIL"):
        shutil.rmtree(testcase + ".FAIL")

    if os.path.isfile(testcase + ".pass"):
        shutil.rmtree(testcase + ".pass")

    if os.path.isfile("vsim.wlf"):
        shutil.rmtree("vsim.wlf")

    if os.path.isfile("vsim.log"):
        shutil.rmtree("vsim.log")

    if os.path.isdir("work"):
        shutil.rmtree("work")


def compileToVHDL(src, cover):
    # VHDL compiler command
    # vcom -f $src -2008 $cover -l compile.log -lint -nologo
    print("vcom -f " + src + " -2008 " + cover + "-l compile.log -lint -nologo")
    os.system("vcom -f " + src + " -2008 " +
              cover + "-l compile.log -lint -nologo")


def compileToVerilog(src, cover):
    # Verilog compiler command
    # vlog -f $src $cover -l compile.log -lint -nologo -sv $define
    print("vlog -f " + src + " " + cover + " -l compile.log -lint -nologo")
    os.system("vlog -f " + src + " " + cover + " -l compile.log -lint -nologo")


def runSim(testcase, gui, coverstore, sdf, log, vcd, wave, quit, wavefile):
    # print("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
    #       " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile)
    # os.system("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
    #           " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile)
    print("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
          " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log ")
    os.system("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
              " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log ")


def main(argv):

    printProgramBanner()

    print("Initializing Options...")

    # initialize options
    define = "+define+SIM=1"
    gui = "-c"
    quit = "quit"
    runTheSim = 1
    cover = ""
    coverstore = ""
    vcd = ""
    wave = ""
    wavefile = "-wlf vsim.wlf"
    log = "log -r /*"

    sdf = ""
    src = os.path.join("..", "testbench.f")
    testcase = ""
    compileBDF = False

    # setup getopt
    try:
        opts, args = getopt.getopt(
            argv, "hCcgvGb:t:", ["help=", "compile=", "coverage=", "gui=", "vcd=", "Gatesim=", "bdf=", "test="])
    except getopt.GetoptError:
        printUsage()
        sys.exit(2)

    for opt, arg in opts:
        if opt in ("-h", "--help"):
            printUsage()
            sys.exit()

        elif opt in ("-b", "--bdf"):
            compileBDF = True

        elif opt in ("-C", "--compile"):
            runTheSim = 0

        elif opt in ("-c", "--coverage"):
            print("-c is not supported")
            printUsage()
            sys.exit()

        elif opt in ("-g", "--gui"):
            gui = "-gui"
            quit = ""

        elif opt in ("-v", "--vcd"):
            vcd = "vcd file vsim.vcd"

        elif opt in ("-G", "--Gatesim"):
            pass

        elif opt in ("-t", "--test"):
            testcase = arg
            src = os.path.join("..", testcase + ".f")
            wavefile = os.path.join("..", testcase + "_wave.do")

        else:
            print("ERROR: unknown option" + opt)
            printUsage()
            sys.exit(2)

    createSimDir(testcase)
    createSimDir(os.path.join(testcase, "autogenerated_from_bdf_for_sim_only"))

    if (compileBDF == True):
        convertBDF(testcase)

    os.chdir(testcase)
    cleanTestDir(testcase)
    os.system("vlib work")

    # compileToVHDL(src, cover)
    compileToVerilog(src, cover)

    # sim command
    if (runTheSim == 1):
        runSim(testcase, gui, coverstore, sdf, log, vcd, wave, quit, wavefile)

    os.chdir("..")


if __name__ == "__main__":
    main(sys.argv[1:])

#!/usr/bin/python
import os
import sys
import getopt
import shutil


def printProgramBanner():
    print("--------------------------------")
    print("Starting Python runtest script")
    print("--------------------------------")


def printUsage():
    print("test.py -h -g -v -G <gatesim_Type> -t <testname>")


def createSimDir(directory):
    # run the verification model for the testcase to generate expected results and to create stimulus file
    testpath = os.path.join(os.curdir, directory)
    if (os.path.isdir(testpath)):
        print("Directory exists, deleteing old " + directory)
        shutil.rmtree(directory)

    print("Making new directory " + directory)
    os.mkdir(directory)


def convertBDF(testdir):
    RTL_FOLDER_PATH = os.path.join(os.curdir, "..", "firmware")
    RTL_SIM_FOLDER_PATH = os.path.join(
        os.curdir, testdir, "autogenerated_from_bdf_for_sim_only")
    QUARTUS_EXE_PATH = os.path.abspath(os.path.join(
        os.sep, "intelFPGA_lite", "18.1", "quartus", "bin64", "quartus_map.exe"))

    print("Copying BDF RTL files from RTL directory")
    for basename in os.listdir(RTL_FOLDER_PATH):
        if basename.endswith(".bdf"):
            pathname = os.path.join(RTL_FOLDER_PATH, basename)
            if os.path.isfile(pathname):
                shutil.copy2(pathname, RTL_SIM_FOLDER_PATH)

    os.chdir(RTL_SIM_FOLDER_PATH)
    for bdf_file in os.listdir(os.curdir):
        print("\n--------------------------------")
        print("Compiling " + bdf_file + " from bdf to VHDL...")
        os.system(QUARTUS_EXE_PATH +
                  " --read_settings_files=on --write_settings_files=off dco_synth -c dco_synth --convert_bdf_to_vhdl=" + bdf_file)
        print("--------------------------------\n")
    os.chdir(os.path.join("..", ".."))


def cleanTestDir(testcase):
    if os.path.isfile(testcase + ".FAIL"):
        shutil.rmtree(testcase + ".FAIL")

    if os.path.isfile(testcase + ".pass"):
        shutil.rmtree(testcase + ".pass")

    if os.path.isfile("vsim.wlf"):
        shutil.rmtree("vsim.wlf")

    if os.path.isfile("vsim.log"):
        shutil.rmtree("vsim.log")

    if os.path.isdir("work"):
        shutil.rmtree("work")


def compileToVHDL(src, cover):
    # VHDL compiler command
    # vcom -f $src -2008 $cover -l compile.log -lint -nologo
    print("vcom -f " + src + " -2008 " + cover + "-l compile.log -lint -nologo")
    os.system("vcom -f " + src + " -2008 " +
              cover + "-l compile.log -lint -nologo")


def compileToVerilog(src, cover):
    # Verilog compiler command
    # vlog -f $src $cover -l compile.log -lint -nologo -sv $define
    print("vlog -f " + src + " " + cover + " -l compile.log -lint -nologo")
    os.system("vlog -f " + src + " " + cover + " -l compile.log -lint -nologo")


def runSim(testcase, gui, coverstore, sdf, log, vcd, wave, quit, wavefile):
    # print("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
    #       " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile)
    # os.system("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
    #           " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile)
    print("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
          " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log ")
    os.system("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase +
              " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log ")


def main(argv):

    printProgramBanner()

    print("Initializing Options...")

    # initialize options
    define = "+define+SIM=1"
    gui = "-c"
    quit = "quit"
    runTheSim = 1
    cover = ""
    coverstore = ""
    vcd = ""
    wave = ""
    wavefile = "-wlf vsim.wlf"
    log = "log -r /*"

    sdf = ""
    src = os.path.join("..", "testbench.f")
    testcase = ""
    compileBDF = False

    # setup getopt
    try:
        opts, args = getopt.getopt(
            argv, "hCcgvGb:t:", ["help=", "compile=", "coverage=", "gui=", "vcd=", "Gatesim=", "bdf=", "test="])
    except getopt.GetoptError:
        printUsage()
        sys.exit(2)

    for opt, arg in opts:
        if opt in ("-h", "--help"):
            printUsage()
            sys.exit()

        elif opt in ("-b", "--bdf"):
            compileBDF = True

        elif opt in ("-C", "--compile"):
            runTheSim = 0

        elif opt in ("-c", "--coverage"):
            print("-c is not supported")
            printUsage()
            sys.exit()

        elif opt in ("-g", "--gui"):
            gui = "-gui"
            quit = ""

        elif opt in ("-v", "--vcd"):
            vcd = "vcd file vsim.vcd"

        elif opt in ("-G", "--Gatesim"):
            pass

        elif opt in ("-t", "--test"):
            testcase = arg
            src = os.path.join("..", testcase + ".f")
            wavefile = os.path.join("..", testcase + "_wave.do")

        else:
            print("ERROR: unknown option" + opt)
            printUsage()
            sys.exit(2)

    createSimDir(testcase)
    createSimDir(os.path.join(testcase, "autogenerated_from_bdf_for_sim_only"))

    if (compileBDF == True):
        convertBDF(testcase)

    os.chdir(testcase)
    cleanTestDir(testcase)
    os.system("vlib work")

    # compileToVHDL(src, cover)
    compileToVerilog(src, cover)

    # sim command
    if (runTheSim == 1):
        runSim(testcase, gui, coverstore, sdf, log, vcd, wave, quit, wavefile)

    os.chdir("..")


if __name__ == "__main__":
    main(sys.argv[1:])

#!/usr/bin/python # run the verification model for the testcase to generate expected results and to create stimulus file # VHDL compiler command # vcom -f $src -2008 $cover -l compile.log -lint -nologo # Verilog compiler command # vlog -f $src $cover -l compile.log -lint -nologo -sv $define # print("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase + #       " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile) # os.system("vsim tb_" + testcase + " " + gui + " " + coverstore + " " + sdf + "-testname " + testcase + #           " -do \"" + log + "; " + vcd + "; " + wave + "; run -a; " + quit + "\" -l vsim.log " + wavefile) # initialize options # setup getopt # compileToVHDL(src, cover) # sim command