0001-Add-Litex-VexRiscv-support.patch

From e7e0c7db1d4ac7a665382f660f0f54c006d24336 Mon Sep 17 00:00:00 2001
From: Karol Gugala <[email protected]>
Date: Mon, 13 May 2019 13:57:06 +0200
Subject: [PATCH] Add Litex/VexRiscv support

---
 board/litex_vexriscv/linux.config                  |  30 ++
 .../litex_vexriscv/linux_add_liteeth_driver.patch  | 466 +++++++++++++++++++++
 board/litex_vexriscv/litex_vexriscv.dts            |  85 ++++
 board/litex_vexriscv/litex_vexriscv_arty.dts       |  85 ++++
 board/litex_vexriscv/litex_vexriscv_genesys2.dts   |  85 ++++
 board/litex_vexriscv/litex_vexriscv_kcu105.dts     |  85 ++++
 .../litex_vexriscv/litex_vexriscv_minispartan6.dts |  85 ++++
 board/litex_vexriscv/litex_vexriscv_netv2.dts      |  85 ++++
 board/litex_vexriscv/litex_vexriscv_nexys4ddr.dts  |  85 ++++
 board/litex_vexriscv/litex_vexriscv_ulx3s.dts      |  85 ++++
 board/litex_vexriscv/litex_vexriscv_versa_ecp5.dts |  85 ++++
 board/litex_vexriscv/rootfs_overlay/etc/motd       |   9 +
 board/litex_vexriscv/rootfs_overlay/etc/profile    |  20 +
 configs/litex_vexriscv_defconfig                   |  13 +
 14 files changed, 1303 insertions(+)
 create mode 100644 board/litex_vexriscv/linux.config
 create mode 100644 board/litex_vexriscv/linux_add_liteeth_driver.patch
 create mode 100644 board/litex_vexriscv/litex_vexriscv.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_arty.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_genesys2.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_kcu105.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_minispartan6.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_netv2.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_nexys4ddr.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_ulx3s.dts
 create mode 100644 board/litex_vexriscv/litex_vexriscv_versa_ecp5.dts
 create mode 100644 board/litex_vexriscv/rootfs_overlay/etc/motd
 create mode 100644 board/litex_vexriscv/rootfs_overlay/etc/profile
 create mode 100644 configs/litex_vexriscv_defconfig

diff --git a/board/litex_vexriscv/linux.config b/board/litex_vexriscv/linux.config
new file mode 100644
index 0000000..de8819f
--- /dev/null
+++ b/board/litex_vexriscv/linux.config
@@ -0,0 +1,30 @@
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+
+# Architecture
+CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
+CONFIG_ARCH_RV32I=y
+CONFIG_RISCV_ISA_M=y
+CONFIG_RISCV_ISA_A=y
+CONFIG_RISCV_ISA_C=n
+CONFIG_SIFIVE_PLIC=y
+CONFIG_FPU=n
+CONFIG_SMP=n
+
+CONFIG_HVC_RISCV_SBI=y
+
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+
+#CONFIG_NET=y
+#CONFIG_INET=y
+#CONFIG_NETDEVICES=y
+#CONFIG_NET_VENDOR_LITEX=y
+#CONFIG_LITEX_LITEETH=y
+
+CONFIG_PRINTK_TIME=y
diff --git a/board/litex_vexriscv/linux_add_liteeth_driver.patch b/board/litex_vexriscv/linux_add_liteeth_driver.patch
new file mode 100644
index 0000000..d15d50f
--- /dev/null
+++ b/board/litex_vexriscv/linux_add_liteeth_driver.patch
@@ -0,0 +1,466 @@
+diff -uNr linux-5.0.11/drivers/net/ethernet/Kconfig linux-5.0.11-liteeth/drivers/net/ethernet/Kconfig
+--- linux-5.0.11/drivers/net/ethernet/Kconfig	2019-05-06 13:01:32.254348532 +0100
++++ linux-5.0.11-liteeth/drivers/net/ethernet/Kconfig	2019-05-06 13:04:47.297358187 +0100
+@@ -115,6 +115,7 @@
+ 	  Support for the PMAC of the Gigabit switch (GSWIP) inside the
+ 	  Lantiq / Intel VRX200 VDSL SoC
+ 
++source "drivers/net/ethernet/litex/Kconfig"
+ source "drivers/net/ethernet/marvell/Kconfig"
+ source "drivers/net/ethernet/mediatek/Kconfig"
+ source "drivers/net/ethernet/mellanox/Kconfig"
+diff -uNr linux-5.0.11/drivers/net/ethernet/litex/Kconfig linux-5.0.11-liteeth/drivers/net/ethernet/litex/Kconfig
+--- linux-5.0.11/drivers/net/ethernet/litex/Kconfig	1970-01-01 01:00:00.000000000 +0100
++++ linux-5.0.11-liteeth/drivers/net/ethernet/litex/Kconfig	2019-05-06 13:03:36.607478986 +0100
+@@ -0,0 +1,27 @@
++#
++# LiteX device configuration
++#
++
++config NET_VENDOR_LITEX
++	bool "LiteX devices"
++	default y
++	---help---
++	  If you have a network (Ethernet) card belonging to this class, say Y.
++
++	  Note that the answer to this question doesn't directly affect the
++	  kernel: saying N will just cause the configurator to skip all
++	  the questions about LiteX devices. If you say Y, you will be asked
++	  for your specific card in the following questions.
++
++if NET_VENDOR_LITEX
++
++config LITEX_LITEETH
++	tristate "LiteX Ethernet support"
++	select NET_CORE
++	select MII
++	select PHYLIB
++	---help---
++	  If you wish to compile a kernel for hardware with a LiteX LiteEth
++	  device then you should answer Y to this.
++
++endif # NET_VENDOR_LITEX
+diff -uNr linux-5.0.11/drivers/net/ethernet/litex/litex_liteeth.c linux-5.0.11-liteeth/drivers/net/ethernet/litex/litex_liteeth.c
+--- linux-5.0.11/drivers/net/ethernet/litex/litex_liteeth.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-5.0.11-liteeth/drivers/net/ethernet/litex/litex_liteeth.c	2019-05-06 14:11:58.028388249 +0100
+@@ -0,0 +1,400 @@
++/*
++ * LiteX Liteeth Ethernet
++ *
++ * Copyright 2017 Joel Stanley <[email protected]>
++ *
++ */
++
++#include <linux/etherdevice.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/of_address.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#include <linux/iopoll.h>
++
++#define DRV_NAME	"liteeth"
++#define DRV_VERSION	"0.1"
++
++#define LITEETH_WRITER_SLOT		0x00
++#define LITEETH_WRITER_LENGTH		0x04
++#define LITEETH_WRITER_ERRORS		0x14
++#define LITEETH_WRITER_EV_STATUS	0x24
++#define LITEETH_WRITER_EV_PENDING	0x28
++#define LITEETH_WRITER_EV_ENABLE	0x2c
++#define LITEETH_READER_START		0x30
++#define LITEETH_READER_READY		0x34
++#define LITEETH_READER_LEVEL		0x38
++#define LITEETH_READER_SLOT		0x3c
++#define LITEETH_READER_LENGTH		0x40
++#define LITEETH_READER_EV_STATUS	0x48
++#define LITEETH_READER_EV_PENDING	0x4c
++#define LITEETH_READER_EV_ENABLE	0x50
++#define LITEETH_PREAMBLE_CRC		0x54
++#define LITEETH_PREAMBLE_ERRORS		0x58
++#define LITEETH_CRC_ERRORS		0x68
++
++#define LITEETH_PHY_CRG_RESET		0x00
++#define LITEETH_MDIO_W			0x04
++#define LITEETH_MDIO_R			0x08
++
++#define LITEETH_BUFFER_SIZE		0x800
++#define MAX_PKT_SIZE			LITEETH_BUFFER_SIZE
++
++struct liteeth {
++	void __iomem *base;
++	void __iomem *mdio_base;
++	struct net_device *netdev;
++	struct device *dev;
++	struct mii_bus *mii_bus;
++
++	/* Link management */
++	int cur_duplex;
++	int cur_speed;
++
++	/* Tx */
++	int tx_slot;
++	int num_tx_slots;
++	void __iomem *tx_base;
++
++	/* Rx */
++	int rx_slot;
++	int num_rx_slots;
++	void __iomem *rx_base;
++};
++
++/* Helper routines for accessing MMIO over a wishbone bus.
++ * Each 32 bit memory location contains a single byte of data, stored
++ * little endian
++ */
++static inline void outreg8(u8 val, void __iomem *addr)
++{
++	iowrite32(val, addr);
++}
++
++static inline void outreg16(u16 val, void __iomem *addr)
++{
++	outreg8(val >> 8, addr);
++	outreg8(val, addr + 4);
++}
++
++static inline u8 inreg8(void __iomem *addr)
++{
++	return ioread32(addr);
++}
++
++static inline u32 inreg32(void __iomem *addr)
++{
++	return (inreg8(addr) << 24) |
++		(inreg8(addr + 0x4) << 16) |
++		(inreg8(addr + 0x8) <<  8) |
++		(inreg8(addr + 0xc) <<  0);
++}
++
++static int liteeth_rx(struct net_device *netdev)
++{
++	struct liteeth *priv = netdev_priv(netdev);
++	struct sk_buff *skb;
++	unsigned char *data;
++	u8 rx_slot;
++	int len;
++
++	rx_slot = inreg8(priv->base + LITEETH_WRITER_SLOT);
++	len = inreg32(priv->base + LITEETH_WRITER_LENGTH);
++
++	skb = netdev_alloc_skb(netdev, len + NET_IP_ALIGN);
++	if (!skb) {
++		netdev_err(netdev, "couldn't get memory");
++		netdev->stats.rx_dropped++;
++		return NET_RX_DROP;
++	}
++
++	/* Ensure alignemnt of the ip header within the skb */
++	skb_reserve(skb, NET_IP_ALIGN);
++	if (len == 0 || len > 2048)
++		return NET_RX_DROP;
++	data = skb_put(skb, len);
++	memcpy_fromio(data, priv->rx_base + rx_slot * LITEETH_BUFFER_SIZE, len);
++	skb->protocol = eth_type_trans(skb, netdev);
++
++	netdev->stats.rx_packets++;
++	netdev->stats.rx_bytes += len;
++
++	return netif_rx(skb);
++}
++
++static void liteeth_tx_done(struct net_device *netdev)
++{
++	netdev->stats.tx_packets++;
++}
++
++static irqreturn_t liteeth_interrupt(int irq, void *dev_id)
++{
++	struct net_device *netdev = dev_id;
++	struct liteeth *priv = netdev_priv(netdev);
++	u8 reg;
++
++	reg = inreg8(priv->base + LITEETH_READER_EV_PENDING);
++	if (reg) {
++		liteeth_tx_done(netdev);
++		outreg8(reg, priv->base + LITEETH_READER_EV_PENDING);
++	}
++
++	reg = inreg8(priv->base + LITEETH_WRITER_EV_PENDING);
++	if (reg) {
++		liteeth_rx(netdev);
++		outreg8(reg, priv->base + LITEETH_WRITER_EV_PENDING);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int liteeth_open(struct net_device *netdev)
++{
++	struct liteeth *priv = netdev_priv(netdev);
++	int err;
++
++	/* TODO: Remove these once we have working mdio support */
++	priv->cur_duplex = DUPLEX_FULL;
++	priv->cur_speed = SPEED_100;
++	netif_carrier_on(netdev);
++
++	err = request_irq(netdev->irq, liteeth_interrupt, 0, netdev->name, netdev);
++	if (err) {
++		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
++		goto err_irq;
++	}
++
++	/* Clear pending events? */
++	outreg8(1, priv->base + LITEETH_WRITER_EV_PENDING);
++	outreg8(1, priv->base + LITEETH_READER_EV_PENDING);
++
++	/* Enable IRQs? */
++	outreg8(1, priv->base + LITEETH_WRITER_EV_ENABLE);
++	outreg8(1, priv->base + LITEETH_READER_EV_ENABLE);
++
++	netif_start_queue(netdev);
++
++	return 0;
++
++err_irq:
++	netif_carrier_off(netdev);
++	return err;
++}
++
++static int liteeth_stop(struct net_device *netdev)
++{
++	struct liteeth *priv = netdev_priv(netdev);
++
++	outreg8(0, priv->base + LITEETH_WRITER_EV_ENABLE);
++	outreg8(0, priv->base + LITEETH_READER_EV_ENABLE);
++
++	free_irq(netdev->irq, netdev);
++
++	return 0;
++}
++
++static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++	struct liteeth *priv = netdev_priv(netdev);
++	void *txbuffer;
++	int ret;
++	u8 val;
++
++	/* Reject oversize packets */
++	if (unlikely(skb->len > MAX_PKT_SIZE)) {
++		if (net_ratelimit())
++			netdev_dbg(netdev, "tx packet too big\n");
++		goto drop;
++	}
++
++	txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
++	memcpy_fromio(txbuffer, skb->data, skb->len);
++	outreg8(priv->tx_slot, priv->base + LITEETH_READER_SLOT);
++	outreg16(skb->len, priv->base + LITEETH_READER_LENGTH);
++
++	ret = readb_poll_timeout_atomic(priv->base + LITEETH_READER_READY,
++			val, val, 5, 1000);
++	if (ret == -ETIMEDOUT) {
++		netdev_err(netdev, "LITEETH_READER_READY timed out\n");
++		goto drop;
++	}
++
++	outreg8(1, priv->base + LITEETH_READER_START);
++
++	priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
++	dev_kfree_skb_any(skb);
++	return NETDEV_TX_OK;
++drop:
++	/* Drop the packet */
++	dev_kfree_skb_any(skb);
++	netdev->stats.tx_dropped++;
++
++	return NETDEV_TX_OK;
++}
++
++static void liteeth_get_drvinfo(struct net_device *netdev,
++				struct ethtool_drvinfo *info)
++{
++	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
++	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
++	strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
++}
++
++static const struct net_device_ops liteeth_netdev_ops = {
++	.ndo_open		= liteeth_open,
++	.ndo_stop		= liteeth_stop,
++	.ndo_start_xmit         = liteeth_start_xmit,
++};
++
++static const struct ethtool_ops liteeth_ethtool_ops = {
++	.get_drvinfo		= liteeth_get_drvinfo,
++	.get_link		= ethtool_op_get_link,
++	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
++	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
++	.nway_reset		= phy_ethtool_nway_reset,
++};
++
++static void liteeth_reset_hw(struct liteeth *priv)
++{
++	/* Reset, twice */
++	outreg8(0, priv->base + LITEETH_PHY_CRG_RESET);
++	udelay(10);
++	outreg8(1, priv->base + LITEETH_PHY_CRG_RESET);
++	udelay(10);
++	outreg8(0, priv->base + LITEETH_PHY_CRG_RESET);
++	udelay(10);
++}
++
++static int liteeth_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct net_device *netdev;
++	void __iomem *buf_base;
++	struct resource *res;
++	struct liteeth *priv;
++	const char *mac_addr;
++	int irq, err;
++
++	netdev = alloc_etherdev(sizeof(*priv));
++	if (!netdev)
++		return -ENOMEM;
++
++	priv = netdev_priv(netdev);
++	priv->netdev = netdev;
++	priv->dev = &pdev->dev;
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		dev_err(&pdev->dev, "Failed to get IRQ\n");
++		return irq;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	priv->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(priv->base)) {
++		err = PTR_ERR(priv->base);
++		goto err;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(priv->mdio_base)) {
++		err = PTR_ERR(priv->mdio_base);
++		goto err;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++	buf_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(buf_base)) {
++		err = PTR_ERR(buf_base);
++		goto err;
++	}
++
++	err = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
++			&priv->num_rx_slots);
++	if (err) {
++		dev_err(&pdev->dev, "unable to get rx-fifo-depth\n");
++		goto err;
++	}
++
++	err = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
++			&priv->num_tx_slots);
++	if (err) {
++		dev_err(&pdev->dev, "unable to get tx-fifo-depth\n");
++		goto err;
++	}
++
++	/* Rx slots */
++	priv->rx_base = buf_base;
++	priv->rx_slot = 0;
++
++	/* Tx slots come after Rx slots */
++	priv->tx_base = buf_base + priv->num_rx_slots * LITEETH_BUFFER_SIZE;
++	priv->tx_slot = 0;
++
++	mac_addr = of_get_mac_address(np);
++	if (mac_addr && is_valid_ether_addr(mac_addr))
++		memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
++	else
++		eth_hw_addr_random(netdev);
++
++	SET_NETDEV_DEV(netdev, &pdev->dev);
++	platform_set_drvdata(pdev, netdev);
++
++	netdev->netdev_ops = &liteeth_netdev_ops;
++	netdev->ethtool_ops = &liteeth_ethtool_ops;
++	netdev->irq = irq;
++
++	liteeth_reset_hw(priv);
++
++	err = register_netdev(netdev);
++	if (err) {
++		dev_err(&pdev->dev, "Failed to register netdev\n");
++		goto err;
++	}
++
++	netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
++
++	return 0;
++err:
++	free_netdev(netdev);
++	return err;
++}
++
++static int liteeth_remove(struct platform_device *pdev)
++{
++	struct net_device *netdev;
++	struct liteeth *priv;
++
++	netdev = platform_get_drvdata(pdev);
++	priv = netdev_priv(netdev);
++
++	unregister_netdev(netdev);
++
++	free_netdev(netdev);
++
++	return 0;
++}
++
++static const struct of_device_id liteeth_of_match[] = {
++	{ .compatible = "litex,liteeth" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, liteeth_of_match);
++
++static struct platform_driver liteeth_driver = {
++	.probe = liteeth_probe,
++	.remove = liteeth_remove,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = liteeth_of_match,
++	},
++};
++module_platform_driver(liteeth_driver);
++
++MODULE_AUTHOR("Joel Stanley <[email protected]>");
++MODULE_LICENSE("GPL");
+diff -uNr linux-5.0.11/drivers/net/ethernet/litex/Makefile linux-5.0.11-liteeth/drivers/net/ethernet/litex/Makefile
+--- linux-5.0.11/drivers/net/ethernet/litex/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ linux-5.0.11-liteeth/drivers/net/ethernet/litex/Makefile	2019-05-06 13:03:36.607478986 +0100
+@@ -0,0 +1,5 @@
++#
++# Makefile for the LiteX network device drivers.
++#
++
++obj-$(CONFIG_LITEX_LITEETH) += litex_liteeth.o
+diff -uNr linux-5.0.11/drivers/net/ethernet/Makefile linux-5.0.11-liteeth/drivers/net/ethernet/Makefile
+--- linux-5.0.11/drivers/net/ethernet/Makefile	2019-05-06 13:01:32.254348532 +0100
++++ linux-5.0.11-liteeth/drivers/net/ethernet/Makefile	2019-05-06 14:08:36.340330906 +0100
+@@ -50,6 +50,7 @@
+ obj-$(CONFIG_KORINA) += korina.o
+ obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
+ obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
++obj-$(CONFIG_NET_VENDOR_LITEX) += litex/
+ obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
+ obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
+ obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
diff --git a/board/litex_vexriscv/litex_vexriscv.dts b/board/litex_vexriscv/litex_vexriscv.dts
new file mode 100644
index 0000000..f89af76
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x02000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_arty.dts b/board/litex_vexriscv/litex_vexriscv_arty.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_arty.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_genesys2.dts b/board/litex_vexriscv/litex_vexriscv_genesys2.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_genesys2.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_kcu105.dts b/board/litex_vexriscv/litex_vexriscv_kcu105.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_kcu105.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_minispartan6.dts b/board/litex_vexriscv/litex_vexriscv_minispartan6.dts
new file mode 100644
index 0000000..f89af76
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_minispartan6.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x02000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_netv2.dts b/board/litex_vexriscv/litex_vexriscv_netv2.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_netv2.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_nexys4ddr.dts b/board/litex_vexriscv/litex_vexriscv_nexys4ddr.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_nexys4ddr.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_ulx3s.dts b/board/litex_vexriscv/litex_vexriscv_ulx3s.dts
new file mode 100644
index 0000000..f89af76
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_ulx3s.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x02000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/litex_vexriscv_versa_ecp5.dts b/board/litex_vexriscv/litex_vexriscv_versa_ecp5.dts
new file mode 100644
index 0000000..5de7ce5
--- /dev/null
+++ b/board/litex_vexriscv/litex_vexriscv_versa_ecp5.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	chosen {
+		bootargs = "mem=128M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32";
+		linux,initrd-start = <0xC0800000>;
+		linux,initrd-end   = <0xC1000000>; // max 8MB ramdisk image
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x47868C0>;
+
+		cpu@0 {
+			clock-frequency = <0x0>;
+			compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x1>;
+			d-tlb-size = <0x20>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x40>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x1>;
+			i-tlb-size = <0x20>;
+			mmu-type = "riscv,sv32";
+			reg = <0x0>;
+			riscv,isa = "rv32ima";
+			sifive,itim = <0x1>;
+			status = "okay";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x2>;
+			};
+		};
+
+		interrupt-controller {
+			#address-cells = <0x0>;
+			#interrupt-cells = <0x1>;
+			compatible = "riscv,vex";
+			interrupt-controller;
+			interrupts-extended = <0x2 0xb>;
+			reg = <0xe000000 0x4000000>;
+			riscv,ndev = <0xa>;
+			phandle = <0x3>;
+		};
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x1 0x08000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+
+		mac0: mac@f0009800 {
+			compatible = "litex,liteeth";
+			reg = <0x0 0xf0009800 0x0 0x7c
+				0x0 0xf0009000 0x0 0x0a
+				0x0 0xb0000000 0x0 0x2000>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x2>;
+			tx-fifo-depth = <2>;
+			rx-fifo-depth = <2>;
+		};
+
+	};
+
+};
diff --git a/board/litex_vexriscv/rootfs_overlay/etc/motd b/board/litex_vexriscv/rootfs_overlay/etc/motd
new file mode 100644
index 0000000..3d1abf8
--- /dev/null
+++ b/board/litex_vexriscv/rootfs_overlay/etc/motd
@@ -0,0 +1,9 @@
+
+   __   _                                  __   _ __      _  __   _   __         ___  _
+  / /  (_)__  __ ____ _________  ___  ____/ /  (_) /____ | |/_/__| | / /____ __ / _ \(_)__ _____  __
+ / /__/ / _ \/ // /\ \ /___/ _ \/ _ \/___/ /__/ / __/ -_)>  </___/ |/ / -_) \ // , _/ (_-</ __/ |/ /
+/____/_/_//_/\_,_//_\_\    \___/_//_/   /____/_/\__/\__/_/|_|    |___/\__/_\_\/_/|_/_/___/\__/|___/
+
+                    32-bits VexRiscv CPU with MMU integrated in a LiteX SoC
+
+
diff --git a/board/litex_vexriscv/rootfs_overlay/etc/profile b/board/litex_vexriscv/rootfs_overlay/etc/profile
new file mode 100644
index 0000000..d4f7585
--- /dev/null
+++ b/board/litex_vexriscv/rootfs_overlay/etc/profile
@@ -0,0 +1,20 @@
+export PATH="/bin:/sbin:/usr/bin:/usr/sbin"
+
+if [ "$PS1" ]; then
+	if [ "`id -u`" -eq 0 ]; then
+		export PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\# '
+	else
+		export PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\$ '
+	fi
+fi
+
+export PAGER='/bin/more'
+export EDITOR='/bin/vi'
+
+# Source configuration files from /etc/profile.d
+for i in /etc/profile.d/*.sh ; do
+	if [ -r "$i" ]; then
+		. $i
+	fi
+done
+unset i
diff --git a/configs/litex_vexriscv_defconfig b/configs/litex_vexriscv_defconfig
new file mode 100644
index 0000000..a19e6c3
--- /dev/null
+++ b/configs/litex_vexriscv_defconfig
@@ -0,0 +1,13 @@
+BR2_riscv=y
+BR2_riscv_custom=y
+BR2_RISCV_ISA_CUSTOM_RVM=y
+BR2_RISCV_32=y
+BR2_KERNEL_HEADERS_5_0=y
+BR2_GCC_VERSION_8_X=y
+BR2_TARGET_GENERIC_GETTY_PORT="hvc0"
+BR2_ROOTFS_OVERLAY="board/litex_vexriscv/rootfs_overlay"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_PATCH="board/litex_vexriscv/linux_add_liteeth_driver.patch"
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/litex_vexriscv/linux.config"
+BR2_TARGET_ROOTFS_CPIO=y
-- 
2.9.5