 any of a variety of known media for use in a data processing system, such as a diskette, hard drive, or CD-ROM. The code can be distributed on such media, or for use by users of such other systems from the memory or storage of one computer system to other computer systems over a network, Distribution to users 5050 and 5051 is possible.
Alternatively, programming code can be embodied in memory 5025 and accessed by processor 5026 using a processor bus. Such program code includes an operating system that controls the functions and interactions of various computer components and one or more application programs 5032. Program code is typically paged from storage media 5027 to high speed memory 5025 that can be used for processing by processor 5026. Techniques and methods for instantiating software program code in memory on physical media and / or distributing software code over a network are well known and described herein. The book does not consider any more. When program code is created and stored on tangible media (including but not limited to electronic memory modules (RAM), flash memory, compact disks (CD), DVDs, magnetic tapes, etc.), It is called “Computer Program Product”. The computer program product media is typically readable by processing circuitry in the computer system, preferably for execution by the processing circuitry.
The cache that is most easily used by the processor (usually faster and smaller than the processor's other caches) is the lowest (L1 or level 1) cache, and the main store (main memory) is the highest level cache (3 If there is a level, it is L3). The lowest level cache is often divided into an instruction cache that holds machine instructions to be executed (I cache) and a data cache that holds data operands (D cache).
With reference to FIG. 21, an exemplary processor embodiment is illustrated with respect to processor 5026. Typically, one or more levels of cache 5053 are employed to buffer memory blocks to improve processor performance. The cache 5053 is a high-speed buffer that holds a cache line of memory data that is likely to be used. A typical cache line is 64, 128, or 256 bytes of memory data. Separate caches are often employed for instruction caches rather than data caches. Cache coherence (synchronization of copies of lines in memory and cache) is often provided by various “snoop” algorithms well known in the art. The main memory storage 5025 of the processor system is often referred to as a cache. In a processor system with a four level cache 5053, the main storage 5025 is usually faster and holds only a portion of the non-volatile storage (DASD, tape, etc.) that the computer system can use, Sometimes called level 5 (L5). The main storage 5025 “caches” pages of data paged in and out of the main storage 5025 by the operating system.
A program counter (instruction counter) 5061 keeps track of the address of the current instruction to be executed. The program counter in the z / Architecture® processor is 64 bits and can be truncated to 31 or 24 bits to support previous addressing limits. The program counter is usually embodied in the computer's PSW (program status word) to persist at context switch. Thus, for example, an operating system can interrupt an ongoing program with a program counter value (context switch from program environment to operating system environment). The program's PSW maintains the program counter value while the program is not active, and the operating system's (PSW's) program counter is used while the operating system is running. Normally, the program counter is incremented by a number equal to the number of bytes in the current instruction. RISC (Reduced Instruction Set Computing) instructions are typically fixed length, and CISC (Multiple Instruction Set Computing) instructions are typically variable length. The IBM z / Architecture (R) instruction is a CISC instruction having 2, 4, or 6 bytes. The program counter 5061 is modified by either a context switching operation or a branch execution operation of a branch instruction, for example. In a context switch operation, the current program's counter value is stored in the program status word along with other state information (such as the condition code) about the program being executed and points to the instruction of the new program module that will be executed. The new program's counter value is loaded. A branch execution operation is performed to allow the program to make decisions or loop within the program by loading the result of the branch instruction into the program counter 5061.
Typically, instruction fetch unit 5055 is employed to fetch instructions on behalf of processor 5026. The fetch unit fetches either the “next sequential instruction”, the target instruction of the branch execution instruction, or the first instruction of the program following the context switch. Current instruction fetch units often employ prefetch techniques to speculatively prefetch instructions based on the likelihood that prefetched instructions will be used. For example, the fetch unit can fetch a 16-byte instruction, including the next sequential instruction and additional bytes of other sequential instructions.
The fetched instruction is then executed by the processor 5026. In one embodiment, fetched instructions are passed to the fetch unit dispatch unit 5056. The dispatch unit decodes the instructions and forwards information about the decoded instructions to the appropriate units 5057, 5058, 5060. Execution unit 5057 typically receives information about the decoded arithmetic instruction from instruction fetch unit 5055 and will perform arithmetic operations on the operands according to the instruction's operation code. Operands are provided to execution unit 5057, preferably from either memory 5025, architecture register 5029, or the immediate field of the instruction being executed. The results of execution, when stored, are stored either in memory 5025, register 5029, or other machine hardware (such as control registers, PSW registers).
The processor 5026 typically has one or more units 5057, 5058, 5060 for performing the functions of the instructions. Referring to FIG. 22, execution unit 5057 can communicate by interface logic 5071 with processor units of architecture general register 5059, decode / dispatch unit 5056, load / store unit 5060, and others 5065. Execution unit 5057 may employ several register circuits 5067, 5068, 5069 to hold information on which arithmetic logic unit (ALU) 5066 will operate. The ALU performs arithmetic operations such as addition, subtraction, multiplication, and division, and logical functions such as logical product, logical sum, and exclusive logical sum (XOR), rotation, and shift. Preferably, the ALU supports special operations depending on the design. Other circuitry may provide other architectural features 5072, including, for example, condition codes and recovery support logic. Typically, the result of the ALU operation is held in an output register circuit 5070 that can transfer the result to various other processing functions. Although there are many arrangements of processor units, this description is intended only to give a representative understanding of one embodiment.
For example, ADD instructions are executed in execution unit 5057 with arithmetic and logic functions, while floating point instructions, for example, are executed in floating point execution with special floating point functions. Preferably, the execution unit operates on the operand identified by the instruction by performing an operation code definition function on the operand. For example, an add instruction can be executed by execution unit 5057 on operands found in two registers 5059 identified by the register field of the instruction.
Execution unit 5057 performs the arithmetic addition on the two operands and stores the result in the third operand, which is the third register or one of the two source registers. It can be one. The execution unit preferably performs various logical functions, such as shift, rotation, logical product, logical sum, and exclusive logical sum, and various arithmetic functions including any of addition, subtraction, multiplication, and division. An arithmetic logic unit (ALU) 5066 that can be executed is used. Some of the ALU 5066 are designed for scalar operations and some for floating point. Depending on the architecture, the data can be Big Endian (with the least significant byte at the highest byte address) or Little Endian (with the least significant byte at the lowest byte address). IBM z / Architecture® is big endian. The signed field can be a signed absolute value, one's complement, or two's complement depending on the architecture. The two's complement is advantageous in that the ALU does not need to design a subtraction function because either a negative or positive value in the two's complement requires only addition within the ALU. Numbers are usually written in shorthand, for example, a 12-bit field defines the address of a 4096-byte block and is generally described as a 4 Kbyte (kilobyte) block.
Referring to FIG. 23, branch instruction information for executing a branch instruction is often used by a branch prediction algorithm such as the branch history table 5082 to predict the result of a branch before other conditional operations are completed. It is transmitted to the branch unit 5058 to be adopted. The target of the current branch instruction is fetched and speculatively executed before the conditional operation is completed. When the conditional operation is completed, the speculatively executed branch instruction is completed or discarded based on the condition of the conditional operation and the speculative result. A typical branch instruction can test a condition code and branch to a target address if the condition code meets the branch requirements of the branch instruction, which can be, for example, an instruction register field Or it can be calculated based on some number found in the immediate field. The branch unit 5058 may employ an ALU 5074 having a plurality of input register circuits 5075, 5076, 5077 and an output register circuit 5080. Branch unit 5058 can communicate with general purpose registers 5059, decode dispatch unit 5056, or other circuitry 5073, for example.
Instruction group execution may include, for example, a context switch initiated