x4048
#define AR_GPIO_OE_OUT			0x404c
#define AR_GPIO_INTR_POL		0x4050
#define AR_GPIO_INPUT_EN_VAL		0x4054
#define AR_GPIO_INPUT_MUX1		0x4058
#define AR_GPIO_INPUT_MUX2		0x405c
#define AR_GPIO_OUTPUT_MUX(i)		(0x4060 + (i) * 4)
#define AR_INPUT_STATE			0x406c
#define AR_EEPROM_STATUS_DATA		0x407c
#define AR_OBS				0x4080
#define AR_GPIO_PDPU			0x4088
#define AR_PCIE_MSI			0x4094

/*
 * Analog registers.
 */
#define AR_IS_ANALOG_REG(reg)		((reg) >= 0x7800 && (reg) <= 0x78b4)
#define AR_AN_RF2G1_CH0			0x7810
#define AR_AN_RF5G1_CH0			0x7818
#define AR_AN_RF2G1_CH1			0x7834
#define AR_AN_RF5G1_CH1			0x783c
#define AR_AN_SYNTH9			0x7868
#define AR_AN_TOP1			0x7890
#define AR_AN_TOP2			0x7894

/*
 * PHY registers.
 */
#define AR_PHY_BASE			0x9800
#define AR_PHY(i)			(AR_PHY_BASE + (i) * 4)
#define AR_PHY_TEST			0x9800
#define AR_PHY_TURBO			0x9804
#define AR_PHY_TEST2			0x9808
#define AR_PHY_TIMING2			0x9810
#define AR_PHY_TIMING3			0x9814
#define AR_PHY_CHIP_ID			0x9818
#define AR_PHY_ACTIVE			0x981c
#define AR_PHY_RF_CTL2			0x9824
#define AR_PHY_RF_CTL3			0x9828
#define AR_PHY_ADC_CTL			0x982c
#define AR_PHY_ADC_SERIAL_CTL		0x9830
#define AR_PHY_RF_CTL4			0x9834
#define AR_PHY_TSTDAC_CONST		0x983c
#define AR_PHY_SETTLING			0x9844
#define AR_PHY_RXGAIN			0x9848
#define AR_PHY_DESIRED_SZ		0x9850
#define AR_PHY_FIND_SIG			0x9858
#define AR_PHY_AGC_CTL1			0x985c
#define AR_PHY_AGC_CONTROL		0x9860
#define AR_PHY_CCA(i)			(0x9864 + (i) * 0x1000)
#define AR_PHY_SFCORR			0x9868
#define AR_PHY_SFCORR_LOW		0x986c
#define AR_PHY_SLEEP_CTR_CONTROL	0x9870
#define AR_PHY_SLEEP_CTR_LIMIT		0x9874
#define AR_PHY_SLEEP_SCAL		0x9878
#define AR_PHY_PLL_CTL			0x987c
#define AR_PHY_BIN_MASK_1		0x9900
#define AR_PHY_BIN_MASK_2		0x9904
#define AR_PHY_BIN_MASK_3		0x9908
#define AR_PHY_MASK_CTL			0x990c
#define AR_PHY_RX_DELAY			0x9914
#define AR_PHY_SEARCH_START_DELAY	0x9918
#define AR_PHY_TIMING_CTRL4_0		0x9920
#define AR_PHY_TIMING_CTRL4(i)		(0x9920 + (i) * 0x1000)
#define AR_PHY_TIMING5			0x9924
#define AR_PHY_POWER_TX_RATE1		0x9934
#define AR_PHY_POWER_TX_RATE2		0x9938
#define AR_PHY_POWER_TX_RATE_MAX	0x993c
#define AR_PHY_RADAR_EXT		0x9940
#define AR_PHY_FRAME_CTL		0x9944
#define AR_PHY_SPUR_REG			0x994c
#define AR_PHY_RADAR_0			0x9954
#define AR_PHY_RADAR_1			0x9958
#define AR_PHY_SWITCH_CHAIN_0		0x9960
#define AR_PHY_SWITCH_COM		0x9964
#define AR_PHY_SIGMA_DELTA		0x996c
#define AR_PHY_RESTART			0x9970
#define AR_PHY_RFBUS_REQ		0x997c
#define AR_PHY_TIMING7			0x9980
#define AR_PHY_TIMING8			0x9984
#define AR_PHY_BIN_MASK2_1		0x9988
#define AR_PHY_BIN_MASK2_2		0x998c
#define AR_PHY_BIN_MASK2_3		0x9990
#define AR_PHY_BIN_MASK2_4		0x9994
#define AR_PHY_TIMING9			0x9998
#define AR_PHY_TIMING10			0x999c
#define AR_PHY_TIMING11			0x99a0
#define AR_PHY_RX_CHAINMASK		0x99a4
#define AR_PHY_MULTICHAIN_GAIN_CTL	0x99ac
#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i)	(0x99b4 + (i) * 0x1000)
#define AR_PHY_EXT_CCA0			0x99b8
#define AR_PHY_EXT_CCA(i)		(0x99bc + (i) * 0x1000)
#define AR_PHY_SFCORR_EXT		0x99c0
#define AR_PHY_HALFGI			0x99d0
#define AR_PHY_CHANNEL_MASK_01_30	0x99d4
#define AR_PHY_CHANNEL_MASK_31_60	0x99d8
#define AR_PHY_CHAN_INFO_MEMORY		0x99dc
#define AR_PHY_HEAVY_CLIP_ENABLE	0x99e0
#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS	0x99ec
#define AR_PHY_CALMODE			0x99f0
#define AR_PHY_REFCLKDLY		0x99f4
#define AR_PHY_REFCLKPD			0x99f8
#define AR_PHY_BB_RFGAIN(i)		(0x9a00 + (i) * 4)
#define AR_PHY_CAL_MEAS_0(i)		(0x9c10 + (i) * 0x1000)
#define AR_PHY_CAL_MEAS_1(i)		(0x9c14 + (i) * 0x1000)
#define AR_PHY_CAL_MEAS_2(i)		(0x9c18 + (i) * 0x1000)
#define AR_PHY_CAL_MEAS_3(i)		(0x9c1c + (i) * 0x1000)
#define AR_PHY_CURRENT_RSSI		0x9c1c
#define AR_PHY_RFBUS_GRANT		0x9c20
#define AR9280_PHY_CURRENT_RSSI		0x9c3c
#define AR_PHY_CHAN_INFO_GAIN_DIFF	0x9cf4
#define AR_PHY_CHAN_INFO_GAIN		0x9cfc
#define AR_PHY_MODE			0xa200
#define AR_PHY_CCK_TX_CTRL		