, Kenya over the weekend.
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Merry Christmas to those who observe! This week we are joined by Madeline Knott! She and the vagibonds decided to find out who else wants to be like Mary and have a virgin birth. We also discuss whether religiousness effects your definitions of sex.
Twitter: @thevagibonds
Instagram: @thevagibondspod
Facebook: The Vagibonds Podcast
References:
Yahoo question 1, question 2, question 3
Herring Amy H, Attard Samantha M, Gordon-Larsen Penny, Joyner William H, Halpern Carolyn T. Like a virgin (mother): analysis of data from a longitudinal, US population representative sample survey BMJ 2013; 347 :f71024 ¥ 10 –4 to 4.5 ¥ 10 –4 gate/ l 2.
4840 to 11,900 mil 2.
TABLE 15.2 System partitioning for the Sun Microsystems SPARCstation 10.
We shall need to add (0.175/0.5) ¥ 2 ¥ (15 to 20) = 10.5 to 21 mil (per side) for the pad heights (we included the effects of scaling in this calculation). With a pad pitch of 5 mil and roughly 166/4 = 42 I/Os per side (not counting any power pads), we need a die at least 5 ¥ 42 = 210 mil on a side for the I/Os. Thus the die size must be at least 210 ¥ 210 = 4.4 ¥ 10 4 mil 2 to fit 166 I/Os. Of this die area only 1.19 ¥ 10 4 /(4.4 ¥ 10 4 ) = 27 % (at most) is used by the core logic. This is a severely pad-limited design and we need to rethink the partitioning of this system.
A leading-one detector with barrel shifter normalizes a mantissa.
A priority encoder corrects exponents due to mantissa normalization.
A denormalizing barrel shifter aligns mantissas.
A normalizing barrel shifter with a leading-one detector normalizes mantissa subtraction.
TABLE 15.3 Some useful numbers for ASIC estimates, normalized to a 1 m m technology unless noted.

Not to be confused with minimum CAD grid size (which is usually less than 0.01 m m).
Less than drawn gate length, usually by about 10 percent.
For a 1 m m technology, 2LM ( l = 0.5 m m). Scales less than linearly with l.
For a 1 m m technology, 2LM ( l = 0.5 m m). Scales approximately linearly with l.
= 4 ¥ 10 –4 gate /l 2 (independent of scaling).
= 5 ¥ 10 –4 gate/ l 2 (independent of scaling).
Most datapath elements have an area per bit that depends on the number of bits in the datapath (the datapath width). Sometimes this dependency is linear (for the multipliers and the barrel shifter, for example); in other elements it depends on the logarithm (to base 2) of the datapath width (the leading one, all ones, and zero detectors, for example). In some elements you might expect there to be a dependency on datapath width, but it is small (the comparators are an example).
The area estimates given in Table 15.4 can be misleading. The exact size of an adder, for example, depends on the architecture: carry-save, carry-select, carry-lookahead, or ripple-carry (which depends on the speed you require). These area figures also exclude the routing between datapath elements, which is difficult to predict—it will depend on the number and size of the datapath elements, their type, and how much logic is random and how much is datapath.
Figure 15.3 (a) shows the typical size of SRAM constructed on an ASIC. These figures are based on the use of a RAM compiler (as opposed to building memory from flip-flops or latches) using a standard CMOS ASIC process, typically using a six-transistor cell. The actual size of a memory will depend on (1) the required access time, (2) the use of synchronous or asynchronous read or write, (3) the number and type of ports (read–write), (4) the use of special design rules, (5) the number of interconnect layers available, (6) the RAM architecture (number of devices in RAM cell), and (7) the process technology (active pull-up devices or pull-up resistors).
FIGURE 15.3 (a) ASIC memory size. These figures are for static RAM constructed using compilers in a 2LM ASIC process, but with no special memory design rules. The actual area of a RAM will depend on the speed and number of read–write ports. (b) Multiplier size for a 2LM process. The actual area will depend on the multiplier architecture and speed.
The maximum size of SRAM in Figure 15.3 (a) is 32 k-bit, which occupies approximately 6.0 ¥ 10 7 l 2. In a 0.5 m m process (with l = 0.25 m m), the area of a 32 k-bit SRAM is 6.0 ¥ 10 7 ¥ 0.25 ¥ 0.25 = 3.75 ¥ 10 6 m m 2 (or about 2 mm on a side—a large piece of silicon). If you need an SRAM that is larger than this, you probably need to consult with your ASIC vendor to determine the best way to implement a large on-chip memory. Figure 15.3 (b) shows the typical sizes for multipliers. Again the actual multiplier size will depend on the architecture (Booth encoding, Wallace tree, and so on), the process technology, and design rules. Table 15.5 shows some estimated gate counts for medium-size functions corresponding to some popular ASSP devices.
TABLE 15.5 Gate size estimates for popular ASSP functions.
Source: Fujitsu channelless gate-array data book, AU and CG21 series.
1. 2LM = two-level metal; 3LM = three-level metal.
2. Area estimates are for a two-level metal (2 LM) process. Areas for a three-level metal (3LM) process are approximately 0.75 to 1.0 times these figures.THÉ VERT Eau Fraîche Parfumée. Fresh fragrant water for women scented with fresh water Thé Vert. The freshness, beauty and tranquility of Japanese gardens are moved into this refined fragrance that combines mandarin, bergamot, grapefruit, lemon and yuzu with green tea, freesia, jasmine, cyclamen and lily of the valley that rest on a wooden base of cedarwood, amberwood and guaiac. The cylindrical bottle reflects in green hues the peace and essence of this fragrance.
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