BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


zmtarzmFTAOElim() : MachineFunctionPass(ID) {

zmtarzmFTAOElim ( ) : MachineFunctionPass ( ID ) {


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm FRAME_TO_ARGS_OFFSET Elimination";


bool zmtarzmFTAOElim::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


bool zmtarzmInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {

bool zmtarzmInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const {


MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();

MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ;


if ( ! isUnpredicatedTerminator ( * I ) ) {


MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();

MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ;


for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); J++) {

for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) {


if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) {


FirstUncondOrIndirectBr = J . getReverse ( ) ;


if ( J -> getDesc ( ) . isIndirectBranch ( ) ) {


if (FirstUncondOrIndirectBr != MBB.end()) {

if ( FirstUncondOrIndirectBr != MBB . end ( ) ) {


for(; std::next(FirstUncondOrIndirectBr) != MBB.end();) {

for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) {


std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ;


if ( I -> getDesc ( ) . isIndirectBranch ( ) ) {


if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


if ( I -> getDesc ( ) . isConditionalBranch ( ) ) {


if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) {


parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ;


void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {

void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;


if ( # . contains ( DestReg , SrcReg ) ) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


if ( zmtarzm :: GR16RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR16RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOV16rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MOV16rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOV8rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MOV8rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


if ( zmtarzm :: GR64RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR64RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV64rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV64rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR32RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR32RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV32rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV32rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR64PRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR64PRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV64rrP ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV64rrP), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR128RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR128RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV128rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV128rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: FP32RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::FP32RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI ( MBB , I , DL , get ( zmtarzm :: FMOV32rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::FMOV32rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: FP64RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::FP64RegClass.contains(DestReg, SrcReg)) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: FMOV64rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::FMOV64rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


MachineInstr* zmtarzmInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const {

MachineInstr * zmtarzmInstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const {


MachineInstrBuilder MIB = BuildMI(MF, DL, get(zmtarzm::DBG_VALUE)).addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);

MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( zmtarzm :: DBG_VALUE ) ) . addFrameIndex ( FrameIx ) . addImm ( 0 ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


static inline unsigned GetCondBranchFromCond(zmtarzm::CondCode BrOpc) {

static inline unsigned GetCondBranchFromCond ( zmtarzm :: CondCode BrOpc ) {


llvm_unreachable
(
"Illegal condition code!"
)
;


static zmtarzm::CondCode GetCondFromBranchOpc(unsigned CC) {

static zmtarzm :: CondCode GetCondFromBranchOpc ( unsigned CC ) {


unsigned zmtarzmInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {

unsigned zmtarzmInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const {


const MachineBasicBlock &MBB = *MI->getParent();

const MachineBasicBlock & MBB = * MI -> getParent ( ) ;


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();

const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


if (MI->getOpcode() == zmtarzm::INLINEASM) {

if ( MI -> getOpcode ( ) == zmtarzm :: INLINEASM ) {


return getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Desc . getOpcode ( ) == TargetOpcode :: DBG_VALUE ) {

if (Desc.getOpcode() == TargetOpcode::DBG_VALUE) {


if ( Desc . getOpcode ( ) == TargetOpcode :: EH_LABEL ) {

if (Desc.getOpcode() == TargetOpcode::EH_LABEL) {


if ( Desc . getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) {

if (Desc.getOpcode() == TargetOpcode::IMPLICIT_DEF) {


if ( Desc . getOpcode ( ) == TargetOpcode :: KILL ) {

if (Desc.getOpcode() == TargetOpcode::KILL) {


const MachineFunction *MF = MI->getParent()->getParent();

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const zmtarzmTargetMachine &TM = static_cast<const zmtarzmTargetMachine&>(MF->getTarget());

const zmtarzmTargetMachine & TM = static_cast < const zmtarzmTargetMachine & > ( MF -> getTarget ( ) ) ;


const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();

const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;


return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


const char *AsmStr = MI->getOperand(0).getSymbolName();

const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");


static inline zmtarzm::CondCode GetOppositeBranchCondition(zmtarzm::CondCode CC) {

static inline zmtarzm :: CondCode GetOppositeBranchCondition ( zmtarzm :: CondCode CC ) {


llvm_unreachable
(
"Illegal condition code!"
)
;


virtual const TargetRegisterInfo &getRegisterInfo() const {

virtual const TargetRegisterInfo & getRegisterInfo ( ) const {


unsigned zmtarzmInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {

unsigned zmtarzmInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const {


assert(TBB && "insertBranch must not be told to insert a fallthrough");


assert((Cond.size() == 3 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(TBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( TBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(TBB);


*BytesAdded = *BytesAdded + getInstSizeInBytes(MI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ;


unsigned Opc = Cond [ 0 ] . getImm ( ) ;


MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);

MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ;


*BytesAdded = *BytesAdded + getInstSizeInBytes(CondMI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ;


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(FBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( FBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(FBB);


assert((Cond.size() == 2 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(TBB);


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(FBB);


zmtarzmInstrInfo::zmtarzmInstrInfo() : zmtarzmGenInstrInfo(zmtarzm::ADJCALLSTACKDOWN, zmtarzm::ADJCALLSTACKUP), RI(*this) {

zmtarzmInstrInfo :: zmtarzmInstrInfo ( ) : zmtarzmGenInstrInfo ( zmtarzm :: ADJCALLSTACKDOWN , zmtarzm :: ADJCALLSTACKUP ) , RI ( * this ) {


static inline bool IsBRF(unsigned BrOpc) {

static inline bool IsBRF ( unsigned BrOpc ) {


if ( BrOpc == zmtarzm :: V_READLANE_B32 ) {


if ( BrOpc == zmtarzm :: V_WRITELANE_B32 ) {

if (BrOpc == zmtarzm::V_WRITELANE_B32) {


static inline bool IsBRT(unsigned BrOpc) {

static inline bool IsBRT ( unsigned BrOpc ) {


static inline bool IsBRU(unsigned BrOpc) {

static inline bool IsBRU ( unsigned BrOpc ) {


static inline bool IsBR_JT(unsigned BrOpc) {

static inline bool IsBR_JT ( unsigned BrOpc ) {


static inline bool IsCondBranch(unsigned BrOpc) {

static inline bool IsCondBranch ( unsigned BrOpc ) {


unsigned zmtarzmInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) && (isZeroImm(MI->getOperand(2)))) {

if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) {


FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ;


return MI -> getOperand ( 0 ) . getReg ( ) ;


unsigned zmtarzmInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


static bool isZeroImm(const MachineOperand &Op) {

static bool isZeroImm ( const MachineOperand & Op ) {


void zmtarzmInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


BuildMI(MBB, MI, DL, get(#), DestReg).addFrameIndex(FrameIndex).addImm(0);

BuildMI ( MBB , MI , DL , get ( # ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI ( MBB , MI , DL , get ( zmtarzm :: POP ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI(MBB, MI, DL, get(zmtarzm::POP), DestReg).addFrameIndex(FrameIndex).addImm(0);


BuildMI ( MBB , MI , DL , get ( zmtarzm :: LW ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI(MBB, MI, DL, get(zmtarzm::LW), DestReg).addFrameIndex(FrameIndex).addImm(0);


unsigned zmtarzmInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {

unsigned zmtarzmInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const {


MachineBasicBlock::iterator I = MBB.end();

MachineBasicBlock :: iterator I = MBB . end ( ) ;


if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) {

if ( ! IsBRU ( I -> getOpcode ( ) ) && ! IsCondBranch ( I -> getOpcode ( ) ) ) {


if ( ! IsCondBranch ( I -> getOpcode ( ) ) ) {


bool zmtarzmInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {

bool zmtarzmInstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {


assert((Cond.size() == #) && "Invalid zmtarzm branch condition!");

assert
(
(
Cond
.
size
(
)
==
#
)
&&
"Invalid zmtarzm branch condition!"
)
;

assert
(
(
Cond
.
size
(
)
==
1
)
&&
"Invalid zmtarzm branch condition!"
)
;

assert((Cond.size() == 1) && "Invalid zmtarzm branch condition!");


Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( ( zmtarzm :: CondCode ) Cond [ 0 ] . getImm ( ) ) ) ;


assert
(
(
Cond
.
size
(
)
==
2
)
&&
"Invalid zmtarzm branch condition!"
)
;

assert((Cond.size() == 2) && "Invalid zmtarzm branch condition!");


void zmtarzmInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();

MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ;


MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex), MachineMemOperand::MOStore, MFI->getObjectSize(FrameIndex), MFI->getObjectAlignment(FrameIndex));

MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI -> getObjectSize ( FrameIndex ) , MFI -> getObjectAlignment ( FrameIndex ) ) ;


BuildMI(MBB, I, DL, get(#)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: STDPtrQRr ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(zmtarzm::STDPtrQRr)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0);


FunctionPass *llvm::createzmtarzmISelDag(zmtarzmTargetMachine &TM, CodeGenOpt::Level OptLevel) {

FunctionPass * llvm :: createzmtarzmISelDag ( zmtarzmTargetMachine & TM , CodeGenOpt :: Level OptLevel ) {


return new zmtarzmDAGToDAGISel(TM, OptLevel);

return new zmtarzmDAGToDAGISel ( TM , OptLevel ) ;


zmtarzmDAGToDAGISel(zmtarzmTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(TM, OptLevel), Lowering(*TM.getTargetLowering()), Subtarget(*TM.getSubtargetImpl()) {

zmtarzmDAGToDAGISel ( zmtarzmTargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


inline SDValue getI32Imm(unsigned Imm) {

inline SDValue getI32Imm ( unsigned Imm ) {


return CurDAG -> getTargetConstant ( Imm , MVT :: i32 ) ;


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm DAG->DAG Pattern Instruction Selection";


inline bool immBitp(SDNode *inN) const {

inline bool immBitp ( SDNode * inN ) const {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


inline bool immMskBitp(SDNode *inN) const {

inline bool immMskBitp ( SDNode * inN ) const {


bool zmtarzmDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRcpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if (Addr.getOpcode() == zmtarzmISD::CPRelativeWrapper) {

if ( Addr . getOpcode ( ) == zmtarzmISD :: CPRelativeWrapper ) {


Offset = CurDAG->getTargetConstant(0, MVT::i32);

Offset = CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ;


if ( Addr . getOpcode ( ) == ISD :: ADD ) {


if ((Addr.getOperand(0).getOpcode() == zmtarzmISD::CPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == zmtarzmISD :: CPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


Base = Addr . getOperand ( 0 ) . getOperand ( 0 ) ;


Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);

Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRdpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if (Addr.getOpcode() == zmtarzmISD::DPRelativeWrapper) {

if ( Addr . getOpcode ( ) == zmtarzmISD :: DPRelativeWrapper ) {


if ((Addr.getOperand(0).getOpcode() == zmtarzmISD::DPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == zmtarzmISD :: DPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


bool zmtarzmDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRspii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {

if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) {


Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( 0 ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


if ( ConstraintID == InlineAsm :: Constraint_m ) {

if (ConstraintID == InlineAsm::Constraint_m) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


bool zmtarzmTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {

bool zmtarzmTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const {


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);

CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ;


if (!CCInfo.CheckReturn(Outs, RetCC_zmtarzm)) {

if ( ! CCInfo . CheckReturn ( Outs , RetCC_zmtarzm ) ) {


if (CCInfo.getNextStackOffset() != 0 && isVarArg) {

if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) {


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CSEL ) {

if (Op.getOpcode() == zmtarzmISD::CSEL) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_ldaxr ) {

if (IntID == Intrinsic::zmtarzm_ldaxr) {


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


if ( IntID == Intrinsic :: zmtarzm_ldxr ) {


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_umaxv ) {

if (IntID == Intrinsic::zmtarzm_neon_umaxv) {


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;

assert(BitWidth >= 8 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;

assert(BitWidth >= 16 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_uminv ) {

if (IntID == Intrinsic::zmtarzm_neon_uminv) {


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


MachineBasicBlock* zmtarzmTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const {

MachineBasicBlock * zmtarzmTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const {


const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();

const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ;


assert((MI->getOpcode() == zmtarzm::SELECT_CC) && "Unexpected instr type to insert");

assert
(
(
MI
->
getOpcode
(
)
==
zmtarzm
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;


const BasicBlock *LLVM_BB = BB->getBasicBlock();

const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ;


MachineFunction * F = BB -> getParent ( ) ;


MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);

MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ;


MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);

MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ;


copy1MBB->splice(copy1MBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end());

copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ;


copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


BuildMI ( BB , dl , TII . get ( # ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ;

BuildMI ( BB , dl , TII . get ( zmtarzm :: BF ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ;


BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( zmtarzm :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( # ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( # ) . getReg ( ) ) . addMBB ( thisMBB ) ;

BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( zmtarzm :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ;


SDValue zmtarzmTargetLowering::ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: ExpandADDSUB ( SDNode * N , SelectionDAG & DAG ) const {


assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!");

assert
(
(
N
->
getOpcode
(
)
==
ISD
::
SRL
||
N
->
getOpcode
(
)
==
ISD
::
SRA
)
&&
"Unknown shift to lower!"
)
;


if (!isa<ConstantSDNode>(N->getOperand(1)) || cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) {

if ( ! isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) || cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) {


SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned Opc = N->getOpcode() == ISD::SRL ? zmtarzmISD::SRL_FLAG:zmtarzmISD::SRA_FLAG;

unsigned Opc = N -> getOpcode ( ) == ISD :: SRL ? zmtarzmISD :: SRL_FLAG : zmtarzmISD :: SRA_FLAG ;


Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);

Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( MVT :: i32 , MVT :: Glue ) , Hi ) ;


Lo = DAG.getNode(zmtarzmISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));

Lo = DAG . getNode ( zmtarzmISD :: RRX , dl , MVT :: i32 , Lo , Hi . getValue ( 1 ) ) ;


return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);

return DAG . getNode ( ISD :: BUILD_PAIR , dl , MVT :: i64 , Lo , Hi ) ;


assert(VT.is256BitVector() && VT == V1.getValueType() && "Invalid nodes in input!");

assert
(
VT
.
is256BitVector
(
)
&&
VT
==
V1
.
getValueType
(
)
&&
"Invalid nodes in input!"
)
;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);

SDValue V0_LO = Extract128BitVector ( V0 , 0 , DAG , DL ) ;


SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);

SDValue V0_HI = Extract128BitVector ( V0 , NumElts / 2 , DAG , DL ) ;


SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);

SDValue V1_LO = Extract128BitVector ( V1 , 0 , DAG , DL ) ;


SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);

SDValue V1_HI = Extract128BitVector ( V1 , NumElts / 2 , DAG , DL ) ;


if (!isUndefLO && V0->getOpcode() != ISD::UNDEF) {

if ( ! isUndefLO && V0 -> getOpcode ( ) != ISD :: UNDEF ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V0_HI);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V0_HI ) ;


if (!isUndefHI && V1->getOpcode() != ISD::UNDEF) {

if ( ! isUndefHI && V1 -> getOpcode ( ) != ISD :: UNDEF ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V1_LO, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V1_LO , V1_HI ) ;


if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF || V1_LO->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefLO && ( V0_LO -> getOpcode ( ) != ISD :: UNDEF || V1_LO -> getOpcode ( ) != ISD :: UNDEF ) ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V1_LO);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V1_LO ) ;


if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF || V1_HI->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefHI && ( V0_HI -> getOpcode ( ) != ISD :: UNDEF || V1_HI -> getOpcode ( ) != ISD :: UNDEF ) ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_HI, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_HI , V1_HI ) ;


return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);

return DAG . getNode ( ISD :: CONCAT_VECTORS , DL , VT , LO , HI ) ;


SDValue zmtarzmTargetLowering::ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: ExpandADDSUB ( SDNode * N , SelectionDAG & DAG ) const {


assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!");

assert
(
(
N
->
getOpcode
(
)
==
ISD
::
SRL
||
N
->
getOpcode
(
)
==
ISD
::
SRA
)
&&
"Unknown shift to lower!"
)
;


if (!isa<ConstantSDNode>(N->getOperand(1)) || cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) {

if ( ! isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) || cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) {


SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned Opc = N->getOpcode() == ISD::SRL ? zmtarzmISD::SRL_FLAG:zmtarzmISD::SRA_FLAG;

unsigned Opc = N -> getOpcode ( ) == ISD :: SRL ? zmtarzmISD :: SRL_FLAG : zmtarzmISD :: SRA_FLAG ;


Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);

Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( MVT :: i32 , MVT :: Glue ) , Hi ) ;


Lo = DAG.getNode(zmtarzmISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));

Lo = DAG . getNode ( zmtarzmISD :: RRX , dl , MVT :: i32 , Lo , Hi . getValue ( 1 ) ) ;


return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);

return DAG . getNode ( ISD :: BUILD_PAIR , dl , MVT :: i64 , Lo , Hi ) ;


assert(VT.is256BitVector() && VT == V1.getValueType() && "Invalid nodes in input!");

assert
(
VT
.
is256BitVector
(
)
&&
VT
==
V1
.
getValueType
(
)
&&
"Invalid nodes in input!"
)
;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);

SDValue V0_LO = Extract128BitVector ( V0 , 0 , DAG , DL ) ;


SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);

SDValue V0_HI = Extract128BitVector ( V0 , NumElts / 2 , DAG , DL ) ;


SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);

SDValue V1_LO = Extract128BitVector ( V1 , 0 , DAG , DL ) ;


SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);

SDValue V1_HI = Extract128BitVector ( V1 , NumElts / 2 , DAG , DL ) ;


if (!isUndefLO && V0->getOpcode() != ISD::UNDEF) {

if ( ! isUndefLO && V0 -> getOpcode ( ) != ISD :: UNDEF ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V0_HI);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V0_HI ) ;


if (!isUndefHI && V1->getOpcode() != ISD::UNDEF) {

if ( ! isUndefHI && V1 -> getOpcode ( ) != ISD :: UNDEF ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V1_LO, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V1_LO , V1_HI ) ;


if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF || V1_LO->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefLO && ( V0_LO -> getOpcode ( ) != ISD :: UNDEF || V1_LO -> getOpcode ( ) != ISD :: UNDEF ) ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V1_LO);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V1_LO ) ;


if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF || V1_HI->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefHI && ( V0_HI -> getOpcode ( ) != ISD :: UNDEF || V1_HI -> getOpcode ( ) != ISD :: UNDEF ) ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_HI, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_HI , V1_HI ) ;


return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);

return DAG . getNode ( ISD :: CONCAT_VECTORS , DL , VT , LO , HI ) ;


unsigned zmtarzmTargetLowering::getJumpTableEncoding() const {

unsigned zmtarzmTargetLowering :: getJumpTableEncoding ( ) const {


return MachineJumpTableInfo :: EK_Inline ;


std::pair<unsigned, const TargetRegisterClass *> zmtarzmTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {

std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const {


return std :: make_pair ( 0U , zmtarzm :: GR64RegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


return std :: make_pair ( 0U , zmtarzm :: GenericRegsRegClass ) ;


virtual MVT getShiftAmountTy(EVT LHSTy) const {

virtual MVT getShiftAmountTy ( EVT LHSTy ) const {


const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {

const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


if ((zmtarzmISD::NodeType)Opcode == #) {

if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMUL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMUL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TBUFFER_STORE_FORMAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TBUFFER_STORE_FORMAT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: STORE_MSKOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::STORE_MSKOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_P2 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_P2) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_P1 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_P1) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_MOV ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_MOV) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SENDMSG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SENDMSG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST_DATA_PTR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST_DATA_PTR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BUILD_VERTICAL_VECTOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BUILD_VERTICAL_VECTOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE2 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE2) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE1 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE1) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE0 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE0) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLEL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLEL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLED ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLED) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLEB ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLEB) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LOAD_INPUT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LOAD_INPUT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LOAD_CONSTANT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LOAD_CONSTANT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: REGISTER_STORE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::REGISTER_STORE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: REGISTER_LOAD ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::REGISTER_LOAD) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RCP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RCP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ_CLAMPED ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ_CLAMPED) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LDEXP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LDEXP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FP_CLASS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FP_CLASS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DOT4 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DOT4) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CARRY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CARRY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BORROW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BORROW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST_ADDRESS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST_ADDRESS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXPORT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXPORT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TEXTURE_FETCH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TEXTURE_FETCH) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAD_I24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAD_I24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAD_U24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAD_U24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MUL_I24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MUL_I24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MUL_U24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MUL_U24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FFBH_U32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FFBH_U32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFI ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFI) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFE_I32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFE_I32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFE_U32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFE_U32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BRANCH_COND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BRANCH_COND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DWORDADDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DWORDADDR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FRACT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FRACT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CLAMP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CLAMP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: COS_HW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::COS_HW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SIN_HW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SIN_HW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMAX_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMAX_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMIN_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMIN_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: URECIP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::URECIP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_SCALE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_SCALE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_FMAS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_FMAS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_FIXUP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_FIXUP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TRIG_PREOP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TRIG_PREOP) {


const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {

const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {


if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ((zmtarzmISD::NodeType)Opcode == #) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Wrapper ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Wrapper) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RLC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RLC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RRC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RRC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SLA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SLA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SRA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SRA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SRL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SRL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DEC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DEC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ADD ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ADD) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ADC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ADC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SUB ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SUB) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SBC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SBC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: XOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::XOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: OR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::OR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TST) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MLT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MLT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SEXT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SEXT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RETN_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RETN_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RETI_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RETI_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BRCOND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BRCOND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SELECT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SELECT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: POP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::POP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: PUSH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::PUSH) {


bool zmtarzmTargetLowering::isLegalAddImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


return isUInt<32>(Imm) || isUInt<32>(-Imm);

return isUInt < 32 > ( Imm ) || isUInt < 32 > ( - Imm ) ;


bool zmtarzmTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {

bool zmtarzmTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const {


if ( ! isInt < # > ( AM . BaseOffs ) ) {


bool zmtarzmTargetLowering::isLegalICmpImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const {


SDValue zmtarzmTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerADJUST_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG ) const {


SDValue zmtarzmTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const {


return DAG.getNode(#, dl, MVT::Other, Op.getOperand(0));

return DAG . getNode ( # , dl , MVT :: Other , Op . getOperand ( 0 ) ) ;

return DAG . getNode ( zmtarzmISD :: Sync , dl , MVT :: Other , Op . getOperand ( 0 ) ) ;

return DAG.getNode(zmtarzmISD::Sync, dl, MVT::Other, Op.getOperand(0));


SDValue zmtarzmTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const {


const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), true);

SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true ) ;


return DAG.getNode(#, DL, getPointerTy(), Result);

return DAG . getNode ( # , DL , getPointerTy ( ) , Result ) ;

return DAG . getNode ( zmtarzmISD :: Wrapper , DL , getPointerTy ( ) , Result ) ;

return DAG.getNode(zmtarzmISD::Wrapper, DL, getPointerTy(), Result);


return DAG . getNode ( zmtarzmISD :: PCREL_WRAPPER , DL , getPointerTy ( ) , Result ) ;

return DAG.getNode(zmtarzmISD::PCREL_WRAPPER, DL, getPointerTy(), Result);


SDValue zmtarzmTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const {


const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));

const auto * JT = cast < JumpTableSDNode > ( Op . getOperand ( 1 ) ) ;


assert(JT->getTargetFlags() == 0 && "zmtarzm doesn't set target flags");

assert
(
JT
->
getTargetFlags
(
)
==
0
&&
"zmtarzm doesn't set target flags"
)
;


MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();

MachineJumpTableInfo * MJTI = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) ;


const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;

const auto & MBBs = MJTI -> getJumpTables ( ) [ JT -> getIndex ( ) ] . MBBs ;


Ops . push_back ( DAG . getBasicBlock ( MBB ) ) ;


Ops . push_back ( DAG . getBasicBlock ( MBBs [ 0 ] ) ) ;


return DAG.getNode(zmtarzmISD::BR_TABLE, DL, MVT::Other, Ops);

return DAG . getNode ( zmtarzmISD :: BR_TABLE , DL , MVT :: Other , Ops ) ;


JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);

JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();

const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ;


SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);

SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , MVT :: i32 ) ;


const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();

const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ;


const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;

const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ;


for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = JTBBs . size ( ) ; i != e ; ++ i ) {


BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ;


SDValue JumpTableBase = DAG.getNode(zmtarzmISD::WrapperJT, dl, getPointerTy(), TargetJT);

SDValue JumpTableBase = DAG . getNode ( zmtarzmISD :: WrapperJT , dl , getPointerTy ( ) , TargetJT ) ;


SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, DAG.getConstant(2, MVT::i32));

SDValue ShiftIndex = DAG . getNode ( ISD :: SHL , dl , MVT :: i32 , Index , DAG . getConstant ( 2 , MVT :: i32 ) ) ;


SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,ShiftIndex);

SDValue JTAddress = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , JumpTableBase , ShiftIndex ) ;


SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, MachinePointerInfo(), false, false, false, 0);

SDValue LoadTarget = DAG . getLoad ( MVT :: i32 , dl , Chain , JTAddress , MachinePointerInfo ( ) , false , false , false , 0 ) ;


return DAG.getNode(zmtarzmISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);

return DAG . getNode ( zmtarzmISD :: BR_JT , dl , MVT :: Other , Chain , LoadTarget ) ;


SDValue zmtarzmTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const {


const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));

const auto * JT = cast < JumpTableSDNode > ( Op . getOperand ( 1 ) ) ;


assert(JT->getTargetFlags() == 0 && "zmtarzm doesn't set target flags");

assert
(
JT
->
getTargetFlags
(
)
==
0
&&
"zmtarzm doesn't set target flags"
)
;


MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();

MachineJumpTableInfo * MJTI = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) ;


const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;

const auto & MBBs = MJTI -> getJumpTables ( ) [ JT -> getIndex ( ) ] . MBBs ;


Ops . push_back ( DAG . getBasicBlock ( MBB ) ) ;


Ops . push_back ( DAG . getBasicBlock ( MBBs [ 0 ] ) ) ;


return DAG.getNode(zmtarzmISD::BR_TABLE, DL, MVT::Other, Ops);

return DAG . getNode ( zmtarzmISD :: BR_TABLE , DL , MVT :: Other , Ops ) ;


JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);

JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();

const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ;


SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);

SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , MVT :: i32 ) ;


const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();

const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ;


const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;

const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ;


for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = JTBBs . size ( ) ; i != e ; ++ i ) {


BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ;


SDValue JumpTableBase = DAG.getNode(zmtarzmISD::WrapperJT, dl, getPointerTy(), TargetJT);

SDValue JumpTableBase = DAG . getNode ( zmtarzmISD :: WrapperJT , dl , getPointerTy ( ) , TargetJT ) ;


SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, DAG.getConstant(2, MVT::i32));

SDValue ShiftIndex = DAG . getNode ( ISD :: SHL , dl , MVT :: i32 , Index , DAG . getConstant ( 2 , MVT :: i32 ) ) ;


SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,ShiftIndex);

SDValue JTAddress = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , JumpTableBase , ShiftIndex ) ;


SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, MachinePointerInfo(), false, false, false, 0);

SDValue LoadTarget = DAG . getLoad ( MVT :: i32 , dl , Chain , JTAddress , MachinePointerInfo ( ) , false , false , false , 0 ) ;


return DAG.getNode(zmtarzmISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);

return DAG . getNode ( zmtarzmISD :: BR_JT , dl , MVT :: Other , Chain , LoadTarget ) ;


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {

if (VA.getLocInfo() == CCValAssign::BCvt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


unsigned Reg = RVLocs [ i ] . getLocReg ( ) ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1);

Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ;


InVals . push_back ( Chain . getValue ( 0 ) ) ;


return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , DL , DAG , InVals ) ;

return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, InVals);


SDValue zmtarzmTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const {


ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);

ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ;


if ( CP -> isMachineConstantPoolEntry ( ) ) {


Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlignment());

Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;


Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment());

Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;


return DAG.getNode(#, dl, MVT::i32, Res);

return DAG . getNode ( # , dl , MVT :: i32 , Res ) ;

return DAG . getNode ( zmtarzmISD :: Wrapper , dl , MVT :: i32 , Res ) ;

return DAG.getNode(zmtarzmISD::Wrapper, dl, MVT::i32, Res);


return DAG . getNode ( zmtarzmISD :: PCREL_WRAPPER , dl , MVT :: i32 , Res ) ;

return DAG.getNode(zmtarzmISD::PCREL_WRAPPER, dl, MVT::i32, Res);


SDValue zmtarzmTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const {


assert(Subtarget->isTargetWindows() && "unsupported target platform");

assert
(
Subtarget
->
isTargetWindows
(
)
&&
"unsupported target platform"
)
;


if ( isa < ConstantSDNode > ( Size ) ) {


return lowerDYNAMIC_STACKALLOCImpl ( Op , DAG ) ;


return zmtarzmTargetLowering :: LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) {


MaybeAlign Align = cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();

MaybeAlign Align = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) -> getMaybeAlignValue ( ) ;


SDValue SP = DAG.getCopyFromReg(Chain, DL, zmtarzm::SP, MVT::i32);

SDValue SP = DAG . getCopyFromReg ( Chain , DL , zmtarzm :: SP , MVT :: i32 ) ;


SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);

SP = DAG . getNode ( ISD :: SUB , DL , MVT :: i32 , SP , Size ) ;


SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0), DAG.getConstant(-(uint64_t)Align->value(), DL, MVT::i32));

SP = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , SP . getValue ( 0 ) , DAG . getConstant ( - ( uint64_t ) Align -> value ( ) , DL , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::SP, SP);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: SP , SP ) ;


SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size, DAG.getConstant(2, DL, MVT::i32));

SDValue Words = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , Size , DAG . getConstant ( 2 , DL , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R4, Words, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R4 , Words , Flag ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;