return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);

return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder ) ;


static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {

static DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {


MCRegister Register = zmtarzm :: R0 + RegNo ;

MCRegister Register = zmtarzm::R0 + RegNo;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


static DecodeStatus DecodePulpV2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {

static DecodeStatus DecodePulpV2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {


return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);

return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


static DecodeStatus DecodePulpV4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {

static DecodeStatus DecodePulpV4RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {


static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned d = fieldFromInstruction(Insn, #, #);

unsigned d = fieldFromInstruction ( Insn , # , # ) ;

unsigned d = fieldFromInstruction ( Insn , 28 , 4 ) ;

unsigned d = fieldFromInstruction(Insn, 28, 4);


unsigned s1 = fieldFromInstruction(Insn, #, #);

unsigned s1 = fieldFromInstruction ( Insn , # , # ) ;

unsigned s1 = fieldFromInstruction ( Insn , 8 , 4 ) ;

unsigned s1 = fieldFromInstruction(Insn, 8, 4);


DecodeStatus status = DecodeGPRRegisterClass(Inst, d, Address, Decoder);

DecodeStatus status = DecodeGPRRegisterClass ( Inst , d , Address , Decoder ) ;


if (status != MCDisassembler::Success) {

if ( status != MCDisassembler :: Success ) {


Inst . addOperand ( MCOperand :: createImm ( const9 ) ) ;


status = DecodeGPRRegisterClass(Inst, s1, Address, Decoder);

status = DecodeGPRRegisterClass ( Inst , s1 , Address , Decoder ) ;


static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned char cmode = (insn >> 8) & 0xF;

unsigned char cmode = ( insn >> 8 ) & 0xF ;


const JmpExtraValues *extra = (reinterpret_cast<const JmpExtraValues*>(Addr));

const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ;


uint64_t address = extra->Address + extra->Imm;

uint64_t address = extra -> Address + extra -> Imm ;


if (!tryAddingSymbolicOperand(address, 0, true, 0, Inst, Decoder)) {

if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) {


Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ;


unsigned Register = PredicateTable[extra->Predicate];

unsigned Register = PredicateTable [ extra -> Predicate ] ;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


Inst . addOperand ( MCOperand :: createImm ( # ) ) ;

Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < 16 > ( Offset ) ) ) ;


Inst . addOperand ( MCOperand :: createImm ( extra -> Polarity ) ) ;


static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned Rd = fieldFromInstruction(Insn, #, #);

unsigned Rd = fieldFromInstruction ( Insn , # , # ) ;

unsigned Rd = fieldFromInstruction ( Insn , 12 , 4 ) ;

unsigned Rd = fieldFromInstruction(Insn, 12, 4);


unsigned Rs2 = fieldFromInstruction(Insn, #, #);

unsigned Rs2 = fieldFromInstruction ( Insn , # , # ) ;

unsigned Rs2 = fieldFromInstruction ( Insn , 8 , 4 ) ;

unsigned Rs2 = fieldFromInstruction(Insn, 8, 4);


DecodeStatus status = DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);

DecodeStatus status = DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;


if ( status != MCDisassembler :: Success ) {


status = DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);

status = DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;


static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


Inst . addOperand ( MCOperand :: createImm ( # ) ) ;


static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned char cmode = ( insn >> 8 ) & 0xF ;


const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ;


uint64_t address = extra -> Address + extra -> Imm ;


if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) {


Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ;


unsigned Register = PredicateTable [ extra -> Predicate ] ;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < 16 > ( Offset ) ) ) ;


Inst . addOperand ( MCOperand :: createImm ( extra -> Polarity ) ) ;


template <unsigned N> static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


assert(isUInt<N>(Imm) && "Invalid immediate");

assert
(
isUInt
<
N
>
(
Imm
)
&&
"Invalid immediate"
)
;


addImplySP ( Inst , Address , Decoder ) ;


Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;


template <unsigned N> static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeSImmOperandAndLsl1 ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << 1 ) ) ) ;


template <unsigned N> static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


template <unsigned N> static DecodeStatus decodeUImmMinus1Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeUImmMinus1Operand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


assert(isUInt<N>(Imm+1) && "Invalid immediate");

assert
(
isUInt
<
N
>
(
Imm
+
1
)
&&
"Invalid immediate"
)
;


Inst . addOperand ( MCOperand :: createImm ( Imm + 1 ) ) ;


template <unsigned N> static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


template <unsigned N> static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeVMaskReg ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {


MCRegister Reg = zmtarzm :: NoRegister ;


Inst . addOperand ( MCOperand :: createReg ( # ) ) ;


Inst . addOperand ( MCOperand :: createReg ( zmtarzm :: FCC0 ) ) ;


Inst . addOperand ( MCOperand :: createReg ( zmtarzm :: FCC1 ) ) ;


Inst . addOperand ( MCOperand :: createReg ( zmtarzm :: FCC2 ) ) ;


Inst . addOperand ( MCOperand :: createReg ( zmtarzm :: FCC3 ) ) ;


static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {

static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {


MCRegister Register = zmtarzm :: R0 + RegNo ;

MCRegister Register = zmtarzm::R0 + RegNo;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


zmtarzmDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,  MCInstrInfo const *MCII): MCDisassembler(STI, Ctx), MCII(MCII) {

zmtarzmDisassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {


DecodeStatus zmtarzmDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &CS) const {

DecodeStatus zmtarzmDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const {


if (!readInstruction64(Bytes, Address, Size, Insn64)) {

if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) {


Result = decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);

Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");


LLVM_DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");


if (!readInstruction32(Bytes, Address, Size, Insn32)) {

if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) {


return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);

return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ;


if (!readInstruction48(Bytes, Address, Size, Insn48)) {

if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) {


Result = decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);

Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Successfully decoded 16-bit instruction with limm.");


LLVM_DEBUG(dbgs() << "Not a 16-bit instruction with limm, try without it.");


if (!readInstruction16(Bytes, Address, Size, Insn16)) {

if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) {


return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);

return decodeInstruction ( DecoderTable16 , Instr , Insn16 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Trying zmtarzm 24bit table :\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"Trying zmtarzm 24bit table :\n"
)
;


Result = decodeInstruction(DecoderTable24, MI, Inst, Address, this, STI);

Result = decodeInstruction ( DecoderTable24 , MI , Inst , Address , this , STI ) ;


Inst = support :: endian :: read16le ( Bytes . data ( ) ) ;


LLVM_DEBUG(dbgs() << "Trying zmtarzm 16bit table :\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"Trying zmtarzm 16bit table :\n"
)
;


Result = decodeInstruction(DecoderTable16, MI, Inst, Address, this, STI);

Result = decodeInstruction ( DecoderTable16 , MI , Inst , Address , this , STI ) ;


DecodeStatus zmtarzmDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &CS) const {

DecodeStatus zmtarzmDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const {


if (!readInstruction64(Bytes, Address, Size, Insn64)) {

if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) {


Result = decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);

Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");


LLVM_DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");


if (!readInstruction32(Bytes, Address, Size, Insn32)) {

if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) {


return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);

return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ;


if (!readInstruction48(Bytes, Address, Size, Insn48)) {

if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) {


Result = decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);

Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Successfully decoded 16-bit instruction with limm.");


LLVM_DEBUG(dbgs() << "Not a 16-bit instruction with limm, try without it.");


if (!readInstruction16(Bytes, Address, Size, Insn16)) {

if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) {


return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);

return decodeInstruction ( DecoderTable16 , Instr , Insn16 , Address , this , STI ) ;


LLVM_DEBUG(dbgs() << "Trying zmtarzm 24bit table :\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"Trying zmtarzm 24bit table :\n"
)
;


Result = decodeInstruction(DecoderTable24, MI, Inst, Address, this, STI);

Result = decodeInstruction ( DecoderTable24 , MI , Inst , Address , this , STI ) ;


Inst = support :: endian :: read16le ( Bytes . data ( ) ) ;


LLVM_DEBUG(dbgs() << "Trying zmtarzm 16bit table :\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"Trying zmtarzm 16bit table :\n"
)
;


Result = decodeInstruction(DecoderTable16, MI, Inst, Address, this, STI);

Result = decodeInstruction ( DecoderTable16 , MI , Inst , Address , this , STI ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmDisassembler() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmDisassembler ( ) {


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzmTarget ( ) , createzmtarzmDisassembler ) ;


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzm32Target ( ) , createzmtarzmDisassembler ) ;


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzm64Target ( ) , createzmtarzmDisassembler ) ;


std::unique_ptr<MCObjectTargetWriter> llvm::createzmtarzmELFObjectWriter(uint8_t OSABI, bool Is64Bit) {

std :: unique_ptr < MCObjectTargetWriter > llvm :: createzmtarzmELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) {


return std :: make_unique < zmtarzmELFObjectWriter > ( OSABI , Is64Bit ) ;


zmtarzmELFObjectWriter::zmtarzmELFObjectWriter(uint8_t OSABI, bool Is64Bit) : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_zmtarzm, #) {

zmtarzmELFObjectWriter :: zmtarzmELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_zmtarzm , # ) {

zmtarzmELFObjectWriter :: zmtarzmELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , EM_zmtarzm , true ) {

zmtarzmELFObjectWriter::zmtarzmELFObjectWriter(uint8_t OSABI, bool Is64Bit) : MCELFObjectTargetWriter(Is64Bit, OSABI, EM_zmtarzm, true) {


zmtarzmELFObjectWriter :: zmtarzmELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , EM_zmtarzm , false ) {

zmtarzmELFObjectWriter::zmtarzmELFObjectWriter(uint8_t OSABI, bool Is64Bit) : MCELFObjectTargetWriter(Is64Bit, OSABI, EM_zmtarzm, false) {


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_R_DISP32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_R_DISP32) {


if (Kind >= FirstLiteralRelocationKind){

if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind;

return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


if ( Kind == zmtarzm :: fixup_zmtarzm_call30 ) {

if(Kind == zmtarzm::fixup_zmtarzm_call30) {


if ( Kind == zmtarzm :: fixup_zmtarzm_br22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_br22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_br19 ) {

if(Kind == zmtarzm::fixup_zmtarzm_br19) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc10) {


if ( Kind == zmtarzm :: fixup_zmtarzm_wplt30 ) {

if(Kind == zmtarzm::fixup_zmtarzm_wplt30) {


Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");

Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;


if ( Kind == zmtarzm :: fixup_zmtarzm_hi22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_hi22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_lo10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_lo10) {


if ( Kind == zmtarzm :: fixup_zmtarzm_h44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_h44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_m44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_m44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_l44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_l44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_hh ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_hm ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_got22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_got10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got10) {


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {

unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {


if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {

if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PC_LO32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_PC_LO32) {


if ( Kind >= FirstLiteralRelocationKind ) {

if (Kind >= FirstLiteralRelocationKind){


return Kind - FirstLiteralRelocationKind ;

return Kind - FirstLiteralRelocationKind;


Ctx.reportError(Fixup.getLoc(), "1-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "8-byte pc-relative data relocation is not supported");


if ( Kind == zmtarzm :: fixup_zmtarzm_reflong ) {

if(Kind == zmtarzm::fixup_zmtarzm_reflong) {


if ( Kind == zmtarzm :: fixup_zmtarzm_srel32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_srel32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc_lo32) {


Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;

Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");


Ctx.reportError(Fixup.getLoc(), "1-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative srel32 relocation is not supported");


if ( Kind == zmtarzm :: fixup_zmtarzm_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_lo32) {


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_hi32 relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_lo32 relocation is not supported");


if ( Kind == zmtarzm :: fixup_zmtarzm_got_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_got_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got_lo32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_gotoff_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_gotoff_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_gotoff_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_gotoff_lo32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_plt_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_plt_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_plt_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_plt_lo32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_tls_gd_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_tls_gd_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_tls_gd_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_tls_gd_lo32) {


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


if ( Kind == zmtarzm :: fixup_zmtarzm_tpoff_hi32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_tpoff_hi32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_tpoff_lo32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_tpoff_lo32) {


Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;

Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");


unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {

unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {


if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {

if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {


if ( Kind >= FirstLiteralRelocationKind ) {

if (Kind >= FirstLiteralRelocationKind){


return Kind - FirstLiteralRelocationKind ;

return Kind - FirstLiteralRelocationKind;


if ( Kind == zmtarzm :: fixup_zmtarzm__BO_7 ) {

if(Kind == zmtarzm::fixup_zmtarzm__BO_7) {


if ( Kind == zmtarzm :: fixup_zmtarzm__HO_7 ) {

if(Kind == zmtarzm::fixup_zmtarzm__HO_7) {


if ( Kind == zmtarzm :: fixup_zmtarzm__WO_7 ) {

if(Kind == zmtarzm::fixup_zmtarzm__WO_7) {


if ( Kind == zmtarzm :: fixup_zmtarzm__abs_ALUi ) {

if(Kind == zmtarzm::fixup_zmtarzm__abs_ALUi) {


if ( Kind == zmtarzm :: fixup_zmtarzm__abs_CFLi ) {

if(Kind == zmtarzm::fixup_zmtarzm__abs_CFLi) {


if ( Kind == zmtarzm :: fixup_zmtarzm__abs_ALUl ) {

if(Kind == zmtarzm::fixup_zmtarzm__abs_ALUl) {


if ( Kind == zmtarzm :: fixup_zmtarzm__stc ) {

if(Kind == zmtarzm::fixup_zmtarzm__stc) {


if ( Kind == zmtarzm :: fixup_zmtarzm__PCrel ) {

if(Kind == zmtarzm::fixup_zmtarzm__PCrel) {


if ( Kind == zmtarzm :: fixup_zmtarzm_jump_target ) {

if(Kind == zmtarzm::fixup_zmtarzm_jump_target) {


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


if ( Kind == zmtarzm :: fixup_zmtarzm_cond_branch12_target ) {

if(Kind == zmtarzm::fixup_zmtarzm_cond_branch12_target) {


bool needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const override {

bool needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned Type ) const override {


zmtarzmELFObjectWriter :: ~ zmtarzmELFObjectWriter ( ) {


size_t zmtarzmTargetELFStreamer::calculateContentSize() const {

size_t zmtarzmTargetELFStreamer :: calculateContentSize ( ) const {


for ( i = 0 ; i < Contents . size ( ) ; ++ i ) {


if (item.Type == AttributeType::Hidden) {

if ( item . Type == AttributeType :: Hidden ) {


if (item.Type == AttributeType::Numeric) {

if ( item . Type == AttributeType :: Numeric ) {


Result = Result + getULEB128Size(item.Tag);

Result = Result + getULEB128Size ( item . Tag ) ;


Result = Result + getULEB128Size(item.IntValue);

Result = Result + getULEB128Size ( item . IntValue ) ;


if ( item . Type == AttributeType :: Text ) {


Result = Result + item.StringValue.size() + 1;

Result = Result + item . StringValue . size ( ) + 1 ;


if (item.Type == AttributeType::NumericAndText) {

if ( item . Type == AttributeType :: NumericAndText ) {


void zmtarzmTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {

void zmtarzmTargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) {


setAttributeItem ( Attribute , Value , true ) ;


void zmtarzmTargetELFStreamer :: emitDirectiveOptionNoPIC ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionNoRelax ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionNoRVC ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionPIC ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionPop ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionPush ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionRelax ( ) {


void zmtarzmTargetELFStreamer :: emitDirectiveOptionRVC ( ) {


void zmtarzmTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {

void zmtarzmTargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


setAttributeItems(Attribute, IntValue, StringValue, true);

setAttributeItems ( Attribute , IntValue , StringValue , true ) ;


void zmtarzmTargetELFStreamer::emitTextAttribute(unsigned Attribute, StringRef String) {

void zmtarzmTargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


setAttributeItem(Attribute, String,  true);

setAttributeItem ( Attribute , String , true ) ;


void zmtarzmTargetELFStreamer :: finishAttributeSection ( ) {


if (Arch != zmtarzm::ArchKind::INVALID) {

if ( Arch != zmtarzm :: ArchKind :: INVALID ) {


MCELFStreamer &Streamer = getStreamer();

MCELFStreamer & Streamer = getStreamer ( ) ;


llvm :: sort ( Contents , AttributeItem :: LessTag ) ;


Streamer . SwitchSection ( AttributeSection ) ;


AttributeSection = Streamer.getContext().getELFSection(".zmtarzm_lower.attributes", ELF::SHT_zmtarzm_ATTRIBUTES, 0);

AttributeSection = Streamer . getContext ( ) . getELFSection ( ".zmtarzm_lower.attributes" , ELF :: SHT_zmtarzm_ATTRIBUTES , 0 ) ;


Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ;


const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;

const size_t VendorHeaderSize = 4 + CurrentVendor . size ( ) + 1 ;


const size_t ContentsSize = calculateContentSize();

const size_t ContentsSize = calculateContentSize ( ) ;


Streamer.emitInt32(VendorHeaderSize + TagHeaderSize + ContentsSize);

Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ;


Streamer . emitBytes ( CurrentVendor ) ;


Streamer . emitInt8 ( ELFAttrs :: File ) ;


Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ;


for ( i = 0 ; i < Contents . size ( ) ; ++ i ) {


Streamer . emitULEB128IntValue ( item . Tag ) ;


if ( item . Type == AttributeType :: Numeric ) {


Streamer . emitULEB128IntValue ( item . IntValue ) ;


if ( item . Type == AttributeType :: Text ) {


Streamer . emitBytes ( item . StringValue ) ;


if ( item . Type == AttributeType :: NumericAndText ) {


llvm_unreachable
(
"Invalid attribute type"
)
;


void zmtarzmTargetELFStreamer :: finishAttributeSection ( ) {


if ( Arch != zmtarzm :: ArchKind :: INVALID ) {


MCELFStreamer & Streamer = getStreamer ( ) ;


llvm :: sort ( Contents , AttributeItem :: LessTag ) ;


Streamer . SwitchSection ( AttributeSection ) ;


AttributeSection = Streamer . getContext ( ) . getELFSection ( ".zmtarzm_lower.attributes" , ELF :: SHT_zmtarzm_ATTRIBUTES , 0 ) ;


Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ;


const size_t VendorHeaderSize = 4 + CurrentVendor . size ( ) + 1 ;


const size_t ContentsSize = calculateContentSize ( ) ;


Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ;


Streamer . emitBytes ( CurrentVendor ) ;


Streamer . emitInt8 ( ELFAttrs :: File ) ;


Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ;


for ( i = 0 ; i < Contents . size ( ) ; ++ i ) {


Streamer . emitULEB128IntValue ( item . Tag ) ;


if ( item . Type == AttributeType :: Numeric ) {


Streamer . emitULEB128IntValue ( item . IntValue ) ;


if ( item . Type == AttributeType :: Text ) {


Streamer . emitBytes ( item . StringValue ) ;


if ( item . Type == AttributeType :: NumericAndText ) {


llvm_unreachable
(
"Invalid attribute type"
)
;


AttributeItem *getAttributeItem(unsigned Attribute) {

AttributeItem * getAttributeItem ( unsigned Attribute ) {


if ( Contents [ i ] . Tag == Attribute ) {


MCELFStreamer & zmtarzmTargetELFStreamer :: getStreamer ( ) {


return static_cast < MCELFStreamer & > ( Streamer ) ;


void setAttributeItem(unsigned Attribute, unsigned Value, bool OverwriteExisting) {

void setAttributeItem ( unsigned Attribute , unsigned Value , bool OverwriteExisting ) {


if (Item = getAttributeItem(Attribute)) {

if ( Item = getAttributeItem ( Attribute ) ) {


Item -> Type = AttributeType :: Numeric ;


Contents.push_back({AttributeType::Numeric, Attribute, Value, ""});

Contents . push_back ( { AttributeType :: Numeric , Attribute , Value , "" } ) ;


void setAttributeItem(unsigned Attribute, StringRef Value, bool OverwriteExisting) {

void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) {


Item -> StringValue = std :: string ( Value ) ;


Contents.push_back({AttributeType::Text, Attribute, 0, std::string(Value)});

Contents . push_back ( { AttributeType :: Text , Attribute , 0 , std :: string ( Value ) } ) ;


void setAttributeItems(unsigned Attribute, unsigned IntValue, StringRef StringValue, bool OverwriteExisting) {

void setAttributeItems ( unsigned Attribute , unsigned IntValue , StringRef StringValue , bool OverwriteExisting ) {


Item -> Type = AttributeType :: NumericAndText ;


Item -> StringValue = std :: string ( StringValue ) ;


Contents.push_back({AttributeType::NumericAndText, Attribute, IntValue, std::string(StringValue)});

Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue , std :: string ( StringValue ) } ) ;


zmtarzmTargetELFStreamer::zmtarzmTargetELFStreamer(MCStreamer &S,  const MCSubtargetInfo &STI) : zmtarzmTargetStreamer(S), CurrentVendor("zmtarzm") {

zmtarzmTargetELFStreamer :: zmtarzmTargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : zmtarzmTargetStreamer ( S ) , CurrentVendor ( "zmtarzm" ) {


MCA = getStreamer ( ) . getAssembler ( ) ;


MAB = static_cast < zmtarzmMCAsmBackend & > ( MCA . getBackend ( ) ) ;


EFlags = EFlags | ELF :: EF_zmtarzm_ABIV2 ;

EFlags = EFlags | ELF::EF_zmtarzm_ABIV2;


if ( Features [ zmtarzm :: ProcCK801 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_801 ;


if ( Features [ zmtarzm :: ProcCK802 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_802 ;


if ( Features [ zmtarzm :: ProcCK803 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_803 ;


if ( Features [ zmtarzm :: ProcCK804 ] ) {


if ( Features [ zmtarzm :: ProcCK805 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_805 ;


if ( Features [ zmtarzm :: ProcCK807 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_807 ;


if ( Features [ zmtarzm :: ProcCK810 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_810 ;


if ( Features [ zmtarzm :: ProcCK860 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_860 ;


if ( Features [ zmtarzm :: FeatureFPUV2_SF ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_FLOAT ;

EFlags = EFlags | ELF::EF_zmtarzm_FLOAT;


if ( Features [ zmtarzm :: FeatureFPUV3_SF ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_EFV1 ;


zmtarzmTargetELFStreamer :: zmtarzmTargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : zmtarzmTargetStreamer ( S ) , CurrentVendor ( "zmtarzm" ) {


MCA = getStreamer ( ) . getAssembler ( ) ;


MAB = static_cast < zmtarzmMCAsmBackend & > ( MCA . getBackend ( ) ) ;


if ( Features [ zmtarzm :: Featurezmtarzm64r6 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_64R6 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_64R6;


if ( Features [ zmtarzm :: Featurezmtarzm64r2 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_64R2 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_64R2;


if ( Features [ zmtarzm :: Featurezmtarzm64r3 ] ) {


if ( Features [ zmtarzm :: Featurezmtarzm64r5 ] ) {


if ( Features [ zmtarzm :: Featurezmtarzm64 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_64 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_64;


if ( Features [ zmtarzm :: Featurezmtarzm5 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_5 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_5;


if ( Features [ zmtarzm :: Featurezmtarzm4 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_4 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_4;


if ( Features [ zmtarzm :: Featurezmtarzm3 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_3 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_3;


if ( Features [ zmtarzm :: Featurezmtarzm32r6 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_32R6 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_32R6;


if ( Features [ zmtarzm :: Featurezmtarzm32r2 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_32R2 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_32R2;


if ( Features [ zmtarzm :: Featurezmtarzm32r3 ] ) {


if ( Features [ zmtarzm :: Featurezmtarzm32r5 ] ) {


if ( Features [ zmtarzm :: Featurezmtarzm32 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_32 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_32;


if ( Features [ zmtarzm :: Featurezmtarzm2 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_2 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_2;


if ( Features [ zmtarzm :: Featurezmtarzm1 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_ARCH_1 ;

EFlags = EFlags | ELF::EF_zmtarzm_ARCH_1;


if ( Features [ zmtarzm :: FeatureNaN2008 ] ) {


EFlags = EFlags | ELF :: EF_zmtarzm_NAN2008 ;

EFlags = EFlags | ELF::EF_zmtarzm_NAN2008;


EFlags = EFlags | ELF :: EF_zmtarzm_CPIC ;


FunctionPass * llvm :: createzmtarzmExpandAtomicPseudoPass ( ) {


return new zmtarzmExpandAtomicPseudo ( ) ;


zmtarzmExpandAtomicPseudo() : MachineFunctionPass(ID) {

zmtarzmExpandAtomicPseudo ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandAtomicPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ;


bool zmtarzmExpandAtomicPseudo::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandAtomicPseudo :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;


MachineBasicBlock::iterator NMBBI = std::next(MBBI);

MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;


Modified = Modified | expandMI(MBB, MBBI, NMBBI);

Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;


bool zmtarzmExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandAtomicPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);

return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);

return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);

return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOp(MBB, MBBI, NMBB);

return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandAtomicPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


bool zmtarzmExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());

TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandPseudoPass ( ) {


bool zmtarzmExpandPseudo::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;

MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();


MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;

MachineBasicBlock::iterator NMBBI = std::next(MBBI);


Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;

Modified = Modified | expandMI(MBB, MBBI, NMBBI);


bool zmtarzmExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandPseudo() : MachineFunctionPass(ID) {

zmtarzmExpandPseudo ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName ( ) const override {

StringRef getPassName() const override {


bool zmtarzmExpandPseudo::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;

TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandSDMAPass ( ) {


bool zmtarzmExpandSDMA::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandSDMA :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;

MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();


MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;

MachineBasicBlock::iterator NMBBI = std::next(MBBI);


Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;

Modified = Modified | expandMI(MBB, MBBI, NMBBI);


bool zmtarzmExpandSDMAInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandSDMAInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandSDMAInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandSDMAInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandSDMA() : MachineFunctionPass(ID) {

zmtarzmExpandSDMA ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandSDMAPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName ( ) const override {

StringRef getPassName() const override {


bool zmtarzmExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) {

bool zmtarzmExpandPseudo::runOnMachineFunction(MachineFunction &MF) {


TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;

TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandSSRPass ( ) {


bool zmtarzmExpandSSR::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandSSR :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;


MachineBasicBlock::iterator NMBBI = std::next(MBBI);

MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;


Modified = Modified | expandMI(MBB, MBBI, NMBBI);

Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;


bool zmtarzmExpandSSRInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandSSRInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);

return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);

return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);

return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOp(MBB, MBBI, NMBB);

return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandSSRInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandSSRInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandSSR() : MachineFunctionPass(ID) {

zmtarzmExpandSSR ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandSSRPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


bool zmtarzmExpandSSRInsts::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandSSRInsts :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());

TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;


Modified = Modified | expandMBB ( MBB ) ;


fixup_zmtarzm_pcrel_adr_imm21 = FirstTargetFixupKind ,


NumTargetFixupKinds = # - FirstTargetFixupKind

NumTargetFixupKinds = fixup_zmtarzm_invalid - FirstTargetFixupKind


fixup_zmtarzm_32 = FirstTargetFixupKind ,


fixup_zmtarzm_Branch20 = FirstTargetFixupKind ,


fixup_zmtarzm_NONE = FirstTargetFixupKind ,


fixup_zmtarzm_BO_7 = FirstTargetFixupKind ,


fixup_zmtarzm_call30 = FirstTargetFixupKind ,


fixup_zmtarzm_call_imm18 = FirstTargetFixupKind ,


fixup_zmtarzm_riprel_4byte = FirstTargetFixupKind ,


void zmtarzmFrameLowering::adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag) const {

void zmtarzmFrameLowering :: adjustReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DestReg , Register SrcReg , int64_t Val , MachineInstr :: MIFlag Flag ) const {


MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV), DestReg).addReg(SrcReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV ) , DestReg ) . addReg ( SrcReg ) ;


BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::ADDI), DestReg).addReg(SrcReg).addImm(Val).setMIFlag(Flag);

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: ADDI ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ;


Register ScratchReg = MRI.createVirtualRegister(&zmtarzm::GPRRegClass);

Register ScratchReg = MRI . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);

TII -> movImm ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ;


BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg).addReg(SrcReg).addReg(ScratchReg, RegState::Kill).setMIFlag(Flag);

BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ;


bool zmtarzmFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {

bool zmtarzmFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const {


if ( ! needPopSpecialFixUp ( * MBB . getParent ( ) ) ) {


MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);

MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ;


const MachineFunction &MF = *MBB.getParent();

const MachineFunction & MF = * MBB . getParent ( ) ;


if ( MF . getInfo < MachineFunctionInfo > ( ) -> hasSwiftAsyncContext ( ) ) {


if ( canUseLEAForSPInEpilogue ( * MBB . getParent ( ) ) ) {


return emitPopSpecialFixUp ( * TmpMBB , false ) ;


assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;

assert(MBB.getParent() && "Block is not attached to a function!");


bool zmtarzmFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {

bool zmtarzmFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const {


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const Subtarget &Subtarget = MF->getSubtarget<Subtarget>();

const Subtarget & Subtarget = MF -> getSubtarget < Subtarget > ( ) ;


const RegisterInfo *RegInfo = Subtarget.getRegisterInfo();

const RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


if ( ! RegInfo -> hasStackRealignment ( * MF ) ) {


return findScratchNonCalleeSaveRegister(TmpMBB) != zmtarzm::NoRegister;

return findScratchNonCalleeSaveRegister ( TmpMBB ) != zmtarzm :: NoRegister ;


if ( ! MBB . isLiveIn ( zmtarzm :: EFLAGS ) ) {


const MachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const MachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


return findScratchRegister ( TmpMBB , false , twoUniqueScratchRegsRequired ( TmpMBB ) ) ;

return findScratchRegister(TmpMBB, false, twoUniqueScratchRegsRequired(TmpMBB));


void zmtarzmFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const {

void zmtarzmFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {


TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


static const MCPhysReg CSRegs[] = {zmtarzm::R0,  zmtarzm::R1,  zmtarzm::R2, zmtarzm::R3, zmtarzm::R12, zmtarzm::R13, 0};

static const MCPhysReg CSRegs [ ] = { zmtarzm :: R0 , zmtarzm :: R1 , zmtarzm :: R2 , zmtarzm :: R3 , zmtarzm :: R12 , zmtarzm :: R13 , 0 } ;


for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) {


static const MCPhysReg CSHRegs[] = {zmtarzm::R18, zmtarzm::R19, zmtarzm::R20, zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24, zmtarzm::R25, 0};

static const MCPhysReg CSHRegs [ ] = { zmtarzm :: R18 , zmtarzm :: R19 , zmtarzm :: R20 , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , 0 } ;


for ( unsigned i = 0 ; CSHRegs [ i ] ; ++ i ) {


static const MCPhysReg CSF32Regs[] = {zmtarzm::F8_32,  zmtarzm::F9_32,  zmtarzm::F10_32, zmtarzm::F11_32, zmtarzm::F12_32, zmtarzm::F13_32, zmtarzm::F14_32, zmtarzm::F15_32, 0};

static const MCPhysReg CSF32Regs [ ] = { zmtarzm :: F8_32 , zmtarzm :: F9_32 , zmtarzm :: F10_32 , zmtarzm :: F11_32 , zmtarzm :: F12_32 , zmtarzm :: F13_32 , zmtarzm :: F14_32 , zmtarzm :: F15_32 , 0 } ;


static const MCPhysReg CSF64Regs[] = {zmtarzm::F8_64,  zmtarzm::F9_64,  zmtarzm::F10_64, zmtarzm::F11_64, zmtarzm::F12_64, zmtarzm::F13_64, zmtarzm::F14_64, zmtarzm::F15_64, 0};

static const MCPhysReg CSF64Regs [ ] = { zmtarzm :: F8_64 , zmtarzm :: F9_64 , zmtarzm :: F10_64 , zmtarzm :: F11_64 , zmtarzm :: F12_64 , zmtarzm :: F13_64 , zmtarzm :: F14_64 , zmtarzm :: F15_64 , 0 } ;


const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs();

const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ;


for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) {


if ( zmtarzm :: FPR64RegClass . contains ( Regs [ i ] ) ) {


if ( zmtarzm :: FPR32RegClass . contains ( Regs [ i ] ) ) {


CFI -> setLRIsSpilled ( SavedRegs . test ( zmtarzm :: R15 ) ) ;


for (unsigned Reg : SavedRegs.set_bits()) {

for ( unsigned Reg : SavedRegs . set_bits ( ) ) {


auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;

auto RegSize = TRI -> getRegSizeInBits ( Reg , MRI ) / 8 ;


CFI -> setCalleeSaveAreaSize ( CSStackSize ) ;


uint64_t Limit = estimateRSStackSizeLimit(MF, STI);

uint64_t Limit = estimateRSStackSizeLimit ( MF , STI ) ;


bool BigFrame = (MFI.estimateStackSize(MF) + CSStackSize >= Limit);

bool BigFrame = ( MFI . estimateStackSize ( MF ) + CSStackSize >= Limit ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


unsigned size = TRI -> getSpillSize ( * RC ) ;


Align align = TRI -> getSpillAlign ( * RC ) ;


RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( size , align , false ) ) ;


MachineBasicBlock::iterator zmtarzmFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {

MachineBasicBlock :: iterator zmtarzmFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const {


int64_t Amount = MI->getOperand(0).getImm();

int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ;


if (MI->getOpcode() == zmtarzm::ADJCALLSTACKDOWN) {

if ( MI -> getOpcode ( ) == zmtarzm :: ADJCALLSTACKDOWN ) {


adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);

adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ;


void zmtarzmFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineBasicBlock::iterator MBBI = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . end ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


LastFrameDestroy = std::prev(MBBI, CSI.size());

LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ;


uint64_t StackSize = MFI.getStackSize();

uint64_t StackSize = MFI . getStackSize ( ) ;


uint64_t ActualSize = CFI->getCalleeSaveAreaSize() + CFI->getVarArgsSaveSize();

uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ;


BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg).addReg(FPReg).setMIFlag(MachineInstr::NoFlags);

BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ;


adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize), MachineInstr::FrameDestroy);

adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize, MachineInstr::FrameDestroy);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ;


if (materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDrr ) , zmtarzm :: SP ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


if (!materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( ! materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI(MBB, MBBI, DL, TII.get(zmtarzm::ADDri), zmtarzm::SP).addReg(StackReg).addImm(StackSize).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDri ) , zmtarzm :: SP ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsUp, #, #), STI(STI) {

explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsUp , # , # ) , STI ( STI ) {

explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 16 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 16, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( 16 ) , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(16), 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 4 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 4, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 8 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 8, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 2 , - 2 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 2, -2), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( 8 ) , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(8), 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( 4 ) , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(4), 0), STI(STI) {


StackOffset zmtarzmFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const {

StackOffset zmtarzmFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const {


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const auto *CFI = MF.getInfo<MachineFunctionInfo>();

const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const auto & CSI = MFI . getCalleeSavedInfo ( ) ;

const auto &CSI = MFI.getCalleeSavedInfo();


int Offset = MFI.getObjectOffset(FI) + MFI.getOffsetAdjustment();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ;


MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();

MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ;


Offset = Offset + CFI->getVarArgsSaveSize() + CFI->getCalleeSaveAreaSize();

Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


if ( ! MFI . isFixedObjectIndex ( FI ) ) {


FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : zmtarzm :: R14 ;

FrameReg = hasBP(MF) ? getBPReg(STI) : zmtarzm::R14;


Offset = Offset + MFI . getStackSize ( ) ;


if ( MFI . isFixedObjectIndex ( FI ) ) {


if ( ! RI -> hasStackRealignment ( MF ) ) {


int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);

int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ;


return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize());

return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ;


if ( RI -> needsStackRealignment ( MF ) ) {


FrameReg = RI -> getFrameRegister ( MF ) ;


return StackOffset :: getFixed ( Offset ) ;


StackOffset zmtarzmFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const {


const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ;


MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ;


Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


if ( ! MFI . isFixedObjectIndex ( FI ) ) {


Offset = Offset + MFI . getStackSize ( ) ;


if ( MFI . isFixedObjectIndex ( FI ) ) {


if ( ! RI -> hasStackRealignment ( MF ) ) {


int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ;


return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ;


if ( RI -> needsStackRealignment ( MF ) ) {


FrameReg = RI -> getFrameRegister ( MF ) ;


return StackOffset :: getFixed ( FrameOffset ) ;


bool zmtarzmFrameLowering::hasBP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasBP ( const MachineFunction & MF ) const {


const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo *TRI = STI.getRegisterInfo();

const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;


return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);

return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment ( MF ) ;


bool zmtarzmFrameLowering::hasFP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasFP ( const MachineFunction & MF ) const {


const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


bool zmtarzmFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {


return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


void zmtarzmFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const {

void zmtarzmFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const {


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


if ( ! isInt < # > ( MFI . estimateStackSize ( MF ) ) ) {

if ( ! isInt < 9 > ( MFI . estimateStackSize ( MF ) ) ) {


int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);

int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ;


RS -> addScavengingFrameIndex ( RegScavFI ) ;


bool zmtarzmFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);

TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg()).addReg(zmtarzm::R15);

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: MOV32mrpop ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::MOV32mrpop), CSI[i].getReg()).addReg(zmtarzm::R15);


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg());

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSHRr ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSHRr)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;