extern "C" void LLVMInitializezmtarzmTargetInfo() {

extern "C" void LLVMInitializezmtarzmTargetInfo ( ) {


RegisterTarget<Triple::zmtarzm> X(ThezmtarzmTarget, "zmtarzm", "zmtarzm");

RegisterTarget < Triple :: zmtarzm > X ( ThezmtarzmTarget , "zmtarzm" , "zmtarzm" ) ;


bool zmtarzmTargetMachine::addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmISelDag ( * this , OptLevel ) ) ;


bool zmtarzmTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmSimpleBranchOptPass ( ) ) ;


PM . add ( createzmtarzmStackUsage ( ) ) ;


bool zmtarzmTargetMachine::addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmStackAnalysisPrepare ( ) ) ;


PM . add ( createzmtarzmLoopMetadataLowering ( ) ) ;


virtual const zmtarzmFrameLowering *getFrameLowering() const {

virtual const zmtarzmFrameLowering * getFrameLowering ( ) const {


virtual const zmtarzmInstrInfo *getInstrInfo() const {

virtual const zmtarzmInstrInfo * getInstrInfo ( ) const {


virtual const TargetRegisterInfo *getRegisterInfo() const {

virtual const TargetRegisterInfo * getRegisterInfo ( ) const {


return & InstrInfo . getRegisterInfo ( ) ;


virtual const zmtarzmSelectionDAGInfo* getSelectionDAGInfo() const {

virtual const zmtarzmSelectionDAGInfo * getSelectionDAGInfo ( ) const {


virtual const zmtarzmSubtarget *getSubtargetImpl() const {

virtual const zmtarzmSubtarget * getSubtargetImpl ( ) const {


virtual const TargetData *getTargetData() const {

virtual const TargetData * getTargetData ( ) const {


virtual const zmtarzmTargetLowering *getTargetLowering() const {

virtual const zmtarzmTargetLowering * getTargetLowering ( ) const {


extern "C" void LLVMInitializezmtarzmTarget() {

extern "C" void LLVMInitializezmtarzmTarget ( ) {


RegisterTargetMachine < zmtarzmTargetMachine > X ( ThezmtarzmTarget ) ;


zmtarzmTargetMachine::zmtarzmTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, Reloc::Model RM, CodeModel::Model CM) : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-v64:32:32-v128:32:32-n32"), InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) {


MCSection *zmtarzmTargetObjectFile::getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


StringRef SectionName = GO->getSection();

StringRef SectionName = GO -> getSection ( ) ;


if ( SectionName . startswith ( ".zmtarzm.comment." ) ) {


if (isExecuteOnlyFunction(GO, SK, TM)) {

if ( isExecuteOnlyFunction ( GO , SK , TM ) ) {


SK = SectionKind :: getExecuteOnly ( ) ;


return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);

return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ;


MCSection *zmtarzmELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const {

MCSection * zmtarzmELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const {


if ( isConstantInSmallSection ( DL , C ) ) {


return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment);

return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ;


void zmtarzmELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {

void zmtarzmELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {


TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


InitializeELF ( TM . Options . UseInitArray ) ;


SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


this->TM = &static_cast<const zmtarzmTargetMachine &>(TM);

this -> TM = & static_cast < const zmtarzmTargetMachine & > ( TM ) ;


MCSection *zmtarzmELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


if ( isGlobalInSmallSection ( GO , TM ) ) {


return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM);

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


bool zmtarzmAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const {

bool zmtarzmAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const {


unsigned zmtarzmAsmBackend::getRelaxedOpcode(unsigned Op) const {

unsigned zmtarzmAsmBackend :: getRelaxedOpcode ( unsigned Op ) const {


void zmtarzmAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {

void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand &MO = MI->getOperand(OpNo);

const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


llvm_unreachable
(
"not implemented"
)
;


O << getRegisterName ( MO . getReg ( ) ) ;


case MachineOperand :: MO_MachineBasicBlock :


O << * MO . getMBB ( ) -> getSymbol ( ) ;


case MachineOperand :: MO_GlobalAddress :


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


case MachineOperand :: MO_ConstantPoolIndex :


O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


case MachineOperand :: MO_BlockAddress :


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


case MachineOperand :: MO_ExternalSymbol :


case MachineOperand :: MO_JumpTableIndex :


O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if (Kind >= FirstLiteralRelocationKind){

if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind;

return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;

Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");


case zmtarzm :: fixup_zmtarzm_RELATIVE :


case zmtarzm :: fixup_zmtarzm_JUMP_SLOT :


case zmtarzm :: fixup_zmtarzm_TLS_DTPMOD32 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPMOD64 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPREL32 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPREL64 :


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PC_LO32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_PC_LO32) {


Ctx.reportError(Fixup.getLoc(), "1-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "8-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "1-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative srel32 relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_hi32 relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_lo32 relocation is not supported");


case zmtarzm :: fixup_zmtarzm_got_hi32 :


case zmtarzm :: fixup_zmtarzm_got_lo32 :


case zmtarzm :: fixup_zmtarzm_gotoff_hi32 :


case zmtarzm :: fixup_zmtarzm_gotoff_lo32 :


case zmtarzm :: fixup_zmtarzm_plt_hi32 :


case zmtarzm :: fixup_zmtarzm_plt_lo32 :


case zmtarzm :: fixup_zmtarzm_tls_gd_hi32 :


case zmtarzm :: fixup_zmtarzm_tls_gd_lo32 :


case zmtarzm :: fixup_zmtarzm_tpoff_hi32 :


case zmtarzm :: fixup_zmtarzm_tpoff_lo32 :


bool zmtarzmInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {

bool zmtarzmInstrInfo :: isBranchOffsetInRange ( unsigned BranchOpc , int64_t BrOffset ) const {


llvm_unreachable
(
"Unexpected opcode!"
)
;


static inline bool IsBRF(unsigned BrOpc) {

static inline bool IsBRF ( unsigned BrOpc ) {


static inline bool IsBRT(unsigned BrOpc) {

static inline bool IsBRT ( unsigned BrOpc ) {


static inline bool IsBRU(unsigned BrOpc) {

static inline bool IsBRU ( unsigned BrOpc ) {


static inline bool IsBR_JT(unsigned BrOpc) {

static inline bool IsBR_JT ( unsigned BrOpc ) {


static inline bool IsCondBranch(unsigned BrOpc) {

static inline bool IsCondBranch ( unsigned BrOpc ) {


bool zmtarzmInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const {

bool zmtarzmInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {


if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF)) {

if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) {


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


zmtarzmTargetLowering::ConstraintType zmtarzmTargetLowering::getConstraintType(StringRef Constraint) const {

zmtarzmTargetLowering :: ConstraintType zmtarzmTargetLowering :: getConstraintType ( StringRef Constraint ) const {


return TargetLowering :: getConstraintType ( Constraint ) ;


unsigned zmtarzmMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


assert(MO.isReg() && "Expected a register.");

assert
(
MO
.
isReg
(
)
&&
"Expected a register."
)
;


llvm_unreachable
(
"Invalid mask register."
)
;


static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {

static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) {


llvm_unreachable("Can't handle nested target expression");

llvm_unreachable
(
"Can't handle nested target expression"
)
;


fixELFSymbolsInTLSFixupsImpl ( cast < MCExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ;


const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ;


fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


StringRef zmtarzmMCExpr::getVariantKindName(VariantKind Kind) {

StringRef zmtarzmMCExpr :: getVariantKindName ( VariantKind Kind ) {


llvm_unreachable("Invalid ELF symbol kind");

llvm_unreachable
(
"Invalid ELF symbol kind"
)
;


bool zmtarzmRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const {


void zmtarzmAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,const MCValue &Target,MutableArrayRef<char> Data, uint64_t Value,bool IsResolved, const MCSubtargetInfo *STI) const {

void zmtarzmAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const {


if (Kind >= FirstLiteralRelocationKind) {

if ( Kind >= FirstLiteralRelocationKind ) {


MCContext & Ctx = Asm . getContext ( ) ;


Value = adjustFixupValue ( Fixup , Value , Ctx ) ;

Value = adjustFixupValue(Fixup, Value, Ctx);


NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ;


assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");

assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;


if ( MCAsmBackend :: Endian == support :: little ) {

if (MCAsmBackend::Endian == support::little) {


Data [ Offset + i ] = Data [ Offset + i ] | uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ;

Data[Offset + i] = Data[Offset + i] | uint8_t((Value >> (i * 8)) & 0xff);


if ( MCAsmBackend :: Endian == support :: big ) {

if (MCAsmBackend::Endian == support::big) {


Data [ Offset + i ] = Data [ Offset + i ] | uint8_t ( ( Value >> ( ( NumBytes - i - 1 ) * 8 ) ) & 0xff ) ;

Data[Offset + i] = Data[Offset + i] | uint8_t((Value >> ((NumBytes - i - 1) * 8)) & 0xff);


const MCFixupKindInfo & zmtarzmAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {

const MCFixupKindInfo & zmtarzmAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const {


const static MCFixupKindInfo Infos[zmtarzm::NumTargetFixupKinds] = {

const static MCFixupKindInfo Infos [ zmtarzm :: NumTargetFixupKinds ] = {


{ "fixup_zmtarzm_sopp_br" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_sopp_br" zmsplit 0 zmsplit 16 zmsplit MCFixupKindInfo::FKF_IsPCRel

{ "fixup_zmtarzm_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },


"fixup_zmtarzm_rodata" zmsplit 0 zmsplit 32 zmsplit MCFixupKindInfo::FKF_IsPCRel

{ "fixup_zmtarzm_rodata", 0, 32, MCFixupKindInfo::FKF_IsPCRel }


return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ;


return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!");

assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;


static_assert((array_lengthof(Infos)) == zmtarzm::NumTargetFixupKinds, "Not all fixup kinds added to Infos array");


return Infos[Kind - FirstTargetFixupKind];

return Infos [ Kind - FirstTargetFixupKind ] ;


zmtarzmMCAsmInfo::zmtarzmMCAsmInfo(const Triple &TT) {

zmtarzmMCAsmInfo :: zmtarzmMCAsmInfo ( const Triple & TT ) {


ExceptionsType = ExceptionHandling :: DwarfCFI ;


void addExpr(MCInst &Inst, const MCExpr *Expr) const {

void addExpr ( MCInst & Inst , const MCExpr * Expr ) const {


assert(Expr && "Expr shouldn't be null!");

assert
(
Expr
&&
"Expr shouldn't be null!"
)
;


zmtarzmMCExpr::VariantKind VK = zmtarzmMCExpr::VK_zmtarzm_None;

zmtarzmMCExpr :: VariantKind VK = zmtarzmMCExpr :: VK_zmtarzm_None ;


bool IsConstant = evaluateConstantImm(Expr, Imm, VK);

bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ;


Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, zmtarzmMCExpr::VariantKind &VK) const {

static bool evaluateConstantImm ( const MCExpr * Expr , int64_t & Imm , zmtarzmMCExpr :: VariantKind & VK ) const {


if (auto *RE = dyn_cast<zmtarzmMCExpr>(Expr)) {

if ( auto * RE = dyn_cast < zmtarzmMCExpr > ( Expr ) ) {


return RE -> evaluateAsConstant ( Imm ) ;


if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {

if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) {


if (evaluateConstantImm(getImm(), Imm, VK)) {

if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) {


if (!evaluateConstantImm(getImm(), Imm, VK)) {

if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) {


OperandMatchResultTy zmtarzmAsmParser::parseImmediate(OperandVector &Operands) {

OperandMatchResultTy zmtarzmAsmParser :: parseImmediate ( OperandVector & Operands ) {


SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);

SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ;


if (getLexer().getKind() == AsmToken::LParen) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) {


if ( getParser ( ) . parseExpression ( Res ) ) {


Operands.push_back(zmtarzmOperand::createImm(Res, S, E, isRV64()));

Operands . push_back ( zmtarzmOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ;


if (getLexer().getKind() == AsmToken::Minus) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) {


if (getLexer().getKind() == AsmToken::Plus) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) {


if (getLexer().getKind() == AsmToken::Integer) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) {


if (getLexer().getKind() == AsmToken::String) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: String ) {


if (getLexer().getKind() == AsmToken::Identifier) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) {


if ( getParser ( ) . parseIdentifier ( Res ) ) {


if ( getLexer ( ) . getKind ( ) == # ) {


if (getLexer().getKind() == AsmToken::Percent) {

if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) {


return parseOperandWithModifier ( Operands ) ;


template <unsigned N> static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


assert(isUInt<N>(Imm) && "Invalid immediate");

assert
(
isUInt
<
N
>
(
Imm
)
&&
"Invalid immediate"
)
;


addImplySP ( Inst , Address , Decoder ) ;


Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;


template <unsigned N> static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmDisassembler() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmDisassembler ( ) {


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzmTarget ( ) , createzmtarzmDisassembler ) ;


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzm32Target ( ) , createzmtarzmDisassembler ) ;


TargetRegistry :: RegisterMCDisassembler ( getThezmtarzm64Target ( ) , createzmtarzmDisassembler ) ;


ArrayRef<std::pair<unsigned, const char *>> zmtarzmInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {


static const std::pair<unsigned, const char *> TargetFlags[] = #;

static const std :: pair < unsigned , const char * > TargetFlags [ ] = # ;

static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOTPCREL , "amdgpu-gotprel" } , { MO_GOTPCREL32_LO , "amdgpu-gotprel32-lo" } , { MO_GOTPCREL32_HI , "amdgpu-gotprel32-hi" } , { MO_REL32_LO , "amdgpu-rel32-lo" } , { MO_REL32_HI , "amdgpu-rel32-hi" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{ MO_GOTPCREL, "amdgpu-gotprel" },{ MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" },{ MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" },{ MO_REL32_LO, "amdgpu-rel32-lo" },{ MO_REL32_HI, "amdgpu-rel32-hi" }};


Optional<DestSourcePair> zmtarzmInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {

Optional < DestSourcePair > zmtarzmInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ;


if ( MI . getOperand ( 2 ) . getImm ( ) == 0x0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ORRWrs ) {

if (MI.getOpcode() == zmtarzm::ORRWrs) {


if (MI.getOperand(1).getReg() == zmtarzm::WZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: WZR ) {


if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ;


if (MI.getOperand(2).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 2 ) . getReg ( ) == zmtarzm :: R0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ORRXrs ) {

if (MI.getOpcode() == zmtarzm::ORRXrs) {


if (MI.getOperand(1).getReg() == zmtarzm::XZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: XZR ) {


if (MI.getOperand(1).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: R0 ) {


static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl<MachineOperand> &Cond) {

static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) {


assert(LastInst.getDesc().isConditionalBranch() && "Unknown conditional branch");

assert
(
LastInst
.
getDesc
(
)
.
isConditionalBranch
(
)
&&
"Unknown conditional branch"
)
;


Target = LastInst . getOperand ( 2 ) . getMBB ( ) ;


Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ;


Cond . push_back ( LastInst . getOperand ( 0 ) ) ;


Cond . push_back ( LastInst . getOperand ( # ) ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) {


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_byte ) {

if (IntNo == Intrinsic::zmtarzm_load_byte) {


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_half ) {

if (IntNo == Intrinsic::zmtarzm_load_half) {


if ( IntNo == Intrinsic :: zmtarzm_load_word ) {

if (IntNo == Intrinsic::zmtarzm_load_word) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


SDValue zmtarzmTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const {


const zmtarzmRegisterInfo &RI = *Subtarget.getRegisterInfo();

const zmtarzmRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


Register FrameReg = RI.getFrameRegister(MF);

Register FrameReg = RI . getFrameRegister ( MF ) ;


SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ;


unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, DAG.getIntPtrConstant(Offset, DL));

SDValue Ptr = DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;


SDValue zmtarzmTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{

SDValue zmtarzmTargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const {


MFI . setReturnAddressIsTaken ( true ) ;


if (verifyReturnAddressArgumentIsConstant(Op, DAG)) {

if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) {


SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);

SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ;


SDValue Offset = DAG.getConstant(Off, DL, VT);

SDValue Offset = DAG . getConstant ( Off , DL , VT ) ;


return DAG.getLoad(VT, DL, DAG.getEntryNode(), DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));

Register Reg = MF . addLiveIn ( RI . getRARegister ( ) , getRegClassFor ( XLenVT ) ) ;


return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ;


int64_t zmtarzmMCExpr::evaluateAsInt64(int64_t Value) const {

int64_t zmtarzmMCExpr :: evaluateAsInt64 ( int64_t Value ) const {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_LO ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_LO) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HI ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HI) {


static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {

static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) {


if (Expr->getKind() == MCExpr::Target) {

if ( Expr -> getKind ( ) == MCExpr :: Target ) {


llvm_unreachable("Can't handle nested target expression");

llvm_unreachable
(
"Can't handle nested target expression"
)
;


fixELFSymbolsInTLSFixupsImpl ( cast < MCExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


if (Expr->getKind() == MCExpr::Constant) {

if ( Expr -> getKind ( ) == MCExpr :: Constant ) {


if (Expr->getKind() == MCExpr::Binary) {

if ( Expr -> getKind ( ) == MCExpr :: Binary ) {


fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ;


if (Expr->getKind() == MCExpr::SymbolRef) {

if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) {


const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ;


if ( Expr -> getKind ( ) == MCExpr :: Unary ) {


fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


static MCTargetStreamer *createzmtarzmObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {

static MCTargetStreamer * createzmtarzmObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {


const Triple &TT = STI.getTargetTriple();

const Triple & TT = STI . getTargetTriple ( ) ;


return new zmtarzmTargetELFStreamer(S, STI);

return new zmtarzmTargetELFStreamer ( S , STI ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for (Target *T : {&getThezmtarzm32Target(), &getThezmtarzm64Target()}) {

for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


auto &Subtarget = MF->getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF -> getSubtarget < zmtarzmSubtarget > ( ) ;


if (MF->getFunction().getCallingConv() == #) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == # ) {


if ( MF -> getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) {


if (MF->getFnAttribute("interrupt").getValueAsString() == #) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == # ) {


if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


if ( Subtarget . hasFPUv3DoubleFloat ( ) ) {


if ( Subtarget . hasFPUv3SingleFloat ( ) ) {


if ( Subtarget . hasFPUv2DoubleFloat ( ) ) {


if ( Subtarget . hasFPUv2SingleFloat ( ) ) {


if ( Subtarget . getTargetABI ( ) == # ) {


explicit FrepLoop ( MachineLoop * ML ) {


void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


zmtarzmSubtarget &zmtarzmSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {

zmtarzmSubtarget & zmtarzmSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) {


CPUName = Is64Bit ? "generic-la64" : "generic-la32";


ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ;


TargetABI = Is64Bit ? zmtarzmABI::ABI_LP64D : zmtarzmABI::ABI_ILP32D;

TargetABI = Is64Bit ? zmtarzmABI :: ABI_LP64D : zmtarzmABI :: ABI_ILP32D ;


int zmtarzmTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) {

int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers");


unsigned Ty->getPrimitiveSizeInBits() = Ty->getPrimitiveSizeInBits();

unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if (Ty->getPrimitiveSizeInBits() == 0) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() > 64) {

if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {

if (Opcode == Instruction::GetElementPtr) {


if (Ty->getPrimitiveSizeInBits() == 8) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


int NumConstants = divideCeil(Ty->getPrimitiveSizeInBits(), 64);

int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if (getIntImmCost(Imm, Ty, CostKind) <= NumConstants * TTI::TCC_Basic) {

if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost(Imm, Ty, CostKind);

return getIntImmCost ( Imm , Ty , CostKind ) ;


if (Imm.getZExtValue() == 0x100000000ULL) {

if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() <= 32) {

if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( Opcode == Instruction :: Select ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


"getIntImmCost can only estimate cost of materialising integers"


unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {


if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost ( Imm , Ty , CostKind ) ;


if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


if ( Opcode == Instruction :: Select ) {


int zmtarzmTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);

return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if (IID == Intrinsic::sadd_with_overflow) {

if ( IID == Intrinsic :: sadd_with_overflow ) {


Cost = zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

Cost = zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ;

return (Cost <= NumConstants * TTI::TCC_Basic) ? static_cast<int>(TTI::TCC_Free) : Cost;


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < # > ( - Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::uadd_with_overflow) {

if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: ssub_with_overflow ) {

if (IID == Intrinsic::ssub_with_overflow) {


if ( IID == Intrinsic :: usub_with_overflow ) {

if (IID == Intrinsic::usub_with_overflow) {


if ( IID == Intrinsic :: smul_with_overflow ) {

if (IID == Intrinsic::smul_with_overflow) {


if ( isUInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: umul_with_overflow ) {

if (IID == Intrinsic::umul_with_overflow) {


if (IID == Intrinsic::experimental_stackmap) {

if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::experimental_patchpoint_void) {

if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if (IID == Intrinsic::experimental_patchpoint_i64) {

if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


int zmtarzmTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {

if ((Imm.getZExtValue() & 0xffffffff) == 0) {


zmtarzmMCAsmInfo::zmtarzmMCAsmInfo(const Target &T, StringRef TT) {

zmtarzmMCAsmInfo :: zmtarzmMCAsmInfo ( const Target & T , StringRef TT ) {


void zmtarzmAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {

void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand &MO = MI->getOperand(OpNo);

const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if (MO.getType() == MachineOperand::MO_Register) {

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if (MO.getType() == MachineOperand::MO_Immediate) {

if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if (MO.getType() == MachineOperand::MO_MachineBasicBlock) {

if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if (MO.getType() == MachineOperand::MO_GlobalAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if (MO.getType() == MachineOperand::MO_ConstantPoolIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if (MO.getType() == MachineOperand::MO_BlockAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if (MO.getType() == MachineOperand::MO_JumpTableIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


case MachineOperand :: MO_MachineBasicBlock :


case MachineOperand :: MO_GlobalAddress :


case MachineOperand :: MO_ConstantPoolIndex :


case MachineOperand :: MO_BlockAddress :


case MachineOperand :: MO_ExternalSymbol :


case MachineOperand :: MO_JumpTableIndex :


static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {

static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) {


llvm_unreachable("Can't handle nested target expression");

llvm_unreachable
(
"Can't handle nested target expression"
)
;


fixELFSymbolsInTLSFixupsImpl ( cast < MCExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ;


const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ;


fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


std::unique_ptr<MCObjectTargetWriter> zmtarzmAsmBackend::createObjectTargetWriter() const {

std :: unique_ptr < MCObjectTargetWriter > zmtarzmAsmBackend :: createObjectTargetWriter ( ) const {


return createzmtarzmELFObjectWriter ( OSABI , Is64Bit ) ;


const MCFixupKindInfo & zmtarzmAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {

const MCFixupKindInfo & zmtarzmAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const {


const static MCFixupKindInfo Infos[zmtarzm::NumTargetFixupKinds] = {

const static MCFixupKindInfo Infos [ zmtarzm :: NumTargetFixupKinds ] = {


"fixup_zmtarzm_32" zmsplit 0 zmsplit 32 zmsplit 0


{ "fixup_zmtarzm_10_pcrel" , 0 , 10 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_10_pcrel" zmsplit 0 zmsplit 10 zmsplit MCFixupKindInfo::FKF_IsPCRel

{"fixup_zmtarzm_10_pcrel", 0, 10, MCFixupKindInfo::FKF_IsPCRel},


"fixup_zmtarzm_16" zmsplit 0 zmsplit 16 zmsplit 0


{ "fixup_zmtarzm_16_pcrel" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_16_pcrel" zmsplit 0 zmsplit 16 zmsplit MCFixupKindInfo::FKF_IsPCRel

{"fixup_zmtarzm_16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel},


"fixup_zmtarzm_16_byte" zmsplit 0 zmsplit 16 zmsplit 0


{ "fixup_zmtarzm_16_pcrel_byte" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_16_pcrel_byte" zmsplit 0 zmsplit 16 zmsplit MCFixupKindInfo::FKF_IsPCRel

{"fixup_zmtarzm_16_pcrel_byte", 0, 16, MCFixupKindInfo::FKF_IsPCRel},


{ "fixup_zmtarzm_2x_pcrel" , 0 , 10 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_2x_pcrel" zmsplit 0 zmsplit 10 zmsplit MCFixupKindInfo::FKF_IsPCRel

{"fixup_zmtarzm_2x_pcrel", 0, 10, MCFixupKindInfo::FKF_IsPCRel},


{ "fixup_zmtarzm_rl_pcrel" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } ,

"fixup_zmtarzm_rl_pcrel" zmsplit 0 zmsplit 16 zmsplit MCFixupKindInfo::FKF_IsPCRel

{"fixup_zmtarzm_rl_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel},


"fixup_zmtarzm_8" zmsplit 0 zmsplit 8 zmsplit 0


"fixup_zmtarzm_sym_diff" zmsplit 0 zmsplit 32 zmsplit 0


if (Kind >= FirstLiteralRelocationKind) {

if ( Kind >= FirstLiteralRelocationKind ) {


return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ;


return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!");

assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;


static_assert((array_lengthof(Infos)) == zmtarzm::NumTargetFixupKinds, "Not all fixup kinds added to Infos array");


return Infos[Kind - FirstTargetFixupKind];

return Infos [ Kind - FirstTargetFixupKind ] ;


zmtarzmMCAsmInfo::zmtarzmMCAsmInfo(const Triple &TT) {

zmtarzmMCAsmInfo :: zmtarzmMCAsmInfo ( const Triple & TT ) {


ExceptionsType = ExceptionHandling :: DwarfCFI ;


unsigned zmtarzmAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned Kind) {

unsigned zmtarzmAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) {


zmtarzmOperand &Op = static_cast<zmtarzmOperand &>(AsmOp);

zmtarzmOperand & Op = static_cast < zmtarzmOperand & > ( AsmOp ) ;


if ( zmtarzmMCRegisterClasses [ # ] . contains ( Reg ) ) {

if ( zmtarzmMCRegisterClasses [ zmtarzm :: FPR32RegClassID ] . contains ( Reg ) ) {


Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ;


if ( Op . Reg . RegNum < zmtarzm :: F0_64 ) {


if ( Op . Reg . RegNum > zmtarzm :: F31_64 ) {


if ( zmtarzmMCRegisterClasses [ zmtarzm :: GPRRegClassID ] . contains ( Reg ) ) {


Op . Reg . RegNum = MRI -> getEncodingValue ( Reg ) + zmtarzm :: R0_R1 ;

Op.Reg.RegNum = MRI->getEncodingValue(Reg) + zmtarzm::R0_R1;


bool zmtarzmCleanupVSETVLI::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmCleanupVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


template <unsigned N> static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


assert(isUInt<N>(Imm) && "Invalid immediate");

assert
(
isUInt
<
N
>
(
Imm
)
&&
"Invalid immediate"
)
;


addImplySP ( Inst , Address , Decoder ) ;


Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;


template <unsigned N> static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) {

template < unsigned N > static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {


Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if (Kind >= FirstLiteralRelocationKind){

if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind;

return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");

Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;


if ( Kind == zmtarzm :: fixup_zmtarzm_32 ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_64 ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_RELATIVE ) {

if(Kind == zmtarzm::fixup_zmtarzm_RELATIVE) {


if ( Kind == zmtarzm :: fixup_zmtarzm_COPY ) {

if(Kind == zmtarzm::fixup_zmtarzm_COPY) {


if ( Kind == zmtarzm :: fixup_zmtarzm_JUMP_SLOT ) {

if(Kind == zmtarzm::fixup_zmtarzm_JUMP_SLOT) {


if ( Kind == zmtarzm :: fixup_zmtarzm_TLS_DTPMOD32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_TLS_DTPMOD32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_TLS_DTPMOD64 ) {

if(Kind == zmtarzm::fixup_zmtarzm_TLS_DTPMOD64) {


if ( Kind == zmtarzm :: fixup_zmtarzm_TLS_DTPREL32 ) {

if(Kind == zmtarzm::fixup_zmtarzm_TLS_DTPREL32) {


if ( Kind == zmtarzm :: fixup_zmtarzm_TLS_DTPREL64 ) {

if(Kind == zmtarzm::fixup_zmtarzm_TLS_DTPREL64) {


void zmtarzmInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS) {

void zmtarzmInstPrinter :: printBranchOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS ) {


const MCOperand &MO = MI->getOperand(OpNo);

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


return printOperand ( MI , OpNo , STI , OS ) ;


if ( ! STI . hasFeature ( zmtarzm :: Feature64Bit ) ) {


unsigned zmtarzmInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: ST16B ) {


if ( MI . getOperand ( 1 ) . isFI ( ) ) {


if ( MI . getOperand ( 2 ) . isImm ( ) ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: ST16H ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST16W ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32B ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32H ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32W ) {


if ( MI . getOpcode ( ) == zmtarzm :: FST_S ) {


if ( MI . getOpcode ( ) == zmtarzm :: FST_D ) {


if ( MI . getOpcode ( ) == zmtarzm :: f2FST_S ) {

if (MI.getOpcode() == zmtarzm::f2FST_S) {


if ( MI . getOpcode ( ) == zmtarzm :: f2FST_D ) {

if (MI.getOpcode() == zmtarzm::f2FST_D) {


if ( MI . getOpcode ( ) == zmtarzm :: SPILL_CARRY ) {

if (MI.getOpcode() == zmtarzm::SPILL_CARRY) {


bool zmntarzmInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const {

bool zmntarzmInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const {


if ( convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ) {


ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";


if ( MI . getOpcode ( ) == zmtarzm :: tMOVr ) {


if ( ! zmtarzm :: hGPRRegClass . contains ( MI . getOperand ( 0 ) . getReg ( ) ) ) {


if ( ! zmtarzm :: hGPRRegClass . contains ( MI . getOperand ( 1 ) . getReg ( ) ) ) {


ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";


if ( MI . getOpcode ( ) == zmtarzm :: tPUSH ) {


for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2)) {

for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) {


ErrInfo = "Unsupported register in Thumb1 push/pop";


if ( MI . getOpcode ( ) == zmtarzm :: tPOP ) {


if ( MI . getOpcode ( ) == zmtarzm :: tPOP_RET ) {

if (MI.getOpcode() == zmtarzm::tPOP_RET) {


if ( MI . getOpcode ( ) == zmtarzm :: MVE_VMOV_q_rr ) {

if (MI.getOpcode() == zmtarzm::MVE_VMOV_q_rr) {


assert ( MI . getOperand ( 4 ) . isImm ( ) && MI . getOperand ( 5 ) . isImm ( ) ) ;


if (MI.getOperand(4).getImm() != MI.getOperand(5).getImm() + 2) {

if ( MI . getOperand ( 4 ) . getImm ( ) != MI . getOperand ( 5 ) . getImm ( ) + 2 ) {


ErrInfo = "Incorrect array index for MVE_VMOV_q_rr";


bool zmtarzmDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {

bool zmtarzmDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


imm = CurDAG->getTargetConstant(bit, MVT::i32);

imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


if ( Node -> getOpcode ( ) == ISD :: FrameIndex ) {

if (Node->getOpcode() == ISD::FrameIndex) {


int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


zmtarzmTargetLowering::ConstraintType zmtarzmTargetLowering::getConstraintType(StringRef Constraint) const {

zmtarzmTargetLowering :: ConstraintType zmtarzmTargetLowering :: getConstraintType ( StringRef Constraint ) const {


return TargetLowering :: getConstraintType ( Constraint ) ;


EVT zmtarzmTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const {

EVT zmtarzmTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {


if ( Subtarget . isScalableVector ( ) ) {


return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ;


return VT . changeVectorElementTypeToInteger ( ) ;


bool zmtarzmTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {

bool zmtarzmTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const {


if ( ! isInt < # > ( AM . BaseOffs ) ) {

if ( ! isInt < 16 > ( AM . BaseOffs ) ) {


bool llvm::LowerzmtarzmMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP) {

bool llvm :: LowerzmtarzmMachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) {


if (MO.getType() == MachineOperand::MO_MCSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_MCSymbol ) {


MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);

MCOp = lowerSymbolOperand ( MO , MO . getMCSymbol ( ) , AP ) ;


if (MO.getType() == MachineOperand::MO_ConstantPoolIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_JumpTableIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_Register) {

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ;


if (MO.getType() == MachineOperand::MO_Immediate) {

if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ;


if (MO.getType() == MachineOperand::MO_RegisterMask) {

if ( MO . getType ( ) == MachineOperand :: MO_RegisterMask ) {


if (MO.getType() == MachineOperand::MO_MachineBasicBlock) {

if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);

MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ;


if (MO.getType() == MachineOperand::MO_GlobalAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP);

MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_BlockAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


MCOp = lowerSymbolOperand(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


MCOp = lowerSymbolOperand(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ;


report_fatal_error("LowerzmtarzmMachineInstrToMCInst: unknown operand type");


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for (Target *T : {&getThezmtarzm32Target(), &getThezmtarzm64Target()}) {

for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


const uint32_t *zmtarzmRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const {

const uint32_t * zmtarzmRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {


auto &Subtarget = MF.getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


if ( Subtarget . getTargetABI ( ) == # ) {

if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32S ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32S) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64S ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64S) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32F ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32F) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64F ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64F) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32D ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32D) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64D ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64D) {


llvm_unreachable
(
"Unrecognized ABI"
)
;


zmtarzmSubtarget &zmtarzmSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {

zmtarzmSubtarget & zmtarzmSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) {


CPUName = Is64Bit ? "generic-la64" : "generic-la32";


ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ;


TargetABI = Is64Bit ? zmtarzmABI::ABI_LP64D : zmtarzmABI::ABI_ILP32D;

TargetABI = Is64Bit ? zmtarzmABI :: ABI_LP64D : zmtarzmABI :: ABI_ILP32D ;


void zmtarzmPassConfig :: addPreRegAlloc ( ) {


if (TM->getOptLevel() != CodeGenOpt::None) {

if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) {


addPass ( createzmtarzmAdvSIMDScalar ( ) ) ;


int zmtarzmTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {

if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


void getAnalysisUsage(AnalysisUsage &AU) const {

void getAnalysisUsage ( AnalysisUsage & AU ) const {


AU . addRequired < zmtarzmMetadata > ( ) ;


void zmtarzmAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {

void zmtarzmAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) {


if (MI->getOperand(opNum + 1).isImm() && MI->getOperand(opNum + 1).getImm() == 0) {

if ( MI -> getOperand ( opNum + 1 ) . isImm ( ) && MI -> getOperand ( opNum + 1 ) . getImm ( ) == 0 ) {


void zmtarzmELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {

void zmtarzmELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {


TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


InitializeELF ( TM . Options . UseInitArray ) ;


SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


this->TM = &static_cast<const zmtarzmTargetMachine &>(TM);

this -> TM = & static_cast < const zmtarzmTargetMachine & > ( TM ) ;


bool zmtarzmAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const {

bool zmtarzmAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const {


case zmtarzm :: fixup_zmtarzm_pcrel_imm10_scale2 :


return ! isShiftedInt < 10 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_imm16_scale2 :


return ! isShiftedInt < 16 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_imm26_scale2 :


return ! isShiftedInt < 26 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_uimm7_scale4 :


return ! isShiftedInt < 8 , 2 > ( Offset ) ;


static inline bool IsCondBranch(unsigned BrOpc) {

static inline bool IsCondBranch ( unsigned BrOpc ) {


unsigned zmtarzmMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


assert(MO.isReg() && "Expected a register.");

assert
(
MO
.
isReg
(
)
&&
"Expected a register."
)
;


llvm_unreachable
(
"Invalid mask register."
)
;