Chain = DAG.getNode(zmtarzmISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);

Chain = DAG . getNode ( zmtarzmISD :: WIN__CHKSTK , DL , NodeTys , Chain , Flag ) ;


SDValue NewSP = DAG.getCopyFromReg(Chain, DL, zmtarzm::SP, MVT::i32);

SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , zmtarzm :: SP , MVT :: i32 ) ;


SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, dl, PtrVT), Size);

SDValue NegSize = DAG . getNode ( ISD :: SUB , dl , PtrVT , DAG . getConstant ( 0 , dl , PtrVT ) , Size ) ;


SDValue FPSIdx = getFramePointerFrameIndex(DAG);

SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ;


SDValue Ops[3] = { Chain, NegSize, FPSIdx };

SDValue Ops [ 3 ] = { Chain , NegSize , FPSIdx } ;


SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);

SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other ) ;


return DAG.getNode(zmtarzmISD::DYNALLOC, dl, VTs, Ops);

return DAG . getNode ( zmtarzmISD :: DYNALLOC , dl , VTs , Ops ) ;


SDValue zmtarzmTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


SDValue Offset = Op . getOperand ( 1 ) ;


SDValue Handler = Op . getOperand ( 2 ) ;


auto PtrVT = getPointerTy(DAG.getDataLayout());

auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(zmtarzm::R30, PtrVT), DAG.getIntPtrConstant(4, dl));

SDValue StoreAddr = DAG . getNode ( ISD :: ADD , dl , PtrVT , DAG . getRegister ( zmtarzm :: R30 , PtrVT ) , DAG . getIntPtrConstant ( 4 , dl ) ) ;


Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), false, false, 0);

Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , 0 ) ;


Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


Chain = DAG.getCopyToReg(Chain, dl, AddrReg, Handler);

Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler ) ;


Chain = DAG.getCopyToReg(Chain, dl, ReturnReg, DAG.getIntPtrConstant(0));

Chain = DAG . getCopyToReg ( Chain , dl , ReturnReg , DAG . getIntPtrConstant ( 0 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, MVT::i32), DAG.getRegister(AddrReg, getPointerTy()));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( ) ) ) ;


EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;

EVT Ty = ABI . IsN64 ( ) ? MVT :: i64 : MVT :: i32 ;


unsigned OffsetReg = ABI.IsN64() ? zmtarzm::V1_64 : zmtarzm::V1;

unsigned OffsetReg = ABI . IsN64 ( ) ? zmtarzm :: V1_64 : zmtarzm :: V1 ;


unsigned AddrReg = ABI.IsN64() ? zmtarzm::V0_64 : zmtarzm::V0;

unsigned AddrReg = ABI . IsN64 ( ) ? zmtarzm :: V0_64 : zmtarzm :: V0 ;


Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset, SDValue());

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset , SDValue ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, AddrReg, Handler, Chain.getValue(1));

Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler , Chain . getValue ( 1 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, MVT::i32), DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), Chain.getValue(1));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain);

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, Ty), DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), Chain.getValue(1));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ;


SDValue zmtarzmTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


if ( CallCConv != CallingConv :: Fast ) {


report_fatal_error
(
"Unsupported calling convention"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Lowering formal arguments\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"ISelDAG: Lowering formal arguments\n"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Can't lower variadic arguments\n");


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CC_zmtarzm ) ;


CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ;


Chain = DAG.getNode(zmtarzmISD::ENTRY_FLAG, DL, MVT::Other, {Chain, DAG.getRegister(zmtarzm::a1, MVT::i32), DAG.getTargetConstant(4, DL, MVT::i32)});

Chain = DAG . getNode ( zmtarzmISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( zmtarzm :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ;


assert ( ArgLocs . size ( ) == Ins . size ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ;


FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ;


for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


ArgValue = unpack64(DAG, Chain, VA, DL);

ArgValue = unpack64 ( DAG , Chain , VA , DL ) ;


ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);

ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ;


ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);

ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ;


unsigned VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ;


SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());

SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ;


if ( VA . getValVT ( ) == MVT :: i32 ) {


Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, DAG.getConstant(32, DL, MVT::i32));

Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);

Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ;


assert(VA.needsCustom() == false && "Doesn't support custom argument lowering");


unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;

unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;


unsigned ValSize = VA.getValVT().getSizeInBits() / 8;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ;


int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),  MachinePointerInfo::getFixedStack(MF, FI)));

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);

unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


if (VA.getLocInfo() == CCValAssign::Full) {

if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {


if (VA.getLocInfo() == CCValAssign::BCvt) {

if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {


ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);

ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ;


SDValue Val = DAG.getLoad(VA.getLocInfo() == CCValAssign::AExt ? VA.getValVT() : VA.getLocVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())), MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));

SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


InVals.push_back(DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val));

InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ;


ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs);

ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;


unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &RegInfo = MF.getRegInfo();

MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


VaArgOffset = CCInfo . getNextStackOffset ( ) ;


VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ;


int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


zmtarzmFI -> setVarArgsFrameIndex ( FI ) ;


for (unsigned i = Idx; i < ArgRegs.size(); ++i, VaArgOffset += XLenInBytes) {

for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) {


const Register Reg = RegInfo.createVirtualRegister(RC);

const Register Reg = RegInfo . createVirtualRegister ( RC ) ;


RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ;


FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));

SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI));

SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ;


cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


zmtarzmFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ;


Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);

Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ;


unsigned ArgOffset = ArgLocs.size() * 8;

unsigned ArgOffset = ArgLocs . size ( ) * 8 ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ;


SDValue zmtarzmTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const {


const zmtarzmRegisterInfo &RI = *Subtarget.getRegisterInfo();

const zmtarzmRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


Register FrameReg = RI.getFrameRegister(MF);

Register FrameReg = RI . getFrameRegister ( MF ) ;


SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ;


unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, DAG.getIntPtrConstant(Offset, DL));

SDValue Ptr = DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;


SDValue zmtarzmTargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const {


const zmtarzmRegisterInfo *RegInfo = Subtarget.getRegisterInfo();

const zmtarzmRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));

return DAG . getIntPtrConstant ( 2 * RegInfo -> getSlotSize ( ) , SDLoc ( Op ) ) ;


SDValue zmtarzmTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const {


GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);

GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ;


const GlobalValue * GV = N -> getGlobal ( ) ;


bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);

bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


SDValue Addr = getAddr(N, DAG, IsLocal);

SDValue Addr = getAddr ( N , DAG , IsLocal ) ;


return DAG.getNode(ISD::ADD, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT));

return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ;


MVT XLenVT = getPointerTy ( DAG . getDataLayout ( ) ) ;

MVT XLenVT = getPointerTy(DAG.getDataLayout());


SDValue zmtarzmTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const {


if ( DAG . getTarget ( ) . useEmulatedTLS ( ) ) {


return LowerToTLSEmulatedModel ( Node , DAG ) ;


if (DAG.getMachineFunction().getFunction().getCallingConv() == #) {

if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == # ) {

if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) {

if (DAG.getMachineFunction().getFunction().getCallingConv() == CallingConv::GHC) {


report_fatal_error("In GHC calling convention TLS is not supported");


if ( Model == TLSModel :: GeneralDynamic ) {

if (Model == TLSModel::GeneralDynamic) {


if ( Model == TLSModel :: InitialExec ) {


if ( Model == TLSModel :: LocalDynamic ) {


MFI -> incNumLocalDynamicTLSAccesses ( ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == # ) {

if (DAG.getMachineFunction().getFunction().getCallingConv() == #) {


SDValue zmtarzmTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINIT_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG ) const {


EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


bool isPPC64 = ( PtrVT == MVT :: i64 ) ;


Type *IntPtrTy = DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(*DAG.getContext());

Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ;


Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, isPPC64 ? MVT::i64 : MVT::i32);

Entry . Node = DAG . getConstant ( isPPC64 ? 48 : 40 , isPPC64 ? MVT :: i64 : MVT :: i32 ) ;


Entry.Node = DAG.getConstant(40, MVT::i32);

Entry . Node = DAG . getConstant ( 40 , MVT :: i32 ) ;


TargetLowering::CallLoweringInfo CLI(Chain, Type::getVoidTy(*DAG.getContext()), false, false, false, false, 0, CallingConv::C, false, false, true, DAG.getExternalSymbol("__trampoline_setup", PtrVT), Args, DAG, dl);

TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , CallingConv :: C , false , false , true , DAG . getExternalSymbol ( "__trampoline_setup" , PtrVT ) , Args , DAG , dl ) ;


std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_thread_pointer ) {

if (IntNo == Intrinsic::zmtarzm_thread_pointer) {


return DAG.getNode(zmtarzmISD::EH_SJLJ_SETJMP, DL, MVT::i32, Op.getOperand(1));

return DAG . getNode ( zmtarzmISD :: EH_SJLJ_SETJMP , DL , MVT :: i32 , Op . getOperand ( 1 ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


return DAG.getNode(zmtarzmISD::Wrapper, DL, VT, DAG.getMCSymbol(S, PtrVT));

return DAG . getNode ( zmtarzmISD :: Wrapper , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_tuple ) {

if (IntNo == Intrinsic::zmtarzm_tuple) {


return DAG.getNode(zmtarzmISD::EH_SJLJ_SETJMP, DL, MVT::i32, Op.getOperand(1));

return DAG . getNode ( zmtarzmISD :: EH_SJLJ_SETJMP , DL , MVT :: i32 , Op . getOperand ( 1 ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


return DAG . getNode ( Cmd , DL , MVT :: zmtarzmTuple , Ops ) ;

return DAG.getNode(Cmd, DL, MVT::zmtarzmTuple, Ops);


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


return DAG.getNode(zmtarzmISD::Wrapper, DL, VT, DAG.getMCSymbol(S, PtrVT));

return DAG . getNode ( zmtarzmISD :: Wrapper , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ;


SDValue zmtarzmTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const {


StoreSDNode *StoreNode = cast<StoreSDNode>(Op);

StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ;


assert (StoreNode && "Can only custom lower store nodes");

assert
(
StoreNode
&&
"Can only custom lower store nodes"
)
;


SDValue Value = StoreNode -> getValue ( ) ;


EVT MemVT = StoreNode -> getMemoryVT ( ) ;


assert (VT.isVector() && "Can only custom lower vector store types");


unsigned AS = StoreNode->getAddressSpace();

unsigned AS = StoreNode -> getAddressSpace ( ) ;


unsigned Align = StoreNode->getAlignment();

unsigned Align = StoreNode -> getAlignment ( ) ;


if (Align < MemVT.getStoreSize() && !allowsMisalignedMemoryAccesses(MemVT, AS, Align, StoreNode->getMemOperand()->getFlags(), nullptr)) {

if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) {


return scalarizeVectorStore ( StoreNode , DAG ) ;


if ( StoreNode -> isTruncatingStore ( ) ) {


return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);

return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ;


if (VT == MVT::v2f16 && !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, StoreNode->getAddressSpace(), StoreNode->getAlignment())) {

if ( VT == MVT :: v2f16 && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , StoreNode -> getAddressSpace ( ) , StoreNode -> getAlignment ( ) ) ) {


return expandUnalignedStore ( Store , DAG ) ;


SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, StoreNode->getValue());

SDValue Val = DAG . getNode ( ISD :: BITCAST , dl , MVT :: v2i32 , StoreNode -> getValue ( ) ) ;


SDValue Chain = DAG.getStore(StoreNode->getChain(), dl, Val, StoreNode->getBasePtr(), StoreNode->getPointerInfo(), StoreNode->getAlignment(), StoreNode->getMemOperand()->getFlags(), StoreNode->getAAInfo());

SDValue Chain = DAG . getStore ( StoreNode -> getChain ( ) , dl , Val , StoreNode -> getBasePtr ( ) , StoreNode -> getPointerInfo ( ) , StoreNode -> getAlignment ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , StoreNode -> getAAInfo ( ) ) ;


SDValue zmtarzmTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const {


if ( Op . getOpcode ( ) == ISD :: SHL ) {


if ( Op . getOpcode ( ) == ISD :: SRA ) {


if ( Op . getOpcode ( ) == ISD :: SRL ) {


if ( Op . getOpcode ( ) == ISD :: GlobalAddress ) {

if (Op.getOpcode() == ISD::GlobalAddress) {


return LowerGlobalAddress ( Op , DAG ) ;


if ( Op . getOpcode ( ) == ISD :: BlockAddress ) {

if (Op.getOpcode() == ISD::BlockAddress) {


if ( Op . getOpcode ( ) == ISD :: BR_CC ) {


if ( Op . getOpcode ( ) == ISD :: SELECT_CC ) {


if ( Op . getOpcode ( ) == ISD :: SETCC ) {


if ( Op . getOpcode ( ) == ISD :: VASTART ) {


if ( Op . getOpcode ( ) == ISD :: ExternalSymbol ) {

if (Op.getOpcode() == ISD::ExternalSymbol) {


return LowerExternalSymbol ( Op , DAG ) ;


if ( Op . getOpcode ( ) == ISD :: SIGN_EXTEND ) {

if (Op.getOpcode() == ISD::SIGN_EXTEND) {


if ( Op . getOpcode ( ) == ISD :: RETURNADDR ) {

if (Op.getOpcode() == ISD::RETURNADDR) {


if ( Op . getOpcode ( ) == ISD :: FRAMEADDR ) {


if ( Op . getOpcode ( ) == ISD :: JumpTable ) {


report_fatal_error
(
"unimplemented operand"
)
;


SDValue zmtarzmTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const {


if ( Op . getOpcode ( ) == ISD :: ZERO_EXTEND ) {

if (Op.getOpcode() == ISD::ZERO_EXTEND) {


if ( Op . getOpcode ( ) == ISD :: SUB ) {


if ( Op . getOpcode ( ) == ISD :: SUBC ) {


if ( Op . getOpcode ( ) == ISD :: SRL ) {


if ( Op . getOpcode ( ) == ISD :: SRA ) {


if ( Op . getOpcode ( ) == ISD :: ROTL ) {


if ( Op . getOpcode ( ) == ISD :: ROTR ) {


if ( Op . getOpcode ( ) == ISD :: AND ) {


if ( Op . getOpcode ( ) == ISD :: OR ) {


if ( Op . getOpcode ( ) == ISD :: XOR ) {


if ( Op . getOpcode ( ) == ISD :: SELECT_CC ) {


if ( Op . getOpcode ( ) == ISD :: BR_CC ) {


if ( Op . getOpcode ( ) == ISD :: GlobalAddress ) {


return LowerGlobalAddress ( Op , DAG ) ;


if ( Op . getOpcode ( ) == ISD :: STORE ) {


if ( Op . getOpcode ( ) == ISD :: LOAD ) {


report_fatal_error
(
"unimplemented operand"
)
;


SDValue zmtarzmTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{

SDValue zmtarzmTargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const {


const zmtarzmRegisterInfo &RI = *Subtarget.getRegisterInfo();

const zmtarzmRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MFI . setReturnAddressIsTaken ( true ) ;


if (verifyReturnAddressArgumentIsConstant(Op, DAG)) {

if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) {


unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);

SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ;


SDValue Offset = DAG.getConstant(Off, DL, VT);

SDValue Offset = DAG . getConstant ( Off , DL , VT ) ;


return DAG.getLoad(VT, DL, DAG.getEntryNode(), DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));

Register Reg = MF . addLiveIn ( RI . getRARegister ( ) , getRegClassFor ( XLenVT ) ) ;


return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const {


auto *AFI = DAG.getMachineFunction().getInfo<zmtarzmFunctionInfo>();

auto * AFI = DAG . getMachineFunction ( ) . getInfo < zmtarzmFunctionInfo > ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), getTargetMachine(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( AFI -> getReturnStackOffset ( ) , 4 ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


SmallVector < SDValue , 12 > MemOpChains ;


for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) {


report_fatal_error("Can't return value from vararg function in memory");


unsigned ObjSize = VA.getLocVT().getStoreSize() / 8;

unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) / 8 ;


int FI = MFI->CreateFixedObject(ObjSize, Offset, false);

int FI = MFI -> CreateFixedObject ( ObjSize , Offset , false ) ;


SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);

SDValue FIN = DAG . getFrameIndex ( FI , MVT :: i32 ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN, MachinePointerInfo::getFixedStack(FI), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , 0 ) ) ;


Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size());

Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , & MemOpChains [ 0 ] , MemOpChains . size ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


return DAG.getNode(#, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32), Flag);

return DAG . getNode ( # , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) , Flag ) ;

return DAG . getNode ( zmtarzmISD :: RET , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) , Flag ) ;

return DAG.getNode(zmtarzmISD::RET, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32), Flag);


return DAG.getNode(#, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32));

return DAG . getNode ( # , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) ) ;

return DAG . getNode ( zmtarzmISD :: RET , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) ) ;

return DAG.getNode(zmtarzmISD::RET, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32));


SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const {


auto * AFI = DAG . getMachineFunction ( ) . getInfo < zmtarzmFunctionInfo > ( ) ;


MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( AFI -> getReturnStackOffset ( ) , 4 ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


SmallVector < SDValue , 12 > MemOpChains ;


for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) {


"Can't return value from vararg function in memory"


unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) / 8 ;


int FI = MFI -> CreateFixedObject ( ObjSize , Offset , false ) ;


SDValue FIN = DAG . getFrameIndex ( FI , MVT :: i32 ) ;


MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , 0 ) ) ;


Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , & MemOpChains [ 0 ] , MemOpChains . size ( ) ) ;


Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


return DAG . getNode ( # , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) , Flag ) ;

return DAG . getNode ( zmtarzmISD :: RET_FLAG , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) , Flag ) ;

return DAG.getNode(zmtarzmISD::RET_FLAG, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32), Flag);


return DAG . getNode ( # , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) ) ;

return DAG . getNode ( zmtarzmISD :: RET_FLAG , dl , MVT :: Other , Chain , DAG . getConstant ( 0 , MVT :: i32 ) ) ;

return DAG.getNode(zmtarzmISD::RET_FLAG, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32));


SDValue zmtarzmTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const {


SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));

SDValue Cond = DAG . getNode ( ISD :: SETCC , dl , MVT :: i32 , Op . getOperand ( 2 ) , Op . getOperand ( 3 ) , Op . getOperand ( 4 ) ) ;


return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),Op.getOperand(1));

return DAG . getNode ( ISD :: SELECT , dl , MVT :: i32 , Cond , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) ) ;


SDValue zmtarzmTargetLowering::LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerSMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) const {


lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);

lowerMUL_LOHI32 ( DAG , DL , ISD :: SIGN_EXTEND , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ;


else if (Subtarget.hasMiscellaneousExtensions2()) {

else if ( Subtarget . hasMiscellaneousExtensions2 ( ) ) {


lowerGR128Binary(DAG, DL, VT, zmtarzmISD::SMUL_LOHI, Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);

lowerGR128Binary ( DAG , DL , VT , zmtarzmISD :: SMUL_LOHI , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ;


SDValue C63 = DAG.getConstant(63, DL, MVT::i64);

SDValue C63 = DAG . getConstant ( 63 , DL , MVT :: i64 ) ;


SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);

SDValue LH = DAG . getNode ( ISD :: SRA , DL , VT , LL , C63 ) ;


SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);

SDValue RH = DAG . getNode ( ISD :: SRA , DL , VT , RL , C63 ) ;


lowerGR128Binary(DAG, DL, VT, zmtarzmISD::UMUL_LOHI, LL, RL, Ops[1], Ops[0]);

lowerGR128Binary ( DAG , DL , VT , zmtarzmISD :: UMUL_LOHI , LL , RL , Ops [ 1 ] , Ops [ 0 ] ) ;


SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);

SDValue NegLLTimesRH = DAG . getNode ( ISD :: AND , DL , VT , LL , RH ) ;


SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);

SDValue NegLHTimesRL = DAG . getNode ( ISD :: AND , DL , VT , LH , RL ) ;


SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);

SDValue NegSum = DAG . getNode ( ISD :: ADD , DL , VT , NegLLTimesRH , NegLHTimesRL ) ;


Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);

Ops [ 1 ] = DAG . getNode ( ISD :: SUB , DL , VT , Ops [ 1 ] , NegSum ) ;


return DAG . getMergeValues ( Ops , DL ) ;


SDValue zmtarzmTargetLowering::LowerSTACKSAVE(SDValue Op,  SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MF . getInfo < zmtarzmMachineFunctionInfo > ( ) -> setManipulatesSP ( true ) ;


return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op), zmtarzm::R15D, Op.getValueType());

return DAG . getCopyFromReg ( Op . getOperand ( 0 ) , SDLoc ( Op ) , zmtarzm :: R15D , Op . getValueType ( ) ) ;


SDValue zmtarzmTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const {


StoreSDNode *StoreNode = cast<StoreSDNode>(Op);

StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ;


assert (StoreNode && "Can only custom lower store nodes");

assert
(
StoreNode
&&
"Can only custom lower store nodes"
)
;


SDValue Value = StoreNode -> getValue ( ) ;


EVT MemVT = StoreNode -> getMemoryVT ( ) ;


assert (VT.isVector() && "Can only custom lower vector store types");


unsigned AS = StoreNode->getAddressSpace();

unsigned AS = StoreNode -> getAddressSpace ( ) ;


unsigned Align = StoreNode->getAlignment();

unsigned Align = StoreNode -> getAlignment ( ) ;


if (Align < MemVT.getStoreSize() && !allowsMisalignedMemoryAccesses(MemVT, AS, Align, StoreNode->getMemOperand()->getFlags(), nullptr)) {

if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) {


return scalarizeVectorStore ( StoreNode , DAG ) ;


if ( StoreNode -> isTruncatingStore ( ) ) {


return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);

return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ;


if (VT == MVT::v2f16 && !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, StoreNode->getAddressSpace(), StoreNode->getAlignment())) {

if ( VT == MVT :: v2f16 && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , StoreNode -> getAddressSpace ( ) , StoreNode -> getAlignment ( ) ) ) {


return expandUnalignedStore ( Store , DAG ) ;


SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, StoreNode->getValue());

SDValue Val = DAG . getNode ( ISD :: BITCAST , dl , MVT :: v2i32 , StoreNode -> getValue ( ) ) ;


SDValue Chain = DAG.getStore(StoreNode->getChain(), dl, Val, StoreNode->getBasePtr(), StoreNode->getPointerInfo(), StoreNode->getAlignment(), StoreNode->getMemOperand()->getFlags(), StoreNode->getAAInfo());

SDValue Chain = DAG . getStore ( StoreNode -> getChain ( ) , dl , Val , StoreNode -> getBasePtr ( ) , StoreNode -> getPointerInfo ( ) , StoreNode -> getAlignment ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , StoreNode -> getAAInfo ( ) ) ;


SDValue zmtarzmTargetLowering::LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerUMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) const {


lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);

lowerMUL_LOHI32 ( DAG , DL , ISD :: ZERO_EXTEND , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ;


lowerGR128Binary(DAG, DL, VT, zmtarzmISD::UMUL_LOHI, Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);

lowerGR128Binary ( DAG , DL , VT , zmtarzmISD :: UMUL_LOHI , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ;


return DAG . getMergeValues ( Ops , DL ) ;


SDValue zmtarzmTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const {


SDValue InChain = Node -> getOperand ( 0 ) ;


SDValue VAListPtr = Node->getOperand(1);

SDValue VAListPtr = Node -> getOperand ( 1 ) ;


const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();

const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( 2 ) ) -> getValue ( ) ;


SDValue VAList = DAG.getLoad(getPointerTy(), DL, InChain, VAListPtr, MachinePointerInfo(SV), false, false, 0);

SDValue VAList = DAG . getLoad ( getPointerTy ( ) , DL , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , 0 ) ;


SDValue NextPtr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, DAG.getIntPtrConstant(VT.getSizeInBits(), getPointerTy()));

SDValue NextPtr = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( ) , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) , getPointerTy ( ) ) ) ;


NextPtr = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr, MachinePointerInfo(SV), false, false, 0);

NextPtr = DAG . getStore ( VAList . getValue ( 1 ) , DL , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , 0 ) ;


return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), false, false, 0);

return DAG . getLoad ( VT , DL , InChain , VAList , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue zmtarzmTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *FuncInfo = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * FuncInfo = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), MVT::i32);

SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , MVT :: i32 ) ;


return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), MachinePointerInfo(), false, false, 0);

return DAG . getStore ( Op . getOperand ( 0 ) , dl , FR , Op . getOperand ( 1 ) , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue zmtarzmTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {

SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: ADDE ) {


return performADDECombine ( N , DAG , DCI , Subtarget ) ;

return performADDECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SUBE ) {


return performSUBECombine ( N , DAG , DCI , Subtarget ) ;

return performSUBECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SHL ) {


return performSHLCombine ( N , DAG , DCI , Subtarget ) ;

return performSHLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRA ) {


return performSRACombine ( N , DAG , DCI , Subtarget ) ;

return performSRACombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRL ) {


return performSRLCombine ( N , DAG , DCI , Subtarget ) ;

return performSRLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: VSELECT ) {


return performVSELECTCombine ( N , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: SETCC ) {


return TargetLowering :: PerformDAGCombine ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: ZERO_EXTEND ) {

if (N->getOpcode() == ISD::ZERO_EXTEND) {


if ( N -> getOpcode ( ) == ISD :: SIGN_EXTEND ) {

if (N->getOpcode() == ISD::SIGN_EXTEND) {


if ( N -> getOpcode ( ) == ISD :: SIGN_EXTEND_INREG ) {

if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {


return combineSIGN_EXTEND_INREG ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: MERGE_HIGH ) {

if (N->getOpcode() == ISD::MERGE_HIGH) {


if ( N -> getOpcode ( ) == ISD :: MERGE_LOW ) {


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


if ( N -> getOpcode ( ) == ISD :: STORE ) {


if ( N -> getOpcode ( ) == ISD :: VECTOR_SHUFFLE ) {

if (N->getOpcode() == ISD::VECTOR_SHUFFLE) {


return combineVECTOR_SHUFFLE ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_VECTOR_ELT ) {

if (N->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {


return combineEXTRACT_VECTOR_ELT ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: JOIN_DWORDS ) {

if (N->getOpcode() == ISD::JOIN_DWORDS) {


if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) {


if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) {


if ( N -> getOpcode ( ) == ISD :: BSWAP ) {


if ( N -> getOpcode ( ) == ISD :: BR_CCMASK ) {


if ( N -> getOpcode ( ) == ISD :: SELECT_CCMASK ) {

if (N->getOpcode() == ISD::SELECT_CCMASK) {


return combineSELECT_CCMASK ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: GET_CCMASK ) {

if (N->getOpcode() == ISD::GET_CCMASK) {


if ( N -> getOpcode ( ) == ISD :: SDIV ) {


if ( N -> getOpcode ( ) == ISD :: UDIV ) {


if ( N -> getOpcode ( ) == ISD :: SREM ) {


if ( N -> getOpcode ( ) == ISD :: UREM ) {


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: BITCAST ) {


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_ADD ) {

if (N->getOpcode() == ISD::VECREDUCE_ADD) {


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_SMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_SMIN) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_UMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_UMIN) {


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: CTPOP ) {


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


if ( N -> getOpcode ( ) == ISD :: SMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


if ( N -> getOpcode ( ) == ISD :: SMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


if ( N -> getOpcode ( ) == ISD :: UMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;

assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: ATOMIC_CMP_SWAP ) {

if (N->getOpcode() == ISD::ATOMIC_CMP_SWAP) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


assert
(
SDValue
(
N
,
0
)
.
getValueType
(
)
==
MVT
::
i128
&&
"unexpected load's value type"
)
;

assert(SDValue(N, 0).getValueType() == MVT::i128 && "unexpected load's value type");


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {


if (N->getOperand(0).getValueType() != MVT::i64) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) {


Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


return ReplaceLongIntrinsic(N, Results, DAG);

return ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_SUBVECTOR ) {

if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) {


ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


assert
(
(
VT
==
MVT
::
i8
||
VT
==
MVT
::
i16
)
&&
"custom lowering for unexpected type"
)
;

assert((VT == MVT::i8 || VT == MVT::i16) &&"custom lowering for unexpected type");


ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));

ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if (IntID == Intrinsic::aarch64_sve_clasta_n) {

if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) {


auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));

auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ;


auto V = DAG.getNode(zmtarzmISD::CLASTA_N, DL, MVT::i32, N->getOperand(1), Op2, N->getOperand(3));

auto V = DAG . getNode ( zmtarzmISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ;


Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));

Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ;


if (IntID == Intrinsic::aarch64_sve_lasta) {

if ( IntID == Intrinsic :: aarch64_sve_lasta ) {


auto V = DAG.getNode(zmtarzmISD::LASTA, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


if (IntID == Intrinsic::aarch64_sve_lastb) {

if ( IntID == Intrinsic :: aarch64_sve_lastb ) {


auto V = DAG.getNode(zmtarzmISD::LASTB, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


LoadSDNode * Ld = cast < LoadSDNode > ( N ) ;


if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) {


if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) {


SDValue LoadRes = DAG.getExtLoad(Ld->getExtensionType(), DL, MVT::v2i32, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), Ld->getMemOperand()->getFlags(), Ld->getAAInfo());

SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


SDValue Res = DAG.getNode(ISD::BITCAST, DL, MVT::i64, LoadRes);

SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ;


Results . push_back ( LoadRes . getValue ( 1 ) ) ;


llvm_unreachable("Don't know how to custom expand this");

llvm_unreachable
(
"Don't know how to custom expand this"
)
;


zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {

zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {

for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


addRegisterClass ( MVT :: f32 , & zmtarzm :: sFPR32RegClass ) ;


addRegisterClass ( MVT :: f32 , & zmtarzm :: FPR32RegClass ) ;


addRegisterClass ( MVT :: f64 , & zmtarzm :: sFPR64RegClass ) ;


addRegisterClass ( MVT :: f64 , & zmtarzm :: FPR64RegClass ) ;


auto *RegInfo = Subtarget.getRegisterInfo();

auto * RegInfo = Subtarget . getRegisterInfo ( ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction ( ISD :: ADDCARRY , MVT :: i32 , Legal ) ;

ISD::ADDCARRY zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: SUBCARRY , MVT :: i32 , Legal ) ;

ISD::SUBCARRY zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: BITREVERSE , MVT :: i32 , Legal ) ;

ISD::BITREVERSE zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIVREM , MVT :: i32 , Expand ) ;

ISD::UDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIVREM , MVT :: i32 , Expand ) ;

ISD::SDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Expand ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Expand ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Expand ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction(#,             #,   #);

setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);

setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);

setOperationAction(#,              #,   #);


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

ISD :: DYNAMIC_STACKALLOC MVT :: i32 Expand


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: MULHS , MVT :: i32 , Expand ) ;

ISD::MULHS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i32 , Expand ) ;

ISD::MULHU zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: VAARG , MVT :: Other , Expand ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand


setLoadExtAction ( ISD :: EXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::EXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: EXTLOAD MVT :: i32 MVT :: i1 Promote


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: SEXTLOAD MVT :: i32 MVT :: i1 Promote


setLoadExtAction ( ISD :: ZEXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::ZEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: ZEXTLOAD MVT :: i32 MVT :: i1 Promote


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: ExternalSymbol , MVT :: i32 , Custom ) ;

ISD::ExternalSymbol zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

ISD :: GlobalTLSAddress MVT :: i32 Custom


setOperationAction ( ISD :: BlockAddress , MVT :: i32 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i8 , Expand ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i8 zmsplit  Expand

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Expand);

ISD :: SEXTLOAD MVT :: i32 MVT :: i8 Expand


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i16 , Expand ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i16 zmsplit  Expand

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand);

ISD :: SEXTLOAD MVT :: i32 MVT :: i16 Expand


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ABS , MVT :: i32 , Expand ) ;

ISD::ABS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BITREVERSE , MVT :: i32 , Expand ) ;

ISD::BITREVERSE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ATOMIC_FENCE , MVT :: Other , Expand ) ;

ISD::ATOMIC_FENCE zmsplit MVT::Other zmsplit Expand


ISD :: CondCode FPCCToExtend [ ] = { ISD :: SETONE , ISD :: SETUEQ , ISD :: SETUGT , ISD :: SETUGE , ISD :: SETULT , ISD :: SETULE } ;

ISD::CondCode FPCCToExtend[] = {ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE};


ISD :: NodeType FPOpToExpand [ ] = { ISD :: FSIN , ISD :: FCOS , ISD :: FSINCOS , ISD :: FPOW , ISD :: FREM , ISD :: FCOPYSIGN } ;

ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN};


MVT AllVTy [ ] = { MVT :: f32 , MVT :: f64 } ;


setOperationAction ( ISD :: FREM , VT , Expand ) ;


setOperationAction ( ISD :: SELECT_CC , VT , Expand ) ;

ISD::SELECT_CC zmsplit VT zmsplit Expand


setOperationAction ( ISD :: BR_CC , VT , Expand ) ;


setCondCodeAction ( CC , VT , Expand ) ;


setOperationAction ( Op , VT , Expand ) ;


setOperationAction ( ISD :: ConstantFP , MVT :: f32 , Legal ) ;

ISD::ConstantFP zmsplit MVT::f32 zmsplit Legal


setLoadExtAction ( ISD :: EXTLOAD , MVT :: f64 , MVT :: f32 , Expand ) ;

ISD::EXTLOAD zmsplit  MVT::f64 zmsplit  MVT::f32 zmsplit  Expand

setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);

ISD :: EXTLOAD MVT :: f64 MVT :: f32 Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f32 , Expand ) ;

MVT::f64 zmsplit MVT::f32 zmsplit Expand


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction(#,           #,   #);

setOperationAction(#,           #,   #);


setStackPointerRegisterToSaveRestore ( # ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);

setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {

zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {

for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto * RegInfo = Subtarget . getRegisterInfo ( ) ;

auto *RegInfo = Subtarget.getRegisterInfo();


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setCondCodeAction ( CC , VT , Expand ) ;


MVT GRLenVT = Subtarget . getGRLenVT ( ) ;


addRegisterClass ( GRLenVT , & zmtarzm :: GPRRegClass ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


FunctionPass * llvm :: createzmtarzmLoopMetadataLowering ( ) {


return new zmtarzmLoopMetadataLowering ( ) ;


virtual void getAnalysisUsage(AnalysisUsage &AU) const override {

virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


zmtarzmLoopMetadataLowering() : FunctionPass(ID) {

zmtarzmLoopMetadataLowering ( ) : FunctionPass ( ID ) {


initializezmtarzmLoopMetadataLowering ( * PassRegistry :: getPassRegistry ( ) ) ;


bool zmtarzmLoopMetadataLowering::runOnFunction(Function &F) {

bool zmtarzmLoopMetadataLowering :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


zmtarzmCall(unsigned T) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmCall ( unsigned T ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


static inline bool classof(const zmtarzmCall *C) {

static inline bool classof ( const zmtarzmCall * C ) {


return C->getType() == zmtarzmCall::FunctionType;

return C -> getType ( ) == zmtarzmCall :: FunctionType ;


static inline bool classof(const zmtarzmFunctionCall *) {

static inline bool classof ( const zmtarzmFunctionCall * ) {


static inline bool classof(const zmtarzmCall *) {

static inline bool classof ( const zmtarzmCall * ) {


static inline bool classof(const zmtarzmExternalSymbolCall *) {

static inline bool classof ( const zmtarzmExternalSymbolCall * ) {


return C->getType() == zmtarzmCall::ExternalSymbolType;

return C -> getType ( ) == zmtarzmCall :: ExternalSymbolType ;


zmtarzmExternalSymbolCall(const char *S) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmExternalSymbolCall ( const char * S ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


zmtarzmFunctionCall(const Function *F) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmFunctionCall ( const Function * F ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


explicit zmtarzmFunctionInfo(MachineFunction &MF) : : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

explicit zmtarzmFunctionInfo ( MachineFunction & MF ) : : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


zmtarzmFunctionInfo() : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmFunctionInfo ( ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


const std::vector<zmtarzmCall*> &getCalls() const {

const std :: vector < zmtarzmCall * > & getCalls ( ) const {


void setVarArgsFrameIndex ( int Index ) {


zmtarzmFunctionInfo :: ~ zmtarzmFunctionInfo ( ) {


static MCAsmInfo *createzmtarzmMCAsmInfo(const Target &T, StringRef TT) {

static MCAsmInfo * createzmtarzmMCAsmInfo ( const Target & T , StringRef TT ) {


MCAsmInfo *MAI = new zmtarzmMCAsmInfo(T, TT);

MCAsmInfo * MAI = new zmtarzmMCAsmInfo ( T , TT ) ;


MachineLocation Dst ( MachineLocation :: VirtualFP ) ;


MachineLocation Src ( zmtarzm :: R6 , 0 ) ;


MAI -> addInitialFrameState ( 0 , Dst , Src ) ;


MachineLocation Src ( zmtarzm :: D8 , 0 ) ;


static MCCodeGenInfo *createzmtarzmMCCodeGenInfo(StringRef TT,  Reloc::Model RM, CodeModel::Model CM) {

static MCCodeGenInfo * createzmtarzmMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) {


MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


static MCInstrInfo *createzmtarzmMCInstrInfo() {

static MCInstrInfo * createzmtarzmMCInstrInfo ( ) {


static MCRegisterInfo *createzmtarzmMCRegisterInfo(StringRef TT) {

static MCRegisterInfo * createzmtarzmMCRegisterInfo ( StringRef TT ) {


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: LR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: BLINK ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R15 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PC ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: X0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: SW ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: ADDR0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RA ) ;


static MCSubtargetInfo *createzmtarzmMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {

static MCSubtargetInfo * createzmtarzmMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) {


MCSubtargetInfo *X = new MCSubtargetInfo();

MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;


InitzmtarzmMCSubtargetInfo(X, TT, CPU, FS);

InitzmtarzmMCSubtargetInfo ( X , TT , CPU , FS ) ;


extern "C" void LLVMInitializezmtarzmTargetMC() {

extern "C" void LLVMInitializezmtarzmTargetMC ( ) {


RegisterMCAsmInfoFn X ( ThezmtarzmTarget , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( ThezmtarzmTarget , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( ThezmtarzmTarget , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( ThezmtarzmTarget , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( ThezmtarzmTarget , createzmtarzmMCSubtargetInfo ) ;


void zmtarzmRegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {

void zmtarzmRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


if ( ! TFI -> hasReservedCallFrame ( MF ) ) {


uint64_t Amount = Old->getOperand(0).getImm();

uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ;


unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();

unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ;


Amount = ( Amount + Align - 1 ) / Align * Align ;


if (Old->getOpcode() == zmtarzm::ADJUSTSTACKDOWN) {

if ( Old -> getOpcode ( ) == zmtarzm :: ADJUSTSTACKDOWN ) {


New=BuildMI(MF, Old->getDebugLoc(), TII.get(zmtarzm::LDA), zmtarzm::R30).addImm(-Amount).addReg(zmtarzm::R30);

New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( zmtarzm :: LDA ) , zmtarzm :: R30 ) . addImm ( - Amount ) . addReg ( zmtarzm :: R30 ) ;


assert ( Old -> getOpcode ( ) == zmtarzm :: ADJUSTSTACKUP ) ;


New=BuildMI(MF, Old->getDebugLoc(), TII.get(zmtarzm::LDA), zmtarzm::R30).addImm(Amount).addReg(zmtarzm::R30);

New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( zmtarzm :: LDA ) , zmtarzm :: R30 ) . addImm ( Amount ) . addReg ( zmtarzm :: R30 ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: FRMIDX ) {

if (MI.getOpcode() == zmtarzm::FRMIDX) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


const unsigned * zmtarzmRegisterInfo::getArgRegs(const MachineFunction *MF) {

const unsigned * zmtarzmRegisterInfo :: getArgRegs ( const MachineFunction * MF ) {


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


const zmtarzzmFrameLowering *TFI = getFrameLowering(*MF);

const zmtarzzmFrameLowering * TFI = getFrameLowering ( * MF ) ;


static const MCPhysReg CalleeSavedRegs[] = {zmtarzm::S0, zmtarzm::SRB, zmtarzm::SRO,zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24,zmtarzm::R25, zmtarzm::R26, zmtarzm::R27, zmtarzm::R28,zmtarzm::P1, zmtarzm::P2, zmtarzm::P3, zmtarzm::P4,zmtarzm::P5, zmtarzm::P6, zmtarzm::P7,0

static const MCPhysReg CalleeSavedRegs [ ] = { zmtarzm :: S0 , zmtarzm :: SRB , zmtarzm :: SRO , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , zmtarzm :: R26 , zmtarzm :: R27 , zmtarzm :: R28 , zmtarzm :: P1 , zmtarzm :: P2 , zmtarzm :: P3 , zmtarzm :: P4 , zmtarzm :: P5 , zmtarzm :: P6 , zmtarzm :: P7 , 0


static const MCPhysReg CalleeSavedRegsFP[] = {

static const MCPhysReg CalleeSavedRegsFP [ ] = {


zmtarzm::S0, zmtarzm::SRB, zmtarzm::SRO,zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24,zmtarzm::R25, zmtarzm::R26, zmtarzm::R27, zmtarzm::R28,zmtarzm::RFP,zmtarzm::P1, zmtarzm::P2, zmtarzm::P3, zmtarzm::P4,zmtarzm::P5, zmtarzm::P6, zmtarzm::P7,0

zmtarzm :: S0 , zmtarzm :: SRB , zmtarzm :: SRO , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , zmtarzm :: R26 , zmtarzm :: R27 , zmtarzm :: R28 , zmtarzm :: RFP , zmtarzm :: P1 , zmtarzm :: P2 , zmtarzm :: P3 , zmtarzm :: P4 , zmtarzm :: P5 , zmtarzm :: P6 , zmtarzm :: P7 , 0


unsigned zmtarzmRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

unsigned zmtarzmRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


return TFI -> hasFP ( MF ) ? zmtarzm :: R8 : zmtarzm :: R14 ;

return TFI->hasFP(MF) ? zmtarzm::R8 : zmtarzm::R14;


return TFI -> hasFP ( MF ) ? zmtarzm :: R31 : zmtarzm :: R30 ;

return TFI->hasFP(MF) ? zmtarzm::R31 : zmtarzm::R30;


return TFI -> hasFP ( MF ) ? zmtarzm :: R11 : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::R11 : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: FPW : zmtarzm :: SPW ;

return TFI->hasFP(MF) ? zmtarzm::FPW : zmtarzm::SPW;


return TFI -> hasFP ( MF ) ? zmtarzm :: X2 : zmtarzm :: X1 ;

return TFI->hasFP(MF) ? zmtarzm::X2 : zmtarzm::X1;


unsigned zmtarzmRegisterInfo::getNumArgRegs(const MachineFunction *MF) {

unsigned zmtarzmRegisterInfo :: getNumArgRegs ( const MachineFunction * MF ) {


return array_lengthof ( zmtarzm_ArgRegs ) ;


BitVector zmtarzmRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


bool zmtarzmRegisterInfo::needsFrameMoves(const MachineFunction &MF) {

bool zmtarzmRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) {


return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow();

return MF . getMMI ( ) . hasDebugInfo ( ) || ! MF . getFunction ( ) -> doesNotThrow ( ) ;


void zmtarzmRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const {

void zmtarzmRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(#), TII(tii) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( # ) , TII ( tii ) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: R0 ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::R0), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: PC ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::PC), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: INVALID ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::INVALID), TII(tii) {


bool zmtarzmRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {

bool zmtarzmRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const {


bool zmtarzmRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {

bool zmtarzmRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const {


SDValue zmtarzmSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {

SDValue zmtarzmSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


const zmtarzmSubtarget &STI = DAG.getMachineFunction().getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) ;


return EmitMOPS(zmtarzmISD::MOPS_MEMCOPY, DAG, DL, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo);

return EmitMOPS ( zmtarzmISD :: MOPS_MEMCOPY , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ;


if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {

if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) {


return emitMemMem(DAG, DL, zmtarzmISD::MVC, zmtarzmISD::MVC_LOOP, Chain, Dst, Src, CSize->getZExtValue());

return emitMemMem ( DAG , DL , zmtarzmISD :: MVC , zmtarzmISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


return EmitTargetCodeForMemOp(DAG, dl, Chain, Dst, Src, Size, Alignment, isVolatile, AlwaysInline, MustPreserveCheriCapabilities, DstPtrInfo, SrcPtrInfo, true);

return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ;


if ( ! DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) . hasBulkMemory ( ) ) {


SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);

SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ;


return DAG.getNode(zmtarzmISD::MEMORY_COPY, DL, MVT::Other, {Chain, MemIdx, MemIdx, Dst, Src, DAG.getZExtOrTrunc(Size, DL, MVT::i32)});

return DAG . getNode ( zmtarzmISD :: MEMORY_COPY , DL , MVT :: Other , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) } ) ;


zmtarzmSelectionDAGInfo::zmtarzmSelectionDAGInfo(const zmtarzmTargetMachine &TM) : TargetSelectionDAGInfo(TM), TLI(*TM.getTargetLowering()) {

zmtarzmSelectionDAGInfo :: zmtarzmSelectionDAGInfo ( const zmtarzmTargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) , TLI ( * TM . getTargetLowering ( ) ) {


zmtarzmSelectionDAGInfo :: ~ zmtarzmSelectionDAGInfo ( ) {


FunctionPass * llvm :: createzmtarzmSimpleBranchOptPass ( ) {


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm branch to trap optimization";

return
"zmtarzm branch to trap optimization"
;


bool zmtarzmSimpleBranchOpt::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmSimpleBranchOpt :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


zmtarzmSimpleBranchOpt() : MachineFunctionPass(ID) {

zmtarzmSimpleBranchOpt ( ) : MachineFunctionPass ( ID ) {


FunctionPass * llvm :: createzmtarzmStackAnalysisPrepare ( ) {


return new zmtarzmStackAnalysisPrepare ( ) ;


virtual void getAnalysisUsage(AnalysisUsage &AU) const override {

virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


bool zmtarzmStackAnalysisPrepare::runOnFunction(Function &F) {

bool zmtarzmStackAnalysisPrepare :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


zmtarzmStackAnalysisPrepare() : FunctionPass(ID) {

zmtarzmStackAnalysisPrepare ( ) : FunctionPass ( ID ) {


initializezmtarzmStackAnalysisPrepare ( * PassRegistry :: getPassRegistry ( ) ) ;


FunctionPass * llvm :: createzmtarzmStackUsage ( ) {


virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


return "Calculates zmtarzm stack usage";

return
"Calculates zmtarzm stack usage"
;


bool zmtarzmStackUsage::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmStackUsage :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


zmtarzmStackUsage() : MachineFunctionPass(ID) {

zmtarzmStackUsage ( ) : MachineFunctionPass ( ID ) {


zmtarzmSubtarget::zmtarzmSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : zmtarzmGenSubtargetInfo(TT, CPU, FS) {

zmtarzmSubtarget :: zmtarzmSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : zmtarzmGenSubtargetInfo ( TT , CPU , FS ) {