if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_None ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_None) {


FixupKind = zmtarzm :: fixup_zmtarzm_REL26 ;


Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(FixupKind), MI.getLoc()));

Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


if (cast<MCSymbolRefExpr>(Expr)->getKind() == #) {

if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == # ) {

if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_ABS_HI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_ABS_HI) {


FixupKind = zmtarzm :: fixup_zmtarzm_HI16_INSN ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_ABS_LO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_ABS_LO) {


FixupKind = zmtarzm :: fixup_zmtarzm_LO16_INSN ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PLT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_PLT) {


FixupKind = zmtarzm :: fixup_zmtarzm_PLT26 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTPCHI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTPCHI) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTPC_HI16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTPCLO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTPCLO) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTPC_LO16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTOFFHI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTOFFHI) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTOFF_HI16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTOFFLO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTOFFLO) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTOFF_LO16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOT) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOT16 ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


llvm_unreachable
(
"Unknown fixup kind!"
)
;


unsigned zmtarzmMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();

Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ;


assert (Kind == MCExpr::SymbolRef && "unknown MCExpr kind");

assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == # ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == #) {


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_LO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_LO) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_lo16_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_HI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_HI) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_hi16_pcrel ;


unsigned zmtarzmMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


if ( MI . getOpcode ( ) == zmtarzm :: BAL ) {


Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(#), MI.getLoc()));

Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( # ) , MI . getLoc ( ) ) ) ;

Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( zmtarzm :: fixup_zmtarzm_BAL32 ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(zmtarzm::fixup_zmtarzm_BAL32), MI.getLoc()));


if ( MI . getOpcode ( ) == zmtarzm :: BAL_short ) {

if (MI.getOpcode() == zmtarzm::BAL_short) {


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( zmtarzm :: fixup_zmtarzm_BAL16 ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(zmtarzm::fixup_zmtarzm_BAL16), MI.getLoc()));


llvm_unreachable
(
"Unhandled expression!"
)
;


if ( MI . getOpcode ( ) == zmtarzm :: JAL ) {


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( zmtarzm :: fixup_zmtarzm_PCRel_4 ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(zmtarzm::fixup_zmtarzm_PCRel_4), MI.getLoc()));


if ( MI . getOpcode ( ) == zmtarzm :: LD_imm64 ) {

if (MI.getOpcode() == zmtarzm::LD_imm64) {


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( zmtarzm :: fixup_zmtarzm_SecRel_8 ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(zmtarzm::fixup_zmtarzm_SecRel_8), MI.getLoc()));


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( # ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(#), MI.getLoc()));


unsigned zmtarzmMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


assert(MO.isReg() && "Expected a register.");

assert
(
MO
.
isReg
(
)
&&
"Expected a register."
)
;


if ( MO . getReg ( ) == zmtarzm :: R3 ) {


if ( MO . getReg ( ) == zmtarzm :: R4 ) {


if ( MO . getReg ( ) == zmtarzm :: R5 ) {


if ( MO . getReg ( ) == zmtarzm :: R124 ) {


if ( MO . getReg ( ) == zmtarzm :: R127 ) {


llvm_unreachable
(
"Invalid mask register."
)
;


if ( MO . getReg ( ) == zmtarzm :: R0 ) {


if ( MO . getReg ( ) == zmtarzm :: D1 ) {


if ( MO . getReg ( ) == zmtarzm :: D2 ) {


if ( MO . getReg ( ) == zmtarzm :: R19 ) {


if ( MO . getReg ( ) == zmtarzm :: R20 ) {


if ( MO . getReg ( ) == zmtarzm :: r0 ) {


if ( MO . getReg ( ) == zmtarzm :: r1 ) {


if ( MO . getReg ( ) == zmtarzm :: r2 ) {


if ( MO . getReg ( ) == zmtarzm :: r8 ) {


if ( MO . getReg ( ) == zmtarzm :: c30 ) {


if ( MO . getReg ( ) == zmtarzm :: c31 ) {


unsigned zmtarzmMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


assert
(
MO
.
isReg
(
)
&&
"Expected a register."
)
;


if ( MO . getReg ( ) == zmtarzm :: a2 ) {


if ( MO . getReg ( ) == zmtarzm :: s0 ) {


if ( MO . getReg ( ) == zmtarzm :: s1 ) {


if ( MO . getReg ( ) == zmtarzm :: s2 ) {


if ( MO . getReg ( ) == zmtarzm :: ra ) {


llvm_unreachable
(
"Invalid mask register."
)
;


zmtarzmMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) : Ctx(ctx), MCII(MCII) {

zmtarzmMCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {


static bool classof ( const MCExpr * E ) {


return E -> getKind ( ) == MCExpr :: Target ;


static bool classof(const zmtarzmMCExpr *) {

static bool classof ( const zmtarzmMCExpr * ) {


const zmtarzmMCExpr *zmtarzmMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) {

const zmtarzmMCExpr * zmtarzmMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) {


return new (Ctx) zmtarzmMCExpr(Expr, Kind);

return new ( Ctx ) zmtarzmMCExpr ( Expr , Kind ) ;


bool zmtarzmMCExpr::evaluateAsConstant(int64_t &Res) const {

bool zmtarzmMCExpr :: evaluateAsConstant ( int64_t & Res ) const {


if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr)) {

if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) {


Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;


int64_t zmtarzmMCExpr::evaluateAsInt64(int64_t Value) const {

int64_t zmtarzmMCExpr :: evaluateAsInt64 ( int64_t Value ) const {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR16_LO ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR16_LO) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR24_SEGMENT_LO ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR24_SEGMENT_LO) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR16_HI ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR16_HI) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR24_SEGMENT_HI ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR24_SEGMENT_HI) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR24_BANK ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR24_BANK) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ADDR24_SEGMENT ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ADDR24_SEGMENT) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_IMM16 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_IMM16) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_LO8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_LO8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HI8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HI8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HH8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HH8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HHI8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HHI8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PM_LO8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PM_LO8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PM_HI8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PM_HI8) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PM_HH8 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PM_HH8) {


bool zmtarzmMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const {

bool zmtarzmMCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const {


if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup)){

if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) {


Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());

Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GOT) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PCREL ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_PCREL) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_ADDR ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_ADDR) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTPC ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTPC) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTOFF ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTOFF) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_TPOFF ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_TPOFF) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_TLSGD ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_TLSGD) {


MCFragment *findAssociatedFragment() const override {

MCFragment * findAssociatedFragment ( ) const override {


return getSubExpr ( ) -> findAssociatedFragment ( ) ;


static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {

static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) {


if (Expr->getKind() == MCExpr::Target) {

if ( Expr -> getKind ( ) == MCExpr :: Target ) {


llvm_unreachable("Can't handle nested target expression");

llvm_unreachable
(
"Can't handle nested target expression"
)
;


fixELFSymbolsInTLSFixupsImpl ( cast < MCExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


if (Expr->getKind() == MCExpr::Constant) {

if ( Expr -> getKind ( ) == MCExpr :: Constant ) {


if (Expr->getKind() == MCExpr::Binary) {

if ( Expr -> getKind ( ) == MCExpr :: Binary ) {


fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ;


if (Expr->getKind() == MCExpr::SymbolRef) {

if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) {


const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ;


if ( Expr -> getKind ( ) == MCExpr :: Unary ) {


fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


void zmtarzmMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {

void zmtarzmMCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const {


fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ;


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_DTPREL ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_DTPREL) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTTPREL ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTTPREL) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_TPREL ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_TPREL) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_TLSDESC ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_TLSDESC) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GD_GOT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GD_GOT) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_LD_GOT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_LD_GOT) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GD_PLT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_GD_PLT) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_IE_GOT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_IE_GOT) {


if ( getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_LD_PLT ) {

if(getKind() == zmtarzmMCExpr::VK_zmtarzm_LD_PLT) {


const MCFixup *zmtarzmMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const {

const MCFixup * zmtarzmMCExpr :: getPCRelHiFixup ( const MCFragment * * DFOut ) const {


if ( ( unsigned ) F . getKind ( ) == # ) {

if ( ( unsigned ) F . getKind ( ) == FK_Data_2 ) {

if ((unsigned)F.getKind() == FK_Data_2) {


if ( ( unsigned ) F . getKind ( ) == FK_Data_4 ) {

if ((unsigned)F.getKind() == FK_Data_4) {


if ( ( unsigned ) F . getKind ( ) == FK_Data_8 ) {

if ((unsigned)F.getKind() == FK_Data_8) {


if ( ( unsigned ) F . getKind ( ) == zmtarzm :: fixup_zmtarzm_PC16DBL ) {

if ((unsigned)F.getKind() == zmtarzm::fixup_zmtarzm_PC16DBL) {


if ( ( unsigned ) F . getKind ( ) == zmtarzm :: fixup_zmtarzm_PC32DBL ) {

if ((unsigned)F.getKind() == zmtarzm::fixup_zmtarzm_PC32DBL) {


if ( ( unsigned ) F . getKind ( ) == zmtarzm :: fixup_zmtarzm_PLT16DBL ) {

if ((unsigned)F.getKind() == zmtarzm::fixup_zmtarzm_PLT16DBL) {


if ( ( unsigned ) F . getKind ( ) == zmtarzm :: fixup_zmtarzm_PLT32DBL ) {

if ((unsigned)F.getKind() == zmtarzm::fixup_zmtarzm_PLT32DBL) {


llvm_unreachable
(
"Unsupported PC-relative address"
)
;


zmtarzmMCExpr::VariantKind zmtarzmMCExpr::getVariantKindForName(StringRef name) {

zmtarzmMCExpr :: VariantKind zmtarzmMCExpr :: getVariantKindForName ( StringRef name ) {


return zmtarzm :: ExprType :: ExceptRef ;


StringRef zmtarzmMCExpr::getVariantKindName(VariantKind Kind) {

StringRef zmtarzmMCExpr :: getVariantKindName ( VariantKind Kind ) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_LO ) {

if (Kind == zmtarzmMCExpr::VK_zmtarzm_LO) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HI ) {

if (Kind == zmtarzmMCExpr::VK_zmtarzm_HI) {


llvm_unreachable("Invalid ELF symbol kind");

llvm_unreachable
(
"Invalid ELF symbol kind"
)
;


explicit zmtarzmMCExpr(const MCExpr *Expr, VariantKind Kind) : Expr(Expr), Kind(Kind) {

explicit zmtarzmMCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {


void zmtarzmMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {

void zmtarzmMCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ABS_HI ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ABS_HI) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_ABS_LO ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_ABS_LO) {


if(Kind == zmtarzmMCExpr::VK_zmtarzm_LO) {


if(Kind == zmtarzmMCExpr::VK_zmtarzm_HI) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HH ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HH) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_LM ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_LM) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_TLS_IE_ADD ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_TLS_IE_ADD) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_TLS_IE_LD ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_TLS_IE_LD) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_R_DISP32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_R_DISP32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_TLS_GD_CALL ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_TLS_GD_CALL) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_TLS_LE_LOX10 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_TLS_LE_LOX10) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_HI32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_HI32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_LO32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_LO32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PC_HI32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PC_HI32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PC_LO32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PC_LO32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_GOT_HI32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_GOT_HI32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_GOT_LO32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_GOT_LO32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PLT_HI32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PLT_HI32) {


if ( Kind == zmtarzmMCExpr :: VK_zmtarzm_PLT_LO32 ) {

if(Kind == zmtarzmMCExpr::VK_zmtarzm_PLT_LO32) {


llvm_unreachable
(
"Invalid ELF symbol kind"
)
;

llvm_unreachable("Invalid ELF symbol kind");


void zmtarzmMCExpr::visitUsedExpr(MCStreamer &Streamer) const {

void zmtarzmMCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const {


Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


void llvm::LowerMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, const AsmPrinter &AP) {

void llvm :: LowerMachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , const AsmPrinter & AP ) {


OutMI . setOpcode ( MI -> getOpcode ( ) ) ;


for (const MachineOperand &MO : MI->operands()) {

for ( const MachineOperand & MO : MI -> operands ( ) ) {


OutMI . addOperand ( LowerOperand ( MI , MO , AP ) ) ;


LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ;


if (LowerMachineOperandToMCOperand(MO, MCOp, AP)) {

if ( LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ) {


bool llvm::LowerzmtarzmMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP) {

bool llvm :: LowerzmtarzmMachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) {


if (MO.getType() == MachineOperand::MO_MCSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_MCSymbol ) {


MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);

MCOp = lowerSymbolOperand ( MO , MO . getMCSymbol ( ) , AP ) ;


if (MO.getType() == MachineOperand::MO_ConstantPoolIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_JumpTableIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_Register) {

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ;


if (MO.getType() == MachineOperand::MO_Immediate) {

if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ;


if (MO.getType() == MachineOperand::MO_RegisterMask) {

if ( MO . getType ( ) == MachineOperand :: MO_RegisterMask ) {


if (MO.getType() == MachineOperand::MO_MachineBasicBlock) {

if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);

MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ;


if (MO.getType() == MachineOperand::MO_GlobalAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP);

MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_BlockAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


MCOp = lowerSymbolOperand(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ;


if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


MCOp = lowerSymbolOperand(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);

MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ;


report_fatal_error("LowerzmtarzmMachineInstrToMCInst: unknown operand type");


static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP) {

static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) {


Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_zmtarzm_None, Ctx);

Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_zmtarzm_None , Ctx ) ;


Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);

Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOT ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOT) {


Expr = zmtarzmMCExpr::create(Expr, #, Ctx);

Expr = zmtarzmMCExpr :: create ( Expr , # , Ctx ) ;

Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOT , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOT, Ctx);


return MCOperand :: createExpr ( Expr ) ;


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOTOFF ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOTOFF) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOT_LO12 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOT_LO12, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_LO12 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_LO12) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_LO12 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_LO12, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_DTPREL_G1 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_DTPREL_G1) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_DTPREL_G1 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_DTPREL_G1, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_DTPREL_G0_NC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_DTPREL_G0_NC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_DTPREL_G0_NC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_DTPREL_G0_NC, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOTTPREL ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOTTPREL) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOTTPREL , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOTTPREL, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOTTPREL_LO12 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOTTPREL_LO12) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOTTPREL_LO12 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOTTPREL_LO12, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_TLSDESC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_TLSDESC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_TLSDESC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_TLSDESC, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_TLSDESC_LO12 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_TLSDESC_LO12) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_TLSDESC_LO12 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_TLSDESC_LO12, Ctx);


return MCOperand :: createExpr ( Expr ) ;


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_TPREL_G1 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_TPREL_G1) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_TPREL_G1 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_TPREL_G1, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_TPREL_G0_NC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_TPREL_G0_NC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_TPREL_G0_NC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_TPREL_G0_NC, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ABS_G3 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ABS_G3) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ABS_G3 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ABS_G3, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ABS_G2_NC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ABS_G2_NC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ABS_G2_NC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ABS_G2_NC, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ABS_G1_NC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ABS_G1_NC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ABS_G1_NC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ABS_G1_NC, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ABS_G0_NC ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ABS_G0_NC) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ABS_G0_NC , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ABS_G0_NC, Ctx);


if (MO.getTargetFlags() == zmtarzmII::MO_None) {

if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_None ) {


llvm_unreachable("Unknown target flag on GV operand");

llvm_unreachable
(
"Unknown target flag on GV operand"
)
;


static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) {

static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP) {


Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_zmtarzm_None , Ctx ) ;

Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_zmtarzm_None, Ctx);


Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;

Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOT32 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOT32) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOT32 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOT32, Ctx);


return MCOperand :: createExpr ( Expr ) ;


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_GOTOFF ) {

if (MO.getTargetFlags() == zmtarzmII::MO_GOTOFF) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_GOTOFF , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_GOTOFF, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ADDR32 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ADDR32) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ADDR , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ADDR, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_PLT32 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_PLT32) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_PLT , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_PLT, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ADDR_HI16 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ADDR_HI16) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ADDR_HI16 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ADDR_HI16, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_ADDR_LO16 ) {

if (MO.getTargetFlags() == zmtarzmII::MO_ADDR_LO16) {


Expr = zmtarzmMCExpr :: create ( Expr , zmtarzmMCExpr :: VK_ADDR_LO16 , Ctx ) ;

Expr = zmtarzmMCExpr::create(Expr, zmtarzmMCExpr::VK_ADDR_LO16, Ctx);


if ( MO . getTargetFlags ( ) == zmtarzmII :: MO_None ) {

if (MO.getTargetFlags() == zmtarzmII::MO_None) {


llvm_unreachable
(
"Unknown target flag on GV operand"
)
;

llvm_unreachable("Unknown target flag on GV operand");


static MCTargetStreamer *createzmtarzmAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) {

static MCTargetStreamer * createzmtarzmAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) {


return new zmtarzmTargetAsmStreamer(S, OS);

return new zmtarzmTargetAsmStreamer ( S , OS ) ;


static MCInstrAnalysis *createzmtarzmInstrAnalysis(const MCInstrInfo *Info) {

static MCInstrAnalysis * createzmtarzmInstrAnalysis ( const MCInstrInfo * Info ) {


return new zmtarzmMCInstrAnalysis ( Info ) ;


static MCAsmInfo *createzmtarzmMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) {

static MCAsmInfo * createzmtarzmMCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) {


Reg = MRI . getDwarfRegNum ( # , true ) ;

Reg = MRI . getDwarfRegNum ( zmtarzm :: XSP , true ) ;

Reg = MRI.getDwarfRegNum(zmtarzm::XSP, true);


MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);

MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , 0 ) ;


Reg = MRI . getDwarfRegNum ( # , true ) ;


Reg = MRI . getDwarfRegNum ( zmtarzm :: SP , true ) ;

Reg = MRI.getDwarfRegNum(zmtarzm::SP, true);


Reg = MRI . getDwarfRegNum ( zmtarzm :: SP_REG , true ) ;

Reg = MRI.getDwarfRegNum(zmtarzm::SP_REG, true);


Reg = MRI . getDwarfRegNum ( zmtarzm :: R1 , true ) ;

Reg = MRI.getDwarfRegNum(zmtarzm::R1, true);


Reg = MRI . getDwarfRegNum ( zmtarzm :: RSP , true ) ;

Reg = MRI.getDwarfRegNum(zmtarzm::RSP, true);


static MCInstPrinter *createzmtarzmMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) {

static MCInstPrinter * createzmtarzmMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


return new zmtarzmInstPrinter(MAI, MII, MRI);

return new zmtarzmInstPrinter ( MAI , MII , MRI ) ;


static MCInstrInfo *createzmtarzmMCInstrInfo() {

static MCInstrInfo * createzmtarzmMCInstrInfo ( ) {


static MCRegisterInfo *createzmtarzmMCRegisterInfo(const Triple &TT) {

static MCRegisterInfo * createzmtarzmMCRegisterInfo ( const Triple & TT ) {


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: BLINK ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: LR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RRA ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R15 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RA_REG ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R14D ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R1 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PCW ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: dpI32_0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: IP ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PC ) ;


static MCSubtargetInfo *createzmtarzmMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {

static MCSubtargetInfo * createzmtarzmMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {


return createzmtarzmMCSubtargetInfoImpl(TT, CPUName, CPUName, FS);

return createzmtarzmMCSubtargetInfoImpl ( TT , CPUName , CPUName , FS ) ;


static MCTargetStreamer *createzmtarzmNullTargetStreamer(MCStreamer &S) {

static MCTargetStreamer * createzmtarzmNullTargetStreamer ( MCStreamer & S ) {


return new zmtarzmTargetStreamer ( S ) ;


static MCTargetStreamer *createzmtarzmObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {

static MCTargetStreamer * createzmtarzmObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {


const Triple &TT = STI.getTargetTriple();

const Triple & TT = STI . getTargetTriple ( ) ;


return new zmtarzmTargetELFStreamer(S, STI);

return new zmtarzmTargetELFStreamer ( S , STI ) ;


bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const {

bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const {


if ( Inst . getOpcode ( ) == zmtarzm :: BCCi64 ) {

if(Inst.getOpcode() == zmtarzm::BCCi64) {


Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) + 8 ;

Target = Addr + Inst.getOperand(0).getImm() + 8;


if ( Inst . getOpcode ( ) == zmtarzm :: BCCZi64 ) {

if(Inst.getOpcode() == zmtarzm::BCCZi64) {


if ( Inst . getOpcode ( ) == zmtarzm :: t2Bcc ) {

if(Inst.getOpcode() == zmtarzm::t2Bcc) {


if ( Inst . getOpcode ( ) == zmtarzm :: Bcc ) {


if ( Inst . getOpcode ( ) == zmtarzm :: B ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BL ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BL_Pred ) {

if(Inst.getOpcode() == zmtarzm::BL_Pred) {


if ( Inst . getOpcode ( ) == zmtarzm :: BLXi ) {


if ( Inst . getOpcode ( ) == zmtarzm :: J ) {


Target = Addr & ~ uint64_t ( 0xfffffff ) + Inst . getOperand ( 0 ) . getImm ( ) ;

Target = Addr & ~uint64_t(0xfffffff) + Inst.getOperand(0).getImm();


if ( Inst . getOpcode ( ) == zmtarzm :: JAL ) {


if ( Inst . getOpcode ( ) == zmtarzm :: JALX ) {


if ( Inst . getOpcode ( ) == zmtarzm :: JALS ) {


Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ;

Target = Addr + Inst.getOperand(1).getImm();


if ( Inst . getOpcode ( ) == zmtarzm :: BEQ ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BNE ) {


bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const {


Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) * Size ;

Target = Addr + Inst.getOperand(2).getImm() * Size;


if ( Inst . getOpcode ( ) == zmtarzm :: BA ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BCC ) {


Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) * Size ;

Target = Addr + Inst.getOperand(1).getImm() * Size;


if ( Inst . getOpcode ( ) == zmtarzm :: BCCLR ) {

if(Inst.getOpcode() == zmtarzm::BCCLR) {


if ( Inst . getOpcode ( ) == zmtarzm :: BC ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BCLR ) {


Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) * Size ;

Target = Addr + Inst.getOperand(0).getImm() * Size;


if ( Inst . getOpcode ( ) == zmtarzm :: BDZ8 ) {


if ( Inst . getOpcode ( ) == zmtarzm :: BDNZ8 ) {

if(Inst.getOpcode() == zmtarzm::BDNZ8) {


if ( Inst . getOpcode ( ) == zmtarzm :: BCCL ) {


explicit zmtarzmMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {

explicit zmtarzmMCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for (Target *T : {&getThezmtarzm32Target(), &getThezmtarzm64Target()}) {

for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


FunctionPass * llvm :: createzmtarzmMergeBaseOffsetOptPass ( ) {


return new zmtarzmMergeBaseOffsetOpt ( ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


MachineFunctionProperties getRequiredProperties() const override {

MachineFunctionProperties getRequiredProperties ( ) const override {


return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: AllVRegsAllocated ) ;


return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ;


zmtarzmMergeBaseOffsetOpt() : MachineFunctionPass(ID) {

zmtarzmMergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) {


bool zmtarzmMergeBaseOffset::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmMergeBaseOffset :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( * F . getFunction ( ) ) ) {


const Subtarget &ST = MF.getSubtarget<Subtarget>();

const Subtarget & ST = MF . getSubtarget < Subtarget > ( ) ;


ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


FunctionPass * llvm :: createzmtarzmFixupHwLoops ( ) {


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


StringRef getPassName ( ) const override {


MachineFunctionProperties getRequiredProperties ( ) const override {


return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


zmtarzmFixupHwLoops() : MachineFunctionPass(ID) {

zmtarzmFixupHwLoops ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmFixupHwLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


bool zmtarzmFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) {


MLI = & getAnalysis < MachineLoopInfo > ( ) ;


MDT = & getAnalysis < MachineDominatorTree > ( ) ;


TII = MF . getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


Changed = Changed | convertToHardwareLoop(L, L0Used, L1Used);

Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ;


bool zmtarzmHardwareLoops::checkForImmediate(const MachineOperand &MO, int64_t &Val) const {

bool zmtarzmHardwareLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const {


MachineInstr * DI = MRI -> getVRegDef ( R ) ;


if (!checkForImmediate(DI->getOperand(1), TV)) {

if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) {


if (MO.getSubReg() == zmtarzm::subreg_loreg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if (MO.getSubReg() == zmtarzm::subreg_hireg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


if (DOpc == zmtarzm::CONST32_Int_Real) {

if ( DOpc == zmtarzm :: CONST32_Int_Real ) {


if (DOpc == zmtarzm::CONST64_Int_Real) {

if ( DOpc == zmtarzm :: CONST64_Int_Real ) {


if ( DOpc == zmtarzm :: A2_combineii ) {


const MachineOperand &S1 = DI->getOperand(1);

const MachineOperand & S1 = DI -> getOperand ( 1 ) ;


const MachineOperand &S2 = DI->getOperand(2);

const MachineOperand & S2 = DI -> getOperand ( 2 ) ;


if ( ! checkForImmediate ( S1 , V1 ) ) {


if ( ! checkForImmediate ( S2 , V2 ) ) {


if ( DOpc == zmtarzm :: A4_combineir ) {


if ( DOpc == zmtarzm :: A4_combineii ) {


if ( DOpc == zmtarzm :: A4_combineri ) {


if (DOpc == TargetOpcode::REG_SEQUENCE) {

if ( DOpc == TargetOpcode :: REG_SEQUENCE ) {


const MachineOperand &S3 = DI->getOperand(3);

const MachineOperand & S3 = DI -> getOperand ( 3 ) ;


if ( ! checkForImmediate ( S3 , V3 ) ) {


unsigned Sub2 = DI->getOperand(2).getImm();

unsigned Sub2 = DI -> getOperand ( 2 ) . getImm ( ) ;


unsigned Sub4 = DI->getOperand(4).getImm();

unsigned Sub4 = DI -> getOperand ( 4 ) . getImm ( ) ;


if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


llvm_unreachable("Unexpected form of REG_SEQUENCE");

llvm_unreachable
(
"Unexpected form of REG_SEQUENCE"
)
;


bool zmtarzmHardwareLoops::containsInvalidInstruction(MachineLoop *L) const {

bool zmtarzmHardwareLoops :: containsInvalidInstruction ( MachineLoop * L ) const {


LLVM_DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nhw_loop head, BB#"
<<
Blocks
[
0
]
->
getNumber
(
)
;
)
;


for (MachineBasicBlock *MBB : L->getBlocks()) {

for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) {


LLVM_DEBUG(dbgs() << "\nCannot convert to hwloop due to:"; MI.dump(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nCannot convert to hwloop due to:"
;
MI
.
dump
(
)
;
)
;


bool zmtarzmHardwareLoops::convertToHardwareLoop(MachineLoop *L, bool &RecL0used, bool &RecL1used) {

bool zmtarzmHardwareLoops :: convertToHardwareLoop ( MachineLoop * L , bool & RecL0used , bool & RecL1used ) {


assert(L->getHeader() && "Loop without a header?");

assert
(
L
->
getHeader
(
)
&&
"Loop without a header?"
)
;


for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {

for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) {


Changed = Changed | convertToHardwareLoop(*I, RecL0used, RecL1used);

Changed = Changed | convertToHardwareLoop ( * I , RecL0used , RecL1used ) ;


if (containsInvalidInstruction(L, IsInnerHWLoop)) {

if ( containsInvalidInstruction ( L , IsInnerHWLoop ) ) {


MachineBasicBlock *LastMBB = getExitingBlock(L);

MachineBasicBlock * LastMBB = getExitingBlock ( L ) ;


MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();

MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ;


MachineBasicBlock *Preheader = L->getLoopPreheader();

MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ;


Preheader = createPreheaderForLoop ( L ) ;


MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();

MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ;


SmallVector < MachineInstr * , 2 > OldInsts ;


CountValue *TripCount = getLoopTripCount(L, OldInsts);

CountValue * TripCount = getLoopTripCount ( L , OldInsts ) ;


MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());

MachineInstr * TCDef = MRI -> getVRegDef ( TripCount -> getReg ( ) ) ;


MachineBasicBlock *BBDef = TCDef->getParent();

MachineBasicBlock * BBDef = TCDef -> getParent ( ) ;


if (!MDT->dominates(BBDef, Preheader)) {

if ( ! MDT -> dominates ( BBDef , Preheader ) ) {


MachineBasicBlock *TopBlock = L->getTopBlock();

MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ;


MachineBasicBlock *ExitingBlock = getExitingBlock(L);

MachineBasicBlock * ExitingBlock = getExitingBlock ( L ) ;


if (ExitingBlock != L->getLoopLatch()) {

if ( ExitingBlock != L -> getLoopLatch ( ) ) {


SmallVector < MachineOperand , 2 > Cond ;


if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) {

if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) {


if (ExitingBlock == L->getLoopLatch()) {

if ( ExitingBlock == L -> getLoopLatch ( ) ) {


DEBUG(dbgs() << "Change to hardware loop at "; L->dump());

DEBUG
(
dbgs
(
)
<<
"Change to hardware loop at "
;
L
->
dump
(
)
)
;


if ( InsertPos != Preheader -> end ( ) ) {


unsigned CountReg = MRI->createVirtualRegister(&zmtarzm::IntRegsRegClass);

unsigned CountReg = MRI -> createVirtualRegister ( & zmtarzm :: IntRegsRegClass ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg(), 0, TripCount->getSubReg());

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , 0 , TripCount -> getSubReg ( ) ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart).addReg(CountReg);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ;


assert(TripCount->isImm() && "Expecting immediate value for trip count");


int64_t CountImm = TripCount -> getImm ( ) ;


if (!TII->isValidOffset(LOOP_i, CountImm)) {

if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(zmtarzm::A2_tfrsi), CountReg).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( zmtarzm :: A2_tfrsi ) , CountReg ) . addImm ( CountImm ) ;


if (TII->isValidOffset(LOOP_i, CountImm)) {

if ( TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i)).addMBB(LoopStart).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ;


BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ;


DebugLoc LastIDL = LastI->getDebugLoc();

DebugLoc LastIDL = LastI -> getDebugLoc ( ) ;


BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);

BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpt ) {


MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();

MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ;


if ( ! L -> contains ( BranchTarget ) ) {


SmallVector < MachineOperand , 0 > Cond ;


TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);

TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpf ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpt ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpf ) {


for (unsigned i = 0; i < OldInsts.size(); ++i) {

for ( unsigned i = 0 ; i < OldInsts . size ( ) ; ++ i ) {


explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {

explicit CountValue ( CountValueType t , unsigned v , unsigned u = 0 ) {


FunctionPass * llvm :: createzmtarzmHardwareLoops ( ) {


bool zmtarzmHardwareLoops::findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp) const {

bool zmtarzmHardwareLoops :: findInductionRegister ( MachineLoop * L , unsigned & Reg , int64_t & IVBump , MachineInstr * & IVOp ) const {


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineBasicBlock *Header = L->getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


MachineBasicBlock *Latch = L->getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


using RegisterBump = std::pair<unsigned, int64_t>;

using RegisterBump = std :: pair < unsigned , int64_t > ;


using InductionMap = std::map<unsigned, RegisterBump>;

using InductionMap = std :: map < unsigned , RegisterBump > ;


using instr_iterator = MachineBasicBlock::instr_iterator;

using instr_iterator = MachineBasicBlock :: instr_iterator ;


for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) {

for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) {


for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (Phi->getOperand(i+1).getMBB() != Latch) {

if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) {


unsigned PhiOpReg = Phi->getOperand(i).getReg();

unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ;


MachineInstr *DI = MRI->getVRegDef(PhiOpReg);

MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ;


if (DI->getDesc().getOpcode() == zmtarzm::ADDI) {

if ( DI -> getDesc ( ) . getOpcode ( ) == zmtarzm :: ADDI ) {


unsigned IndReg = DI->getOperand(1).getReg();

unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ;


MachineOperand &Opnd2 = DI->getOperand(2);

MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ;


if ( MRI -> getVRegDef ( IndReg ) == Phi ) {


if ( checkForImmediate ( Opnd2 , V ) ) {


unsigned UpdReg = DI->getOperand(0).getReg();

unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ;


IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ;


SmallVector < MachineOperand , 2 > Cond ;


MachineBasicBlock *TB = nullptr, *FB = nullptr;

MachineBasicBlock * TB = nullptr , * FB = nullptr ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


unsigned PredR , PredPos , PredRegFlags ;


if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) {


MachineInstr *PredI = MRI->getVRegDef(PredR);

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);

bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


InductionMap::iterator IndMapEnd = IndMap.end();

InductionMap :: iterator IndMapEnd = IndMap . end ( ) ;


InductionMap :: iterator F = IndMapEnd ;


InductionMap::iterator F1 = IndMap.find(CmpReg1);

InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ;


InductionMap::iterator F2 = IndMap.find(CmpReg2);

InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ;


IVOp = MRI -> getVRegDef ( F -> first ) ;


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


zmtarzmHardWareLoops::Comparison::Kind zmtarzmHardwareLoops::getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const {

zmtarzmHardWareLoops :: Comparison :: Kind zmtarzmHardwareLoops :: getComparisonKind ( unsigned CondOpc , MachineOperand * InitialValue , const MachineOperand * EndValue , int64_t IVBump ) const {


Comparison::Kind Cmp = (Comparison::Kind)0;

Comparison :: Kind Cmp = ( Comparison :: Kind ) 0 ;


if ( CondOpc == zmtarzm :: C2_cmpeqi ) {


if ( CondOpc == zmtarzm :: C4_cmpneq ) {


if ( CondOpc == zmtarzm :: C4_cmplte ) {


if ( CondOpc == zmtarzm :: C2_cmpgtui ) {


if ( CondOpc == zmtarzm :: C2_cmpgti ) {


if ( CondOpc == zmtarzm :: C2_cmpeqp ) {


if ( CondOpc == zmtarzm :: C4_cmpneqi ) {


if ( CondOpc == zmtarzm :: C2_cmpgtu ) {


if ( CondOpc == zmtarzm :: C2_cmpgtup ) {


if ( CondOpc == zmtarzm :: C2_cmpgtp ) {


assert(isImm() && "Wrong CountValue accessor");

assert
(
isImm
(
)
&&
"Wrong CountValue accessor"
)
;


CountValue *zmtarzmHardwareLoops::getLoopTripCount(MachineLoop *L, SmallVectorImpl<MachineInstr *> &OldInsts) {

CountValue * zmtarzmHardwareLoops :: getLoopTripCount ( MachineLoop * L , SmallVectorImpl < MachineInstr * > & OldInsts ) {


MachineBasicBlock *TopMBB = L->getTopBlock();

MachineBasicBlock * TopMBB = L -> getTopBlock ( ) ;


MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();

MachineBasicBlock :: pred_iterator PI = TopMBB -> pred_begin ( ) ;


assert(PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!");


MachineBasicBlock * Backedge = * PI ++ ;


MachineBasicBlock * Incoming = * PI ++ ;


MachineBasicBlock *ExitingBlock = L -> findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);

bool FoundIV = findInductionRegister ( L , IVReg , IVBump , IVOp ) ;


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineOperand * InitialValue = nullptr ;


MachineInstr *IV_Phi = MRI -> getVRegDef(IVReg);

MachineInstr * IV_Phi = MRI -> getVRegDef ( IVReg ) ;


MachineBasicBlock *Latch = L -> getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


for (unsigned i = 1, n = IV_Phi -> getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


MachineBasicBlock *MBB = IV_Phi->getOperand(i + 1).getMBB();

MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + 1 ) . getMBB ( ) ;


InitialValue = & IV_Phi -> getOperand ( i ) ;


IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ;


SmallVector < MachineOperand , 2 > Cond ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


MachineBasicBlock *Header = L -> getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


assert (TB && "Exit block without a branch?");

assert
(
TB
&&
"Exit block without a branch?"
)
;


SmallVector < MachineOperand , 2 > LCond ;


bool NotAnalyzed = TII -> analyzeBranch(*Latch, LTB, LFB, LCond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ;


assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");

assert
(
(
!
FB
||
TB
==
Header
||
FB
==
Header
)
&&
"Branches not to header?"
)
;


bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);

bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ;


if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) {


MachineInstr *CondI = MRI->getVRegDef(PredReg);

MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ;


unsigned CondOpc = CondI -> getOpcode ( ) ;


bool AnalyzedCmp = TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);

bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ;


const MachineOperand &Op1 = CondI->getOperand(1);

const MachineOperand & Op1 = CondI -> getOperand ( 1 ) ;


const MachineOperand &Op2 = CondI->getOperand(2);

const MachineOperand & Op2 = CondI -> getOperand ( 2 ) ;


const MachineOperand *EndValue = nullptr;

const MachineOperand * EndValue = nullptr ;


Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);

Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ;


Cmp = Comparison :: getNegatedComparison ( Cmp ) ;


Cmp = Comparison :: getSwappedComparison ( Cmp ) ;


unsigned R = InitialValue -> getReg ( ) ;


MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();

MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ;


if (!MDT->properlyDominates(DefBB, Header)) {

if ( ! MDT -> properlyDominates ( DefBB , Header ) ) {


if (!checkForImmediate(*InitialValue, V)) {

if ( ! checkForImmediate ( * InitialValue , V ) ) {


OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ;


if ( ! checkForImmediate ( * EndValue , V ) ) {


return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);

return computeCount ( L , InitialValue , EndValue , IVReg , IVBump , Cmp ) ;


static Kind getNegatedComparison(Kind Cmp) {

static Kind getNegatedComparison ( Kind Cmp ) {


return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


assert(isReg() && "Wrong CountValue accessor");

assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;


static Kind getSwappedComparison(Kind Cmp) {

static Kind getSwappedComparison ( Kind Cmp ) {


assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator");

assert
(
(
!
(
(
Cmp
&
L
)
&&
(
Cmp
&
G
)
)
)
&&
"Malformed comparison operator"
)
;


zmtarzmHardwareLoops() : MachineFunctionPass(ID) {

zmtarzmHardwareLoops ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmHardwareLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


bool zmtarzmHardwareLoops::isDead(const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DeadPhis) const {

bool zmtarzmHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const {


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand &MO = MI->getOperand(i);

const MachineOperand & MO = MI -> getOperand ( i ) ;


if ( MO . isReg ( ) && MO . isDef ( ) ) {


if ( ! MRI -> use_nodbg_empty ( Reg ) ) {


MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);

MachineRegisterInfo :: use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ;


MachineRegisterInfo::use_nodbg_iterator End = MRI->use_nodbg_end();

MachineRegisterInfo :: use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ;


if ( I -> getParent ( ) -> isPHI ( ) ) {


MachineInstr *OnePhi = I.getOperand().getParent();

MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ;


for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {

for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) {


const MachineOperand &OPO = OnePhi->getOperand(j);

const MachineOperand & OPO = OnePhi -> getOperand ( j ) ;


MachineRegisterInfo :: use_nodbg_iterator nextJ ;


for (MachineRegisterInfo::use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J!=End; J=nextJ) {

for ( MachineRegisterInfo :: use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) {


MachineInstr * UseMI = Use . getParent ( ) ;


if ( ! I -> getParent ( ) -> isPHI ( ) ) {


bool zmtarzmHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI) const {

bool zmtarzmHardwareLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const {


if ( MO . getReg ( ) == zmtarzm :: LC0 ) {


if ( MO . getReg ( ) == zmtarzm :: LC1 ) {


if ( MO . getReg ( ) == zmtarzm :: SA0 ) {


if ( MO . getReg ( ) == zmtarzm :: SA1 ) {


if ( MO . getReg ( ) == zmtarzm :: CTR ) {


if ( MO . getReg ( ) == zmtarzm :: CTR8 ) {


for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand & MO = MI -> getOperand ( i ) ;


bool zmtarzmHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI, const MachineOperand *MO, LoopFeederMap &LoopFeederPhi) const {

bool zmtarzmHardwareLoops :: isLoopFeeder ( MachineLoop * L , MachineBasicBlock * A , MachineInstr * MI , const MachineOperand * MO , LoopFeederMap & LoopFeederPhi ) const {


if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {

if ( LoopFeederPhi . find ( MO -> getReg ( ) ) == LoopFeederPhi . end ( ) ) {


LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(**L->block_begin()));

LLVM_DEBUG
(
dbgs
(
)
<<
"\nhw_loop head, "
<<
printMBBReference
(
*
*
L
->
block_begin
(
)
)
)
;


for (MachineBasicBlock *MBB : L->getBlocks()) {

for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) {


MachineInstr *Def = MRI->getVRegDef(MO->getReg());

MachineInstr * Def = MRI -> getVRegDef ( MO -> getReg ( ) ) ;


LoopFeederPhi . insert ( std :: make_pair ( MO -> getReg ( ) , Def ) ) ;


return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ;


bool zmtarzmHardwareLoops::loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const {

bool zmtarzmHardwareLoops :: loopCountMayWrapOrUnderFlow ( const MachineOperand * InitVal , const MachineOperand * EndVal , MachineBasicBlock * MBB , MachineLoop * L , LoopFeederMap & LoopFeederPhi ) const {


if ( checkForImmediate ( * InitVal , Imm ) ) {


MachineInstr *Def = MRI->getVRegDef(Reg);

MachineInstr * Def = MRI -> getVRegDef ( Reg ) ;


if (!phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(), L, LoopFeederPhi)) {

if ( ! phiMayWrapOrUnderflow ( Def , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) {


if (!loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)), EndVal, Def->getParent(), L, LoopFeederPhi)) {

if ( ! loopCountMayWrapOrUnderFlow ( & ( Def -> getOperand ( 1 ) ) , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) {


for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); I != E; ++I) {

for ( MachineRegisterInfo :: use_instr_nodbg_iterator I = MRI -> use_instr_nodbg_begin ( Reg ) , E = MRI -> use_instr_nodbg_end ( ) ; I != E ; ++ I ) {


if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue)) {

if ( ! TII -> analyzeCompare ( * MI , CmpReg1 , CmpReg2 , CmpMask , CmpValue ) ) {


SmallVector < MachineOperand , 2 > Cond ;


if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) {

if ( TII -> analyzeBranch ( * MI -> getParent ( ) , TBB , FBB , Cond , false ) ) {


Comparison::Kind Cmp = getComparisonKind(MI->getOpcode(), nullptr, nullptr, 0);

Comparison :: Kind Cmp = getComparisonKind ( MI -> getOpcode ( ) , nullptr , nullptr , 0 ) ;


if (TII -> predOpcodeHasNot(Cond) ^ (TBB != MBB)) {

if ( TII -> predOpcodeHasNot ( Cond ) ^ ( TBB != MBB ) ) {


Cmp = Comparison :: getNegatedComparison ( Cmp ) ;


Cmp = Comparison :: getSwappedComparison ( Cmp ) ;


bool zmtarzmHardwareLoops::phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const {

bool zmtarzmHardwareLoops :: phiMayWrapOrUnderflow ( MachineInstr * Phi , const MachineOperand * EndVal , MachineBasicBlock * MBB , MachineLoop * L , LoopFeederMap & LoopFeederPhi ) const {


assert(Phi->isPHI() && "Expecting a Phi.");

assert
(
Phi
->
isPHI
(
)
&&
"Expecting a Phi."
)
;


for (int i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( int i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi)) {

if ( isLoopFeeder ( L , MBB , Phi , & ( Phi -> getOperand ( i ) ) , LoopFeederPhi ) ) {


if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal, Phi->getParent(), L, LoopFeederPhi)) {

if ( loopCountMayWrapOrUnderFlow ( & ( Phi -> getOperand ( i ) ) , EndVal , Phi -> getParent ( ) , L , LoopFeederPhi ) ) {


void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {

void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const {


OS << "register: " << printReg(Contents.R.Reg, TRI, Contents.R.Sub) << '\n';

OS
<<
"register: "
<<
printReg
(
Contents
.
R
.
Reg
,
TRI
,
Contents
.
R
.
Sub
)
<<
'\n'
;


OS << "immediate: " << Contents.ImmVal << '\n';

OS
<<
"immediate: "
<<
Contents
.
ImmVal
<<
'\n'
;


void zmtarzmHardwareLoops::removeIfDead(MachineInstr *MI) {

void zmtarzmHardwareLoops :: removeIfDead ( MachineInstr * MI ) {


SmallVector<MachineInstr *, 1> DeadPhis;

SmallVector < MachineInstr * , 1 > DeadPhis ;


LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI);

LLVM_DEBUG
(
dbgs
(
)
<<
"HW looping will remove: "
<<
*
MI
)
;


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand &MO = MI->getOperand(i);

const MachineOperand & MO = MI -> getOperand ( i ) ;


MachineRegisterInfo :: use_iterator nextI ;


for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) {

for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) {


MachineInstr * UseMI = I -> getParent ( ) ;


UseMI -> getOperand ( 0 ) . setReg ( 0U ) ;


for (unsigned i = 0; i < DeadPhis.size(); ++i) {

for ( unsigned i = 0 ; i < DeadPhis . size ( ) ; ++ i ) {


bool zmtarzmFrepLoops::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmFrepLoops :: runOnMachineFunction ( MachineFunction & MF ) {


MLI = & getAnalysis < MachineLoopInfo > ( ) ;


MDT = & getAnalysis < MachineDominatorTree > ( ) ;


TII = MF . getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


Changed = Changed | convertToHardwareLoop(L, L0Used, L1Used);

Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ;


zmtarzmRegisterBankInfo::zmtarzmRegisterBankInfo(const TargetRegisterInfo &TRI) : zmtarzmGenRegisterBankInfo() {

zmtarzmRegisterBankInfo :: zmtarzmRegisterBankInfo ( const TargetRegisterInfo & TRI ) : zmtarzmGenRegisterBankInfo ( ) {


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


assert
(
isUInt
<
6
>
(
Offset
)
&&
"Offset is out of range"
)
;

assert(isUInt<6>(Offset) && "Offset is out of range");


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LDR ) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STR ) {


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


auto &Subtarget = MF->getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF -> getSubtarget < zmtarzmSubtarget > ( ) ;


if (MF->getFunction().getCallingConv() == #) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == # ) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) {

if (MF->getFunction().getCallingConv() == CallingConv::GHC) {


if ( MF -> getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) {


if (MF->getFnAttribute("interrupt").getValueAsString() == #) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == # ) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) {

if (MF->getFnAttribute("interrupt").getValueAsString() == "FIQ") {


if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ;

return STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;


if ( Subtarget . getTargetABI ( ) == # ) {


const uint32_t *zmtarzmRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const {

const uint32_t * zmtarzmRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {


auto &Subtarget = MF.getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


llvm_unreachable
(
"Unrecognized ABI"
)
;


Register zmtarzmRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

Register zmtarzmRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


const TargetFrameLowering *TFI = getFrameLowering(MF);

const TargetFrameLowering * TFI = getFrameLowering ( MF ) ;


return TFI -> hasFP ( MF ) ? zmtarzm :: FP : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::FP : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: R30 : zmtarzm :: R31 ;

return TFI->hasFP(MF) ? zmtarzm::R30 : zmtarzm::R31;


return TFI -> hasFP ( MF ) ? zmtarzm :: R31 : zmtarzm :: R30 ;

return TFI->hasFP(MF) ? zmtarzm::R31 : zmtarzm::R30;


return TFI -> hasFP ( MF ) ? zmtarzm :: R11 : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::R11 : zmtarzm::SP;


const uint32_t *zmtarzmRegisterInfo::getNoPreservedMask() const {

const uint32_t * zmtarzmRegisterInfo :: getNoPreservedMask ( ) const {


const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const override {

const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override {


return & zmtarzm :: GenericRegsRegClass ;


BitVector zmtarzmRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


const zmtarzmFrameLowering *TFI = getFrameLowering(MF);

const zmtarzmFrameLowering * TFI = getFrameLowering ( MF ) ;


for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {

for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) {


if ( MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


if ( ! MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


markSuperRegs ( Reserved , zmtarzm :: WSP ) ;


markSuperRegs ( Reserved , zmtarzm :: WZR ) ;


markSuperRegs ( Reserved , zmtarzm :: W19 ) ;


markSuperRegs ( Reserved , zmtarzm :: W16 ) ;


markSuperRegs ( Reserved , zmtarzm :: CRSub ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) {


if ( zmtarzm :: hasPACStackAttribute ( MF ) ) {


assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


markSuperRegs ( Reserved , zmtarzm :: r254 ) ;


markSuperRegs ( Reserved , zmtarzm :: r253 ) ;


markSuperRegs ( Reserved , zmtarzm :: r252 ) ;


markSuperRegs ( Reserved , zmtarzm :: VRFrame32 ) ;


markSuperRegs ( Reserved , zmtarzm :: VRFrameLocal32 ) ;


markSuperRegs ( Reserved , zmtarzm :: VRFrame64 ) ;


markSuperRegs ( Reserved , zmtarzm :: VRFrameLocal64 ) ;


markSuperRegs ( Reserved , zmtarzm :: VRDepot ) ;


bool zmtarzmRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const {

bool zmtarzmRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const {


const auto *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const auto * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


if ( zmtarzm :: PRegsRegClass . contains ( Reg ) ) {


FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ;


FrameIdx = FI -> getCRSpillFrameIndex ( ) ;


bool zmtarzmRegisterInfo::isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const {


return ! MF . getSubtarget < zmtarzmSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ;


bool zmtarzmRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const {


zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(#, 0, 0, 0, HwMode) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( # , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: R31 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::R31, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: ra , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::ra, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( 0 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(0, 0, 0, 0, HwMode) {


bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {

bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {


bool requiresRegisterScavenging(const MachineFunction &MF) const override {

bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


bool zmtarzmFrepLoops::checkForImmediate(const MachineOperand &MO, int64_t &Val) const {

bool zmtarzmFrepLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const {


MachineInstr * DI = MRI -> getVRegDef ( R ) ;


if (!checkForImmediate(DI->getOperand(1), TV)) {

if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) {


if (MO.getSubReg() == zmtarzm::subreg_loreg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if (MO.getSubReg() == zmtarzm::subreg_hireg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


if (DOpc == zmtarzm::CONST32_Int_Real) {

if ( DOpc == zmtarzm :: CONST32_Int_Real ) {


if (DOpc == zmtarzm::CONST64_Int_Real) {

if ( DOpc == zmtarzm :: CONST64_Int_Real ) {


if ( DOpc == zmtarzm :: A2_combineii ) {


const MachineOperand &S1 = DI->getOperand(1);

const MachineOperand & S1 = DI -> getOperand ( 1 ) ;


const MachineOperand &S2 = DI->getOperand(2);

const MachineOperand & S2 = DI -> getOperand ( 2 ) ;


if ( ! checkForImmediate ( S1 , V1 ) ) {


if ( ! checkForImmediate ( S2 , V2 ) ) {


if ( DOpc == zmtarzm :: A4_combineir ) {


if ( DOpc == zmtarzm :: A4_combineii ) {


if ( DOpc == zmtarzm :: A4_combineri ) {


if (DOpc == TargetOpcode::REG_SEQUENCE) {

if ( DOpc == TargetOpcode :: REG_SEQUENCE ) {


const MachineOperand &S3 = DI->getOperand(3);

const MachineOperand & S3 = DI -> getOperand ( 3 ) ;


if ( ! checkForImmediate ( S3 , V3 ) ) {


unsigned Sub2 = DI->getOperand(2).getImm();

unsigned Sub2 = DI -> getOperand ( 2 ) . getImm ( ) ;


unsigned Sub4 = DI->getOperand(4).getImm();

unsigned Sub4 = DI -> getOperand ( 4 ) . getImm ( ) ;


if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


llvm_unreachable("Unexpected form of REG_SEQUENCE");

llvm_unreachable
(
"Unexpected form of REG_SEQUENCE"
)
;


bool zmtarzmHardwareLoops::containsInvalidInstruction(MachineLoop *L) const {

bool zmtarzmHardwareLoops :: containsInvalidInstruction ( MachineLoop * L ) const {


LLVM_DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nhw_loop head, BB#"
<<
Blocks
[
0
]
->
getNumber
(
)
;
)
;


for (MachineBasicBlock *MBB : L->getBlocks()) {

for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) {


LLVM_DEBUG(dbgs() << "\nCannot convert to hwloop due to:"; MI.dump(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nCannot convert to hwloop due to:"
;
MI
.
dump
(
)
;
)
;


bool zmtarzmHardwareLoops::convertToHardwareLoop(MachineLoop *L, bool &RecL0used, bool &RecL1used) {

bool zmtarzmHardwareLoops :: convertToHardwareLoop ( MachineLoop * L , bool & RecL0used , bool & RecL1used ) {


assert(L->getHeader() && "Loop without a header?");

assert
(
L
->
getHeader
(
)
&&
"Loop without a header?"
)
;


for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {

for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) {


Changed = Changed | convertToHardwareLoop(*I, RecL0used, RecL1used);

Changed = Changed | convertToHardwareLoop ( * I , RecL0used , RecL1used ) ;


if (containsInvalidInstruction(L, IsInnerHWLoop)) {

if ( containsInvalidInstruction ( L , IsInnerHWLoop ) ) {


MachineBasicBlock *LastMBB = getExitingBlock(L);

MachineBasicBlock * LastMBB = getExitingBlock ( L ) ;


MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();

MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ;


MachineBasicBlock *Preheader = L->getLoopPreheader();

MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ;


Preheader = createPreheaderForLoop ( L ) ;


MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();

MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ;


SmallVector < MachineInstr * , 2 > OldInsts ;


CountValue *TripCount = getLoopTripCount(L, OldInsts);

CountValue * TripCount = getLoopTripCount ( L , OldInsts ) ;


MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());

MachineInstr * TCDef = MRI -> getVRegDef ( TripCount -> getReg ( ) ) ;


MachineBasicBlock *BBDef = TCDef->getParent();

MachineBasicBlock * BBDef = TCDef -> getParent ( ) ;


if (!MDT->dominates(BBDef, Preheader)) {

if ( ! MDT -> dominates ( BBDef , Preheader ) ) {


MachineBasicBlock *TopBlock = L->getTopBlock();

MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ;


MachineBasicBlock *ExitingBlock = getExitingBlock(L);

MachineBasicBlock * ExitingBlock = getExitingBlock ( L ) ;


if (ExitingBlock != L->getLoopLatch()) {

if ( ExitingBlock != L -> getLoopLatch ( ) ) {


SmallVector < MachineOperand , 2 > Cond ;


if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) {

if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) {


if (ExitingBlock == L->getLoopLatch()) {

if ( ExitingBlock == L -> getLoopLatch ( ) ) {


DEBUG(dbgs() << "Change to hardware loop at "; L->dump());

DEBUG
(
dbgs
(
)
<<
"Change to hardware loop at "
;
L
->
dump
(
)
)
;


if ( InsertPos != Preheader -> end ( ) ) {


unsigned CountReg = MRI->createVirtualRegister(&zmtarzm::IntRegsRegClass);

unsigned CountReg = MRI -> createVirtualRegister ( & zmtarzm :: IntRegsRegClass ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg(), 0, TripCount->getSubReg());

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , 0 , TripCount -> getSubReg ( ) ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart).addReg(CountReg);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ;


assert(TripCount->isImm() && "Expecting immediate value for trip count");


int64_t CountImm = TripCount -> getImm ( ) ;


if (!TII->isValidOffset(LOOP_i, CountImm)) {

if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(zmtarzm::A2_tfrsi), CountReg).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( zmtarzm :: A2_tfrsi ) , CountReg ) . addImm ( CountImm ) ;


if (TII->isValidOffset(LOOP_i, CountImm)) {

if ( TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i)).addMBB(LoopStart).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ;


BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ;


DebugLoc LastIDL = LastI->getDebugLoc();

DebugLoc LastIDL = LastI -> getDebugLoc ( ) ;


BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);

BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpt ) {


MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();

MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ;


if ( ! L -> contains ( BranchTarget ) ) {


SmallVector < MachineOperand , 0 > Cond ;


TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);

TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpf ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpt ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpf ) {


for (unsigned i = 0; i < OldInsts.size(); ++i) {

for ( unsigned i = 0 ; i < OldInsts . size ( ) ; ++ i ) {


explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {

explicit CountValue ( CountValueType t , unsigned v , unsigned u = 0 ) {


FunctionPass * createzmtarzmFrepLoopsPass ( ) {


const MachineInstr * zmtarzmFrepLoops::findBranchInstruction(MachineLoop *L) {

const MachineInstr * zmtarzmFrepLoops :: findBranchInstruction ( MachineLoop * L ) {


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineBasicBlock *Header = L->getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


MachineBasicBlock *Latch = L->getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


using RegisterBump = std::pair<unsigned, int64_t>;

using RegisterBump = std :: pair < unsigned , int64_t > ;


using InductionMap = std::map<unsigned, RegisterBump>;

using InductionMap = std :: map < unsigned , RegisterBump > ;


using instr_iterator = MachineBasicBlock::instr_iterator;

using instr_iterator = MachineBasicBlock :: instr_iterator ;


for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) {

for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) {


for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (Phi->getOperand(i+1).getMBB() != Latch) {

if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) {


unsigned PhiOpReg = Phi->getOperand(i).getReg();

unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ;


MachineInstr *DI = MRI->getVRegDef(PhiOpReg);

MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ;


if (DI->getDesc().getOpcode() == zmtarzm::ADDI) {

if ( DI -> getDesc ( ) . getOpcode ( ) == zmtarzm :: ADDI ) {


unsigned IndReg = DI->getOperand(1).getReg();

unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ;


MachineOperand &Opnd2 = DI->getOperand(2);

MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ;


if ( MRI -> getVRegDef ( IndReg ) == Phi ) {


if ( checkForImmediate ( Opnd2 , V ) ) {


unsigned UpdReg = DI->getOperand(0).getReg();

unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ;


IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ;


SmallVector < MachineOperand , 2 > Cond ;


MachineBasicBlock *TB = nullptr, *FB = nullptr;

MachineBasicBlock * TB = nullptr , * FB = nullptr ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


unsigned PredR , PredPos , PredRegFlags ;


if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) {


MachineInstr *PredI = MRI->getVRegDef(PredR);

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);

bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


InductionMap::iterator IndMapEnd = IndMap.end();

InductionMap :: iterator IndMapEnd = IndMap . end ( ) ;


InductionMap :: iterator F = IndMapEnd ;


InductionMap::iterator F1 = IndMap.find(CmpReg1);

InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ;


InductionMap::iterator F2 = IndMap.find(CmpReg2);

InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ;


IVOp = MRI -> getVRegDef ( F -> first ) ;


bool zmtarzmHardwareLoops::findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp) const {

bool zmtarzmHardwareLoops :: findInductionRegister ( MachineLoop * L , unsigned & Reg , int64_t & IVBump , MachineInstr * & IVOp ) const {


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineBasicBlock *Header = L->getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


MachineBasicBlock *Latch = L->getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


using RegisterBump = std::pair<unsigned, int64_t>;

using RegisterBump = std :: pair < unsigned , int64_t > ;


using InductionMap = std::map<unsigned, RegisterBump>;

using InductionMap = std :: map < unsigned , RegisterBump > ;


using instr_iterator = MachineBasicBlock::instr_iterator;

using instr_iterator = MachineBasicBlock :: instr_iterator ;


for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) {

for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) {


for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (Phi->getOperand(i+1).getMBB() != Latch) {

if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) {


unsigned PhiOpReg = Phi->getOperand(i).getReg();

unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ;


MachineInstr *DI = MRI->getVRegDef(PhiOpReg);

MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ;


if (DI->getDesc().getOpcode() == zmtarzm::ADDI) {

if ( DI -> getDesc ( ) . getOpcode ( ) == zmtarzm :: ADDI ) {


unsigned IndReg = DI->getOperand(1).getReg();

unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ;


MachineOperand &Opnd2 = DI->getOperand(2);

MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ;


if ( MRI -> getVRegDef ( IndReg ) == Phi ) {


if ( checkForImmediate ( Opnd2 , V ) ) {


unsigned UpdReg = DI->getOperand(0).getReg();

unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ;


IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ;


SmallVector < MachineOperand , 2 > Cond ;


MachineBasicBlock *TB = nullptr, *FB = nullptr;

MachineBasicBlock * TB = nullptr , * FB = nullptr ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


unsigned PredR , PredPos , PredRegFlags ;


if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) {


MachineInstr *PredI = MRI->getVRegDef(PredR);

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);

bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


InductionMap::iterator IndMapEnd = IndMap.end();

InductionMap :: iterator IndMapEnd = IndMap . end ( ) ;


InductionMap :: iterator F = IndMapEnd ;


InductionMap::iterator F1 = IndMap.find(CmpReg1);

InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ;