SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout()));

SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ;


const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( 2 ) ) -> getValue ( ) ;


return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV));

return DAG . getStore ( Op . getOperand ( 0 ) , DL , FI , Op . getOperand ( 1 ) , MachinePointerInfo ( SV ) ) ;


SDValue zmtarzmTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


auto PtrVT = getPointerTy(MF.getDataLayout());

auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ;


const zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

const zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


static SDValue zmtarzmTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const {

static SDValue zmtarzmTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const {


LLVMContext & Ctx = * DAG . getContext ( ) ;


assert
(
BV
.
getOpcode
(
)
==
ISD
::
BUILD_VECTOR
&&
"Unknown opcode!"
)
;

assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");


if (VT.getSizeInBits().getKnownMinSize() != zmtarzm::SVEBitsPerBlock) {

if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != zmtarzm :: SVEBitsPerBlock ) {


unsigned ElemSize = VT.getVectorElementType().getSizeInBits() / 8;

unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ;


unsigned ByteSize = VT.getSizeInBits().getKnownMinSize() / 8;

unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ;


EVT ByteVT = EVT::getVectorVT(Ctx, MVT::i8, { ByteSize, true });

EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ;


if (BV.getOperand(0).getOpcode() != ISD::FP_EXTEND) {

if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_EXTEND ) {


if (BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) {

if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


SDValue Op0 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(1));

SDValue Op0 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 1 ) ) ;


SDValue Op1 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(2));

SDValue Op1 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 2 ) ) ;


SDValue Op2 = DAG.getNode(ISD::MUL, DL, MVT::i32, N->getOperand(3), DAG.getConstant(ElemSize, DL, MVT::i32));

SDValue Op2 = DAG . getNode ( ISD :: MUL , DL , MVT :: i32 , N -> getOperand ( 3 ) , DAG . getConstant ( ElemSize , DL , MVT :: i32 ) ) ;


SDValue EXT = DAG.getNode(zmtarzmISD::EXT, DL, ByteVT, Op0, Op1, Op2);

SDValue EXT = DAG . getNode ( zmtarzmISD :: EXT , DL , ByteVT , Op0 , Op1 , Op2 ) ;


int Offset = BV.getOperand(0).getOperand(0).getConstantOperandVal(1);

int Offset = BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) ;


if ( Op0 . getValueType ( ) != MVT :: v8f16 ) {


if (!Check(BV.getOperand(i), Op0, 2 * i + Offset)) {

if ( ! Check ( BV . getOperand ( i ) , Op0 , 2 * i + Offset ) ) {


MVT ElemTy = ty(InpV).getVectorElementType();

MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ;


if ( Subtarget . isHVXVectorType ( ResTy ) ) {


return DAG . getNode ( zmtarzmISD :: VCVTL , DL , VT , Op0 , DAG . getConstant ( Offset , DL , MVT :: i32 ) ) ;

return DAG.getNode(zmtarzmISD::VCVTL, DL, VT, Op0, DAG.getConstant(Offset, DL, MVT::i32));


SDValue zmtarzmTargetLowering::lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
BV
.
getOpcode
(
)
==
ISD
::
BUILD_VECTOR
&&
"Unknown opcode!"
)
;


if (BV.getOperand(0).getOpcode() != ISD::FP_ROUND) {

if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_ROUND ) {


if (BV.getOperand(0).getOperand(0).getConstantOperandVal(1) != 0) {

if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) {


if (BV.getOperand(1).getOpcode() != ISD::FP_ROUND) {

if ( BV . getOperand ( 1 ) . getOpcode ( ) != ISD :: FP_ROUND ) {


if (BV.getOperand(1).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) {

if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


if (BV.getOperand(1).getOperand(0).getConstantOperandVal(1) != 0) {

if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) {


SDValue Op0 = BV.getOperand(0).getOperand(0).getOperand(0);

SDValue Op0 = BV . getOperand ( 0 ) . getOperand ( 0 ) . getOperand ( 0 ) ;


SDValue Op1 = BV.getOperand(1).getOperand(0).getOperand(0);

SDValue Op1 = BV . getOperand ( 1 ) . getOperand ( 0 ) . getOperand ( 0 ) ;


if ( Op0 . getValueType ( ) != MVT :: v4f32 ) {


if ( Op1 . getValueType ( ) != MVT :: v4f32 ) {


if (!Check(BV.getOperand(i * 2 + 0), Op0, i)) {

if ( ! Check ( BV . getOperand ( i * 2 + 0 ) , Op0 , i ) ) {


if (!Check(BV.getOperand(i * 2 + 1), Op1, i)) {

if ( ! Check ( BV . getOperand ( i * 2 + 1 ) , Op1 , i ) ) {


SDValue N1 = DAG.getNode(zmtarzmISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0, DAG.getConstant(0, dl, MVT::i32));

SDValue N1 = DAG . getNode ( zmtarzmISD :: VCVTN , dl , VT , DAG . getUNDEF ( VT ) , Op0 , DAG . getConstant ( 0 , dl , MVT :: i32 ) ) ;


return DAG.getNode(zmtarzmISD::VCVTN, dl, VT, N1, Op1, DAG.getConstant(1, dl, MVT::i32));

return DAG . getNode ( zmtarzmISD :: VCVTN , dl , VT , N1 , Op1 , DAG . getConstant ( 1 , dl , MVT :: i32 ) ) ;


bool zmtarzmTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {

bool zmtarzmTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const {


static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {

static void normaliseSetCC ( SDValue & LHS , SDValue & RHS , ISD :: CondCode & CC ) {


CC = ISD :: getSetCCSwappedOperands ( CC ) ;


SDValue zmtarzmTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {

SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: ADDE ) {


return performADDECombine ( N , DAG , DCI , Subtarget ) ;

return performADDECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SUBE ) {


return performSUBECombine ( N , DAG , DCI , Subtarget ) ;

return performSUBECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SHL ) {


return performSHLCombine ( N , DAG , DCI , Subtarget ) ;

return performSHLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRA ) {


return performSRACombine ( N , DAG , DCI , Subtarget ) ;

return performSRACombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRL ) {


return performSRLCombine ( N , DAG , DCI , Subtarget ) ;

return performSRLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: VSELECT ) {


return performVSELECTCombine ( N , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: SETCC ) {


return TargetLowering :: PerformDAGCombine ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: VECTOR_SHUFFLE ) {

if (N->getOpcode() == ISD::VECTOR_SHUFFLE) {


return performVECTOR_SHUFFLECombine ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: SIGN_EXTEND ) {

if (N->getOpcode() == ISD::SIGN_EXTEND) {


return performVectorExtendCombine ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: ZERO_EXTEND ) {

if (N->getOpcode() == ISD::ZERO_EXTEND) {


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT_SAT ) {

if (N->getOpcode() == ISD::FP_TO_SINT_SAT) {


return performVectorTruncZeroCombine ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT_SAT ) {

if (N->getOpcode() == ISD::FP_TO_UINT_SAT) {


if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) {


if ( N -> getOpcode ( ) == ISD :: CONCAT_VECTORS ) {

if (N->getOpcode() == ISD::CONCAT_VECTORS) {


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: BITCAST ) {


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_ADD ) {

if (N->getOpcode() == ISD::VECREDUCE_ADD) {


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_SMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_SMIN) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_UMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_UMIN) {


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: CTPOP ) {


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


if ( N -> getOpcode ( ) == ISD :: SMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


if ( N -> getOpcode ( ) == ISD :: SMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


if ( N -> getOpcode ( ) == ISD :: UMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;

assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: ATOMIC_CMP_SWAP ) {

if (N->getOpcode() == ISD::ATOMIC_CMP_SWAP) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


assert
(
SDValue
(
N
,
0
)
.
getValueType
(
)
==
MVT
::
i128
&&
"unexpected load's value type"
)
;

assert(SDValue(N, 0).getValueType() == MVT::i128 && "unexpected load's value type");


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {


if (N->getOperand(0).getValueType() != MVT::i64) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) {


Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


return ReplaceLongIntrinsic(N, Results, DAG);

return ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_SUBVECTOR ) {

if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) {


ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


assert
(
(
VT
==
MVT
::
i8
||
VT
==
MVT
::
i16
)
&&
"custom lowering for unexpected type"
)
;

assert((VT == MVT::i8 || VT == MVT::i16) &&"custom lowering for unexpected type");


ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));

ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if (IntID == Intrinsic::aarch64_sve_clasta_n) {

if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) {


auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));

auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ;


auto V = DAG.getNode(zmtarzmISD::CLASTA_N, DL, MVT::i32, N->getOperand(1), Op2, N->getOperand(3));

auto V = DAG . getNode ( zmtarzmISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ;


Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));

Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ;


if (IntID == Intrinsic::aarch64_sve_lasta) {

if ( IntID == Intrinsic :: aarch64_sve_lasta ) {


auto V = DAG.getNode(zmtarzmISD::LASTA, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


if (IntID == Intrinsic::aarch64_sve_lastb) {

if ( IntID == Intrinsic :: aarch64_sve_lastb ) {


auto V = DAG.getNode(zmtarzmISD::LASTB, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


LoadSDNode * Ld = cast < LoadSDNode > ( N ) ;


if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) {


if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) {


SDValue LoadRes = DAG.getExtLoad(Ld->getExtensionType(), DL, MVT::v2i32, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), Ld->getMemOperand()->getFlags(), Ld->getAAInfo());

SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


SDValue Res = DAG.getNode(ISD::BITCAST, DL, MVT::i64, LoadRes);

SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ;


Results . push_back ( LoadRes . getValue ( 1 ) ) ;


llvm_unreachable("Don't know how to custom expand this");

llvm_unreachable
(
"Don't know how to custom expand this"
)
;


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


if ( N -> getOpcode ( ) == ISD :: READ_REGISTER ) {

if (N->getOpcode() == ISD::READ_REGISTER) {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: BITCAST ) {


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: SRL ) {


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: SRA ) {


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SHL ) {


if ( N -> getOpcode ( ) == ISD :: SREM ) {


if ( N -> getOpcode ( ) == ISD :: UREM ) {


if ( N -> getOpcode ( ) == ISD :: SDIVREM ) {


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;

assert(Res.getNumOperands() == 2 && "DivRem needs two values");


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: UDIVREM ) {


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SADDSAT ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: SSUBSAT ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


if ( N -> getOpcode ( ) == ISD :: READCYCLECOUNTER ) {

if (N->getOpcode() == ISD::READCYCLECOUNTER) {


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UDIV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;

assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;

assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: ATOMIC_CMP_SWAP ) {

if (N->getOpcode() == ISD::ATOMIC_CMP_SWAP) {


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


assert
(
SDValue
(
N
,
0
)
.
getValueType
(
)
==
MVT
::
i128
&&
"unexpected load's value type"
)
;

assert(SDValue(N, 0).getValueType() == MVT::i128 && "unexpected load's value type");


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_SUBVECTOR ) {

if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {


if (N->getOperand(0).getValueType() != MVT::i64) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) {


Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


return ReplaceLongIntrinsic(N, Results, DAG);

return ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: ABS ) {


ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));

ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if (IntID == Intrinsic::aarch64_sve_clasta_n) {

if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) {


auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));

auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ;


auto V = DAG.getNode(zmtarzmISD::CLASTA_N, DL, MVT::i32, N->getOperand(1), Op2, N->getOperand(3));

auto V = DAG . getNode ( zmtarzmISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ;


Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));

Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ;


if (IntID == Intrinsic::aarch64_sve_lasta) {

if ( IntID == Intrinsic :: aarch64_sve_lasta ) {


auto V = DAG.getNode(zmtarzmISD::LASTA, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


if (IntID == Intrinsic::aarch64_sve_lastb) {

if ( IntID == Intrinsic :: aarch64_sve_lastb ) {


auto V = DAG.getNode(zmtarzmISD::LASTB, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


LoadSDNode * Ld = cast < LoadSDNode > ( N ) ;


if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) {


if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) {


SDValue LoadRes = DAG.getExtLoad(Ld->getExtensionType(), DL, MVT::v2i32, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), Ld->getMemOperand()->getFlags(), Ld->getAAInfo());

SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


SDValue Res = DAG.getNode(ISD::BITCAST, DL, MVT::i64, LoadRes);

SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ;


Results . push_back ( LoadRes . getValue ( 1 ) ) ;


llvm_unreachable("Don't know how to custom expand this");

llvm_unreachable
(
"Don't know how to custom expand this"
)
;


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: READCYCLECOUNTER ) {

if (N->getOpcode() == ISD::READCYCLECOUNTER) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


assert ( Subtarget -> hasLeonCycleCounter ( ) ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: SINT_TO_FP ) {

if (N->getOpcode() == ISD::SINT_TO_FP) {


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {


if (N->getOperand(0).getValueType() != MVT::i64) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) {


Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


return ReplaceLongIntrinsic(N, Results, DAG);

return ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: UINT_TO_FP ) {

if (N->getOpcode() == ISD::UINT_TO_FP) {


ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));

ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if (IntID == Intrinsic::aarch64_sve_clasta_n) {

if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) {


auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));

auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ;


auto V = DAG.getNode(zmtarzmISD::CLASTA_N, DL, MVT::i32, N->getOperand(1), Op2, N->getOperand(3));

auto V = DAG . getNode ( zmtarzmISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ;


Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));

Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ;


if (IntID == Intrinsic::aarch64_sve_lasta) {

if ( IntID == Intrinsic :: aarch64_sve_lasta ) {


auto V = DAG.getNode(zmtarzmISD::LASTA, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


if (IntID == Intrinsic::aarch64_sve_lastb) {

if ( IntID == Intrinsic :: aarch64_sve_lastb ) {


auto V = DAG.getNode(zmtarzmISD::LASTB, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


LoadSDNode * Ld = cast < LoadSDNode > ( N ) ;


if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) {


if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) {


SDValue LoadRes = DAG.getExtLoad(Ld->getExtensionType(), DL, MVT::v2i32, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), Ld->getMemOperand()->getFlags(), Ld->getAAInfo());

SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


SDValue Res = DAG.getNode(ISD::BITCAST, DL, MVT::i64, LoadRes);

SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ;


Results . push_back ( LoadRes . getValue ( 1 ) ) ;


llvm_unreachable("Don't know how to custom expand this");

llvm_unreachable
(
"Don't know how to custom expand this"
)
;


bool shouldConsiderGEPOffsetSplit() const override {

bool shouldConsiderGEPOffsetSplit ( ) const override {


bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override {

bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override {


TargetLowering::AtomicExpansionKind zmtarzmTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {

TargetLowering :: AtomicExpansionKind zmtarzmTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const {


unsigned Size = AI->getCompareOperand()->getType()->getPrimitiveSizeInBits();

unsigned Size = AI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ;


TargetLowering::AtomicExpansionKind zmtarzmTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {

TargetLowering :: AtomicExpansionKind zmtarzmTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const {


if ( AI -> isFloatingPointOperation ( ) ) {


if (getTargetMachine().getOptLevel() == #) {

if ( getTargetMachine ( ) . getOptLevel ( ) == # ) {


unsigned Size = AI->getType()->getPrimitiveSizeInBits();

unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;


if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) {

if (AI->getOperation() == AtomicRMWInst::Nand) {


bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();

bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ;


if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) {

if (getTargetMachine().getOptLevel() == CodeGenOpt::None) {


if ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) {

if (Size <= (Subtarget->isMClass() ? 32U : 64U)) {


bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {

bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) {


if ( ! Subtarget -> isTargetWindows ( ) ) {


if ( Subtarget -> isTargetWindows ( ) ) {


bool zmtarzmTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {

bool zmtarzmTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const {


if ( Subtarget . abiUsesSoftFloat ( ) ) {


bool shouldInsertFencesForAtomic(const Instruction *I) const override {

bool shouldInsertFencesForAtomic ( const Instruction * I ) const override {


bool zmtarzmTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {

bool zmtarzmTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const {


zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {

zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {

for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto *RegInfo = Subtarget.getRegisterInfo();

auto * RegInfo = Subtarget . getRegisterInfo ( ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


for ( MVT VT : MVT :: integer_valuetypes ( ) ) {

for (MVT VT : MVT::integer_valuetypes()) {


setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1, Promote);


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction ( ISD :: ADDC , MVT :: i32 , Expand ) ;

ISD::ADDC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i32 , Expand ) ;

ISD::ADDE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i32 , Expand ) ;

ISD::SUBC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i32 , Expand ) ;

ISD::SUBE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIVREM , MVT :: i32 , Expand ) ;

ISD::UDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIVREM , MVT :: i32 , Expand ) ;

ISD::SDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MUL , MVT :: i32 , Expand ) ;

ISD::MUL zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHS , MVT :: i32 , Expand ) ;

ISD::MULHS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHS , MVT :: i64 , Expand ) ;

ISD::MULHS zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i32 , Expand ) ;

ISD::MULHU zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i64 , Expand ) ;

ISD::MULHU zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BITCAST , MVT :: f32 , Expand ) ;

ISD::BITCAST zmsplit MVT::f32 zmsplit Expand


setOperationAction ( ISD :: BITCAST , MVT :: i32 , Expand ) ;

ISD::BITCAST zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i64 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i64 zmsplit Expand


setOperationAction(#,             #,   #);

setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);

setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);

setOperationAction(#,              #,   #);


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i64 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Custom ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: SELECT_CC , MVT :: Other , Expand ) ;

ISD::SELECT_CC zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: SETCC , MVT :: i1 , Promote ) ;

ISD::SETCC zmsplit MVT::i1 zmsplit Promote


setOperationAction ( ISD :: SETCC , MVT :: i64 , Expand ) ;

ISD::SETCC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SETCC , MVT :: f32 , Expand ) ;

ISD::SETCC zmsplit MVT::f32 zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: SETCC , MVT :: f64 , Expand ) ;

ISD::SETCC zmsplit MVT::f64 zmsplit Expand


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);

ISD :: GlobalTLSAddress MVT :: i32 Custom


setOperationAction ( ISD :: ConstantPool , MVT :: i32 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VASTART,            MVT::Other, Custom);


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAEND,              MVT::Other, Expand);


setOperationAction ( ISD :: VAARG , MVT :: Other , Expand ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAARG,              MVT::Other, Expand);


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VACOPY,             MVT::Other, Expand);


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::BR_JT,              MVT::Other, Expand);


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);


setOperationAction ( ISD :: BR_CC , MVT :: f32 , Expand ) ;

ISD::BR_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::f32,   Expand);


setCondCodeAction ( CC , VT , Expand ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setOperationAction ( ISD :: BR_CC , MVT :: f64 , Expand ) ;

ISD::BR_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::f64,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::i32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i64 , Expand ) ;

ISD::BR_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::i64,   Expand);


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i1 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i1 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG,  MVT::i1,    Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i1 Expand


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Expand ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Expand ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Expand ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f32 , Expand ) ;

ISD::FP_ROUND zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP_ROUND,           MVT::f32,   Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f64 , Expand ) ;

ISD::FP_ROUND zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP_ROUND,           MVT::f64,   Expand);


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTPOP,              MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ,               MVT::i32,   Expand);


setOperationAction(#,           #,   #);

setOperationAction(#,           #,   #);


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTLZ,               MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ_ZERO_UNDEF , MVT :: i32 , Expand ) ;

ISD::CTTZ_ZERO_UNDEF zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ_ZERO_UNDEF,    MVT::i32,   Expand);

ISD :: CTTZ_ZERO_UNDEF MVT :: i32 Expand


setOperationAction ( ISD :: CTLZ_ZERO_UNDEF , MVT :: i32 , Expand ) ;

ISD::CTLZ_ZERO_UNDEF zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTLZ_ZERO_UNDEF,    MVT::i32,   Expand);

ISD :: CTLZ_ZERO_UNDEF MVT :: i32 Expand


setOperationAction ( ISD :: ROTL , MVT :: i32 , Expand ) ;

ISD::ROTL zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTL , MVT::i32, Expand);


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTR , MVT::i32, Expand);


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FREM , MVT :: f32 , Expand ) ;

ISD::FREM zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FREM,       MVT::f32, Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i8 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i8 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP, MVT::i8,  Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i16 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i16 zmsplit Expand


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i32 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i32 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FP_ROUND , MVT :: f32 , Expand ) ;

setOperationAction(ISD::FP_ROUND,   MVT::f32, Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f64 , Expand ) ;

setOperationAction(ISD::FP_ROUND,   MVT::f64, Expand);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f32 , Expand ) ;

ISD::FCOPYSIGN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOPYSIGN,  MVT::f32, Expand);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f64 , Expand ) ;

ISD::FCOPYSIGN zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FCOPYSIGN,  MVT::f64, Expand);


setOperationAction ( ISD :: FSUB , MVT :: f32 , Expand ) ;

ISD::FSUB zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSUB,       MVT::f32, Expand);


setOperationAction ( ISD :: FSIN , MVT :: f32 , Expand ) ;

ISD::FSIN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSIN,       MVT::f32, Expand);


setOperationAction ( ISD :: FCOS , MVT :: f32 , Expand ) ;

ISD::FCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOS,       MVT::f32, Expand);


setOperationAction ( ISD :: FPOWI , MVT :: f32 , Expand ) ;

ISD::FPOWI zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOWI,      MVT::f32, Expand);


setOperationAction ( ISD :: FPOW , MVT :: f32 , Expand ) ;

ISD::FPOW zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOW,       MVT::f32, Expand);


setOperationAction ( ISD :: FPOW , MVT :: f64 , Expand ) ;

ISD::FPOW zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FPOW,       MVT::f64, Expand);


setOperationAction ( ISD :: FLOG , MVT :: f32 , Expand ) ;

ISD::FLOG zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG,       MVT::f32, Expand);


setOperationAction ( ISD :: FLOG2 , MVT :: f32 , Expand ) ;

ISD::FLOG2 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG2,      MVT::f32, Expand);


setOperationAction ( ISD :: FLOG10 , MVT :: f32 , Expand ) ;

ISD::FLOG10 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG10,     MVT::f32, Expand);


setOperationAction ( ISD :: FEXP , MVT :: f32 , Expand ) ;

ISD::FEXP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FEXP,       MVT::f32, Expand);


setOperationAction ( ISD :: FSQRT , MVT :: f64 , Expand ) ;

ISD::FSQRT zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSQRT,      MVT::f64, Expand);


setOperationAction ( ISD :: FSQRT , MVT :: f32 , Expand ) ;

ISD::FSQRT zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSQRT,      MVT::f32, Expand);


setOperationAction ( ISD :: EH_LABEL , MVT :: Other , Expand ) ;

ISD::EH_LABEL zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::EH_LABEL,          MVT::Other, Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i32 Expand


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);


setStackPointerRegisterToSaveRestore ( # ) ;

setStackPointerRegisterToSaveRestore ( zmtarzm :: RSP ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);

setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {

zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {

for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto * RegInfo = Subtarget . getRegisterInfo ( ) ;

auto *RegInfo = Subtarget.getRegisterInfo();


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {

for ( MVT VT : MVT :: integer_valuetypes ( ) ) {

for (MVT VT : MVT::integer_valuetypes()) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::ZEXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::SEXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);


for ( MVT VT : MVT :: fp_valuetypes ( ) ) {


setLoadExtAction ( # , # , MVT :: f32 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: f32 , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::f32 zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);


setLoadExtAction ( # , # , MVT :: f16 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: f16 , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::f16 zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);


for ( MVT VT : MVT :: fp_vector_valuetypes ( ) ) {

for (MVT VT : MVT::fp_vector_valuetypes()) {


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);


MVT F16VT = MVT :: getVectorVT ( MVT :: f16 , VT . getVectorNumElements ( ) ) ;

MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());


setLoadExtAction ( # , # , F16 # , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , F16VT , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit F16VT zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);


setTruncStoreAction ( MVT :: f32 , MVT :: f16 , Expand ) ;

MVT::f32 zmsplit  MVT::f16 zmsplit  Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f16 , Expand ) ;

MVT::f64 zmsplit  MVT::f16 zmsplit  Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f32 , Expand ) ;

MVT::f64 zmsplit MVT::f32 zmsplit Expand


AddPromotedToType ( ISD :: SETCC , MVT :: i1 , MVT :: i32 ) ;

ISD::SETCC zmsplit MVT::i1 zmsplit MVT::i32


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::BR_JT,              MVT::Other, Expand);


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);


setOperationAction ( ISD :: BlockAddress , MVT :: i32 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);


setOperationAction ( ISD :: ConstantPool , MVT :: i32 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: f32 , Custom ) ;

ISD::SELECT zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::f32,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: f64 , Custom ) ;

ISD::SELECT zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::f64,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: i32 , Custom ) ;

ISD::SELECT zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::i32,   Custom);


setOperationAction ( ISD :: SETCC , MVT :: f32 , Custom ) ;

ISD::SETCC zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::SETCC,              MVT::f32,   Custom);


setOperationAction ( ISD :: SETCC , MVT :: f64 , Custom ) ;

ISD::SETCC zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::SETCC,              MVT::f64,   Custom);


setOperationAction ( ISD :: BRCOND , MVT :: Other , Custom ) ;

ISD::BRCOND zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::BRCOND,             MVT::Other, Custom);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f32 , Custom ) ;

ISD::FCOPYSIGN zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f64 , Custom ) ;

ISD::FCOPYSIGN zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);


setOperationAction ( ISD :: FP_TO_SINT , MVT :: i32 , Custom ) ;

ISD::FP_TO_SINT zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalAddress , MVT :: i64 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);


setOperationAction ( ISD :: BlockAddress , MVT :: i64 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i64 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);

ISD :: GlobalTLSAddress MVT :: i64 Custom


setOperationAction ( ISD :: JumpTable , MVT :: i64 , Custom ) ;

ISD::JumpTable zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);


setOperationAction ( ISD :: ConstantPool , MVT :: i64 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: i64 , Custom ) ;

ISD::SELECT zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::i64,   Custom);


setOperationAction ( ISD :: LOAD , MVT :: i64 , Custom ) ;

ISD::LOAD zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::LOAD,               MVT::i64,   Custom);


setOperationAction ( ISD :: STORE , MVT :: i64 , Custom ) ;

ISD::STORE zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::STORE,              MVT::i64,   Custom);


setOperationAction ( ISD :: FP_TO_SINT , MVT :: i64 , Custom ) ;

ISD::FP_TO_SINT zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);


setOperationAction ( ISD :: SHL_PARTS , MVT :: i64 , Custom ) ;

ISD::SHL_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i64 , Custom ) ;

ISD::SRA_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i64 , Custom ) ;

ISD::SRL_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Custom ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Custom ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Custom ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: EH_DWARF_CFA , MVT :: i32 , Custom ) ;

ISD::EH_DWARF_CFA zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);


setOperationAction ( ISD :: EH_DWARF_CFA , MVT :: i64 , Custom ) ;

ISD::EH_DWARF_CFA zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i64 , Expand ) ;

ISD::SDIV zmsplit MVT::i64 zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: SREM , MVT :: i64 , Expand ) ;

ISD::SREM zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i64 , Expand ) ;

ISD::UDIV zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i64 , Expand ) ;

ISD::UREM zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i32 , Expand ) ;

ISD::ADDC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i32 , Expand ) ;

ISD::ADDE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i64 , Expand ) ;

ISD::ADDC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i64 , Expand ) ;

ISD::ADDE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i32 , Expand ) ;

ISD::SUBC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i32 , Expand ) ;

ISD::SUBE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i64 , Expand ) ;

ISD::SUBC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i64 , Expand ) ;

ISD::SUBE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BR_CC , MVT :: f32 , Expand ) ;

ISD::BR_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: f64 , Expand ) ;

ISD::BR_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);


setCondCodeAction ( CC , VT , Expand ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i64 , Expand ) ;

ISD::BR_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i32 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i64 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i32 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i64 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i1 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i1 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Legal ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Legal ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Expand ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i64 , Expand ) ;

ISD::CTTZ zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i32 , Expand ) ;

ISD::ROTL zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i32,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i64 , Expand ) ;

ISD::ROTL zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i64,   Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i64 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i64 Expand


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i32,   Expand);


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i64 , Expand ) ;

ISD::ROTR zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i64,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f32 , Expand ) ;

ISD::FSIN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f32,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f64 , Expand ) ;

ISD::FSIN zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f64,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f32 , Expand ) ;

ISD::FCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f32,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f64 , Expand ) ;

ISD::FCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f64,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f32 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f64 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f32 , Expand ) ;

ISD::FPOW zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f32,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f64 , Expand ) ;

ISD::FPOW zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f64,   Expand);


setOperationAction ( ISD :: FLOG , MVT :: f32 , Expand ) ;

ISD::FLOG zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG,              MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG2 , MVT :: f32 , Expand ) ;

ISD::FLOG2 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG10 , MVT :: f32 , Expand ) ;

ISD::FLOG10 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);


setOperationAction ( ISD :: FEXP , MVT :: f32 , Expand ) ;

ISD::FEXP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FEXP,              MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f32 , Expand ) ;

ISD::FMA zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f64 , Expand ) ;

ISD::FMA zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f64,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f32 , Expand ) ;

ISD::FREM zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f32,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f64 , Expand ) ;

ISD::FREM zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f64,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f32 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f32 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f64 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f64 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);


setOperationAction ( ISD :: EH_RETURN , MVT :: Other , Custom ) ;

ISD::EH_RETURN zmsplit MVT::Other zmsplit Custom


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VASTART,           MVT::Other, Custom);


setOperationAction ( ISD :: VAARG , MVT :: Other , Custom ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VAARG,             MVT::Other, Custom);


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VACOPY,            MVT::Other, Expand);


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAEND,             MVT::Other, Expand);


setStackPointerRegisterToSaveRestore ( # ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);


setOperationAction ( ISD :: ATOMIC_LOAD , MVT :: i64 , Expand ) ;

ISD::ATOMIC_LOAD zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);


setOperationAction ( ISD :: ATOMIC_STORE , MVT :: i64 , Expand ) ;

ISD::ATOMIC_STORE zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i8 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i8 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i8 Expand


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i16 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i16 zmsplit Expand

ISD :: SIGN_EXTEND_INREG MVT :: i16 Expand


if ( Subtarget . inzmtarzm16Mode ( ) ) {


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTLZ , MVT :: i64 , Expand ) ;

ISD::CTLZ zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: BSWAP , MVT :: i64 , Expand ) ;

ISD::BSWAP zmsplit MVT::i64 zmsplit Expand


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::SEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: SEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: ZEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::ZEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: ZEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: EXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::EXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: EXTLOAD MVT :: i64 MVT :: i32 Custom


setTruncStoreAction ( MVT :: i64 , MVT :: i32 , Custom ) ;

MVT::i64 zmsplit  MVT::i32 zmsplit  Custom


setOperationAction ( ISD :: TRAP , MVT :: Other , Legal ) ;

ISD::TRAP zmsplit MVT::Other zmsplit Legal


setTargetDAGCombine ( ISD :: SDIVREM ) ;


setTargetDAGCombine ( ISD :: UDIVREM ) ;


setTargetDAGCombine ( ISD :: AssertZext ) ;


setLibcallName ( RTLIB :: SHL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRA_I128 , nullptr ) ;


setMinFunctionAlignment ( Subtarget . isGP64bit ( ) ? 3 : 2 ) ;

setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);


setMinStackArgumentAlignment ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? 8 : 4 ) ;

setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);


setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;

setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);


isMicrozmtarzm = Subtarget . inMicrozmtarzmMode ( ) ;


bool zmtarzmTargetLowering::targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const {

bool zmtarzmTargetLowering :: targetShrinkDemandedConstant ( SDValue Op , const APInt & DemandedBits , const APInt & DemandedElts , TargetLoweringOpt & TLO ) const {


if ( Op . getOpcode ( ) != ISD :: AND ) {


assert
(
VT
==
MVT
::
i32
&&
"Unexpected integer type"
)
;

assert(VT == MVT::i32 && "Unexpected integer type");


unsigned Size = VT . getSizeInBits ( ) ;


ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));

ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ;


const APInt & Mask = C -> getAPIntValue ( ) ;


APInt ShrunkMask = Mask & DemandedBits ;


APInt ExpandedMask = Mask | ~ Demanded ;


return TLO . CombineTo ( Op , Op . getOperand ( 0 ) ) ;


unsigned Width = ShrunkMask.getActiveBits();

unsigned Width = ShrunkMask . getActiveBits ( ) ;


Width = PowerOf2Ceil(std::max(Width, 8U));

Width = PowerOf2Ceil ( std :: max ( Width , 8U ) ) ;


APInt ZeroExtendMask = APInt::getLowBitsSet(Size, Width);

APInt ZeroExtendMask = APInt :: getLowBitsSet ( Size , Width ) ;


if (!ZeroExtendMask.isSubsetOf(Mask | ~Demanded)) {

if ( ! ZeroExtendMask . isSubsetOf ( Mask | ~ Demanded ) ) {


SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);

SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ;


SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);

SDValue NewOp = TLO . DAG . getNode ( ISD :: AND , DL , VT , Op . getOperand ( 0 ) , NewC ) ;


SDValue NewC = TLO . DAG . getConstant ( ZeroExtendMask , DL , VT ) ;

SDValue NewC = TLO.DAG.getConstant(ZeroExtendMask, DL, VT);


void zmtarzmTargetLowering::validateCCReservedRegs(const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, MachineFunction &MF) const {

void zmtarzmTargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const {


auto *CA = dyn_cast<ConstantSDNode>(Ptr);

auto * CA = dyn_cast < ConstantSDNode > ( Ptr ) ;


unsigned Addr = CA -> getZExtValue ( ) ;


Align HaveAlign = Addr != 0 ? Align(1ull << countTrailingZeros(Addr)) : NeedAlign;

Align HaveAlign = Addr != 0 ? Align ( 1ull << countTrailingZeros ( Addr ) ) : NeedAlign ;


static int DK_MisalignedTrap = llvm::getNextAvailablePluginDiagnosticKind();

static int DK_MisalignedTrap = llvm :: getNextAvailablePluginDiagnosticKind ( ) ;


OS << "Misaligned constant address: " << format_hex(Addr, 10) << " has alignment " << HaveAlign.value() << ", but the memory access requires " << NeedAlign.value();

OS
<<
"Misaligned constant address: "
<<
format_hex
(
Addr
,
10
)
<<
" has alignment "
<<
HaveAlign
.
value
(
)
<<
", but the memory access requires "
<<
NeedAlign
.
value
(
)
;


if ( DebugLoc DL = dl . getDebugLoc ( ) ) {


OS << ". The instruction has been replaced with a trap.";


DAG . getContext ( ) -> diagnose ( DiagnosticInfoMisalignedTrap ( O . str ( ) ) ) ;


zmtarzmLegalizerInfo::zmtarzmLegalizerInfo(const zmtarzmSubtarget &ST) {

zmtarzmLegalizerInfo :: zmtarzmLegalizerInfo ( const zmtarzmSubtarget & ST ) {


unsigned getLibCallStackSize ( ) const {


int getMoveF64FrameIndex(MachineFunction &MF) {

int getMoveF64FrameIndex ( MachineFunction & MF ) {


zmtarzmMachineFunctionInfo(const MachineFunction &MF) {

zmtarzmMachineFunctionInfo ( const MachineFunction & MF ) {


void setLibCallStackSize(unsigned Size) {

void setLibCallStackSize ( unsigned Size ) {


void setVarArgsFrameIndex ( int Index ) {


bool useSaveRestoreLibCalls(const MachineFunction &MF) const {

bool useSaveRestoreLibCalls ( const MachineFunction & MF ) const {


MatInt::InstSeq MatInt::generateInstSeq(int64_t Val) {

MatInt :: InstSeq MatInt :: generateInstSeq ( int64_t Val ) {


const int64_t Highest12 = Val >> 52 & 0xFFF;


const int64_t Higher20 = Val >> 32 & 0xFFFFF;


const int64_t Hi20 = Val >> 12 & 0xFFFFF;


if ( SignExtend64 < 52 > ( Val ) == 0 ) {


Insts . push_back ( Inst ( zmtarzm :: LU52I_D , SignExtend64 < 12 > ( Highest12 ) ) ) ;


Insts . push_back ( Inst ( zmtarzm :: ORI , Lo12 ) ) ;


Insts . push_back ( Inst ( zmtarzm :: ADDI_W , SignExtend64 < 12 > ( Lo12 ) ) ) ;


Insts . push_back ( Inst ( zmtarzm :: LU12I_W , SignExtend64 < 20 > ( Hi20 ) ) ) ;


if (SignExtend32<1>(Hi20 >> 19) != SignExtend32<20>(Higher20)) {

if ( SignExtend32 < 1 > ( Hi20 >> 19 ) != SignExtend32 < 20 > ( Higher20 ) ) {


Insts . push_back ( Inst ( zmtarzm :: LU32I_D , SignExtend64 < 20 > ( Higher20 ) ) ) ;


if (SignExtend32<1>(Higher20 >> 19) != SignExtend32<12>(Highest12)) {

if ( SignExtend32 < 1 > ( Higher20 >> 19 ) != SignExtend32 < 12 > ( Highest12 ) ) {


int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {

int getIntMatCost ( const APInt & Val , unsigned Size , bool IsRV64 ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {

Inst ( unsigned Opc , int64_t Imm ) : Opc ( Opc ) , Imm ( Imm ) {


MCCodeEmitter *llvm::createzmtarzmMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) {

MCCodeEmitter * llvm :: createzmtarzmMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {


return new zmtarzmMCCodeEmitter(Ctx, MCII);

return new zmtarzmMCCodeEmitter ( Ctx , MCII ) ;


void zmtarzmMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

void zmtarzmMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


Desc = MCII . get ( MI . getOpcode ( ) ) ;


expand_TLSDESCCALL(MI, OS, Fixups, STI);

expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ;


expand_CompilerBarrier(MI, OS, Fixups, STI);

expand_CompilerBarrier ( MI , OS , Fixups , STI ) ;


expand_SPACE ( MI , OS , Fixups , STI ) ;


expand_EH_SjLj_Setup(MI, OS, Fixups, STI);

expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ;


CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ;


TmpInst = MCInstBuilder ( zmtarzm :: JS ) . addImm ( 0 ) ;


TmpInst = MCInstBuilder ( zmtarzm :: J ) . addImm ( - 2 ) ;


Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


support :: endian :: write < # > ( OS , # , # ) ;


expand_COPY_TO_REGCLASS(MI, OS, Fixups, STI);

expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ;


Bits = getBinaryCodeForInstr(MI, Fixups, STI);

Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


support :: endian :: write < # > ( OS , Bits , # ) ;


support :: endian :: write < uint32_t > ( OS , Bits , support :: little ) ;

uint32_t zmsplit Bits zmsplit  support::little


llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;


void zmtarzmMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


Desc = MCII . get ( MI . getOpcode ( ) ) ;


expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ;


expand_CompilerBarrier ( MI , OS , Fixups , STI ) ;


expand_SPACE ( MI , OS , Fixups , STI ) ;


expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ;


CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ;


TmpInst = MCInstBuilder ( zmtarzm :: JS ) . addImm ( 0 ) ;


TmpInst = MCInstBuilder ( zmtarzm :: J ) . addImm ( - 2 ) ;


Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


support :: endian :: write < # > ( OS , # , # ) ;


expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ;


Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


support :: endian :: write < uint8_t > ( OS , Bits , support :: big ) ;

uint8_t zmsplit Bits zmsplit  support::big


support :: endian :: write < # > ( OS , Bits , # ) ;


support :: endian :: write < uint16_t > ( OS , Bits , support :: big ) ;

uint16_t zmsplit Bits zmsplit support::big


support :: endian :: write < uint8_t > ( OS , ( Bits >> 16 ) & 0xff , support :: big ) ;

uint8_t zmsplit (Bits >> 16) & 0xff zmsplit  support::big

support::endian::write<uint8_t>(OS, (Bits >> 16) & 0xff, support::big);

uint8_t ( Bits >> 16 ) & 0xff support :: big


llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;


void zmtarzmMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


Desc = MCII . get ( MI . getOpcode ( ) ) ;


expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ;


expand_CompilerBarrier ( MI , OS , Fixups , STI ) ;


expand_SPACE ( MI , OS , Fixups , STI ) ;


expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ;


CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ;


TmpInst = MCInstBuilder ( zmtarzm :: JS ) . addImm ( 0 ) ;


TmpInst = MCInstBuilder ( zmtarzm :: J ) . addImm ( - 2 ) ;


Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


support :: endian :: write < # > ( OS , # , # ) ;


expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ;


Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


support :: endian :: write < uint16_t > ( OS , Bits , support :: little ) ;

uint16_t zmsplit Bits zmsplit  support::little


support :: endian :: write < # > ( OS , Bits , # ) ;


support :: endian :: write < uint32_t > ( OS , Bits , support :: little ) ;


support :: endian :: write < uint64_t > ( OS , Bits , support :: little ) ;

uint64_t zmsplit Bits zmsplit support::little


llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;


void zmtarzmMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


Desc = MCII . get ( MI . getOpcode ( ) ) ;


expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ;


expand_CompilerBarrier ( MI , OS , Fixups , STI ) ;


expand_SPACE ( MI , OS , Fixups , STI ) ;


expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ;


CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ;


TmpInst = MCInstBuilder ( zmtarzm :: JS ) . addImm ( 0 ) ;


TmpInst = MCInstBuilder ( zmtarzm :: J ) . addImm ( - 2 ) ;


Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


support :: endian :: write < # > ( OS , # , # ) ;


expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ;


Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


support :: endian :: write < # > ( OS , Bits , # ) ;


support :: endian :: write < uint64_t > ( OS , Bits , support :: little ) ;


llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;


unsigned zmtarzmMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getImmOpValueAsr1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();

Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ;


assert (Kind == MCExpr::SymbolRef && "unknown MCExpr kind");

assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;


if (cast<MCSymbolRefExpr>(Expr)->getKind() == #) {

if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == # ) {

if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q1 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q1) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q1_pcrel ;


Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(FixupKind), MI.getLoc()));

Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q2 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q2) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q2_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q3 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q3) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q3_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q4 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q4) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q4_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_CALL26 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_CALL26) {


FixupKind = zmtarzm :: fixup_zmtarzm_call26_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_CALL19 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_CALL19) {


FixupKind = zmtarzm :: fixup_zmtarzm_call19_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_9BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_9BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_9bit_address ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_6BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_6BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_6bit_shamt ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_12BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_12BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_12bit_imm ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_MOVRZ ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_MOVRZ) {


FixupKind = zmtarzm :: fixup_zmtarzm_movrz_pcrel ;


llvm_unreachable
(
"Unknown fixup kind!"
)
;


unsigned zmtarzmMCCodeEmitter :: getImmOpValueAsr1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ;


assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == # ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == #) {


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_LO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_LO) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_lo16_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_HI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_HI) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_hi16_pcrel ;


unsigned zmtarzmMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {


Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();


assert (Kind == MCExpr::SymbolRef && "unknown MCExpr kind");


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_None ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_None) {


FixupKind = zmtarzm :: fixup_zmtarzm_REL26 ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;

Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(FixupKind), MI.getLoc()));


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_ABS_HI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_ABS_HI) {


FixupKind = zmtarzm :: fixup_zmtarzm_HI16_INSN ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_ABS_LO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_ABS_LO) {


FixupKind = zmtarzm :: fixup_zmtarzm_LO16_INSN ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PLT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_PLT) {


FixupKind = zmtarzm :: fixup_zmtarzm_PLT26 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTPCHI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTPCHI) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTPC_HI16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTPCLO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTPCLO) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTPC_LO16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTOFFHI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTOFFHI) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTOFF_HI16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOTOFFLO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOTOFFLO) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOTOFF_LO16 ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_GOT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_GOT) {


FixupKind = zmtarzm :: fixup_zmtarzm_GOT16 ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


llvm_unreachable
(
"Unknown fixup kind!"
)
;


unsigned zmtarzmMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getImmOpValueMinus1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ;


assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q1 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q1) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q1_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q2 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q2) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q2_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q3 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q3) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q3_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_Q4 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_Q4) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_q4_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_CALL26 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_CALL26) {


FixupKind = zmtarzm :: fixup_zmtarzm_call26_pcrel ;


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_CALL19 ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_CALL19) {


FixupKind = zmtarzm :: fixup_zmtarzm_call19_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_9BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_9BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_9bit_address ;


Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(FixupKind), MI.getLoc()));


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_6BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_6BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_6bit_shamt ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_12BIT ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_12BIT) {


FixupKind = zmtarzm :: fixup_zmtarzm_12bit_imm ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_MOVRZ ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_MOVRZ) {


FixupKind = zmtarzm :: fixup_zmtarzm_movrz_pcrel ;


llvm_unreachable
(
"Unknown fixup kind!"
)
;


unsigned zmtarzmMCCodeEmitter :: getImmOpValueMinus1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


return static_cast < unsigned > ( MO . getImm ( ) ) ;


return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ;

Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();


assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;

assert (Kind == MCExpr::SymbolRef && "unknown MCExpr kind");


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == # ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == #) {


Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_LO ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_LO) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_lo16_pcrel ;


if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_HI ) {

if (cast<MCSymbolRefExpr>(Expr)->getKind() == zmtarzmMCExpr::VK_zmtarzm_HI) {


FixupKind = zmtarzm :: fixup_zmtarzm_mov_hi16_pcrel ;


unsigned zmtarzmMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {