if ( Base . getMachineOpcode ( ) == zmtarzm :: ADDItocL ) {

if (Base.getMachineOpcode() == zmtarzm::ADDItocL) {


DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase:    ");


SDValue ImmOpnd = Base . getOperand ( 1 ) ;


if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {

if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) {


const GlobalValue *GV = GA->getGlobal();

const GlobalValue * GV = GA -> getGlobal ( ) ;


ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);

ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , MVT :: i64 , 0 , Flags ) ;


if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) {


const Constant * C = CP -> getConstVal ( ) ;


ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,  CP->getAlignment(),  0, Flags);

ImmOpnd = CurDAG -> getTargetConstantPool ( C , MVT :: i64 , CP -> getAlignment ( ) , 0 , Flags ) ;


(void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, Base.getOperand(0), N->getOperand(3));

( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ;


if ( Base . getNode ( ) -> use_empty ( ) ) {


CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ;


bool runOnMachineFunction(MachineFunction &MF) override {

bool runOnMachineFunction ( MachineFunction & MF ) override {


Subtarget = & MF . getSubtarget < zmtarzmSubtarget > ( ) ;


return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


bool zmtarzmDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {

bool zmtarzmDAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) {


if (auto FIN = dyn_cast<FrameIndexSDNode>(Addr)) {

if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) {


Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), #);

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , # ) ;

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;

Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


if ( ConstraintID == InlineAsm :: Constraint_m ) {

if (ConstraintID == InlineAsm::Constraint_m) {


llvm_unreachable("Unexpected asm memory constraint");

llvm_unreachable
(
"Unexpected asm memory constraint"
)
;


if ( ConstraintID == InlineAsm :: Constraint_i ) {

if (ConstraintID == InlineAsm::Constraint_i) {


bool zmtarzmDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {

bool zmtarzmDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


imm = CurDAG->getTargetConstant(bit, MVT::i32);

imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


bool zmtarzmTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0, unsigned Align = 1, MachineMemOperand::Flags Flags = MachineMemOperand::MONone, bool *Fast = nullptr) const {

bool zmtarzmTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , MachineMemOperand :: Flags Flags = MachineMemOperand :: MONone , bool * Fast = nullptr ) const {


if ( Subtarget . isHVXVectorType ( ) ) {


void zmtarzmTargetLowering::analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {

void zmtarzmTargetLowering :: analyzeInputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: InputArg > & Ins , bool IsRet ) const {


FunctionType *FType = MF.getFunction().getFunctionType();

FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ;


for (unsigned i = 0; i != NumArgs; ++i) {

for ( unsigned i = 0 ; i != NumArgs ; ++ i ) {


ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;

ISD :: ArgFlagsTy ArgFlags = Ins [ i ] . Flags ;


if (RetCC_(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) {

if ( RetCC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) {


LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << '\n');

LLVM_DEBUG
(
dbgs
(
)
<<
"InputArg #"
<<
i
<<
" has unhandled type "
<<
EVT
(
ArgVT
)
.
getEVTString
(
)
<<
'\n'
)
;


if (CC_(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) {

if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) {


if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {

if ( Fn ( i , ArgVT , CCValAssign :: Full , CCInfo ) ) {


void zmtarzmTargetLowering::analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, CallLoweringInfo *CLI) const {

void zmtarzmTargetLowering :: analyzeOutputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: OutputArg > & Outs , bool IsRet , CallLoweringInfo * CLI ) const {


for (unsigned i = 0; i != NumArgs; i++) {

for ( unsigned i = 0 ; i != NumArgs ; i ++ ) {


ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;

ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ;


LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"OutputArg #"
<<
i
<<
" has unhandled type "
<<
EVT
(
ArgVT
)
.
getEVTString
(
)
<<
"\n"
)
;


bool zmtarzmTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {

bool zmtarzmTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const {


CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS ? RetCC_zmtarzm_WebKit_JS : RetCC_zmtarzm_AAPCS;

CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_zmtarzm_WebKit_JS : RetCC_zmtarzm_AAPCS ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);

CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;


CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;


auto CCFunction = CCAssignFnForReturn(CallConv);

auto CCFunction = CCAssignFnForReturn ( CallConv ) ;


for (unsigned i = 0, e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


return CCInfo . CheckReturn ( Outs , RetCC ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC ) {

if (Op.getOpcode() == zmtarzmISD::SETCC) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SELECT_CC ) {

if (Op.getOpcode() == zmtarzmISD::SELECT_CC) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


unsigned zmtarzmTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

unsigned zmtarzmTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


return Op . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CARRY ) {

if (Op.getOpcode() == zmtarzmISD::CARRY) {


if ( Op . getOpcode ( ) == zmtarzmISD :: BORROW ) {

if (Op.getOpcode() == zmtarzmISD::BORROW) {


if ( Op . getOpcode ( ) == zmtarzmISD :: FP_TO_FP16 ) {

if (Op.getOpcode() == zmtarzmISD::FP_TO_FP16) {


if ( Op . getOpcode ( ) == zmtarzmISD :: FP16_ZEXT ) {

if (Op.getOpcode() == zmtarzmISD::FP16_ZEXT) {


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_I32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_I32) {


ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


unsigned SignBits = 32 - Width->getZExtValue() + 1;

unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ;


if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) {


unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);

unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ;


unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1);

unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ;


Tmp = Tmp + VTBits - Src.getScalarValueSizeInBits();

Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ;


return std :: max ( SignBits , Op0SignBits ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_U32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_U32) {


APInt ShiftVal = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();

APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ;


return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ;

return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;


unsigned zmtarzmTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC_CARRY ) {

if (Op.getOpcode() == zmtarzmISD::SETCC_CARRY) {


return Op . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: PCMPGT ) {

if (Op.getOpcode() == zmtarzmISD::PCMPGT) {


if ( Op . getOpcode ( ) == zmtarzmISD :: PCMPEQ ) {

if (Op.getOpcode() == zmtarzmISD::PCMPEQ) {


if ( Op . getOpcode ( ) == zmtarzmISD :: CMPP ) {

if (Op.getOpcode() == zmtarzmISD::CMPP) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VPCOM ) {

if (Op.getOpcode() == zmtarzmISD::VPCOM) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VPCOMU ) {

if (Op.getOpcode() == zmtarzmISD::VPCOMU) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VSEXT ) {

if (Op.getOpcode() == zmtarzmISD::VSEXT) {


ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ;


if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) {


unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ;


unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ;


Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSRAI ) {

if (Op.getOpcode() == zmtarzmISD::VSRAI) {


APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ;


return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ;

return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();


bool convertSelectOfConstantsToMath(EVT VT) const override {

bool convertSelectOfConstantsToMath ( EVT VT ) const override {


bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {

bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override {


bool zmtarzmTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const {

bool zmtarzmTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const {


if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {

if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) {


if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) {


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


unsigned Shift = countTrailingZeros<uint64_t>(Imm);

unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ;


uint64_t UImm = static_cast<uint64_t>(Imm);

uint64_t UImm = static_cast < uint64_t > ( Imm ) ;


MachineBasicBlock *zmtarzmTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const {

MachineBasicBlock * zmtarzmTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const {


return expandSelectCC(MI, BB, zmtarzm::BCOND);

return expandSelectCC ( MI , BB , zmtarzm :: BCOND ) ;


return expandSelectCC(MI, BB, zmtarzm::FBCOND);

return expandSelectCC ( MI , BB , zmtarzm :: FBCOND ) ;


if ( MI . getOpcode ( ) == zmtarzm :: F128CSEL ) {

if (MI.getOpcode() == zmtarzm::F128CSEL) {


if ( MI . getOpcode ( ) == TargetOpcode :: STACKMAP ) {

if (MI.getOpcode() == TargetOpcode::STACKMAP) {


if ( MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) {

if (MI.getOpcode() == TargetOpcode::PATCHPOINT) {


if ( MI . getOpcode ( ) == TargetOpcode :: STATEPOINT ) {

if (MI.getOpcode() == TargetOpcode::STATEPOINT) {


if ( MI . getOpcode ( ) == TargetOpcode :: CATCHRET ) {

if (MI.getOpcode() == TargetOpcode::CATCHRET) {


return EmitLoweredCatchRet ( MI , BB ) ;


if ( MI . getOpcode ( ) == TargetOpcode :: zmtarzm_setjmp_instr ) {

if (MI.getOpcode() == TargetOpcode::zmtarzm_setjmp_instr) {


if ( MI . getOpcode ( ) == TargetOpcode :: zmtarzm_longjmp_instr ) {

if (MI.getOpcode() == TargetOpcode::zmtarzm_longjmp_instr) {


llvm_unreachable("Unexpected instruction for custom inserter!");


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_Int_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_Int_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_FP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_FP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_DFP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_DFP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_QFP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_QFP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_Int_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_Int_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_FP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_FP_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_DFP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_DFP_FCC) {


return expandSelectCC ( MI , BB , zmtarzm :: FBCOND ) ;


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_QFP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_QFP_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_SETJMP32rr ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_SETJMP32rr) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_LONGJMP32rr ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_LONGJMP32rr) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_LONGJMP32ri ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_LONGJMP32ri) {


Instruction *zmtarzmTargetLowering::emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const {

Instruction * zmtarzmTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const {


if ( Ord == AtomicOrdering :: NotAtomic ) {


llvm_unreachable
(
"Invalid fence: unordered/non-atomic"
)
;


if ( Ord == AtomicOrdering :: Unordered ) {


if ( Ord == AtomicOrdering :: Monotonic ) {


if ( Ord == AtomicOrdering :: Acquire ) {


if (Ord == AtomicOrdering::SequentiallyConsistent) {

if ( Ord == AtomicOrdering :: SequentiallyConsistent ) {


if ( Ord == AtomicOrdering :: Release ) {


if ( Subtarget -> preferISHSTBarriers ( ) ) {


return makeDMB ( Builder , zmtarzm_MB :: ISHST ) ;


if ( ! Subtarget -> preferISHSTBarriers ( ) ) {


return makeDMB ( Builder , zmtarzm_MB :: ISH ) ;


if ( Ord == AtomicOrdering :: AcquireRelease ) {

if (Ord == AtomicOrdering::AcquireRelease) {


return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ;


llvm_unreachable("Unknown fence ordering in emitLeadingFence");


return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ;


Value *zmtarzmTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {

Value * zmtarzmTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const {


assert
(
shouldInlineQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;

assert(shouldInlineQuadwordAtomics() && "Only support quadword now");


Module *M = Builder.GetInsertBlock()->getParent()->getParent();

Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


assert ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) ;


Function *IntCmpXchg = Intrinsic::getDeclaration(M, Intrinsic::ppc_cmpxchg_i128);

Function * IntCmpXchg = Intrinsic :: getDeclaration ( M , Intrinsic :: ppc_cmpxchg_i128 ) ;


Type *Int64Ty = Type::getInt64Ty(M->getContext());

Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ;


Value *CmpLo = Builder.CreateTrunc(CmpVal, Int64Ty, "cmp_lo");

Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , "cmp_lo" ) ;


Value *CmpHi = Builder.CreateTrunc(Builder.CreateLShr(CmpVal, 64), Int64Ty, "cmp_hi");

Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , 64 ) , Int64Ty , "cmp_hi" ) ;


Value *NewLo = Builder.CreateTrunc(NewVal, Int64Ty, "new_lo");

Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , "new_lo" ) ;


Value *NewHi = Builder.CreateTrunc(Builder.CreateLShr(NewVal, 64), Int64Ty, "new_hi");

Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , 64 ) , Int64Ty , "new_hi" ) ;


Value *Addr = Builder.CreateBitCast(AlignedAddr, Type::getInt8PtrTy(M->getContext()));

Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


emitLeadingFence ( Builder , CI , Ord ) ;


Value *LoHi = Builder.CreateCall(IntCmpXchg, {Addr, CmpLo, CmpHi, NewLo, NewHi});

Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ;


emitTrailingFence ( Builder , CI , Ord ) ;


Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");

Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ;


Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");

Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ;


Lo = Builder.CreateZExt(Lo, ValTy, "lo64");

Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ;


Hi = Builder.CreateZExt(Hi, ValTy, "hi64");

Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ;


return Builder.CreateOr(Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");

return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ;


Value *zmtarzmTargetLowering::emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {

Value * zmtarzmTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const {


assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;

assert(EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && "Only support quadword now");


Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


Type *ValTy = AlignedAddr->getType()->getPointerElementType();

Type * ValTy = AlignedAddr -> getType ( ) -> getPointerElementType ( ) ;


assert ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) ;


Function *RMW = Intrinsic::getDeclaration(M, getIntrinsicForAtomicRMWBinOp128(AI->getOperation()));

Function * RMW = Intrinsic :: getDeclaration ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ;


Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ;


Value *IncrLo = Builder.CreateTrunc(Incr, Int64Ty, "incr_lo");

Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , "incr_lo" ) ;


Value *IncrHi = Builder.CreateTrunc(Builder.CreateLShr(Incr, 64), Int64Ty, "incr_hi");

Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , 64 ) , Int64Ty , "incr_hi" ) ;


Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


Value *LoHi = Builder.CreateCall(RMW, {Addr, IncrLo, IncrHi});

Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ;


Instruction *zmtarzmTargetLowering::emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const {

Instruction * zmtarzmTargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const {


if ( Ord == AtomicOrdering :: NotAtomic ) {


llvm_unreachable
(
"Invalid fence: unordered/not-atomic"
)
;


if ( Ord == AtomicOrdering :: Unordered ) {


if ( Ord == AtomicOrdering :: Acquire ) {


return makeDMB ( Builder , zmtarzm_MB :: ISH ) ;


if (Ord == AtomicOrdering::AcquireRelease) {

if ( Ord == AtomicOrdering :: AcquireRelease ) {


if (Ord == AtomicOrdering::SequentiallyConsistent) {

if ( Ord == AtomicOrdering :: SequentiallyConsistent ) {


if ( Ord == AtomicOrdering :: Monotonic ) {


if ( Ord == AtomicOrdering :: Release ) {


llvm_unreachable("Unknown fence ordering in emitTrailingFence");


return Builder.CreateCall(Intrinsic::getDeclaration(Builder.GetInsertBlock()->getParent()->getParent(), Intrinsic::ppc_cfence, {Inst->getType()}), {Inst});

return Builder . CreateCall ( Intrinsic :: getDeclaration ( Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) , Intrinsic :: ppc_cfence , { Inst -> getType ( ) } ) , { Inst } ) ;


return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ;


return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;


return Builder . CreateFence ( AtomicOrdering :: SequentiallyConsistent ) ;


template <class NodeTy> SDValue zmtarzmTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const {

template < class NodeTy > SDValue zmtarzmTargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal ) const {


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


Flag = IsLocal  ? zmtarzmII::MO_GOTOFF : IsCall ? zmtarzmII::MO_PLT32 : zmtarzmII::MO_GOT32;

Flag = IsLocal ? zmtarzmII :: MO_GOTOFF : IsCall ? zmtarzmII :: MO_PLT32 : zmtarzmII :: MO_GOT32 ;


SDValue GPReg = DAG.getRegister(zmtarzm::GP_REG, MVT::i32);

SDValue GPReg = DAG . getRegister ( zmtarzm :: GP_REG , MVT :: i32 ) ;


SDValue Wrapper = DAG.getNode(zmtarzmISD::GOT_ADDR, DL, Ty, GPReg, getTargetNode(N, Ty, DAG, zmtarzm::MO_GOT));

SDValue Wrapper = DAG . getNode ( zmtarzmISD :: GOT_ADDR , DL , Ty , GPReg , getTargetNode ( N , Ty , DAG , zmtarzm :: MO_GOT ) ) ;


return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, MachinePointerInfo::getGOT(DAG.getMachineFunction()));

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


SDValue TCPV = getTargetConstantPoolValue(N, Ty, DAG, Flag);

SDValue TCPV = getTargetConstantPoolValue ( N , Ty , DAG , Flag ) ;


SDValue TV = getTargetNode(N, DL, Ty, DAG, Flag);

SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ;


SDValue Hi = getTargetNode(N, Ty, DAG, zmtarzm::MO_ABS_HI);

SDValue Hi = getTargetNode ( N , Ty , DAG , zmtarzm :: MO_ABS_HI ) ;


SDValue Lo = getTargetNode(N, Ty, DAG, zmtarzm::MO_ABS_LO);

SDValue Lo = getTargetNode ( N , Ty , DAG , zmtarzm :: MO_ABS_LO ) ;


SDValue MoveHi = DAG.getNode(zmtarzmISD::MOVEHI, DL, MVT::i32, Hi);

SDValue MoveHi = DAG . getNode ( zmtarzmISD :: MOVEHI , DL , MVT :: i32 , Hi ) ;


return DAG . getNode ( zmtarzmISD :: LOAD_ADDR , DL , Ty , { TV , TCPV } ) ;

return DAG.getNode(zmtarzmISD::LOAD_ADDR, DL, Ty, {TV, TCPV});


DAG.getNode(ISD::ADD, DL, Ty, {DAG.getGLOBAL_OFFSET_TABLE(Ty), Addr});

DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ;


return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Result, MachinePointerInfo::getGOT(DAG.getMachineFunction()));

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


return DAG . getNode ( zmtarzmISD :: ORLO , DL , MVT :: i32 , MoveHi , Lo ) ;

return DAG.getNode(zmtarzmISD::ORLO, DL, MVT::i32, MoveHi, Lo);


zmtarzmTargetLowering::ConstraintType zmtarzmTargetLowering::getConstraintType(StringRef Constraint) const {

zmtarzmTargetLowering :: ConstraintType zmtarzmTargetLowering :: getConstraintType ( StringRef Constraint ) const {


return TargetLowering :: getConstraintType ( Constraint ) ;


SDValue zmtarzmTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: getDynamicTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned zmtarzmPCLabelIndex = CFI->createPICLabelUId();

unsigned zmtarzmPCLabelIndex = CFI -> createPICLabelUId ( ) ;


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());

IntegerType * CallTy = Type :: getIntNTy ( * DAG . getContext ( ) , Ty . getSizeInBits ( ) ) ;


const GlobalValue * GV = N -> getGlobal ( ) ;


zmtarzmConstantPoolValue *CPV = zmtarzmConstantPoolConstant::Create(N->getGlobal(), zmtarzmCP::CPValue, 4, zmtarzmCP::TLSGD, true, zmtarzmPCLabelIndex);

zmtarzmConstantPoolValue * CPV = zmtarzmConstantPoolConstant :: Create ( N -> getGlobal ( ) , zmtarzmCP :: CPValue , 4 , zmtarzmCP :: TLSGD , true , zmtarzmPCLabelIndex ) ;


SDValue PICLabel = DAG.getTargetConstant(zmtarzmPCLabelIndex, DL, MVT::i32);

SDValue PICLabel = DAG . getTargetConstant ( zmtarzmPCLabelIndex , DL , MVT :: i32 ) ;


SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);

SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , 0 , 0 ) ;


SDValue Load = SDValue(DAG.getMachineNode(#, DL, Ty, Addr), 0);

SDValue Load = SDValue ( DAG . getMachineNode ( # , DL , Ty , Addr ) , 0 ) ;

SDValue Load = SDValue ( DAG . getMachineNode ( zmtarzm :: PseudoTLSLA32 , DL , Ty , Addr ) , 0 ) ;

SDValue Load = SDValue(DAG.getMachineNode(zmtarzm::PseudoTLSLA32, DL, Ty, Addr), 0);


TargetLowering :: CallLoweringInfo CLI ( DAG ) ;


CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, CallTy, DAG.getExternalSymbol("__tls_get_addr", Ty), std::move(Args));

CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( "__tls_get_addr" , Ty ) , std :: move ( Args ) ) ;


Register zmtarzmTargetLowering::getExceptionPointerRegister(const Constant *PersonalityFn) const {

Register zmtarzmTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {


Register zmtarzmTargetLowering::getExceptionSelectorRegister(const Constant *PersonalityFn) const {

Register zmtarzmTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const {


ISD::NodeType getExtendForAtomicCmpSwapArg() const override {

ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override {


ISD::NodeType getExtendForAtomicOps() const override {

ISD :: NodeType getExtendForAtomicOps ( ) const override {


unsigned zmtarzmTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {

unsigned zmtarzmTargetLowering :: getInlineAsmMemConstraint ( StringRef ConstraintCode ) const {


return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


MVT zmtarzmTargetLowering::getPointerMemTy(const DataLayout &DL, uint32_t AS) const {

MVT zmtarzmTargetLowering :: getPointerMemTy ( const DataLayout & DL , uint32_t AS ) const {


if ( AS == WASM_ADDRESS_SPACE_EXTERNREF ) {

if (AS == WASM_ADDRESS_SPACE_EXTERNREF) {


if ( AS == WASM_ADDRESS_SPACE_FUNCREF ) {


MVT zmtarzmTargetLowering::getPointerTy(const DataLayout &DL, uint32_t AS) const {

MVT zmtarzmTargetLowering :: getPointerTy ( const DataLayout & DL , uint32_t AS ) const {


bool zmtarzmTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {

bool zmtarzmTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const {


if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) {

if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) {


AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;

AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ;


if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (LD->getExtensionType() != ISD::NON_EXTLOAD) {

if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) {


if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {

if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) {


if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


if ( Op -> getOpcode ( ) == ISD :: SUB ) {


Offset = DAG.getConstant(RHSC, DL, MVT::i8);

Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ;


if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if ( zmtarzm :: isProgramMemoryAccess ( ST ) ) {


LoadSDNode * LD = cast < LoadSDNode > ( N ) ;


if ( Op -> getOpcode ( ) == ISD :: ADD ) {


Offset = DAG . getConstant ( RHSC , VT ) ;


if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


uint64_t RHSC = RHS -> getZExtValue ( ) ;


std::pair<unsigned, const TargetRegisterClass *> zmtarzmTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {

std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const {


return std :: make_pair ( zmtarzm :: R14 , & # ) ;


return std :: make_pair ( zmtarzm :: C , & # ) ;


return std :: make_pair ( 0U , & zmtarzm :: GRRegsRegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


unsigned XRegFromAlias = zmtarzm::NoRegister;

unsigned XRegFromAlias = zmtarzm :: NoRegister ;


if ( Constraint . lower ( ) == "{zero}" ) {


if ( Constraint . lower ( ) == "{r0}" ) {


if ( Constraint . lower ( ) == "{r1}" ) {


if ( Constraint . lower ( ) == "{r2}" ) {


if ( Constraint . lower ( ) == "{r3}" ) {


if ( Constraint . lower ( ) == "{r4}" ) {


if ( Constraint . lower ( ) == "{r5}" ) {


if ( Constraint . lower ( ) == "{r6}" ) {


if ( Constraint . lower ( ) == "{r7}" ) {


if ( Constraint . lower ( ) == "{r8}" ) {


if ( Constraint . lower ( ) == "{r9}" ) {


if ( Constraint . lower ( ) == "{r10}" ) {


if ( Constraint . lower ( ) == "{r11}" ) {


if ( Constraint . lower ( ) == "{r12}" ) {


if ( Constraint . lower ( ) == "{r13}" ) {


if ( Constraint . lower ( ) == "{bp}" ) {


if ( Constraint . lower ( ) == "{r14}" ) {


if ( Constraint . lower ( ) == "{sp}" ) {


if ( Constraint . lower ( ) == "{r15}" ) {


if (XRegFromAlias != zmtarzm::NoRegister) {

if ( XRegFromAlias != zmtarzm :: NoRegister ) {


return std :: make_pair ( XRegFromAlias , & # ) ;

return std :: make_pair ( XRegFromAlias , & zmtarzm :: GRRegsRegClass ) ;


assert(zmtarzm::F0_32 <= FReg && FReg <= zmtarzm::F31_32 && "Unknown fp-reg");

assert
(
zmtarzm
::
F0_32
<=
FReg
&&
FReg
<=
zmtarzm
::
F31_32
&&
"Unknown fp-reg"
)
;


unsigned RegNo = FReg - zmtarzm :: F0_32 ;


unsigned DReg = zmtarzm :: F0_64 + RegNo ;


return std :: make_pair ( DReg , & # ) ;


return std :: make_pair ( FReg , & # ) ;


return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);

return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


Register zmtarzmTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const {

Register zmtarzmTargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const {


const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();

const MCRegisterInfo * MRI = Subtarget -> getRegisterInfo ( ) ;


unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);

unsigned DwarfRegNum = MRI -> getDwarfRegNum ( Reg , false ) ;


if ( ! Subtarget -> isXRegisterReserved ( DwarfRegNum ) ) {


report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;

report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName) + "\"."));


MVT zmtarzmTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, EVT) const {

MVT zmtarzmTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const {


EVT zmtarzmTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const {

EVT zmtarzmTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {


return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ;


return VT . changeVectorElementTypeToInteger ( ) ;


SDValue zmtarzmTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const {

SDValue zmtarzmTargetLowering :: getStaticTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG , bool UseGOT ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned zmtarzmPCLabelIndex = CFI->createPICLabelUId();

unsigned zmtarzmPCLabelIndex = CFI -> createPICLabelUId ( ) ;


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


zmtarzmCP::zmtarzmCPModifier Flag = UseGOT ? zmtarzmCP::TLSIE : zmtarzmCP::TLSLE;

zmtarzmCP :: zmtarzmCPModifier Flag = UseGOT ? zmtarzmCP :: TLSIE : zmtarzmCP :: TLSLE ;


bool AddCurrentAddr = UseGOT ? true : false;

bool AddCurrentAddr = UseGOT ? true : false ;


unsigned char PCAjust = UseGOT ? 4 : 0 ;


zmtarzmConstantPoolValue *CPV = zmtarzmConstantPoolConstant::Create(N->getGlobal(), zmtarzmCP::CPValue, PCAjust, Flag, AddCurrentAddr, zmtarzmPCLabelIndex);

zmtarzmConstantPoolValue * CPV = zmtarzmConstantPoolConstant :: Create ( N -> getGlobal ( ) , zmtarzmCP :: CPValue , PCAjust , Flag , AddCurrentAddr , zmtarzmPCLabelIndex ) ;


SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty);

SDValue CAddr = DAG . getTargetConstantPool ( CPV , Ty ) ;


SDValue PICLabel = DAG.getTargetConstant(zmtarzmPCLabelIndex, DL, MVT::i32);

SDValue PICLabel = DAG . getTargetConstant ( zmtarzmPCLabelIndex , DL , MVT :: i32 ) ;


auto *LRWGRS = DAG.getMachineNode(zmtarzm::PseudoTLSLA32, DL, {Ty, Ty}, {CAddr, PICLabel});

auto * LRWGRS = DAG . getMachineNode ( zmtarzm :: PseudoTLSLA32 , DL , { Ty , Ty } , { CAddr , PICLabel } ) ;


auto LRWADDGRS = DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));

auto LRWADDGRS = DAG . getNode ( ISD :: ADD , DL , Ty , SDValue ( LRWGRS , 0 ) , SDValue ( LRWGRS , 1 ) ) ;


Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS, MachinePointerInfo(N->getGlobal()));

Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ;


Load = SDValue(DAG.getMachineNode(zmtarzm::LRW32, DL, Ty, CAddr), 0);

Load = SDValue ( DAG . getMachineNode ( zmtarzm :: LRW32 , DL , Ty , CAddr ) , 0 ) ;


SDValue TPReg = DAG.getRegister(zmtarzm::R31, MVT::i32);

SDValue TPReg = DAG . getRegister ( zmtarzm :: R31 , MVT :: i32 ) ;


return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);

return DAG . getNode ( ISD :: ADD , DL , Ty , Load , TPReg ) ;


const zmtarzmSubtarget &getSubtarget() const {

const zmtarzmSubtarget & getSubtarget ( ) const {


const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {

const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


if ((zmtarzmISD::NodeType)Opcode == #) {

if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ALLOCA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ALLOCA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DCFETCH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DCFETCH) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST32_GP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST32_GP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: COMBINE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::COMBINE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALLR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALLR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALLnr ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALLnr) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BARRIER ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BARRIER) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AT_GOT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AT_GOT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AT_PCREL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AT_PCREL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: JT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::JT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INSERT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INSERT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXTRACTU ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXTRACTU) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TSTBIT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TSTBIT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EH_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EH_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VLSR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VLSR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VASR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VASR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VASL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VASL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VALIGNADDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VALIGNADDR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VALIGN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VALIGN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TYPECAST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TYPECAST) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QFALSE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QFALSE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QTRUE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QTRUE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QCAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QCAT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Q2V ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Q2V) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: V2Q ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::V2Q) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: P2D ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::P2D) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: D2P ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::D2P) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VZERO ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VZERO) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: READCYCLE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::READCYCLE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VROR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VROR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VINSERTW0 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VINSERTW0) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VEXTRACTW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VEXTRACTW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VSPLAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VSPLAT) {


const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {

const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {


if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ((zmtarzmISD::NodeType)Opcode == #) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Wrapper ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Wrapper) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RLC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RLC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RRC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RRC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SLA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SLA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SRA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SRA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SRL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SRL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DEC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DEC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ADD ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ADD) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ADC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ADC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SUB ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SUB) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SBC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SBC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: XOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::XOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: OR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::OR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TST) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MLT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MLT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SEXT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SEXT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RETN_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RETN_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RETI_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RETI_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BRCOND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BRCOND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SELECT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SELECT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: POP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::POP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: PUSH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::PUSH) {


bool zmtarzmTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const {

bool zmtarzmTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const {


if ( Intrinsic == Intrinsic :: zmtarzm_ldaxr ) {

if (Intrinsic == Intrinsic::zmtarzm_ldaxr) {


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ;


Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 0 ) ;


Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_ldxr ) {

if (Intrinsic == Intrinsic::zmtarzm_ldxr) {


if ( Intrinsic == Intrinsic :: zmtarzm_stlxr ) {

if (Intrinsic == Intrinsic::zmtarzm_stlxr) {


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 1 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_stxr ) {

if (Intrinsic == Intrinsic::zmtarzm_stxr) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldaxp ) {

if (Intrinsic == Intrinsic::zmtarzm_ldaxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldxp ) {

if (Intrinsic == Intrinsic::zmtarzm_ldxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_stlxp ) {

if (Intrinsic == Intrinsic::zmtarzm_stlxp) {


Info . ptrVal = I . getArgOperand ( 2 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_stxp ) {

if (Intrinsic == Intrinsic::zmtarzm_stxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2) {


uint64_t NumElts = I.getModule()->getDataLayout().getTypeSizeInBits(I.getType()) / 64;

uint64_t NumElts = I . getModule ( ) -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) / 64 ;


Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);

Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ;


Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);

Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x2 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x2) {


EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts )


Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;

Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ;


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x3 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x3) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x4 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x4) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2r) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3r) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4r) {


bool zmtarzmTargetLowering::hasBitPreservingFPLogic(EVT VT) const {

bool zmtarzmTargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const {


return ( VT == MVT :: f32 || VT == MVT :: f64 || VT == MVT :: v4f32 || VT == MVT :: v2f64 ) || Subtarget . hasVSX ( ) || ( Subtarget . hasP9Vector ( ) && VT == MVT :: f128 ) ;

return (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::v4f32 || VT == MVT::v2f64) || Subtarget.hasVSX() || (Subtarget.hasP9Vector() && VT == MVT::f128);


bool zmtarzmTargetLowering::isCheapToSpeculateCtlz() const {

bool zmtarzmTargetLowering :: isCheapToSpeculateCtlz ( ) const {


bool zmtarzmTargetLowering::isCheapToSpeculateCttz() const {

bool zmtarzmTargetLowering :: isCheapToSpeculateCttz ( ) const {


bool zmtarzmTargetLowering::isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const {

bool zmtarzmTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const {


if ( N -> getOpcode ( ) != ISD :: SHL ) {


bool zmtarzmTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector<CCValAssign, 16> &ArgLocs) const {

bool zmtarzmTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const {


if ( ! mayTailCallThisCC ( CalleeCC ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const Function &CallerF = MF.getFunction();

const Function & CallerF = MF . getFunction ( ) ;


CallingConv::ID CallerCC = CallerF.getCallingConv();

CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ;


for (Function::const_arg_iterator i = CallerF.arg_begin(), e = CallerF.arg_end(); i != e; ++i) {

for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) {


if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) {


return canGuaranteeTCO(CalleeCC) && CCMatch;

return canGuaranteeTCO ( CalleeCC ) && CCMatch ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


const Triple &TT = getTargetMachine().getTargetTriple();

const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;


if ( GV -> hasExternalWeakLinkage ( ) ) {


assert((!isVarArg || CalleeCC == CallingConv::C) && "Unexpected variadic calling convention");


LLVMContext & C = * DAG . getContext ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);

CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ;


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ;


for (const CCValAssign &ArgLoc : ArgLocs) {

for ( const CCValAssign & ArgLoc : ArgLocs ) {


if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, CCAssignFnForCall(CalleeCC, isVarArg), CCAssignFnForCall(CallerCC, isVarArg))) {

if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) {


const zmtarzmRegisterInfo *TRI = Subtarget->getRegisterInfo();

const zmtarzmRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ;


const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);

const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ;


const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);

const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;


if ( Subtarget -> hasCustomCallingConv ( ) ) {


TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ;


TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ;


if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) {

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) {


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ;


const zmtarzmFunctionInfo *FuncInfo = MF.getInfo<zmtarzmFunctionInfo>();

const zmtarzmFunctionInfo * FuncInfo = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {

if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) {


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) {

if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) {


if (CCInfo.getInRegsParamsCount() > 0) {

if ( CCInfo . getInRegsParamsCount ( ) > 0 ) {


bool zmtarzmTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector<CCValAssign, 16> &ArgLocs) const {

bool zmtarzmTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const {


if ( ! mayTailCallThisCC ( CalleeCC ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const Function &CallerF = MF.getFunction();

const Function & CallerF = MF . getFunction ( ) ;


CallingConv::ID CallerCC = CallerF.getCallingConv();

CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ;


for (Function::const_arg_iterator i = CallerF.arg_begin(), e = CallerF.arg_end(); i != e; ++i) {

for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) {


if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) {


return canGuaranteeTCO(CalleeCC) && CCMatch;

return canGuaranteeTCO ( CalleeCC ) && CCMatch ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


const Triple &TT = getTargetMachine().getTargetTriple();

const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;


if ( GV -> hasExternalWeakLinkage ( ) ) {


assert((!isVarArg || CalleeCC == CallingConv::C) && "Unexpected variadic calling convention");


LLVMContext & C = * DAG . getContext ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);

CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ;


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ;


for (const CCValAssign &ArgLoc : ArgLocs) {

for ( const CCValAssign & ArgLoc : ArgLocs ) {


if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, CCAssignFnForCall(CalleeCC, isVarArg), CCAssignFnForCall(CallerCC, isVarArg))) {

if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) {


const zmtarzmRegisterInfo *TRI = Subtarget->getRegisterInfo();

const zmtarzmRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ;


const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);

const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ;


const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);

const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;


if ( Subtarget -> hasCustomCallingConv ( ) ) {


TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ;


TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ;


if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) {

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) {


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ;


const zmtarzmFunctionInfo *FuncInfo = MF.getInfo<zmtarzmFunctionInfo>();

const zmtarzmFunctionInfo * FuncInfo = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {

if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) {


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) {

if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) {


if (CCInfo.getInRegsParamsCount() > 0) {

if ( CCInfo . getInRegsParamsCount ( ) > 0 ) {


return NextStackOffset <= FI . getIncomingArgSize ( ) ;

return NextStackOffset <= FI.getIncomingArgSize();


bool zmtarzmTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const {

bool zmtarzmTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const {


if ( VT . getSimpleVT ( ) . SimpleTy == # ) {


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f16 ) {

if (VT.getSimpleVT().SimpleTy == MVT::f16) {


if (VT.getSimpleVT().SimpleTy == MVT::f32) {

if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f32 ) {


if (VT.getSimpleVT().SimpleTy == MVT::f64) {

if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f64 ) {


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: v4f32 ) {

if (VT.getSimpleVT().SimpleTy == MVT::v4f32) {


return Subtarget -> hasMVEFloatOps ( ) ;


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: v8f16 ) {

if (VT.getSimpleVT().SimpleTy == MVT::v8f16) {


return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ;

return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();


bool zmtarzmTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const {

bool zmtarzmTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const {


return zmtarzm_AM::getFP16Imm(Imm) != -1;

return zmtarzm_AM :: getFP16Imm ( Imm ) != - 1 ;


return zmtarzm_AM::getFP32Imm(Imm) != -1;

return zmtarzm_AM :: getFP32Imm ( Imm ) != - 1 ;


return zmtarzm_AM::getFP64Imm(Imm) != -1;

return zmtarzm_AM :: getFP64Imm ( Imm ) != - 1 ;


bool zmtarzmTargetLowering::isLegalAddImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


bool zmtarzmTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {

bool zmtarzmTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const {


if ( ! isInt < # > ( AM . BaseOffs ) ) {


bool zmtarzmTargetLowering::isLegalICmpImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const {


bool zmtarzmTargetLowering::isSExtCheaperThanZExt(EVT VT1, EVT VT2) const {

bool zmtarzmTargetLowering :: isSExtCheaperThanZExt ( EVT VT1 , EVT VT2 ) const {


return Subtarget.is64Bit() && VT1 == MVT::i32 && VT2 == MVT::i64;

return Subtarget . is64Bit ( ) && VT1 == MVT :: i32 && VT2 == MVT :: i64 ;


bool zmtarzmTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {

bool zmtarzmTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const {


unsigned SrcBits = SrcVT.getSizeInBits();

unsigned SrcBits = SrcVT . getSizeInBits ( ) ;


unsigned DestBits = DstVT.getSizeInBits();

unsigned DestBits = DstVT . getSizeInBits ( ) ;


return (SrcBits == 64 && DestBits == 32);

return ( SrcBits == 64 && DestBits == 32 ) ;


bool zmtarzmTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {

bool zmtarzmTargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const {


unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits();

unsigned NumBits1 = SrcTy -> getPrimitiveSizeInBits ( ) ;


unsigned NumBits2 = DstTy->getPrimitiveSizeInBits();

unsigned NumBits2 = DstTy -> getPrimitiveSizeInBits ( ) ;


return NumBits1 == 64 && NumBits2 == 32;


bool zmtarzmTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {

bool zmtarzmTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const {


if (auto *LD = dyn_cast<LoadSDNode>(Val)) {

if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) {


if (LD->getExtensionType() == ISD::NON_EXTLOAD) {

if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) {


if (LD->getExtensionType() == ISD::ZEXTLOAD) {

if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) {


return TargetLowering :: isZExtFree ( Val , VT2 ) ;


void zmtarzmTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const {


char ConstraintLetter = Constraint [ 0 ] ;


if (auto *C = dyn_cast<ConstantSDNode>(Op)) {

if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) {


Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ;


Ops . push_back ( DAG . getTargetConstant ( 0 , DL , XLenVT ) ) ;


TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);

TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


SDValue zmtarzmTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const {


BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);

BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


assert ( VA . getLocVT ( ) == MVT :: f64 ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;