InductionMap::iterator F2 = IndMap.find(CmpReg2);

InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ;


IVOp = MRI -> getVRegDef ( F -> first ) ;


zmtarzmFrepLoops() : MachineFunctionPass(ID) {

zmtarzmFrepLoops ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmFrepLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


explicit FrepLoop ( MachineLoop * ML ) {


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


zmtarzmFrepLoops::Comparison::Kind zmtarzmFrepLoops::getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const {

zmtarzmFrepLoops :: Comparison :: Kind zmtarzmFrepLoops :: getComparisonKind ( unsigned CondOpc , MachineOperand * InitialValue , const MachineOperand * EndValue , int64_t IVBump ) const {


Comparison::Kind Cmp = (Comparison::Kind)0;

Comparison :: Kind Cmp = ( Comparison :: Kind ) 0 ;


if ( CondOpc == zmtarzm :: C2_cmpeqi ) {


if ( CondOpc == zmtarzm :: C4_cmpneq ) {


if ( CondOpc == zmtarzm :: C4_cmplte ) {


if ( CondOpc == zmtarzm :: C2_cmpgtui ) {


if ( CondOpc == zmtarzm :: C2_cmpgti ) {


if ( CondOpc == zmtarzm :: C2_cmpeqp ) {


if ( CondOpc == zmtarzm :: C4_cmpneqi ) {


if ( CondOpc == zmtarzm :: C2_cmpgtu ) {


if ( CondOpc == zmtarzm :: C2_cmpgtup ) {


if ( CondOpc == zmtarzm :: C2_cmpgtp ) {


assert(isImm() && "Wrong CountValue accessor");

assert
(
isImm
(
)
&&
"Wrong CountValue accessor"
)
;


CountValue *zmtarzmFrepLoops::getLoopTripCount(MachineLoop *L, SmallVectorImpl<MachineInstr *> &OldInsts) {

CountValue * zmtarzmFrepLoops :: getLoopTripCount ( MachineLoop * L , SmallVectorImpl < MachineInstr * > & OldInsts ) {


MachineBasicBlock *TopMBB = L->getTopBlock();

MachineBasicBlock * TopMBB = L -> getTopBlock ( ) ;


MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();

MachineBasicBlock :: pred_iterator PI = TopMBB -> pred_begin ( ) ;


assert(PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!");


MachineBasicBlock * Backedge = * PI ++ ;


MachineBasicBlock * Incoming = * PI ++ ;


MachineBasicBlock *ExitingBlock = L -> findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);

bool FoundIV = findInductionRegister ( L , IVReg , IVBump , IVOp ) ;


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineOperand * InitialValue = nullptr ;


MachineInstr *IV_Phi = MRI -> getVRegDef(IVReg);

MachineInstr * IV_Phi = MRI -> getVRegDef ( IVReg ) ;


MachineBasicBlock *Latch = L -> getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


for (unsigned i = 1, n = IV_Phi -> getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


MachineBasicBlock *MBB = IV_Phi->getOperand(i + 1).getMBB();

MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + 1 ) . getMBB ( ) ;


InitialValue = & IV_Phi -> getOperand ( i ) ;


IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ;


SmallVector < MachineOperand , 2 > Cond ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


MachineBasicBlock *Header = L -> getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


assert (TB && "Exit block without a branch?");

assert
(
TB
&&
"Exit block without a branch?"
)
;


SmallVector < MachineOperand , 2 > LCond ;


bool NotAnalyzed = TII -> analyzeBranch(*Latch, LTB, LFB, LCond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ;


assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");

assert
(
(
!
FB
||
TB
==
Header
||
FB
==
Header
)
&&
"Branches not to header?"
)
;


bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);

bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ;


if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) {


MachineInstr *CondI = MRI->getVRegDef(PredReg);

MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ;


unsigned CondOpc = CondI -> getOpcode ( ) ;


bool AnalyzedCmp = TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);

bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ;


const MachineOperand &Op1 = CondI->getOperand(1);

const MachineOperand & Op1 = CondI -> getOperand ( 1 ) ;


const MachineOperand &Op2 = CondI->getOperand(2);

const MachineOperand & Op2 = CondI -> getOperand ( 2 ) ;


const MachineOperand *EndValue = nullptr;

const MachineOperand * EndValue = nullptr ;


Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);

Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ;


Cmp = Comparison :: getNegatedComparison ( Cmp ) ;


Cmp = Comparison :: getSwappedComparison ( Cmp ) ;


unsigned R = InitialValue -> getReg ( ) ;


MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();

MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ;


if (!MDT->properlyDominates(DefBB, Header)) {

if ( ! MDT -> properlyDominates ( DefBB , Header ) ) {


if (!checkForImmediate(*InitialValue, V)) {

if ( ! checkForImmediate ( * InitialValue , V ) ) {


OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ;


if ( ! checkForImmediate ( * EndValue , V ) ) {


return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);

return computeCount ( L , InitialValue , EndValue , IVReg , IVBump , Cmp ) ;


static Kind getNegatedComparison(Kind Cmp) {

static Kind getNegatedComparison ( Kind Cmp ) {


return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


assert(isReg() && "Wrong CountValue accessor");

assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;


static Kind getSwappedComparison(Kind Cmp) {

static Kind getSwappedComparison ( Kind Cmp ) {


assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator");

assert
(
(
!
(
(
Cmp
&
L
)
&&
(
Cmp
&
G
)
)
)
&&
"Malformed comparison operator"
)
;


bool zmtarzmFrepLoops::isDead(const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DeadPhis) const {

bool zmtarzmFrepLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const {


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand &MO = MI->getOperand(i);

const MachineOperand & MO = MI -> getOperand ( i ) ;


if ( MO . isReg ( ) && MO . isDef ( ) ) {


if ( ! MRI -> use_nodbg_empty ( Reg ) ) {


MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);

MachineRegisterInfo :: use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ;


MachineRegisterInfo::use_nodbg_iterator End = MRI->use_nodbg_end();

MachineRegisterInfo :: use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ;


if ( I -> getParent ( ) -> isPHI ( ) ) {


MachineInstr *OnePhi = I.getOperand().getParent();

MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ;


for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {

for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) {


const MachineOperand &OPO = OnePhi->getOperand(j);

const MachineOperand & OPO = OnePhi -> getOperand ( j ) ;


MachineRegisterInfo :: use_nodbg_iterator nextJ ;


for (MachineRegisterInfo::use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J!=End; J=nextJ) {

for ( MachineRegisterInfo :: use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) {


MachineInstr * UseMI = Use . getParent ( ) ;


if ( ! I -> getParent ( ) -> isPHI ( ) ) {


bool zmtarzmFrepLoops::isInvalidLoopOperation(const MachineInstr *MI) const {

bool zmtarzmFrepLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const {


if ( MO . getReg ( ) == zmtarzm :: LC0 ) {


if ( MO . getReg ( ) == zmtarzm :: LC1 ) {


if ( MO . getReg ( ) == zmtarzm :: SA0 ) {


if ( MO . getReg ( ) == zmtarzm :: SA1 ) {


if ( MO . getReg ( ) == zmtarzm :: CTR ) {


if ( MO . getReg ( ) == zmtarzm :: CTR8 ) {


for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand & MO = MI -> getOperand ( i ) ;


return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ;


void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {

void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const {


OS << "register: " << printReg(Contents.R.Reg, TRI, Contents.R.Sub) << '\n';

OS
<<
"register: "
<<
printReg
(
Contents
.
R
.
Reg
,
TRI
,
Contents
.
R
.
Sub
)
<<
'\n'
;


OS << "immediate: " << Contents.ImmVal << '\n';

OS
<<
"immediate: "
<<
Contents
.
ImmVal
<<
'\n'
;


void zmtarzmFrepLoops::removeIfDead(MachineInstr *MI) {

void zmtarzmFrepLoops :: removeIfDead ( MachineInstr * MI ) {


SmallVector<MachineInstr *, 1> DeadPhis;

SmallVector < MachineInstr * , 1 > DeadPhis ;


LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI);

LLVM_DEBUG
(
dbgs
(
)
<<
"HW looping will remove: "
<<
*
MI
)
;


MachineRegisterInfo :: use_iterator nextI ;


for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) {

for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) {


MachineInstr * UseMI = I -> getParent ( ) ;


UseMI -> getOperand ( 0 ) . setReg ( 0U ) ;


for (unsigned i = 0; i < DeadPhis.size(); ++i) {

for ( unsigned i = 0 ; i < DeadPhis . size ( ) ; ++ i ) {


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {


const MachineOperand &MO = MI->getOperand(i);


bool zmtarzmHardwareLoops::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmHardwareLoops :: runOnMachineFunction ( MachineFunction & MF ) {


MLI = & getAnalysis < MachineLoopInfo > ( ) ;


MDT = & getAnalysis < MachineDominatorTree > ( ) ;


TII = MF . getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


Changed = Changed | convertToHardwareLoop(L, L0Used, L1Used);

Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ;


bool enableMachineScheduler() const override {

bool enableMachineScheduler ( ) const override {


const CallLowering *zmtarzmSubtarget::getCallLowering() const {

const CallLowering * zmtarzmSubtarget :: getCallLowering ( ) const {


const zmtarzmFrameLowering *getFrameLowering() const override {

const zmtarzmFrameLowering * getFrameLowering ( ) const override {


const zmtarzmInstrInfo *getInstrInfo() const override {

const zmtarzmInstrInfo * getInstrInfo ( ) const override {


InstructionSelector *zmtarzmSubtarget::getInstructionSelector() const {

InstructionSelector * zmtarzmSubtarget :: getInstructionSelector ( ) const {


const LegalizerInfo *zmtarzmSubtarget::getLegalizerInfo() const {

const LegalizerInfo * zmtarzmSubtarget :: getLegalizerInfo ( ) const {


const RegisterBankInfo *zmtarzmSubtarget::getRegBankInfo() const {

const RegisterBankInfo * zmtarzmSubtarget :: getRegBankInfo ( ) const {


const zmtarzmRegisterInfo *getRegisterInfo() const override {

const zmtarzmRegisterInfo * getRegisterInfo ( ) const override {


const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {

const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


zmtarzmABI :: ABI getTargetABI ( ) const {


const zmtarzmTargetLowering *getTargetLowering() const override {

const zmtarzmTargetLowering * getTargetLowering ( ) const override {


bool hasExtXfauxvecaltquarter ( ) const {


bool hasExtXfexpauxvecalthalf ( ) const {


bool hasExtXfexpauxvecaltquarter() const {

bool hasExtXfexpauxvecaltquarter ( ) const {


bool hasExtXfexpauxvecquarter ( ) const {


zmtarzmSubtarget &zmtarzmSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {

zmtarzmSubtarget & zmtarzmSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) {


CPUName = Is64Bit ? "generic-la64" : "generic-la32";


ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ;


TargetABI = Is64Bit ? zmtarzmABI::ABI_LP64D : zmtarzmABI::ABI_ILP32D;

TargetABI = Is64Bit ? zmtarzmABI :: ABI_LP64D : zmtarzmABI :: ABI_ILP32D ;


bool isRegisterReservedByUser(Register R) const {

bool isRegisterReservedByUser ( Register R ) const {


assert(R < zmtarzm::NUM_TARGET_REGS && "Register out of range");

assert
(
R
<
zmtarzm
::
NUM_TARGET_REGS
&&
"Register out of range"
)
;


zmtarzmSubtarget::zmtarzmSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM) : zmtarzmGenSubtargetInfo(TT, CPU, TuneCPU, FS), UserReservedRegister(zmtarzm::NUM_TARGET_REGS), FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {

zmtarzmSubtarget :: zmtarzmSubtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : zmtarzmGenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , UserReservedRegister ( zmtarzm :: NUM_TARGET_REGS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , TuneCPU , FS , ABIName ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {


CallLoweringInfo . reset ( new zmtarzmCallLowering ( * getTargetLowering ( ) ) ) ;


Legalizer . reset ( new zmtarzmLegalizerInfo ( * this ) ) ;


auto *RBI = new zmtarzmRegisterBankInfo(*getRegisterInfo());

auto * RBI = new zmtarzmRegisterBankInfo ( * getRegisterInfo ( ) ) ;


InstSelector.reset(createzmtarzmInstructionSelector(*static_cast<const zmtarzmTargetMachine*>(&TM), *this, *RBI));

InstSelector . reset ( createzmtarzmInstructionSelector ( * static_cast < const zmtarzmTargetMachine * > ( & TM ) , * this , * RBI ) ) ;


Target & llvm :: getThezmtarzm32Target ( ) {


Target & llvm :: getThezmtarzm64Target ( ) {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetInfo() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetInfo ( ) {


RegisterTarget<Triple::zmtarzm32> X(getThezmtarzm32Target(), "zmtarzm32", "32-bit zmtarzm", "zmtarzm");

RegisterTarget
<
Triple
::
zmtarzm32
>
X
(
getThezmtarzm32Target
(
)
,
"zmtarzm32"
,
"32-bit zmtarzm"
,
"zmtarzm"
)
;


RegisterTarget<Triple::zmtarzm64> Y(getThezmtarzm64Target(), "zmtarzm64", "64-bit zmtarzm", "zmtarzm");

RegisterTarget
<
Triple
::
zmtarzm64
>
Y
(
getThezmtarzm64Target
(
)
,
"zmtarzm64"
,
"64-bit zmtarzm"
,
"zmtarzm"
)
;


bool zmtarzmPassConfig :: addGlobalInstructionSelect ( ) {


bool zmtarzmPassConfig :: addInstSelector ( ) {


addPass ( createzmtarzmISelDag ( getzmtarzmTargetMachine ( ) ) ) ;


void zmtarzmPassConfig :: addIRPasses ( ) {


addPass ( createAtomicExpandPass ( ) ) ;


bool zmtarzmPassConfig :: addIRTranslator ( ) {


addPass ( new IRTranslator ( getOptLevel ( ) ) ) ;


bool zmtarzmPassConfig :: addLegalizeMachineIR ( ) {


void zmtarzmPassConfig :: addPreEmitPass2 ( ) {


addPass ( createzmtarzmExpandPseudoPass ( ) ) ;


addPass ( createzmtarzmExpandAtomicPseudoPass ( ) ) ;


addPass ( createBranchSelectionPass ( ) ) ;


addPass ( createzmtarzmFixupHwLoops ( ) ) ;


void zmtarzmPassConfig :: addPreEmitPass ( ) {


void zmtarzmPassConfig :: addPreSched2 ( ) {


bool zmtarzmPassConfig :: addRegBankSelect ( ) {


static StringRef computeDataLayout(const Triple &TT) {

static StringRef computeDataLayout ( const Triple & TT ) {


assert(TT.isArch32Bit() && "only LA32 and LA64 are currently supported");


if ( TT . getVendor ( ) == Triple :: r600 ) {


TargetPassConfig *TargetMachine::createPassConfig(PassManagerBase &PM) {

TargetPassConfig * TargetMachine :: createPassConfig ( PassManagerBase & PM ) {


return new zmtarzmPassConfig(*this, PM);

return new zmtarzmPassConfig ( * this , PM ) ;


static Reloc::Model getEffectiveRelocModel(const Triple &TT, Optional<Reloc::Model> RM) {

static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) {


TargetLoweringObjectFile *getObjFileLowering() const override {

TargetLoweringObjectFile * getObjFileLowering ( ) const override {


const zmtarzmSubtarget *zmtarzmTargetMachine::getSubtargetImpl(const Function &F) const {

const zmtarzmSubtarget * zmtarzmTargetMachine :: getSubtargetImpl ( const Function & F ) const {


Attribute TuneAttr = F.getFnAttribute("tune-cpu");

Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ;


Attribute CPUAttr = F.getFnAttribute("target-cpu");

Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ;


Attribute FSAttr = F.getFnAttribute("target-features");

Attribute FSAttr = F . getFnAttribute ( "target-features" ) ;


std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;

std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ;


std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;

std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ;


std :: string Key = CPU + TuneCPU + FS ;


auto ABIName = Options.MCOptions.getABIName();

auto ABIName = Options . MCOptions . getABIName ( ) ;


if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(F.getParent()->getModuleFlag("target-abi"))) {

if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( "target-abi" ) ) ) {


auto TargetABI = zmtarzmABI::getTargetABI(ABIName);

auto TargetABI = zmtarzmABI :: getTargetABI ( ABIName ) ;


if (TargetABI != zmtarzmABI::ABI_Unknown) {

if ( TargetABI != zmtarzmABI :: ABI_Unknown ) {


if (ModuleTargetABI->getString() != ABIName) {

if ( ModuleTargetABI -> getString ( ) != ABIName ) {


ABIName = ModuleTargetABI -> getString ( ) ;


I = std::make_unique<zmtarzmSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);

I = std :: make_unique < zmtarzmSubtarget > ( TargetTriple , CPU , TuneCPU , FS , ABIName , * this ) ;


std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ;

std::string TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;


report_fatal_error("-target-abi option != target-abi module flag");


zmtarzmTargetMachine &getzmtarzmTargetMachine() const {

zmtarzmTargetMachine & getzmtarzmTargetMachine ( ) const {


return getTM < zmtarzmTargetMachine > ( ) ;


TargetTransformInfo zmtarzmTargetMachine::getTargetTransformInfo(const Function &F) {

TargetTransformInfo zmtarzmTargetMachine :: getTargetTransformInfo ( const Function & F ) {


return TargetTransformInfo ( zmtarzmTTIImpl ( this , F ) ) ;


bool zmtarzmTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {

bool zmtarzmTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTarget() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTarget ( ) {


RegisterTargetMachine < zmtarzmTargetMachine > X ( getThezmtarzmTarget ( ) ) ;


RegisterTargetMachine < zmtarzmTargetMachine > X ( getThezmtarzm32Target ( ) ) ;


RegisterTargetMachine < zmtarzmTargetMachine > Y ( getThezmtarzm64Target ( ) ) ;


auto *PR = PassRegistry::getPassRegistry();

auto * PR = PassRegistry :: getPassRegistry ( ) ;


initializezmtarzmExpandPseudoPass ( * PR ) ;


initializezmtarzmRelaxMemPass ( * PR ) ;


initializezmtarzmModuleAnalysisPass ( * PR ) ;


zmtarzmPassConfig(zmtarzmTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) {

zmtarzmPassConfig ( zmtarzmTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


void zmtarzmTargetMachine::setTargetOptionsWithModuleMetadata(const Module &M LLVM_ATTRIBUTE_UNUSED) {

void zmtarzmTargetMachine :: setTargetOptionsWithModuleMetadata ( const Module & M LLVM_ATTRIBUTE_UNUSED ) {


constexpr StringLiteral DeadKeys[] = {ValVerKey};

constexpr StringLiteral DeadKeys [ ] = { ValVerKey } ;


SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ;


M . getModuleFlagsMetadata ( ModuleFlags ) ;


NamedMDNode *MDFlags = M.getModuleFlagsMetadata();

NamedMDNode * MDFlags = M . getModuleFlagsMetadata ( ) ;


StringRef Key = Flag . Key -> getString ( ) ;


M . addModuleFlag ( Flag . Behavior , Key , Flag . Val ) ;


zmtarzmTargetMachine::zmtarzmTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique<TargetObjectFile>()), Subtarget(TT, CPU, FS, *this) {

zmtarzmTargetMachine :: zmtarzmTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


void zmtarzmELFTargetObjectFile::getModuleMetadata(Module &M) {

void zmtarzmELFTargetObjectFile :: getModuleMetadata ( Module & M ) {


MCSection *zmtarzmELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const {

MCSection * zmtarzmELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const {


if ( isConstantInSmallSection ( DL , C ) ) {


return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment);

return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ;


void zmtarzmELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {

void zmtarzmELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {


TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


InitializeELF ( TM . Options . UseInitArray ) ;


SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


this->TM = &static_cast<const zmtarzmTargetMachine &>(TM);

this -> TM = & static_cast < const zmtarzmTargetMachine & > ( TM ) ;


bool zmtarzmELFTargetObjectFile::isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const {

bool zmtarzmELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const {


return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ;


bool zmtarzmTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const {

bool zmtarzmTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const {


return TM.getCodeModel() == CodeModel::Small;

return TM . getCodeModel ( ) == CodeModel :: Small ;


return isGlobalInSmallSectionImpl ( GO , TM ) ;


if ( GO -> hasAvailableExternallyLinkage ( ) ) {


return isGlobalInSmallSection(GO, TM, getKindForGlobal(GO, TM));

return isGlobalInSmallSection ( GO , TM , getKindForGlobal ( GO , TM ) ) ;


bool zmtarzmELFTargetObjectFile::isInSmallSection(uint64_t Size) const {

bool zmtarzmELFTargetObjectFile :: isInSmallSection ( uint64_t Size ) const {


return Size > 0 && Size <= SSThreshold ;


MCSection *zmtarzmELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


if ( isGlobalInSmallSection ( GO , TM ) ) {


return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM);

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


void zmtarzmTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {

void zmtarzmTargetStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) {


void zmtarzmTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {

void zmtarzmTargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) {


OS << # << Attribute << # << Twine(Value) << #;

OS << # << Attribute << # << Twine ( Value ) << # ;

OS
<<
"\t.csky_attribute\t"
<<
Attribute
<<
", "
<<
Twine
(
Value
)
<<
"\n"
;

"\t.csky_attribute\t" zmsplit ", " zmsplit "\n"

OS << "\t.csky_attribute\t" << Attribute << ", " << Twine(Value) << "\n";


OS
<<
"\t.hsa_code_object_version "
<<
Attribute
<<
","
<<
Twine
(
Value
)
<<
'\n'
;

"\t.hsa_code_object_version " zmsplit "," zmsplit '\n'

OS << "\t.hsa_code_object_version " << Attribute << "," << Twine(Value) << '\n';


void zmtarzmTargetStreamer :: emitDirectiveOptionNoPIC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionNoRelax ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoRelax ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionNoRVC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoRVC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPIC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPIC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPop ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPop ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPush ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPush ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionRelax ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionRelax ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionRVC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionRVC ( ) {


void zmtarzmTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {

void zmtarzmTargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


void zmtarzmTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {

void zmtarzmTargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


void zmtarzmTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {

void zmtarzmTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) {


ArchID = zmtarzm :: parseCPUArch ( CPU ) ;


if (ArchID == zmtarzm::ArchKind::CK804) {

if ( ArchID == zmtarzm :: ArchKind :: CK804 ) {


CPU_ARCH = zmtarzm :: getArchName ( ArchID ) ;


if (ArchID == zmtarzm::ArchKind::INVALID) {

if ( ArchID == zmtarzm :: ArchKind :: INVALID ) {


emitTextAttribute ( zmtarzmAttrs :: zmtarzm_ARCH_NAME | zm - split | CPU_ARCH , zmtarzmAttrs :: zmtarzm_ARCH_NAME | zm - split | CPU_ARCH ) ;

emitTextAttribute ( zmtarzmAttrs :: zmtarzm_ARCH_NAME , CPU_ARCH ) ;


emitTextAttribute ( zmtarzmAttrs :: zmtarzm_CPU_NAME | zm - split | CPU , zmtarzmAttrs :: zmtarzm_CPU_NAME | zm - split | CPU ) ;

emitTextAttribute ( zmtarzmAttrs :: zmtarzm_CPU_NAME , CPU ) ;


if ( STI . hasFeature ( zmtarzm :: HasE1 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_E1;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_E1 ;


if ( STI . hasFeature ( zmtarzm :: HasE2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_1E2 ;


if ( STI . hasFeature ( zmtarzm :: Has2E3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_2E3;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_2E3 ;


if ( STI . hasFeature ( zmtarzm :: HasMP ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_MP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_MP ;


if ( STI . hasFeature ( zmtarzm :: Has3E3r1 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R1;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R1 ;


if ( STI . hasFeature ( zmtarzm :: Has3r1E3r2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R2;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R2 ;


if ( STI . hasFeature ( zmtarzm :: Has3r2E3r3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R3;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R3 ;


if ( STI . hasFeature ( zmtarzm :: Has3E7 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E7;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E7 ;


if ( STI . hasFeature ( zmtarzm :: HasMP1E2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_MP_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_MP_1E2 ;


if ( STI . hasFeature ( zmtarzm :: Has7E10 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_7E10;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_7E10 ;


if ( STI . hasFeature ( zmtarzm :: Has10E60 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_10E60;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_10E60 ;


if ( STI . hasFeature ( zmtarzm :: FeatureTrust ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_TRUST;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_TRUST ;


if ( STI . hasFeature ( zmtarzm :: FeatureJAVA ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_JAVA;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_JAVA ;


if ( STI . hasFeature ( zmtarzm :: FeatureCache ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_CACHE;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_CACHE ;


if ( STI . hasFeature ( zmtarzm :: FeatureNVIC ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_NVIC;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_NVIC ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSP ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP ;


if ( STI . hasFeature ( zmtarzm :: HasDSP1E2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_1E2 ;


if ( STI . hasFeature ( zmtarzm :: HasDSPE60 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_DSPE60;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_DSPE60 ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSPV2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_ENHANCE;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_ENHANCE ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSP_Silan ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_SILAN;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_SILAN ;


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV1_128 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP ;


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2 ;


if ( STI . hasFeature ( zmtarzm :: HasVDSP2E3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2E3;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2E3 ;


if ( STI . hasFeature ( zmtarzm :: HasVDSP2E60F ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2E60F;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2E60F ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_FLAGS | zm - split | ISAFlag , zmtarzmAttrs :: zmtarzm_ISA_FLAGS | zm - split | ISAFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_FLAGS , ISAFlag ) ;

zmtarzmAttrs :: zmtarzm_ISA_FLAGS ISAFlag


if ( STI . hasFeature ( zmtarzm :: HasFLOATE1 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_E1;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_E1 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT1E2 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_1E2;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_1E2 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT1E3 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_1E3;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_1E3 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT3E4 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_3E4;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_3E4 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT7E60 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_7E60;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_7E60 ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS | zm - split | ISAExtFlag , zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS | zm - split | ISAExtFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS , ISAExtFlag ) ;

zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS ISAExtFlag


if ( STI . hasFeature ( zmtarzm :: FeatureDSP ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_EXTENSION , zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_EXTENSION ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION , zmtarzmAttrs :: DSP_VERSION_EXTENSION ) ;

zmtarzmAttrs :: zmtarzm_DSP_VERSION zmtarzmAttrs :: DSP_VERSION_EXTENSION


if ( STI . hasFeature ( zmtarzm :: FeatureDSPV2 ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_2 , zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION , zmtarzmAttrs :: DSP_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_DSP_VERSION zmtarzmAttrs :: DSP_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV2 ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_VDSP_VERSION | zm - split | zmtarzmAttrs :: VDSP_VERSION_2 , zmtarzmAttrs :: zmtarzm_VDSP_VERSION | zm - split | zmtarzmAttrs :: VDSP_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_VDSP_VERSION , zmtarzmAttrs :: VDSP_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_VDSP_VERSION zmtarzmAttrs :: VDSP_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV2_SF ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_2 , zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION , zmtarzmAttrs :: FPU_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_FPU_VERSION zmtarzmAttrs :: FPU_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV2_DF ) ) {


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_HF ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_3 , zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_3 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION , zmtarzmAttrs :: FPU_VERSION_3 ) ;

zmtarzmAttrs :: zmtarzm_FPU_VERSION zmtarzmAttrs :: FPU_VERSION_3


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_SF ) ) {


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_DF ) ) {


hasAnyFloatExt = STI.hasFeature(zmtarzm::FeatureFPUV2_SF) || STI.hasFeature(zmtarzm::FeatureFPUV2_DF) ||  STI.hasFeature(zmtarzm::FeatureFPUV3_HF) || STI.hasFeature(zmtarzm::FeatureFPUV3_SF) || STI.hasFeature(zmtarzm::FeatureFPUV3_DF);

hasAnyFloatExt = STI . hasFeature ( zmtarzm :: FeatureFPUV2_SF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV2_DF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_HF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_SF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_DF ) ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_ABI | zm - split | zmtarzmAttrs :: FPU_ABI_SOFTFP , zmtarzmAttrs :: zmtarzm_FPU_ABI | zm - split | zmtarzmAttrs :: FPU_ABI_SOFTFP ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_ABI , zmtarzmAttrs :: FPU_ABI_SOFTFP ) ;

zmtarzmAttrs :: zmtarzm_FPU_ABI zmtarzmAttrs :: FPU_ABI_SOFTFP


if ( ! STI . hasFeature ( zmtarzm :: ModeHardFloat ) ) {


if ( ! STI . hasFeature ( zmtarzm :: ModeHardFloatABI ) ) {


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_HALF;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_HALF ;


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_SINGLE;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_SINGLE ;


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_DOUBLE;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_DOUBLE ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_DENORMAL | zm - split | zmtarzmAttrs :: NEEDED , zmtarzmAttrs :: zmtarzm_FPU_DENORMAL | zm - split | zmtarzmAttrs :: NEEDED ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_DENORMAL , zmtarzmAttrs :: NEEDED ) ;

zmtarzmAttrs :: zmtarzm_FPU_DENORMAL zmtarzmAttrs :: NEEDED


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION | zm - split | zmtarzmAttrs :: NEEDED , zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION | zm - split | zmtarzmAttrs :: NEEDED ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION , zmtarzmAttrs :: NEEDED ) ;

zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION zmtarzmAttrs :: NEEDED


emitTextAttribute
(
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
|
zm
split
|
"IEEE 754"
,
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
|
zm
split
|
"IEEE 754"
)
;

emitTextAttribute
(
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
,
"IEEE 754"
)
;

zmtarzmAttrs::zmtarzm_FPU_NUMBER_MODULE zmsplit "IEEE 754"

zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
"IEEE 754"


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_HARDFP | zm - split | HardFPFlag , zmtarzmAttrs :: zmtarzm_FPU_HARDFP | zm - split | HardFPFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_HARDFP , HardFPFlag ) ;

zmtarzmAttrs :: zmtarzm_FPU_HARDFP HardFPFlag


void zmtarzmTargetStreamer::emitTextAttribute(unsigned Attribute, StringRef String) {

void zmtarzmTargetStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


void zmtarzmTargetAsmStreamer::emitTextAttribute(unsigned Attribute, StringRef String) {

void zmtarzmTargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


OS << # << Attribute << # << String << #;

OS << # << Attribute << # << String << # ;

OS
<<
"\t.csky_attribute\t"
<<
Attribute
<<
", \""
<<
String
<<
"\"\n"
;

"\t.csky_attribute\t" zmsplit ", \"" zmsplit "\"\n"

OS << "\t.csky_attribute\t" << Attribute << ", \"" << String << "\"\n";


OS
<<
"\t.import_module\t"
<<
Attribute
<<
", "
<<
String
<<
'\n'
;

"\t.import_module\t" zmsplit ", " zmsplit '\n'

OS << "\t.import_module\t" << Attribute << ", " << String << '\n';


void zmtarzmTargetStreamer :: finishAttributeSection ( ) {


void zmtarzmTargetAsmStreamer :: finishAttributeSection ( ) {


void zmtarzmTargetStreamer :: finish ( ) {


zmtarzmTargetAsmStreamer::zmtarzmTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : zmtarzmTargetStreamer(S), OS(OS) {

zmtarzmTargetAsmStreamer :: zmtarzmTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : zmtarzmTargetStreamer ( S ) , OS ( OS ) {


zmtarzmTargetStreamer::zmtarzmTargetStreamer(MCStreamer &S)  : MCTargetStreamer(S) {

zmtarzmTargetStreamer :: zmtarzmTargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


int zmtarzmTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) {

int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers");


unsigned Ty->getPrimitiveSizeInBits() = Ty->getPrimitiveSizeInBits();

unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if (Ty->getPrimitiveSizeInBits() == 0) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() > 64) {

if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {

if (Opcode == Instruction::GetElementPtr) {


if (Ty->getPrimitiveSizeInBits() == 8) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


int NumConstants = divideCeil(Ty->getPrimitiveSizeInBits(), 64);

int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if (getIntImmCost(Imm, Ty, CostKind) <= NumConstants * TTI::TCC_Basic) {

if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost(Imm, Ty, CostKind);

return getIntImmCost ( Imm , Ty , CostKind ) ;


if (Imm.getZExtValue() == 0x100000000ULL) {

if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() <= 32) {

if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( Opcode == Instruction :: Select ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


int zmtarzmTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


return BaseT :: getIntImmCostIntrin ( IID , Idx , Imm , Ty , CostKind ) ;

return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);

return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if (IID == Intrinsic::sadd_with_overflow) {

if ( IID == Intrinsic :: sadd_with_overflow ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < # > ( - Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::uadd_with_overflow) {

if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: zmtarzm_sadd_with_overflow ) {

if (IID == Intrinsic::zmtarzm_sadd_with_overflow) {


if ( IID == Intrinsic :: zmtarzm_uadd_with_overflow ) {

if (IID == Intrinsic::zmtarzm_uadd_with_overflow) {


if ( IID == Intrinsic :: zmtarzm_ssub_with_overflow ) {

if (IID == Intrinsic::zmtarzm_ssub_with_overflow) {


if ( isUInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: zmtarzm_usub_with_overflow ) {

if (IID == Intrinsic::zmtarzm_usub_with_overflow) {


if (IID == Intrinsic::experimental_stackmap) {

if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if (IID == Intrinsic::experimental_patchpoint_void) {

if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if (IID == Intrinsic::experimental_patchpoint_i64) {

if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


int zmtarzmTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {

if ((Imm.getZExtValue() & 0xffffffff) == 0) {


const zmtarzmSubtarget * getST ( ) const {


const zmtarzmTargetLowering *getTLI() const {

const zmtarzmTargetLowering * getTLI ( ) const {


bool zmtarzmTTIImpl::isLoweredToCall(const Function *F) {

bool zmtarzmTTIImpl :: isLoweredToCall ( const Function * F ) {


if ( F -> getName ( ) . startswith ( "llvm.zmtarzm_lower" ) ) {


bool zmtarzmTTIImpl::shouldFavorPostInc() const {

bool zmtarzmTTIImpl :: shouldFavorPostInc ( ) const {


explicit zmtarzmTTIImpl(const zmtarzmTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {

explicit zmtarzmTTIImpl ( const zmtarzmTargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


zmtarzmMCAsmInfo::zmtarzmMCAsmInfo(const Target &T, StringRef TT) {

zmtarzmMCAsmInfo :: zmtarzmMCAsmInfo ( const Target & T , StringRef TT ) {


explicit zmtarzmAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {

explicit zmtarzmAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {


void zmtarzmAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock *MBB) {

void zmtarzmAsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock * MBB ) {


AsmPrinter :: EmitBasicBlockStart ( MBB ) ;


OutStreamer
->
EmitRawText
(
StringRef
(
"\t.pragma \"nounroll\";\n"
)
)
;


void zmtarzmAsmPrinter :: EmitConstantPool ( ) {


const MachineConstantPool *MCP = MF->getConstantPool();

const MachineConstantPool * MCP = MF -> getConstantPool ( ) ;


const std::vector<MachineConstantPoolEntry> &CP = MCP->getConstants();

const std :: vector < MachineConstantPoolEntry > & CP = MCP -> getConstants ( ) ;


zmtarzmTargetMachine &TTM = static_cast<zmtarzmTargetMachine &>(TM);

zmtarzmTargetMachine & TTM = static_cast < zmtarzmTargetMachine & > ( TM ) ;


const std::vector<MachineConstantPoolEntry> &CP = TTM.MCP.getConstants();

const std :: vector < MachineConstantPoolEntry > & CP = TTM . MCP . getConstants ( ) ;


const MCSection *S = TM.getTargetLowering()->getObjFileLowering().getDataSection();

const MCSection * S = TM . getTargetLowering ( ) -> getObjFileLowering ( ) . getDataSection ( ) ;


for (unsigned i = 0, e = CP.size(); i != e; ++i) {

for ( unsigned i = 0 , e = CP . size ( ) ; i != e ; ++ i ) {


const MachineConstantPoolEntry &CPE = CP[i];

const MachineConstantPoolEntry & CPE = CP [ i ] ;


unsigned Align = CPE . getAlignment ( ) ;


unsigned AlignMask = CPE.getAlignment() - 1;

unsigned AlignMask = CPE . getAlignment ( ) - 1 ;


unsigned NewOffset = (Offset + AlignMask) & ~AlignMask;

unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ;


OS << "\tstring\tbyte[" << (NewOffset - Offset) << "] 0\n";

OS
<<
"\tstring\tbyte["
<<
(
NewOffset
Offset
)
<<
"] 0\n"
;


Offset = NewOffset + TM.getDataLayout()->getTypeAllocSize(Ty);

Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ;


MCSymbol * Symbol = GetCPISymbol ( i ) ;


HackStreamer ( OutStreamer ) << OS . str ( ) ;


if ( CPE . isMachineConstantPoolEntry ( ) ) {


EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ;


EmitGlobalConstant ( CPE . Val . ConstVal ) ;


MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();

MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ;


zmtarzmTargetStreamer &TTS = static_cast<zmtarzmTargetStreamer &>(TS);

zmtarzmTargetStreamer & TTS = static_cast < zmtarzmTargetStreamer & > ( TS ) ;


TTS . EmitConstantPoolEntry ( CP [ cpi ++ ] ) ;


void zmtarzmAsmPrinter :: EmitConstantPool ( ) {


const MachineConstantPool * MCP = MF -> getConstantPool ( ) ;


const std :: vector < MachineConstantPoolEntry > & CP = MCP -> getConstants ( ) ;


zmtarzmTargetMachine & TTM = static_cast < zmtarzmTargetMachine & > ( TM ) ;


const std :: vector < MachineConstantPoolEntry > & CP = TTM . MCP . getConstants ( ) ;


const MCSection * S = TM . getTargetLowering ( ) -> getObjFileLowering ( ) . getDataSection ( ) ;


for ( unsigned i = 0 , e = CP . size ( ) ; i != e ; ++ i ) {


const MachineConstantPoolEntry & CPE = CP [ i ] ;


unsigned Align = CPE . getAlignment ( ) ;


unsigned AlignMask = CPE . getAlignment ( ) - 1 ;


unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ;


OS
<<
"\tstring\tbyte["
<<
(
NewOffset
Offset
)
<<
"] 0\n"
;


Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ;


MCSymbol * Symbol = GetCPISymbol ( i ) ;


HackStreamer ( OutStreamer ) << OS . str ( ) ;


if ( CPE . isMachineConstantPoolEntry ( ) ) {


EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ;


EmitGlobalConstant ( CPE . Val . ConstVal ) ;


MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ;


zmtarzmTargetStreamer & TTS = static_cast < zmtarzmTargetStreamer & > ( TS ) ;


TTS . EmitConstantPoolEntry ( CP [ cpi ++ ] ) ;


void zmtarzmAsmPrinter::EmitEndOfAsmFile(Module &M) {

void zmtarzmAsmPrinter :: EmitEndOfAsmFile ( Module & M ) {


if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) {


const TargetLoweringObjectFile &TLOF = getObjFileLowering();

const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ;


OutStreamer . SwitchSection ( TLOF . getTextSection ( ) ) ;


MCSymbol *EndOfTextLabel = OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));

MCSymbol * EndOfTextLabel = OutContext . GetOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ;


OutStreamer . EmitLabel ( EndOfTextLabel ) ;


void zmtarzmAsmPrinter :: EmitFunctionEntryLabel ( ) {


getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ;


OutStreamer . EmitLabel ( CurrentFnSym ) ;


void zmtarzmAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {

void zmtarzmAsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) {


zmtarzmoldTargetStreamer *TS = static_cast<zmtarzmoldTargetStreamer *>(OutStreamer->getTargetStreamer());

zmtarzmoldTargetStreamer * TS = static_cast < zmtarzmoldTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ;


if (GVSym->isDefined() || GVSym->isVariable()) {

if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) {


report_fatal_error("symbol '" + Twine(GVSym->getName()) + "' is already defined");

report_fatal_error
(
"symbol '"
+
Twine
(
GVSym
->
getName
(
)
)
+
"' is already defined"
)
;


SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);

SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ;


MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));

MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ;


GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ;


SectionKind GVKind = getObjFileLowering().getKindForGlobal(GV, TM);

SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ;


if ((!GVKind.isCommon() && !GVKind.isBSS() && !GVKind.isData() &&!GVKind.isReadOnly()) || GVKind.isMergeable2ByteCString() || GVKind.isMergeable4ByteCString()) {

if ( ( ! GVKind . isCommon ( ) && ! GVKind . isBSS ( ) && ! GVKind . isData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) {


report_fatal_error("Encountered a global variable kind that is not supported yet.");


MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(getObjFileLowering().SectionForGlobal(GV, GVKind, TM));

MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ;


OutStreamer -> SwitchSection ( Csect ) ;


const DataLayout &DL = GV->getParent()->getDataLayout();

const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;


uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());

uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ;


unsigned Align = DL.getPreferredAlignment(GV);

unsigned Align = DL . getPreferredAlignment ( GV ) ;


MCSection *TheSection = getObjFileLowering().SectionForGlobal(GV, GVKind, TM);

MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ;


OutStreamer -> SwitchSection ( TheSection ) ;


EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ;


if (GVKind.isCommon() || GVKind.isBSSLocal()) {

if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) {


unsigned Align = GV->getAlignment() ? GV->getAlignment() : DL.getPreferredAlignment(GV);

unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ;


OutStreamer->EmitXCOFFLocalCommonSymbol(GVSym, Size, Csect->getQualNameSymbol(), Align);

OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ;


OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ;


EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ;


OutStreamer -> EmitLabel ( EmittedInitSym ) ;


EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ;


void zmtarzmAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {

void zmtarzmAsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) {


zmtarzmoldTargetStreamer *TS = static_cast<zmtarzmoldTargetStreamer *>(OutStreamer->getTargetStreamer());

zmtarzmoldTargetStreamer * TS = static_cast < zmtarzmoldTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ;


if (GVSym->isDefined() || GVSym->isVariable()) {

if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) {


report_fatal_error("symbol '" + Twine(GVSym->getName()) + "' is already defined");

report_fatal_error
(
"symbol '"
+
Twine
(
GVSym
->
getName
(
)
)
+
"' is already defined"
)
;


SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);

SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ;


MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));

MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ;


GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ;


SectionKind GVKind = getObjFileLowering().getKindForGlobal(GV, TM);

SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ;


if ((!GVKind.isCommon() && !GVKind.isBSS() && !GVKind.isData() &&!GVKind.isReadOnly()) || GVKind.isMergeable2ByteCString() || GVKind.isMergeable4ByteCString()) {

if ( ( ! GVKind . isCommon ( ) && ! GVKind . isBSS ( ) && ! GVKind . isData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) {


report_fatal_error("Encountered a global variable kind that is not supported yet.");


MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(getObjFileLowering().SectionForGlobal(GV, GVKind, TM));

MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ;


OutStreamer -> SwitchSection ( Csect ) ;


const DataLayout &DL = GV->getParent()->getDataLayout();

const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;


uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());

uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ;


unsigned Align = DL.getPreferredAlignment(GV);

unsigned Align = DL . getPreferredAlignment ( GV ) ;


MCSection *TheSection = getObjFileLowering().SectionForGlobal(GV, GVKind, TM);

MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ;


OutStreamer -> SwitchSection ( TheSection ) ;


EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ;


if (GVKind.isCommon() || GVKind.isBSSLocal()) {

if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) {


unsigned Align = GV->getAlignment() ? GV->getAlignment() : DL.getPreferredAlignment(GV);

unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ;


OutStreamer->EmitXCOFFLocalCommonSymbol(GVSym, Size, Csect->getQualNameSymbol(), Align);

OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ;


OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ;


EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ;


OutStreamer -> EmitLabel ( EmittedInitSym ) ;


EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ;


void zmtarzmAsmPrinter::EmitInstruction(const MachineInstr *MI) {

void zmtarzmAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {


if (emitPseudoExpansionLowering(*OutStreamer, MI)) {

if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) {


LowerzmtarzmMachineInstrToMCInst ( MI , TmpInst , * this ) ;


EmitToStreamer ( * OutStreamer , TmpInst ) ;


void zmtarzmAsmPrinter::emitStartOfAsmFile(Module &M) {

void zmtarzmAsmPrinter :: emitStartOfAsmFile ( Module & M ) {


OutStreamer -> emitAssemblerFlag ( MCAF_SyntaxUnified ) ;


if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) {


if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) {


if ( TM . getTargetTriple ( ) . isThumb ( ) ) {


OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ;


void getAnalysisUsage(AnalysisUsage &AU) const {

void getAnalysisUsage ( AnalysisUsage & AU ) const {


AU . addRequired < zmtarzmMetadata > ( ) ;


MachineLocation zmtarzmAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {

MachineLocation zmtarzmAsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const {


assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");

assert
(
MI
->
getNumOperands
(
)
==
4
&&
"Invalid no. of machine operands!"
)
;


assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && "Unexpected MachineOperand types");

assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
"Unexpected MachineOperand types"
)
;


return MachineLocation ( MI -> getOperand ( 0 ) . getReg ( ) , MI -> getOperand ( 1 ) . getImm ( ) ) ;


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


extern "C" void LLVMInitializezmtarzmAsmPrinter() {

extern "C" void LLVMInitializezmtarzmAsmPrinter ( ) {


RegisterAsmPrinter < zmtarzmAsmPrinter > X ( ThezmtarzmTarget ) ;


bool zmtarzmAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) {

bool zmtarzmAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) {


bool zmtarzmAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) {

bool zmtarzmAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) {


void zmtarzmInstPrinter::printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) {

void zmtarzmInstPrinter :: printInlineJT32 ( const MCInst * MI , int opNum , raw_ostream & O ) {


report_fatal_error
(
"can't handle InlineJT32"
)
;


void zmtarzmInstPrinter::printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) {

void zmtarzmInstPrinter :: printInlineJT ( const MCInst * MI , int opNum , raw_ostream & O ) {


report_fatal_error
(
"can't handle InlineJT"
)
;


void zmtarzmAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {

void zmtarzmAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) {


if (MI->getOperand(opNum + 1).isImm() && MI->getOperand(opNum + 1).getImm() == 0) {

if ( MI -> getOperand ( opNum + 1 ) . isImm ( ) && MI -> getOperand ( opNum + 1 ) . getImm ( ) == 0 ) {


void zmtarzmAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {

void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand &MO = MI->getOperand(OpNo);

const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if (MO.getType() == MachineOperand::MO_Register) {

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if (MO.getType() == MachineOperand::MO_Immediate) {

if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if (MO.getType() == MachineOperand::MO_MachineBasicBlock) {

if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if (MO.getType() == MachineOperand::MO_GlobalAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if (MO.getType() == MachineOperand::MO_ConstantPoolIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if (MO.getType() == MachineOperand::MO_BlockAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if (MO.getType() == MachineOperand::MO_JumpTableIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter::PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Code) const {

void zmtarzmAsmPrinter :: PrintSpecial ( const MCInst * MI , raw_ostream & O , const char * Code ) const {


assert ( strcmp ( Code , "arguments" ) == 0 ) ;


for (unsigned i = 0; i < MI->getNumOperands() - 1; i++) {

for ( unsigned i = 0 ; i < MI -> getNumOperands ( ) - 1 ; i ++ ) {


bool zmtarzmAsmPrinter::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) {


NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


void zmtarzmFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineBasicBlock::iterator MBBI = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . end ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


LastFrameDestroy = std::prev(MBBI, CSI.size());

LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ;


uint64_t StackSize = MFI.getStackSize();

uint64_t StackSize = MFI . getStackSize ( ) ;


uint64_t ActualSize = CFI->getCalleeSaveAreaSize() + CFI->getVarArgsSaveSize();

uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ;


BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg).addReg(FPReg).setMIFlag(MachineInstr::NoFlags);

BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ;


adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize), MachineInstr::FrameDestroy);

adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize, MachineInstr::FrameDestroy);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ;


if (materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDrr ) , zmtarzm :: SP ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


if (!materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( ! materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI(MBB, MBBI, DL, TII.get(zmtarzm::ADDri), zmtarzm::SP).addReg(StackReg).addImm(StackSize).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDri ) , zmtarzm :: SP ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


void zmtarzmFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const RegisterInfo *RI = STI.getRegisterInfo();

const RegisterInfo * RI = STI . getRegisterInfo ( ) ;


MachineFunctionInfo *CFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


MachineBasicBlock::iterator MBBI = MBB.begin();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ;


const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: NIE ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::NIE));


uint64_t StackSize = MFI . getStackSize ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


unsigned spillAreaSize = CFI->getCalleeSaveAreaSize();

unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ;


uint64_t ActualSize = spillAreaSize + CFI->getVarArgsSaveSize();

uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, ActualSize));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


std :: advance ( MBBI , CSI . size ( ) ) ;


int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());

int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ;


unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;

unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ;


for ( unsigned i = 0 ; i < Num ; i ++ ) {


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, RI->getDwarfRegNum(Reg, true) + i, Offset + i * 4));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RI->getDwarfRegNum(FPReg, true)));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(StackSize - ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


const zmtarzmRegisterInfo *RI = STI.getRegisterInfo();

const zmtarzmRegisterInfo * RI = STI . getRegisterInfo ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


Align MaxAlignment = MFI . getMaxAlign ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: ANDNI32 ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::ANDNI32), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));


unsigned ShiftAmount = Log2(MaxAlignment);

unsigned ShiftAmount = Log2 ( MaxAlignment ) ;


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::GPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI32 ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI32), VR).addReg(SPReg).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI32 ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI32), SPReg).addReg(VR).addImm(ShiftAmount);


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::mGPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: mGPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , VR ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), VR).addReg(SPReg);


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , SPReg ) . addReg ( VR ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), SPReg).addReg(VR);


if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), BPReg).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , BPReg ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , BPReg ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), BPReg).addReg(SPReg);


adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, #, #), STI(STI) {

zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , # , # ) , STI ( STI ) {

zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( 1 ) , - 2 ) , STI ( STI ) {

zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(1), -2), STI(STI) {


zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , 8 , 0 ) , STI ( STI ) {

zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(STI) {


bool zmtarzmFrameLowering::hasFP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasFP ( const MachineFunction & MF ) const {


return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();

return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


bool zmtarzmFrameLowering::isShrinkWrappingProfitable() const {

bool zmtarzmFrameLowering :: isShrinkWrappingProfitable ( ) const {


void zmtarzmFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const {

void zmtarzmFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const {


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( # ) ;

MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R0 ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R1 ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R2 ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetRegisterClass *RC = &zmtarzm::R32CRegClass;

const TargetRegisterClass * RC = & zmtarzm :: R32CRegClass ;


RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


zmtarzmFunctionInfo *FI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * FI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


CallingConv::ID CallConv = MF.getFunction()->getCallingConv();

CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ;


bool requiresRA = CallConv == CallingConv::MBLAZE_INTR;

bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ;


if (MFI->adjustsStack() || requiresRA) {

if ( MFI -> adjustsStack ( ) || requiresRA ) {


MFI -> CreateFixedObject ( 4 , 0 , true ) ;


MFI -> CreateFixedObject ( 4 , 4 , true ) ;


void zmtarzmFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) const {

void zmtarzmFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


bool zmtarzmFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);

TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg()).addReg(zmtarzm::R15);

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg());

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: POP ) , CSI [ i ] . getReg ( ) ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::POP), CSI[i].getReg());


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSHRr ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSHRr)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {