MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
16
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 16 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PHAstk ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PHAstk)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {

bool zmtarzmInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) {


const char *zmtarzmInstPrinter::getRegisterName(unsigned RegNo) {

const char * zmtarzmInstPrinter :: getRegisterName ( unsigned RegNo ) {


return getRegisterName ( RegNo , NoRegAltName ) ;


return getRegisterName ( RegNo , ArchRegNames ? zmtarzm :: NoRegAltName : zmtarzm :: ABIRegAltName ) ;

return getRegisterName(RegNo, ArchRegNames ? zmtarzm::NoRegAltName : zmtarzm::ABIRegAltName);


return getRegisterName ( RegNo , RegAliasName ) ;


zmtarzmInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {

zmtarzmInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


void zmtarzmInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printAtomicMemOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


OS
<<
", 0x"
<<
zmtarzm_ez_int2hex
(
Offset
)
;

OS << ", 0x" << zmtarzm_ez_int2hex(Offset);


void zmtarzmInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS) {

void zmtarzmInstPrinter :: printBranchOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS ) {


const MCOperand &MO = MI->getOperand(OpNo);

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


return printOperand ( MI , OpNo , STI , OS ) ;


if ( ! STI . hasFeature ( zmtarzm :: Feature64Bit ) ) {


void zmtarzmInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printCSRSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


Val = MI -> getOperand ( OpNo ) . getImm ( ) ;


if (Val == zmtarzmSysReg::DBGDTRRX_EL0) {

if ( Val == zmtarzmSysReg :: DBGDTRRX_EL0 ) {


Reg = SysReg :: lookupSysRegByEncoding ( Val ) ;


if ( Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) {


OS << SysReg :: genericRegisterString ( Val ) ;


if ( ! Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) {


void zmtarzmInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printFenceArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


unsigned FenceArg = MI->getOperand(OpNo).getImm();

unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ;


assert
(
FenceArg
<=
7
&&
"Invalid xopcc argument!"
)
;

assert(FenceArg <= 7 && "Invalid xopcc argument!");


if ( FenceArg == zmtarzm :: ExceptRef ) {


void zmtarzmInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printFRMArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


auto FRMArg = MI->getOperand(OpNo).getImm();

auto FRMArg = MI -> getOperand ( OpNo ) . getImm ( ) ;


OS << FPRndMode :: roundingModeToString ( MO . getImm ( ) ) ;


void zmtarzmInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) {


if ( ! printAliasInstr ( MI , STI , O ) ) {


printInstruction(NewMI, Address, STI, O);

printInstruction ( NewMI , Address , STI , O ) ;


if (!printAliasInstr(NewMI, Address, STI, O)) {

if ( ! printAliasInstr ( NewMI , Address , STI , O ) ) {


void zmtarzmInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,  const MCSubtargetInfo &STI, raw_ostream &OS, const char *Modifier) {

void zmtarzmInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS , const char * Modifier ) {


assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");

assert
(
(
Modifier
==
0
||
Modifier
[
0
]
==
0
)
&&
"No modifiers supported"
)
;


const MCOperand &Op = MI->getOperand(OpNo);

const MCOperand & Op = MI -> getOperand ( OpNo ) ;


OS << getRegisterName ( Op . getReg ( ) ) ;


assert(Op.isExpr() && "Unknown operand kind in printOperand");

assert
(
Op
.
isExpr
(
)
&&
"Unknown operand kind in printOperand"
)
;


Op . getExpr ( ) -> print ( OS , & MAI ) ;


void zmtarzmInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {

void zmtarzmInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {


void zmtarzmInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) {

void zmtarzmInstPrinter :: printVMaskReg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


OS
<<
", 0x"
<<
zmtarzm_ez_int2hex
(
Offset
)
;

OS << ", 0x" << zmtarzm_ez_int2hex(Offset);


void zmtarzmInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, raw_ostream &O) {

void zmtarzmInstPrinter :: printVTypeI ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;


zmtarzmVType :: printVType ( Imm , O ) ;


bool zmtarzmInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {

bool zmtarzmInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const {


MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();

MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ;


if ( ! isUnpredicatedTerminator ( * I ) ) {


MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();

MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ;


for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); J++) {

for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) {


if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) {


FirstUncondOrIndirectBr = J . getReverse ( ) ;


if ( J -> getDesc ( ) . isIndirectBranch ( ) ) {


if (FirstUncondOrIndirectBr != MBB.end()) {

if ( FirstUncondOrIndirectBr != MBB . end ( ) ) {


for(; std::next(FirstUncondOrIndirectBr) != MBB.end();) {

for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) {


std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ;


if ( I -> getDesc ( ) . isIndirectBranch ( ) ) {


if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


if ( I -> getDesc ( ) . isConditionalBranch ( ) ) {


if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) {


parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ;


bool zmtarzmInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const {

bool zmtarzmInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const {


assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");

assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;


assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");

assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;


if ( MIa . hasUnmodeledSideEffects ( ) ) {


if ( MIb . hasUnmodeledSideEffects ( ) ) {


const TargetRegisterInfo *TRI = STI.getRegisterInfo();

const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;


const MachineOperand *BaseOpA = nullptr;

const MachineOperand * BaseOpA = nullptr ;


const MachineOperand *BaseOpB = nullptr;

const MachineOperand * BaseOpB = nullptr ;


if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI)) {

if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) ) {


if (getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {

if ( getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) {


if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) {


int LowOffset = std::min(OffsetA, OffsetB);

int LowOffset = std :: min ( OffsetA , OffsetB ) ;


int HighOffset = std::max(OffsetA, OffsetB);

int HighOffset = std :: max ( OffsetA , OffsetB ) ;


int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;

int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;


if (LowOffset + LowWidth <= HighOffset) {

if ( LowOffset + LowWidth <= HighOffset ) {


void zmtarzmInstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const {

void zmtarzmInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const {


if (OF.FrameConstructionID == MachineOutlinerThunk) {

if ( OF . FrameConstructionID == MachineOutlinerThunk ) {


MachineInstr *Call = &*--MBB.instr_end();

MachineInstr * Call = & * -- MBB . instr_end ( ) ;


bool isThumb = Subtarget . isThumb ( ) ;


unsigned Opc = Call->getOperand(FuncOp).isReg() ? isThumb ? zmtarzm::tTAILJMPr : zmtarzm::TAILJMPr : isThumb ? Subtarget.isTargetMachO() ? zmtarzm::tTAILJMPd  : zmtarzm::tTAILJMPdND : zmtarzm::TAILJMPd;

unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? zmtarzm :: tTAILJMPr : zmtarzm :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? zmtarzm :: tTAILJMPd : zmtarzm :: tTAILJMPdND : zmtarzm :: TAILJMPd ;


MachineInstrBuilder MIB = BuildMI(MBB, MBB.end(), DebugLoc(), get(Opc)).add(Call->getOperand(FuncOp));

MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ;


if ( ! Call -> getOperand ( FuncOp ) . isReg ( ) ) {


MIB . add ( predOps ( zmtarzmCC :: AL ) ) ;


if (llvm::any_of(MBB.instrs(), IsNonTailCall)) {

if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) {


MachineBasicBlock::iterator It = MBB.begin();

MachineBasicBlock :: iterator It = MBB . begin ( ) ;


MachineBasicBlock::iterator Et = MBB.end();

MachineBasicBlock :: iterator Et = MBB . end ( ) ;


if (OF.FrameConstructionID == MachineOutlinerTailCall) {

if ( OF . FrameConstructionID == MachineOutlinerTailCall ) {


if ( ! MBB . isLiveIn ( zmtarzm :: LR ) ) {


assert
(
OF
.
FrameConstructionID
!=
MachineOutlinerDefault
&&
"Can only fix up stack references once"
)
;

assert(OF.FrameConstructionID != MachineOutlinerDefault && "Can only fix up stack references once");


emitCFIForLRRestoreFromStack ( MBB , Et ) ;


BuildMI(MBB, MBB.end(), DebugLoc(), get(Subtarget.getReturnOpcode())).add(predOps(#));

BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( # ) ) ;

BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( zmtarzmCC :: AL ) ) ;

BuildMI(MBB, MBB.end(), DebugLoc(), get(Subtarget.getReturnOpcode())).add(predOps(zmtarzmCC::AL));


if (OF.FrameConstructionID != MachineOutlinerDefault) {

if ( OF . FrameConstructionID != MachineOutlinerDefault ) {


if (OF.Candidates[0].CallConstructionID != MachineOutlinerDefault) {

if ( OF . Candidates [ 0 ] . CallConstructionID != MachineOutlinerDefault ) {


MachineInstr *retq = BuildMI(MF, DebugLoc(), get(zmtarzm::RET64));

MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( zmtarzm :: RET64 ) ) ;


void zmtarzmInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const {


if ( OF . FrameConstructionID == MachineOutlinerThunk ) {


MachineInstr * Call = & * -- MBB . instr_end ( ) ;


bool isThumb = Subtarget . isThumb ( ) ;


unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? zmtarzm :: tTAILJMPr : zmtarzm :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? zmtarzm :: tTAILJMPd : zmtarzm :: tTAILJMPdND : zmtarzm :: TAILJMPd ;


MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ;


if ( ! Call -> getOperand ( FuncOp ) . isReg ( ) ) {


MIB . add ( predOps ( zmtarzmCC :: AL ) ) ;


if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) {


MachineBasicBlock :: iterator It = MBB . begin ( ) ;


MachineBasicBlock :: iterator Et = MBB . end ( ) ;


if ( OF . FrameConstructionID == MachineOutlinerTailCall ) {


if ( ! MBB . isLiveIn ( zmtarzm :: LR ) ) {


emitCFIForLRRestoreFromStack ( MBB , Et ) ;


BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( # ) ) ;

BuildMI(MBB, MBB.end(), DebugLoc(), get(Subtarget.getReturnOpcode())).add(predOps(#));


if ( OF . FrameConstructionID != MachineOutlinerDefault ) {


if ( OF . Candidates [ 0 ] . CallConstructionID != MachineOutlinerDefault ) {


MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( zmtarzm :: RET64 ) ) ;


void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {

void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {


if ( # . contains ( DstReg , SrcReg ) ) {

if ( zmtarzm :: GPRRegClass . contains ( DstReg , SrcReg ) ) {

if (zmtarzm::GPRRegClass.contains(DstReg, SrcReg)) {


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( # . contains ( DestReg , SrcReg ) ) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( zmtarzm :: GR16RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR16RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOV16rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MOV16rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOV8rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MOV8rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GPRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GPRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: G8RCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::G8RCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR8 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR8), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: F4RCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::F4RCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: FMR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::FMR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: CRRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::CRRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MCRF ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MCRF), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


if ( zmtarzm :: VRRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::VRRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: VOR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::VOR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: CRBITRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::CRBITRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: CROR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::CROR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {

void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( zmtarzm :: GR64RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR64RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV64rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV64rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR32RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR32RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV32rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV32rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR64PRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR64PRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV64rrP ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV64rrP), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR128RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR128RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV128rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV128rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: FP32RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::FP32RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: FMOV32rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::FMOV32rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: FP64RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::FP64RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: FMOV64rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::FMOV64rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {

void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( # . contains ( DestReg , SrcReg ) ) {


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


if ( zmtarzm :: IntRegsRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::IntRegsRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: OR ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::OR), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));


std::pair<unsigned, unsigned> zmtarzmInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {

std :: pair < unsigned , unsigned > zmtarzmInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const {


const unsigned Mask = zmtarzmII :: MO_FRAGMENT ;

const unsigned Mask = zmtarzmII::MO_FRAGMENT;


return std::make_pair(TF & Mask, TF & ~Mask);

return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;


const unsigned Mask = zmtarzmII :: MO_MASK ;

const unsigned Mask = zmtarzmII::MO_MASK;


const unsigned Mask = zmtarzmII :: MO_OPTION_MASK ;

const unsigned Mask = zmtarzmII::MO_OPTION_MASK;


MachineBasicBlock *zmtarzmInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {

MachineBasicBlock * zmtarzmInstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const {


assert(MI.getDesc().isBranch() && "Unexpected opcode!");

assert
(
MI
.
getDesc
(
)
.
isBranch
(
)
&&
"Unexpected opcode!"
)
;


return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();

return MI . getOperand ( MI . getNumExplicitOperands ( ) - 1 ) . getMBB ( ) ;


unsigned zmtarzmInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {

unsigned zmtarzmInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const {


const MachineBasicBlock &MBB = *MI.getParent();

const MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();

const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Opcode == TargetOpcode :: INLINEASM ) {

if (Opcode == TargetOpcode::INLINEASM) {


const MachineFunction *MF = MI->getParent()->getParent();

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const char *AsmStr = MI->getOperand(0).getSymbolName();

const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


return MI -> getDesc ( ) . getSize ( ) ;


assert(StackMapOpers(&MI).getNumPatchBytes() % 4 == 0 && "Invalid number of NOP bytes requested!");


return StackMapOpers ( & MI ) . getNumPatchBytes ( ) ;


assert(PatchPointOpers(&MI).getNumPatchBytes() % 4 == 0 && "Invalid number of NOP bytes requested!");


return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ;


const MachineFunction *MF = MI.getParent()->getParent();

const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


const char *AsmStr = MI.getOperand(0).getSymbolName();

const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ;


return MI . getOperand ( 1 ) . getImm ( ) ;


return MI . getOperand ( 2 ) . getImm ( ) ;


unsigned zmtarzmInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const {


const MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: INLINEASM ) {

if (MI.getOpcode() == zmtarzm::INLINEASM) {


return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Opcode == TargetOpcode :: DBG_VALUE ) {

if (Opcode == TargetOpcode::DBG_VALUE) {


const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


return MI -> getDesc ( ) . getSize ( ) ;


if ( Opcode == TargetOpcode :: EH_LABEL ) {


if ( Opcode == TargetOpcode :: IMPLICIT_DEF ) {

if (Opcode == TargetOpcode::IMPLICIT_DEF) {


if ( Opcode == TargetOpcode :: STACKMAP ) {


"Invalid number of NOP bytes requested!"


return StackMapOpers ( & MI ) . getNumPatchBytes ( ) ;


if ( Opcode == TargetOpcode :: PATCHPOINT ) {

if (Opcode == TargetOpcode::PATCHPOINT) {


return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ;


if ( Opcode == zmtarzm :: TLSDESC_CALLSEQ ) {

if (Opcode == zmtarzm::TLSDESC_CALLSEQ) {


if ( Opcode == zmtarzm :: JumpTableDest32 ) {

if (Opcode == zmtarzm::JumpTableDest32) {


const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ;


if ( Opcode == zmtarzm :: JumpTableDest16 ) {

if (Opcode == zmtarzm::JumpTableDest16) {


if ( Opcode == zmtarzm :: JumpTableDest8 ) {

if (Opcode == zmtarzm::JumpTableDest8) {


return MI . getOperand ( 1 ) . getImm ( ) ;


return MI . getOperand ( 2 ) . getImm ( ) ;


unsigned zmtarzmInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const {

unsigned zmtarzmInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {


const MachineBasicBlock & MBB = * MI . getParent ( ) ;

const MachineBasicBlock &MBB = *MI.getParent();


const MachineFunction * MF = MBB . getParent ( ) ;

const MachineFunction *MF = MBB.getParent();


const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;

const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();


return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;

const MachineFunction *MF = MI->getParent()->getParent();


const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;

const char *AsmStr = MI->getOperand(0).getSymbolName();


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


return MI -> getDesc ( ) . getSize ( ) ;


assert(StackMapOpers(&MI).getNumPatchBytes() % 4 == 0 && "Invalid number of NOP bytes requested!");


return StackMapOpers ( & MI ) . getNumPatchBytes ( ) ;


assert(PatchPointOpers(&MI).getNumPatchBytes() % 4 == 0 && "Invalid number of NOP bytes requested!");


return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ;


const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;

const MachineFunction *MF = MI.getParent()->getParent();


const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ;

const char *AsmStr = MI.getOperand(0).getSymbolName();


if ( Opcode == zmtarzm :: INLINEASM_BR ) {


if ( Opcode == TargetOpcode :: STACKMAP ) {


if ( Opcode == TargetOpcode :: PATCHPOINT ) {


return MI . getOperand ( 1 ) . getImm ( ) ;


return MI . getOperand ( 2 ) . getImm ( ) ;


unsigned zmtarzmInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const {


const MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


return MI -> getDesc ( ) . getSize ( ) ;


"Invalid number of NOP bytes requested!"


return StackMapOpers ( & MI ) . getNumPatchBytes ( ) ;


return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ;


const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ;


if ( Opcode == TargetOpcode :: INLINEASM ) {

if (Opcode == TargetOpcode::INLINEASM) {


if ( Opcode == zmtarzm :: CONSTPOOL_ENTRY ) {

if (Opcode == zmtarzm::CONSTPOOL_ENTRY) {


return MI . getOperand ( 1 ) . getImm ( ) ;


return MI . getOperand ( 2 ) . getImm ( ) ;


bool zmtarzmInstrInfo::getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const {

bool zmtarzmInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const {


if (LdSt.getNumExplicitOperands() != 3) {

if ( LdSt . getNumExplicitOperands ( ) != 3 ) {


if ( ! LdSt . getOperand ( 2 ) . isImm ( ) ) {


if ( ! LdSt . getOperand ( 1 ) . isReg ( ) ) {


Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ;


Offset = LdSt . getOperand ( 2 ) . getImm ( ) ;


outliner::OutlinedFunction zmtarzmInstrInfo::getOutliningCandidateInfo(std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {

outliner :: OutlinedFunction zmtarzmInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const {


MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();

MachineBasicBlock :: iterator MBBI = RepeatedSequenceLocs [ 0 ] . front ( ) ;


for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx(); Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {

for ( unsigned Loc = RepeatedSequenceLocs [ 0 ] . getStartIdx ( ) ; Loc < RepeatedSequenceLocs [ 0 ] . getEndIdx ( ) + 1 ; Loc ++ ) {


for (outliner::Candidate &C : RepeatedSequenceLocs) {

for ( outliner :: Candidate & C : RepeatedSequenceLocs ) {


std::vector<MCCFIInstruction> CFIInstructions = C.getMF()->getFrameInstructions();

std :: vector < MCCFIInstruction > CFIInstructions = C . getMF ( ) -> getFrameInstructions ( ) ;


if (CFICount != CFIInstructions.size()) {

if ( CFICount != CFIInstructions . size ( ) ) {


return outliner :: OutlinedFunction ( ) ;


if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) {


C . setCallInfo ( MachineOutlinerTailCall , 1 ) ;


return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 0,MachineOutlinerTailCall);

return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 0 , MachineOutlinerTailCall ) ;


C . setCallInfo ( MachineOutlinerDefault , 1 ) ;


return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1, MachineOutlinerDefault);

return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 1 , MachineOutlinerDefault ) ;


outliner::InstrType zmtarzmInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const {

outliner :: InstrType zmtarzmInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const {


MachineBasicBlock *MBB = MI.getParent();

MachineBasicBlock * MBB = MI . getParent ( ) ;


const TargetRegisterInfo *TRI = MBB->getParent()->getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ;


return MachineOutlinerInstrType :: Invisible ;


return MachineOutlinerInstrType :: Legal ;


if ( MI . getParent ( ) -> succ_empty ( ) ) {


return MachineOutlinerInstrType :: Illegal ;


if (MI.modifiesRegister(OpcodeRSP, &RI)) {

if ( MI . modifiesRegister ( OpcodeRSP , & RI ) ) {


if ( MI . readsRegister ( OpcodeRSP , & RI ) ) {


if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRSP ) ) {


if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRSP ) ) {


if ( MI . readsRegister ( OpcodeRIP , & RI ) ) {


if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRIP ) ) {


if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRIP ) ) {


for (const MachineOperand &MOP : MI.operands()) {

for ( const MachineOperand & MOP : MI . operands ( ) ) {


ArrayRef<std::pair<unsigned, const char *>> zmtarzmInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {


static const std::pair<unsigned, const char *> TargetFlags[] = #;

static const std :: pair < unsigned , const char * > TargetFlags [ ] = # ;

static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PAGE , "aarch64-page" } , { MO_PAGEOFF , "aarch64-pageoff" } , { MO_G3 , "aarch64-g3" } , { MO_G2 , "aarch64-g2" } , { MO_G1 , "aarch64-g1" } , { MO_G0 , "aarch64-g0" } , { MO_HI12 , "aarch64-hi12" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{MO_PAGE, "aarch64-page"}, {MO_PAGEOFF, "aarch64-pageoff"},{MO_G3, "aarch64-g3"}, {MO_G2, "aarch64-g2"},{MO_G1, "aarch64-g1"}, {MO_G0, "aarch64-g0"},{MO_HI12, "aarch64-hi12"}};


static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOTPCREL , "amdgpu-gotprel" } , { MO_GOTPCREL32_LO , "amdgpu-gotprel32-lo" } , { MO_GOTPCREL32_HI , "amdgpu-gotprel32-hi" } , { MO_REL32_LO , "amdgpu-rel32-lo" } , { MO_REL32_HI , "amdgpu-rel32-hi" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{ MO_GOTPCREL, "amdgpu-gotprel" },{ MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" },{ MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" },{ MO_REL32_LO, "amdgpu-rel32-lo" },{ MO_REL32_HI, "amdgpu-rel32-hi" }};


static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { 1 , "lanai-hi" } , { 2 , "lanai-lo" } , { 3 , "lanai-nf" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{1, "lanai-hi"},{2, "lanai-lo"},{3, "lanai-nf"}};


static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_ABS_HI , "lanai-hi" } , { MO_ABS_LO , "lanai-lo" } , { MO_NO_FLAG , "lanai-nf" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{MO_ABS_HI, "lanai-hi"}, {MO_ABS_LO, "lanai-lo"}, {MO_NO_FLAG, "lanai-nf"}};


static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_ABSOLUTE_ADDRESS , "m68k-absolute" } , { MO_PC_RELATIVE_ADDRESS , "m68k-pcrel" } , { MO_GOT , "m68k-got" } , { MO_GOTOFF , "m68k-gotoff" } , { MO_GOTPCREL , "m68k-gotpcrel" } , { MO_PLT , "m68k-plt" } } ;

static const std::pair<unsigned, const char *> TargetFlags[] = {{MO_ABSOLUTE_ADDRESS, "m68k-absolute"}, {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"}, {MO_GOT, "m68k-got"}, {MO_GOTOFF, "m68k-gotoff"}, {MO_GOTPCREL, "m68k-gotpcrel"}, {MO_PLT, "m68k-plt"}};


static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_ABS_HI , "m88k-abs-hi" } , { MO_ABS_LO , "m88k-abs-lo" } , } ;

static const std::pair<unsigned, const char *> TargetFlags[] = { {MO_ABS_HI, "m88k-abs-hi"}, {MO_ABS_LO, "m88k-abs-lo"}, };


unsigned zmtarzmInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {

unsigned zmtarzmInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const {


assert(TBB && "insertBranch must not be told to insert a fallthrough");


assert((Cond.size() == 3 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(TBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( TBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(TBB);


*BytesAdded = *BytesAdded + getInstSizeInBytes(MI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ;


unsigned Opc = Cond [ 0 ] . getImm ( ) ;


MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);

MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ;


*BytesAdded = *BytesAdded + getInstSizeInBytes(CondMI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ;


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(FBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( FBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(FBB);


assert((Cond.size() == 2 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(TBB);


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(FBB);


unsigned zmtarzmInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const {

unsigned zmtarzmInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const {


assert(RS && "RegScavenger required for long branching");


assert(MBB.empty() && "new block should be inserted for expanding unconditional branch");


MachineFunction * MF = MBB . getParent ( ) ;


MachineRegisterInfo &MRI = MF->getRegInfo();

MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;


unsigned PCReg = MRI.createVirtualRegister(&zmtarzm::SReg_64RegClass);

unsigned PCReg = MRI . createVirtualRegister ( & zmtarzm :: SReg_64RegClass ) ;


Register ScratchReg = MRI.createVirtualRegister(&zmtarzm::GPRRCRegClass);

Register ScratchReg = MRI . createVirtualRegister ( & zmtarzm :: GPRRCRegClass ) ;


MachineInstr *GetPC = BuildMI(MBB, I, DL, get(zmtarzm::S_GETPC_B64), PCReg);

MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( zmtarzm :: S_GETPC_B64 ) , PCReg ) ;


BuildMI(MBB, I, DL, get(zmtarzm::PseudoJump)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_FORWARD);

BuildMI ( MBB , I , DL , get ( zmtarzm :: PseudoJump ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_FORWARD ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: S_ADD_U32 ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_FORWARD ) ;

BuildMI(MBB, I, DL, get(zmtarzm::S_ADD_U32)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_FORWARD);


BuildMI(MBB, I, DL, get(#)).addReg(PCReg, RegState::Define, zmtarzm::sub1).addReg(PCReg, 0, zmtarzm::sub1).addImm(0);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub1 ) . addReg ( PCReg , 0 , zmtarzm :: sub1 ) . addImm ( 0 ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: S_ADDC_U32 ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub1 ) . addReg ( PCReg , 0 , zmtarzm :: sub1 ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(zmtarzm::S_ADDC_U32)).addReg(PCReg, RegState::Define, zmtarzm::sub1).addReg(PCReg, 0, zmtarzm::sub1).addImm(0);


BuildMI ( & MBB , DL , get ( # ) ) . addReg ( PCReg ) ;

BuildMI ( & MBB , DL , get ( zmtarzm :: S_SETPC_B64 ) ) . addReg ( PCReg ) ;


unsigned Scav = RS->scavengeRegisterBackwards(zmtarzm::SReg_64RegClass, MachineBasicBlock::iterator(GetPC), false, 0);

unsigned Scav = RS -> scavengeRegisterBackwards ( zmtarzm :: SReg_64RegClass , MachineBasicBlock :: iterator ( GetPC ) , false , 0 ) ;


BuildMI(MBB, I, DL, get(#)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_BACKWARD);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_BACKWARD ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: S_SUB_U32 ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_BACKWARD ) ;

BuildMI(MBB, I, DL, get(zmtarzm::S_SUB_U32)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_BACKWARD);


BuildMI ( MBB , I , DL , get ( zmtarzm :: S_SUBB_U32 ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub1 ) . addReg ( PCReg , 0 , zmtarzm :: sub1 ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(zmtarzm::S_SUBB_U32)).addReg(PCReg, RegState::Define, zmtarzm::sub1).addReg(PCReg, 0, zmtarzm::sub1).addImm(0);


BuildMI(MBB, I, DL, get(#)).addReg(ScratchReg, RegState::Define | RegState::Dead).addReg(zmtarzm::R0).addMBB(&NewDestBB, zmtarzmII::MO_ABS_HI);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addReg ( zmtarzm :: R0 ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_HI ) ;


BuildMI(MBB, I, DL, get(#)).addReg(ScratchReg).addReg(ScratchReg).addMBB(&NewDestBB, zmtarzmII::MO_ABS_LO);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_LO ) ;


MachineInstr *MI = BuildMI(MBB, I, DL, get(zmtarzm::JMP)).addReg(ScratchReg);

MachineInstr * MI = BuildMI ( MBB , I , DL , get ( zmtarzm :: JMP ) ) . addReg ( ScratchReg ) ;


unsigned Scav = RS->scavengeRegisterBackwards(zmtarzm::GPRRCRegClass, MI->getIterator(), false, 0);

unsigned Scav = RS -> scavengeRegisterBackwards ( zmtarzm :: GPRRCRegClass , MI -> getIterator ( ) , false , 0 ) ;


assert(Scav != zmtarzm::NoRegister && "No register is scavenged!");

assert
(
Scav
!=
zmtarzm
::
NoRegister
&&
"No register is scavenged!"
)
;


MRI . replaceRegWith ( ScratchReg , Scav ) ;


unsigned zmtarzmInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const {

unsigned zmtarzmInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const {


assert(RS && "RegScavenger required for long branching");


assert(MBB.empty() && "new block should be inserted for expanding unconditional branch");


MachineFunction * MF = MBB . getParent ( ) ;


MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;

MachineRegisterInfo &MRI = MF->getRegInfo();


unsigned PCReg = MRI . createVirtualRegister ( & zmtarzm :: SReg_64RegClass ) ;

unsigned PCReg = MRI.createVirtualRegister(&zmtarzm::SReg_64RegClass);


Register ScratchReg = MRI . createVirtualRegister ( & zmtarzm :: GPRRCRegClass ) ;

Register ScratchReg = MRI.createVirtualRegister(&zmtarzm::GPRRCRegClass);


MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( zmtarzm :: S_GETPC_B64 ) , PCReg ) ;

MachineInstr *GetPC = BuildMI(MBB, I, DL, get(zmtarzm::S_GETPC_B64), PCReg);


BuildMI ( MBB , I , DL , get ( zmtarzm :: PseudoJump ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_FORWARD ) ;

BuildMI(MBB, I, DL, get(zmtarzm::PseudoJump)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_FORWARD);


BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub1 ) . addReg ( PCReg , 0 , zmtarzm :: sub1 ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(#)).addReg(PCReg, RegState::Define, zmtarzm::sub1).addReg(PCReg, 0, zmtarzm::sub1).addImm(0);


BuildMI ( & MBB , DL , get ( # ) ) . addReg ( PCReg ) ;


unsigned Scav = RS -> scavengeRegisterBackwards ( zmtarzm :: SReg_64RegClass , MachineBasicBlock :: iterator ( GetPC ) , false , 0 ) ;

unsigned Scav = RS->scavengeRegisterBackwards(zmtarzm::SReg_64RegClass, MachineBasicBlock::iterator(GetPC), false, 0);


BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( PCReg , RegState :: Define , zmtarzm :: sub0 ) . addReg ( PCReg , 0 , zmtarzm :: sub0 ) . addMBB ( & DestBB , zmtarzm :: TF_LONG_BRANCH_BACKWARD ) ;

BuildMI(MBB, I, DL, get(#)).addReg(PCReg, RegState::Define, zmtarzm::sub0).addReg(PCReg, 0, zmtarzm::sub0).addMBB(&DestBB, zmtarzm::TF_LONG_BRANCH_BACKWARD);


BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addReg ( zmtarzm :: R0 ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_HI ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: ORriu ) ) . addReg ( ScratchReg , RegState :: Define | RegState :: Dead ) . addReg ( zmtarzm :: R0 ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_HI ) ;

BuildMI(MBB, I, DL, get(zmtarzm::ORriu)).addReg(ScratchReg, RegState::Define | RegState::Dead).addReg(zmtarzm::R0).addMBB(&NewDestBB, zmtarzmII::MO_ABS_HI);


BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_LO ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: ORri ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addMBB ( & NewDestBB , zmtarzmII :: MO_ABS_LO ) ;

BuildMI(MBB, I, DL, get(zmtarzm::ORri)).addReg(ScratchReg).addReg(ScratchReg).addMBB(&NewDestBB, zmtarzmII::MO_ABS_LO);


MachineInstr * MI = BuildMI ( MBB , I , DL , get ( zmtarzm :: JMP ) ) . addReg ( ScratchReg ) ;


unsigned Scav = RS -> scavengeRegisterBackwards ( zmtarzm :: GPRRCRegClass , MI -> getIterator ( ) , false , 0 ) ;


assert
(
Scav
!=
zmtarzm
::
NoRegister
&&
"No register is scavenged!"
)
;


MRI . replaceRegWith ( ScratchReg , Scav ) ;


MachineBasicBlock::iterator zmtarzmInstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const {

MachineBasicBlock :: iterator zmtarzmInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const {


It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(zmtarzm::JMP_1)).addGlobalAddress(M.getNamedValue(MF.getName())));

It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( zmtarzm :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ;


It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(zmtarzm::CALL64pcrel32)).addGlobalAddress(M.getNamedValue(MF.getName())));

It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( zmtarzm :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ;


zmtarzmInstrInfo::zmtarzmInstrInfo(zmtarzmSubtarget &STI) : zmtarzmGenInstrInfo( zmtarzm::ADJCALLSTACKDOWN, zmtarzm::ADJCALLSTACKUP), STI(STI) {

zmtarzmInstrInfo :: zmtarzmInstrInfo ( zmtarzmSubtarget & STI ) : zmtarzmGenInstrInfo ( zmtarzm :: ADJCALLSTACKDOWN , zmtarzm :: ADJCALLSTACKUP ) , STI ( STI ) {


bool zmtarzmInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {

bool zmtarzmInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const {


const unsigned Opcode = MI . getOpcode ( ) ;


return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() ==zmtarzm::ZERO);

return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: ZERO ) ;


bool zmtarzmInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {

bool zmtarzmInstrInfo :: isBranchOffsetInRange ( unsigned BranchOpc , int64_t BrOffset ) const {


llvm_unreachable
(
"Unexpected opcode!"
)
;


Optional<DestSourcePair> zmtarzmInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {

Optional < DestSourcePair > zmtarzmInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ;


if ( MI . getOperand ( 2 ) . getImm ( ) == 0x0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ORRWrs ) {

if (MI.getOpcode() == zmtarzm::ORRWrs) {


if (MI.getOperand(1).getReg() == zmtarzm::WZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: WZR ) {


if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ;


if (MI.getOperand(2).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 2 ) . getReg ( ) == zmtarzm :: R0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ORRXrs ) {

if (MI.getOpcode() == zmtarzm::ORRXrs) {


if (MI.getOperand(1).getReg() == zmtarzm::XZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: XZR ) {


if (MI.getOperand(1).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: R0 ) {


bool zmtarzmInstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {

bool zmtarzmInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const {


const Function & F = MF . getFunction ( ) ;


if ( ! MF . getInfo < FunctionInfo > ( ) ) {


if ( MF . getInfo < FunctionInfo > ( ) -> hasRedZone ( ) . getValueOr ( true ) ) {


unsigned zmtarzmInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LDDRdPtrQ ) {

if (MI.getOpcode() == zmtarzm::LDDRdPtrQ) {


if ( MI . getOperand ( 1 ) . isFI ( ) ) {


if ( MI . getOperand ( 2 ) . isImm ( ) ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LDDWRdYQ ) {

if (MI.getOpcode() == zmtarzm::LDDWRdYQ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD16B ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD16H ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD16W ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD32B ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD32BS ) {

if (MI.getOpcode() == zmtarzm::LD32BS) {


if ( MI . getOpcode ( ) == zmtarzm :: LD32H ) {


if ( MI . getOpcode ( ) == zmtarzm :: LD32HS ) {

if (MI.getOpcode() == zmtarzm::LD32HS) {


if ( MI . getOpcode ( ) == zmtarzm :: LD32W ) {


if ( MI . getOpcode ( ) == zmtarzm :: RESTORE_CARRY ) {

if (MI.getOpcode() == zmtarzm::RESTORE_CARRY) {


unsigned zmtarzmInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOpcode ( ) == zmtarzm :: LD ) {


if ( MI . getOperand ( 2 ) . isFI ( ) ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LWZ ) {


if ( MI . getOpcode ( ) == zmtarzm :: LFS ) {


if ( MI . getOpcode ( ) == zmtarzm :: LFD ) {


if ( MI . getOpcode ( ) == zmtarzm :: RESTORE_CR ) {

if (MI.getOpcode() == zmtarzm::RESTORE_CR) {


if ( MI . getOpcode ( ) == zmtarzm :: RESTORE_CRBIT ) {

if (MI.getOpcode() == zmtarzm::RESTORE_CRBIT) {


if ( MI . getOpcode ( ) == zmtarzm :: LVX ) {


if ( MI . getOpcode ( ) == zmtarzm :: LXVD2X ) {

if (MI.getOpcode() == zmtarzm::LXVD2X) {


if ( MI . getOpcode ( ) == zmtarzm :: LXV ) {


if ( MI . getOpcode ( ) == zmtarzm :: QVLFDX ) {

if (MI.getOpcode() == zmtarzm::QVLFDX) {


if ( MI . getOpcode ( ) == zmtarzm :: QVLFSXs ) {

if (MI.getOpcode() == zmtarzm::QVLFSXs) {


if ( MI . getOpcode ( ) == zmtarzm :: QVLFDXb ) {

if (MI.getOpcode() == zmtarzm::QVLFDXb) {


if ( MI . getOpcode ( ) == zmtarzm :: RESTORE_VRSAVE ) {

if (MI.getOpcode() == zmtarzm::RESTORE_VRSAVE) {


if ( MI . getOperand ( 2 ) . isFI ( ) ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: SPILLTOVSR_LD ) {

if (MI.getOpcode() == zmtarzm::SPILLTOVSR_LD) {


bool zmtarzmInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const {

bool zmtarzmInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const {


assert(MBB.getParent()->getRegInfo().tracksLiveness() && "Suitable Machine Function for outlining must track liveness");


LiveRegUnits LRU ( getRegisterInfo ( ) ) ;


std::for_each(MBB.rbegin(), MBB.rend(), [&LRU](MachineInstr &MI) { LRU.accumulate(MI); });

std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ;


bool R12AvailableInBlock = LRU.available(zmtarzm::R12);

bool R12AvailableInBlock = LRU . available ( zmtarzm :: R12 ) ;


bool CPSRAvailableInBlock = LRU.available(zmtarzm::CPSR);

bool CPSRAvailableInBlock = LRU . available ( zmtarzm :: CPSR ) ;


if (any_of(MBB, [](MachineInstr &MI) { return MI.isCall(); })) {

if ( any_of ( MBB , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) {


Flags = Flags | MachineOutlinerMBBFlags :: HasCalls ;

Flags = Flags | MachineOutlinerMBBFlags::HasCalls;


if ( ! LRU . available ( zmtarzm :: LR ) ) {


Flags = Flags | MachineOutlinerMBBFlags :: LRUnavailableSomewhere ;

Flags = Flags | MachineOutlinerMBBFlags::LRUnavailableSomewhere;


bool zmtarzmInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const {

bool zmtarzmInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {


if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF)) {

if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) {


if ( MI . getOpcode ( ) == zmtarzm :: MFFS ) {


if ( MI . getOpcode ( ) == zmtarzm :: MTFSF ) {


if ( MI . getOpcode ( ) == zmtarzm :: ENDBR64 ) {

if (MI.getOpcode() == zmtarzm::ENDBR64) {


if ( MI . getOpcode ( ) == zmtarzm :: ENDBR32 ) {

if (MI.getOpcode() == zmtarzm::ENDBR32) {


if ( MI . getOpcode ( ) == zmtarzm :: LDTILECFG ) {

if (MI.getOpcode() == zmtarzm::LDTILECFG) {


unsigned zmtarzmInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STDPtrQRr ) {

if (MI.getOpcode() == zmtarzm::STDPtrQRr) {


if ( MI . getOperand ( 0 ) . isFI ( ) ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STDWPtrQRr ) {

if (MI.getOpcode() == zmtarzm::STDWPtrQRr) {


if ( MI . getOpcode ( ) == zmtarzm :: STORE32fi ) {

if (MI.getOpcode() == zmtarzm::STORE32fi) {


if ( MI . getOperand ( 1 ) . isFI ( ) ) {


if ( MI . getOperand ( 2 ) . isImm ( ) ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: STORE16fi ) {

if (MI.getOpcode() == zmtarzm::STORE16fi) {


unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: ST16B ) {


FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: ST16H ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST16W ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32B ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32H ) {


if ( MI . getOpcode ( ) == zmtarzm :: ST32W ) {


if ( MI . getOperand ( 1 ) . isFI ( ) ) {


if ( MI . getOperand ( 2 ) . isImm ( ) ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: FST_S ) {


if ( MI . getOpcode ( ) == zmtarzm :: FST_D ) {


if ( MI . getOpcode ( ) == zmtarzm :: f2FST_S ) {

if (MI.getOpcode() == zmtarzm::f2FST_S) {


if ( MI . getOpcode ( ) == zmtarzm :: f2FST_D ) {

if (MI.getOpcode() == zmtarzm::f2FST_D) {


if ( MI . getOpcode ( ) == zmtarzm :: SPILL_CARRY ) {

if (MI.getOpcode() == zmtarzm::SPILL_CARRY) {


unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STDPtrQRr ) {


if ( MI . getOperand ( 0 ) . isFI ( ) ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ;


return MI . getOperand ( 2 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STDWPtrQRr ) {


if ( MI . getOpcode ( ) == zmtarzm :: SW ) {


if ( MI . getOperand ( 1 ) . isFI ( ) ) {


if ( MI . getOperand ( 2 ) . isImm ( ) ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: BLOCK_STOREI ) {

if (MI.getOpcode() == zmtarzm::BLOCK_STOREI) {


unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOpcode ( ) == zmtarzm :: STD ) {


if ( MI . getOperand ( 2 ) . isFI ( ) ) {


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STW ) {


if ( MI . getOpcode ( ) == zmtarzm :: STFS ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: STFD ) {


if ( MI . getOpcode ( ) == zmtarzm :: SPILL_CR ) {

if (MI.getOpcode() == zmtarzm::SPILL_CR) {


if ( MI . getOpcode ( ) == zmtarzm :: SPILL_CRBIT ) {

if (MI.getOpcode() == zmtarzm::SPILL_CRBIT) {


if ( MI . getOpcode ( ) == zmtarzm :: STVX ) {


if ( MI . getOpcode ( ) == zmtarzm :: STXVD2X ) {

if (MI.getOpcode() == zmtarzm::STXVD2X) {


if ( MI . getOpcode ( ) == zmtarzm :: QVSTFDX ) {

if (MI.getOpcode() == zmtarzm::QVSTFDX) {


if ( MI . getOpcode ( ) == zmtarzm :: QVSTFSXs ) {

if (MI.getOpcode() == zmtarzm::QVSTFSXs) {


FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: QVSTFDXb ) {

if (MI.getOpcode() == zmtarzm::QVSTFDXb) {


if ( MI . getOpcode ( ) == zmtarzm :: SPILL_VRSAVE ) {

if (MI.getOpcode() == zmtarzm::SPILL_VRSAVE) {


unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {


if ( MI . getOperand ( # ) . isFI ( ) ) {


if ( MI . getOperand ( # ) . isImm ( ) ) {


if ( MI . getOperand ( # ) . getImm ( ) == # ) {


FrameIndex = MI . getOperand ( # ) . getIndex ( ) ;


return MI . getOperand ( 0 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STri ) {


if ( MI . getOperand ( 0 ) . isFI ( ) ) {


if ( MI . getOperand ( 1 ) . isImm ( ) ) {


if ( MI . getOperand ( 1 ) . getImm ( ) == 0 ) {


FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ;


return MI . getOperand ( 2 ) . getReg ( ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STXri ) {


if ( MI . getOpcode ( ) == zmtarzm :: STFri ) {


if ( MI . getOpcode ( ) == zmtarzm :: STDFri ) {

if (MI.getOpcode() == zmtarzm::STDFri) {


void zmtarzmInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


MachineFunction * MF = MBB . getParent ( ) ;


const MachineFrameInfo &MFI = MF->getFrameInfo();

const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ;


MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, MFI.getObjectSize(FI), MFI.getObjectAlign(FI));

MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;


BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);

BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ;


if ( zmtarzm :: GRRegsRegClass . hasSubClassEq ( RC ) ) {


llvm_unreachable("Can't load this register from stack slot");


if ( zmtarzm :: GPRRegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: CARRYRegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: sFPR32RegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: sFPR64RegClass . hasSubClassEq ( RC ) ) {


void zmtarzmInstrInfo::movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag) const {

void zmtarzmInstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const {


assert
(
isUInt
<
32
>
(
Val
)
&&
"should be uint32"
)
;

assert(isUInt<32>(Val) && "should be uint32");


MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ;


DstReg = MRI . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVI32), DstReg).addImm(Val & 0xFFFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVI32 ) , DstReg ) . addImm ( Val & 0xFFFF ) . setMIFlags ( Flag ) ;


if ( isShiftedUInt < 16 , 16 > ( Val ) ) {


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVIH32), DstReg).addImm((Val >> 16) & 0xFFFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVIH32 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFFFF ) . setMIFlags ( Flag ) ;


if ( ! isShiftedUInt < 16 , 16 > ( Val ) ) {


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(DstReg).addImm(Val & 0xFFFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & 0xFFFF ) . setMIFlags ( Flag ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: ORI32 ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & 0xFFFF ) . setMIFlags ( Flag ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::ORI32), DstReg).addReg(DstReg).addImm(Val & 0xFFFF).setMIFlags(Flag);


DstReg = MRI . createVirtualRegister ( & zmtarzm :: mGPRRegClass ) ;


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVI16), DstReg).addImm(Val & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVI16 ) , DstReg ) . addImm ( Val & 0xFF ) . setMIFlags ( Flag ) ;


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVI16), DstReg).addImm((Val >> 8) & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 8 ) & 0xFF ) . setMIFlags ( Flag ) ;


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(DstReg).addImm(8).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( DstReg ) . addImm ( 8 ) . setMIFlags ( Flag ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: LSLI16 ) , DstReg ) . addReg ( DstReg ) . addImm ( 8 ) . setMIFlags ( Flag ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::LSLI16), DstReg).addReg(DstReg).addImm(8).setMIFlags(Flag);


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(DstReg).addImm(Val & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: ADDI16 ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::ADDI16), DstReg).addReg(DstReg).addImm(Val & 0xFF).setMIFlags(Flag);


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVI16), DstReg).addImm((Val >> 16) & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFF ) . setMIFlags ( Flag ) ;


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(DstReg).addImm((Val >> 8) & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> 8 ) & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: ADDI16 ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> 8 ) & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::ADDI16), DstReg).addReg(DstReg).addImm((Val >> 8) & 0xFF).setMIFlags(Flag);


BuildMI(MBB, MBBI, DL, get(zmtarzm::MOVI16), DstReg).addImm((Val >> 24) & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 24 ) & 0xFF ) . setMIFlags ( Flag ) ;


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(DstReg).addImm((Val >> 16) & 0xFF).setMIFlags(Flag);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> 16 ) & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: ADDI16 ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> 16 ) & 0xFF ) . setMIFlags ( Flag ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::ADDI16), DstReg).addReg(DstReg).addImm((Val >> 16) & 0xFF).setMIFlags(Flag);


static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl<MachineOperand> &Cond) {

static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) {


assert(LastInst.getDesc().isConditionalBranch() && "Unknown conditional branch");

assert
(
LastInst
.
getDesc
(
)
.
isConditionalBranch
(
)
&&
"Unknown conditional branch"
)
;


Target = LastInst . getOperand ( 2 ) . getMBB ( ) ;


Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ;


Cond . push_back ( LastInst . getOperand ( 0 ) ) ;


Cond . push_back ( LastInst . getOperand ( # ) ) ;


Cond . push_back ( LastInst . getOperand ( 1 ) ) ;


unsigned zmtarzmInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {

unsigned zmtarzmInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const {


MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();

MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ;


if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) {


*BytesRemoved = *BytesRemoved + getInstSizeInBytes(*I);

* BytesRemoved = * BytesRemoved + getInstSizeInBytes ( * I ) ;


bool zmtarzmInstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {

bool zmtarzmInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {


assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;

assert((Cond.size() == 3) && "Invalid branch condition!");


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_EQ ) {

if (Cond[0].getImm() == zmtarzm::COND_EQ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NE ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NE ) {

if (Cond[0].getImm() == zmtarzm::COND_NE) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_EQ ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


assert
(
(
Cond
.
size
(
)
==
2
)
&&
"Invalid branch condition!"
)
;

assert((Cond.size() == 2) && "Invalid branch condition!");


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: EQ ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: NE ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: HS ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: LO ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: MI ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: PL ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: VS ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: VC ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: HI ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: LS ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: LT ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: GE ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: LE ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: GT ) {


bool zmtarzmInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {


assert
(
(
Cond
.
size
(
)
==
1
)
&&
"Invalid branch condition!"
)
;

assert((Cond.size() == 1) && "Invalid branch condition!");


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_EQ ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NE ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NE ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_EQ ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_SH ) {

if (Cond[0].getImm() == zmtarzm::COND_SH) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_LO ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_LO ) {

if (Cond[0].getImm() == zmtarzm::COND_LO) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_SH ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_GE ) {

if (Cond[0].getImm() == zmtarzm::COND_GE) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_LT ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_PL ) {

if (Cond[0].getImm() == zmtarzm::COND_PL) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_MI ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_C ) {

if (Cond[0].getImm() == zmtarzm::COND_C) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NC ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_N ) {

if (Cond[0].getImm() == zmtarzm::COND_N) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NN ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_V ) {

if (Cond[0].getImm() == zmtarzm::COND_V) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NV ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_Z ) {

if (Cond[0].getImm() == zmtarzm::COND_Z) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NZ ) ;


Cond [ 0 ] . setImm ( zmtarzm :: COND_L ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NC ) {

if (Cond[0].getImm() == zmtarzm::COND_NC) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_C ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NN ) {

if (Cond[0].getImm() == zmtarzm::COND_NN) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_N ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NV ) {

if (Cond[0].getImm() == zmtarzm::COND_NV) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_V ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NZ ) {

if (Cond[0].getImm() == zmtarzm::COND_NZ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_Z ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_L ) {

if (Cond[0].getImm() == zmtarzm::COND_L) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_GE ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


bool zmtarzmInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {

bool zmtarzmInstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {


assert
(
(
Cond
.
size
(
)
==
2
)
&&
"Invalid branch condition!"
)
;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BT32 ) {

if (Cond[0].getImm() == zmtarzm::BT32) {


Cond [ 0 ] . setImm ( zmtarzm :: BF32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BT16 ) {

if (Cond[0].getImm() == zmtarzm::BT16) {


Cond [ 0 ] . setImm ( zmtarzm :: BF16 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BF32 ) {

if (Cond[0].getImm() == zmtarzm::BF32) {


Cond [ 0 ] . setImm ( zmtarzm :: BT32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BF16 ) {

if (Cond[0].getImm() == zmtarzm::BF16) {


Cond [ 0 ] . setImm ( zmtarzm :: BT16 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BHZ32 ) {

if (Cond[0].getImm() == zmtarzm::BHZ32) {


Cond [ 0 ] . setImm ( zmtarzm :: BLSZ32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BLZ32 ) {

if (Cond[0].getImm() == zmtarzm::BLZ32) {


Cond [ 0 ] . setImm ( zmtarzm :: BHSZ32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BLSZ32 ) {

if (Cond[0].getImm() == zmtarzm::BLSZ32) {


Cond [ 0 ] . setImm ( zmtarzm :: BHZ32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BNEZ32 ) {

if (Cond[0].getImm() == zmtarzm::BNEZ32) {


Cond [ 0 ] . setImm ( zmtarzm :: BEZ32 ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: BEZ32 ) {

if (Cond[0].getImm() == zmtarzm::BEZ32) {


Cond [ 0 ] . setImm ( zmtarzm :: BNEZ32 ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


bool zmtarzmInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {


assert
(
(
Cond
.
size
(
)
==
1
)
&&
"Invalid branch condition!"
)
;

assert((Cond.size() == 1) && "Invalid branch condition!");


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_EQ ) {

if (Cond[0].getImm() == zmtarzm::COND_EQ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NE ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NE ) {

if (Cond[0].getImm() == zmtarzm::COND_NE) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_EQ ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_SH ) {

if (Cond[0].getImm() == zmtarzm::COND_SH) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_LO ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_LO ) {

if (Cond[0].getImm() == zmtarzm::COND_LO) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_SH ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_GE ) {

if (Cond[0].getImm() == zmtarzm::COND_GE) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_LT ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_LT ) {

if (Cond[0].getImm() == zmtarzm::COND_LT) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_GE ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_PL ) {

if (Cond[0].getImm() == zmtarzm::COND_PL) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_MI ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_MI ) {

if (Cond[0].getImm() == zmtarzm::COND_MI) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_PL ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


bool zmtarzmInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {

bool zmtarzmInstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {


assert
(
(
Cond
.
size
(
)
==
1
)
&&
"Invalid branch condition!"
)
;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_E ) {

if (Cond[0].getImm() == zmtarzm::COND_E) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NE ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NE ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_E ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_L ) {

if (Cond[0].getImm() == zmtarzm::COND_L) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_L ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_HS ) {

if (Cond[0].getImm() == zmtarzm::COND_HS) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_LO ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_LO ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_HS ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_C ) {

if (Cond[0].getImm() == zmtarzm::COND_C) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NC ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_N ) {

if (Cond[0].getImm() == zmtarzm::COND_N) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NN ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_V ) {

if (Cond[0].getImm() == zmtarzm::COND_V) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NV ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_Z ) {

if (Cond[0].getImm() == zmtarzm::COND_Z) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_NZ ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_GE ) {


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NC ) {

if (Cond[0].getImm() == zmtarzm::COND_NC) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_C ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NN ) {

if (Cond[0].getImm() == zmtarzm::COND_NN) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_N ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NV ) {

if (Cond[0].getImm() == zmtarzm::COND_NV) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_V ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_NZ ) {

if (Cond[0].getImm() == zmtarzm::COND_NZ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_Z ) ;


if ( Cond [ 0 ] . getImm ( ) == zmtarzm :: COND_L ) {


Cond [ 0 ] . setImm ( zmtarzm :: COND_GE ) ;


llvm_unreachable
(
"Unrecognized conditional branch"
)
;


void zmtarzmInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


MachineFunction & MF = * MBB . getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;