MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlign(FI));

MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;


MachineFunctionInfo *CFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


if ( zmtarzm :: GPRRegClass . hasSubClassEq ( RC ) ) {


BuildMI(MBB, I, DL, get(Opcode)).addReg(SrcReg, getKillRegState(IsKill)).addFrameIndex(FI).addImm(0).addMemOperand(MMO);

BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ;


if ( zmtarzm :: CARRYRegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: sFPR32RegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: sFPR64RegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: FPR32RegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: FPR64RegClass . hasSubClassEq ( RC ) ) {


llvm_unreachable("Can't store this register to stack slot");


void zmtarzmInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


MachineFunction & MF = * MBB . getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


if ( zmtarzm :: GPR32RegClass . hasSubClassEq ( RC ) ) {


if ( zmtarzm :: VR512RegClass . hasSubClassEq ( RC ) ) {


bool zmntarzmInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const {

bool zmntarzmInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const {


if ( convertAddSubFlagsOpcode ( MI . getOpcode ( ) ) ) {


ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";


if ( MI . getOpcode ( ) == zmtarzm :: tMOVr ) {


if ( ! zmtarzm :: hGPRRegClass . contains ( MI . getOperand ( 0 ) . getReg ( ) ) ) {


if ( ! zmtarzm :: hGPRRegClass . contains ( MI . getOperand ( 1 ) . getReg ( ) ) ) {


ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";


if ( MI . getOpcode ( ) == zmtarzm :: tPUSH ) {


for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2)) {

for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) {


ErrInfo = "Unsupported register in Thumb1 push/pop";


if ( MI . getOpcode ( ) == zmtarzm :: tPOP ) {


if ( MI . getOpcode ( ) == zmtarzm :: tPOP_RET ) {

if (MI.getOpcode() == zmtarzm::tPOP_RET) {


if ( MI . getOpcode ( ) == zmtarzm :: MVE_VMOV_q_rr ) {

if (MI.getOpcode() == zmtarzm::MVE_VMOV_q_rr) {


assert ( MI . getOperand ( 4 ) . isImm ( ) && MI . getOperand ( 5 ) . isImm ( ) ) ;


if (MI.getOperand(4).getImm() != MI.getOperand(5).getImm() + 2) {

if ( MI . getOperand ( 4 ) . getImm ( ) != MI . getOperand ( 5 ) . getImm ( ) + 2 ) {


ErrInfo = "Incorrect array index for MVE_VMOV_q_rr";


InstructionSelector *createzmtarzmInstructionSelector(const zmtarzmTargetMachine &TM, zmtarzmSubtarget &Subtarget, zmtarzmRegisterBankInfo &RBI) {

InstructionSelector * createzmtarzmInstructionSelector ( const zmtarzmTargetMachine & TM , zmtarzmSubtarget & Subtarget , zmtarzmRegisterBankInfo & RBI ) {


return new zmtarzmInstructionSelector(TM, Subtarget, RBI);

return new zmtarzmInstructionSelector ( TM , Subtarget , RBI ) ;


zmtarzmInstructionSelector::zmtarzmInstructionSelector(const zmtarzmTargetMachine &TM, const zmtarzmSubtarget &STI,const zmtarzmRegisterBankInfo &RBI) : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),  #define GET_GLOBALISEL_PREDICATES_INIT #include "zmtarzmGenGlobalISel.inc" #undef GET_GLOBALISEL_PREDICATES_INIT #define GET_GLOBALISEL_TEMPORARIES_INIT #include "zmtarzmGenGlobalISel.inc" #undef GET_GLOBALISEL_TEMPORARIES_INIT {

zmtarzmInstructionSelector :: zmtarzmInstructionSelector ( const zmtarzmTargetMachine & TM , const zmtarzmSubtarget & STI , const zmtarzmRegisterBankInfo & RBI ) : InstructionSelector ( ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , # define GET_GLOBALISEL_PREDICATES_INIT # include "zmtarzmGenGlobalISel.inc" # undef GET_GLOBALISEL_PREDICATES_INIT # define GET_GLOBALISEL_TEMPORARIES_INIT # include "zmtarzmGenGlobalISel.inc" # undef GET_GLOBALISEL_TEMPORARIES_INIT {


bool zmtarzmInstructionSelector::select(MachineInstr &I) {

bool zmtarzmInstructionSelector :: select ( MachineInstr & I ) {


if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) {


if ( selectImpl ( I , * CoverageInfo ) ) {


FunctionPass *llvm::createzmtarzmISelDag(zmtarzmTargetMachine &TM) {

FunctionPass * llvm :: createzmtarzmISelDag ( zmtarzmTargetMachine & TM ) {


explicit zmtarzmDAGToDAGISel(zmtarzmTargetMachine &TargetMachine) : SelectionDAGISel(TargetMachine) {

explicit zmtarzmDAGToDAGISel ( zmtarzmTargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


return "zmtarzm DAG->DAG Pattern Instruction Selection";


bool zmtarzmDAGToDAGISel::MatchSLLIUW(SDNode *N) const {

bool zmtarzmDAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const {


bool zmtarzmDAGToDAGISel::MatchSRLIUW(SDNode *N) const {

bool zmtarzmDAGToDAGISel :: MatchSRLIUW ( SDNode * N ) const {


void zmtarzmDAGToDAGISel :: PostprocessISelDAG ( ) {


const zmtarzmTargetLowering& Lowering = *static_cast<const zmtarzmTargetLowering*>(getTargetLowering());

const zmtarzmTargetLowering & Lowering = * static_cast < const zmtarzmTargetLowering * > ( getTargetLowering ( ) ) ;


if (TM.getOptLevel() == CodeGenOpt::None) {

if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) {


SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ;


SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin();

SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ;


for(; Position != CurDAG->allnodes_end(); ) {

for ( ; Position != CurDAG -> allnodes_end ( ) ; ) {


MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(Node);

MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ;


SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);

SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ;


unsigned StorageOpcode = N->getMachineOpcode();

unsigned StorageOpcode = N -> getMachineOpcode ( ) ;


if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) {


if (N->getConstantOperandVal(FirstOp) != 0) {

if ( N -> getConstantOperandVal ( FirstOp ) != 0 ) {


SDValue Base = N->getOperand(FirstOp + 1);

SDValue Base = N -> getOperand ( FirstOp + 1 ) ;


if ( Base . getMachineOpcode ( ) == # ) {


DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase:    ");


SDValue ImmOpnd = Base . getOperand ( 1 ) ;


if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {

if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) {


const GlobalValue *GV = GA->getGlobal();

const GlobalValue * GV = GA -> getGlobal ( ) ;


ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);

ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , MVT :: i64 , 0 , Flags ) ;


if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) {


const Constant * C = CP -> getConstVal ( ) ;


ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,  CP->getAlignment(),  0, Flags);

ImmOpnd = CurDAG -> getTargetConstantPool ( C , MVT :: i64 , CP -> getAlignment ( ) , 0 , Flags ) ;


(void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, Base.getOperand(0), N->getOperand(3));

( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ;


if ( Base . getNode ( ) -> use_empty ( ) ) {


CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ;


void zmtarzmDAGToDAGISel :: PostprocessISelDAG ( ) {


const zmtarzmTargetLowering & Lowering = * static_cast < const zmtarzmTargetLowering * > ( getTargetLowering ( ) ) ;


if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) {


SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ;


SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ;


for ( ; Position != CurDAG -> allnodes_end ( ) ; ) {


MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ;


SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ;


unsigned StorageOpcode = N -> getMachineOpcode ( ) ;


if ( StorageOpcode == zmtarzm :: LBZ ) {


if ( StorageOpcode == zmtarzm :: LBZ8 ) {


if ( StorageOpcode == zmtarzm :: LFD ) {


if ( StorageOpcode == zmtarzm :: LFS ) {


if ( StorageOpcode == zmtarzm :: LHA ) {


if ( StorageOpcode == zmtarzm :: STB ) {


if ( StorageOpcode == zmtarzm :: STB8 ) {


if ( StorageOpcode == zmtarzm :: STD ) {


if ( StorageOpcode == zmtarzm :: STFD ) {


if ( StorageOpcode == zmtarzm :: STFS ) {


if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) {


if ( N -> getConstantOperandVal ( FirstOp ) != 0 ) {


SDValue Base = N -> getOperand ( FirstOp + 1 ) ;


if ( Base . getMachineOpcode ( ) == # ) {

if ( Base . getMachineOpcode ( ) == zmtarzm :: ADDI8 ) {

if (Base.getMachineOpcode() == zmtarzm::ADDI8) {


if ( Base . getMachineOpcode ( ) == zmtarzm :: ADDIdtprelL ) {

if (Base.getMachineOpcode() == zmtarzm::ADDIdtprelL) {


if ( Base . getMachineOpcode ( ) == zmtarzm :: ADDItlsldL ) {

if (Base.getMachineOpcode() == zmtarzm::ADDItlsldL) {


if ( Base . getMachineOpcode ( ) == zmtarzm :: ADDItocL ) {

if (Base.getMachineOpcode() == zmtarzm::ADDItocL) {


"Folding add-immediate into mem-op:\nBase:    "


SDValue ImmOpnd = Base . getOperand ( 1 ) ;


if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) {


const GlobalValue * GV = GA -> getGlobal ( ) ;


ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , MVT :: i64 , 0 , Flags ) ;


if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) {


const Constant * C = CP -> getConstVal ( ) ;


ImmOpnd = CurDAG -> getTargetConstantPool ( C , MVT :: i64 , CP -> getAlignment ( ) , 0 , Flags ) ;


( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ;


if ( Base . getNode ( ) -> use_empty ( ) ) {


CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ;


bool runOnMachineFunction(MachineFunction &MF) override {

bool runOnMachineFunction ( MachineFunction & MF ) override {


Subtarget = & MF . getSubtarget < zmtarzmSubtarget > ( ) ;


return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


bool zmtarzmDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {

bool zmtarzmDAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) {


if (auto FIN = dyn_cast<FrameIndexSDNode>(Addr)) {

if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) {


Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), #);

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , # ) ;

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i16 ) ;

Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);


Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i64 ) ;

Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);


Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;

Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


if ( ConstraintID == InlineAsm :: Constraint_i ) {

if (ConstraintID == InlineAsm::Constraint_i) {


if ( ConstraintID == InlineAsm :: Constraint_m ) {

if (ConstraintID == InlineAsm::Constraint_m) {


if ( ConstraintID == InlineAsm :: Constraint_Q ) {

if (ConstraintID == InlineAsm::Constraint_Q) {


llvm_unreachable("Unexpected asm memory constraint");

llvm_unreachable
(
"Unexpected asm memory constraint"
)
;


bool zmtarzmDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {

bool zmtarzmDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


imm = CurDAG->getTargetConstant(bit, MVT::i32);

imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) {


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_byte ) {

if (IntNo == Intrinsic::zmtarzm_load_byte) {


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_half ) {

if (IntNo == Intrinsic::zmtarzm_load_half) {


if ( IntNo == Intrinsic :: zmtarzm_load_word ) {

if (IntNo == Intrinsic::zmtarzm_load_word) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


if ( Node -> getOpcode ( ) == ISD :: FrameIndex ) {

if (Node->getOpcode() == ISD::FrameIndex) {


int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


bool zmtarzmTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0, unsigned Align = 1, MachineMemOperand::Flags Flags = MachineMemOperand::MONone, bool *Fast = nullptr) const {

bool zmtarzmTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , MachineMemOperand :: Flags Flags = MachineMemOperand :: MONone , bool * Fast = nullptr ) const {


if ( Subtarget . isHVXVectorType ( ) ) {


void zmtarzmTargetLowering::analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {

void zmtarzmTargetLowering :: analyzeInputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: InputArg > & Ins , bool IsRet ) const {


FunctionType *FType = MF.getFunction().getFunctionType();

FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ;


for (unsigned i = 0; i != NumArgs; ++i) {

for ( unsigned i = 0 ; i != NumArgs ; ++ i ) {


ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;

ISD :: ArgFlagsTy ArgFlags = Ins [ i ] . Flags ;


if (RetCC_(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) {

if ( RetCC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) {


LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << '\n');

LLVM_DEBUG
(
dbgs
(
)
<<
"InputArg #"
<<
i
<<
" has unhandled type "
<<
EVT
(
ArgVT
)
.
getEVTString
(
)
<<
'\n'
)
;


if (CC_(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) {

if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) {


if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {

if ( Fn ( i , ArgVT , CCValAssign :: Full , CCInfo ) ) {


void zmtarzmTargetLowering::analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, CallLoweringInfo *CLI) const {

void zmtarzmTargetLowering :: analyzeOutputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: OutputArg > & Outs , bool IsRet , CallLoweringInfo * CLI ) const {


for (unsigned i = 0; i != NumArgs; i++) {

for ( unsigned i = 0 ; i != NumArgs ; i ++ ) {


ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;

ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ;


LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"OutputArg #"
<<
i
<<
" has unhandled type "
<<
EVT
(
ArgVT
)
.
getEVTString
(
)
<<
"\n"
)
;


bool zmtarzmTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {

bool zmtarzmTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const {


CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS ? RetCC_zmtarzm_WebKit_JS : RetCC_zmtarzm_AAPCS;

CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_zmtarzm_WebKit_JS : RetCC_zmtarzm_AAPCS ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);

CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;


CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;


auto CCFunction = CCAssignFnForReturn(CallConv);

auto CCFunction = CCAssignFnForReturn ( CallConv ) ;


for (unsigned i = 0, e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


return CCInfo . CheckReturn ( Outs , RetCC ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CSEL ) {

if (Op.getOpcode() == zmtarzmISD::CSEL) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_ldaxr ) {

if (IntID == Intrinsic::zmtarzm_ldaxr) {


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


if ( IntID == Intrinsic :: zmtarzm_ldxr ) {


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_umaxv ) {

if (IntID == Intrinsic::zmtarzm_neon_umaxv) {


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;

assert(BitWidth >= 8 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;

assert(BitWidth >= 16 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_uminv ) {

if (IntID == Intrinsic::zmtarzm_neon_uminv) {


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CARRY ) {

if (Op.getOpcode() == zmtarzmISD::CARRY) {


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BORROW ) {

if (Op.getOpcode() == zmtarzmISD::BORROW) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_I32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_I32) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


unsigned BitWidth = Known.getBitWidth();


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_U32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_U32) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


assert((Opc >= ISD::BUILTIN_OP_END || Opc == ISD::INTRINSIC_WO_CHAIN || Opc == ISD::INTRINSIC_W_CHAIN || Opc == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op is a target node!");


if ( Op . getOpcode ( ) == zmtarzmISD :: ADD ) {

if (Op.getOpcode() == zmtarzmISD::ADD) {


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SUB ) {

if (Op.getOpcode() == zmtarzmISD::SUB) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: ADC ) {

if (Op.getOpcode() == zmtarzmISD::ADC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SBB ) {

if (Op.getOpcode() == zmtarzmISD::SBB) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SMUL ) {

if (Op.getOpcode() == zmtarzmISD::SMUL) {


if ( Op . getOpcode ( ) == zmtarzmISD :: UMUL ) {

if (Op.getOpcode() == zmtarzmISD::UMUL) {


if ( Op . getOpcode ( ) == zmtarzmISD :: INC ) {

if (Op.getOpcode() == zmtarzmISD::INC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: DEC ) {

if (Op.getOpcode() == zmtarzmISD::DEC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: OR ) {


if ( Op . getOpcode ( ) == zmtarzmISD :: XOR ) {

if (Op.getOpcode() == zmtarzmISD::XOR) {


if ( Op . getOpcode ( ) == zmtarzmISD :: AND ) {

if (Op.getOpcode() == zmtarzmISD::AND) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC ) {

if (Op.getOpcode() == zmtarzmISD::SETCC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: MOVMSK ) {

if (Op.getOpcode() == zmtarzmISD::MOVMSK) {


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSRLI ) {

if (Op.getOpcode() == zmtarzmISD::VSRLI) {


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSHLI ) {

if (Op.getOpcode() == zmtarzmISD::VSHLI) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);


if ( Op . getOpcode ( ) == zmtarzmISD :: VZEXT ) {

if (Op.getOpcode() == zmtarzmISD::VZEXT) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


assert
(
InNumElts
>=
NumElts
&&
"Illegal VZEXT input"
)
;

assert(InNumElts >= NumElts && "Illegal VZEXT input");


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


unsigned zmtarzmTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

unsigned zmtarzmTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


return Op . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CARRY ) {

if (Op.getOpcode() == zmtarzmISD::CARRY) {


if ( Op . getOpcode ( ) == zmtarzmISD :: BORROW ) {

if (Op.getOpcode() == zmtarzmISD::BORROW) {


if ( Op . getOpcode ( ) == zmtarzmISD :: FP_TO_FP16 ) {

if (Op.getOpcode() == zmtarzmISD::FP_TO_FP16) {


if ( Op . getOpcode ( ) == zmtarzmISD :: FP16_ZEXT ) {

if (Op.getOpcode() == zmtarzmISD::FP16_ZEXT) {


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_I32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_I32) {


ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


unsigned SignBits = 32 - Width->getZExtValue() + 1;

unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ;


if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) {


unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);

unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ;


unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1);

unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ;


Tmp = Tmp + VTBits - Src.getScalarValueSizeInBits();

Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ;


return std :: max ( SignBits , Op0SignBits ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_U32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_U32) {


APInt ShiftVal = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();

APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ;


return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ;

return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;


unsigned zmtarzmTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC_CARRY ) {

if (Op.getOpcode() == zmtarzmISD::SETCC_CARRY) {


return Op . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: PCMPGT ) {

if (Op.getOpcode() == zmtarzmISD::PCMPGT) {


if ( Op . getOpcode ( ) == zmtarzmISD :: PCMPEQ ) {

if (Op.getOpcode() == zmtarzmISD::PCMPEQ) {


if ( Op . getOpcode ( ) == zmtarzmISD :: CMPP ) {

if (Op.getOpcode() == zmtarzmISD::CMPP) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VPCOM ) {

if (Op.getOpcode() == zmtarzmISD::VPCOM) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VPCOMU ) {

if (Op.getOpcode() == zmtarzmISD::VPCOMU) {


if ( Op . getOpcode ( ) == zmtarzmISD :: VSEXT ) {

if (Op.getOpcode() == zmtarzmISD::VSEXT) {


ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ;


if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) {


unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ;


unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ;


Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSRAI ) {

if (Op.getOpcode() == zmtarzmISD::VSRAI) {


APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ;


return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ;

return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();


bool convertSelectOfConstantsToMath(EVT VT) const override {

bool convertSelectOfConstantsToMath ( EVT VT ) const override {


bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {

bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override {


bool zmtarzmTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const {

bool zmtarzmTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const {


if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {

if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) {


if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) {


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


unsigned Shift = countTrailingZeros<uint64_t>(Imm);

unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ;


uint64_t UImm = static_cast<uint64_t>(Imm);

uint64_t UImm = static_cast < uint64_t > ( Imm ) ;


MachineBasicBlock *zmtarzmTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const {

MachineBasicBlock * zmtarzmTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_Int_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_Int_ICC) {


return expandSelectCC(MI, BB, zmtarzm::BCOND);

return expandSelectCC ( MI , BB , zmtarzm :: BCOND ) ;


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_FP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_FP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_DFP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_DFP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_QFP_ICC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_QFP_ICC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_Int_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_Int_FCC) {


return expandSelectCC(MI, BB, zmtarzm::FBCOND);

return expandSelectCC ( MI , BB , zmtarzm :: FBCOND ) ;


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_FP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_FP_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_DFP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_DFP_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT_CC_QFP_FCC ) {

if (MI.getOpcode() == zmtarzm::SELECT_CC_QFP_FCC) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_SETJMP32rr ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_SETJMP32rr) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_LONGJMP32rr ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_LONGJMP32rr) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SJLJ_LONGJMP32ri ) {

if (MI.getOpcode() == zmtarzm::EH_SJLJ_LONGJMP32ri) {


llvm_unreachable("Unexpected instruction for custom inserter!");


if ( MI . getOpcode ( ) == zmtarzm :: EH_SjLj_LongJmp ) {

if (MI.getOpcode() == zmtarzm::EH_SjLj_LongJmp) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SjLj_SetJmp ) {

if (MI.getOpcode() == zmtarzm::EH_SjLj_SetJmp) {


if ( MI . getOpcode ( ) == zmtarzm :: EH_SjLj_Setup_Dispatch ) {

if (MI.getOpcode() == zmtarzm::EH_SjLj_Setup_Dispatch) {


return emitSjLjDispatchBlock ( MI , BB ) ;


MachineBasicBlock * zmtarzmTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const {

MachineBasicBlock *zmtarzmTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const {


return expandSelectCC ( MI , BB , zmtarzm :: BCOND ) ;

return expandSelectCC(MI, BB, zmtarzm::BCOND);


if ( MI . getOpcode ( ) == zmtarzm :: SELECT8 ) {

if (MI.getOpcode() == zmtarzm::SELECT8) {


if ( MI . getOpcode ( ) == zmtarzm :: SELECT16 ) {

if (MI.getOpcode() == zmtarzm::SELECT16) {


if ( MI . getOpcode ( ) == zmtarzm :: SHL8 ) {


return expandSelectCC ( MI , BB , zmtarzm :: FBCOND ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LSHR8 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ASHR8 ) {


if ( MI . getOpcode ( ) == zmtarzm :: SHL16 ) {


if ( MI . getOpcode ( ) == zmtarzm :: LSHR16 ) {

if (MI.getOpcode() == zmtarzm::LSHR16) {


if ( MI . getOpcode ( ) == zmtarzm :: ASHR16 ) {

if (MI.getOpcode() == zmtarzm::ASHR16) {


Instruction *zmtarzmTargetLowering::emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const {

Instruction * zmtarzmTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const {


if ( Ord == AtomicOrdering :: NotAtomic ) {


llvm_unreachable
(
"Invalid fence: unordered/non-atomic"
)
;


if ( Ord == AtomicOrdering :: Unordered ) {


if ( Ord == AtomicOrdering :: Monotonic ) {


if ( Ord == AtomicOrdering :: Acquire ) {


if (Ord == AtomicOrdering::SequentiallyConsistent) {

if ( Ord == AtomicOrdering :: SequentiallyConsistent ) {


if ( Ord == AtomicOrdering :: Release ) {


if ( Subtarget -> preferISHSTBarriers ( ) ) {


return makeDMB ( Builder , zmtarzm_MB :: ISHST ) ;


if ( ! Subtarget -> preferISHSTBarriers ( ) ) {


return makeDMB ( Builder , zmtarzm_MB :: ISH ) ;


if ( Ord == AtomicOrdering :: AcquireRelease ) {

if (Ord == AtomicOrdering::AcquireRelease) {


return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ;


llvm_unreachable("Unknown fence ordering in emitLeadingFence");


return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ;


Value *zmtarzmTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {

Value * zmtarzmTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const {


assert
(
shouldInlineQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;

assert(shouldInlineQuadwordAtomics() && "Only support quadword now");


Module *M = Builder.GetInsertBlock()->getParent()->getParent();

Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


assert ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) ;


Function *IntCmpXchg = Intrinsic::getDeclaration(M, Intrinsic::ppc_cmpxchg_i128);

Function * IntCmpXchg = Intrinsic :: getDeclaration ( M , Intrinsic :: ppc_cmpxchg_i128 ) ;


Type *Int64Ty = Type::getInt64Ty(M->getContext());

Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ;


Value *CmpLo = Builder.CreateTrunc(CmpVal, Int64Ty, "cmp_lo");

Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , "cmp_lo" ) ;


Value *CmpHi = Builder.CreateTrunc(Builder.CreateLShr(CmpVal, 64), Int64Ty, "cmp_hi");

Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , 64 ) , Int64Ty , "cmp_hi" ) ;


Value *NewLo = Builder.CreateTrunc(NewVal, Int64Ty, "new_lo");

Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , "new_lo" ) ;


Value *NewHi = Builder.CreateTrunc(Builder.CreateLShr(NewVal, 64), Int64Ty, "new_hi");

Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , 64 ) , Int64Ty , "new_hi" ) ;


Value *Addr = Builder.CreateBitCast(AlignedAddr, Type::getInt8PtrTy(M->getContext()));

Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


emitLeadingFence ( Builder , CI , Ord ) ;


Value *LoHi = Builder.CreateCall(IntCmpXchg, {Addr, CmpLo, CmpHi, NewLo, NewHi});

Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ;


emitTrailingFence ( Builder , CI , Ord ) ;


Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");

Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ;


Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");

Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ;


Lo = Builder.CreateZExt(Lo, ValTy, "lo64");

Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ;


Hi = Builder.CreateZExt(Hi, ValTy, "hi64");

Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ;


return Builder.CreateOr(Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");

return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ;


Value *zmtarzmTargetLowering::emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {

Value * zmtarzmTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const {


assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;

assert(EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && "Only support quadword now");


Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;


Type *ValTy = AlignedAddr->getType()->getPointerElementType();

Type * ValTy = AlignedAddr -> getType ( ) -> getPointerElementType ( ) ;


assert ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) ;


Function *RMW = Intrinsic::getDeclaration(M, getIntrinsicForAtomicRMWBinOp128(AI->getOperation()));

Function * RMW = Intrinsic :: getDeclaration ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ;


Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ;


Value *IncrLo = Builder.CreateTrunc(Incr, Int64Ty, "incr_lo");

Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , "incr_lo" ) ;


Value *IncrHi = Builder.CreateTrunc(Builder.CreateLShr(Incr, 64), Int64Ty, "incr_hi");

Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , 64 ) , Int64Ty , "incr_hi" ) ;


Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


Value *LoHi = Builder.CreateCall(RMW, {Addr, IncrLo, IncrHi});

Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ;


Instruction *zmtarzmTargetLowering::emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const {

Instruction * zmtarzmTargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const {


if ( Ord == AtomicOrdering :: NotAtomic ) {


llvm_unreachable
(
"Invalid fence: unordered/not-atomic"
)
;


if ( Ord == AtomicOrdering :: Unordered ) {


if ( Ord == AtomicOrdering :: Acquire ) {


return makeDMB ( Builder , zmtarzm_MB :: ISH ) ;


if (Ord == AtomicOrdering::AcquireRelease) {

if ( Ord == AtomicOrdering :: AcquireRelease ) {


if (Ord == AtomicOrdering::SequentiallyConsistent) {

if ( Ord == AtomicOrdering :: SequentiallyConsistent ) {


if ( Ord == AtomicOrdering :: Monotonic ) {


if ( Ord == AtomicOrdering :: Release ) {


llvm_unreachable("Unknown fence ordering in emitTrailingFence");


return Builder.CreateCall(Intrinsic::getDeclaration(Builder.GetInsertBlock()->getParent()->getParent(), Intrinsic::ppc_cfence, {Inst->getType()}), {Inst});

return Builder . CreateCall ( Intrinsic :: getDeclaration ( Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) , Intrinsic :: ppc_cfence , { Inst -> getType ( ) } ) , { Inst } ) ;


return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ;


return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;


return Builder . CreateFence ( AtomicOrdering :: SequentiallyConsistent ) ;


template <class NodeTy> SDValue zmtarzmTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const {

template < class NodeTy > SDValue zmtarzmTargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal ) const {


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


Flag = IsLocal  ? zmtarzmII::MO_GOTOFF : IsCall ? zmtarzmII::MO_PLT32 : zmtarzmII::MO_GOT32;

Flag = IsLocal ? zmtarzmII :: MO_GOTOFF : IsCall ? zmtarzmII :: MO_PLT32 : zmtarzmII :: MO_GOT32 ;


SDValue GPReg = DAG.getRegister(zmtarzm::GP_REG, MVT::i32);

SDValue GPReg = DAG . getRegister ( zmtarzm :: GP_REG , MVT :: i32 ) ;


SDValue Wrapper = DAG.getNode(zmtarzmISD::GOT_ADDR, DL, Ty, GPReg, getTargetNode(N, Ty, DAG, zmtarzm::MO_GOT));

SDValue Wrapper = DAG . getNode ( zmtarzmISD :: GOT_ADDR , DL , Ty , GPReg , getTargetNode ( N , Ty , DAG , zmtarzm :: MO_GOT ) ) ;


return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, MachinePointerInfo::getGOT(DAG.getMachineFunction()));

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


SDValue TCPV = getTargetConstantPoolValue(N, Ty, DAG, Flag);

SDValue TCPV = getTargetConstantPoolValue ( N , Ty , DAG , Flag ) ;


SDValue TV = getTargetNode(N, DL, Ty, DAG, Flag);

SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ;


SDValue Hi = getTargetNode(N, Ty, DAG, zmtarzm::MO_ABS_HI);

SDValue Hi = getTargetNode ( N , Ty , DAG , zmtarzm :: MO_ABS_HI ) ;


SDValue Lo = getTargetNode(N, Ty, DAG, zmtarzm::MO_ABS_LO);

SDValue Lo = getTargetNode ( N , Ty , DAG , zmtarzm :: MO_ABS_LO ) ;


SDValue MoveHi = DAG.getNode(zmtarzmISD::MOVEHI, DL, MVT::i32, Hi);

SDValue MoveHi = DAG . getNode ( zmtarzmISD :: MOVEHI , DL , MVT :: i32 , Hi ) ;


return DAG . getNode ( zmtarzmISD :: LOAD_ADDR , DL , Ty , { TV , TCPV } ) ;

return DAG.getNode(zmtarzmISD::LOAD_ADDR, DL, Ty, {TV, TCPV});


DAG.getNode(ISD::ADD, DL, Ty, {DAG.getGLOBAL_OFFSET_TABLE(Ty), Addr});

DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ;


return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Result, MachinePointerInfo::getGOT(DAG.getMachineFunction()));

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


return DAG . getNode ( zmtarzmISD :: ORLO , DL , MVT :: i32 , MoveHi , Lo ) ;

return DAG.getNode(zmtarzmISD::ORLO, DL, MVT::i32, MoveHi, Lo);


zmtarzmTargetLowering::ConstraintType zmtarzmTargetLowering::getConstraintType(StringRef Constraint) const {

zmtarzmTargetLowering :: ConstraintType zmtarzmTargetLowering :: getConstraintType ( StringRef Constraint ) const {


return TargetLowering :: getConstraintType ( Constraint ) ;


SDValue zmtarzmTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: getDynamicTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned zmtarzmPCLabelIndex = CFI->createPICLabelUId();

unsigned zmtarzmPCLabelIndex = CFI -> createPICLabelUId ( ) ;


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());

IntegerType * CallTy = Type :: getIntNTy ( * DAG . getContext ( ) , Ty . getSizeInBits ( ) ) ;


const GlobalValue * GV = N -> getGlobal ( ) ;


zmtarzmConstantPoolValue *CPV = zmtarzmConstantPoolConstant::Create(N->getGlobal(), zmtarzmCP::CPValue, 4, zmtarzmCP::TLSGD, true, zmtarzmPCLabelIndex);

zmtarzmConstantPoolValue * CPV = zmtarzmConstantPoolConstant :: Create ( N -> getGlobal ( ) , zmtarzmCP :: CPValue , 4 , zmtarzmCP :: TLSGD , true , zmtarzmPCLabelIndex ) ;


SDValue PICLabel = DAG.getTargetConstant(zmtarzmPCLabelIndex, DL, MVT::i32);

SDValue PICLabel = DAG . getTargetConstant ( zmtarzmPCLabelIndex , DL , MVT :: i32 ) ;


SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);

SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , 0 , 0 ) ;


SDValue Load = SDValue(DAG.getMachineNode(#, DL, Ty, Addr), 0);

SDValue Load = SDValue ( DAG . getMachineNode ( # , DL , Ty , Addr ) , 0 ) ;

SDValue Load = SDValue ( DAG . getMachineNode ( zmtarzm :: PseudoTLSLA32 , DL , Ty , Addr ) , 0 ) ;

SDValue Load = SDValue(DAG.getMachineNode(zmtarzm::PseudoTLSLA32, DL, Ty, Addr), 0);


TargetLowering :: CallLoweringInfo CLI ( DAG ) ;


CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, CallTy, DAG.getExternalSymbol("__tls_get_addr", Ty), std::move(Args));

CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( "__tls_get_addr" , Ty ) , std :: move ( Args ) ) ;


Register zmtarzmTargetLowering::getExceptionPointerRegister(const Constant *PersonalityFn) const {

Register zmtarzmTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {


Register zmtarzmTargetLowering::getExceptionSelectorRegister(const Constant *PersonalityFn) const {

Register zmtarzmTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const {


ISD::NodeType getExtendForAtomicCmpSwapArg() const override {

ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override {


ISD::NodeType getExtendForAtomicOps() const override {

ISD :: NodeType getExtendForAtomicOps ( ) const override {


unsigned zmtarzmTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {

unsigned zmtarzmTargetLowering :: getInlineAsmMemConstraint ( StringRef ConstraintCode ) const {


return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


MVT zmtarzmTargetLowering::getPointerMemTy(const DataLayout &DL, uint32_t AS) const {

MVT zmtarzmTargetLowering :: getPointerMemTy ( const DataLayout & DL , uint32_t AS ) const {


if ( AS == WASM_ADDRESS_SPACE_EXTERNREF ) {

if (AS == WASM_ADDRESS_SPACE_EXTERNREF) {


if ( AS == WASM_ADDRESS_SPACE_FUNCREF ) {


MVT zmtarzmTargetLowering::getPointerTy(const DataLayout &DL, uint32_t AS) const {

MVT zmtarzmTargetLowering :: getPointerTy ( const DataLayout & DL , uint32_t AS ) const {


bool zmtarzmTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {

bool zmtarzmTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const {


if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) {

if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) {


AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;

AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ;


if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (LD->getExtensionType() != ISD::NON_EXTLOAD) {

if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) {


if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {

if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) {


if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


if ( Op -> getOpcode ( ) == ISD :: SUB ) {


Offset = DAG.getConstant(RHSC, DL, MVT::i8);

Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ;


if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if ( zmtarzm :: isProgramMemoryAccess ( ST ) ) {


LoadSDNode * LD = cast < LoadSDNode > ( N ) ;


if ( Op -> getOpcode ( ) == ISD :: ADD ) {


Offset = DAG . getConstant ( RHSC , VT ) ;


if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


uint64_t RHSC = RHS -> getZExtValue ( ) ;


bool zmtarzmTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const {


if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) {


AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ;


if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) {


if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) {


if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


if ( Op -> getOpcode ( ) == ISD :: SUB ) {


Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ;


if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if ( zmtarzm :: isProgramMemoryAccess ( ST ) ) {


LoadSDNode * LD = cast < LoadSDNode > ( N ) ;


if ( Op -> getOpcode ( ) == ISD :: ADD ) {


Offset = DAG . getConstant ( RHSC , VT ) ;


if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


uint64_t RHSC = RHS -> getZExtValue ( ) ;


std::pair<unsigned, const TargetRegisterClass *> zmtarzmTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {

std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const {


return std :: make_pair ( zmtarzm :: R14 , & # ) ;


return std :: make_pair ( zmtarzm :: C , & # ) ;


return std :: make_pair ( 0U , & zmtarzm :: GPR32RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: GPR64RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: FPR16RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: FPR32RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: FPR64RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: VPR64RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: FPR128RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: VPR128RegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


unsigned XRegFromAlias = zmtarzm::NoRegister;

unsigned XRegFromAlias = zmtarzm :: NoRegister ;


if (XRegFromAlias != zmtarzm::NoRegister) {

if ( XRegFromAlias != zmtarzm :: NoRegister ) {


return std :: make_pair ( XRegFromAlias , & # ) ;


assert(zmtarzm::F0_32 <= FReg && FReg <= zmtarzm::F31_32 && "Unknown fp-reg");

assert
(
zmtarzm
::
F0_32
<=
FReg
&&
FReg
<=
zmtarzm
::
F31_32
&&
"Unknown fp-reg"
)
;


unsigned RegNo = FReg - zmtarzm :: F0_32 ;


unsigned DReg = zmtarzm :: F0_64 + RegNo ;


return std :: make_pair ( DReg , & # ) ;


return std :: make_pair ( FReg , & # ) ;


return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);

return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const {


return std :: make_pair ( 0U , & zmtarzm :: GPRRegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: mGPRRegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: sGPRRegClass ) ;


return std :: make_pair ( zmtarzm :: R14 , & zmtarzm :: GPRRegClass ) ;


return std :: make_pair ( zmtarzm :: C , & zmtarzm :: CARRYRegClass ) ;


if ( Subtarget . hasFPUv2SingleFloat ( ) ) {


return std :: make_pair ( 0U , & zmtarzm :: sFPR32RegClass ) ;


if ( Subtarget . hasFPUv3SingleFloat ( ) ) {


if ( Subtarget . hasFPUv2DoubleFloat ( ) ) {


return std :: make_pair ( 0U , & zmtarzm :: sFPR64RegClass ) ;


if ( Subtarget . hasFPUv3DoubleFloat ( ) ) {


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


unsigned XRegFromAlias = zmtarzm :: NoRegister ;


if ( Constraint . lower ( ) == "{a0}" ) {


if ( Constraint . lower ( ) == "{a1}" ) {


if ( Constraint . lower ( ) == "{a2}" ) {


if ( Constraint . lower ( ) == "{a3}" ) {


if ( Constraint . lower ( ) == "{l0}" ) {


if ( Constraint . lower ( ) == "{l1}" ) {


if ( Constraint . lower ( ) == "{l2}" ) {


if ( Constraint . lower ( ) == "{l3}" ) {


if ( Constraint . lower ( ) == "{l4}" ) {


if ( Constraint . lower ( ) == "{l5}" ) {


if ( Constraint . lower ( ) == "{l6}" ) {


if ( Constraint . lower ( ) == "{l7}" ) {


if ( Constraint . lower ( ) == "{t0}" ) {


if ( Constraint . lower ( ) == "{t1}" ) {


if ( Constraint . lower ( ) == "{sp}" ) {


if ( Constraint . lower ( ) == "{lr}" ) {


if ( Constraint . lower ( ) == "{l8}" ) {


if ( Constraint . lower ( ) == "{l9}" ) {


if ( Constraint . lower ( ) == "{t2}" ) {


if ( Constraint . lower ( ) == "{t3}" ) {


if ( Constraint . lower ( ) == "{t4}" ) {


if ( Constraint . lower ( ) == "{t5}" ) {


if ( Constraint . lower ( ) == "{t6}" ) {


if ( Constraint . lower ( ) == "{t7}" ) {


if ( Constraint . lower ( ) == "{fp}" ) {


if ( Constraint . lower ( ) == "{t8}" ) {


if ( Constraint . lower ( ) == "{top}" ) {


if ( Constraint . lower ( ) == "{t9}" ) {


if ( Constraint . lower ( ) == "{bsp}" ) {


if ( Constraint . lower ( ) == "{r26}" ) {


if ( Constraint . lower ( ) == "{r27}" ) {


if ( Constraint . lower ( ) == "{gb}" ) {


if ( Constraint . lower ( ) == "{rgb}" ) {


if ( Constraint . lower ( ) == "{rdb}" ) {


if ( Constraint . lower ( ) == "{tb}" ) {


if ( Constraint . lower ( ) == "{rtb}" ) {


if ( Constraint . lower ( ) == "{svbr}" ) {


if ( Constraint . lower ( ) == "{tls}" ) {


if ( XRegFromAlias != zmtarzm :: NoRegister ) {


return std :: make_pair ( XRegFromAlias , & zmtarzm :: GPRRegClass ) ;


if ( Constraint . lower ( ) == "{fr0}" ) {


if ( Constraint . lower ( ) == "{vr0}" ) {


if ( Constraint . lower ( ) == "{fr1}" ) {


if ( Constraint . lower ( ) == "{vr1}" ) {


if ( Constraint . lower ( ) == "{fr2}" ) {


if ( Constraint . lower ( ) == "{vr2}" ) {


if ( Constraint . lower ( ) == "{fr3}" ) {


if ( Constraint . lower ( ) == "{vr3}" ) {


if ( Constraint . lower ( ) == "{fr4}" ) {


if ( Constraint . lower ( ) == "{vr4}" ) {


if ( Constraint . lower ( ) == "{fr5}" ) {


if ( Constraint . lower ( ) == "{vr5}" ) {


if ( Constraint . lower ( ) == "{fr6}" ) {


if ( Constraint . lower ( ) == "{vr6}" ) {


if ( Constraint . lower ( ) == "{fr7}" ) {


if ( Constraint . lower ( ) == "{vr7}" ) {


if ( Constraint . lower ( ) == "{fr8}" ) {


if ( Constraint . lower ( ) == "{vr8}" ) {


if ( Constraint . lower ( ) == "{fr9}" ) {


if ( Constraint . lower ( ) == "{vr9}" ) {


if ( Constraint . lower ( ) == "{fr10}" ) {


if ( Constraint . lower ( ) == "{vr10}" ) {


if ( Constraint . lower ( ) == "{fr11}" ) {


if ( Constraint . lower ( ) == "{vr11}" ) {


if ( Constraint . lower ( ) == "{fr12}" ) {


if ( Constraint . lower ( ) == "{vr12}" ) {


if ( Constraint . lower ( ) == "{fr13}" ) {


if ( Constraint . lower ( ) == "{vr13}" ) {


if ( Constraint . lower ( ) == "{fr14}" ) {


if ( Constraint . lower ( ) == "{vr14}" ) {


if ( Constraint . lower ( ) == "{fr15}" ) {


if ( Constraint . lower ( ) == "{vr15}" ) {


if ( Constraint . lower ( ) == "{fr16}" ) {


if ( Constraint . lower ( ) == "{vr16}" ) {


if ( Constraint . lower ( ) == "{fr17}" ) {


if ( Constraint . lower ( ) == "{vr17}" ) {


if ( Constraint . lower ( ) == "{fr18}" ) {


if ( Constraint . lower ( ) == "{vr18}" ) {


if ( Constraint . lower ( ) == "{fr19}" ) {


if ( Constraint . lower ( ) == "{vr19}" ) {


if ( Constraint . lower ( ) == "{fr20}" ) {


if ( Constraint . lower ( ) == "{vr20}" ) {


if ( Constraint . lower ( ) == "{fr21}" ) {


if ( Constraint . lower ( ) == "{vr21}" ) {


if ( Constraint . lower ( ) == "{fr22}" ) {


if ( Constraint . lower ( ) == "{vr22}" ) {


if ( Constraint . lower ( ) == "{fr23}" ) {


if ( Constraint . lower ( ) == "{vr23}" ) {


if ( Constraint . lower ( ) == "{fr24}" ) {


if ( Constraint . lower ( ) == "{vr24}" ) {


if ( Constraint . lower ( ) == "{fr25}" ) {


if ( Constraint . lower ( ) == "{vr25}" ) {


if ( Constraint . lower ( ) == "{fr26}" ) {


if ( Constraint . lower ( ) == "{vr26}" ) {


if ( Constraint . lower ( ) == "{fr27}" ) {


if ( Constraint . lower ( ) == "{vr27}" ) {


if ( Constraint . lower ( ) == "{fr28}" ) {


if ( Constraint . lower ( ) == "{vr28}" ) {


if ( Constraint . lower ( ) == "{fr29}" ) {


if ( Constraint . lower ( ) == "{vr29}" ) {


if ( Constraint . lower ( ) == "{fr30}" ) {


if ( Constraint . lower ( ) == "{vr30}" ) {


if ( Constraint . lower ( ) == "{fr31}" ) {


if ( Constraint . lower ( ) == "{vr31}" ) {


assert
(
zmtarzm
::
F0_32
<=
FReg
&&
FReg
<=
zmtarzm
::
F31_32
&&
"Unknown fp-reg"
)
;


if ( Subtarget . hasFPUv2DoubleFloat ( ) ) {


unsigned RegNo = FReg - zmtarzm :: F0_32 ;


unsigned DReg = zmtarzm :: F0_64 + RegNo ;


return std :: make_pair ( DReg , & zmtarzm :: sFPR64RegClass ) ;


if ( Subtarget . hasFPUv3DoubleFloat ( ) ) {


return std :: make_pair ( DReg , & zmtarzm :: FPR64RegClass ) ;


if ( Subtarget . hasFPUv2SingleFloat ( ) ) {


return std :: make_pair ( DReg , & zmtarzm :: sFPR32RegClass ) ;


return std :: make_pair ( FReg , & zmtarzm :: FPR32RegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const {


return std :: make_pair ( zmtarzm :: R14 , & # ) ;


return std :: make_pair ( zmtarzm :: C , & # ) ;


return std :: make_pair ( 0U , & zmtarzm :: I64RegClass ) ;


return std :: make_pair ( 0U , & zmtarzm :: V64RegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


unsigned XRegFromAlias = zmtarzm :: NoRegister ;


if ( XRegFromAlias != zmtarzm :: NoRegister ) {


return std :: make_pair ( XRegFromAlias , & # ) ;


assert
(
zmtarzm
::
F0_32
<=
FReg
&&
FReg
<=
zmtarzm
::
F31_32
&&
"Unknown fp-reg"
)
;


unsigned RegNo = FReg - zmtarzm :: F0_32 ;


unsigned DReg = zmtarzm :: F0_64 + RegNo ;


return std :: make_pair ( DReg , & # ) ;


return std :: make_pair ( FReg , & # ) ;


Register zmtarzmTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const {

Register zmtarzmTargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const {


Register Reg = MatchRegisterName ( RegName ) ;

Register Reg = MatchRegisterName(RegName);


const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();

const MCRegisterInfo * MRI = Subtarget -> getRegisterInfo ( ) ;


unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);

unsigned DwarfRegNum = MRI -> getDwarfRegNum ( Reg , false ) ;


if ( ! Subtarget -> isXRegisterReserved ( DwarfRegNum ) ) {


report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;

report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName)  + "\"."));


report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName) + "\"."));


MVT zmtarzmTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, EVT) const {

MVT zmtarzmTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const {


return ( getHasAlu32 ( ) && VT == MVT :: i32 ) ? MVT :: i32 : MVT :: i64 ;

return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64;


EVT zmtarzmTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const {

EVT zmtarzmTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {


if ( Subtarget . isScalableVector ( ) ) {


return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ;


return VT . changeVectorElementTypeToInteger ( ) ;


return Subtarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ;

return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;


SDValue zmtarzmTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const {

SDValue zmtarzmTargetLowering :: getStaticTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG , bool UseGOT ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned zmtarzmPCLabelIndex = CFI->createPICLabelUId();

unsigned zmtarzmPCLabelIndex = CFI -> createPICLabelUId ( ) ;


EVT Ty = getPointerTy(DAG.getDataLayout());

EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


zmtarzmCP::zmtarzmCPModifier Flag = UseGOT ? zmtarzmCP::TLSIE : zmtarzmCP::TLSLE;

zmtarzmCP :: zmtarzmCPModifier Flag = UseGOT ? zmtarzmCP :: TLSIE : zmtarzmCP :: TLSLE ;


bool AddCurrentAddr = UseGOT ? true : false;

bool AddCurrentAddr = UseGOT ? true : false ;


unsigned char PCAjust = UseGOT ? 4 : 0 ;


zmtarzmConstantPoolValue *CPV = zmtarzmConstantPoolConstant::Create(N->getGlobal(), zmtarzmCP::CPValue, PCAjust, Flag, AddCurrentAddr, zmtarzmPCLabelIndex);

zmtarzmConstantPoolValue * CPV = zmtarzmConstantPoolConstant :: Create ( N -> getGlobal ( ) , zmtarzmCP :: CPValue , PCAjust , Flag , AddCurrentAddr , zmtarzmPCLabelIndex ) ;


SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty);

SDValue CAddr = DAG . getTargetConstantPool ( CPV , Ty ) ;


SDValue PICLabel = DAG.getTargetConstant(zmtarzmPCLabelIndex, DL, MVT::i32);

SDValue PICLabel = DAG . getTargetConstant ( zmtarzmPCLabelIndex , DL , MVT :: i32 ) ;


auto *LRWGRS = DAG.getMachineNode(zmtarzm::PseudoTLSLA32, DL, {Ty, Ty}, {CAddr, PICLabel});

auto * LRWGRS = DAG . getMachineNode ( zmtarzm :: PseudoTLSLA32 , DL , { Ty , Ty } , { CAddr , PICLabel } ) ;


auto LRWADDGRS = DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));

auto LRWADDGRS = DAG . getNode ( ISD :: ADD , DL , Ty , SDValue ( LRWGRS , 0 ) , SDValue ( LRWGRS , 1 ) ) ;


Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS, MachinePointerInfo(N->getGlobal()));

Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ;


Load = SDValue(DAG.getMachineNode(zmtarzm::LRW32, DL, Ty, CAddr), 0);

Load = SDValue ( DAG . getMachineNode ( zmtarzm :: LRW32 , DL , Ty , CAddr ) , 0 ) ;


SDValue TPReg = DAG.getRegister(zmtarzm::R31, MVT::i32);

SDValue TPReg = DAG . getRegister ( zmtarzm :: R31 , MVT :: i32 ) ;


return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);

return DAG . getNode ( ISD :: ADD , DL , Ty , Load , TPReg ) ;


const zmtarzmSubtarget &getSubtarget() const {

const zmtarzmSubtarget & getSubtarget ( ) const {


const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {

const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


if ((zmtarzmISD::NodeType)Opcode == #) {

if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BR_CC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BR_CC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Call ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Call) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FPMOV ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FPMOV) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: GOTLoad ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::GOTLoad) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFI ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFI) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXTR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXTR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Ret ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Ret) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SBFX ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SBFX) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SELECT_CC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SELECT_CC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SETCC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SETCC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: THREAD_POINTER ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::THREAD_POINTER) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TLSDESCCALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TLSDESCCALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: WrapperLarge ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::WrapperLarge) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: WrapperSmall ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::WrapperSmall) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_BSL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_BSL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_MOVIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_MOVIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_MVNIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_MVNIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_FMOVIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_FMOVIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_CMP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_CMP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_CMPZ ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_CMPZ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_TST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_TST) {