llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;

return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( Opc , dl , MVT :: Other , RetOps ) ;

return DAG.getNode(Opc, dl, MVT::Other, RetOps);


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( zmtarzmISD :: RET_FLAG , DL , MVT :: Other , RetOps ) ;

return DAG.getNode(zmtarzmISD::RET_FLAG, DL, MVT::Other, RetOps);


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg , Flag ) ;

return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg, Flag);


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;

return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG & DAG ) const {


SDValue FalseV = Op . getOperand ( 2 ) ;


if (Op.getSimpleValueType() == XLenVT) {

if ( Op . getSimpleValueType ( ) == XLenVT ) {


if (CondV.getOperand(0).getSimpleValueType() == XLenVT) {

if ( CondV . getOperand ( 0 ) . getSimpleValueType ( ) == XLenVT ) {


if ( CondV . getOpcode ( ) == ISD :: SETCC ) {


SDValue LHS = CondV . getOperand ( 0 ) ;


SDValue RHS = CondV . getOperand ( 1 ) ;


auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));

auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( 2 ) ) ;


SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);

SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ;


SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};

SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ;


return DAG.getNode(zmtarzmISD::SELECT_CC, DL, VTs, Ops);

return DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VTs , Ops ) ;


SDValue Zero = DAG.getConstant(0, DL, XLenVT);

SDValue Zero = DAG . getConstant ( 0 , DL , XLenVT ) ;


SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);

SDValue SetNE = DAG . getConstant ( ISD :: SETNE , DL , XLenVT ) ;


SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};

SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ;


SDValue zmtarzmTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a quad-shift!"
)
;

assert(Op.getNumOperands() == 3 && "Not a quad-shift!");


unsigned VTBits = VT . getSizeInBits ( ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


assert ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, MVT::i64), Shamt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, Lo, RevShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, Shamt, DAG.getConstant(VTBits, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue Tmp3 = DAG.getNode(ISD::SHL, DL, VT, Lo, ExtraShAmt);

SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue Tmp4 = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt, DAG.getConstant(0, MVT::i64), ISD::SETGE, A64cc, DAG, DL);

SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = getzmtarzmCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, zmtarzmcc, DAG, DL);

SDValue Cmp = getzmtarzmCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , zmtarzmcc , DAG , DL ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, DAG.getConstant(0, Tmp4.getValueType()), Tmp4, A64cc);

SDValue Lo = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , DAG . getConstant ( 0 , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, Tmp3, FalseVal, A64cc);

SDValue Hi = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);

SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , 2 , DL ) ;


SDValue zmtarzmTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const {


unsigned VTBits = VT . getSizeInBits ( ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


assert ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, MVT::i64), Shamt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, Lo, RevShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, Shamt, DAG.getConstant(VTBits, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue Tmp3 = DAG.getNode(ISD::SHL, DL, VT, Lo, ExtraShAmt);

SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue Tmp4 = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt, DAG.getConstant(0, MVT::i64), ISD::SETGE, A64cc, DAG, DL);

SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = getzmtarzmCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, zmtarzmcc, DAG, DL);

SDValue Cmp = getzmtarzmCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , zmtarzmcc , DAG , DL ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, DAG.getConstant(0, Tmp4.getValueType()), Tmp4, A64cc);

SDValue Lo = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , DAG . getConstant ( 0 , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, Tmp3, FalseVal, A64cc);

SDValue Hi = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);

SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( { Lo , Hi } , DL ) ;

return DAG.getMergeValues({Lo, Hi}, DL);


SDValue zmtarzmTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const {


unsigned VTBits = VT . getSizeInBits ( ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


assert ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, MVT::i64), Shamt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, Lo, RevShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, Shamt, DAG.getConstant(VTBits, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue Tmp3 = DAG.getNode(ISD::SHL, DL, VT, Lo, ExtraShAmt);

SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue Tmp4 = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt, DAG.getConstant(0, MVT::i64), ISD::SETGE, A64cc, DAG, DL);

SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = getzmtarzmCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, zmtarzmcc, DAG, DL);

SDValue Cmp = getzmtarzmCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , zmtarzmcc , DAG , DL ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, DAG.getConstant(0, Tmp4.getValueType()), Tmp4, A64cc);

SDValue Lo = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , DAG . getConstant ( 0 , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, Tmp3, FalseVal, A64cc);

SDValue Hi = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);

SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , DL ) ;


SDValue zmtarzmTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const {

SDValue zmtarzmTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const {


assert(Op.getNumOperands() == 3 && "Not a double-shift!");

assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a double-shift!"
)
;


unsigned VTBits = VT . getSizeInBits ( ) ;


SDValue ShOpLo = Op . getOperand ( 0 ) ;


SDValue ShOpHi = Op . getOperand ( 1 ) ;


unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;

unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ;


assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);

assert ( Op . getOpcode ( ) == ISD :: SRA_PARTS || Op . getOpcode ( ) == ISD :: SRL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, DL, MVT::i64), ShAmt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, ShOpLo, ShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, ShAmt, DAG.getConstant(VTBits, DL, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, ShOpHi, RevShAmt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueVal = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, DL, MVT::i64), ISD::SETGE, DL, DAG);

SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ;


SDValue CCVal = DAG.getConstant(zmtarzmCC::GE, DL, MVT::i32);

SDValue CCVal = DAG . getConstant ( zmtarzmCC :: GE , DL , MVT :: i32 ) ;


SDValue FalseValLo = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueValLo = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue FalseValHi = DAG.getNode(Opc, DL, VT, ShOpHi, ShAmt);

SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ;


SDValue TrueValHi = Opc == ISD::SRA ? DAG.getNode(Opc, DL, VT, ShOpHi, DAG.getConstant(VTBits - 1, DL, MVT::i64)) : DAG.getConstant(0, DL, VT);

SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::CMOV, DL, VT, FalseVal, TrueVal, zmtarzmcc, CCR, Cmp);

SDValue Lo = DAG . getNode ( zmtarzmISD :: CMOV , DL , VT , FalseVal , TrueVal , zmtarzmcc , CCR , Cmp ) ;


SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ;


unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;

unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);

SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ;


SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);

SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, VT));

SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);

SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ;


SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);

SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ;


SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);

SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ;


SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;

SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt);

SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, VT));

SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , DL ) ;


SDValue zmtarzmTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const {

SDValue zmtarzmTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const {


assert(Op.getNumOperands() == 3 && "Not a double-shift!");

assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a double-shift!"
)
;


unsigned VTBits = VT . getSizeInBits ( ) ;


SDValue ShOpLo = Op . getOperand ( 0 ) ;


SDValue ShOpHi = Op . getOperand ( 1 ) ;


unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;

unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ;


assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);

assert ( Op . getOpcode ( ) == ISD :: SRA_PARTS || Op . getOpcode ( ) == ISD :: SRL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, DL, MVT::i64), ShAmt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, ShOpLo, ShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, ShAmt, DAG.getConstant(VTBits, DL, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, ShOpHi, RevShAmt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueVal = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, DL, MVT::i64), ISD::SETGE, DL, DAG);

SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ;


SDValue CCVal = DAG.getConstant(zmtarzmCC::GE, DL, MVT::i32);

SDValue CCVal = DAG . getConstant ( zmtarzmCC :: GE , DL , MVT :: i32 ) ;


SDValue FalseValLo = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueValLo = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue FalseValHi = DAG.getNode(Opc, DL, VT, ShOpHi, ShAmt);

SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ;


SDValue TrueValHi = Opc == ISD::SRA ? DAG.getNode(Opc, DL, VT, ShOpHi, DAG.getConstant(VTBits - 1, DL, MVT::i64)) : DAG.getConstant(0, DL, VT);

SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::CMOV, DL, VT, FalseVal, TrueVal, zmtarzmcc, CCR, Cmp);

SDValue Lo = DAG . getNode ( zmtarzmISD :: CMOV , DL , VT , FalseVal , TrueVal , zmtarzmcc , CCR , Cmp ) ;


SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ;


unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;

unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);

SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ;


SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);

SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, VT));

SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);

SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ;


SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);

SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ;


SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);

SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ;


SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;

SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt);

SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, VT));

SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( { Lo , Hi } , DL ) ;

return DAG.getMergeValues({Lo, Hi}, DL);


SDValue zmtarzmTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const {

SDValue zmtarzmTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const {


assert(Op.getNumOperands() == 3 && "Not a double-shift!");

assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a double-shift!"
)
;


unsigned VTBits = VT . getSizeInBits ( ) ;


SDValue ShOpLo = Op . getOperand ( 0 ) ;


SDValue ShOpHi = Op . getOperand ( 1 ) ;


unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;

unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ;


assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);

assert ( Op . getOpcode ( ) == ISD :: SRA_PARTS || Op . getOpcode ( ) == ISD :: SRL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, DL, MVT::i64), ShAmt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, ShOpLo, ShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, ShAmt, DAG.getConstant(VTBits, DL, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, ShOpHi, RevShAmt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueVal = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, DL, MVT::i64), ISD::SETGE, DL, DAG);

SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ;


SDValue CCVal = DAG.getConstant(zmtarzmCC::GE, DL, MVT::i32);

SDValue CCVal = DAG . getConstant ( zmtarzmCC :: GE , DL , MVT :: i32 ) ;


SDValue FalseValLo = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueValLo = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue FalseValHi = DAG.getNode(Opc, DL, VT, ShOpHi, ShAmt);

SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ;


SDValue TrueValHi = Opc == ISD::SRA ? DAG.getNode(Opc, DL, VT, ShOpHi, DAG.getConstant(VTBits - 1, DL, MVT::i64)) : DAG.getConstant(0, DL, VT);

SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::CMOV, DL, VT, FalseVal, TrueVal, zmtarzmcc, CCR, Cmp);

SDValue Lo = DAG . getNode ( zmtarzmISD :: CMOV , DL , VT , FalseVal , TrueVal , zmtarzmcc , CCR , Cmp ) ;


SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ;


unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;

unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);

SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ;


SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);

SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, VT));

SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);

SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ;


SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);

SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ;


SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);

SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ;


SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;

SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt);

SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, VT));

SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , DL ) ;


SDValue zmtarzmTargetLowering::lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerSPLATVECTOR ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
Op
.
getValueType
(
)
.
isVector
(
)
&&
"Vector type expected."
)
;

assert(Op.getValueType().isVector() && "Vector type expected.");


unsigned SrcSize = N1.getValueType().getSizeInBits();

unsigned SrcSize = N1 . getValueType ( ) . getSizeInBits ( ) ;


assert(SrcSize <= 128 && "Source must fit in an Altivec/VSX vector");


SDValue WideSrc = SrcSize == 128 ? N1 : widenVec(DAG, N1, DL);

SDValue WideSrc = SrcSize == 128 ? N1 : widenVec ( DAG , N1 , DL ) ;


unsigned TrgNumElts = TrgVT.getVectorNumElements();

unsigned TrgNumElts = TrgVT . getVectorNumElements ( ) ;


EVT EltVT = TrgVT.getVectorElementType();

EVT EltVT = TrgVT . getVectorElementType ( ) ;


unsigned WideNumElts = 128 / EltVT.getSizeInBits();

unsigned WideNumElts = 128 / EltVT . getSizeInBits ( ) ;


EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);

EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ;


unsigned SizeMult = SrcSize / TrgVT.getSizeInBits();

unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ;


for (unsigned i = 0; i < TrgNumElts; ++i) {

for ( unsigned i = 0 ; i < TrgNumElts ; ++ i ) {


for (unsigned i = 1; i < TrgNumElts; ++i) {

for ( unsigned i = 1 ; i < TrgNumElts ; ++ i ) {


ShuffV . push_back ( i * SizeMult - 1 ) ;


for (unsigned i = TrgNumElts; i < WideNumElts; ++i) {

for ( unsigned i = TrgNumElts ; i < WideNumElts ; ++ i ) {


ShuffV . push_back ( WideNumElts + 1 ) ;


SDValue Conv = DAG.getNode(ISD::BITCAST, DL, WideVT, WideSrc);

SDValue Conv = DAG . getNode ( ISD :: BITCAST , DL , WideVT , WideSrc ) ;


return DAG.getVectorShuffle(WideVT, DL, Conv, DAG.getUNDEF(WideVT), ShuffV);

return DAG . getVectorShuffle ( WideVT , DL , Conv , DAG . getUNDEF ( WideVT ) , ShuffV ) ;


SDValue zmtarzmTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


auto PtrVT = getPointerTy(MF.getDataLayout());

auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ;


const zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

const zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout()));

SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ;


const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( 2 ) ) -> getValue ( ) ;


return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV));

return DAG . getStore ( Op . getOperand ( 0 ) , DL , FI , Op . getOperand ( 1 ) , MachinePointerInfo ( SV ) ) ;


static SDValue zmtarzmTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const {

static SDValue zmtarzmTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const {


LLVMContext & Ctx = * DAG . getContext ( ) ;


assert
(
VT
.
isScalableVector
(
)
&&
"Expected a scalable vector."
)
;

assert(VT.isScalableVector() && "Expected a scalable vector.");


if (VT.getSizeInBits().getKnownMinSize() != zmtarzm::SVEBitsPerBlock) {

if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != zmtarzm :: SVEBitsPerBlock ) {


unsigned ElemSize = VT.getVectorElementType().getSizeInBits() / 8;

unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ;


unsigned ByteSize = VT.getSizeInBits().getKnownMinSize() / 8;

unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ;


EVT ByteVT = EVT::getVectorVT(Ctx, MVT::i8, { ByteSize, true });

EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ;


if (BV.getOperand(0).getOpcode() != ISD::FP_EXTEND) {

if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_EXTEND ) {


if (BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) {

if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


SDValue Op0 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(1));

SDValue Op0 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 1 ) ) ;


SDValue Op1 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(2));

SDValue Op1 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 2 ) ) ;


SDValue Op2 = DAG.getNode(ISD::MUL, DL, MVT::i32, N->getOperand(3), DAG.getConstant(ElemSize, DL, MVT::i32));

SDValue Op2 = DAG . getNode ( ISD :: MUL , DL , MVT :: i32 , N -> getOperand ( 3 ) , DAG . getConstant ( ElemSize , DL , MVT :: i32 ) ) ;


SDValue EXT = DAG.getNode(zmtarzmISD::EXT, DL, ByteVT, Op0, Op1, Op2);

SDValue EXT = DAG . getNode ( zmtarzmISD :: EXT , DL , ByteVT , Op0 , Op1 , Op2 ) ;


int Offset = BV.getOperand(0).getOperand(0).getConstantOperandVal(1);

int Offset = BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) ;


if ( Op0 . getValueType ( ) != MVT :: v8f16 ) {


if (!Check(BV.getOperand(i), Op0, 2 * i + Offset)) {

if ( ! Check ( BV . getOperand ( i ) , Op0 , 2 * i + Offset ) ) {


MVT ElemTy = ty(InpV).getVectorElementType();

MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ;


if ( Subtarget . isHVXVectorType ( ResTy ) ) {


return DAG . getNode ( ISD :: BITCAST , DL , VT , EXT ) ;

return DAG.getNode(ISD::BITCAST, DL, VT, EXT);


static SDValue zmtarzmTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const {


LLVMContext & Ctx = * DAG . getContext ( ) ;


if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != zmtarzm :: SVEBitsPerBlock ) {


unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ;


unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ;


EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ;


if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_EXTEND ) {


if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


SDValue Op0 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 1 ) ) ;


SDValue Op1 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 2 ) ) ;


SDValue Op2 = DAG . getNode ( ISD :: MUL , DL , MVT :: i32 , N -> getOperand ( 3 ) , DAG . getConstant ( ElemSize , DL , MVT :: i32 ) ) ;


SDValue EXT = DAG . getNode ( zmtarzmISD :: EXT , DL , ByteVT , Op0 , Op1 , Op2 ) ;


int Offset = BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) ;


if ( Op0 . getValueType ( ) != MVT :: v8f16 ) {


if ( ! Check ( BV . getOperand ( i ) , Op0 , 2 * i + Offset ) ) {


MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ;


if ( Subtarget . isHVXVectorType ( ResTy ) ) {


return DAG . getNode ( ISD :: ZERO_EXTEND , SDLoc ( Op ) , ResTy , InpV ) ;

return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), ResTy, InpV);


SDValue zmtarzmTargetLowering::lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
BV
.
getOpcode
(
)
==
ISD
::
BUILD_VECTOR
&&
"Unknown opcode!"
)
;

assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");


if (BV.getOperand(0).getOpcode() != ISD::FP_ROUND) {

if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_ROUND ) {


if (BV.getOperand(0).getOperand(0).getConstantOperandVal(1) != 0) {

if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) {


if (BV.getOperand(1).getOpcode() != ISD::FP_ROUND) {

if ( BV . getOperand ( 1 ) . getOpcode ( ) != ISD :: FP_ROUND ) {


if (BV.getOperand(1).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) {

if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


if (BV.getOperand(1).getOperand(0).getConstantOperandVal(1) != 0) {

if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) {


SDValue Op0 = BV.getOperand(0).getOperand(0).getOperand(0);

SDValue Op0 = BV . getOperand ( 0 ) . getOperand ( 0 ) . getOperand ( 0 ) ;


SDValue Op1 = BV.getOperand(1).getOperand(0).getOperand(0);

SDValue Op1 = BV . getOperand ( 1 ) . getOperand ( 0 ) . getOperand ( 0 ) ;


if ( Op0 . getValueType ( ) != MVT :: v4f32 ) {


if ( Op1 . getValueType ( ) != MVT :: v4f32 ) {


if (!Check(BV.getOperand(i * 2 + 0), Op0, i)) {

if ( ! Check ( BV . getOperand ( i * 2 + 0 ) , Op0 , i ) ) {


if (!Check(BV.getOperand(i * 2 + 1), Op1, i)) {

if ( ! Check ( BV . getOperand ( i * 2 + 1 ) , Op1 , i ) ) {


SDValue N1 = DAG.getNode(zmtarzmISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0, DAG.getConstant(0, dl, MVT::i32));

SDValue N1 = DAG . getNode ( zmtarzmISD :: VCVTN , dl , VT , DAG . getUNDEF ( VT ) , Op0 , DAG . getConstant ( 0 , dl , MVT :: i32 ) ) ;


return DAG.getNode(zmtarzmISD::VCVTN, dl, VT, N1, Op1, DAG.getConstant(1, dl, MVT::i32));

return DAG . getNode ( zmtarzmISD :: VCVTN , dl , VT , N1 , Op1 , DAG . getConstant ( 1 , dl , MVT :: i32 ) ) ;


bool zmtarzmTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {

bool zmtarzmTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const {


static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {

static void normaliseSetCC ( SDValue & LHS , SDValue & RHS , ISD :: CondCode & CC ) {


CC = ISD :: getSetCCSwappedOperands ( CC ) ;


SDValue zmtarzmTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {

SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: AND ) {


if ( N -> getOpcode ( ) == ISD :: OR ) {


return PerformORCombine ( N , DCI , getSubtarget ( ) ) ;

return PerformORCombine(N, DCI, getSubtarget());


if ( N -> getOpcode ( ) == ISD :: SHL ) {


return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ;

return PerformShiftCombine(N, DCI, getSubtarget());


if ( N -> getOpcode ( ) == ISD :: SRA ) {


if ( N -> getOpcode ( ) == ISD :: SRL ) {


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


return PerformIntrinsicCombine ( N , DCI . DAG ) ;


if ( N -> getOpcode ( ) == ISD :: NEON_VDUPLANE ) {

if (N->getOpcode() == ISD::NEON_VDUPLANE) {


if ( N -> getOpcode ( ) == ISD :: NEON_LD2DUP ) {

if (N->getOpcode() == ISD::NEON_LD2DUP) {


if ( N -> getOpcode ( ) == ISD :: NEON_LD3DUP ) {

if (N->getOpcode() == ISD::NEON_LD3DUP) {


if ( N -> getOpcode ( ) == ISD :: NEON_LD4DUP ) {

if (N->getOpcode() == ISD::NEON_LD4DUP) {


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_VOID ) {

if (N->getOpcode() == ISD::INTRINSIC_VOID) {


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {


if ( N -> getOpcode ( ) == ISD :: ADD ) {


return combineSelectAndUseCommutative ( N , DCI , false ) ;

return combineSelectAndUseCommutative(N, DCI, false);


if ( N -> getOpcode ( ) == ISD :: XOR ) {


if ( N -> getOpcode ( ) == ISD :: AND ) {


return combineSelectAndUseCommutative ( N , DCI , true ) ;

return combineSelectAndUseCommutative(N, DCI,  true);


if ( N -> getOpcode ( ) == ISD :: SUB ) {


SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: SUBX ) {


if ( N -> getOpcode ( ) == ISD :: ADDX ) {


if ( N -> getOpcode ( ) == ISD :: SETCC ) {


return combinezmtarzmSetCC ( N , DAG , Subtarget ) ;

return combinezmtarzmSetCC(N, DAG, Subtarget);


if ( N -> getOpcode ( ) == ISD :: BRCOND ) {


return combinezmtarzmBrCond ( N , DAG , Subtarget ) ;

return combinezmtarzmBrCond(N, DAG, Subtarget);


if ( N -> getOpcode ( ) == ISD :: ZERO_EXTEND ) {

if (N->getOpcode() == ISD::ZERO_EXTEND) {


if ( N -> getOpcode ( ) == ISD :: SIGN_EXTEND ) {

if (N->getOpcode() == ISD::SIGN_EXTEND) {


if ( N -> getOpcode ( ) == ISD :: SIGN_EXTEND_INREG ) {

if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {


return combineSIGN_EXTEND_INREG ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: MERGE_HIGH ) {

if (N->getOpcode() == ISD::MERGE_HIGH) {


if ( N -> getOpcode ( ) == ISD :: MERGE_LOW ) {


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


if ( N -> getOpcode ( ) == ISD :: STORE ) {


if ( N -> getOpcode ( ) == ISD :: VECTOR_SHUFFLE ) {

if (N->getOpcode() == ISD::VECTOR_SHUFFLE) {


return combineVECTOR_SHUFFLE ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_VECTOR_ELT ) {

if (N->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {


return combineEXTRACT_VECTOR_ELT ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: JOIN_DWORDS ) {

if (N->getOpcode() == ISD::JOIN_DWORDS) {


if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) {


if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) {


if ( N -> getOpcode ( ) == ISD :: BSWAP ) {


if ( N -> getOpcode ( ) == ISD :: BR_CCMASK ) {


if ( N -> getOpcode ( ) == ISD :: SELECT_CCMASK ) {

if (N->getOpcode() == ISD::SELECT_CCMASK) {


return combineSELECT_CCMASK ( N , DCI ) ;


if ( N -> getOpcode ( ) == ISD :: GET_CCMASK ) {

if (N->getOpcode() == ISD::GET_CCMASK) {


if ( N -> getOpcode ( ) == ISD :: SDIV ) {


if ( N -> getOpcode ( ) == ISD :: UDIV ) {


if ( N -> getOpcode ( ) == ISD :: SREM ) {


if ( N -> getOpcode ( ) == ISD :: UREM ) {


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: BITCAST ) {


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_ADD ) {

if (N->getOpcode() == ISD::VECREDUCE_ADD) {


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_SMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_SMIN) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_UMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_UMIN) {


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: CTPOP ) {


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


if ( N -> getOpcode ( ) == ISD :: SMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


if ( N -> getOpcode ( ) == ISD :: SMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


if ( N -> getOpcode ( ) == ISD :: UMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;

assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: ATOMIC_CMP_SWAP ) {

if (N->getOpcode() == ISD::ATOMIC_CMP_SWAP) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


assert
(
SDValue
(
N
,
0
)
.
getValueType
(
)
==
MVT
::
i128
&&
"unexpected load's value type"
)
;

assert(SDValue(N, 0).getValueType() == MVT::i128 && "unexpected load's value type");


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {