return static_cast < int > ( TTI :: TCC_Free ) ;


return getIntImmCost(Imm, Ty, CostKind);

return getIntImmCost ( Imm , Ty , CostKind ) ;


int NumConstants = divideCeil(Ty->getPrimitiveSizeInBits(), 64);

int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if (getIntImmCost(Imm, Ty, CostKind) <= NumConstants * TTI::TCC_Basic) {

if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


if ( Opcode == Instruction :: Select ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


int zmtarzmTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


bool zmtarzmAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const {

bool zmtarzmAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const {


case zmtarzm :: fixup_zmtarzm_pcrel_imm10_scale2 :


return ! isShiftedInt < 10 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_imm16_scale2 :


return ! isShiftedInt < 16 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_imm26_scale2 :


return ! isShiftedInt < 26 , 1 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_pcrel_uimm7_scale4 :


return ! isShiftedInt < 8 , 2 > ( Offset ) ;


case zmtarzm :: fixup_zmtarzm_thumb_br :


return Offset > 2050 || Offset < - 2044 ;


case zmtarzm :: fixup_zmtarzm_thumb_bcc :


case zmtarzm :: fixup_zmtarzm_adr_pcrel_10 :


return Offset > 1024 || Offset < 4 || ( Offset - 4 ) & 3 ;

return Offset > 1024 || Offset < 4 || (Offset-4) & 3;


case zmtarzm :: fixup_zmtarzm_thumb_cp :


unsigned zmtarzmAsmBackend::getRelaxedOpcode(unsigned Op) const {

unsigned zmtarzmAsmBackend :: getRelaxedOpcode ( unsigned Op ) const {


void zmtarzmAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {

void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand &MO = MI->getOperand(OpNo);

const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


llvm_unreachable
(
"not implemented"
)
;


O << getRegisterName ( MO . getReg ( ) ) ;


case MachineOperand :: MO_MachineBasicBlock :


O << * MO . getMBB ( ) -> getSymbol ( ) ;


case MachineOperand :: MO_GlobalAddress :


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


case MachineOperand :: MO_ConstantPoolIndex :


O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


case MachineOperand :: MO_BlockAddress :


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


case MachineOperand :: MO_ExternalSymbol :


case MachineOperand :: MO_JumpTableIndex :


O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_R_DISP32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_R_DISP32) {


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;

Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");


case zmtarzm :: fixup_zmtarzm_10_pcrel :


case zmtarzm :: fixup_zmtarzm_16_pcrel :


case zmtarzm :: fixup_zmtarzm_16_pcrel_byte :


case zmtarzm :: fixup_zmtarzm_2x_pcrel :


case zmtarzm :: fixup_zmtarzm_GOT_HI16 :


case zmtarzm :: fixup_zmtarzm_GOT_LO16 :


case zmtarzm :: fixup_zmtarzm_jump_target :


case zmtarzm :: fixup_zmtarzm_cond_branch12_target :


bool zmtarzmInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {

bool zmtarzmInstrInfo :: isBranchOffsetInRange ( unsigned BranchOpc , int64_t BrOffset ) const {


llvm_unreachable
(
"Unexpected opcode!"
)
;


static inline bool IsBRF(unsigned BrOpc) {

static inline bool IsBRF ( unsigned BrOpc ) {


static inline bool IsBRT(unsigned BrOpc) {

static inline bool IsBRT ( unsigned BrOpc ) {


static inline bool IsBRU(unsigned BrOpc) {

static inline bool IsBRU ( unsigned BrOpc ) {


static inline bool IsBR_JT(unsigned BrOpc) {

static inline bool IsBR_JT ( unsigned BrOpc ) {


static inline bool IsCondBranch(unsigned BrOpc) {

static inline bool IsCondBranch ( unsigned BrOpc ) {


bool zmtarzmInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const {

bool zmtarzmInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {


if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF)) {

if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) {


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


zmtarzmTargetLowering::ConstraintType zmtarzmTargetLowering::getConstraintType(StringRef Constraint) const {

zmtarzmTargetLowering :: ConstraintType zmtarzmTargetLowering :: getConstraintType ( StringRef Constraint ) const {


return TargetLowering :: getConstraintType ( Constraint ) ;


unsigned zmtarzmMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

unsigned zmtarzmMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


assert(MO.isReg() && "Expected a register.");

assert
(
MO
.
isReg
(
)
&&
"Expected a register."
)
;


llvm_unreachable
(
"Invalid mask register."
)
;


static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {

static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) {


llvm_unreachable("Can't handle nested target expression");

llvm_unreachable
(
"Can't handle nested target expression"
)
;


fixELFSymbolsInTLSFixupsImpl ( cast < MCExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ;


fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ;


const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ;


fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


StringRef zmtarzmMCExpr::getVariantKindName(VariantKind Kind) {

StringRef zmtarzmMCExpr :: getVariantKindName ( VariantKind Kind ) {


llvm_unreachable("Invalid ELF symbol kind");

llvm_unreachable
(
"Invalid ELF symbol kind"
)
;


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G3 :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G2 :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G2_S :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G2_NC :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G1_S :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_G1 :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G1_NC :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G0 :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G0_S :


case zmtarzmMCExpr :: VK_zmtarzm_ABS_G0_NC :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_G2 :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_G1_NC :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_G0 :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_G0_NC :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_HI12 :


case zmtarzmMCExpr :: VK_zmtarzm_DTPREL_LO12 :


case zmtarzmMCExpr :: VK_zmtarzm_TPREL_G2 :


case zmtarzmMCExpr :: VK_zmtarzm_TPREL_G1 :


case zmtarzmMCExpr :: VK_zmtarzm_TPREL_G1_NC :


case zmtarzmMCExpr :: VK_zmtarzm_TPREL_G0 :


case zmtarzmMCExpr :: VK_zmtarzm_TPREL_LO12_NC :


case zmtarzmMCExpr :: VK_zmtarzm_TLSDESC_LO12 :


case zmtarzmMCExpr :: VK_zmtarzm_GOT_PAGE :


case zmtarzmMCExpr :: VK_zmtarzm_GOT_LO12 :


case zmtarzmMCExpr :: VK_zmtarzm_GOTTPREL_LO12_NC :


case zmtarzmMCExpr :: VK_zmtarzm_GOTTPREL_G1 :


case zmtarzmMCExpr :: VK_zmtarzm_GOTTPREL_G0_NC :


case zmtarzmMCExpr :: VK_zmtarzm_TLSDESC_PAGE :


StringRef zmtarzmMCExpr :: getVariantKindName ( VariantKind Kind ) {


llvm_unreachable
(
"Invalid ELF symbol kind"
)
;


case zmtarzmMCExpr :: VK_zmtarzm_PCREL :


case zmtarzmMCExpr :: VK_zmtarzm_GOTPC :


case zmtarzmMCExpr :: VK_zmtarzm_GOTOFF :


case zmtarzmMCExpr :: VK_zmtarzm_TPOFF :


case zmtarzmMCExpr :: VK_zmtarzm_TLSGD :


case zmtarzmMCExpr :: VK_zmtarzm_ADDR_HI16 :


case zmtarzmMCExpr :: VK_zmtarzm_ADDR_LO16 :


bool zmtarzmRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const {


bool zmtarzmAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const {

bool zmtarzmAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const {


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_PC_LO32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_PC_LO32) {


if (Kind >= FirstLiteralRelocationKind){

if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind;

return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;

Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;

Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");


Ctx.reportError(Fixup.getLoc(), "1-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "8-byte pc-relative data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "1-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "2-byte data relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative srel32 relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_hi32 relocation is not supported");


Ctx.reportError(Fixup.getLoc(), "A non pc-relative pc_lo32 relocation is not supported");


case zmtarzm :: fixup_zmtarzm_got_hi32 :


case zmtarzm :: fixup_zmtarzm_got_lo32 :


case zmtarzm :: fixup_zmtarzm_gotoff_hi32 :


case zmtarzm :: fixup_zmtarzm_gotoff_lo32 :


case zmtarzm :: fixup_zmtarzm_plt_hi32 :


case zmtarzm :: fixup_zmtarzm_plt_lo32 :


case zmtarzm :: fixup_zmtarzm_tls_gd_hi32 :


case zmtarzm :: fixup_zmtarzm_tls_gd_lo32 :


case zmtarzm :: fixup_zmtarzm_tpoff_hi32 :


case zmtarzm :: fixup_zmtarzm_tpoff_lo32 :


unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;


case zmtarzm :: fixup_zmtarzm_RELATIVE :


case zmtarzm :: fixup_zmtarzm_JUMP_SLOT :


case zmtarzm :: fixup_zmtarzm_TLS_DTPMOD32 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPMOD64 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPREL32 :


case zmtarzm :: fixup_zmtarzm_TLS_DTPREL64 :


zmtarzmMCAsmInfo::zmtarzmMCAsmInfo(const Target &T, StringRef TT) {

zmtarzmMCAsmInfo :: zmtarzmMCAsmInfo ( const Target & T , StringRef TT ) {


ExceptionsType = ExceptionHandling :: DwarfCFI ;


explicit zmtarzmAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {

explicit zmtarzmAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {


void zmtarzmAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock *MBB) {

void zmtarzmAsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock * MBB ) {


AsmPrinter :: EmitBasicBlockStart ( MBB ) ;


OutStreamer
->
EmitRawText
(
StringRef
(
"\t.pragma \"nounroll\";\n"
)
)
;


void zmtarzmAsmPrinter :: EmitConstantPool ( ) {


const MachineConstantPool *MCP = MF->getConstantPool();

const MachineConstantPool * MCP = MF -> getConstantPool ( ) ;


const std::vector<MachineConstantPoolEntry> &CP = MCP->getConstants();

const std :: vector < MachineConstantPoolEntry > & CP = MCP -> getConstants ( ) ;


zmtarzmTargetMachine &TTM = static_cast<zmtarzmTargetMachine &>(TM);

zmtarzmTargetMachine & TTM = static_cast < zmtarzmTargetMachine & > ( TM ) ;


const std::vector<MachineConstantPoolEntry> &CP = TTM.MCP.getConstants();

const std :: vector < MachineConstantPoolEntry > & CP = TTM . MCP . getConstants ( ) ;


const MCSection *S = TM.getTargetLowering()->getObjFileLowering().getDataSection();

const MCSection * S = TM . getTargetLowering ( ) -> getObjFileLowering ( ) . getDataSection ( ) ;


for (unsigned i = 0, e = CP.size(); i != e; ++i) {

for ( unsigned i = 0 , e = CP . size ( ) ; i != e ; ++ i ) {


const MachineConstantPoolEntry &CPE = CP[i];

const MachineConstantPoolEntry & CPE = CP [ i ] ;


unsigned Align = CPE . getAlignment ( ) ;


unsigned AlignMask = CPE.getAlignment() - 1;

unsigned AlignMask = CPE . getAlignment ( ) - 1 ;


unsigned NewOffset = (Offset + AlignMask) & ~AlignMask;

unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ;


OS << "\tstring\tbyte[" << (NewOffset - Offset) << "] 0\n";

OS
<<
"\tstring\tbyte["
<<
(
NewOffset
Offset
)
<<
"] 0\n"
;


Offset = NewOffset + TM.getDataLayout()->getTypeAllocSize(Ty);

Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ;


MCSymbol * Symbol = GetCPISymbol ( i ) ;


HackStreamer ( OutStreamer ) << OS . str ( ) ;


if ( CPE . isMachineConstantPoolEntry ( ) ) {


EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ;


EmitGlobalConstant ( CPE . Val . ConstVal ) ;


MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();

MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ;


zmtarzmTargetStreamer &TTS = static_cast<zmtarzmTargetStreamer &>(TS);

zmtarzmTargetStreamer & TTS = static_cast < zmtarzmTargetStreamer & > ( TS ) ;


TTS . EmitConstantPoolEntry ( CP [ cpi ++ ] ) ;


void zmtarzmAsmPrinter :: EmitConstantPool ( ) {


const MachineConstantPool * MCP = MF -> getConstantPool ( ) ;


const std :: vector < MachineConstantPoolEntry > & CP = MCP -> getConstants ( ) ;


zmtarzmTargetMachine & TTM = static_cast < zmtarzmTargetMachine & > ( TM ) ;


const std :: vector < MachineConstantPoolEntry > & CP = TTM . MCP . getConstants ( ) ;


const MCSection * S = TM . getTargetLowering ( ) -> getObjFileLowering ( ) . getDataSection ( ) ;


for ( unsigned i = 0 , e = CP . size ( ) ; i != e ; ++ i ) {


const MachineConstantPoolEntry & CPE = CP [ i ] ;


unsigned Align = CPE . getAlignment ( ) ;


unsigned AlignMask = CPE . getAlignment ( ) - 1 ;


unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ;


OS
<<
"\tstring\tbyte["
<<
(
NewOffset
Offset
)
<<
"] 0\n"
;


Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ;


MCSymbol * Symbol = GetCPISymbol ( i ) ;


HackStreamer ( OutStreamer ) << OS . str ( ) ;


if ( CPE . isMachineConstantPoolEntry ( ) ) {


EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ;


EmitGlobalConstant ( CPE . Val . ConstVal ) ;


MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ;


zmtarzmTargetStreamer & TTS = static_cast < zmtarzmTargetStreamer & > ( TS ) ;


TTS . EmitConstantPoolEntry ( CP [ cpi ++ ] ) ;


void zmtarzmAsmPrinter::EmitEndOfAsmFile(Module &M) {

void zmtarzmAsmPrinter :: EmitEndOfAsmFile ( Module & M ) {


zmtarzmTargetStreamer & CTS = static_cast < zmtarzmTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;

zmtarzmTargetStreamer &CTS = static_cast<zmtarzmTargetStreamer &>(*OutStreamer->getTargetStreamer());


if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) {


const TargetLoweringObjectFile &TLOF = getObjFileLowering();

const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ;


OutStreamer . SwitchSection ( TLOF . getTextSection ( ) ) ;


MCSymbol *EndOfTextLabel = OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));

MCSymbol * EndOfTextLabel = OutContext . GetOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ;


OutStreamer . EmitLabel ( EndOfTextLabel ) ;


void zmtarzmAsmPrinter :: EmitFunctionEntryLabel ( ) {


getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ;


OutStreamer . EmitLabel ( CurrentFnSym ) ;


void zmtarzmAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {

void zmtarzmAsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) {


zmtarzmoldTargetStreamer *TS = static_cast<zmtarzmoldTargetStreamer *>(OutStreamer->getTargetStreamer());

zmtarzmoldTargetStreamer * TS = static_cast < zmtarzmoldTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ;


if (GVSym->isDefined() || GVSym->isVariable()) {

if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) {


report_fatal_error("symbol '" + Twine(GVSym->getName()) + "' is already defined");

report_fatal_error
(
"symbol '"
+
Twine
(
GVSym
->
getName
(
)
)
+
"' is already defined"
)
;


SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);

SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ;


MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));

MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ;


GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ;


SectionKind GVKind = getObjFileLowering().getKindForGlobal(GV, TM);

SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ;


if ((!GVKind.isCommon() && !GVKind.isBSS() && !GVKind.isData() &&!GVKind.isReadOnly()) || GVKind.isMergeable2ByteCString() || GVKind.isMergeable4ByteCString()) {

if ( ( ! GVKind . isCommon ( ) && ! GVKind . isBSS ( ) && ! GVKind . isData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) {


report_fatal_error("Encountered a global variable kind that is not supported yet.");


MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(getObjFileLowering().SectionForGlobal(GV, GVKind, TM));

MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ;


OutStreamer -> SwitchSection ( Csect ) ;


const DataLayout &DL = GV->getParent()->getDataLayout();

const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;


uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());

uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ;


unsigned Align = DL.getPreferredAlignment(GV);

unsigned Align = DL . getPreferredAlignment ( GV ) ;


MCSection *TheSection = getObjFileLowering().SectionForGlobal(GV, GVKind, TM);

MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ;


OutStreamer -> SwitchSection ( TheSection ) ;


EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ;


if (GVKind.isCommon() || GVKind.isBSSLocal()) {

if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) {


unsigned Align = GV->getAlignment() ? GV->getAlignment() : DL.getPreferredAlignment(GV);

unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ;


OutStreamer->EmitXCOFFLocalCommonSymbol(GVSym, Size, Csect->getQualNameSymbol(), Align);

OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ;


OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ;


EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ;


OutStreamer -> EmitLabel ( EmittedInitSym ) ;


EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ;


void zmtarzmAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {

void zmtarzmAsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) {


zmtarzmoldTargetStreamer *TS = static_cast<zmtarzmoldTargetStreamer *>(OutStreamer->getTargetStreamer());

zmtarzmoldTargetStreamer * TS = static_cast < zmtarzmoldTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ;


if (GVSym->isDefined() || GVSym->isVariable()) {

if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) {


report_fatal_error("symbol '" + Twine(GVSym->getName()) + "' is already defined");

report_fatal_error
(
"symbol '"
+
Twine
(
GVSym
->
getName
(
)
)
+
"' is already defined"
)
;


SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);

SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ;


MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));

MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ;


GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ;


SectionKind GVKind = getObjFileLowering().getKindForGlobal(GV, TM);

SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ;


if ((!GVKind.isCommon() && !GVKind.isBSS() && !GVKind.isData() &&!GVKind.isReadOnly()) || GVKind.isMergeable2ByteCString() || GVKind.isMergeable4ByteCString()) {

if ( ( ! GVKind . isCommon ( ) && ! GVKind . isBSS ( ) && ! GVKind . isData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) {


report_fatal_error("Encountered a global variable kind that is not supported yet.");


MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(getObjFileLowering().SectionForGlobal(GV, GVKind, TM));

MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ;


OutStreamer -> SwitchSection ( Csect ) ;


const DataLayout &DL = GV->getParent()->getDataLayout();

const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;


uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());

uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ;


unsigned Align = DL.getPreferredAlignment(GV);

unsigned Align = DL . getPreferredAlignment ( GV ) ;


MCSection *TheSection = getObjFileLowering().SectionForGlobal(GV, GVKind, TM);

MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ;


OutStreamer -> SwitchSection ( TheSection ) ;


EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ;


if (GVKind.isCommon() || GVKind.isBSSLocal()) {

if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) {


unsigned Align = GV->getAlignment() ? GV->getAlignment() : DL.getPreferredAlignment(GV);

unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ;


OutStreamer->EmitXCOFFLocalCommonSymbol(GVSym, Size, Csect->getQualNameSymbol(), Align);

OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ;


OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ;


EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ;


OutStreamer -> EmitLabel ( EmittedInitSym ) ;


EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ;


void zmtarzmAsmPrinter::EmitInstruction(const MachineInstr *MI) {

void zmtarzmAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {


if (emitPseudoExpansionLowering(*OutStreamer, MI)) {

if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) {


LowerzmtarzmMachineInstrToMCInst ( MI , TmpInst , * this ) ;


EmitToStreamer ( * OutStreamer , TmpInst ) ;


void zmtarzmAsmPrinter::emitStartOfAsmFile(Module &M) {

void zmtarzmAsmPrinter :: emitStartOfAsmFile ( Module & M ) {


OutStreamer -> emitAssemblerFlag ( MCAF_SyntaxUnified ) ;


if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) {


if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) {


if ( TM . getTargetTriple ( ) . isThumb ( ) ) {


OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ;


void getAnalysisUsage(AnalysisUsage &AU) const {

void getAnalysisUsage ( AnalysisUsage & AU ) const {


AU . addRequired < zmtarzmMetadata > ( ) ;


MachineLocation zmtarzmAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {

MachineLocation zmtarzmAsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const {


assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");

assert
(
MI
->
getNumOperands
(
)
==
4
&&
"Invalid no. of machine operands!"
)
;


assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && "Unexpected MachineOperand types");

assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
"Unexpected MachineOperand types"
)
;


return MachineLocation ( MI -> getOperand ( 0 ) . getReg ( ) , MI -> getOperand ( 1 ) . getImm ( ) ) ;


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


extern "C" void LLVMInitializezmtarzmAsmPrinter() {

extern "C" void LLVMInitializezmtarzmAsmPrinter ( ) {


RegisterAsmPrinter < zmtarzmAsmPrinter > X ( ThezmtarzmTarget ) ;


bool zmtarzmAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) {

bool zmtarzmAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) {


bool zmtarzmAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) {

bool zmtarzmAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) {


void zmtarzmInstPrinter::printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) {

void zmtarzmInstPrinter :: printInlineJT32 ( const MCInst * MI , int opNum , raw_ostream & O ) {


report_fatal_error
(
"can't handle InlineJT32"
)
;


void zmtarzmInstPrinter::printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) {

void zmtarzmInstPrinter :: printInlineJT ( const MCInst * MI , int opNum , raw_ostream & O ) {


report_fatal_error
(
"can't handle InlineJT"
)
;


void zmtarzmAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {

void zmtarzmAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) {


if (MI->getOperand(opNum + 1).isImm() && MI->getOperand(opNum + 1).getImm() == 0) {

if ( MI -> getOperand ( opNum + 1 ) . isImm ( ) && MI -> getOperand ( opNum + 1 ) . getImm ( ) == 0 ) {


void zmtarzmAsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) {

void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand &MO = MI->getOperand(OpNo);

const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if (MO.getType() == MachineOperand::MO_Register) {

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if (MO.getType() == MachineOperand::MO_Immediate) {

if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if (MO.getType() == MachineOperand::MO_MachineBasicBlock) {

if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if (MO.getType() == MachineOperand::MO_GlobalAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if (MO.getType() == MachineOperand::MO_ConstantPoolIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if (MO.getType() == MachineOperand::MO_BlockAddress) {

if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if (MO.getType() == MachineOperand::MO_ExternalSymbol) {

if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if (MO.getType() == MachineOperand::MO_JumpTableIndex) {

if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex();

O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) {


const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


O << getRegisterName ( MO . getReg ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) {


if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) {


O << * MO . getMBB ( ) -> getSymbol ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) {


O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) {


O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {


if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) {


O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


llvm_unreachable
(
"not implemented"
)
;


void zmtarzmAsmPrinter::PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Code) const {

void zmtarzmAsmPrinter :: PrintSpecial ( const MCInst * MI , raw_ostream & O , const char * Code ) const {


assert ( strcmp ( Code , "arguments" ) == 0 ) ;


for (unsigned i = 0; i < MI->getNumOperands() - 1; i++) {

for ( unsigned i = 0 ; i < MI -> getNumOperands ( ) - 1 ; i ++ ) {


bool zmtarzmAsmPrinter::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) {


MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ;

MCSubtargetInfo &NewSTI = OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());


NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


void zmtarzmFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineBasicBlock::iterator MBBI = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . end ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


LastFrameDestroy = std::prev(MBBI, CSI.size());

LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ;


uint64_t StackSize = MFI.getStackSize();

uint64_t StackSize = MFI . getStackSize ( ) ;


uint64_t ActualSize = CFI->getCalleeSaveAreaSize() + CFI->getVarArgsSaveSize();

uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ;


BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg).addReg(FPReg).setMIFlag(MachineInstr::NoFlags);

BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ;


adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize), MachineInstr::FrameDestroy);

adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize, MachineInstr::FrameDestroy);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ;


if (materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDrr ) , zmtarzm :: SP ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


if (!materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( ! materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI(MBB, MBBI, DL, TII.get(zmtarzm::ADDri), zmtarzm::SP).addReg(StackReg).addImm(StackSize).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDri ) , zmtarzm :: SP ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


void zmtarzmFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const RegisterInfo *RI = STI.getRegisterInfo();

const RegisterInfo * RI = STI . getRegisterInfo ( ) ;


MachineFunctionInfo *CFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


MachineBasicBlock::iterator MBBI = MBB.begin();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ;


const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: NIE ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::NIE));


uint64_t StackSize = MFI . getStackSize ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


unsigned spillAreaSize = CFI->getCalleeSaveAreaSize();

unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ;


uint64_t ActualSize = spillAreaSize + CFI->getVarArgsSaveSize();

uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, ActualSize));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


std :: advance ( MBBI , CSI . size ( ) ) ;


int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());

int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ;


unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;

unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ;


for ( unsigned i = 0 ; i < Num ; i ++ ) {


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, RI->getDwarfRegNum(Reg, true) + i, Offset + i * 4));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RI->getDwarfRegNum(FPReg, true)));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(StackSize - ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


const zmtarzmRegisterInfo *RI = STI.getRegisterInfo();

const zmtarzmRegisterInfo * RI = STI . getRegisterInfo ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


Align MaxAlignment = MFI . getMaxAlign ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: ANDNI32 ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::ANDNI32), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));


unsigned ShiftAmount = Log2(MaxAlignment);

unsigned ShiftAmount = Log2 ( MaxAlignment ) ;


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::GPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI32 ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI32), VR).addReg(SPReg).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI32 ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI32), SPReg).addReg(VR).addImm(ShiftAmount);


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::mGPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: mGPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , VR ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), VR).addReg(SPReg);


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , SPReg ) . addReg ( VR ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), SPReg).addReg(VR);


if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), BPReg).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , BPReg ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , BPReg ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), BPReg).addReg(SPReg);


adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, #, #), STI(STI) {

zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , # , # ) , STI ( STI ) {

zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , 4 , 0 ) , STI ( STI ) {

zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(STI) {


zmtarzmFrameLowering :: zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , 8 , 0 ) , STI ( STI ) {

zmtarzmFrameLowering::zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(STI) {


bool zmtarzmFrameLowering::hasFP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasFP ( const MachineFunction & MF ) const {


return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();

return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


bool zmtarzmFrameLowering::isShrinkWrappingProfitable() const {

bool zmtarzmFrameLowering :: isShrinkWrappingProfitable ( ) const {


void zmtarzmFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const {

void zmtarzmFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const {


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


MRI . setPhysRegUnused ( zmtarzm :: R6 ) ;


MRI . setPhysRegUnused ( zmtarzm :: R7 ) ;


MRI . setPhysRegUnused ( zmtarzm :: R8 ) ;


MRI . setPhysRegUnused ( zmtarzm :: R9 ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( # ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetRegisterClass *RC = &zmtarzm::R32CRegClass;

const TargetRegisterClass * RC = & zmtarzm :: R32CRegClass ;


RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


zmtarzmFunctionInfo *FI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * FI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


CallingConv::ID CallConv = MF.getFunction()->getCallingConv();

CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ;


bool requiresRA = CallConv == CallingConv::MBLAZE_INTR;

bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ;


if (MFI->adjustsStack() || requiresRA) {

if ( MFI -> adjustsStack ( ) || requiresRA ) {


MFI -> CreateFixedObject ( 4 , 0 , true ) ;


MFI -> CreateFixedObject ( 4 , 4 , true ) ;


void zmtarzmFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) const {

void zmtarzmFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


bool zmtarzmFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);

TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ;


assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg()).addReg(zmtarzm::R15);

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg());

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) ;


BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: MOV32mrpop ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::MOV32mrpop), CSI[i].getReg()).addReg(zmtarzm::R15);


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;

const bool IsLiveIn = MRI.isLiveIn(Reg);


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: MOV32rmpush ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::MOV32rmpush), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
16
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 16 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PHAstk ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PHAstk)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;