unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_tuple ) {

if (IntNo == Intrinsic::zmtarzm_tuple) {


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


bool SmallTuple = Size <= zmtarzmTargetMachine::SmallTupleLimit;

bool SmallTuple = Size <= zmtarzmTargetMachine :: SmallTupleLimit ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


unsigned Cmd = SmallTuple ? zmtarzmISD::TUPLE : zmtarzmISD::TUPLEVAR;

unsigned Cmd = SmallTuple ? zmtarzmISD :: TUPLE : zmtarzmISD :: TUPLEVAR ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);

return DAG . getNode ( ISD :: ADD , DL , VT , GlobalBase , Addr ) ;


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


return DAG . getNode ( Cmd , DL , MVT :: zmtarzmTuple , Ops ) ;

return DAG.getNode(Cmd, DL, MVT::zmtarzmTuple, Ops);


EVT PtrVT = getPointerTy(DAG.getDataLayout());

EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( SPISD :: RET_FLAG , dl , MVT :: Other , & RetOps [ 0 ] , RetOps . size ( ) ) ;

return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, &RetOps[0], RetOps.size());


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {


report_fatal_error
(
"VarArg not supported"
)
;


MachineFunction &MF = DAG.getMachineFunction();


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeReturn ( Outs , RetCC_zmtarzm ) ;


if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) {


for (unsigned i = 0; i != RVLocs.size(); ++i)

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i )


DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


AnalyzeReturnValues ( CCInfo , RVLocs , Outs ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ;


analyzeOutputArgs ( CCInfo , Outs , CC_zmtarzm ) ;


analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs,  true, nullptr);

analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ;


SmallVector<SDValue, 4> RetOps(1, Chain);

SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ;


assert(VA.isRegLoc() && "Can only return in registers!");

assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


if (VA.getLocInfo() == CCValAssign::AExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {


ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);

ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


SDValue Split64 = DAG.getNode(zmtarzmISD::BITCAST_TO_LOHI, DL, DAG.getVTList(MVT::i32, MVT::i32), Val);

SDValue Split64 = DAG . getNode ( zmtarzmISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ;


assert(RegLo < zmtarzm::R31 && "Invalid register pair");

assert
(
RegLo
<
zmtarzm
::
R31
&&
"Invalid register pair"
)
;


Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ;


RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return DAG.getNode(zmtarzmISD::NIR, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: NIR , DL , MVT :: Other , RetOps ) ;


return DAG.getNode(zmtarzmISD::RET, DL, MVT::Other, RetOps);

return DAG . getNode ( zmtarzmISD :: RET , DL , MVT :: Other , RetOps ) ;


if ( VA . getLocVT ( ) != MVT :: i32 ) {


Val = convertValVTToLocVT(DAG, Val, VA, DL);

Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ;


Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);

Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ;


if ( VA . getValVT ( ) != MVT :: f64 ) {


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmMFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmMFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


Register Reg = zmtarzmMFI->getSRetReturnReg();

Register Reg = zmtarzmMFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::RV, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: RV , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


unsigned Reg = FuncInfo->getSRetReturnReg();

unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ;


llvm_unreachable("sret virtual register not created in entry block");


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


unsigned Opc = (CallConv == CallingConv::zmtarzm_INTR ? zmtarzmISD::RETI_FLAG : zmtarzmISD::RET_FLAG);

unsigned Opc = ( CallConv == CallingConv :: zmtarzm_INTR ? zmtarzmISD :: RETI_FLAG : zmtarzmISD :: RET_FLAG ) ;


if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {


zmtarzmMachineFunctionInfo *SFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * SFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


llvm_unreachable("sret virtual register not created in the entry block");


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::I0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: I0 , Val , Flag ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R0 , Val , Flag ) ;


RetOps . push_back ( DAG . getRegister ( zmtarzm :: I0 , getPointerTy ( ) ) ) ;


if ( MF . getRegInfo ( ) . liveout_empty ( ) ) {


MF . getRegInfo ( ) . addLiveOut ( zmtarzm :: R0 ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {


MachineFunction &MF      = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


unsigned Reg = zmtarzmFI->getSRetReturnReg();

unsigned Reg = zmtarzmFI -> getSRetReturnReg ( ) ;


SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());

SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, zmtarzm::V0, Val, Flag);

Chain = DAG . getCopyToReg ( Chain , dl , zmtarzm :: V0 , Val , Flag ) ;


RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);

RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ;


SDValue LinkReg = DAG.getRegister(zmtarzm::LinkRegister, getPointerTy());

SDValue LinkReg = DAG . getRegister ( zmtarzm :: LinkRegister , getPointerTy ( ) ) ;


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32), Flag);

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) , Flag ) ;


return DAG . getNode ( zmtarzmISD :: RET_FLAG , dl , MVT :: Other , Chain , Flag ) ;

return DAG.getNode(zmtarzmISD::RET_FLAG, dl, MVT::Other, Chain, Flag);


const Function &Func = DAG.getMachineFunction().getFunction();

const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ;


if ( Func . hasFnAttribute ( "interrupt" ) ) {


llvm_unreachable
(
"interrupts not supported"
)
;


return DAG . getNode ( zmtarzmISD :: RET_FLAG , dl , MVT :: Other , Chain ) ;

return DAG.getNode(zmtarzmISD::RET_FLAG, dl, MVT::Other, Chain);


return DAG.getNode(zmtarzmISD::Ret, dl, MVT::Other, Chain, DAG.getRegister(zmtarzm::RA, MVT::i32));

return DAG . getNode ( zmtarzmISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( zmtarzm :: RA , MVT :: i32 ) ) ;


return DAG.getNode(T64ISD::JRP, DL, MVT::Other, Chain, LinkReg);

return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ;


SDValue zmtarzmTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a double-shift!"
)
;

assert(Op.getNumOperands() == 3 && "Not a double-shift!");


unsigned VTBits = VT . getSizeInBits ( ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


assert ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, MVT::i64), Shamt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, Lo, RevShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, Shamt, DAG.getConstant(VTBits, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue Tmp3 = DAG.getNode(ISD::SHL, DL, VT, Lo, ExtraShAmt);

SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue Tmp4 = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue CmpOp = getSelectableIntSetCC(ExtraShAmt, DAG.getConstant(0, MVT::i64), ISD::SETGE, A64cc, DAG, DL);

SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = getzmtarzmCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, zmtarzmcc, DAG, DL);

SDValue Cmp = getzmtarzmCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , zmtarzmcc , DAG , DL ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, DAG.getConstant(0, Tmp4.getValueType()), Tmp4, A64cc);

SDValue Lo = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , DAG . getConstant ( 0 , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::SELECT_CC, DL, VT, CmpOp, Tmp3, FalseVal, A64cc);

SDValue Hi = DAG . getNode ( zmtarzmISD :: SELECT_CC , DL , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ;


SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);

SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , 2 , DL ) ;


SDValue zmtarzmTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const {

SDValue zmtarzmTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const {


assert(Op.getNumOperands() == 3 && "Not a double-shift!");

assert
(
Op
.
getNumOperands
(
)
==
3
&&
"Not a double-shift!"
)
;


unsigned VTBits = VT . getSizeInBits ( ) ;


SDValue ShOpLo = Op . getOperand ( 0 ) ;


SDValue ShOpHi = Op . getOperand ( 1 ) ;


unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;

unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ;


assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);

assert ( Op . getOpcode ( ) == ISD :: SRA_PARTS || Op . getOpcode ( ) == ISD :: SRL_PARTS ) ;


SDValue RevShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, DAG.getConstant(VTBits, DL, MVT::i64), ShAmt);

SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ;


SDValue Tmp1 = DAG.getNode(ISD::SRL, DL, VT, ShOpLo, ShAmt);

SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ;


SDValue ExtraShAmt = DAG.getNode(ISD::SUB, DL, MVT::i64, ShAmt, DAG.getConstant(VTBits, DL, MVT::i64));

SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ;


SDValue Tmp2 = DAG.getNode(ISD::SHL, DL, VT, ShOpHi, RevShAmt);

SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ;


SDValue FalseVal = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueVal = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue CCR = DAG.getRegister(zmtarzm::CPSR, MVT::i32);

SDValue CCR = DAG . getRegister ( zmtarzm :: CPSR , MVT :: i32 ) ;


SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, DL, MVT::i64), ISD::SETGE, DL, DAG);

SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ;


SDValue CCVal = DAG.getConstant(zmtarzmCC::GE, DL, MVT::i32);

SDValue CCVal = DAG . getConstant ( zmtarzmCC :: GE , DL , MVT :: i32 ) ;


SDValue FalseValLo = DAG.getNode(ISD::OR, DL, VT, Tmp1, Tmp2);

SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ;


SDValue TrueValLo = DAG.getNode(Opc, DL, VT, ShOpHi, ExtraShAmt);

SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ;


SDValue FalseValHi = DAG.getNode(Opc, DL, VT, ShOpHi, ShAmt);

SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ;


SDValue TrueValHi = Opc == ISD::SRA ? DAG.getNode(Opc, DL, VT, ShOpHi, DAG.getConstant(VTBits - 1, DL, MVT::i64)) : DAG.getConstant(0, DL, VT);

SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::CMOV, DL, VT, FalseVal, TrueVal, zmtarzmcc, CCR, Cmp);

SDValue Lo = DAG . getNode ( zmtarzmISD :: CMOV , DL , VT , FalseVal , TrueVal , zmtarzmcc , CCR , Cmp ) ;


SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ;


unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;

unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ;


SDValue Zero = DAG.getConstant(0, DL, VT);

SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ;


SDValue One = DAG.getConstant(1, DL, VT);

SDValue One = DAG . getConstant ( 1 , DL , VT ) ;


SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);

SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ;


SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);

SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ;


SDValue ShamtMinusRegisterSize = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);

SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ;


SDValue RegisterSizeMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);

SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ;


SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);

SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ;


SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);

SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ;


MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;

MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ;


SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32));

SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ;


SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, VT));

SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ;


SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);

SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ;


SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);

SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ;


SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);

SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ;


SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);

SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ;


SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;

SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ;


SDValue CC = DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);

SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ;


SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ;


SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt);

SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ;


SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), MVT::i32));

SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ;


SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, VT));

SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ;


Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);

Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ;


Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);

Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ;


return DAG . getMergeValues ( Ops , 2 , DL ) ;


static SDValue zmtarzmTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const {

static SDValue zmtarzmTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const {


LLVMContext & Ctx = * DAG . getContext ( ) ;


assert
(
BV
.
getOpcode
(
)
==
ISD
::
BUILD_VECTOR
&&
"Unknown opcode!"
)
;

assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");


if (VT.getSizeInBits().getKnownMinSize() != zmtarzm::SVEBitsPerBlock) {

if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != zmtarzm :: SVEBitsPerBlock ) {


unsigned ElemSize = VT.getVectorElementType().getSizeInBits() / 8;

unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ;


unsigned ByteSize = VT.getSizeInBits().getKnownMinSize() / 8;

unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ;


EVT ByteVT = EVT::getVectorVT(Ctx, MVT::i8, { ByteSize, true });

EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ;


if (BV.getOperand(0).getOpcode() != ISD::FP_EXTEND) {

if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_EXTEND ) {


if (BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) {

if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) {


SDValue Op0 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(1));

SDValue Op0 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 1 ) ) ;


SDValue Op1 = DAG.getNode(ISD::BITCAST, DL, ByteVT, N->getOperand(2));

SDValue Op1 = DAG . getNode ( ISD :: BITCAST , DL , ByteVT , N -> getOperand ( 2 ) ) ;


SDValue Op2 = DAG.getNode(ISD::MUL, DL, MVT::i32, N->getOperand(3), DAG.getConstant(ElemSize, DL, MVT::i32));

SDValue Op2 = DAG . getNode ( ISD :: MUL , DL , MVT :: i32 , N -> getOperand ( 3 ) , DAG . getConstant ( ElemSize , DL , MVT :: i32 ) ) ;


SDValue EXT = DAG.getNode(zmtarzmISD::EXT, DL, ByteVT, Op0, Op1, Op2);

SDValue EXT = DAG . getNode ( zmtarzmISD :: EXT , DL , ByteVT , Op0 , Op1 , Op2 ) ;


int Offset = BV.getOperand(0).getOperand(0).getConstantOperandVal(1);

int Offset = BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) ;


if ( Op0 . getValueType ( ) != MVT :: v8f16 ) {


if (!Check(BV.getOperand(i), Op0, 2 * i + Offset)) {

if ( ! Check ( BV . getOperand ( i ) , Op0 , 2 * i + Offset ) ) {


MVT ElemTy = ty(InpV).getVectorElementType();

MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ;


if ( Subtarget . isHVXVectorType ( ResTy ) ) {


return DAG . getNode ( zmtarzmISD :: VCVTL , DL , VT , Op0 , DAG . getConstant ( Offset , DL , MVT :: i32 ) ) ;

return DAG.getNode(zmtarzmISD::VCVTL, DL, VT, Op0, DAG.getConstant(Offset, DL, MVT::i32));


SDValue zmtarzmTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {

SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: ADDE ) {


return performADDECombine ( N , DAG , DCI , Subtarget ) ;

return performADDECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SUBE ) {


return performSUBECombine ( N , DAG , DCI , Subtarget ) ;

return performSUBECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SHL ) {


return performSHLCombine ( N , DAG , DCI , Subtarget ) ;

return performSHLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRA ) {


return performSRACombine ( N , DAG , DCI , Subtarget ) ;

return performSRACombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRL ) {


return performSRLCombine ( N , DAG , DCI , Subtarget ) ;

return performSRLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: VSELECT ) {


return performVSELECTCombine ( N , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: SETCC ) {


return TargetLowering :: PerformDAGCombine ( N , DCI ) ;


zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {

zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {

for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto *RegInfo = Subtarget.getRegisterInfo();

auto * RegInfo = Subtarget . getRegisterInfo ( ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


for ( MVT VT : MVT :: integer_valuetypes ( ) ) {

for (MVT VT : MVT::integer_valuetypes()) {


setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1, Promote);


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction ( ISD :: ADDC , MVT :: i32 , Expand ) ;

ISD::ADDC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i32 , Expand ) ;

ISD::ADDE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i32 , Expand ) ;

ISD::SUBC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i32 , Expand ) ;

ISD::SUBE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIVREM , MVT :: i32 , Expand ) ;

ISD::UDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIVREM , MVT :: i32 , Expand ) ;

ISD::SDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MUL , MVT :: i32 , Expand ) ;

ISD::MUL zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHS , MVT :: i32 , Expand ) ;

ISD::MULHS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHS , MVT :: i64 , Expand ) ;

ISD::MULHS zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i32 , Expand ) ;

ISD::MULHU zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i64 , Expand ) ;

ISD::MULHU zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BITCAST , MVT :: f32 , Expand ) ;

ISD::BITCAST zmsplit MVT::f32 zmsplit Expand


setOperationAction ( ISD :: BITCAST , MVT :: i32 , Expand ) ;

ISD::BITCAST zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i64 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i64 zmsplit Expand


setOperationAction(#,             #,   #);

setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);

setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);

setOperationAction(#,              #,   #);


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i64 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Custom ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: SELECT_CC , MVT :: Other , Expand ) ;

ISD::SELECT_CC zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: SETCC , MVT :: i1 , Promote ) ;

ISD::SETCC zmsplit MVT::i1 zmsplit Promote


setOperationAction ( ISD :: SETCC , MVT :: i64 , Expand ) ;

ISD::SETCC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SETCC , MVT :: f32 , Expand ) ;

ISD::SETCC zmsplit MVT::f32 zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: SETCC , MVT :: f64 , Expand ) ;

ISD::SETCC zmsplit MVT::f64 zmsplit Expand


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);

ISD :: GlobalTLSAddress MVT :: i32 Custom


setOperationAction ( ISD :: ConstantPool , MVT :: i32 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VASTART,            MVT::Other, Custom);


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAEND,              MVT::Other, Expand);


setOperationAction ( ISD :: VAARG , MVT :: Other , Expand ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAARG,              MVT::Other, Expand);


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VACOPY,             MVT::Other, Expand);


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::BR_JT,              MVT::Other, Expand);


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);


setOperationAction ( ISD :: BR_CC , MVT :: f32 , Expand ) ;

ISD::BR_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::f32,   Expand);


setCondCodeAction ( CC , VT , Expand ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setOperationAction ( ISD :: BR_CC , MVT :: f64 , Expand ) ;

ISD::BR_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::f64,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::i32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i64 , Expand ) ;

ISD::BR_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::BR_CC,              MVT::i64,   Expand);


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i1 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i1 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG,  MVT::i1,    Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i1 Expand


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Expand ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Expand ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Expand ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f32 , Expand ) ;

ISD::FP_ROUND zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP_ROUND,           MVT::f32,   Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f64 , Expand ) ;

ISD::FP_ROUND zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP_ROUND,           MVT::f64,   Expand);


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTPOP,              MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ,               MVT::i32,   Expand);


setOperationAction(#,           #,   #);

setOperationAction(#,           #,   #);


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTLZ,               MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ_ZERO_UNDEF , MVT :: i32 , Expand ) ;

ISD::CTTZ_ZERO_UNDEF zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ_ZERO_UNDEF,    MVT::i32,   Expand);

ISD :: CTTZ_ZERO_UNDEF MVT :: i32 Expand


setOperationAction ( ISD :: CTLZ_ZERO_UNDEF , MVT :: i32 , Expand ) ;

ISD::CTLZ_ZERO_UNDEF zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTLZ_ZERO_UNDEF,    MVT::i32,   Expand);

ISD :: CTLZ_ZERO_UNDEF MVT :: i32 Expand


setOperationAction ( ISD :: ROTL , MVT :: i32 , Expand ) ;

ISD::ROTL zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTL , MVT::i32, Expand);


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTR , MVT::i32, Expand);


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FREM , MVT :: f32 , Expand ) ;

ISD::FREM zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FREM,       MVT::f32, Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i8 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i8 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP, MVT::i8,  Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i16 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i16 zmsplit Expand


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i32 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i32 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: FP_ROUND , MVT :: f32 , Expand ) ;

setOperationAction(ISD::FP_ROUND,   MVT::f32, Expand);


setOperationAction ( ISD :: FP_ROUND , MVT :: f64 , Expand ) ;

setOperationAction(ISD::FP_ROUND,   MVT::f64, Expand);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f32 , Expand ) ;

ISD::FCOPYSIGN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOPYSIGN,  MVT::f32, Expand);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f64 , Expand ) ;

ISD::FCOPYSIGN zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FCOPYSIGN,  MVT::f64, Expand);


setOperationAction ( ISD :: FSUB , MVT :: f32 , Expand ) ;

ISD::FSUB zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSUB,       MVT::f32, Expand);


setOperationAction ( ISD :: FSIN , MVT :: f32 , Expand ) ;

ISD::FSIN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSIN,       MVT::f32, Expand);


setOperationAction ( ISD :: FCOS , MVT :: f32 , Expand ) ;

ISD::FCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOS,       MVT::f32, Expand);


setOperationAction ( ISD :: FPOWI , MVT :: f32 , Expand ) ;

ISD::FPOWI zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOWI,      MVT::f32, Expand);


setOperationAction ( ISD :: FPOW , MVT :: f32 , Expand ) ;

ISD::FPOW zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOW,       MVT::f32, Expand);


setOperationAction ( ISD :: FPOW , MVT :: f64 , Expand ) ;

ISD::FPOW zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FPOW,       MVT::f64, Expand);


setOperationAction ( ISD :: FLOG , MVT :: f32 , Expand ) ;

ISD::FLOG zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG,       MVT::f32, Expand);


setOperationAction ( ISD :: FLOG2 , MVT :: f32 , Expand ) ;

ISD::FLOG2 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG2,      MVT::f32, Expand);


setOperationAction ( ISD :: FLOG10 , MVT :: f32 , Expand ) ;

ISD::FLOG10 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG10,     MVT::f32, Expand);


setOperationAction ( ISD :: FEXP , MVT :: f32 , Expand ) ;

ISD::FEXP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FEXP,       MVT::f32, Expand);


setOperationAction ( ISD :: FSQRT , MVT :: f64 , Expand ) ;

ISD::FSQRT zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSQRT,      MVT::f64, Expand);


setOperationAction ( ISD :: FSQRT , MVT :: f32 , Expand ) ;

ISD::FSQRT zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSQRT,      MVT::f32, Expand);


setOperationAction ( ISD :: EH_LABEL , MVT :: Other , Expand ) ;

ISD::EH_LABEL zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::EH_LABEL,          MVT::Other, Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i32 Expand


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);


setStackPointerRegisterToSaveRestore ( # ) ;

setStackPointerRegisterToSaveRestore ( zmtarzm :: RSP ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);

setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {

zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {

for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto * RegInfo = Subtarget . getRegisterInfo ( ) ;

auto *RegInfo = Subtarget.getRegisterInfo();


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {

for ( MVT VT : MVT :: integer_valuetypes ( ) ) {

for (MVT VT : MVT::integer_valuetypes()) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::ZEXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

ISD::SEXTLOAD zmsplit VT zmsplit MVT::i1 zmsplit Promote

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);


for ( MVT VT : MVT :: fp_valuetypes ( ) ) {


setLoadExtAction ( # , # , MVT :: f32 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: f32 , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::f32 zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);


setLoadExtAction ( # , # , MVT :: f16 , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , MVT :: f16 , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit MVT::f16 zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);


for ( MVT VT : MVT :: fp_vector_valuetypes ( ) ) {

for (MVT VT : MVT::fp_vector_valuetypes()) {


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);


MVT F16VT = MVT :: getVectorVT ( MVT :: f16 , VT . getVectorNumElements ( ) ) ;

MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());


setLoadExtAction ( # , # , F16 # , # ) ;

setLoadExtAction ( ISD :: EXTLOAD , VT , F16VT , Expand ) ;

ISD::EXTLOAD zmsplit VT zmsplit F16VT zmsplit Expand

setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);


setTruncStoreAction ( MVT :: f32 , MVT :: f16 , Expand ) ;

MVT::f32 zmsplit  MVT::f16 zmsplit  Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f16 , Expand ) ;

MVT::f64 zmsplit  MVT::f16 zmsplit  Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f32 , Expand ) ;

MVT::f64 zmsplit MVT::f32 zmsplit Expand


AddPromotedToType ( ISD :: SETCC , MVT :: i1 , MVT :: i32 ) ;

ISD::SETCC zmsplit MVT::i1 zmsplit MVT::i32


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::BR_JT,              MVT::Other, Expand);


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);


setOperationAction ( ISD :: BlockAddress , MVT :: i32 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);


setOperationAction ( ISD :: ConstantPool , MVT :: i32 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: f32 , Custom ) ;

ISD::SELECT zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::f32,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: f64 , Custom ) ;

ISD::SELECT zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::f64,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: i32 , Custom ) ;

ISD::SELECT zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::i32,   Custom);


setOperationAction ( ISD :: SETCC , MVT :: f32 , Custom ) ;

ISD::SETCC zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::SETCC,              MVT::f32,   Custom);


setOperationAction ( ISD :: SETCC , MVT :: f64 , Custom ) ;

ISD::SETCC zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::SETCC,              MVT::f64,   Custom);


setOperationAction ( ISD :: BRCOND , MVT :: Other , Custom ) ;

ISD::BRCOND zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::BRCOND,             MVT::Other, Custom);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f32 , Custom ) ;

ISD::FCOPYSIGN zmsplit MVT::f32 zmsplit Custom

setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);


setOperationAction ( ISD :: FCOPYSIGN , MVT :: f64 , Custom ) ;

ISD::FCOPYSIGN zmsplit MVT::f64 zmsplit Custom

setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);


setOperationAction ( ISD :: FP_TO_SINT , MVT :: i32 , Custom ) ;

ISD::FP_TO_SINT zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);


setOperationAction ( ISD :: GlobalAddress , MVT :: i64 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);


setOperationAction ( ISD :: BlockAddress , MVT :: i64 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i64 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);

ISD :: GlobalTLSAddress MVT :: i64 Custom


setOperationAction ( ISD :: JumpTable , MVT :: i64 , Custom ) ;

ISD::JumpTable zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);


setOperationAction ( ISD :: ConstantPool , MVT :: i64 , Custom ) ;

ISD::ConstantPool zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);


setOperationAction ( ISD :: SELECT , MVT :: i64 , Custom ) ;

ISD::SELECT zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SELECT,             MVT::i64,   Custom);


setOperationAction ( ISD :: LOAD , MVT :: i64 , Custom ) ;

ISD::LOAD zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::LOAD,               MVT::i64,   Custom);


setOperationAction ( ISD :: STORE , MVT :: i64 , Custom ) ;

ISD::STORE zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::STORE,              MVT::i64,   Custom);


setOperationAction ( ISD :: FP_TO_SINT , MVT :: i64 , Custom ) ;

ISD::FP_TO_SINT zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);


setOperationAction ( ISD :: SHL_PARTS , MVT :: i64 , Custom ) ;

ISD::SHL_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i64 , Custom ) ;

ISD::SRA_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i64 , Custom ) ;

ISD::SRL_PARTS zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Custom ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Custom ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Custom ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);


setOperationAction ( ISD :: EH_DWARF_CFA , MVT :: i32 , Custom ) ;

ISD::EH_DWARF_CFA zmsplit MVT::i32 zmsplit Custom

setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);


setOperationAction ( ISD :: EH_DWARF_CFA , MVT :: i64 , Custom ) ;

ISD::EH_DWARF_CFA zmsplit MVT::i64 zmsplit Custom

setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i64 , Expand ) ;

ISD::SDIV zmsplit MVT::i64 zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: SREM , MVT :: i64 , Expand ) ;

ISD::SREM zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i64 , Expand ) ;

ISD::UDIV zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i64 , Expand ) ;

ISD::UREM zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i32 , Expand ) ;

ISD::ADDC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i32 , Expand ) ;

ISD::ADDE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i64 , Expand ) ;

ISD::ADDC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i64 , Expand ) ;

ISD::ADDE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i32 , Expand ) ;

ISD::SUBC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i32 , Expand ) ;

ISD::SUBE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i64 , Expand ) ;

ISD::SUBC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i64 , Expand ) ;

ISD::SUBE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BR_CC , MVT :: f32 , Expand ) ;

ISD::BR_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: f64 , Expand ) ;

ISD::BR_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);


setCondCodeAction ( CC , VT , Expand ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i64 , Expand ) ;

ISD::BR_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i32 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i64 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i32 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i64 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i1 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i1 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Legal ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Legal ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Expand ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i64 , Expand ) ;

ISD::CTTZ zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i32 , Expand ) ;

ISD::ROTL zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i32,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i64 , Expand ) ;

ISD::ROTL zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i64,   Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i64 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i64 Expand


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i32,   Expand);


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i64 , Expand ) ;

ISD::ROTR zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i64,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f32 , Expand ) ;

ISD::FSIN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f32,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f64 , Expand ) ;

ISD::FSIN zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f64,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f32 , Expand ) ;

ISD::FCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f32,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f64 , Expand ) ;

ISD::FCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f64,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f32 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f64 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f32 , Expand ) ;

ISD::FPOW zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f32,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f64 , Expand ) ;

ISD::FPOW zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f64,   Expand);


setOperationAction ( ISD :: FLOG , MVT :: f32 , Expand ) ;

ISD::FLOG zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG,              MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG2 , MVT :: f32 , Expand ) ;

ISD::FLOG2 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG10 , MVT :: f32 , Expand ) ;

ISD::FLOG10 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);


setOperationAction ( ISD :: FEXP , MVT :: f32 , Expand ) ;

ISD::FEXP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FEXP,              MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f32 , Expand ) ;

ISD::FMA zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f64 , Expand ) ;

ISD::FMA zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f64,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f32 , Expand ) ;

ISD::FREM zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f32,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f64 , Expand ) ;

ISD::FREM zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f64,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f32 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f32 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f64 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f64 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);


setOperationAction ( ISD :: EH_RETURN , MVT :: Other , Custom ) ;

ISD::EH_RETURN zmsplit MVT::Other zmsplit Custom


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VASTART,           MVT::Other, Custom);


setOperationAction ( ISD :: VAARG , MVT :: Other , Custom ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VAARG,             MVT::Other, Custom);


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VACOPY,            MVT::Other, Expand);


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAEND,             MVT::Other, Expand);


setStackPointerRegisterToSaveRestore ( # ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);


setOperationAction ( ISD :: ATOMIC_LOAD , MVT :: i64 , Expand ) ;

ISD::ATOMIC_LOAD zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);


setOperationAction ( ISD :: ATOMIC_STORE , MVT :: i64 , Expand ) ;

ISD::ATOMIC_STORE zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i8 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i8 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i8 Expand


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i16 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i16 zmsplit Expand

ISD :: SIGN_EXTEND_INREG MVT :: i16 Expand


if ( Subtarget . inzmtarzm16Mode ( ) ) {


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTLZ , MVT :: i64 , Expand ) ;

ISD::CTLZ zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: BSWAP , MVT :: i64 , Expand ) ;

ISD::BSWAP zmsplit MVT::i64 zmsplit Expand


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::SEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: SEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: ZEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::ZEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: ZEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: EXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::EXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: EXTLOAD MVT :: i64 MVT :: i32 Custom


setTruncStoreAction ( MVT :: i64 , MVT :: i32 , Custom ) ;

MVT::i64 zmsplit  MVT::i32 zmsplit  Custom


setOperationAction ( ISD :: TRAP , MVT :: Other , Legal ) ;

ISD::TRAP zmsplit MVT::Other zmsplit Legal


setTargetDAGCombine ( ISD :: SDIVREM ) ;


setTargetDAGCombine ( ISD :: UDIVREM ) ;


setTargetDAGCombine ( ISD :: AssertZext ) ;


setLibcallName ( RTLIB :: SHL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRA_I128 , nullptr ) ;


setMinFunctionAlignment ( Subtarget . isGP64bit ( ) ? 3 : 2 ) ;

setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);


setMinStackArgumentAlignment ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? 8 : 4 ) ;

setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);


setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;

setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);


isMicrozmtarzm = Subtarget . inMicrozmtarzmMode ( ) ;


int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {

int getIntMatCost ( const APInt & Val , unsigned Size , bool IsRV64 ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetMC ( ) {


for (Target *T : {&getThezmtarzm32Target(), &getThezmtarzm64Target()}) {

for ( Target * T : { & getThezmtarzm32Target ( ) , & getThezmtarzm64Target ( ) } ) {


TargetRegistry :: RegisterMCAsmInfo ( * T , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( * T , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( * T , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCAsmBackend ( * T , createzmtarzmAsmBackend ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmMCCodeEmitter ) ;


TargetRegistry :: RegisterMCCodeEmitter ( * T , createzmtarzmCodeEmitter ) ;


TargetRegistry :: RegisterMCInstPrinter ( * T , createzmtarzmMCInstPrinter ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( * T , createzmtarzmMCSubtargetInfo ) ;


TargetRegistry :: RegisterObjectTargetStreamer ( * T , createzmtarzmObjectTargetStreamer ) ;


TargetRegistry :: RegisterMCInstrAnalysis ( * T , createzmtarzmInstrAnalysis ) ;


TargetRegistry :: RegisterAsmTargetStreamer ( * T , createzmtarzmAsmTargetStreamer ) ;


TargetRegistry :: RegisterNullTargetStreamer ( * T , createzmtarzmNullTargetStreamer ) ;


TargetRegistry :: RegisterELFStreamer ( * T , createzmtarzmELFStreamer ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( * T , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCObjectStreamer ( * T , createzmtarzmMCObjStreamer ) ;


bool zmtarzmMergeBaseOffset::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmMergeBaseOffset :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( * F . getFunction ( ) ) ) {


const Subtarget &ST = MF.getSubtarget<Subtarget>();

const Subtarget & ST = MF . getSubtarget < Subtarget > ( ) ;


ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


assert
(
isUInt
<
6
>
(
Offset
)
&&
"Offset is out of range"
)
;

assert(isUInt<6>(Offset) && "Offset is out of range");


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


auto &Subtarget = MF->getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF -> getSubtarget < zmtarzmSubtarget > ( ) ;


if (MF->getFunction().getCallingConv() == #) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == # ) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) {

if (MF->getFunction().getCallingConv() == CallingConv::GHC) {


if ( MF -> getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) {


if (MF->getFnAttribute("interrupt").getValueAsString() == #) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == # ) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) {

if (MF->getFnAttribute("interrupt").getValueAsString() == "FIQ") {


if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


return STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ;

return STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;


if ( Subtarget . getTargetABI ( ) == # ) {


BitVector zmtarzmRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


const zmtarzmFrameLowering *TFI = getFrameLowering(MF);

const zmtarzmFrameLowering * TFI = getFrameLowering ( MF ) ;


for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {

for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) {


if ( MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


if ( ! MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


markSuperRegs ( Reserved , zmtarzm :: WSP ) ;


markSuperRegs ( Reserved , zmtarzm :: WZR ) ;


markSuperRegs ( Reserved , zmtarzm :: W19 ) ;


markSuperRegs ( Reserved , zmtarzm :: W16 ) ;


markSuperRegs ( Reserved , zmtarzm :: CRSub ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) {


if ( zmtarzm :: hasPACStackAttribute ( MF ) ) {


assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


bool zmtarzmRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const {

bool zmtarzmRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const {


const auto *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const auto * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


if ( zmtarzm :: PRegsRegClass . contains ( Reg ) ) {


FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ;


FrameIdx = FI -> getCRSpillFrameIndex ( ) ;


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


int zmtarzmTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) {

int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers");


unsigned Ty->getPrimitiveSizeInBits() = Ty->getPrimitiveSizeInBits();

unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if (Ty->getPrimitiveSizeInBits() == 0) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() > 64) {

if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {

if (Opcode == Instruction::GetElementPtr) {


if (Ty->getPrimitiveSizeInBits() == 8) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


int NumConstants = divideCeil(Ty->getPrimitiveSizeInBits(), 64);

int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if (getIntImmCost(Imm, Ty, CostKind) <= NumConstants * TTI::TCC_Basic) {

if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost(Imm, Ty, CostKind);

return getIntImmCost ( Imm , Ty , CostKind ) ;


if (Imm.getZExtValue() == 0x100000000ULL) {

if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() <= 32) {

if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {