CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CC_zmtarzm ) ;


CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ;


Chain = DAG.getNode(zmtarzmISD::ENTRY_FLAG, DL, MVT::Other, {Chain, DAG.getRegister(zmtarzm::a1, MVT::i32), DAG.getTargetConstant(4, DL, MVT::i32)});

Chain = DAG . getNode ( zmtarzmISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( zmtarzm :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ;


assert ( ArgLocs . size ( ) == Ins . size ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ;


FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ;


for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


ArgValue = unpack64(DAG, Chain, VA, DL);

ArgValue = unpack64 ( DAG , Chain , VA , DL ) ;


ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);

ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ;


ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);

ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ;


unsigned VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ;


SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());

SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ;


if ( VA . getValVT ( ) == MVT :: i32 ) {


Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, DAG.getConstant(32, DL, MVT::i32));

Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);

Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ;


assert(VA.needsCustom() == false && "Doesn't support custom argument lowering");


unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;

unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;


unsigned ValSize = VA.getValVT().getSizeInBits() / 8;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ;


int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),  MachinePointerInfo::getFixedStack(MF, FI)));

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);

unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


if (VA.getLocInfo() == CCValAssign::Full) {

if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {


if (VA.getLocInfo() == CCValAssign::BCvt) {

if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {


ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);

ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ;


SDValue Val = DAG.getLoad(VA.getLocInfo() == CCValAssign::AExt ? VA.getValVT() : VA.getLocVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())), MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));

SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


InVals.push_back(DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val));

InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ;


ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs);

ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;


unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &RegInfo = MF.getRegInfo();

MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


VaArgOffset = CCInfo . getNextStackOffset ( ) ;


VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ;


int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


zmtarzmFI -> setVarArgsFrameIndex ( FI ) ;


for (unsigned i = Idx; i < ArgRegs.size(); ++i, VaArgOffset += XLenInBytes) {

for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) {


const Register Reg = RegInfo.createVirtualRegister(RC);

const Register Reg = RegInfo . createVirtualRegister ( RC ) ;


RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ;


FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));

SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI));

SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ;


cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


zmtarzmFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ;


Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);

Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ;


unsigned ArgOffset = ArgLocs.size() * 8;

unsigned ArgOffset = ArgLocs . size ( ) * 8 ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ;


void zmtarzmTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


ExpandREAD_REGISTER ( N , Results , DAG ) ;


Res = ExpandBITCAST ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: BITCAST ) {


ReplaceBITCASTResults ( N , Results , DAG ) ;


Res = Expand64BitShift(N, DAG, Subtarget);

Res = Expand64BitShift ( N , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_ADD ) {

if (N->getOpcode() == ISD::VECREDUCE_ADD) {


Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_SMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_SMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_SMIN) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMAX ) {

if (N->getOpcode() == ISD::VECREDUCE_UMAX) {


if ( N -> getOpcode ( ) == ISD :: VECREDUCE_UMIN ) {

if (N->getOpcode() == ISD::VECREDUCE_UMIN) {


Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ;


Results . push_back ( Res . getValue ( 0 ) ) ;


Results . push_back ( Res . getValue ( 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: CTPOP ) {


Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ;


if ( N -> getOpcode ( ) == ISD :: SADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::SADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: SADDV ) ;


Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);

Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UADDV ) {


ReplaceReductionResults(N, Results, DAG, ISD::ADD, zmtarzmISD::UADDV);

ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , zmtarzmISD :: UADDV ) ;


if ( N -> getOpcode ( ) == ISD :: SMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMIN, zmtarzmISD::SMINVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , zmtarzmISD :: SMINVV ) ;


ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);

ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ;


if ( N -> getOpcode ( ) == ISD :: UMINV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMINV, zmtarzmISD::UMINV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , zmtarzmISD :: UMINV ) ;


return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results);

return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ;


if ( N -> getOpcode ( ) == ISD :: SMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::SMAX, zmtarzmISD::SMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: SMAX , zmtarzmISD :: SMAXVV ) ;


if ( N -> getOpcode ( ) == ISD :: UMAXV ) {


ReplaceReductionResults(N, Results, DAG, ISD::UMAX, zmtarzmISD::UMAXVV);

ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , zmtarzmISD :: UMAXVV ) ;


RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;

RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) {

if (N->getOpcode() == ISD::FP_TO_UINT) {


assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;

assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");


ReplaceCMP_SWAP_128Results(N, Results, DAG, Subtarget);

ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ;


if (N->getOperand(0).getValueType() != MVT::f128) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) {


if ( N -> getValueType ( 0 ) != MVT :: i64 ) {


Results.push_back(LowerF128Op(SDValue(N, 0), DAG, getLibcallName(libCall), 1));

Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) {

if (N->getOpcode() == ISD::FP_TO_SINT) {


LoadSDNode *LoadNode = cast<LoadSDNode>(N);

LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ;


if (LoadNode->getMemoryVT() != MVT::i128) {

if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) {


SDValue Result = DAG.getMemIntrinsicNode(zmtarzmISD::LDP, SDLoc(N), DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}), {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Result = DAG . getMemIntrinsicNode ( zmtarzmISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Result.getValue(0), Result.getValue(1));

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ;


Results.append({Pair, Result.getValue(2)  });

Results . append ( { Pair , Result . getValue ( 2 ) } ) ;


if ( N -> getOpcode ( ) == ISD :: ATOMIC_CMP_SWAP ) {

if (N->getOpcode() == ISD::ATOMIC_CMP_SWAP) {


ReplaceExtractSubVectorResults ( N , Results , DAG ) ;


SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), DL, zmtarzm::ASR23, MVT::i32);

SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , zmtarzm :: ASR23 , MVT :: i32 ) ;


SDValue Hi = DAG.getCopyFromReg(Lo, DL, zmtarzm::G0, MVT::i32);

SDValue Hi = DAG . getCopyFromReg ( Lo , DL , zmtarzm :: G0 , MVT :: i32 ) ;


SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);

SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ;


Results . push_back ( N -> getOperand ( 0 ) ) ;


if ( N -> getOpcode ( ) == ISD :: LOAD ) {


assert
(
SDValue
(
N
,
0
)
.
getValueType
(
)
==
MVT
::
i128
&&
"unexpected load's value type"
)
;

assert(SDValue(N, 0).getValueType() == MVT::i128 && "unexpected load's value type");


if ( N -> getValueType ( 0 ) != MVT :: f128 ) {


if (N->getOperand(0).getValueType() != MVT::i64) {

if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) {


Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ;


return ReplaceLongIntrinsic(N, Results, DAG);

return ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: EXTRACT_SUBVECTOR ) {

if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) {


ReplaceLongIntrinsic ( N , Results , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (N->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


assert
(
(
VT
==
MVT
::
i8
||
VT
==
MVT
::
i16
)
&&
"custom lowering for unexpected type"
)
;

assert((VT == MVT::i8 || VT == MVT::i16) &&"custom lowering for unexpected type");


ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));

ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if (IntID == Intrinsic::aarch64_sve_clasta_n) {

if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) {


auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));

auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ;


auto V = DAG.getNode(zmtarzmISD::CLASTA_N, DL, MVT::i32, N->getOperand(1), Op2, N->getOperand(3));

auto V = DAG . getNode ( zmtarzmISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ;


Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));

Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ;


if (IntID == Intrinsic::aarch64_sve_lasta) {

if ( IntID == Intrinsic :: aarch64_sve_lasta ) {


auto V = DAG.getNode(zmtarzmISD::LASTA, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


if (IntID == Intrinsic::aarch64_sve_lastb) {

if ( IntID == Intrinsic :: aarch64_sve_lastb ) {


auto V = DAG.getNode(zmtarzmISD::LASTB, DL, MVT::i32, N->getOperand(1), N->getOperand(2));

auto V = DAG . getNode ( zmtarzmISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ;


LoadSDNode * Ld = cast < LoadSDNode > ( N ) ;


if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) {


if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) {


SDValue LoadRes = DAG.getExtLoad(Ld->getExtensionType(), DL, MVT::v2i32, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), Ld->getMemOperand()->getFlags(), Ld->getAAInfo());

SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ;


SDValue Res = DAG.getNode(ISD::BITCAST, DL, MVT::i64, LoadRes);

SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ;


Results . push_back ( LoadRes . getValue ( 1 ) ) ;


llvm_unreachable("Don't know how to custom expand this");

llvm_unreachable
(
"Don't know how to custom expand this"
)
;


void zmtarzmFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const {

void zmtarzmFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const {


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( # ) ;

MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R0 ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R1 ) ;


MF . getRegInfo ( ) . setPhysRegUnused ( zmtarzm :: R2 ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetRegisterClass *RC = &zmtarzm::R32CRegClass;

const TargetRegisterClass * RC = & zmtarzm :: R32CRegClass ;


RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


zmtarzmFunctionInfo *FI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * FI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


CallingConv::ID CallConv = MF.getFunction()->getCallingConv();

CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ;


bool requiresRA = CallConv == CallingConv::MBLAZE_INTR;

bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ;


if (MFI->adjustsStack() || requiresRA) {

if ( MFI -> adjustsStack ( ) || requiresRA ) {


MFI -> CreateFixedObject ( 4 , 0 , true ) ;


MFI -> CreateFixedObject ( 4 , 4 , true ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSHRr ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSHRr)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


inline bool immBitp(SDNode *inN) const {

inline bool immBitp ( SDNode * inN ) const {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


inline bool immMskBitp(SDNode *inN) const {

inline bool immMskBitp ( SDNode * inN ) const {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CSEL ) {

if (Op.getOpcode() == zmtarzmISD::CSEL) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_ldaxr ) {

if (IntID == Intrinsic::zmtarzm_ldaxr) {


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


if ( IntID == Intrinsic :: zmtarzm_ldxr ) {


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) {

if (Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_umaxv ) {

if (IntID == Intrinsic::zmtarzm_neon_umaxv) {


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;

assert(BitWidth >= 8 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;

assert(BitWidth >= 16 && "Unexpected width!");


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


if ( IntID == Intrinsic :: zmtarzm_neon_uminv ) {

if (IntID == Intrinsic::zmtarzm_neon_uminv) {


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


SDValue zmtarzmTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


zmtarzmFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmFunctionInfo>();

zmtarzmFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


SDValue Offset = Op . getOperand ( 1 ) ;


SDValue Handler = Op . getOperand ( 2 ) ;


auto PtrVT = getPointerTy(DAG.getDataLayout());

auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(zmtarzm::R30, PtrVT), DAG.getIntPtrConstant(4, dl));

SDValue StoreAddr = DAG . getNode ( ISD :: ADD , dl , PtrVT , DAG . getRegister ( zmtarzm :: R30 , PtrVT ) , DAG . getIntPtrConstant ( 4 , dl ) ) ;


Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), false, false, 0);

Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , 0 ) ;


Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


Chain = DAG.getCopyToReg(Chain, dl, AddrReg, Handler);

Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler ) ;


Chain = DAG.getCopyToReg(Chain, dl, ReturnReg, DAG.getIntPtrConstant(0));

Chain = DAG . getCopyToReg ( Chain , dl , ReturnReg , DAG . getIntPtrConstant ( 0 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, MVT::i32), DAG.getRegister(AddrReg, getPointerTy()));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( ) ) ) ;


EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;

EVT Ty = ABI . IsN64 ( ) ? MVT :: i64 : MVT :: i32 ;


unsigned OffsetReg = ABI.IsN64() ? zmtarzm::V1_64 : zmtarzm::V1;

unsigned OffsetReg = ABI . IsN64 ( ) ? zmtarzm :: V1_64 : zmtarzm :: V1 ;


unsigned AddrReg = ABI.IsN64() ? zmtarzm::V0_64 : zmtarzm::V0;

unsigned AddrReg = ABI . IsN64 ( ) ? zmtarzm :: V0_64 : zmtarzm :: V0 ;


Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset, SDValue());

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset , SDValue ( ) ) ;


Chain = DAG.getCopyToReg(Chain, dl, AddrReg, Handler, Chain.getValue(1));

Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler , Chain . getValue ( 1 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, MVT::i32), DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), Chain.getValue(1));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain);

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain ) ;


return DAG.getNode(zmtarzmISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(OffsetReg, Ty), DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), Chain.getValue(1));

return DAG . getNode ( zmtarzmISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_thread_pointer ) {

if (IntNo == Intrinsic::zmtarzm_thread_pointer) {


return DAG.getNode(zmtarzmISD::EH_SJLJ_SETJMP, DL, MVT::i32, Op.getOperand(1));

return DAG . getNode ( zmtarzmISD :: EH_SJLJ_SETJMP , DL , MVT :: i32 , Op . getOperand ( 1 ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


return DAG.getNode(zmtarzmISD::Wrapper, DL, VT, DAG.getMCSymbol(S, PtrVT));

return DAG . getNode ( zmtarzmISD :: Wrapper , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_tuple ) {

if (IntNo == Intrinsic::zmtarzm_tuple) {


return DAG.getNode(zmtarzmISD::EH_SJLJ_SETJMP, DL, MVT::i32, Op.getOperand(1));

return DAG . getNode ( zmtarzmISD :: EH_SJLJ_SETJMP , DL , MVT :: i32 , Op . getOperand ( 1 ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


return DAG . getNode ( Cmd , DL , MVT :: zmtarzmTuple , Ops ) ;

return DAG.getNode(Cmd, DL, MVT::zmtarzmTuple, Ops);


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


return DAG.getNode(zmtarzmISD::Wrapper, DL, VT, DAG.getMCSymbol(S, PtrVT));

return DAG . getNode ( zmtarzmISD :: Wrapper , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ;


SDValue zmtarzmTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const {


StoreSDNode *StoreNode = cast<StoreSDNode>(Op);

StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ;


assert (StoreNode && "Can only custom lower store nodes");

assert
(
StoreNode
&&
"Can only custom lower store nodes"
)
;


SDValue Value = StoreNode -> getValue ( ) ;


EVT MemVT = StoreNode -> getMemoryVT ( ) ;


assert (VT.isVector() && "Can only custom lower vector store types");


unsigned AS = StoreNode->getAddressSpace();

unsigned AS = StoreNode -> getAddressSpace ( ) ;


unsigned Align = StoreNode->getAlignment();

unsigned Align = StoreNode -> getAlignment ( ) ;


if (Align < MemVT.getStoreSize() && !allowsMisalignedMemoryAccesses(MemVT, AS, Align, StoreNode->getMemOperand()->getFlags(), nullptr)) {

if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) {


return scalarizeVectorStore ( StoreNode , DAG ) ;


if ( StoreNode -> isTruncatingStore ( ) ) {


return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);

return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ;


if (VT == MVT::v2f16 && !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, StoreNode->getAddressSpace(), StoreNode->getAlignment())) {

if ( VT == MVT :: v2f16 && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , StoreNode -> getAddressSpace ( ) , StoreNode -> getAlignment ( ) ) ) {


return expandUnalignedStore ( Store , DAG ) ;


SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, StoreNode->getValue());

SDValue Val = DAG . getNode ( ISD :: BITCAST , dl , MVT :: v2i32 , StoreNode -> getValue ( ) ) ;


SDValue Chain = DAG.getStore(StoreNode->getChain(), dl, Val, StoreNode->getBasePtr(), StoreNode->getPointerInfo(), StoreNode->getAlignment(), StoreNode->getMemOperand()->getFlags(), StoreNode->getAAInfo());

SDValue Chain = DAG . getStore ( StoreNode -> getChain ( ) , dl , Val , StoreNode -> getBasePtr ( ) , StoreNode -> getPointerInfo ( ) , StoreNode -> getAlignment ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , StoreNode -> getAAInfo ( ) ) ;


SDValue zmtarzmTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const {


SDValue zmtarzmTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {

SDValue zmtarzmTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


if ( N -> getOpcode ( ) == ISD :: ADDE ) {


return performADDECombine ( N , DAG , DCI , Subtarget ) ;

return performADDECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SUBE ) {


return performSUBECombine ( N , DAG , DCI , Subtarget ) ;

return performSUBECombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SHL ) {


return performSHLCombine ( N , DAG , DCI , Subtarget ) ;

return performSHLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRA ) {


return performSRACombine ( N , DAG , DCI , Subtarget ) ;

return performSRACombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: SRL ) {


return performSRLCombine ( N , DAG , DCI , Subtarget ) ;

return performSRLCombine(N, DAG, DCI, Subtarget);


if ( N -> getOpcode ( ) == ISD :: VSELECT ) {


return performVSELECTCombine ( N , DAG ) ;


if ( N -> getOpcode ( ) == ISD :: SETCC ) {


return TargetLowering :: PerformDAGCombine ( N , DCI ) ;


zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {

zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {

for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {


setBooleanContents ( ZeroOrOneBooleanContent ) ;


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


addRegisterClass ( MVT :: f32 , & zmtarzm :: sFPR32RegClass ) ;


addRegisterClass ( MVT :: f32 , & zmtarzm :: FPR32RegClass ) ;


addRegisterClass ( MVT :: f64 , & zmtarzm :: sFPR64RegClass ) ;


addRegisterClass ( MVT :: f64 , & zmtarzm :: FPR64RegClass ) ;


auto *RegInfo = Subtarget.getRegisterInfo();

auto * RegInfo = Subtarget . getRegisterInfo ( ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);

setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction ( ISD :: ADDCARRY , MVT :: i32 , Legal ) ;

ISD::ADDCARRY zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: SUBCARRY , MVT :: i32 , Legal ) ;

ISD::SUBCARRY zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: BITREVERSE , MVT :: i32 , Legal ) ;

ISD::BITREVERSE zmsplit MVT::i32 zmsplit Legal


setOperationAction ( ISD :: SREM , MVT :: i32 , Expand ) ;

ISD::SREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i32 , Expand ) ;

ISD::UREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIVREM , MVT :: i32 , Expand ) ;

ISD::UDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIVREM , MVT :: i32 , Expand ) ;

ISD::SDIVREM zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SHL_PARTS , MVT :: i32 , Expand ) ;

ISD::SHL_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SRL_PARTS , MVT :: i32 , Expand ) ;

ISD::SRL_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SRA_PARTS , MVT :: i32 , Expand ) ;

ISD::SRA_PARTS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::UMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SMUL_LOHI , MVT :: i32 , Expand ) ;

ISD::SMUL_LOHI zmsplit MVT::i32 zmsplit Expand


setOperationAction(#,             #,   #);

setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);

setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);

setOperationAction(#,              #,   #);


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BR_JT , MVT :: Other , Expand ) ;

ISD::BR_JT zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

ISD :: DYNAMIC_STACKALLOC MVT :: i32 Expand


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setOperationAction ( ISD :: MULHS , MVT :: i32 , Expand ) ;

ISD::MULHS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: MULHU , MVT :: i32 , Expand ) ;

ISD::MULHU zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: VAARG , MVT :: Other , Expand ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand


setLoadExtAction ( ISD :: EXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::EXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: EXTLOAD MVT :: i32 MVT :: i1 Promote


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: SEXTLOAD MVT :: i32 MVT :: i1 Promote


setLoadExtAction ( ISD :: ZEXTLOAD , MVT :: i32 , MVT :: i1 , Promote ) ;

ISD::ZEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i1 zmsplit  Promote

setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote);

ISD :: ZEXTLOAD MVT :: i32 MVT :: i1 Promote


setOperationAction ( ISD :: GlobalAddress , MVT :: i32 , Custom ) ;

ISD::GlobalAddress zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: ExternalSymbol , MVT :: i32 , Custom ) ;

ISD::ExternalSymbol zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: GlobalTLSAddress , MVT :: i32 , Custom ) ;

ISD::GlobalTLSAddress zmsplit MVT::i32 zmsplit Custom

ISD :: GlobalTLSAddress MVT :: i32 Custom


setOperationAction ( ISD :: BlockAddress , MVT :: i32 , Custom ) ;

ISD::BlockAddress zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: JumpTable , MVT :: i32 , Custom ) ;

ISD::JumpTable zmsplit MVT::i32 zmsplit Custom


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i8 , Expand ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i8 zmsplit  Expand

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Expand);

ISD :: SEXTLOAD MVT :: i32 MVT :: i8 Expand


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i32 , MVT :: i16 , Expand ) ;

ISD::SEXTLOAD zmsplit  MVT::i32 zmsplit  MVT::i16 zmsplit  Expand

setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand);

ISD :: SEXTLOAD MVT :: i32 MVT :: i16 Expand


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ABS , MVT :: i32 , Expand ) ;

ISD::ABS zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: BITREVERSE , MVT :: i32 , Expand ) ;

ISD::BITREVERSE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SDIV , MVT :: i32 , Expand ) ;

ISD::SDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: UDIV , MVT :: i32 , Expand ) ;

ISD::UDIV zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ATOMIC_FENCE , MVT :: Other , Expand ) ;

ISD::ATOMIC_FENCE zmsplit MVT::Other zmsplit Expand


ISD :: CondCode FPCCToExtend [ ] = { ISD :: SETONE , ISD :: SETUEQ , ISD :: SETUGT , ISD :: SETUGE , ISD :: SETULT , ISD :: SETULE } ;

ISD::CondCode FPCCToExtend[] = {ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE};


ISD :: NodeType FPOpToExpand [ ] = { ISD :: FSIN , ISD :: FCOS , ISD :: FSINCOS , ISD :: FPOW , ISD :: FREM , ISD :: FCOPYSIGN } ;

ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN};


MVT AllVTy [ ] = { MVT :: f32 , MVT :: f64 } ;


setOperationAction ( ISD :: FREM , VT , Expand ) ;


setOperationAction ( ISD :: SELECT_CC , VT , Expand ) ;

ISD::SELECT_CC zmsplit VT zmsplit Expand


setOperationAction ( ISD :: BR_CC , VT , Expand ) ;


setCondCodeAction ( CC , VT , Expand ) ;


setOperationAction ( Op , VT , Expand ) ;


setOperationAction ( ISD :: ConstantFP , MVT :: f32 , Legal ) ;

ISD::ConstantFP zmsplit MVT::f32 zmsplit Legal


setLoadExtAction ( ISD :: EXTLOAD , MVT :: f64 , MVT :: f32 , Expand ) ;

ISD::EXTLOAD zmsplit  MVT::f64 zmsplit  MVT::f32 zmsplit  Expand

setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);

ISD :: EXTLOAD MVT :: f64 MVT :: f32 Expand


setTruncStoreAction ( MVT :: f64 , MVT :: f32 , Expand ) ;

MVT::f64 zmsplit MVT::f32 zmsplit Expand


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction(#,           #,   #);

setOperationAction(#,           #,   #);


setStackPointerRegisterToSaveRestore ( # ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);

setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


zmtarzmTargetLowering :: zmtarzmTargetLowering ( const TargetMachine & TM , const zmtarzmSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) {

zmtarzmTargetLowering::zmtarzmTargetLowering(const TargetMachine &TM, const zmtarzmSubtarget &STI) : TargetLowering(TM), Subtarget(STI) {


setStackPointerRegisterToSaveRestore ( zmtarzm :: X1 ) ;


for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) {

for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {


addRegisterClass ( MVT :: i32 , & zmtarzm :: GPRRegClass ) ;


auto * RegInfo = Subtarget . getRegisterInfo ( ) ;

auto *RegInfo = Subtarget.getRegisterInfo();


setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ;


for ( auto VT : { MVT :: i1 , MVT :: i8 } ) {


setLoadExtAction ( # , # , MVT :: i1 , # ) ;


setLoadExtAction ( # , # , MVT :: f32 , # ) ;


setLoadExtAction ( # , # , MVT :: f16 , # ) ;


setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ;

setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);


setLoadExtAction ( # , # , F16 # , # ) ;


setOperationAction(#,             #,   #);


setOperationAction(#,               #,   #);


setOperationAction(#,              #,   #);


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setMinimumJumpTableEntries ( INT_MAX ) ;


setCondCodeAction ( CC , VT , Expand ) ;


MVT GRLenVT = Subtarget . getGRLenVT ( ) ;


addRegisterClass ( GRLenVT , & zmtarzm :: GPRRegClass ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setStackPointerRegisterToSaveRestore ( # ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


bool zmtarzmLoopMetadataLowering::runOnFunction(Function &F) {

bool zmtarzmLoopMetadataLowering :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: FRMIDX ) {

if (MI.getOpcode() == zmtarzm::FRMIDX) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


SDValue zmtarzmSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {

SDValue zmtarzmSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


const zmtarzmSubtarget &STI = DAG.getMachineFunction().getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) ;


return EmitMOPS(zmtarzmISD::MOPS_MEMCOPY, DAG, DL, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo);

return EmitMOPS ( zmtarzmISD :: MOPS_MEMCOPY , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ;


if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {

if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) {


return emitMemMem(DAG, DL, zmtarzmISD::MVC, zmtarzmISD::MVC_LOOP, Chain, Dst, Src, CSize->getZExtValue());

return emitMemMem ( DAG , DL , zmtarzmISD :: MVC , zmtarzmISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


return EmitTargetCodeForMemOp(DAG, dl, Chain, Dst, Src, Size, Alignment, isVolatile, AlwaysInline, MustPreserveCheriCapabilities, DstPtrInfo, SrcPtrInfo, true);

return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ;


if ( ! DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) . hasBulkMemory ( ) ) {


SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);

SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ;


return DAG.getNode(zmtarzmISD::MEMORY_COPY, DL, MVT::Other, {Chain, MemIdx, MemIdx, Dst, Src, DAG.getZExtOrTrunc(Size, DL, MVT::i32)});

return DAG . getNode ( zmtarzmISD :: MEMORY_COPY , DL , MVT :: Other , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) } ) ;


bool zmtarzmStackAnalysisPrepare::runOnFunction(Function &F) {

bool zmtarzmStackAnalysisPrepare :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;