return findScratchRegister ( TmpMBB , false , twoUniqueScratchRegsRequired ( TmpMBB ) ) ;

return findScratchRegister(TmpMBB, false, twoUniqueScratchRegsRequired(TmpMBB));


void zmtarzmInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS) {

void zmtarzmInstPrinter :: printBranchOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS ) {


const MCOperand &MO = MI->getOperand(OpNo);

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


return printOperand ( MI , OpNo , STI , OS ) ;


if ( STI . hasFeature ( zmtarzm :: Feature32Bit ) ) {


if ( STI . hasFeature ( zmtarzm :: Feature16Bit ) ) {


if ( ! STI . hasFeature ( zmtarzm :: Feature64Bit ) ) {


EVT zmtarzmTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const {

EVT zmtarzmTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {


return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ;


return VT . changeVectorElementTypeToInteger ( ) ;


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


assert ( VA . getLocVT ( ) == MVT :: f64 ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


unsigned Reg = RVLocs [ i ] . getLocReg ( ) ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1);

Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ;


InVals . push_back ( Chain . getValue ( 0 ) ) ;


SDValue zmtarzmTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


if ( CallCConv != CallingConv :: Fast ) {


report_fatal_error
(
"Unsupported calling convention"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Lowering formal arguments\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"ISelDAG: Lowering formal arguments\n"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Can't lower variadic arguments\n");


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CC_zmtarzm ) ;


CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ;


Chain = DAG.getNode(zmtarzmISD::ENTRY_FLAG, DL, MVT::Other, {Chain, DAG.getRegister(zmtarzm::a1, MVT::i32), DAG.getTargetConstant(4, DL, MVT::i32)});

Chain = DAG . getNode ( zmtarzmISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( zmtarzm :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ;


assert ( ArgLocs . size ( ) == Ins . size ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ;


FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ;


for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


ArgValue = unpack64(DAG, Chain, VA, DL);

ArgValue = unpack64 ( DAG , Chain , VA , DL ) ;


ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);

ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ;


ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);

ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ;


unsigned VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ;


SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());

SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ;


if ( VA . getValVT ( ) == MVT :: i32 ) {


Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, DAG.getConstant(32, DL, MVT::i32));

Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);

Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ;


assert(VA.needsCustom() == false && "Doesn't support custom argument lowering");


unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;

unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;


unsigned ValSize = VA.getValVT().getSizeInBits() / 8;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ;


int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),  MachinePointerInfo::getFixedStack(MF, FI)));

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);

unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


if (VA.getLocInfo() == CCValAssign::Full) {

if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {


if (VA.getLocInfo() == CCValAssign::BCvt) {

if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {


ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);

ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ;


SDValue Val = DAG.getLoad(VA.getLocInfo() == CCValAssign::AExt ? VA.getValVT() : VA.getLocVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())), MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));

SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


InVals.push_back(DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val));

InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ;


ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs);

ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;


unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &RegInfo = MF.getRegInfo();

MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


VaArgOffset = CCInfo . getNextStackOffset ( ) ;


VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ;


int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


zmtarzmFI -> setVarArgsFrameIndex ( FI ) ;


for (unsigned i = Idx; i < ArgRegs.size(); ++i, VaArgOffset += XLenInBytes) {

for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) {


const Register Reg = RegInfo.createVirtualRegister(RC);

const Register Reg = RegInfo . createVirtualRegister ( RC ) ;


RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ;


FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));

SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI));

SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ;


cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


zmtarzmFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ;


Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);

Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ;


unsigned ArgOffset = ArgLocs.size() * 8;

unsigned ArgOffset = ArgLocs . size ( ) * 8 ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LDR ) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STR ) {


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


int zmtarzmTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


return BaseT :: getIntImmCostIntrin ( IID , Idx , Imm , Ty , CostKind ) ;

return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);

return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if (IID == Intrinsic::sadd_with_overflow) {

if ( IID == Intrinsic :: sadd_with_overflow ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < # > ( - Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::uadd_with_overflow) {

if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: zmtarzm_sadd_with_overflow ) {

if (IID == Intrinsic::zmtarzm_sadd_with_overflow) {


if ( IID == Intrinsic :: zmtarzm_uadd_with_overflow ) {

if (IID == Intrinsic::zmtarzm_uadd_with_overflow) {


if ( IID == Intrinsic :: zmtarzm_ssub_with_overflow ) {

if (IID == Intrinsic::zmtarzm_ssub_with_overflow) {


if ( isUInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: zmtarzm_usub_with_overflow ) {

if (IID == Intrinsic::zmtarzm_usub_with_overflow) {


if (IID == Intrinsic::experimental_stackmap) {

if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::experimental_patchpoint_void) {

if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if (IID == Intrinsic::experimental_patchpoint_i64) {

if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


const MCFixupKindInfo & zmtarzmAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {

const MCFixupKindInfo & zmtarzmAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const {


const static MCFixupKindInfo Infos[zmtarzm::NumTargetFixupKinds] = {

const static MCFixupKindInfo Infos [ zmtarzm :: NumTargetFixupKinds ] = {


{ "fixupfixup_zmtarzm_pcrel_adr_imm21" , 0 , 32 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_adr_imm21" zmsplit 0 zmsplit 32 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_adr_imm21", 0, 32, PCRelFlagVal},


{ "fixupfixup_zmtarzm_pcrel_adrp_imm21" , 0 , 32 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_adrp_imm21" zmsplit 0 zmsplit 32 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},


"fixup_zmtarzm_add_imm12" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_add_imm12", 10, 12, 0},


"fixup_zmtarzm_ldst_imm12_scale1" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_ldst_imm12_scale1", 10, 12, 0},


"fixup_zmtarzm_ldst_imm12_scale2" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_ldst_imm12_scale2", 10, 12, 0},


"fixup_zmtarzm_ldst_imm12_scale4" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_ldst_imm12_scale4", 10, 12, 0},


"fixup_zmtarzm_ldst_imm12_scale8" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_ldst_imm12_scale8", 10, 12, 0},


"fixup_zmtarzm_ldst_imm12_scale16" zmsplit 10 zmsplit 12 zmsplit 0

{"fixupfixup_zmtarzm_ldst_imm12_scale16", 10, 12, 0},


{ "fixupfixup_zmtarzm_ldr_pcrel_imm19" , 5 , 19 , PCRelFlagVal } ,

"fixup_zmtarzm_ldr_pcrel_imm19" zmsplit 5 zmsplit 19 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},


"fixup_zmtarzm_movw" zmsplit 5 zmsplit 16 zmsplit 0


{ "fixupfixup_zmtarzm_pcrel_branch14" , 5 , 14 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_branch14" zmsplit 5 zmsplit 14 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_branch14", 5, 14, PCRelFlagVal},


{ "fixupfixup_zmtarzm_pcrel_branch19" , 5 , 19 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_branch19" zmsplit 5 zmsplit 19 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_branch19", 5, 19, PCRelFlagVal},


{ "fixupfixup_zmtarzm_pcrel_branch26" , 0 , 26 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_branch26" zmsplit 0 zmsplit 26 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_branch26", 0, 26, PCRelFlagVal},


{ "fixupfixup_zmtarzm_pcrel_call26" , 0 , 26 , PCRelFlagVal } ,

"fixup_zmtarzm_pcrel_call26" zmsplit 0 zmsplit 26 zmsplit PCRelFlagVal

{"fixupfixup_zmtarzm_pcrel_call26", 0, 26, PCRelFlagVal},


"fixup_zmtarzm_tlsdesc_call" zmsplit 0 zmsplit 0 zmsplit 0

{"fixupfixup_zmtarzm_tlsdesc_call", 0, 0, 0}


if (Kind >= FirstLiteralRelocationKind) {

if ( Kind >= FirstLiteralRelocationKind ) {


return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ;


return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!");

assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;


static_assert((array_lengthof(Infos)) == zmtarzm::NumTargetFixupKinds, "Not all fixup kinds added to Infos array");


return Infos[Kind - FirstTargetFixupKind];

return Infos [ Kind - FirstTargetFixupKind ] ;


static std::unique_ptr<zmtarzmOperand> createImm(const MCExpr *Val, SMLoc S, SMLoc E, bool IsRV64) {

static std :: unique_ptr < zmtarzmOperand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) {


auto Op = std::make_unique<zmtarzmOperand>(KindTy::Immediate);

auto Op = std :: make_unique < zmtarzmOperand > ( KindTy :: Immediate ) ;


static std::unique_ptr<zmtarzmOperand> createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsRV64) {

static std :: unique_ptr < zmtarzmOperand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 ) {


auto Op = std::make_unique<zmtarzmOperand>(KindTy::Register);

auto Op = std :: make_unique < zmtarzmOperand > ( KindTy :: Register ) ;


static std::unique_ptr<zmtarzmOperand> createToken(StringRef Str, SMLoc S, bool IsRV64) {

static std :: unique_ptr < zmtarzmOperand > createToken ( StringRef Str , SMLoc S , bool IsRV64 ) {


auto Op = std::make_unique<zmtarzmOperand>(KindTy::Token);

auto Op = std :: make_unique < zmtarzmOperand > ( KindTy :: Token ) ;


static std::unique_ptr<zmtarzmOperand> createVType(unsigned VTypeI, SMLoc S,  bool IsRV64) {

static std :: unique_ptr < zmtarzmOperand > createVType ( unsigned VTypeI , SMLoc S , bool IsRV64 ) {


auto Op = std::make_unique<zmtarzmOperand>(KindTy::VType);

auto Op = std :: make_unique < zmtarzmOperand > ( KindTy :: VType ) ;


static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, zmtarzmMCExpr::VariantKind &VK) const {

static bool evaluateConstantImm ( const MCExpr * Expr , int64_t & Imm , zmtarzmMCExpr :: VariantKind & VK ) const {


if (auto *RE = dyn_cast<zmtarzmMCExpr>(Expr)) {

if ( auto * RE = dyn_cast < zmtarzmMCExpr > ( Expr ) ) {


return RE -> evaluateAsConstant ( Imm ) ;


if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {

if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) {


const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Value);

const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ;


int64_t Value = ConstExpr -> getValue ( ) ;


if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {

if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) {


return isUInt < 5 > ( CE -> getValue ( ) ) ;


if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {

if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) {


const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());

const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


zmtarzmMCExpr::VariantKind VK = zmtarzmMCExpr::VK_zmtarzm_None;

zmtarzmMCExpr :: VariantKind VK = zmtarzmMCExpr :: VK_zmtarzm_None ;


if (evaluateConstantImm(getImm(), Imm, VK)) {

if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) {


return isShiftedInt < N - 1 , 1 > ( Imm ) && VK == zmtarzmMCExpr :: VK_zmtarzm_None ;

return isShiftedInt<N - 1, 1>(Imm) && VK == zmtarzmMCExpr::VK_zmtarzm_None;


if (!evaluateConstantImm(getImm(), Imm, VK)) {

if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) {


return zmtarzmAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == zmtarzmMCExpr :: VK_zmtarzm_None ;

return zmtarzmAsmParser::classifySymbolRef(getImm(), VK) && VK == zmtarzmMCExpr::VK_zmtarzm_None;


bool zmtarzmCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {

bool zmtarzmCleanupVSETVLI :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) {


const Subtarget &STI = MBB.getParent()->getSubtarget<Subtarget>();

const Subtarget & STI = MBB . getParent ( ) -> getSubtarget < Subtarget > ( ) ;


const InstrInfo *TII = STI.getInstrInfo();

const InstrInfo * TII = STI . getInstrInfo ( ) ;


InstrInfo = MBB . getParent ( ) -> getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


for (MachineBasicBlock::iterator I = MBB.instr_begin(); I != MBB.instr_end(); ++I) {

for ( MachineBasicBlock :: iterator I = MBB . instr_begin ( ) ; I != MBB . instr_end ( ) ; ++ I ) {


BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(zmtarzm::NOP));

BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( zmtarzm :: NOP ) ) ;


MIBundleBuilder(MBB, I, std::next(I, 2));

MIBundleBuilder ( MBB , I , std :: next ( I , 2 ) ) ;


if (insertStall(MBB, I, TII, MI->getOpcode())) {

if ( insertStall ( MBB , I , TII , MI -> getOpcode ( ) ) ) {


if (InstrInfo->isStoreToStackSlot(Inst, FI)) {

if ( InstrInfo -> isStoreToStackSlot ( Inst , FI ) ) {


static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned char cmode = (insn >> 8) & 0xF;

unsigned char cmode = ( insn >> 8 ) & 0xF ;


const JmpExtraValues *extra = (reinterpret_cast<const JmpExtraValues*>(Addr));

const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ;


uint64_t address = extra->Address + extra->Imm;

uint64_t address = extra -> Address + extra -> Imm ;


if (!tryAddingSymbolicOperand(address, 0, true, 0, Inst, Decoder)) {

if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) {


Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ;


unsigned Register = PredicateTable[extra->Predicate];

unsigned Register = PredicateTable [ extra -> Predicate ] ;


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


Inst . addOperand ( MCOperand :: createImm ( # ) ) ;

Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < 16 > ( Offset ) ) ) ;


static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrRdSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {

static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) {


unsigned zmtarzmELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {

unsigned zmtarzmELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {


if (SExpr = dyn_cast<zmtarzmMCExpr>(Fixup.getValue())) {

if ( SExpr = dyn_cast < zmtarzmMCExpr > ( Fixup . getValue ( ) ) ) {


if ( SExpr -> getKind ( ) == zmtarzmMCExpr :: VK_zmtarzm_R_DISP32 ) {

if (SExpr->getKind() == zmtarzmMCExpr::VK_zmtarzm_R_DISP32) {


if (Kind >= FirstLiteralRelocationKind){

if ( Kind >= FirstLiteralRelocationKind ) {


return Kind - FirstLiteralRelocationKind;

return Kind - FirstLiteralRelocationKind ;


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


if ( Kind == zmtarzm :: fixup_zmtarzm_call30 ) {

if(Kind == zmtarzm::fixup_zmtarzm_call30) {


if ( Kind == zmtarzm :: fixup_zmtarzm_br22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_br22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_br19 ) {

if(Kind == zmtarzm::fixup_zmtarzm_br19) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_pc10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_pc10) {


if ( Kind == zmtarzm :: fixup_zmtarzm_wplt30 ) {

if(Kind == zmtarzm::fixup_zmtarzm_wplt30) {


Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");

Ctx
.
reportError
(
Fixup
.
getLoc
(
)
,
"Unsupported relocation type"
)
;


if ( Kind == zmtarzm :: fixup_zmtarzm_hi22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_hi22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_lo10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_lo10) {


if ( Kind == zmtarzm :: fixup_zmtarzm_h44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_h44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_m44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_m44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_l44 ) {

if(Kind == zmtarzm::fixup_zmtarzm_l44) {


if ( Kind == zmtarzm :: fixup_zmtarzm_hh ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_hm ) {


if ( Kind == zmtarzm :: fixup_zmtarzm_got22 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got22) {


if ( Kind == zmtarzm :: fixup_zmtarzm_got10 ) {

if(Kind == zmtarzm::fixup_zmtarzm_got10) {


Ctx . reportError ( Fixup . getLoc ( ) , # ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


MachineBasicBlock * EntryBlock = MF -> begin ( ) ;

MachineBasicBlock *EntryBlock = MF->begin();


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


Optional<DestSourcePair> zmtarzmInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {

Optional < DestSourcePair > zmtarzmInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ;


if ( MI . getOpcode ( ) == zmtarzm :: ORri ) {


if ( MI . getOperand ( 2 ) . getImm ( ) == 0x0 ) {


if ( MI . getOpcode ( ) == zmtarzm :: ORrr ) {


if (MI.getOperand(1).getReg() == zmtarzm::WZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: WZR ) {


if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) {


return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ;


if (MI.getOperand(2).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 2 ) . getReg ( ) == zmtarzm :: R0 ) {


if (MI.getOperand(1).getReg() == zmtarzm::XZR) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: XZR ) {


if (MI.getOperand(1).getReg() == zmtarzm::R0) {

if ( MI . getOperand ( 1 ) . getReg ( ) == zmtarzm :: R0 ) {


bool zmtarzmDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {

bool zmtarzmDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


imm = CurDAG->getTargetConstant(bit, MVT::i32);

imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) {


bool zmtarzmDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {

bool zmtarzmDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC ) {

if (Op.getOpcode() == zmtarzmISD::SETCC) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SELECT_CC ) {

if (Op.getOpcode() == zmtarzmISD::SELECT_CC) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


bool zmtarzmTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {

bool zmtarzmTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const {


if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) {

if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) {


AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;

AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ;


if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {

if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) {


if (LD->getExtensionType() != ISD::NON_EXTLOAD) {

if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) {


if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {

if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) {


if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


if ( Op -> getOpcode ( ) == ISD :: SUB ) {


Offset = DAG.getConstant(RHSC, DL, MVT::i8);

Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ;


if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {

if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


if ( zmtarzm :: isProgramMemoryAccess ( ST ) ) {


LoadSDNode * LD = cast < LoadSDNode > ( N ) ;


if ( Op -> getOpcode ( ) == ISD :: ADD ) {


Offset = DAG . getConstant ( RHSC , VT ) ;


if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {

if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) {


uint64_t RHSC = RHS -> getZExtValue ( ) ;


Register zmtarzmTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const {

Register zmtarzmTargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const {


const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();

const MCRegisterInfo * MRI = Subtarget -> getRegisterInfo ( ) ;


unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);

unsigned DwarfRegNum = MRI -> getDwarfRegNum ( Reg , false ) ;


if ( ! Subtarget -> isXRegisterReserved ( DwarfRegNum ) ) {


report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;

report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName) + "\"."));


bool zmtarzmTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const {

bool zmtarzmTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const {


if ( Intrinsic == Intrinsic :: zmtarzm_ldaxr ) {

if (Intrinsic == Intrinsic::zmtarzm_ldaxr) {


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ;


Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 0 ) ;


Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_ldxr ) {

if (Intrinsic == Intrinsic::zmtarzm_ldxr) {


if ( Intrinsic == Intrinsic :: zmtarzm_stlxr ) {

if (Intrinsic == Intrinsic::zmtarzm_stlxr) {


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 1 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_stxr ) {

if (Intrinsic == Intrinsic::zmtarzm_stxr) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldaxp ) {

if (Intrinsic == Intrinsic::zmtarzm_ldaxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldxp ) {

if (Intrinsic == Intrinsic::zmtarzm_ldxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_stlxp ) {

if (Intrinsic == Intrinsic::zmtarzm_stlxp) {


Info . ptrVal = I . getArgOperand ( 2 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_stxp ) {

if (Intrinsic == Intrinsic::zmtarzm_stxp) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2) {


uint64_t NumElts = I.getModule()->getDataLayout().getTypeSizeInBits(I.getType()) / 64;

uint64_t NumElts = I . getModule ( ) -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) / 64 ;


Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);

Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ;


Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);

Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x2 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x2) {


EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts )


Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;

Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ;


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x3 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x3) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld1x4 ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld1x4) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4lane ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4lane) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld2r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld2r) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld3r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld3r) {


if ( Intrinsic == Intrinsic :: zmtarzm_neon_ld4r ) {

if (Intrinsic == Intrinsic::zmtarzm_neon_ld4r) {


SDValue zmtarzmTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


if ( ! isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


EVT ExtrTy = WideTy.getVectorElementType();

EVT ExtrTy = WideTy . getVectorElementType ( ) ;


if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {

if ( const ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ) {


SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue Result = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result, DAG.getConstant(16, SL, MVT::i32));

Result = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , Result , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


if ( ResultVT . bitsLT ( MVT :: i32 ) ) {


Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);

Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ;


return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);

return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;


SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);

SDValue Sixteen = DAG . getConstant ( 16 , SL , MVT :: i32 ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , Sixteen ) ;


SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BC = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);

SDValue Elt = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , BC , ScaledIdx ) ;


if ( Subtarget . isHVXVectorType ( VecTy ) ) {


return LowerHvxExtractElement ( Op , DAG ) ;


MVT ElemTy = ty(Vec).getVectorElementType();

MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;


SDValue Vector = Op . getOperand ( 0 ) ;


SDValue LaneIndex = Op . getOperand ( 1 ) ;


if (Vector.getSimpleValueType() != MVT::v16i1) {

if ( Vector . getSimpleValueType ( ) != MVT :: v16i1 ) {


SDValue MaskBits = DAG.getNode(zmtarzmISD::MASK_TO_INT, DL, MVT::i32, Vector);

SDValue MaskBits = DAG . getNode ( zmtarzmISD :: MASK_TO_INT , DL , MVT :: i32 , Vector ) ;


SDValue Elem = DAG.getNode(ISD::SRL, DL, MVT::i32, MaskBits, LaneIndex);

SDValue Elem = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , MaskBits , LaneIndex ) ;


if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {

if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) {


uint64_t Index = CIndexN->getZExtValue();

uint64_t Index = CIndexN -> getZExtValue ( ) ;


unsigned Mask = VecVT.getVectorNumElements() - 1;

unsigned Mask = VecVT . getVectorNumElements ( ) - 1 ;


MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VecVT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);

SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ;


return extractVector ( Vec , Op . getOperand ( 1 ) , SDLoc ( Op ) , ElemTy , ty ( Op ) , DAG ) ;

return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);


SDValue zmtarzmTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


if ( ! isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


EVT ExtrTy = WideTy.getVectorElementType();

EVT ExtrTy = WideTy . getVectorElementType ( ) ;


if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {

if ( const ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ) {


SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue Result = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result, DAG.getConstant(16, SL, MVT::i32));

Result = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , Result , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


if ( ResultVT . bitsLT ( MVT :: i32 ) ) {


Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);

Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ;


return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);

return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;


SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);

SDValue Sixteen = DAG . getConstant ( 16 , SL , MVT :: i32 ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , Sixteen ) ;


SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BC = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);

SDValue Elt = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , BC , ScaledIdx ) ;


if ( Subtarget . isHVXVectorType ( VecTy ) ) {


return LowerHvxExtractElement ( Op , DAG ) ;


MVT ElemTy = ty(Vec).getVectorElementType();

MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;


SDValue Vector = Op . getOperand ( 0 ) ;


SDValue LaneIndex = Op . getOperand ( 1 ) ;


if (Vector.getSimpleValueType() != MVT::v16i1) {

if ( Vector . getSimpleValueType ( ) != MVT :: v16i1 ) {


SDValue MaskBits = DAG.getNode(zmtarzmISD::MASK_TO_INT, DL, MVT::i32, Vector);

SDValue MaskBits = DAG . getNode ( zmtarzmISD :: MASK_TO_INT , DL , MVT :: i32 , Vector ) ;


SDValue Elem = DAG.getNode(ISD::SRL, DL, MVT::i32, MaskBits, LaneIndex);

SDValue Elem = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , MaskBits , LaneIndex ) ;


if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {

if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) {


uint64_t Index = CIndexN->getZExtValue();

uint64_t Index = CIndexN -> getZExtValue ( ) ;


unsigned Mask = VecVT.getVectorNumElements() - 1;

unsigned Mask = VecVT . getVectorNumElements ( ) - 1 ;


MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VecVT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);

SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ;


return DAG . getNode ( ISD :: BITCAST , DL , VT , Res ) ;

return DAG.getNode(ISD::BITCAST, DL, VT, Res);


SDValue zmtarzmTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Should only be called for ISD::INSERT_VECTOR_ELT");


ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


if (CI->getZExtValue() >= VT.getVectorNumElements()) {

if ( CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) {


SDValue Mtvsrz = DAG.getNode(PPCISD::MTVSRZ, dl, VT, V2);

SDValue Mtvsrz = DAG . getNode ( PPCISD :: MTVSRZ , dl , VT , V2 ) ;


unsigned BytesInEachElement = VT.getVectorElementType().getSizeInBits() / 8;

unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ;


unsigned InsertAtElement = C->getZExtValue();

unsigned InsertAtElement = C -> getZExtValue ( ) ;


unsigned InsertAtByte = InsertAtElement * BytesInEachElement;

unsigned InsertAtByte = InsertAtElement * BytesInEachElement ;


InsertAtByte = (16 - BytesInEachElement) - InsertAtByte;

InsertAtByte = ( 16 - BytesInEachElement ) - InsertAtByte ;


return DAG . getNode ( PPCISD :: VECINSERT , dl , VT , V1 , Mtvsrz , DAG . getConstant ( InsertAtByte , dl , MVT :: i32 ) ) ;

return DAG.getNode(PPCISD::VECINSERT, dl, VT, V1, Mtvsrz, DAG.getConstant(InsertAtByte, dl, MVT::i32));


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, Op.getOperand(1), Op.getOperand(2));

SDValue Node = DAG . getNode ( ISD :: INSERT_VECTOR_ELT , DL , WideTy , WideVec , Op . getOperand ( 1 ) , Op . getOperand ( 2 ) ) ;


SDValue Val = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Op.getOperand(1));

SDValue Val = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i16 , Op . getOperand ( 1 ) ) ;


SDValue ExtVal = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Val);

SDValue ExtVal = DAG . getNode ( ISD :: ZERO_EXTEND , SL , MVT :: i32 , Val ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, DAG.getConstant(16, SL, MVT::i32));

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BCVec = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue BFM = DAG.getNode(ISD::SHL, SL, MVT::i32, DAG.getConstant(0xffff, SL, MVT::i32), ScaledIdx);

SDValue BFM = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , DAG . getConstant ( 0xffff , SL , MVT :: i32 ) , ScaledIdx ) ;


SDValue LHS = DAG.getNode(ISD::AND, SL, MVT::i32, BFM, ExtVal);

SDValue LHS = DAG . getNode ( ISD :: AND , SL , MVT :: i32 , BFM , ExtVal ) ;


SDValue RHS = DAG.getNode(ISD::AND, SL, MVT::i32, DAG.getNOT(SL, BFM, MVT::i32), BCVec);

SDValue RHS = DAG . getNode ( ISD :: AND , SL , MVT :: i32 , DAG . getNOT ( SL , BFM , MVT :: i32 ) , BCVec ) ;


SDValue BFI = DAG.getNode(ISD::OR, SL, MVT::i32, LHS, RHS);

SDValue BFI = DAG . getNode ( ISD :: OR , SL , MVT :: i32 , LHS , RHS ) ;


MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getScalarSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);

SDValue Res = DAG . getNode ( ISD :: INSERT_VECTOR_ELT , DL , IntVecVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , DAG . getNode ( ISD :: BITCAST , DL , IntVT , Op1 ) , Op2 ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ;


return DAG.getNode(zmtarzmISD::THREAD_POINTER, DL, PtrVT);

return DAG . getNode ( zmtarzmISD :: THREAD_POINTER , DL , PtrVT ) ;


if ( IntNo == Intrinsic :: zmtarzm_thread_pointer ) {

if (IntNo == Intrinsic::zmtarzm_thread_pointer) {


SmallVector<SDValue, 16> Ops(std::next(Op->op_begin()), Op->op_end());

SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ;


bool SmallTuple = Size <= zmtarzmTargetMachine::SmallTupleLimit;

bool SmallTuple = Size <= zmtarzmTargetMachine :: SmallTupleLimit ;


Ops.push_back(DAG.getConstant(Size, DL, MVT::i257, SmallTuple));

Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ;


unsigned Cmd = SmallTuple ? zmtarzmISD::TUPLE : zmtarzmISD::TUPLEVAR;

unsigned Cmd = SmallTuple ? zmtarzmISD :: TUPLE : zmtarzmISD :: TUPLEVAR ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const zmtarzmTargetMachine *TM = static_cast<const zmtarzmTargetMachine *>(&DAG.getTarget());

const zmtarzmTargetMachine * TM = static_cast < const zmtarzmTargetMachine * > ( & DAG . getTarget ( ) ) ;


TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ;


SDValue Addr = DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);

SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ;


Addr = makeHiLoPair(Addr, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_HI32, zmtarzmMCExpr::VK_zmtarzm_GOTOFF_LO32, DAG);

Addr = makeHiLoPair ( Addr , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_HI32 , zmtarzmMCExpr :: VK_zmtarzm_GOTOFF_LO32 , DAG ) ;


SDValue GlobalBase = DAG.getNode(zmtarzmISD::GLOBAL_BASE_REG, DL, VT);

SDValue GlobalBase = DAG . getNode ( zmtarzmISD :: GLOBAL_BASE_REG , DL , VT ) ;


return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);

return DAG . getNode ( ISD :: ADD , DL , VT , GlobalBase , Addr ) ;


const zmtarzmTargetLowering &TLI = DAG.getTargetLoweringInfo();

const zmtarzmTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());

MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ;


auto &Context = MF.getMMI().getContext();

auto & Context = MF . getMMI ( ) . getContext ( ) ;


MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber()));

MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ;


EVT PtrVT = getPointerTy(DAG.getDataLayout());

EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


return DAG . getRegister ( zmtarzm :: G7 , PtrVT ) ;


SDValue zmtarzmTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const {


MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;