New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: FRMIDX ) {

if (MI.getOpcode() == zmtarzm::FRMIDX) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


auto &Subtarget = MF->getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF -> getSubtarget < zmtarzmSubtarget > ( ) ;


if (MF->getFunction().getCallingConv() == #) {

if ( MF -> getFunction ( ) . getCallingConv ( ) == # ) {


if ( MF -> getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) {


if (MF->getFnAttribute("interrupt").getValueAsString() == #) {

if ( MF -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == # ) {


if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


if ( Subtarget . hasFPUv3DoubleFloat ( ) ) {


if ( Subtarget . hasFPUv3SingleFloat ( ) ) {


if ( Subtarget . hasFPUv2DoubleFloat ( ) ) {


if ( Subtarget . hasFPUv2SingleFloat ( ) ) {


if ( Subtarget . getTargetABI ( ) == # ) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32S ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32S) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64S ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64S) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32F ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32F) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64F ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64F) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_ILP32D ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_ILP32D) {


if ( Subtarget . getTargetABI ( ) == zmtarzmABI :: ABI_LP64D ) {

if (Subtarget.getTargetABI() == zmtarzmABI::ABI_LP64D) {


llvm_unreachable
(
"Unrecognized ABI"
)
;


const uint32_t *zmtarzmRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const {

const uint32_t * zmtarzmRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {


auto &Subtarget = MF.getSubtarget<zmtarzmSubtarget>();

auto & Subtarget = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


if ( CC == CallingConv :: PreserveAll ) {


if ( CC == CallingConv :: Z80_LibCall ) {


if ( CC == CallingConv :: Z80_LibCall_AC ) {

if (CC == CallingConv::Z80_LibCall_AC) {


if ( CC == CallingConv :: Z80_LibCall_BC ) {

if (CC == CallingConv::Z80_LibCall_BC) {


if ( CC == CallingConv :: Z80_LibCall_C ) {


if ( CC == CallingConv :: Z80_LibCall_L ) {


Register zmtarzmRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

Register zmtarzmRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


const TargetFrameLowering *TFI = getFrameLowering(MF);

const TargetFrameLowering * TFI = getFrameLowering ( MF ) ;


return TFI -> hasFP ( MF ) ? zmtarzm :: FP : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::FP : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: R28 : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::R28 : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: X2 : zmtarzm :: X1 ;

return TFI->hasFP(MF) ? zmtarzm::X2 : zmtarzm::X1  ;


return TFI -> hasFP ( MF ) ? zmtarzm :: R8 : zmtarzm :: R14 ;

return TFI->hasFP(MF) ? zmtarzm::R8 : zmtarzm::R14;


return TFI -> hasFP ( MF ) ? zmtarzm :: J : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::J : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: RFP : zmtarzm :: RSP ;

return TFI->hasFP(MF) ? zmtarzm::RFP : zmtarzm::RSP;


return TFI -> hasFP ( MF ) ? zmtarzm :: R22 : zmtarzm :: R3 ;

return TFI->hasFP(MF) ? zmtarzm::R22 : zmtarzm::R3;


return TFI -> hasFP ( MF ) ? zmtarzm :: FPW : zmtarzm :: SPW ;

return TFI->hasFP(MF) ? zmtarzm::FPW : zmtarzm::SPW;


return TFI->hasFP(MF) ? zmtarzm::X2 : zmtarzm::X1;


return TFI -> hasFP ( MF ) ? zmtarzm :: A14 : zmtarzm :: A10 ;

return TFI->hasFP(MF) ? zmtarzm::A14 : zmtarzm::A10;


const uint32_t *zmtarzmRegisterInfo::getNoPreservedMask() const {

const uint32_t * zmtarzmRegisterInfo :: getNoPreservedMask ( ) const {


const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const override {

const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override {


return & zmtarzm :: PTRDISPREGSRegClass ;


BitVector zmtarzmRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


const zmtarzmFrameLowering *TFI = getFrameLowering(MF);

const zmtarzmFrameLowering * TFI = getFrameLowering ( MF ) ;


for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {

for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) {


if ( MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


if ( ! MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


markSuperRegs ( Reserved , zmtarzm :: W10 ) ;


markSuperRegs ( Reserved , zmtarzm :: W11 ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) {


if ( zmtarzm :: hasPACStackAttribute ( MF ) ) {


assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


markSuperRegs ( Reserved , zmtarzm :: X0 ) ;


markSuperRegs ( Reserved , zmtarzm :: X1 ) ;


markSuperRegs ( Reserved , zmtarzm :: X2 ) ;


markSuperRegs ( Reserved , zmtarzm :: FR ) ;


markSuperRegs ( Reserved , zmtarzm :: SP ) ;


if ( ! MF . getSubtarget < zmtarzmSubtarget > ( ) . hasE2 ( ) ) {


markSuperRegs ( Reserved , zmtarzm :: R14 ) ;


markSuperRegs ( Reserved , zmtarzm :: R7 ) ;


markSuperRegs ( Reserved , zmtarzm :: R26 ) ;


markSuperRegs ( Reserved , zmtarzm :: R27 ) ;


markSuperRegs ( Reserved , zmtarzm :: R28 ) ;


markSuperRegs ( Reserved , zmtarzm :: R29 ) ;


markSuperRegs ( Reserved , zmtarzm :: R30 ) ;


markSuperRegs ( Reserved , zmtarzm :: R31 ) ;


BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


const zmtarzmFrameLowering * TFI = getFrameLowering ( MF ) ;


for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) {


if ( MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


if ( ! MF . getSubtarget < zmtarzmSubtarget > ( ) . # ) {


if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) {


if ( zmtarzm :: hasPACStackAttribute ( MF ) ) {


markSuperRegs ( Reserved , zmtarzm :: R0 ) ;


markSuperRegs ( Reserved , zmtarzm :: R2 ) ;


markSuperRegs ( Reserved , zmtarzm :: R3 ) ;


markSuperRegs ( Reserved , zmtarzm :: R21 ) ;


markSuperRegs ( Reserved , zmtarzm :: R22 ) ;


assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


markSuperRegs ( Reserved , zmtarzm :: SP ) ;


markSuperRegs ( Reserved , zmtarzm :: PC ) ;


markSuperRegs ( Reserved , zmtarzm :: SP_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: R8_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: R9_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: R10_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: R11_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: R12_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: PC_USER ) ;


markSuperRegs ( Reserved , zmtarzm :: MCR ) ;


markSuperRegs ( Reserved , zmtarzm :: FRET ) ;


markSuperRegs ( Reserved , zmtarzm :: R11 ) ;


bool zmtarzmRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const {

bool zmtarzmRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const {


const auto *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const auto * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


if ( zmtarzm :: PRegsRegClass . contains ( Reg ) ) {


FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ;


FrameIdx = FI -> getCRSpillFrameIndex ( ) ;


bool zmtarzmRegisterInfo::isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const {


return ! MF . getSubtarget < zmtarzmSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ;


bool zmtarzmRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {

bool zmtarzmRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const {


if ( PhysReg == zmtarzm :: SGPR_NULL ) {


if ( PhysReg == zmtarzm :: SRC_SHARED_BASE ) {

if (PhysReg == zmtarzm::SRC_SHARED_BASE) {


if ( PhysReg == zmtarzm :: SRC_PRIVATE_BASE ) {

if (PhysReg == zmtarzm::SRC_PRIVATE_BASE) {


if ( PhysReg == zmtarzm :: SRC_SHARED_LIMIT ) {

if (PhysReg == zmtarzm::SRC_SHARED_LIMIT) {


if ( PhysReg == zmtarzm :: SRC_PRIVATE_LIMIT ) {

if (PhysReg == zmtarzm::SRC_PRIVATE_LIMIT) {


if ( PhysReg == zmtarzm :: V_LANE_ID_32 ) {


if ( PhysReg == zmtarzm :: V_LANE_ID_16 ) {


if ( PhysReg == zmtarzm :: V_LANE_ID_8 ) {


zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(#, 0, 0, 0, HwMode) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( # , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: X0 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::X0, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: GR0 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::GR0, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: R1 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::R1, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( 0 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(0, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: X1 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::X1, 0, 0, 0, HwMode) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( unsigned HwMode ) : zmtarzmGenRegisterInfo ( zmtarzm :: r0 , 0 , 0 , 0 , HwMode ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(unsigned HwMode) : zmtarzmGenRegisterInfo(zmtarzm::r0, 0, 0, 0, HwMode) {


bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {

bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {


bool requiresRegisterScavenging(const MachineFunction &MF) const override {

bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


bool zmtarzmFrepLoops::checkForImmediate(const MachineOperand &MO, int64_t &Val) const {

bool zmtarzmFrepLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const {


MachineInstr * DI = MRI -> getVRegDef ( R ) ;


if (!checkForImmediate(DI->getOperand(1), TV)) {

if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) {


if (MO.getSubReg() == zmtarzm::subreg_loreg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if (MO.getSubReg() == zmtarzm::subreg_hireg) {

if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


if (DOpc == zmtarzm::CONST32_Int_Real) {

if ( DOpc == zmtarzm :: CONST32_Int_Real ) {


if (DOpc == zmtarzm::CONST64_Int_Real) {

if ( DOpc == zmtarzm :: CONST64_Int_Real ) {


if ( DOpc == zmtarzm :: A2_combineii ) {


const MachineOperand &S1 = DI->getOperand(1);

const MachineOperand & S1 = DI -> getOperand ( 1 ) ;


const MachineOperand &S2 = DI->getOperand(2);

const MachineOperand & S2 = DI -> getOperand ( 2 ) ;


if ( ! checkForImmediate ( S1 , V1 ) ) {


if ( ! checkForImmediate ( S2 , V2 ) ) {


if ( DOpc == zmtarzm :: A4_combineir ) {


if ( DOpc == zmtarzm :: A4_combineii ) {


if ( DOpc == zmtarzm :: A4_combineri ) {


if (DOpc == TargetOpcode::REG_SEQUENCE) {

if ( DOpc == TargetOpcode :: REG_SEQUENCE ) {


const MachineOperand &S3 = DI->getOperand(3);

const MachineOperand & S3 = DI -> getOperand ( 3 ) ;


if ( ! checkForImmediate ( S3 , V3 ) ) {


unsigned Sub2 = DI->getOperand(2).getImm();

unsigned Sub2 = DI -> getOperand ( 2 ) . getImm ( ) ;


unsigned Sub4 = DI->getOperand(4).getImm();

unsigned Sub4 = DI -> getOperand ( 4 ) . getImm ( ) ;


if ( MO . getSubReg ( ) == zmtarzm :: subreg_loreg ) {


if ( MO . getSubReg ( ) == zmtarzm :: subreg_hireg ) {


llvm_unreachable("Unexpected form of REG_SEQUENCE");

llvm_unreachable
(
"Unexpected form of REG_SEQUENCE"
)
;


bool zmtarzmHardwareLoops::containsInvalidInstruction(MachineLoop *L) const {

bool zmtarzmHardwareLoops :: containsInvalidInstruction ( MachineLoop * L ) const {


LLVM_DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nhw_loop head, BB#"
<<
Blocks
[
0
]
->
getNumber
(
)
;
)
;


for (MachineBasicBlock *MBB : L->getBlocks()) {

for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) {


LLVM_DEBUG(dbgs() << "\nCannot convert to hwloop due to:"; MI.dump(););

LLVM_DEBUG
(
dbgs
(
)
<<
"\nCannot convert to hwloop due to:"
;
MI
.
dump
(
)
;
)
;


bool zmtarzmHardwareLoops::convertToHardwareLoop(MachineLoop *L, bool &RecL0used, bool &RecL1used) {

bool zmtarzmHardwareLoops :: convertToHardwareLoop ( MachineLoop * L , bool & RecL0used , bool & RecL1used ) {


assert(L->getHeader() && "Loop without a header?");

assert
(
L
->
getHeader
(
)
&&
"Loop without a header?"
)
;


for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {

for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) {


Changed = Changed | convertToHardwareLoop(*I, RecL0used, RecL1used);

Changed = Changed | convertToHardwareLoop ( * I , RecL0used , RecL1used ) ;


if (containsInvalidInstruction(L, IsInnerHWLoop)) {

if ( containsInvalidInstruction ( L , IsInnerHWLoop ) ) {


MachineBasicBlock *LastMBB = getExitingBlock(L);

MachineBasicBlock * LastMBB = getExitingBlock ( L ) ;


MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();

MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ;


MachineBasicBlock *Preheader = L->getLoopPreheader();

MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ;


Preheader = createPreheaderForLoop ( L ) ;


MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();

MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ;


SmallVector < MachineInstr * , 2 > OldInsts ;


CountValue *TripCount = getLoopTripCount(L, OldInsts);

CountValue * TripCount = getLoopTripCount ( L , OldInsts ) ;


MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());

MachineInstr * TCDef = MRI -> getVRegDef ( TripCount -> getReg ( ) ) ;


MachineBasicBlock *BBDef = TCDef->getParent();

MachineBasicBlock * BBDef = TCDef -> getParent ( ) ;


if (!MDT->dominates(BBDef, Preheader)) {

if ( ! MDT -> dominates ( BBDef , Preheader ) ) {


MachineBasicBlock *TopBlock = L->getTopBlock();

MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ;


MachineBasicBlock *ExitingBlock = getExitingBlock(L);

MachineBasicBlock * ExitingBlock = getExitingBlock ( L ) ;


if (ExitingBlock != L->getLoopLatch()) {

if ( ExitingBlock != L -> getLoopLatch ( ) ) {


SmallVector < MachineOperand , 2 > Cond ;


if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) {

if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) {


if (ExitingBlock == L->getLoopLatch()) {

if ( ExitingBlock == L -> getLoopLatch ( ) ) {


DEBUG(dbgs() << "Change to hardware loop at "; L->dump());

DEBUG
(
dbgs
(
)
<<
"Change to hardware loop at "
;
L
->
dump
(
)
)
;


if ( InsertPos != Preheader -> end ( ) ) {


unsigned CountReg = MRI->createVirtualRegister(&zmtarzm::IntRegsRegClass);

unsigned CountReg = MRI -> createVirtualRegister ( & zmtarzm :: IntRegsRegClass ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg(), 0, TripCount->getSubReg());

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , 0 , TripCount -> getSubReg ( ) ) ;


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart).addReg(CountReg);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ;


assert(TripCount->isImm() && "Expecting immediate value for trip count");


int64_t CountImm = TripCount -> getImm ( ) ;


if (!TII->isValidOffset(LOOP_i, CountImm)) {

if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(zmtarzm::A2_tfrsi), CountReg).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( zmtarzm :: A2_tfrsi ) , CountReg ) . addImm ( CountImm ) ;


if (TII->isValidOffset(LOOP_i, CountImm)) {

if ( TII -> isValidOffset ( LOOP_i , CountImm ) ) {


BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i)).addMBB(LoopStart).addImm(CountImm);

BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ;


BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ;


DebugLoc LastIDL = LastI->getDebugLoc();

DebugLoc LastIDL = LastI -> getDebugLoc ( ) ;


BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);

BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpt ) {


MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();

MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ;


if ( ! L -> contains ( BranchTarget ) ) {


SmallVector < MachineOperand , 0 > Cond ;


TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);

TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ;


if (LastI->getOpcode() == zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) == zmtarzm :: J2_jumpf ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpt) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpt ) {


if (LastI->getOpcode() != zmtarzm::J2_jumpf) {

if ( LastI -> getOpcode ( ) != zmtarzm :: J2_jumpf ) {


for (unsigned i = 0; i < OldInsts.size(); ++i) {

for ( unsigned i = 0 ; i < OldInsts . size ( ) ; ++ i ) {


explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {

explicit CountValue ( CountValueType t , unsigned v , unsigned u = 0 ) {


FunctionPass * createzmtarzmFrepLoopsPass ( ) {


const MachineInstr * zmtarzmFrepLoops::findBranchInstruction(MachineLoop *L) {

const MachineInstr * zmtarzmFrepLoops :: findBranchInstruction ( MachineLoop * L ) {


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineBasicBlock *Header = L->getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


MachineBasicBlock *Latch = L->getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


using RegisterBump = std::pair<unsigned, int64_t>;

using RegisterBump = std :: pair < unsigned , int64_t > ;


using InductionMap = std::map<unsigned, RegisterBump>;

using InductionMap = std :: map < unsigned , RegisterBump > ;


using instr_iterator = MachineBasicBlock::instr_iterator;

using instr_iterator = MachineBasicBlock :: instr_iterator ;


for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) {

for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) {


for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (Phi->getOperand(i+1).getMBB() != Latch) {

if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) {


unsigned PhiOpReg = Phi->getOperand(i).getReg();

unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ;


MachineInstr *DI = MRI->getVRegDef(PhiOpReg);

MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ;


if (DI->getDesc().getOpcode() == zmtarzm::ADDI) {

if ( DI -> getDesc ( ) . getOpcode ( ) == zmtarzm :: ADDI ) {


unsigned IndReg = DI->getOperand(1).getReg();

unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ;


MachineOperand &Opnd2 = DI->getOperand(2);

MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ;


if ( MRI -> getVRegDef ( IndReg ) == Phi ) {


if ( checkForImmediate ( Opnd2 , V ) ) {


unsigned UpdReg = DI->getOperand(0).getReg();

unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ;


IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ;


SmallVector < MachineOperand , 2 > Cond ;


MachineBasicBlock *TB = nullptr, *FB = nullptr;

MachineBasicBlock * TB = nullptr , * FB = nullptr ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


unsigned PredR , PredPos , PredRegFlags ;


if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) {


MachineInstr *PredI = MRI->getVRegDef(PredR);

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);

bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


InductionMap::iterator IndMapEnd = IndMap.end();

InductionMap :: iterator IndMapEnd = IndMap . end ( ) ;


InductionMap :: iterator F = IndMapEnd ;


InductionMap::iterator F1 = IndMap.find(CmpReg1);

InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ;


InductionMap::iterator F2 = IndMap.find(CmpReg2);

InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ;


IVOp = MRI -> getVRegDef ( F -> first ) ;


bool zmtarzmHardwareLoops::findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp) const {

bool zmtarzmHardwareLoops :: findInductionRegister ( MachineLoop * L , unsigned & Reg , int64_t & IVBump , MachineInstr * & IVOp ) const {


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineBasicBlock *Header = L->getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


MachineBasicBlock *Latch = L->getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


using RegisterBump = std::pair<unsigned, int64_t>;

using RegisterBump = std :: pair < unsigned , int64_t > ;


using InductionMap = std::map<unsigned, RegisterBump>;

using InductionMap = std :: map < unsigned , RegisterBump > ;


using instr_iterator = MachineBasicBlock::instr_iterator;

using instr_iterator = MachineBasicBlock :: instr_iterator ;


for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) {

for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) {


for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


if (Phi->getOperand(i+1).getMBB() != Latch) {

if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) {


unsigned PhiOpReg = Phi->getOperand(i).getReg();

unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ;


MachineInstr *DI = MRI->getVRegDef(PhiOpReg);

MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ;


if (DI->getDesc().getOpcode() == zmtarzm::ADDI) {

if ( DI -> getDesc ( ) . getOpcode ( ) == zmtarzm :: ADDI ) {


unsigned IndReg = DI->getOperand(1).getReg();

unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ;


MachineOperand &Opnd2 = DI->getOperand(2);

MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ;


if ( MRI -> getVRegDef ( IndReg ) == Phi ) {


if ( checkForImmediate ( Opnd2 , V ) ) {


unsigned UpdReg = DI->getOperand(0).getReg();

unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ;


IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ;


SmallVector < MachineOperand , 2 > Cond ;


MachineBasicBlock *TB = nullptr, *FB = nullptr;

MachineBasicBlock * TB = nullptr , * FB = nullptr ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


unsigned PredR , PredPos , PredRegFlags ;


if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) {


MachineInstr *PredI = MRI->getVRegDef(PredR);

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);

bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


InductionMap::iterator IndMapEnd = IndMap.end();

InductionMap :: iterator IndMapEnd = IndMap . end ( ) ;


InductionMap :: iterator F = IndMapEnd ;


InductionMap::iterator F1 = IndMap.find(CmpReg1);

InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ;


InductionMap::iterator F2 = IndMap.find(CmpReg2);

InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ;


IVOp = MRI -> getVRegDef ( F -> first ) ;


zmtarzmFrepLoops() : MachineFunctionPass(ID) {

zmtarzmFrepLoops ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmFrepLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


explicit FrepLoop ( MachineLoop * ML ) {


void getAnalysisUsage(AnalysisUsage &AU) const override {

void getAnalysisUsage ( AnalysisUsage & AU ) const override {


AU . addRequired < MachinePostDominatorTree > ( ) ;


AU . addRequired < MachineDominatorTree > ( ) ;


AU . addRequired < MachineLoopInfo > ( ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


zmtarzmFrepLoops::Comparison::Kind zmtarzmFrepLoops::getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const {

zmtarzmFrepLoops :: Comparison :: Kind zmtarzmFrepLoops :: getComparisonKind ( unsigned CondOpc , MachineOperand * InitialValue , const MachineOperand * EndValue , int64_t IVBump ) const {


Comparison::Kind Cmp = (Comparison::Kind)0;

Comparison :: Kind Cmp = ( Comparison :: Kind ) 0 ;


if ( CondOpc == zmtarzm :: C2_cmpeqi ) {


if ( CondOpc == zmtarzm :: C4_cmpneq ) {


if ( CondOpc == zmtarzm :: C4_cmplte ) {


if ( CondOpc == zmtarzm :: C2_cmpgtui ) {


if ( CondOpc == zmtarzm :: C2_cmpgti ) {


if ( CondOpc == zmtarzm :: C2_cmpeqp ) {


if ( CondOpc == zmtarzm :: C4_cmpneqi ) {


if ( CondOpc == zmtarzm :: C2_cmpgtu ) {


if ( CondOpc == zmtarzm :: C2_cmpgtup ) {


if ( CondOpc == zmtarzm :: C2_cmpgtp ) {


assert(isImm() && "Wrong CountValue accessor");

assert
(
isImm
(
)
&&
"Wrong CountValue accessor"
)
;


CountValue *zmtarzmFrepLoops::getLoopTripCount(MachineLoop *L, SmallVectorImpl<MachineInstr *> &OldInsts) {

CountValue * zmtarzmFrepLoops :: getLoopTripCount ( MachineLoop * L , SmallVectorImpl < MachineInstr * > & OldInsts ) {


MachineBasicBlock *TopMBB = L->getTopBlock();

MachineBasicBlock * TopMBB = L -> getTopBlock ( ) ;


MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();

MachineBasicBlock :: pred_iterator PI = TopMBB -> pred_begin ( ) ;


assert(PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!");


MachineBasicBlock * Backedge = * PI ++ ;


MachineBasicBlock * Incoming = * PI ++ ;


MachineBasicBlock *ExitingBlock = L -> findLoopControlBlock();

MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ;


bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);

bool FoundIV = findInductionRegister ( L , IVReg , IVBump , IVOp ) ;


MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);

MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ;


MachineOperand * InitialValue = nullptr ;


MachineInstr *IV_Phi = MRI -> getVRegDef(IVReg);

MachineInstr * IV_Phi = MRI -> getVRegDef ( IVReg ) ;


MachineBasicBlock *Latch = L -> getLoopLatch();

MachineBasicBlock * Latch = L -> getLoopLatch ( ) ;


for (unsigned i = 1, n = IV_Phi -> getNumOperands(); i < n; i += 2) {

for ( unsigned i = 1 , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += 2 ) {


MachineBasicBlock *MBB = IV_Phi->getOperand(i + 1).getMBB();

MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + 1 ) . getMBB ( ) ;


InitialValue = & IV_Phi -> getOperand ( i ) ;


IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ;


SmallVector < MachineOperand , 2 > Cond ;


bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ;


MachineBasicBlock *Header = L -> getHeader();

MachineBasicBlock * Header = L -> getHeader ( ) ;


assert (TB && "Exit block without a branch?");

assert
(
TB
&&
"Exit block without a branch?"
)
;


SmallVector < MachineOperand , 2 > LCond ;


bool NotAnalyzed = TII -> analyzeBranch(*Latch, LTB, LFB, LCond, false);

bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ;


assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");

assert
(
(
!
FB
||
TB
==
Header
||
FB
==
Header
)
&&
"Branches not to header?"
)
;


bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);

bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ;


if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) {

if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) {


MachineInstr *CondI = MRI->getVRegDef(PredReg);

MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ;


unsigned CondOpc = CondI -> getOpcode ( ) ;


bool AnalyzedCmp = TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);

bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ;


const MachineOperand &Op1 = CondI->getOperand(1);

const MachineOperand & Op1 = CondI -> getOperand ( 1 ) ;


const MachineOperand &Op2 = CondI->getOperand(2);

const MachineOperand & Op2 = CondI -> getOperand ( 2 ) ;


const MachineOperand *EndValue = nullptr;

const MachineOperand * EndValue = nullptr ;


Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);

Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ;


Cmp = Comparison :: getNegatedComparison ( Cmp ) ;


Cmp = Comparison :: getSwappedComparison ( Cmp ) ;


unsigned R = InitialValue -> getReg ( ) ;


MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();

MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ;


if (!MDT->properlyDominates(DefBB, Header)) {

if ( ! MDT -> properlyDominates ( DefBB , Header ) ) {


if (!checkForImmediate(*InitialValue, V)) {

if ( ! checkForImmediate ( * InitialValue , V ) ) {


OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ;


if ( ! checkForImmediate ( * EndValue , V ) ) {


return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);

return computeCount ( L , InitialValue , EndValue , IVReg , IVBump , Cmp ) ;


static Kind getNegatedComparison(Kind Cmp) {

static Kind getNegatedComparison ( Kind Cmp ) {


return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


assert(isReg() && "Wrong CountValue accessor");

assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;


static Kind getSwappedComparison(Kind Cmp) {

static Kind getSwappedComparison ( Kind Cmp ) {


assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator");

assert
(
(
!
(
(
Cmp
&
L
)
&&
(
Cmp
&
G
)
)
)
&&
"Malformed comparison operator"
)
;


bool zmtarzmFrepLoops::isDead(const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DeadPhis) const {

bool zmtarzmFrepLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const {


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand &MO = MI->getOperand(i);

const MachineOperand & MO = MI -> getOperand ( i ) ;


if ( MO . isReg ( ) && MO . isDef ( ) ) {


if ( ! MRI -> use_nodbg_empty ( Reg ) ) {


MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);

MachineRegisterInfo :: use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ;


MachineRegisterInfo::use_nodbg_iterator End = MRI->use_nodbg_end();

MachineRegisterInfo :: use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ;


if ( I -> getParent ( ) -> isPHI ( ) ) {


MachineInstr *OnePhi = I.getOperand().getParent();

MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ;


for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {

for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) {


const MachineOperand &OPO = OnePhi->getOperand(j);

const MachineOperand & OPO = OnePhi -> getOperand ( j ) ;


MachineRegisterInfo :: use_nodbg_iterator nextJ ;


for (MachineRegisterInfo::use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J!=End; J=nextJ) {

for ( MachineRegisterInfo :: use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) {


MachineInstr * UseMI = Use . getParent ( ) ;


if ( ! I -> getParent ( ) -> isPHI ( ) ) {


bool zmtarzmFrepLoops::isInvalidLoopOperation(const MachineInstr *MI) const {

bool zmtarzmFrepLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const {


if ( MO . getReg ( ) == zmtarzm :: LC0 ) {


if ( MO . getReg ( ) == zmtarzm :: LC1 ) {


if ( MO . getReg ( ) == zmtarzm :: SA0 ) {


if ( MO . getReg ( ) == zmtarzm :: SA1 ) {


if ( MO . getReg ( ) == zmtarzm :: CTR ) {


if ( MO . getReg ( ) == zmtarzm :: CTR8 ) {


for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


const MachineOperand & MO = MI -> getOperand ( i ) ;


return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ;


void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {

void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const {


OS << "register: " << printReg(Contents.R.Reg, TRI, Contents.R.Sub) << '\n';

OS
<<
"register: "
<<
printReg
(
Contents
.
R
.
Reg
,
TRI
,
Contents
.
R
.
Sub
)
<<
'\n'
;


OS << "immediate: " << Contents.ImmVal << '\n';

OS
<<
"immediate: "
<<
Contents
.
ImmVal
<<
'\n'
;


void zmtarzmFrepLoops::removeIfDead(MachineInstr *MI) {

void zmtarzmFrepLoops :: removeIfDead ( MachineInstr * MI ) {


SmallVector<MachineInstr *, 1> DeadPhis;

SmallVector < MachineInstr * , 1 > DeadPhis ;


LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI);

LLVM_DEBUG
(
dbgs
(
)
<<
"HW looping will remove: "
<<
*
MI
)
;


MachineRegisterInfo :: use_iterator nextI ;


for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) {

for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) {


MachineInstr * UseMI = I -> getParent ( ) ;


UseMI -> getOperand ( 0 ) . setReg ( 0U ) ;


for (unsigned i = 0; i < DeadPhis.size(); ++i) {

for ( unsigned i = 0 ; i < DeadPhis . size ( ) ; ++ i ) {


for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {


const MachineOperand &MO = MI->getOperand(i);


bool zmtarzmHardwareLoops::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmHardwareLoops :: runOnMachineFunction ( MachineFunction & MF ) {


MLI = & getAnalysis < MachineLoopInfo > ( ) ;


MDT = & getAnalysis < MachineDominatorTree > ( ) ;


TII = MF . getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


Changed = Changed | convertToHardwareLoop(L, L0Used, L1Used);

Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ;


bool enableMachineScheduler() const override {

bool enableMachineScheduler ( ) const override {


const CallLowering *zmtarzmSubtarget::getCallLowering() const {

const CallLowering * zmtarzmSubtarget :: getCallLowering ( ) const {


const zmtarzmFrameLowering *getFrameLowering() const override {

const zmtarzmFrameLowering * getFrameLowering ( ) const override {


const zmtarzmInstrInfo *getInstrInfo() const override {

const zmtarzmInstrInfo * getInstrInfo ( ) const override {


InstructionSelector *zmtarzmSubtarget::getInstructionSelector() const {

InstructionSelector * zmtarzmSubtarget :: getInstructionSelector ( ) const {


const LegalizerInfo *zmtarzmSubtarget::getLegalizerInfo() const {

const LegalizerInfo * zmtarzmSubtarget :: getLegalizerInfo ( ) const {


const RegisterBankInfo *zmtarzmSubtarget::getRegBankInfo() const {

const RegisterBankInfo * zmtarzmSubtarget :: getRegBankInfo ( ) const {


const zmtarzmRegisterInfo *getRegisterInfo() const override {

const zmtarzmRegisterInfo * getRegisterInfo ( ) const override {


const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {

const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


zmtarzmABI :: ABI getTargetABI ( ) const {


const zmtarzmTargetLowering *getTargetLowering() const override {

const zmtarzmTargetLowering * getTargetLowering ( ) const override {


bool hasExtXfauxvecaltquarter ( ) const {


bool hasExtXfexpauxvecalthalf ( ) const {


bool hasExtXfexpauxvecaltquarter() const {

bool hasExtXfexpauxvecaltquarter ( ) const {


bool hasExtXfexpauxvecquarter ( ) const {


zmtarzmSubtarget &zmtarzmSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {

zmtarzmSubtarget & zmtarzmSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) {


CPUName = Is64Bit ? "generic-la64" : "generic-la32";


ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ;


TargetABI = Is64Bit ? zmtarzmABI::ABI_LP64D : zmtarzmABI::ABI_ILP32D;

TargetABI = Is64Bit ? zmtarzmABI :: ABI_LP64D : zmtarzmABI :: ABI_ILP32D ;


bool isRegisterReservedByUser(Register R) const {

bool isRegisterReservedByUser ( Register R ) const {


assert(R < zmtarzm::NUM_TARGET_REGS && "Register out of range");

assert
(
R
<
zmtarzm
::
NUM_TARGET_REGS
&&
"Register out of range"
)
;


zmtarzmSubtarget::zmtarzmSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM) : zmtarzmGenSubtargetInfo(TT, CPU, TuneCPU, FS), UserReservedRegister(zmtarzm::NUM_TARGET_REGS), FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {

zmtarzmSubtarget :: zmtarzmSubtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : zmtarzmGenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , UserReservedRegister ( zmtarzm :: NUM_TARGET_REGS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , TuneCPU , FS , ABIName ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {


CallLoweringInfo . reset ( new zmtarzmCallLowering ( * getTargetLowering ( ) ) ) ;


Legalizer . reset ( new zmtarzmLegalizerInfo ( * this ) ) ;


auto *RBI = new zmtarzmRegisterBankInfo(*getRegisterInfo());

auto * RBI = new zmtarzmRegisterBankInfo ( * getRegisterInfo ( ) ) ;


InstSelector.reset(createzmtarzmInstructionSelector(*static_cast<const zmtarzmTargetMachine*>(&TM), *this, *RBI));

InstSelector . reset ( createzmtarzmInstructionSelector ( * static_cast < const zmtarzmTargetMachine * > ( & TM ) , * this , * RBI ) ) ;


Target & llvm :: getThezmtarzm32Target ( ) {


Target & llvm :: getThezmtarzm64Target ( ) {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetInfo() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTargetInfo ( ) {


RegisterTarget<Triple::zmtarzm32> X(getThezmtarzm32Target(), "zmtarzm32", "32-bit zmtarzm", "zmtarzm");

RegisterTarget
<
Triple
::
zmtarzm32
>
X
(
getThezmtarzm32Target
(
)
,
"zmtarzm32"
,
"32-bit zmtarzm"
,
"zmtarzm"
)
;


RegisterTarget<Triple::zmtarzm64> Y(getThezmtarzm64Target(), "zmtarzm64", "64-bit zmtarzm", "zmtarzm");

RegisterTarget
<
Triple
::
zmtarzm64
>
Y
(
getThezmtarzm64Target
(
)
,
"zmtarzm64"
,
"64-bit zmtarzm"
,
"zmtarzm"
)
;


bool zmtarzmPassConfig :: addGlobalInstructionSelect ( ) {


bool zmtarzmPassConfig :: addInstSelector ( ) {


addPass ( createzmtarzmISelDag ( getzmtarzmTargetMachine ( ) ) ) ;


void zmtarzmPassConfig :: addIRPasses ( ) {


addPass ( createAtomicExpandPass ( ) ) ;


bool zmtarzmPassConfig :: addIRTranslator ( ) {


addPass ( new IRTranslator ( getOptLevel ( ) ) ) ;


bool zmtarzmPassConfig :: addLegalizeMachineIR ( ) {


void zmtarzmPassConfig :: addPreEmitPass2 ( ) {


addPass ( createzmtarzmExpandPseudoPass ( ) ) ;


addPass ( createzmtarzmExpandAtomicPseudoPass ( ) ) ;


addPass ( createBranchSelectionPass ( ) ) ;


addPass ( createzmtarzmFixupHwLoops ( ) ) ;


void zmtarzmPassConfig :: addPreEmitPass ( ) {


void zmtarzmPassConfig :: addPreRegAlloc ( ) {


if (TM->getOptLevel() != CodeGenOpt::None) {

if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) {


addPass ( createzmtarzmAdvSIMDScalar ( ) ) ;


void zmtarzmPassConfig :: addPreSched2 ( ) {


bool zmtarzmPassConfig :: addRegBankSelect ( ) {


static StringRef computeDataLayout(const Triple &TT) {

static StringRef computeDataLayout ( const Triple & TT ) {


assert
(
TT
.
isArch16Bit
(
)
&&
"COMET-II 16bit only"
)
;

assert(TT.isArch16Bit() && "COMET-II 16bit only");


if ( TT . getVendor ( ) == Triple :: bpfeb ) {


if ( TT . getVendor ( ) == Triple :: r600 ) {


TargetPassConfig *TargetMachine::createPassConfig(PassManagerBase &PM) {

TargetPassConfig * TargetMachine :: createPassConfig ( PassManagerBase & PM ) {


return new zmtarzmPassConfig(*this, PM);

return new zmtarzmPassConfig ( * this , PM ) ;


static Reloc::Model getEffectiveRelocModel(const Triple &TT, Optional<Reloc::Model> RM) {

static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) {


TargetLoweringObjectFile *getObjFileLowering() const override {

TargetLoweringObjectFile * getObjFileLowering ( ) const override {


const zmtarzmSubtarget *zmtarzmTargetMachine::getSubtargetImpl(const Function &F) const {

const zmtarzmSubtarget * zmtarzmTargetMachine :: getSubtargetImpl ( const Function & F ) const {


Attribute TuneAttr = F.getFnAttribute("tune-cpu");

Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ;


Attribute CPUAttr = F.getFnAttribute("target-cpu");

Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ;


Attribute FSAttr = F.getFnAttribute("target-features");

Attribute FSAttr = F . getFnAttribute ( "target-features" ) ;


std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;

std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ;


std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;

std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ;


std :: string Key = CPU + TuneCPU + FS ;


auto ABIName = Options.MCOptions.getABIName();

auto ABIName = Options . MCOptions . getABIName ( ) ;


if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(F.getParent()->getModuleFlag("target-abi"))) {

if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( "target-abi" ) ) ) {


auto TargetABI = zmtarzmABI::getTargetABI(ABIName);

auto TargetABI = zmtarzmABI :: getTargetABI ( ABIName ) ;


if (TargetABI != zmtarzmABI::ABI_Unknown) {

if ( TargetABI != zmtarzmABI :: ABI_Unknown ) {


if (ModuleTargetABI->getString() != ABIName) {

if ( ModuleTargetABI -> getString ( ) != ABIName ) {


ABIName = ModuleTargetABI -> getString ( ) ;


I = std::make_unique<zmtarzmSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);

I = std :: make_unique < zmtarzmSubtarget > ( TargetTriple , CPU , TuneCPU , FS , ABIName , * this ) ;


std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ;

std::string TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;


report_fatal_error("-target-abi option != target-abi module flag");


zmtarzmTargetMachine &getzmtarzmTargetMachine() const {

zmtarzmTargetMachine & getzmtarzmTargetMachine ( ) const {


return getTM < zmtarzmTargetMachine > ( ) ;


TargetTransformInfo zmtarzmTargetMachine::getTargetTransformInfo(const Function &F) {

TargetTransformInfo zmtarzmTargetMachine :: getTargetTransformInfo ( const Function & F ) {


return TargetTransformInfo ( zmtarzmTTIImpl ( this , F ) ) ;


bool zmtarzmTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {

bool zmtarzmTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const {


extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTarget() {

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializezmtarzmTarget ( ) {


RegisterTargetMachine < zmtarzmTargetMachine > X ( getThezmtarzmTarget ( ) ) ;


RegisterTargetMachine < zmtarzmTargetMachine > X ( getThezmtarzm32Target ( ) ) ;


RegisterTargetMachine < zmtarzmTargetMachine > Y ( getThezmtarzm64Target ( ) ) ;


auto *PR = PassRegistry::getPassRegistry();

auto * PR = PassRegistry :: getPassRegistry ( ) ;


initializezmtarzmPrepareModulePass ( * PR ) ;


initializezmtarzmOpLoweringLegacyPass ( * PR ) ;


initializezmtarzmTranslateMetadataPass ( * PR ) ;


initializezmtarzmDelaySlotFillerPass ( * PR ) ;


initializezmtarzmIntrRangePass ( * PR ) ;


initializezmtarzmGenericToNVVMPass ( * PR ) ;


initializezmtarzmAllocaHoistingPass ( * PR ) ;


initializezmtarzmWinEHStatePass ( * PR ) ;


initializezmtarzmFixupBWInstPass ( * PR ) ;


initializezmtarzmEvexToVexInstPass ( * PR ) ;


initializezmtarzmFixupLEAPass ( * PR ) ;


initializezmtarzmExecutionDepsFixPass ( * PR ) ;


zmtarzmPassConfig(zmtarzmTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) {

zmtarzmPassConfig ( zmtarzmTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


void zmtarzmTargetMachine::setTargetOptionsWithModuleMetadata(const Module &M LLVM_ATTRIBUTE_UNUSED) {

void zmtarzmTargetMachine :: setTargetOptionsWithModuleMetadata ( const Module & M LLVM_ATTRIBUTE_UNUSED ) {


constexpr StringLiteral DeadKeys[] = {ValVerKey};

constexpr StringLiteral DeadKeys [ ] = { ValVerKey } ;


SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ;


M . getModuleFlagsMetadata ( ModuleFlags ) ;


NamedMDNode *MDFlags = M.getModuleFlagsMetadata();

NamedMDNode * MDFlags = M . getModuleFlagsMetadata ( ) ;


StringRef Key = Flag . Key -> getString ( ) ;


M . addModuleFlag ( Flag . Behavior , Key , Flag . Val ) ;


zmtarzmTargetMachine::zmtarzmTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique<TargetObjectFile>()), Subtarget(TT, CPU, FS, *this) {

zmtarzmTargetMachine :: zmtarzmTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


void zmtarzmELFTargetObjectFile::getModuleMetadata(Module &M) {

void zmtarzmELFTargetObjectFile :: getModuleMetadata ( Module & M ) {


MCSection *zmtarzmELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const {

MCSection * zmtarzmELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const {


if ( isConstantInSmallSection ( DL , C ) ) {


return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment);

return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ;


void zmtarzmELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {

void zmtarzmELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {


TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


InitializeELF ( TM . Options . UseInitArray ) ;


SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


this->TM = &static_cast<const zmtarzmTargetMachine &>(TM);

this -> TM = & static_cast < const zmtarzmTargetMachine & > ( TM ) ;


bool zmtarzmELFTargetObjectFile::isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const {

bool zmtarzmELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const {


return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ;


bool zmtarzmTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const {

bool zmtarzmTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const {


return TM.getCodeModel() == CodeModel::Small;

return TM . getCodeModel ( ) == CodeModel :: Small ;


return isGlobalInSmallSectionImpl ( GO , TM ) ;


if ( GO -> hasAvailableExternallyLinkage ( ) ) {


return isGlobalInSmallSection(GO, TM, getKindForGlobal(GO, TM));

return isGlobalInSmallSection ( GO , TM , getKindForGlobal ( GO , TM ) ) ;


bool zmtarzmELFTargetObjectFile::isInSmallSection(uint64_t Size) const {

bool zmtarzmELFTargetObjectFile :: isInSmallSection ( uint64_t Size ) const {


return Size > 0 && Size <= SSThreshold ;


MCSection *zmtarzmELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


if ( isGlobalInSmallSection ( GO , TM ) ) {


return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM);

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


void zmtarzmTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {

void zmtarzmTargetStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) {


void zmtarzmTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {

void zmtarzmTargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) {


OS << # << Attribute << # << Twine(Value) << #;

OS << # << Attribute << # << Twine ( Value ) << # ;

OS
<<
"\t.csky_attribute\t"
<<
Attribute
<<
", "
<<
Twine
(
Value
)
<<
"\n"
;

"\t.csky_attribute\t" zmsplit ", " zmsplit "\n"

OS << "\t.csky_attribute\t" << Attribute << ", " << Twine(Value) << "\n";


OS
<<
"\t.hsa_code_object_version "
<<
Attribute
<<
","
<<
Twine
(
Value
)
<<
'\n'
;

"\t.hsa_code_object_version " zmsplit "," zmsplit '\n'

OS << "\t.hsa_code_object_version " << Attribute << "," << Twine(Value) << '\n';


void zmtarzmTargetStreamer :: emitDirectiveOptionNoPIC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionNoRelax ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoRelax ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionNoRVC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionNoRVC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPIC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPIC ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPop ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPop ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionPush ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionPush ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionRelax ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionRelax ( ) {


void zmtarzmTargetStreamer :: emitDirectiveOptionRVC ( ) {


void zmtarzmTargetAsmStreamer :: emitDirectiveOptionRVC ( ) {


void zmtarzmTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {

void zmtarzmTargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


void zmtarzmTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {

void zmtarzmTargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


void zmtarzmTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {

void zmtarzmTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) {


ArchID = zmtarzm :: parseCPUArch ( CPU ) ;


if (ArchID == zmtarzm::ArchKind::CK804) {

if ( ArchID == zmtarzm :: ArchKind :: CK804 ) {


CPU_ARCH = zmtarzm :: getArchName ( ArchID ) ;


if (ArchID == zmtarzm::ArchKind::INVALID) {

if ( ArchID == zmtarzm :: ArchKind :: INVALID ) {


emitTextAttribute ( zmtarzmAttrs :: zmtarzm_ARCH_NAME | zm - split | CPU_ARCH , zmtarzmAttrs :: zmtarzm_ARCH_NAME | zm - split | CPU_ARCH ) ;

emitTextAttribute ( zmtarzmAttrs :: zmtarzm_ARCH_NAME , CPU_ARCH ) ;


emitTextAttribute ( zmtarzmAttrs :: zmtarzm_CPU_NAME | zm - split | CPU , zmtarzmAttrs :: zmtarzm_CPU_NAME | zm - split | CPU ) ;

emitTextAttribute ( zmtarzmAttrs :: zmtarzm_CPU_NAME , CPU ) ;


if ( STI . hasFeature ( zmtarzm :: HasE1 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_E1;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_E1 ;


if ( STI . hasFeature ( zmtarzm :: HasE2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_1E2 ;


if ( STI . hasFeature ( zmtarzm :: Has2E3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_2E3;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_2E3 ;


if ( STI . hasFeature ( zmtarzm :: HasMP ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_MP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_MP ;


if ( STI . hasFeature ( zmtarzm :: Has3E3r1 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R1;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R1 ;


if ( STI . hasFeature ( zmtarzm :: Has3r1E3r2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R2;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R2 ;


if ( STI . hasFeature ( zmtarzm :: Has3r2E3r3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E3R3;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E3R3 ;


if ( STI . hasFeature ( zmtarzm :: Has3E7 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_3E7;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_3E7 ;


if ( STI . hasFeature ( zmtarzm :: HasMP1E2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_MP_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_MP_1E2 ;


if ( STI . hasFeature ( zmtarzm :: Has7E10 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_7E10;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_7E10 ;


if ( STI . hasFeature ( zmtarzm :: Has10E60 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_10E60;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_10E60 ;


if ( STI . hasFeature ( zmtarzm :: FeatureTrust ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_TRUST;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_TRUST ;


if ( STI . hasFeature ( zmtarzm :: FeatureJAVA ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_JAVA;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_JAVA ;


if ( STI . hasFeature ( zmtarzm :: FeatureCache ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_CACHE;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_CACHE ;


if ( STI . hasFeature ( zmtarzm :: FeatureNVIC ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_NVIC;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_NVIC ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSP ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP ;


if ( STI . hasFeature ( zmtarzm :: HasDSP1E2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_1E2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_1E2 ;


if ( STI . hasFeature ( zmtarzm :: HasDSPE60 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::V2_ISA_DSPE60;

ISAFlag = ISAFlag | zmtarzmAttrs :: V2_ISA_DSPE60 ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSPV2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_ENHANCE;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_ENHANCE ;


if ( STI . hasFeature ( zmtarzm :: FeatureDSP_Silan ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_DSP_SILAN;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_DSP_SILAN ;


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV1_128 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP ;


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV2 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2 ;


if ( STI . hasFeature ( zmtarzm :: HasVDSP2E3 ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2E3;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2E3 ;


if ( STI . hasFeature ( zmtarzm :: HasVDSP2E60F ) ) {


ISAFlag = ISAFlag | zmtarzmAttrs::ISA_VDSP_2E60F;

ISAFlag = ISAFlag | zmtarzmAttrs :: ISA_VDSP_2E60F ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_FLAGS | zm - split | ISAFlag , zmtarzmAttrs :: zmtarzm_ISA_FLAGS | zm - split | ISAFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_FLAGS , ISAFlag ) ;

zmtarzmAttrs :: zmtarzm_ISA_FLAGS ISAFlag


if ( STI . hasFeature ( zmtarzm :: HasFLOATE1 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_E1;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_E1 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT1E2 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_1E2;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_1E2 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT1E3 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_1E3;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_1E3 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT3E4 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_3E4;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_3E4 ;


if ( STI . hasFeature ( zmtarzm :: HasFLOAT7E60 ) ) {


ISAExtFlag = ISAExtFlag | zmtarzmAttrs::ISA_FLOAT_7E60;

ISAExtFlag = ISAExtFlag | zmtarzmAttrs :: ISA_FLOAT_7E60 ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS | zm - split | ISAExtFlag , zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS | zm - split | ISAExtFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS , ISAExtFlag ) ;

zmtarzmAttrs :: zmtarzm_ISA_EXT_FLAGS ISAExtFlag


if ( STI . hasFeature ( zmtarzm :: FeatureDSP ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_EXTENSION , zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_EXTENSION ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION , zmtarzmAttrs :: DSP_VERSION_EXTENSION ) ;

zmtarzmAttrs :: zmtarzm_DSP_VERSION zmtarzmAttrs :: DSP_VERSION_EXTENSION


if ( STI . hasFeature ( zmtarzm :: FeatureDSPV2 ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_2 , zmtarzmAttrs :: zmtarzm_DSP_VERSION | zm - split | zmtarzmAttrs :: DSP_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_DSP_VERSION , zmtarzmAttrs :: DSP_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_DSP_VERSION zmtarzmAttrs :: DSP_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureVDSPV2 ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_VDSP_VERSION | zm - split | zmtarzmAttrs :: VDSP_VERSION_2 , zmtarzmAttrs :: zmtarzm_VDSP_VERSION | zm - split | zmtarzmAttrs :: VDSP_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_VDSP_VERSION , zmtarzmAttrs :: VDSP_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_VDSP_VERSION zmtarzmAttrs :: VDSP_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV2_SF ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_2 , zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_2 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION , zmtarzmAttrs :: FPU_VERSION_2 ) ;

zmtarzmAttrs :: zmtarzm_FPU_VERSION zmtarzmAttrs :: FPU_VERSION_2


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV2_DF ) ) {


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_HF ) ) {


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_3 , zmtarzmAttrs :: zmtarzm_FPU_VERSION | zm - split | zmtarzmAttrs :: FPU_VERSION_3 ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_VERSION , zmtarzmAttrs :: FPU_VERSION_3 ) ;

zmtarzmAttrs :: zmtarzm_FPU_VERSION zmtarzmAttrs :: FPU_VERSION_3


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_SF ) ) {


if ( STI . hasFeature ( zmtarzm :: FeatureFPUV3_DF ) ) {


hasAnyFloatExt = STI.hasFeature(zmtarzm::FeatureFPUV2_SF) || STI.hasFeature(zmtarzm::FeatureFPUV2_DF) ||  STI.hasFeature(zmtarzm::FeatureFPUV3_HF) || STI.hasFeature(zmtarzm::FeatureFPUV3_SF) || STI.hasFeature(zmtarzm::FeatureFPUV3_DF);

hasAnyFloatExt = STI . hasFeature ( zmtarzm :: FeatureFPUV2_SF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV2_DF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_HF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_SF ) || STI . hasFeature ( zmtarzm :: FeatureFPUV3_DF ) ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_ABI | zm - split | zmtarzmAttrs :: FPU_ABI_SOFTFP , zmtarzmAttrs :: zmtarzm_FPU_ABI | zm - split | zmtarzmAttrs :: FPU_ABI_SOFTFP ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_ABI , zmtarzmAttrs :: FPU_ABI_SOFTFP ) ;

zmtarzmAttrs :: zmtarzm_FPU_ABI zmtarzmAttrs :: FPU_ABI_SOFTFP


if ( ! STI . hasFeature ( zmtarzm :: ModeHardFloat ) ) {


if ( ! STI . hasFeature ( zmtarzm :: ModeHardFloatABI ) ) {


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_HALF;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_HALF ;


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_SINGLE;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_SINGLE ;


HardFPFlag = HardFPFlag |  zmtarzmAttrs::FPU_HARDFP_DOUBLE;

HardFPFlag = HardFPFlag | zmtarzmAttrs :: FPU_HARDFP_DOUBLE ;


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_DENORMAL | zm - split | zmtarzmAttrs :: NEEDED , zmtarzmAttrs :: zmtarzm_FPU_DENORMAL | zm - split | zmtarzmAttrs :: NEEDED ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_DENORMAL , zmtarzmAttrs :: NEEDED ) ;

zmtarzmAttrs :: zmtarzm_FPU_DENORMAL zmtarzmAttrs :: NEEDED


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION | zm - split | zmtarzmAttrs :: NEEDED , zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION | zm - split | zmtarzmAttrs :: NEEDED ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION , zmtarzmAttrs :: NEEDED ) ;

zmtarzmAttrs :: zmtarzm_FPU_EXCEPTION zmtarzmAttrs :: NEEDED


emitTextAttribute
(
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
|
zm
split
|
"IEEE 754"
,
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
|
zm
split
|
"IEEE 754"
)
;

emitTextAttribute
(
zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
,
"IEEE 754"
)
;

zmtarzmAttrs::zmtarzm_FPU_NUMBER_MODULE zmsplit "IEEE 754"

zmtarzmAttrs
::
zmtarzm_FPU_NUMBER_MODULE
"IEEE 754"


emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_HARDFP | zm - split | HardFPFlag , zmtarzmAttrs :: zmtarzm_FPU_HARDFP | zm - split | HardFPFlag ) ;

emitAttribute ( zmtarzmAttrs :: zmtarzm_FPU_HARDFP , HardFPFlag ) ;

zmtarzmAttrs :: zmtarzm_FPU_HARDFP HardFPFlag


void zmtarzmTargetStreamer::emitTextAttribute(unsigned Attribute, StringRef String) {

void zmtarzmTargetStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


void zmtarzmTargetAsmStreamer::emitTextAttribute(unsigned Attribute, StringRef String) {

void zmtarzmTargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


OS << # << Attribute << # << String << #;

OS << # << Attribute << # << String << # ;

OS
<<
"\t.csky_attribute\t"
<<
Attribute
<<
", \""
<<
String
<<
"\"\n"
;

"\t.csky_attribute\t" zmsplit ", \"" zmsplit "\"\n"

OS << "\t.csky_attribute\t" << Attribute << ", \"" << String << "\"\n";


OS
<<
"\t.import_module\t"
<<
Attribute
<<
", "
<<
String
<<
'\n'
;

"\t.import_module\t" zmsplit ", " zmsplit '\n'

OS << "\t.import_module\t" << Attribute << ", " << String << '\n';


void zmtarzmTargetStreamer :: finishAttributeSection ( ) {


void zmtarzmTargetAsmStreamer :: finishAttributeSection ( ) {


void zmtarzmTargetStreamer :: finish ( ) {


zmtarzmTargetAsmStreamer::zmtarzmTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : zmtarzmTargetStreamer(S), OS(OS) {

zmtarzmTargetAsmStreamer :: zmtarzmTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : zmtarzmTargetStreamer ( S ) , OS ( OS ) {


zmtarzmTargetStreamer::zmtarzmTargetStreamer(MCStreamer &S)  : MCTargetStreamer(S) {

zmtarzmTargetStreamer :: zmtarzmTargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


int zmtarzmTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) {

int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers");


unsigned Ty->getPrimitiveSizeInBits() = Ty->getPrimitiveSizeInBits();

unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if (Ty->getPrimitiveSizeInBits() == 0) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() > 64) {

if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {

if (Opcode == Instruction::GetElementPtr) {


if (Ty->getPrimitiveSizeInBits() == 8) {

if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


int NumConstants = divideCeil(Ty->getPrimitiveSizeInBits(), 64);

int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if (getIntImmCost(Imm, Ty, CostKind) <= NumConstants * TTI::TCC_Basic) {

if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost(Imm, Ty, CostKind);

return getIntImmCost ( Imm , Ty , CostKind ) ;


if (Imm.getZExtValue() == 0x100000000ULL) {

if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if (Ty->getPrimitiveSizeInBits() <= 32) {

if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff) {

if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( Opcode == Instruction :: Select ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


int zmtarzmTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) {


"getIntImmCost can only estimate cost of materialising integers"


unsigned Ty -> getPrimitiveSizeInBits ( ) = Ty -> getPrimitiveSizeInBits ( ) ;


if ( Ty -> getPrimitiveSizeInBits ( ) == 0 ) {


if ( Ty -> getPrimitiveSizeInBits ( ) > 64 ) {


if ( Opcode == Instruction :: GetElementPtr ) {


if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


return getIntImmCost ( Imm , Ty , CostKind ) ;


if ( Imm . getZExtValue ( ) == 0x100000000ULL ) {


if ( Imm . getZExtValue ( ) == 0xffffffff ) {


int NumConstants = divideCeil ( Ty -> getPrimitiveSizeInBits ( ) , 64 ) ;


if ( getIntImmCost ( Imm , Ty , CostKind ) <= NumConstants * TTI :: TCC_Basic ) {


return static_cast < int > ( TTI :: TCC_Free ) ;


if ( isUInt < 32 > ( - Imm . getZExtValue ( ) ) ) {


if ( Imm . getZExtValue ( ) == 0x80000000 ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) {


if ( isUInt < 32 > ( ~ Imm . getSExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0xffffffff ) {


if ( Opcode == Instruction :: IntToPtr ) {


if ( Opcode == Instruction :: PtrToInt ) {


if ( Opcode == Instruction :: BitCast ) {


if ( Opcode == Instruction :: Select ) {


int zmtarzmTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


return zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);

return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if (IID == Intrinsic::sadd_with_overflow) {

if ( IID == Intrinsic :: sadd_with_overflow ) {


Cost = zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;

Cost = zmtarzmTTIImpl::getIntImmCost(Imm, Ty, CostKind);


return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ;

return (Cost <= NumConstants * TTI::TCC_Basic) ? static_cast<int>(TTI::TCC_Free) : Cost;


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < # > ( - Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::uadd_with_overflow) {

if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: ssub_with_overflow ) {

if (IID == Intrinsic::ssub_with_overflow) {


if ( IID == Intrinsic :: usub_with_overflow ) {

if (IID == Intrinsic::usub_with_overflow) {


if ( IID == Intrinsic :: smul_with_overflow ) {

if (IID == Intrinsic::smul_with_overflow) {


if ( isUInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: umul_with_overflow ) {

if (IID == Intrinsic::umul_with_overflow) {


if (IID == Intrinsic::experimental_stackmap) {

if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


if (IID == Intrinsic::experimental_patchpoint_void) {

if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if (IID == Intrinsic::experimental_patchpoint_i64) {

if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


if ( IID == Intrinsic :: sadd_with_overflow ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < 32 > ( - Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: ssub_with_overflow ) {


if ( IID == Intrinsic :: usub_with_overflow ) {


if ( IID == Intrinsic :: smul_with_overflow ) {


if ( isUInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: umul_with_overflow ) {


if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


int zmtarzmTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


if ( IID >= Intrinsic :: aarch64_addg ) {


if ( IID <= Intrinsic :: aarch64_udiv ) {


if ( IID == Intrinsic :: sadd_with_overflow ) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( isUInt < # > ( - Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: uadd_with_overflow ) {


if ( IID == Intrinsic :: ssub_with_overflow ) {


if ( IID == Intrinsic :: usub_with_overflow ) {


if ( IID == Intrinsic :: smul_with_overflow ) {


if ( isUInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: umul_with_overflow ) {


return zmtarzmTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ;


if ( IID == Intrinsic :: experimental_stackmap ) {


if ( isInt < 64 > ( Imm . getSExtValue ( ) ) ) {


if ( IID == Intrinsic :: experimental_patchpoint_void ) {


if ( IID == Intrinsic :: experimental_patchpoint_i64 ) {


int zmtarzmTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if (zmtarzm_AM::isLogicalImmediate(Val, 64)) {

if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty->getPrimitiveSizeInBits();

unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if (zmtarzm_AM::getSOImmVal(ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if (zmtarzm_AM::getSOImmVal(~ZImmVal) != -1) {

if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ((Imm.getZExtValue() & 0xFFFF) == 0) {

if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < # > ( Imm . getZExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {

if ((Imm.getZExtValue() & 0xffffffff) == 0) {


if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) {


int zmtarzmTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {


if ( zmtarzm_AM :: isLogicalImmediate ( Val , 64 ) ) {


SmallVector < zmtarzm_IMM :: ImmInsnModel , 4 > Insn ;


zmtarzm_IMM :: expandMOVImm ( Val , 64 , Insn ) ;


return BaseT :: getIntImmCost ( Imm , Ty ) ;


unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ;


int64_t SImmVal = Imm . getSExtValue ( ) ;


uint64_t ZImmVal = Imm . getZExtValue ( ) ;


if ( zmtarzm_AM :: getSOImmVal ( ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) {


if ( zmtarzm_AM :: isThumbImmShiftedVal ( ZImmVal ) ) {


if ( isInt < # > ( Imm . getSExtValue ( ) ) ) {


if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) {


if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) {


if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) {


const zmtarzmSubtarget * getST ( ) const {


const zmtarzmTargetLowering *getTLI() const {

const zmtarzmTargetLowering * getTLI ( ) const {


bool zmtarzmTTIImpl::isLoweredToCall(const Function *F) {

bool zmtarzmTTIImpl :: isLoweredToCall ( const Function * F ) {


if ( F -> getName ( ) . startswith ( "llvm.zmtarzm_lower" ) ) {


bool zmtarzmTTIImpl::shouldFavorPostInc() const {

bool zmtarzmTTIImpl :: shouldFavorPostInc ( ) const {


explicit zmtarzmTTIImpl(const zmtarzmTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {

explicit zmtarzmTTIImpl ( const zmtarzmTargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


bool zmtarzmAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) {

bool zmtarzmAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) {


if (Fixup.getTargetKind() >= FirstLiteralRelocationKind) {

if ( Fixup . getTargetKind ( ) >= FirstLiteralRelocationKind ) {


if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) {


bool zmtarzmCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {

bool zmtarzmCleanupVSETVLI :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) {


const Subtarget &STI = MBB.getParent()->getSubtarget<Subtarget>();

const Subtarget & STI = MBB . getParent ( ) -> getSubtarget < Subtarget > ( ) ;


const InstrInfo *TII = STI.getInstrInfo();

const InstrInfo * TII = STI . getInstrInfo ( ) ;


InstrInfo = MBB . getParent ( ) -> getSubtarget < zmtarzmSubtarget > ( ) . getInstrInfo ( ) ;


for (MachineBasicBlock::iterator I = MBB.instr_begin(); I != MBB.instr_end(); ++I) {

for ( MachineBasicBlock :: iterator I = MBB . instr_begin ( ) ; I != MBB . instr_end ( ) ; ++ I ) {


BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(zmtarzm::NOP));

BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( zmtarzm :: NOP ) ) ;


MIBundleBuilder(MBB, I, std::next(I, 2));

MIBundleBuilder ( MBB , I , std :: next ( I , 2 ) ) ;


if (insertStall(MBB, I, TII, MI->getOpcode())) {

if ( insertStall ( MBB , I , TII , MI -> getOpcode ( ) ) ) {


if (InstrInfo->isStoreToStackSlot(Inst, FI)) {

if ( InstrInfo -> isStoreToStackSlot ( Inst , FI ) ) {


bool zmtarzmFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {

bool zmtarzmFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const {


MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);

MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ;


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const Subtarget &Subtarget = MF->getSubtarget<Subtarget>();

const Subtarget & Subtarget = MF -> getSubtarget < Subtarget > ( ) ;


const RegisterInfo *RegInfo = Subtarget.getRegisterInfo();

const RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


if ( ! RegInfo -> hasStackRealignment ( * MF ) ) {


return findScratchNonCalleeSaveRegister(TmpMBB) != zmtarzm::NoRegister;

return findScratchNonCalleeSaveRegister ( TmpMBB ) != zmtarzm :: NoRegister ;


if ( ! MBB . isLiveIn ( zmtarzm :: EFLAGS ) ) {


const MachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const MachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;