bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


MachineBasicBlock *EntryBlock = MF->begin();

MachineBasicBlock * EntryBlock = MF -> begin ( ) ;


for ( const CalleeSavedInfo & CS : CSI ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


zmtarzmFTAOElim() : MachineFunctionPass(ID) {

zmtarzmFTAOElim ( ) : MachineFunctionPass ( ID ) {


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm FRAME_TO_ARGS_OFFSET Elimination";


bool zmtarzmFTAOElim::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


bool zmtarzmInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {

bool zmtarzmInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const {


MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();

MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ;


if ( ! isUnpredicatedTerminator ( * I ) ) {


MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();

MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ;


for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); J++) {

for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) {


if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) {


FirstUncondOrIndirectBr = J . getReverse ( ) ;


if ( J -> getDesc ( ) . isIndirectBranch ( ) ) {


if (FirstUncondOrIndirectBr != MBB.end()) {

if ( FirstUncondOrIndirectBr != MBB . end ( ) ) {


for(; std::next(FirstUncondOrIndirectBr) != MBB.end();) {

for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) {


std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ;


if ( I -> getDesc ( ) . isIndirectBranch ( ) ) {


if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


if ( I -> getDesc ( ) . isConditionalBranch ( ) ) {


if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) {


parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ;


void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {

void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {


if ( # . contains ( DstReg , SrcReg ) ) {

if ( zmtarzm :: GPRRegClass . contains ( DstReg , SrcReg ) ) {

if (zmtarzm::GPRRegClass.contains(DstReg, SrcReg)) {


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);

BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( # . contains ( DestReg , SrcReg ) ) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));

BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;

BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


if ( zmtarzm :: GPRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GPRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: G8RCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::G8RCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: OR8 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::OR8), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: F4RCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::F4RCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: FMR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::FMR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: CRRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::CRRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: MCRF ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::MCRF), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: VRRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::VRRCRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: VOR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::VOR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


if ( zmtarzm :: CRBITRCRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::CRBITRCRegClass.contains(DestReg, SrcReg)) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , MBBI , DL , get ( zmtarzm :: CROR ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(zmtarzm::CROR), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI(MBB, I, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


void zmtarzmInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const {

void zmtarzmInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const {


if ( # . contains ( DstReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( zmtarzm :: R0 ) ;


if ( # . contains ( DestReg , SrcReg ) ) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: IntRegsRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::IntRegsRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: ORrr ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::ORrr), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: FPRegsRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::FPRegsRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: FMOVS ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::FMOVS), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: DFPRegsRegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::DFPRegsRegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , MBBI , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI ( MBB , I , DL , get ( Subtarget . isV9 ( ) ? zmtarzm :: FMOVD : zmtarzm :: FpMOVD ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(Subtarget.isV9() ? zmtarzm::FMOVD : zmtarzm::FpMOVD), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI(MBB, MBBI, DL, get(#), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(zmtarzm::R0);


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: G0 ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(#), DestReg).addReg(zmtarzm::G0).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: OR ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::OR), DestReg).addReg(zmtarzm::ZERO).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR16RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR16RegClass.contains(DestReg, SrcReg)) {


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV16rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV16rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


if ( zmtarzm :: GR8RegClass . contains ( DestReg , SrcReg ) ) {

if (zmtarzm::GR8RegClass.contains(DestReg, SrcReg)) {


BuildMI(MBB, MBBI, DL, get(#), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( zmtarzm :: MOV8rr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

BuildMI(MBB, I, DL, get(zmtarzm::MOV8rr), DestReg).addReg(SrcReg, getKillRegState(KillSrc));


BuildMI ( MBB , I , DL , get ( # ) , DestReg ) . addReg ( zmtarzm :: ZERO ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;


MachineInstr* zmtarzmInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const {

MachineInstr * zmtarzmInstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const {


MachineInstrBuilder MIB = BuildMI(MF, DL, get(zmtarzm::DBG_VALUE)).addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);

MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( zmtarzm :: DBG_VALUE ) ) . addFrameIndex ( FrameIx ) . addImm ( 0 ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


static inline unsigned GetCondBranchFromCond(zmtarzm::CondCode BrOpc) {

static inline unsigned GetCondBranchFromCond ( zmtarzm :: CondCode BrOpc ) {


llvm_unreachable
(
"Illegal condition code!"
)
;


static zmtarzm::CondCode GetCondFromBranchOpc(unsigned CC) {

static zmtarzm :: CondCode GetCondFromBranchOpc ( unsigned CC ) {


unsigned zmtarzmInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {

unsigned zmtarzmInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const {


const MachineBasicBlock &MBB = *MI->getParent();

const MachineBasicBlock & MBB = * MI -> getParent ( ) ;


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();

const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


if (MI->getOpcode() == zmtarzm::INLINEASM) {

if ( MI -> getOpcode ( ) == zmtarzm :: INLINEASM ) {


return getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Desc . getOpcode ( ) == TargetOpcode :: DBG_VALUE ) {

if (Desc.getOpcode() == TargetOpcode::DBG_VALUE) {


if ( Desc . getOpcode ( ) == TargetOpcode :: EH_LABEL ) {

if (Desc.getOpcode() == TargetOpcode::EH_LABEL) {


if ( Desc . getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) {

if (Desc.getOpcode() == TargetOpcode::IMPLICIT_DEF) {


if ( Desc . getOpcode ( ) == TargetOpcode :: KILL ) {

if (Desc.getOpcode() == TargetOpcode::KILL) {


if ( Desc . getOpcode ( ) == TargetOpcode :: INLINEASM ) {

if (Desc.getOpcode() == TargetOpcode::INLINEASM) {


const MachineFunction *MF = MI->getParent()->getParent();

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const zmtarzmTargetMachine &TM = static_cast<const zmtarzmTargetMachine&>(MF->getTarget());

const zmtarzmTargetMachine & TM = static_cast < const zmtarzmTargetMachine & > ( MF -> getTarget ( ) ) ;


const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();

const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;


return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


const char *AsmStr = MI->getOperand(0).getSymbolName();

const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");


unsigned zmtarzmInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const {


const MachineBasicBlock & MBB = * MI -> getParent ( ) ;


const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


if ( MI -> getOpcode ( ) == zmtarzm :: INLINEASM ) {


return getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Desc . getOpcode ( ) == TargetOpcode :: DBG_VALUE ) {


if ( Desc . getOpcode ( ) == TargetOpcode :: EH_LABEL ) {


if ( Desc . getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) {


if ( Desc . getOpcode ( ) == TargetOpcode :: KILL ) {


if ( Desc . getOpcode ( ) == TargetOpcode :: BLA8_NOP_ELF ) {

if (Desc.getOpcode() == TargetOpcode::BLA8_NOP_ELF) {


if ( Desc . getOpcode ( ) == TargetOpcode :: BL8_NOP_ELF ) {

if (Desc.getOpcode() == TargetOpcode::BL8_NOP_ELF) {


if ( Desc . getOpcode ( ) == TargetOpcode :: INLINEASM ) {


const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const zmtarzmTargetMachine & TM = static_cast < const zmtarzmTargetMachine & > ( MF -> getTarget ( ) ) ;


const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;


return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


"GetInstSizeInBytes()- Unable to determin insn size"


static inline zmtarzm::CondCode GetOppositeBranchCondition(zmtarzm::CondCode CC) {

static inline zmtarzm :: CondCode GetOppositeBranchCondition ( zmtarzm :: CondCode CC ) {


llvm_unreachable
(
"Illegal condition code!"
)
;


virtual const TargetRegisterInfo &getRegisterInfo() const {

virtual const TargetRegisterInfo & getRegisterInfo ( ) const {


unsigned zmtarzmInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {

unsigned zmtarzmInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const {


assert(TBB && "insertBranch must not be told to insert a fallthrough");


assert((Cond.size() == 3 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(TBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( TBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(TBB);


*BytesAdded = *BytesAdded + getInstSizeInBytes(MI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ;


unsigned Opc = Cond [ 0 ] . getImm ( ) ;


MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);

MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ;


*BytesAdded = *BytesAdded + getInstSizeInBytes(CondMI);

* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ;


MachineInstr &MI = *BuildMI(&MBB, DL, get(#)).addMBB(FBB);

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( # ) ) . addMBB ( FBB ) ;

MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: JS ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::JS)).addMBB(FBB);


assert((Cond.size() == 2 || Cond.size() == 0) && "zmtarzm branch conditions have two components!");


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( TBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(TBB);


MachineInstr & MI = * BuildMI ( & MBB , DL , get ( zmtarzm :: BR32 ) ) . addMBB ( FBB ) ;

MachineInstr &MI = *BuildMI(&MBB, DL, get(zmtarzm::BR32)).addMBB(FBB);


zmtarzmInstrInfo::zmtarzmInstrInfo() : zmtarzmGenInstrInfo(zmtarzm::ADJCALLSTACKDOWN, zmtarzm::ADJCALLSTACKUP), RI(*this) {

zmtarzmInstrInfo :: zmtarzmInstrInfo ( ) : zmtarzmGenInstrInfo ( zmtarzm :: ADJCALLSTACKDOWN , zmtarzm :: ADJCALLSTACKUP ) , RI ( * this ) {


static inline bool IsBRF(unsigned BrOpc) {

static inline bool IsBRF ( unsigned BrOpc ) {


if ( BrOpc == zmtarzm :: t2STMDB_UPD ) {


if ( BrOpc == zmtarzm :: VSTMDDB_UPD ) {


static inline bool IsBRT(unsigned BrOpc) {

static inline bool IsBRT ( unsigned BrOpc ) {


static inline bool IsBRU(unsigned BrOpc) {

static inline bool IsBRU ( unsigned BrOpc ) {


static inline bool IsBR_JT(unsigned BrOpc) {

static inline bool IsBR_JT ( unsigned BrOpc ) {


static inline bool IsCondBranch(unsigned BrOpc) {

static inline bool IsCondBranch ( unsigned BrOpc ) {


if ( BrOpc == zmtarzm :: BRANCH_COND_i32 ) {

if (BrOpc == zmtarzm::BRANCH_COND_i32) {


if ( BrOpc == zmtarzm :: BRANCH_COND_f32 ) {

if (BrOpc == zmtarzm::BRANCH_COND_f32) {


unsigned zmtarzmInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) && (isZeroImm(MI->getOperand(2)))) {

if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) {


FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ;


return MI -> getOperand ( 0 ) . getReg ( ) ;


unsigned zmtarzmInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {

unsigned zmtarzmInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


static bool isZeroImm(const MachineOperand &Op) {

static bool isZeroImm ( const MachineOperand & Op ) {


void zmtarzmInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


BuildMI(MBB, MI, DL, get(#), DestReg).addFrameIndex(FrameIndex).addImm(0);

BuildMI ( MBB , MI , DL , get ( # ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI ( MBB , MI , DL , get ( zmtarzm :: POP ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI(MBB, MI, DL, get(zmtarzm::POP), DestReg).addFrameIndex(FrameIndex).addImm(0);


BuildMI ( MBB , MI , DL , get ( zmtarzm :: ADD ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI(MBB, MI, DL, get(zmtarzm::ADD), DestReg).addFrameIndex(FrameIndex).addImm(0);


BuildMI ( MBB , MI , DL , get ( zmtarzm :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ;

BuildMI(MBB, MI, DL, get(zmtarzm::LDR), DestReg).addFrameIndex(FrameIndex).addImm(0);


unsigned zmtarzmInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {

unsigned zmtarzmInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const {


MachineBasicBlock::iterator I = MBB.end();

MachineBasicBlock :: iterator I = MBB . end ( ) ;


if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) {

if ( ! IsBRU ( I -> getOpcode ( ) ) && ! IsCondBranch ( I -> getOpcode ( ) ) ) {


if ( ! IsCondBranch ( I -> getOpcode ( ) ) ) {


bool zmtarzmInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {

bool zmtarzmInstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {


assert((Cond.size() == #) && "Invalid zmtarzm branch condition!");

assert
(
(
Cond
.
size
(
)
==
#
)
&&
"Invalid zmtarzm branch condition!"
)
;

assert
(
(
Cond
.
size
(
)
==
1
)
&&
"Invalid zmtarzm branch condition!"
)
;

assert((Cond.size() == 1) && "Invalid zmtarzm branch condition!");


Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( ( zmtarzm :: CondCode ) Cond [ 0 ] . getImm ( ) ) ) ;


void zmtarzmInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {

void zmtarzmInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();

MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ;


MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex), MachineMemOperand::MOStore, MFI->getObjectSize(FrameIndex), MFI->getObjectAlignment(FrameIndex));

MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI -> getObjectSize ( FrameIndex ) , MFI -> getObjectAlignment ( FrameIndex ) ) ;


BuildMI(MBB, I, DL, get(#)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0);

BuildMI ( MBB , I , DL , get ( # ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ;

BuildMI ( MBB , I , DL , get ( zmtarzm :: STW ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(zmtarzm::STW)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0);


BuildMI ( MBB , I , DL , get ( zmtarzm :: KRZmr ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ;

BuildMI(MBB, I, DL, get(zmtarzm::KRZmr)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0);


FunctionPass *llvm::createzmtarzmISelDag(zmtarzmTargetMachine &TM, CodeGenOpt::Level OptLevel) {

FunctionPass * llvm :: createzmtarzmISelDag ( zmtarzmTargetMachine & TM , CodeGenOpt :: Level OptLevel ) {


return new zmtarzmDAGToDAGISel(TM, OptLevel);

return new zmtarzmDAGToDAGISel ( TM , OptLevel ) ;


zmtarzmDAGToDAGISel(zmtarzmTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(TM, OptLevel), Lowering(*TM.getTargetLowering()), Subtarget(*TM.getSubtargetImpl()) {

zmtarzmDAGToDAGISel ( zmtarzmTargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


inline SDValue getI32Imm(unsigned Imm) {

inline SDValue getI32Imm ( unsigned Imm ) {


return CurDAG -> getTargetConstant ( Imm , MVT :: i32 ) ;


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm DAG->DAG Pattern Instruction Selection";


inline bool immBitp(SDNode *inN) const {

inline bool immBitp ( SDNode * inN ) const {


const ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);

const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ;


CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


unsigned FBits = IntVal . logBase2 ( ) ;


FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32);

FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ;


if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode())) {

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


Reg = CurDAG->getRegister(zmtarzm::NoRegister, MVT::i1);

Reg = CurDAG -> getRegister ( zmtarzm :: NoRegister , MVT :: i1 ) ;


Inv = CurDAG->getTargetConstant((Imm->getConstantIntValue()->isZero())?1:0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ;


if (!(ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(N.getNode()))) {

if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) {


Inv = CurDAG->getTargetConstant(0, dl, MVT::i1);

Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ;


if(FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {


R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {


inline bool immMskBitp(SDNode *inN) const {

inline bool immMskBitp ( SDNode * inN ) const {


bool zmtarzmDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRcpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if (Addr.getOpcode() == zmtarzmISD::CPRelativeWrapper) {

if ( Addr . getOpcode ( ) == zmtarzmISD :: CPRelativeWrapper ) {


Offset = CurDAG->getTargetConstant(0, MVT::i32);

Offset = CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ;


if ( Addr . getOpcode ( ) == ISD :: ADD ) {


if ((Addr.getOperand(0).getOpcode() == zmtarzmISD::CPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == zmtarzmISD :: CPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


Base = Addr . getOperand ( 0 ) . getOperand ( 0 ) ;


Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);

Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , MVT :: i32 ) ;


bool zmtarzmDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRdpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if (Addr.getOpcode() == zmtarzmISD::DPRelativeWrapper) {

if ( Addr . getOpcode ( ) == zmtarzmISD :: DPRelativeWrapper ) {


if ((Addr.getOperand(0).getOpcode() == zmtarzmISD::DPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == zmtarzmISD :: DPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


bool zmtarzmDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset) {

bool zmtarzmDAGToDAGISel :: SelectADDRspii ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {

if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) {


Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ;


if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {

if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( 0 ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) {


bool zmtarzmDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

bool zmtarzmDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) {


if ( ConstraintID == InlineAsm :: Constraint_i ) {

if (ConstraintID == InlineAsm::Constraint_i) {


if ( ConstraintID == InlineAsm :: Constraint_m ) {

if (ConstraintID == InlineAsm::Constraint_m) {


if ( ConstraintID == InlineAsm :: Constraint_Q ) {

if (ConstraintID == InlineAsm::Constraint_Q) {


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) {


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_byte ) {

if (IntNo == Intrinsic::zmtarzm_load_byte) {


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( IntNo == Intrinsic :: zmtarzm_load_half ) {

if (IntNo == Intrinsic::zmtarzm_load_half) {


if ( IntNo == Intrinsic :: zmtarzm_load_word ) {

if (IntNo == Intrinsic::zmtarzm_load_word) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


if ( Node -> getOpcode ( ) == ISD :: FrameIndex ) {

if (Node->getOpcode() == ISD::FrameIndex) {


int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


if ( Opcode == ISD :: GLOBAL_OFFSET_TABLE ) {

if (Opcode == ISD::GLOBAL_OFFSET_TABLE) {


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


void zmtarzmDAGToDAGISel::Select(SDNode *Node) {

void zmtarzmDAGToDAGISel :: Select ( SDNode * Node ) {


unsigned Opcode = Node -> getOpcode ( ) ;


DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');

DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;


DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;


LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");

LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;


EVT NodeTy = Node -> getValueType ( 0 ) ;


const DebugLoc &DL = Node->getDebugLoc();

const DebugLoc & DL = Node -> getDebugLoc ( ) ;


errs() << "Unsupport signed division for DAG: ";

errs
(
)
<<
"Unsupport signed division for DAG: "
;


errs() << "Please convert to unsigned div/mod.\n";

errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;


MultOpc = (Opcode == ISD::MULHU ? zmtarzm::MULTu : zmtarzm::MULT);

MultOpc = ( Opcode == ISD :: MULHU ? zmtarzm :: MULTu : zmtarzm :: MULT ) ;


return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;

return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ;


unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();

unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ;


SDValue Chain = Node -> getOperand ( 0 ) ;


SDValue Skb = Node -> getOperand ( 2 ) ;


SDValue R6Reg = CurDAG->getRegister(zmtarzm::R6, MVT::i64);

SDValue R6Reg = CurDAG -> getRegister ( zmtarzm :: R6 , MVT :: i64 ) ;


Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());

Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ;


Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);

Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ;


CurDAG->SelectNodeTo(Node, Opc, VT, TFI);

CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ;


Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);

Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ;


ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ;


auto ConstNode = cast<ConstantSDNode>(Node);

auto ConstNode = cast < ConstantSDNode > ( Node ) ;


ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);

ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R0, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R0 , MVT :: i32 ) ;


return ReplaceNode ( Node , New . getNode ( ) ) ;


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),zmtarzm::ZERO, XLenVT);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: ZERO , XLenVT ) ;


ReplaceNode ( Node , New . getNode ( ) ) ;


if ( ConstNode -> isAllOnesValue ( ) ) {


SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), zmtarzm::R1, MVT::i32);

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , zmtarzm :: R1 , MVT :: i32 ) ;


int64_t Imm = ConstNode->getSExtValue();

int64_t Imm = ConstNode -> getSExtValue ( ) ;


ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));

ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ;


SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ;


CurDAG->SelectNodeTo(Node, zmtarzm::ADDri, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32));

CurDAG -> SelectNodeTo ( Node , zmtarzm :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDri, dl, MVT::i32, TFI, CurDAG->getTargetConstant(0, dl, MVT::i32)));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ;


const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);

const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ;


unsigned Size = CN->getValueSizeInBits(0);

unsigned Size = CN -> getValueSizeInBits ( 0 ) ;


int FI = cast<FrameIndexSDNode>(Node)->getIndex();

int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ;


ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->hasE2() ? zmtarzm::ADDI32 : zmtarzm::ADDI16XZ,  Dl, MVT::i32, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? zmtarzm :: ADDI32 : zmtarzm :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ;


ReplaceNode(Node, CurDAG->getMachineNode(zmtarzm::ADDI, DL, VT, TFI, Imm));

ReplaceNode ( Node , CurDAG -> getMachineNode ( zmtarzm :: ADDI , DL , VT , TFI , Imm ) ) ;


SDNode * ResNode = SelectCode ( Node ) ;


bool zmtarzmTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {

bool zmtarzmTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const {


SmallVector < CCValAssign , 16 > RVLocs ;


CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);

CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ;


if (!CCInfo.CheckReturn(Outs, RetCC_zmtarzm)) {

if ( ! CCInfo . CheckReturn ( Outs , RetCC_zmtarzm ) ) {


if (CCInfo.getNextStackOffset() != 0 && isVarArg) {

if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) {


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();

unsigned BitWidth = Known . getBitWidth ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: CARRY ) {

if (Op.getOpcode() == zmtarzmISD::CARRY) {


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BORROW ) {

if (Op.getOpcode() == zmtarzmISD::BORROW) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_I32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_I32) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: BFE_U32 ) {

if (Op.getOpcode() == zmtarzmISD::BFE_U32) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC ) {

if (Op.getOpcode() == zmtarzmISD::SETCC) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


unsigned BitWidth = Known.getBitWidth();


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SELECT_CC ) {

if (Op.getOpcode() == zmtarzmISD::SELECT_CC) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


void zmtarzmTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {

void zmtarzmTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const {


KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);

KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ;


unsigned BitWidth = Known.getBitWidth();


assert((Opc >= ISD::BUILTIN_OP_END || Opc == ISD::INTRINSIC_WO_CHAIN || Opc == ISD::INTRINSIC_W_CHAIN || Opc == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op is a target node!");


if ( Op . getOpcode ( ) == zmtarzmISD :: ADD ) {

if (Op.getOpcode() == zmtarzmISD::ADD) {


KnownZero = APInt::getHighBitsSet(32, 31);

KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: SUB ) {

if (Op.getOpcode() == zmtarzmISD::SUB) {


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


DAG.computeKnownBits(Op.getOperand(1), Known2, Depth + 1);

DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: ADC ) {

if (Op.getOpcode() == zmtarzmISD::ADC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SBB ) {

if (Op.getOpcode() == zmtarzmISD::SBB) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SMUL ) {

if (Op.getOpcode() == zmtarzmISD::SMUL) {


if ( Op . getOpcode ( ) == zmtarzmISD :: UMUL ) {

if (Op.getOpcode() == zmtarzmISD::UMUL) {


if ( Op . getOpcode ( ) == zmtarzmISD :: INC ) {

if (Op.getOpcode() == zmtarzmISD::INC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: DEC ) {

if (Op.getOpcode() == zmtarzmISD::DEC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: OR ) {


if ( Op . getOpcode ( ) == zmtarzmISD :: XOR ) {

if (Op.getOpcode() == zmtarzmISD::XOR) {


if ( Op . getOpcode ( ) == zmtarzmISD :: AND ) {

if (Op.getOpcode() == zmtarzmISD::AND) {


if ( Op . getOpcode ( ) == zmtarzmISD :: SETCC ) {

if (Op.getOpcode() == zmtarzmISD::SETCC) {


if ( Op . getOpcode ( ) == zmtarzmISD :: MOVMSK ) {

if (Op.getOpcode() == zmtarzmISD::MOVMSK) {


unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();

unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ;


Known . Zero . setBitsFrom ( NumLoBits ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSRLI ) {

if (Op.getOpcode() == zmtarzmISD::VSRLI) {


if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {

if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) {


DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ;


unsigned ShAmt = ShiftImm->getZExtValue();

unsigned ShAmt = ShiftImm -> getZExtValue ( ) ;


if ( Op . getOpcode ( ) == zmtarzmISD :: VSHLI ) {

if (Op.getOpcode() == zmtarzmISD::VSHLI) {


ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));

ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ;


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ;


unsigned BitWidth = Known . getBitWidth ( ) ;

unsigned BitWidth = Known.getBitWidth();


EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();

EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ;


unsigned MemBits = VT.getScalarSizeInBits();

unsigned MemBits = VT . getScalarSizeInBits ( ) ;


Known.Zero = Known.Zero | APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);

Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));

ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ;


uint32_t Width = CWidth->getZExtValue() & 0x1f;

uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ;


Known . Zero . setBits ( 1 , BitWidth ) ;


DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);


if ( Op . getOpcode ( ) == zmtarzmISD :: VZEXT ) {

if (Op.getOpcode() == zmtarzmISD::VZEXT) {


Intrinsic::ID IntID = static_cast<Intrinsic::ID>(Op.getOperand(0)->getZExtValue());

Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ;


MVT VT = Op.getOperand(1).getValueType().getSimpleVT();

MVT VT = Op . getOperand ( 1 ) . getValueType ( ) . getSimpleVT ( ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ;


APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);

APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ;


unsigned BitWidth = Known.getBitWidth();


KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);

KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


unsigned InNumElts = SrcVT.getVectorNumElements();

unsigned InNumElts = SrcVT . getVectorNumElements ( ) ;


unsigned InBitWidth = SrcVT.getScalarSizeInBits();

unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ;


Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);

Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ;


Known . Zero = Known . Zero & Known2 . Zero ;


Known . One = Known . One & Known2 . One ;


APInt DemandedSrcElts = APInt::getLowBitsSet(InNumElts, NumElts);

APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ;


DAG.computeKnownBits(N0, Known, DemandedSrcElts, Depth + 1);

DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ;


Known . Zero . setBitsFrom ( InBitWidth ) ;


MachineBasicBlock* zmtarzmTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const {

MachineBasicBlock * zmtarzmTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const {


const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();

const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ;


assert((MI->getOpcode() == zmtarzm::SELECT_CC) && "Unexpected instr type to insert");

assert
(
(
MI
->
getOpcode
(
)
==
zmtarzm
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;


const BasicBlock *LLVM_BB = BB->getBasicBlock();

const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ;


MachineFunction * F = BB -> getParent ( ) ;


MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);

MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ;


MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);

MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ;


copy1MBB->splice(copy1MBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end());

copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ;


copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


BuildMI ( BB , dl , TII . get ( # ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ;

BuildMI ( BB , dl , TII . get ( zmtarzm :: BCC ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ;


BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( zmtarzm :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( # ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( # ) . getReg ( ) ) . addMBB ( thisMBB ) ;

BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( zmtarzm :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ;


BuildMI ( BB , dl , TII . get ( zmtarzm :: JCC ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ;


BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( zmtarzm :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 3 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( thisMBB ) ;


SDValue zmtarzmTargetLowering::ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: ExpandADDSUB ( SDNode * N , SelectionDAG & DAG ) const {


assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!");

assert
(
(
N
->
getOpcode
(
)
==
ISD
::
SRL
||
N
->
getOpcode
(
)
==
ISD
::
SRA
)
&&
"Unknown shift to lower!"
)
;


if (!isa<ConstantSDNode>(N->getOperand(1)) || cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) {

if ( ! isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) || cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) {


SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned Opc = N->getOpcode() == ISD::SRL ? zmtarzmISD::SRL_FLAG:zmtarzmISD::SRA_FLAG;

unsigned Opc = N -> getOpcode ( ) == ISD :: SRL ? zmtarzmISD :: SRL_FLAG : zmtarzmISD :: SRA_FLAG ;


Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);

Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( MVT :: i32 , MVT :: Glue ) , Hi ) ;


Lo = DAG.getNode(zmtarzmISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));

Lo = DAG . getNode ( zmtarzmISD :: RRX , dl , MVT :: i32 , Lo , Hi . getValue ( 1 ) ) ;


return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);

return DAG . getNode ( ISD :: BUILD_PAIR , dl , MVT :: i64 , Lo , Hi ) ;


assert(VT.is256BitVector() && VT == V1.getValueType() && "Invalid nodes in input!");

assert
(
VT
.
is256BitVector
(
)
&&
VT
==
V1
.
getValueType
(
)
&&
"Invalid nodes in input!"
)
;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);

SDValue V0_LO = Extract128BitVector ( V0 , 0 , DAG , DL ) ;


SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);

SDValue V0_HI = Extract128BitVector ( V0 , NumElts / 2 , DAG , DL ) ;


SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);

SDValue V1_LO = Extract128BitVector ( V1 , 0 , DAG , DL ) ;


SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);

SDValue V1_HI = Extract128BitVector ( V1 , NumElts / 2 , DAG , DL ) ;


if (!isUndefLO && V0->getOpcode() != ISD::UNDEF) {

if ( ! isUndefLO && V0 -> getOpcode ( ) != ISD :: UNDEF ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V0_HI);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V0_HI ) ;


if (!isUndefHI && V1->getOpcode() != ISD::UNDEF) {

if ( ! isUndefHI && V1 -> getOpcode ( ) != ISD :: UNDEF ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V1_LO, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V1_LO , V1_HI ) ;


if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF || V1_LO->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefLO && ( V0_LO -> getOpcode ( ) != ISD :: UNDEF || V1_LO -> getOpcode ( ) != ISD :: UNDEF ) ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V1_LO);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V1_LO ) ;


if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF || V1_HI->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefHI && ( V0_HI -> getOpcode ( ) != ISD :: UNDEF || V1_HI -> getOpcode ( ) != ISD :: UNDEF ) ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_HI, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_HI , V1_HI ) ;


return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);

return DAG . getNode ( ISD :: CONCAT_VECTORS , DL , VT , LO , HI ) ;


SDValue zmtarzmTargetLowering::ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: ExpandADDSUB ( SDNode * N , SelectionDAG & DAG ) const {


assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!");

assert
(
(
N
->
getOpcode
(
)
==
ISD
::
SRL
||
N
->
getOpcode
(
)
==
ISD
::
SRA
)
&&
"Unknown shift to lower!"
)
;


if (!isa<ConstantSDNode>(N->getOperand(1)) || cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) {

if ( ! isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) || cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) {


SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned Opc = N->getOpcode() == ISD::SRL ? zmtarzmISD::SRL_FLAG:zmtarzmISD::SRA_FLAG;

unsigned Opc = N -> getOpcode ( ) == ISD :: SRL ? zmtarzmISD :: SRL_FLAG : zmtarzmISD :: SRA_FLAG ;


Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);

Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( MVT :: i32 , MVT :: Glue ) , Hi ) ;


Lo = DAG.getNode(zmtarzmISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));

Lo = DAG . getNode ( zmtarzmISD :: RRX , dl , MVT :: i32 , Lo , Hi . getValue ( 1 ) ) ;


return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);

return DAG . getNode ( ISD :: BUILD_PAIR , dl , MVT :: i64 , Lo , Hi ) ;


assert(VT.is256BitVector() && VT == V1.getValueType() && "Invalid nodes in input!");

assert
(
VT
.
is256BitVector
(
)
&&
VT
==
V1
.
getValueType
(
)
&&
"Invalid nodes in input!"
)
;


unsigned NumElts = VT.getVectorNumElements();

unsigned NumElts = VT . getVectorNumElements ( ) ;


SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);

SDValue V0_LO = Extract128BitVector ( V0 , 0 , DAG , DL ) ;


SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);

SDValue V0_HI = Extract128BitVector ( V0 , NumElts / 2 , DAG , DL ) ;


SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);

SDValue V1_LO = Extract128BitVector ( V1 , 0 , DAG , DL ) ;


SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);

SDValue V1_HI = Extract128BitVector ( V1 , NumElts / 2 , DAG , DL ) ;


if (!isUndefLO && V0->getOpcode() != ISD::UNDEF) {

if ( ! isUndefLO && V0 -> getOpcode ( ) != ISD :: UNDEF ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V0_HI);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V0_HI ) ;


if (!isUndefHI && V1->getOpcode() != ISD::UNDEF) {

if ( ! isUndefHI && V1 -> getOpcode ( ) != ISD :: UNDEF ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V1_LO, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V1_LO , V1_HI ) ;


if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF || V1_LO->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefLO && ( V0_LO -> getOpcode ( ) != ISD :: UNDEF || V1_LO -> getOpcode ( ) != ISD :: UNDEF ) ) {


LO = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_LO, V1_LO);

LO = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_LO , V1_LO ) ;


if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF || V1_HI->getOpcode() != ISD::UNDEF)) {

if ( ! isUndefHI && ( V0_HI -> getOpcode ( ) != ISD :: UNDEF || V1_HI -> getOpcode ( ) != ISD :: UNDEF ) ) {


HI = DAG.getNode(zmtarzmOpcode, DL, NewVT, V0_HI, V1_HI);

HI = DAG . getNode ( zmtarzmOpcode , DL , NewVT , V0_HI , V1_HI ) ;


return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);

return DAG . getNode ( ISD :: CONCAT_VECTORS , DL , VT , LO , HI ) ;


unsigned zmtarzmTargetLowering::getJumpTableEncoding() const {

unsigned zmtarzmTargetLowering :: getJumpTableEncoding ( ) const {


return MachineJumpTableInfo :: EK_Inline ;


std::pair<unsigned, const TargetRegisterClass *> zmtarzmTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {

std :: pair < unsigned , const TargetRegisterClass * > zmtarzmTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const {


return std :: make_pair ( 0U , zmtarzm :: CPUGRegsRegClass ) ;


return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


return std :: make_pair ( 0U , zmtarzm :: GPRRegClass ) ;


return std :: make_pair ( 0U , zmtarzm :: GR16RegClass ) ;


virtual MVT getShiftAmountTy(EVT LHSTy) const {

virtual MVT getShiftAmountTy ( EVT LHSTy ) const {


const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {

const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


if ((zmtarzmISD::NodeType)Opcode == #) {

if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BR_CC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BR_CC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Call ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Call) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FPMOV ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FPMOV) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: GOTLoad ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::GOTLoad) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFI ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFI) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXTR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXTR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Ret ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Ret) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SBFX ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SBFX) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SELECT_CC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SELECT_CC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SETCC ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SETCC) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: THREAD_POINTER ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::THREAD_POINTER) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TLSDESCCALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TLSDESCCALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: WrapperLarge ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::WrapperLarge) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: WrapperSmall ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::WrapperSmall) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_BSL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_BSL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_MOVIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_MOVIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_MVNIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_MVNIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_FMOVIMM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_FMOVIMM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_CMP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_CMP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_CMPZ ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_CMPZ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: NEON_TST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::NEON_TST) {


const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {

const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {


if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ((zmtarzmISD::NodeType)Opcode == #) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ALLOCA ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ALLOCA) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DCFETCH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DCFETCH) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST32_GP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST32_GP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: COMBINE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::COMBINE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALLR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALLR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALLnr ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALLnr) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BARRIER ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BARRIER) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AT_GOT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AT_GOT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: AT_PCREL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::AT_PCREL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: JT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::JT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INSERT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INSERT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXTRACTU ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXTRACTU) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TSTBIT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TSTBIT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EH_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EH_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VLSR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VLSR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VASR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VASR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VASL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VASL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TC_RETURN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TC_RETURN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VALIGNADDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VALIGNADDR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VALIGN ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VALIGN) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TYPECAST ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TYPECAST) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QFALSE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QFALSE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QTRUE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QTRUE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: QCAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::QCAT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Q2V ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Q2V) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: V2Q ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::V2Q) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: P2D ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::P2D) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: D2P ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::D2P) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VZERO ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VZERO) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: READCYCLE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::READCYCLE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VROR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VROR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VINSERTW0 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VINSERTW0) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VEXTRACTW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VEXTRACTW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: VSPLAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::VSPLAT) {