if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);

return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp(MBB, MBBI, NMBB);

return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandAtomicPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);

return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);

return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


bool zmtarzmExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());

TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandPseudoPass ( ) {


bool zmtarzmExpandPseudo::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;


MachineBasicBlock::iterator NMBBI = std::next(MBBI);

MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;


Modified = Modified | expandMI(MBB, MBBI, NMBBI);

Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;


bool zmtarzmExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandPseudo() : MachineFunctionPass(ID) {

zmtarzmExpandPseudo ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName ( ) const override {

StringRef getPassName() const override {


bool zmtarzmExpandPseudo::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;

TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandSDMAPass ( ) {


bool zmtarzmExpandSDMA::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandSDMA :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;

MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();


MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;

MachineBasicBlock::iterator NMBBI = std::next(MBBI);


Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;

Modified = Modified | expandMI(MBB, MBBI, NMBBI);


bool zmtarzmExpandSDMAInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandSDMAInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);

return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOp(MBB, MBBI, NMBB);

return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandSDMAInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandSDMAInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandSDMA() : MachineFunctionPass(ID) {

zmtarzmExpandSDMA ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandSDMAPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName ( ) const override {

StringRef getPassName() const override {


bool zmtarzmExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) {

bool zmtarzmExpandPseudo::runOnMachineFunction(MachineFunction &MF) {


TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;

TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());


Modified = Modified | expandMBB ( MBB ) ;


FunctionPass * createzmtarzmExpandSSRPass ( ) {


bool zmtarzmExpandSSR::expandMBB(MachineBasicBlock &MBB) {

bool zmtarzmExpandSSR :: expandMBB ( MachineBasicBlock & MBB ) {


MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ;

MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();


MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ;

MachineBasicBlock::iterator NMBBI = std::next(MBBI);


Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ;

Modified = Modified | expandMI(MBB, MBBI, NMBBI);


bool zmtarzmExpandSSRInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {

bool zmtarzmExpandSSRInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);

return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);

return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: PseudoCONST ) {

if (MBBI->getOpcode() == zmtarzm::PseudoCONST) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I64_POSTRA) {


return expandAtomicCmpSwap(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I8_POSTRA) {


return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_CMP_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_CMP_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I8_POSTRA) {


return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I16_POSTRA) {


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I8_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I8_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I16_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I16_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I32_POSTRA) {


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I32_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I32_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_ADD_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_ADD_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_SUB_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_SUB_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_AND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_AND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_OR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_OR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_XOR_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_XOR_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_LOAD_NAND_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_LOAD_NAND_I64_POSTRA) {


if ( MBBI -> getOpcode ( ) == zmtarzm :: ATOMIC_SWAP_I64_POSTRA ) {

if (MBBI->getOpcode() == zmtarzm::ATOMIC_SWAP_I64_POSTRA) {


bool zmtarzmExpandSSRInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

bool zmtarzmExpandSSRInsts::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) {


return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwap(MBB, MBBI, NMBB);


return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);


return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOpSubword(MBB, MBBI, NMBB);


return expandAtomicBinOp ( MBB , MBBI , NMBB ) ;

return expandAtomicBinOp(MBB, MBBI, NMBB);


if ( MBBI -> getOpcode ( ) == zmtarzm :: LOCRMux ) {

if (MBBI->getOpcode() == zmtarzm::LOCRMux) {


zmtarzmExpandSSR() : MachineFunctionPass(ID) {

zmtarzmExpandSSR ( ) : MachineFunctionPass ( ID ) {


initializezmtarzmExpandSSRPass ( * PassRegistry :: getPassRegistry ( ) ) ;


StringRef getPassName() const override {

StringRef getPassName ( ) const override {


bool zmtarzmExpandSSRInsts::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmExpandSSRInsts :: runOnMachineFunction ( MachineFunction & MF ) {


TII = static_cast<const zmtarzmInstrInfo *>(MF.getSubtarget().getInstrInfo());

TII = static_cast < const zmtarzmInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;


Modified = Modified | expandMBB ( MBB ) ;


fixup_zmtarzm_NONE = FirstTargetFixupKind ,


NumTargetFixupKinds = # - FirstTargetFixupKind

NumTargetFixupKinds = fixup_zmtarzm_invalid - FirstTargetFixupKind


fixup_zmtarzm_ldst_pcrel_12 = FirstTargetFixupKind ,


fixup_zmtarzm_32 = FirstTargetFixupKind ,


fixup_zmtarzm_hi6 = FirstTargetFixupKind ,


fixup_zmtarzm_addr32 = FirstTargetFixupKind ,


fixup_zmtarzm_mov_q1_pcrel = FirstTargetFixupKind ,


fixup_zmtarzm_rel_16 = FirstTargetFixupKind ,


fixup_zmtarzm_Imm8 = FirstTargetFixupKind ,


fixup_zmtarzm_br24 = FirstTargetFixupKind ,


fixup_zmtarzm_hi16_i = FirstTargetFixupKind ,


fixup_zmtarzm_mov_hi16_pcrel = FirstTargetFixupKind ,


fixup_zmtarzm_reflong = FirstTargetFixupKind ,


fixup_zmtarzm_16 = FirstTargetFixupKind ,


fixup_zmtarzm_sleb128_i32 = FirstTargetFixupKind ,


fixup_zmtarzm_ldst_imm4_scale2 = FirstTargetFixupKind ,


void zmtarzmFrameLowering::adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag) const {

void zmtarzmFrameLowering :: adjustReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DestReg , Register SrcReg , int64_t Val , MachineInstr :: MIFlag Flag ) const {


MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV), DestReg).addReg(SrcReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV ) , DestReg ) . addReg ( SrcReg ) ;


BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::ADDI), DestReg).addReg(SrcReg).addImm(Val).setMIFlag(Flag);

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: ADDI ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ;


Register ScratchReg = MRI.createVirtualRegister(&zmtarzm::GPRRegClass);

Register ScratchReg = MRI . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);

TII -> movImm ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ;


BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg).addReg(SrcReg).addReg(ScratchReg, RegState::Kill).setMIFlag(Flag);

BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ;


bool zmtarzmFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {

bool zmtarzmFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const {


if ( ! needPopSpecialFixUp ( * MBB . getParent ( ) ) ) {


MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);

MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ;


const MachineFunction &MF = *MBB.getParent();

const MachineFunction & MF = * MBB . getParent ( ) ;


if ( MF . getInfo < MachineFunctionInfo > ( ) -> hasSwiftAsyncContext ( ) ) {


if ( canUseLEAForSPInEpilogue ( * MBB . getParent ( ) ) ) {


return emitPopSpecialFixUp ( * TmpMBB , false ) ;


assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;

assert(MBB.getParent() && "Block is not attached to a function!");


bool zmtarzmFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {

bool zmtarzmFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const {


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const Subtarget &Subtarget = MF->getSubtarget<Subtarget>();

const Subtarget & Subtarget = MF -> getSubtarget < Subtarget > ( ) ;


const RegisterInfo *RegInfo = Subtarget.getRegisterInfo();

const RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


if ( ! RegInfo -> hasStackRealignment ( * MF ) ) {


return findScratchNonCalleeSaveRegister(TmpMBB) != zmtarzm::NoRegister;

return findScratchNonCalleeSaveRegister ( TmpMBB ) != zmtarzm :: NoRegister ;


if ( ! MBB . isLiveIn ( zmtarzm :: EFLAGS ) ) {


const MachineFunctionInfo *FI = MF.getInfo<zmtarzmMachineFunctionInfo>();

const MachineFunctionInfo * FI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


return ! TRI -> needsStackRealignment ( MF ) && ! FI -> hasSwiftAsyncContext ( ) ;

return !TRI->needsStackRealignment(MF) && !FI->hasSwiftAsyncContext();


void zmtarzmFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const {

void zmtarzmFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {


TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


static const MCPhysReg CSRegs[] = {zmtarzm::R0,  zmtarzm::R1,  zmtarzm::R2, zmtarzm::R3, zmtarzm::R12, zmtarzm::R13, 0};

static const MCPhysReg CSRegs [ ] = { zmtarzm :: R0 , zmtarzm :: R1 , zmtarzm :: R2 , zmtarzm :: R3 , zmtarzm :: R12 , zmtarzm :: R13 , 0 } ;


for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) {


static const MCPhysReg CSHRegs[] = {zmtarzm::R18, zmtarzm::R19, zmtarzm::R20, zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24, zmtarzm::R25, 0};

static const MCPhysReg CSHRegs [ ] = { zmtarzm :: R18 , zmtarzm :: R19 , zmtarzm :: R20 , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , 0 } ;


for ( unsigned i = 0 ; CSHRegs [ i ] ; ++ i ) {


static const MCPhysReg CSF32Regs[] = {zmtarzm::F8_32,  zmtarzm::F9_32,  zmtarzm::F10_32, zmtarzm::F11_32, zmtarzm::F12_32, zmtarzm::F13_32, zmtarzm::F14_32, zmtarzm::F15_32, 0};

static const MCPhysReg CSF32Regs [ ] = { zmtarzm :: F8_32 , zmtarzm :: F9_32 , zmtarzm :: F10_32 , zmtarzm :: F11_32 , zmtarzm :: F12_32 , zmtarzm :: F13_32 , zmtarzm :: F14_32 , zmtarzm :: F15_32 , 0 } ;


static const MCPhysReg CSF64Regs[] = {zmtarzm::F8_64,  zmtarzm::F9_64,  zmtarzm::F10_64, zmtarzm::F11_64, zmtarzm::F12_64, zmtarzm::F13_64, zmtarzm::F14_64, zmtarzm::F15_64, 0};

static const MCPhysReg CSF64Regs [ ] = { zmtarzm :: F8_64 , zmtarzm :: F9_64 , zmtarzm :: F10_64 , zmtarzm :: F11_64 , zmtarzm :: F12_64 , zmtarzm :: F13_64 , zmtarzm :: F14_64 , zmtarzm :: F15_64 , 0 } ;


const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs();

const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ;


for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) {


if ( zmtarzm :: FPR64RegClass . contains ( Regs [ i ] ) ) {


if ( zmtarzm :: FPR32RegClass . contains ( Regs [ i ] ) ) {


CFI -> setLRIsSpilled ( SavedRegs . test ( zmtarzm :: R15 ) ) ;


for (unsigned Reg : SavedRegs.set_bits()) {

for ( unsigned Reg : SavedRegs . set_bits ( ) ) {


auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;

auto RegSize = TRI -> getRegSizeInBits ( Reg , MRI ) / 8 ;


CFI -> setCalleeSaveAreaSize ( CSStackSize ) ;


uint64_t Limit = estimateRSStackSizeLimit(MF, STI);

uint64_t Limit = estimateRSStackSizeLimit ( MF , STI ) ;


bool BigFrame = (MFI.estimateStackSize(MF) + CSStackSize >= Limit);

bool BigFrame = ( MFI . estimateStackSize ( MF ) + CSStackSize >= Limit ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


unsigned size = TRI -> getSpillSize ( * RC ) ;


Align align = TRI -> getSpillAlign ( * RC ) ;


RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( size , align , false ) ) ;


MachineBasicBlock::iterator zmtarzmFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {

MachineBasicBlock :: iterator zmtarzmFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const {


int64_t Amount = MI->getOperand(0).getImm();

int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ;


if (MI->getOpcode() == zmtarzm::ADJCALLSTACKDOWN) {

if ( MI -> getOpcode ( ) == zmtarzm :: ADJCALLSTACKDOWN ) {


adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);

adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ;


void zmtarzmFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


zmtarzmMachineFunctionInfo *CFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * CFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineBasicBlock::iterator MBBI = MBB.end();

MachineBasicBlock :: iterator MBBI = MBB . end ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


LastFrameDestroy = std::prev(MBBI, CSI.size());

LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ;


uint64_t StackSize = MFI.getStackSize();

uint64_t StackSize = MFI . getStackSize ( ) ;


uint64_t ActualSize = CFI->getCalleeSaveAreaSize() + CFI->getVarArgsSaveSize();

uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ;


BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg).addReg(FPReg).setMIFlag(MachineInstr::NoFlags);

BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ;


adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize), MachineInstr::FrameDestroy);

adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize, MachineInstr::FrameDestroy);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ;


if (materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDrr ) , zmtarzm :: SP ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


if (!materializeOffset(MF, MBB, MBBI, (unsigned)StackSize)) {

if ( ! materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) {


BuildMI(MBB, MBBI, DL, TII.get(zmtarzm::ADDri), zmtarzm::SP).addReg(StackReg).addImm(StackSize).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII . get ( zmtarzm :: ADDri ) , zmtarzm :: SP ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


void zmtarzmFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const {

void zmtarzmFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


const RegisterInfo *RI = STI.getRegisterInfo();

const RegisterInfo * RI = STI . getRegisterInfo ( ) ;


MachineFunctionInfo *CFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


MachineBasicBlock::iterator MBBI = MBB.begin();

MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ;


const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) {


BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: NIE ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::NIE));


uint64_t StackSize = MFI . getStackSize ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


unsigned spillAreaSize = CFI->getCalleeSaveAreaSize();

unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ;


uint64_t ActualSize = spillAreaSize + CFI->getVarArgsSaveSize();

uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, ActualSize));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


std :: advance ( MBBI , CSI . size ( ) ) ;


int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());

int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ;


unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;

unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ;


for ( unsigned i = 0 ; i < Num ; i ++ ) {


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, RI->getDwarfRegNum(Reg, true) + i, Offset + i * 4));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , FPReg ) . addReg ( SPReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg).addReg(SPReg).setMIFlag(MachineInstr::FrameSetup);


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RI->getDwarfRegNum(FPReg, true)));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ;


adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(StackSize - ActualSize)), MachineInstr::NoFlags);

adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


const zmtarzmRegisterInfo *RI = STI.getRegisterInfo();

const zmtarzmRegisterInfo * RI = STI . getRegisterInfo ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


Align MaxAlignment = MFI . getMaxAlign ( ) ;


const zmtarzmInstrInfo *TII = STI.getInstrInfo();

const zmtarzmInstrInfo * TII = STI . getInstrInfo ( ) ;


if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: ANDNI32 ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::ANDNI32), SPReg).addReg(SPReg).addImm(~(-(int)MaxAlignment.value()));


unsigned ShiftAmount = Log2(MaxAlignment);

unsigned ShiftAmount = Log2 ( MaxAlignment ) ;


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::GPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: GPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI32 ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI32), VR).addReg(SPReg).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI32 ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI32), SPReg).addReg(VR).addImm(ShiftAmount);


Register VR = MF.getRegInfo().createVirtualRegister(&zmtarzm::mGPRRegClass);

Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & zmtarzm :: mGPRRegClass ) ;


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , VR ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), VR).addReg(SPReg);


BuildMI(MBB, MBBI, DL, TII->get(#), VR).addReg(VR).addImm(ShiftAmount);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSRI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSRI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: LSLI16 ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::LSLI16), VR).addReg(VR).addImm(ShiftAmount);


BuildMI(MBB, MBBI, DL, TII->get(#), SPReg).addReg(VR);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , SPReg ) . addReg ( VR ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( zmtarzm :: MOV16 ) , SPReg ) . addReg ( VR ) ;

BuildMI(MBB, MBBI, DL, TII->get(zmtarzm::MOV16), SPReg).addReg(VR);


if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) {


BuildMI(MBB, MBBI, DL, TII->get(#), BPReg).addReg(SPReg);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) , BPReg ) . addReg ( SPReg ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: COPY ) , BPReg ) . addReg ( SPReg ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), BPReg).addReg(SPReg);


adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ;


unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ;


BuildMI(MBB, MBBI, DL, TII->get(#)).addCFIIndex(CFIIndex);

BuildMI ( MBB , MBBI , DL , TII -> get ( # ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);


explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsUp, #, #), STI(STI) {

explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsUp , # , # ) , STI ( STI ) {

explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 4 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 4, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 8 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 8, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 2 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 2, 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( 16 ) , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(16), 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( 4 ) , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(4), 0), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 1 , - 1 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 1, -1), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 4 , - 4 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 4, -4), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 2 , - 2 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 2, -2), STI(STI) {


explicit zmtarzmFrameLowering ( const zmtarzmSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 16 , 0 ) , STI ( STI ) {

explicit zmtarzmFrameLowering(const zmtarzmSubtarget &STI) : TargetFrameLowering(StackGrowsDown, 16, 0), STI(STI) {


StackOffset zmtarzmFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const {

StackOffset zmtarzmFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const {


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const auto *CFI = MF.getInfo<MachineFunctionInfo>();

const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const auto &CSI = MFI.getCalleeSavedInfo();

const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getOffsetAdjustment();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ;


MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();

MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ;


Offset = Offset + CFI->getVarArgsSaveSize() + CFI->getCalleeSaveAreaSize();

Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


if ( ! MFI . isFixedObjectIndex ( FI ) ) {


FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : zmtarzm :: R14 ;

FrameReg = hasBP(MF) ? getBPReg(STI) : zmtarzm::R14;


Offset = Offset + MFI . getStackSize ( ) ;


if ( MFI . isFixedObjectIndex ( FI ) ) {


if ( ! RI -> hasStackRealignment ( MF ) ) {


int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);

int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ;


return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize());

return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ;


if ( RI -> needsStackRealignment ( MF ) ) {


FrameReg = RI -> getFrameRegister ( MF ) ;


return StackOffset :: getFixed ( Offset ) ;


StackOffset zmtarzmFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const {


const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ;


const auto & CSI = MFI . getCalleeSavedInfo ( ) ;


int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ;


MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ;


Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ;


if ( RI -> hasStackRealignment ( MF ) ) {


if ( ! MFI . isFixedObjectIndex ( FI ) ) {


Offset = Offset + MFI . getStackSize ( ) ;


if ( MFI . isFixedObjectIndex ( FI ) ) {


if ( ! RI -> hasStackRealignment ( MF ) ) {


int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ;


return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ;


if ( RI -> needsStackRealignment ( MF ) ) {


FrameReg = RI -> getFrameRegister ( MF ) ;


return StackOffset :: getFixed ( FrameOffset ) ;


bool zmtarzmFrameLowering::hasBP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasBP ( const MachineFunction & MF ) const {


const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterInfo *TRI = STI.getRegisterInfo();

const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;


return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);

return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment ( MF ) ;


bool zmtarzmFrameLowering::hasFP(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasFP ( const MachineFunction & MF ) const {


const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();

const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


bool zmtarzmFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {

bool zmtarzmFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {


return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


void zmtarzmFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const {

void zmtarzmFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const {


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


if ( ! isInt < # > ( MFI . estimateStackSize ( MF ) ) ) {

if ( ! isInt < 9 > ( MFI . estimateStackSize ( MF ) ) ) {


int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);

int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ;


RS -> addScavengingFrameIndex ( RegScavFI ) ;


bool zmtarzmFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


MachineFunction * MF = MBB . getParent ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);

TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ;


assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg()).addReg(zmtarzm::R15);

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) . addReg ( zmtarzm :: R15 ) ;


BuildMI(MBB, MI, DL, TII.get(#), CSI[i].getReg());

BuildMI ( MBB , MI , DL , TII . get ( # ) , CSI [ i ] . getReg ( ) ) ;


BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: POP ) , CSI [ i ] . getReg ( ) ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::POP), CSI[i].getReg());


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;

assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && "Invalid register size");


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSHRr ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSHRr)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: MOV32rmpush ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::MOV32rmpush), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(zmtarzm::tPUSH));

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: tPUSH ) ) ;


MachineFunctionInfo *zmtarzmFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * zmtarzmFI = MF . getInfo < MachineFunctionInfo > ( ) ;


MachineFunctionInfo *MFI = MF.getInfo<MachineFunctionInfo>();

MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ;


zmtarzmMachineFunctionInfo *MFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * MFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ;


const Register RAReg = STI.getRegisterInfo()->getRARegister();

const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ;


for (unsigned i = CSI.size(); i != 0; --i) {

for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) {


BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), CS.getDstReg()).addReg(Reg, getKillRegState(true));

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


const bool IsLiveIn = MRI.isLiveIn(Reg);

const bool IsLiveIn = MRI . isLiveIn ( Reg ) ;


TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ;


if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) {


if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) {


MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, getKillRegState(IsNotLiveIn)).setMIFlag(MachineInstr::FrameSetup);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


BuildMI(MBB, MI, DL, TII.get(#)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI ( MBB , MI , DL , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;

BuildMI(MBB, MI, DL, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::LR) && MF->getFrameInfo().isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::RA || Reg == zmtarzm::RA_64) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: RA || Reg == zmtarzm :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


bool IsRAAndRetAddrIsTaken = (Reg == zmtarzm::L) && MF->getFrameInfo()->isReturnAddressTaken();

bool IsRAAndRetAddrIsTaken = ( Reg == zmtarzm :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;


const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);


TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


BuildMI(MBB, MI, dl, TII.get(zmtarzm::PUSH16r)).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , dl , TII . get ( zmtarzm :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ;


BuildMI(MBB, MI, DL, TII.get(#), zmtarzm::R15).addReg(Reg).addReg(Reg, RegState::Kill);

BuildMI ( MBB , MI , DL , TII . get ( # ) , zmtarzm :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ;


const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;


TII->storeRegToStackSlot(MBB, MBBI, Reg,  true, CS.getFrameIdx(), RC, TRI);

TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


MIB . setMIFlags ( MachineInstr :: FrameSetup ) ;


zmtarzmFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


bool zmtarzmFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

bool zmtarzmFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const {


DebugLoc DL = MBB . findDebugLoc ( MI ) ;


MachineFunction * MF = MBB . getParent ( ) ;


MachineBasicBlock *EntryBlock = &MF->front();

MachineBasicBlock * EntryBlock = & MF -> front ( ) ;


const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;