const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {

const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {


if ((zmtarzmISD::NodeType)Opcode == #) {

if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CALL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CALL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMUL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMUL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RET_FLAG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RET_FLAG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TBUFFER_STORE_FORMAT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TBUFFER_STORE_FORMAT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: STORE_MSKOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::STORE_MSKOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_P2 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_P2) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_P1 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_P1) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: INTERP_MOV ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::INTERP_MOV) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SENDMSG ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SENDMSG) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST_DATA_PTR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST_DATA_PTR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BUILD_VERTICAL_VECTOR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BUILD_VERTICAL_VECTOR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE2 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE2) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE1 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE1) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CVT_F32_UBYTE0 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CVT_F32_UBYTE0) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLEL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLEL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLED ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLED) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLEB ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLEB) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SAMPLE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SAMPLE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LOAD_INPUT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LOAD_INPUT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LOAD_CONSTANT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LOAD_CONSTANT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: REGISTER_STORE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::REGISTER_STORE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: REGISTER_LOAD ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::REGISTER_LOAD) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RCP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RCP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: RSQ_CLAMPED ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::RSQ_CLAMPED) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LDEXP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LDEXP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FP_CLASS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FP_CLASS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DOT4 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DOT4) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CARRY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CARRY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BORROW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BORROW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CONST_ADDRESS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CONST_ADDRESS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: EXPORT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::EXPORT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TEXTURE_FETCH ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TEXTURE_FETCH) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAD_I24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAD_I24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAD_U24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAD_U24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MUL_I24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MUL_I24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MUL_U24 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MUL_U24) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FFBH_U32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FFBH_U32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFM ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFM) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFI ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFI) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFE_I32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFE_I32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BFE_U32 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BFE_U32) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BRANCH_COND ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BRANCH_COND) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DWORDADDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DWORDADDR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FRACT ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FRACT) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CLAMP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CLAMP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: COS_HW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::COS_HW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SIN_HW ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SIN_HW) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMAX_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMAX_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMIN_LEGACY ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMIN_LEGACY) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMAX3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMAX3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMIN3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMIN3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: UMED3 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::UMED3) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: URECIP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::URECIP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_SCALE ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_SCALE) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_FMAS ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_FMAS) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DIV_FIXUP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DIV_FIXUP) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: TRIG_PREOP ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::TRIG_PREOP) {


const char *zmtarzmTargetLowering::getTargetNodeName(unsigned Opcode) const {

const char * zmtarzmTargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


if ( ( zmtarzmISD :: NodeType ) Opcode == # ) {

if ((zmtarzmISD::NodeType)Opcode == #) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: JmpLink ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::JmpLink) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Hi ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Hi) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Lo ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Lo) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: GPRel ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::GPRel) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ThreadPointer ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ThreadPointer) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Ret ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Ret) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FPBrcond ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FPBrcond) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: FPCmp ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::FPCmp) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CMovFP_T ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CMovFP_T) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: CMovFP_F ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::CMovFP_F) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAdd ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAdd) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MAddu ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MAddu) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MSub ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MSub) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: MSubu ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::MSubu) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DivRem ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DivRem) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DivRemU ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DivRemU) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: BuildPairF64 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::BuildPairF64) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: ExtractElementF64 ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::ExtractElementF64) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Wrapper ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Wrapper) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: DynAlloc ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::DynAlloc) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Sync ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Sync) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Ext ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Ext) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: Ins ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::Ins) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LWL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LWL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LWR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LWR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SWL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SWL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SWR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SWR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LDL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LDL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: LDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::LDR) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SDL ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SDL) {


if ( ( zmtarzmISD :: NodeType ) Opcode == zmtarzmISD :: SDR ) {

if ((zmtarzmISD::NodeType)Opcode == zmtarzmISD::SDR) {


bool zmtarzmTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const {

bool zmtarzmTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const {


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ;


Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 0 ) ;


Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ;


PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());

PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 1 ) ;


Info . ptrVal = I . getArgOperand ( 2 ) ;


uint64_t NumElts = I.getModule()->getDataLayout().getTypeSizeInBits(I.getType()) / 64;

uint64_t NumElts = I . getModule ( ) -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) / 64 ;


Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);

Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ;


Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);

Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ;


Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;

Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ;


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_load_add_f32 ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_load_add_f32) {


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_load_inc_32 ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_load_inc_32) {


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_load_dec_32 ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_load_dec_32) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldu_global_i ) {

if (Intrinsic == Intrinsic::zmtarzm_ldu_global_i) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldu_global_f ) {

if (Intrinsic == Intrinsic::zmtarzm_ldu_global_f) {


if ( Intrinsic == Intrinsic :: zmtarzm_ldu_global_p ) {

if (Intrinsic == Intrinsic::zmtarzm_ldu_global_p) {


bool zmtarzmTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const {


PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ;


Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 0 ) ;


Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ;


PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ;


Info . ptrVal = I . getArgOperand ( 1 ) ;


Info . ptrVal = I . getArgOperand ( 2 ) ;


uint64_t NumElts = I . getModule ( ) -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) / 64 ;


Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ;


Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ;


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_notify ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_notify) {


Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ;


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_wait_i32 ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_wait_i32) {


if ( Intrinsic == Intrinsic :: zmtarzm_atomic_wait_i64 ) {

if (Intrinsic == Intrinsic::zmtarzm_atomic_wait_i64) {


bool zmtarzmTargetLowering::hasBitPreservingFPLogic(EVT VT) const {

bool zmtarzmTargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const {


return VT == MVT :: f32 || VT == MVT :: f64 ;

return VT == MVT::f32 || VT == MVT::f64;


return VT . getScalarType ( ) == MVT :: f32 || VT . getScalarType ( ) == MVT :: f64 || VT . getScalarType ( ) == MVT :: f128 ;

return VT.getScalarType() == MVT::f32 || VT.getScalarType() == MVT::f64 || VT.getScalarType() == MVT::f128;


return VT == MVT :: f32 || VT == MVT :: f64 || VT . isVector ( ) || ( VT == MVT :: f16 && Subtarget . hasFP16 ( ) ) ;

return VT == MVT::f32 || VT == MVT::f64 || VT.isVector() || (VT == MVT::f16 && Subtarget.hasFP16());


bool zmtarzmTargetLowering::isCheapToSpeculateCtlz() const {

bool zmtarzmTargetLowering :: isCheapToSpeculateCtlz ( ) const {


bool zmtarzmTargetLowering::isCheapToSpeculateCttz() const {

bool zmtarzmTargetLowering :: isCheapToSpeculateCttz ( ) const {


bool zmtarzmTargetLowering::isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const {

bool zmtarzmTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const {


if ( N -> getOpcode ( ) != ISD :: SHL ) {


bool zmtarzmTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector<CCValAssign, 16> &ArgLocs) const {

bool zmtarzmTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const {


if ( ! mayTailCallThisCC ( CalleeCC ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const Function &CallerF = MF.getFunction();

const Function & CallerF = MF . getFunction ( ) ;


CallingConv::ID CallerCC = CallerF.getCallingConv();

CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ;


for (Function::const_arg_iterator i = CallerF.arg_begin(), e = CallerF.arg_end(); i != e; ++i) {

for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) {


if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) {


return canGuaranteeTCO(CalleeCC) && CCMatch;

return canGuaranteeTCO ( CalleeCC ) && CCMatch ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


const Triple &TT = getTargetMachine().getTargetTriple();

const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;


if ( GV -> hasExternalWeakLinkage ( ) ) {


assert((!isVarArg || CalleeCC == CallingConv::C) && "Unexpected variadic calling convention");


LLVMContext & C = * DAG . getContext ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);

CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ;


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ;


for (const CCValAssign &ArgLoc : ArgLocs) {

for ( const CCValAssign & ArgLoc : ArgLocs ) {


if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, CCAssignFnForCall(CalleeCC, isVarArg), CCAssignFnForCall(CallerCC, isVarArg))) {

if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) {


const zmtarzmRegisterInfo *TRI = Subtarget->getRegisterInfo();

const zmtarzmRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ;


const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);

const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ;


const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);

const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;


if ( Subtarget -> hasCustomCallingConv ( ) ) {


TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ;


TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ;


if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) {

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) {


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ;


const zmtarzmFunctionInfo *FuncInfo = MF.getInfo<zmtarzmFunctionInfo>();

const zmtarzmFunctionInfo * FuncInfo = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {

if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) {


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) {

if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) {


if (CCInfo.getInRegsParamsCount() > 0) {

if ( CCInfo . getInRegsParamsCount ( ) > 0 ) {


bool zmtarzmTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector<CCValAssign, 16> &ArgLocs) const {

bool zmtarzmTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const {


if ( ! mayTailCallThisCC ( CalleeCC ) ) {


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


const Function &CallerF = MF.getFunction();

const Function & CallerF = MF . getFunction ( ) ;


CallingConv::ID CallerCC = CallerF.getCallingConv();

CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ;


for (Function::const_arg_iterator i = CallerF.arg_begin(), e = CallerF.arg_end(); i != e; ++i) {

for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) {


if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) {


return canGuaranteeTCO(CalleeCC) && CCMatch;

return canGuaranteeTCO ( CalleeCC ) && CCMatch ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


const Triple &TT = getTargetMachine().getTargetTriple();

const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ;


if ( GV -> hasExternalWeakLinkage ( ) ) {


assert((!isVarArg || CalleeCC == CallingConv::C) && "Unexpected variadic calling convention");


LLVMContext & C = * DAG . getContext ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);

CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ;


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ;


for (const CCValAssign &ArgLoc : ArgLocs) {

for ( const CCValAssign & ArgLoc : ArgLocs ) {


if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, CCAssignFnForCall(CalleeCC, isVarArg), CCAssignFnForCall(CallerCC, isVarArg))) {

if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) {


const zmtarzmRegisterInfo *TRI = Subtarget->getRegisterInfo();

const zmtarzmRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ;


const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);

const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ;


const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);

const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;


if ( Subtarget -> hasCustomCallingConv ( ) ) {


TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ;


TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ;


if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) {

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) {


CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ;


const zmtarzmFunctionInfo *FuncInfo = MF.getInfo<zmtarzmFunctionInfo>();

const zmtarzmFunctionInfo * FuncInfo = MF . getInfo < zmtarzmFunctionInfo > ( ) ;


if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {

if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) {


const MachineRegisterInfo &MRI = MF.getRegInfo();

const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals)) {

if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) {


if (CCInfo.getInRegsParamsCount() > 0) {

if ( CCInfo . getInRegsParamsCount ( ) > 0 ) {


return NextStackOffset <= FI . getIncomingArgSize ( ) ;

return NextStackOffset <= FI.getIncomingArgSize();


bool zmtarzmTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const {

bool zmtarzmTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const {


if ( VT . getSimpleVT ( ) . SimpleTy == # ) {


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f16 ) {

if (VT.getSimpleVT().SimpleTy == MVT::f16) {


return Subtarget -> has16BitInsts ( ) && Subtarget -> hasFP16Denormals ( ) ;

return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals();


if (VT.getSimpleVT().SimpleTy == MVT::f32) {

if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f32 ) {


return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ;

return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();


if (VT.getSimpleVT().SimpleTy == MVT::f64) {

if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f64 ) {


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: v4f32 ) {

if (VT.getSimpleVT().SimpleTy == MVT::v4f32) {


return Subtarget -> hasMVEFloatOps ( ) ;


if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: v8f16 ) {

if (VT.getSimpleVT().SimpleTy == MVT::v8f16) {


bool zmtarzmTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const {

bool zmtarzmTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const {


return zmtarzm_AM::getFP16Imm(Imm) != -1;

return zmtarzm_AM :: getFP16Imm ( Imm ) != - 1 ;


return zmtarzm_AM::getFP32Imm(Imm) != -1;

return zmtarzm_AM :: getFP32Imm ( Imm ) != - 1 ;


return zmtarzm_AM::getFP64Imm(Imm) != -1;

return zmtarzm_AM :: getFP64Imm ( Imm ) != - 1 ;


bool zmtarzmTargetLowering::isLegalAddImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


bool zmtarzmTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {

bool zmtarzmTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const {


if ( ! isInt < # > ( AM . BaseOffs ) ) {


if ( ! isInt < 16 > ( AM . BaseOffs ) ) {


bool zmtarzmTargetLowering::isLegalICmpImmediate(int64_t Imm) const {

bool zmtarzmTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const {


bool zmtarzmTargetLowering::isSExtCheaperThanZExt(EVT VT1, EVT VT2) const {

bool zmtarzmTargetLowering :: isSExtCheaperThanZExt ( EVT VT1 , EVT VT2 ) const {


return Subtarget.is64Bit() && VT1 == MVT::i32 && VT2 == MVT::i64;

return Subtarget . is64Bit ( ) && VT1 == MVT :: i32 && VT2 == MVT :: i64 ;


bool zmtarzmTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {

bool zmtarzmTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const {


unsigned SrcBits = SrcVT.getSizeInBits();

unsigned SrcBits = SrcVT . getSizeInBits ( ) ;


unsigned DestBits = DstVT.getSizeInBits();

unsigned DestBits = DstVT . getSizeInBits ( ) ;


return (SrcBits == 64 && DestBits == 32);

return ( SrcBits == 64 && DestBits == 32 ) ;


bool zmtarzmTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {

bool zmtarzmTargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const {


unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits();

unsigned NumBits1 = SrcTy -> getPrimitiveSizeInBits ( ) ;


unsigned NumBits2 = DstTy->getPrimitiveSizeInBits();

unsigned NumBits2 = DstTy -> getPrimitiveSizeInBits ( ) ;


return NumBits1 == 64 && NumBits2 == 32;


bool zmtarzmTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {

bool zmtarzmTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const {


if (auto *LD = dyn_cast<LoadSDNode>(Val)) {

if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) {


if (LD->getExtensionType() == ISD::NON_EXTLOAD) {

if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) {


if (LD->getExtensionType() == ISD::ZEXTLOAD) {

if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) {


return TargetLowering :: isZExtFree ( Val , VT2 ) ;


void zmtarzmTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const {

void zmtarzmTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const {


char ConstraintLetter = Constraint [ 0 ] ;


MVT XLenVT = Op . getValueType ( ) + 1 - 1 ;


if (auto *C = dyn_cast<ConstantSDNode>(Op)) {

if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) {


Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ;


Ops . push_back ( DAG . getTargetConstant ( 0 , DL , XLenVT ) ) ;


TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);

TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


SDValue zmtarzmTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const {


BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);

BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {

if (VA.getLocInfo() == CCValAssign::BCvt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


unsigned Reg = RVLocs [ i ] . getLocReg ( ) ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1);

Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ;


InVals . push_back ( Chain . getValue ( 0 ) ) ;


return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , DL , DAG , InVals ) ;

return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, InVals);


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end.");


assert ( ByValArg != zmtarzmCCInfo . byval_end ( ) ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {

if (VA.getLocInfo() == CCValAssign::Full) {


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


if ( ! Subtarget -> inzmtarzm16Mode ( ) ) {


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


unsigned Reg = RVLocs [ i ] . getLocReg ( ) ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1);

Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ;


InVals . push_back ( Chain . getValue ( 0 ) ) ;


return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;

return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, InVals);


SDValue zmtarzmTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const {


ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);

ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ;


SDValue zmtarzmTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


assert
(
Op
.
getOpcode
(
)
==
ISD
::
EXTRACT_VECTOR_ELT
&&
"Unknown opcode!"
)
;

assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");


if ( ! isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


EVT ExtrTy = WideTy.getVectorElementType();

EVT ExtrTy = WideTy . getVectorElementType ( ) ;


if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {

if ( const ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ) {


SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue Result = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result, DAG.getConstant(16, SL, MVT::i32));

Result = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , Result , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


if ( ResultVT . bitsLT ( MVT :: i32 ) ) {


Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);

Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ;


return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);

return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;


SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);

SDValue Sixteen = DAG . getConstant ( 16 , SL , MVT :: i32 ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , Sixteen ) ;


SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BC = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);

SDValue Elt = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , BC , ScaledIdx ) ;


if ( Subtarget . isHVXVectorType ( VecTy ) ) {


return LowerHvxExtractElement ( Op , DAG ) ;


MVT ElemTy = ty(Vec).getVectorElementType();

MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;


SDValue Vector = Op . getOperand ( 0 ) ;


SDValue LaneIndex = Op . getOperand ( 1 ) ;


if (Vector.getSimpleValueType() != MVT::v16i1) {

if ( Vector . getSimpleValueType ( ) != MVT :: v16i1 ) {


SDValue MaskBits = DAG.getNode(zmtarzmISD::MASK_TO_INT, DL, MVT::i32, Vector);

SDValue MaskBits = DAG . getNode ( zmtarzmISD :: MASK_TO_INT , DL , MVT :: i32 , Vector ) ;


SDValue Elem = DAG.getNode(ISD::SRL, DL, MVT::i32, MaskBits, LaneIndex);

SDValue Elem = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , MaskBits , LaneIndex ) ;


if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {

if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) {


uint64_t Index = CIndexN->getZExtValue();

uint64_t Index = CIndexN -> getZExtValue ( ) ;


unsigned Mask = VecVT.getVectorNumElements() - 1;

unsigned Mask = VecVT . getVectorNumElements ( ) - 1 ;


MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VecVT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);

SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ;


return DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , ExtrTy , WideVec , Op . getOperand ( 1 ) ) ;

return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, Op.getOperand(1));


SDValue zmtarzmTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


if ( ! isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


EVT ExtrTy = WideTy.getVectorElementType();

EVT ExtrTy = WideTy . getVectorElementType ( ) ;


if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {

if ( const ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ) {


SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue Result = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result, DAG.getConstant(16, SL, MVT::i32));

Result = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , Result , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


assert ( CIdx -> getZExtValue ( ) == 0 ) ;


if ( ResultVT . bitsLT ( MVT :: i32 ) ) {


Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);

Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ;


return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);

return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;


SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);

SDValue Sixteen = DAG . getConstant ( 16 , SL , MVT :: i32 ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , Sixteen ) ;


SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BC = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);

SDValue Elt = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , BC , ScaledIdx ) ;


if ( Subtarget . isHVXVectorType ( VecTy ) ) {


return LowerHvxExtractElement ( Op , DAG ) ;


MVT ElemTy = ty(Vec).getVectorElementType();

MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;


SDValue Vector = Op . getOperand ( 0 ) ;


SDValue LaneIndex = Op . getOperand ( 1 ) ;


if (Vector.getSimpleValueType() != MVT::v16i1) {

if ( Vector . getSimpleValueType ( ) != MVT :: v16i1 ) {


SDValue MaskBits = DAG.getNode(zmtarzmISD::MASK_TO_INT, DL, MVT::i32, Vector);

SDValue MaskBits = DAG . getNode ( zmtarzmISD :: MASK_TO_INT , DL , MVT :: i32 , Vector ) ;


SDValue Elem = DAG.getNode(ISD::SRL, DL, MVT::i32, MaskBits, LaneIndex);

SDValue Elem = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , MaskBits , LaneIndex ) ;


if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {

if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) {


uint64_t Index = CIndexN->getZExtValue();

uint64_t Index = CIndexN -> getZExtValue ( ) ;


unsigned Mask = VecVT.getVectorNumElements() - 1;

unsigned Mask = VecVT . getVectorNumElements ( ) - 1 ;


MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VecVT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);

SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ;


return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;

DAG.getNode(ISD::BITCAST, SL, ResultVT, Result)


SDValue zmtarzmTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const {


if ( ! isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) {


EVT VT = Op.getOperand(0).getValueType();

EVT VT = Op . getOperand ( 0 ) . getValueType ( ) ;


SDValue WideVec = WidenVector(Op.getOperand(0), DAG);

SDValue WideVec = WidenVector ( Op . getOperand ( 0 ) , DAG ) ;


EVT WideTy = WideVec . getValueType ( ) ;


EVT ExtrTy = WideTy.getVectorElementType();

EVT ExtrTy = WideTy . getVectorElementType ( ) ;


if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {

if ( const ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ) {


SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue Result = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result, DAG.getConstant(16, SL, MVT::i32));

Result = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , Result , DAG . getConstant ( 16 , SL , MVT :: i32 ) ) ;


if ( ResultVT . bitsLT ( MVT :: i32 ) ) {


Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);

Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ;


return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);

return DAG . getNode ( ISD :: BITCAST , SL , ResultVT , Result ) ;


SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);

SDValue Sixteen = DAG . getConstant ( 16 , SL , MVT :: i32 ) ;


SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);

SDValue ScaledIdx = DAG . getNode ( ISD :: SHL , SL , MVT :: i32 , Idx , Sixteen ) ;


SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);

SDValue BC = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ;


SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);

SDValue Elt = DAG . getNode ( ISD :: SRL , SL , MVT :: i32 , BC , ScaledIdx ) ;


if ( Subtarget . isHVXVectorType ( VecTy ) ) {


return LowerHvxExtractElement ( Op , DAG ) ;


MVT ElemTy = ty(Vec).getVectorElementType();

MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;


SDValue Vector = Op . getOperand ( 0 ) ;


SDValue LaneIndex = Op . getOperand ( 1 ) ;


if (Vector.getSimpleValueType() != MVT::v16i1) {

if ( Vector . getSimpleValueType ( ) != MVT :: v16i1 ) {


SDValue MaskBits = DAG.getNode(zmtarzmISD::MASK_TO_INT, DL, MVT::i32, Vector);

SDValue MaskBits = DAG . getNode ( zmtarzmISD :: MASK_TO_INT , DL , MVT :: i32 , Vector ) ;


SDValue Elem = DAG.getNode(ISD::SRL, DL, MVT::i32, MaskBits, LaneIndex);

SDValue Elem = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , MaskBits , LaneIndex ) ;


if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {

if ( auto * CIndexN = dyn_cast < ConstantSDNode > ( Op1 ) ) {


uint64_t Index = CIndexN->getZExtValue();

uint64_t Index = CIndexN -> getZExtValue ( ) ;


unsigned Mask = VecVT.getVectorNumElements() - 1;

unsigned Mask = VecVT . getVectorNumElements ( ) - 1 ;


MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());

MVT IntVT = MVT :: getIntegerVT ( VT . getSizeInBits ( ) ) ;


MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());

MVT IntVecVT = MVT :: getVectorVT ( IntVT , VecVT . getVectorNumElements ( ) ) ;


SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);

SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ;


return DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Elem , DAG . getConstant ( 1 , DL , MVT :: i32 ) ) ;

return DAG.getNode(ISD::AND, DL, MVT::i32, Elem, DAG.getConstant(1, DL, MVT::i32));


SDValue zmtarzmTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


if ( CallCConv != CallingConv :: Fast ) {


report_fatal_error
(
"Unsupported calling convention"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Lowering formal arguments\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"ISelDAG: Lowering formal arguments\n"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Can't lower variadic arguments\n");


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CC_zmtarzm ) ;


CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ;


Chain = DAG.getNode(zmtarzmISD::ENTRY_FLAG, DL, MVT::Other, {Chain, DAG.getRegister(zmtarzm::a1, MVT::i32), DAG.getTargetConstant(4, DL, MVT::i32)});

Chain = DAG . getNode ( zmtarzmISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( zmtarzm :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ;


CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ;


FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ;


for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


ArgValue = unpack64(DAG, Chain, VA, DL);

ArgValue = unpack64 ( DAG , Chain , VA , DL ) ;


ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);

ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ;


ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);

ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ;


unsigned VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ;


SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());

SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ;


if ( VA . getValVT ( ) == MVT :: i32 ) {


Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, DAG.getConstant(32, DL, MVT::i32));

Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);

Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ;


unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;

unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;


unsigned ValSize = VA.getValVT().getSizeInBits() / 8;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ;


int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),  MachinePointerInfo::getFixedStack(MF, FI)));

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);

unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


if (VA.getLocInfo() == CCValAssign::Full) {

if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {


if (VA.getLocInfo() == CCValAssign::BCvt) {

if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {


ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);

ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ;


SDValue Val = DAG.getLoad(VA.getLocInfo() == CCValAssign::AExt ? VA.getValVT() : VA.getLocVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())), MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));

SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


InVals.push_back(DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val));

InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ;


ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs);

ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;


unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &RegInfo = MF.getRegInfo();

MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ;


zmtarzmMachineFunctionInfo *zmtarzmFI = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * zmtarzmFI = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


VaArgOffset = CCInfo . getNextStackOffset ( ) ;


VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ;


int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


zmtarzmFI -> setVarArgsFrameIndex ( FI ) ;


for (unsigned i = Idx; i < ArgRegs.size(); ++i, VaArgOffset += XLenInBytes) {

for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) {


const Register Reg = RegInfo.createVirtualRegister(RC);

const Register Reg = RegInfo . createVirtualRegister ( RC ) ;


RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ;


FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);

FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ;


SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));

SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI));

SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ;


cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


zmtarzmFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ;


Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);

Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ;


unsigned ArgOffset = ArgLocs.size() * 8;

unsigned ArgOffset = ArgLocs . size ( ) * 8 ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ;


SDValue zmtarzmTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


if ( CallCConv != CallingConv :: Fast ) {


report_fatal_error
(
"Unsupported calling convention"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Lowering formal arguments\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"ISelDAG: Lowering formal arguments\n"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Can't lower variadic arguments\n");


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ;


CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CC_zmtarzm ) ;


CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ;


Chain = DAG.getNode(zmtarzmISD::ENTRY_FLAG, DL, MVT::Other, {Chain, DAG.getRegister(zmtarzm::a1, MVT::i32), DAG.getTargetConstant(4, DL, MVT::i32)});

Chain = DAG . getNode ( zmtarzmISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( zmtarzm :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ;


CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ;


FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ;


for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


bool IsF64Onzmtarzm = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;

bool IsF64Onzmtarzm = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ;


ArgValue = unpack64(DAG, Chain, VA, DL);

ArgValue = unpack64 ( DAG , Chain , VA , DL ) ;


ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);

ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ;


ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);

ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ;


unsigned VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));

unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ;


SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());

SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ;


if ( VA . getValVT ( ) == MVT :: i32 ) {


Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, DAG.getConstant(32, DL, MVT::i32));

Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ;


if (VA.getLocInfo() == CCValAssign::SExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {


Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


if (VA.getLocInfo() == CCValAssign::ZExt) {

if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {


Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, DAG.getValueType(VA.getValVT()));

Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);

Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ;


unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;

unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;


unsigned ValSize = VA.getValVT().getSizeInBits() / 8;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ;


int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),  MachinePointerInfo::getFixedStack(MF, FI)));

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);

unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;


SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


if (VA.getLocInfo() == CCValAssign::Full) {

if ( VA . getLocInfo ( ) == CCValAssign :: Full ) {


if (VA.getLocInfo() == CCValAssign::BCvt) {

if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {


ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);

ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ;


SDValue Val = DAG.getLoad(VA.getLocInfo() == CCValAssign::AExt ? VA.getValVT() : VA.getLocVT(), DL, Chain, DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())), MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));

SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, DAG.getValueType(VA.getValVT()));

Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ;


InVals.push_back(DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val));

InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ;


ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs);

ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;


unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


const TargetRegisterClass *RC = &zmtarzm::GPRRegClass;

const TargetRegisterClass * RC = & zmtarzm :: GPRRegClass ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &RegInfo = MF.getRegInfo();

MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ;