setOperationAction ( ISD :: UDIV , MVT :: i64 , Expand ) ;

ISD::UDIV zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: UREM , MVT :: i64 , Expand ) ;

ISD::UREM zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i32 , Expand ) ;

ISD::ADDC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i32 , Expand ) ;

ISD::ADDE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: ADDC , MVT :: i64 , Expand ) ;

ISD::ADDC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: ADDE , MVT :: i64 , Expand ) ;

ISD::ADDE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i32 , Expand ) ;

ISD::SUBC zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i32 , Expand ) ;

ISD::SUBE zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: SUBC , MVT :: i64 , Expand ) ;

ISD::SUBC zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: SUBE , MVT :: i64 , Expand ) ;

ISD::SUBE zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BR_CC , MVT :: f32 , Expand ) ;

ISD::BR_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: f64 , Expand ) ;

ISD::BR_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);


setCondCodeAction ( CC , VT , Expand ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setBooleanContents ( UndefinedBooleanContent ) ;


setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R14 ) ;


setStackPointerRegisterToSaveRestore ( zmtarzm :: R3 ) ;


setMinFunctionAlignment ( FunctionAlignment ) ;


setSchedulingPreference ( Sched :: Source ) ;


setOperationAction ( ISD :: BR_CC , MVT :: i32 , Expand ) ;

ISD::BR_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);


setOperationAction ( ISD :: BR_CC , MVT :: i64 , Expand ) ;

ISD::BR_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: i64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f32 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);


setOperationAction ( ISD :: SELECT_CC , MVT :: f64 , Expand ) ;

ISD::SELECT_CC zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i32 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);


setOperationAction ( ISD :: UINT_TO_FP , MVT :: i64 , Expand ) ;

ISD::UINT_TO_FP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);


setOperationAction ( ISD :: FP_TO_UINT , MVT :: i32 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);


setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ;


setBooleanContents ( ZeroOrOneBooleanContent ) ;


setOperationAction(#,              #,   #);

setOperationAction ( ISD :: FP_TO_UINT , MVT :: i64 , Expand ) ;

ISD::FP_TO_UINT zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);


setOperationAction(#,               #,   #);

setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i1 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i1 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i1 Expand


setOperationAction(#,           #,   #);

setOperationAction ( ISD :: CTPOP , MVT :: i32 , Legal ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Legal ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Legal

setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);


setOperationAction ( ISD :: CTPOP , MVT :: i32 , Expand ) ;

ISD::CTPOP zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);


setOperationAction ( ISD :: CTPOP , MVT :: i64 , Expand ) ;

ISD::CTPOP zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i32 , Expand ) ;

ISD::CTTZ zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);


setOperationAction ( ISD :: CTTZ , MVT :: i64 , Expand ) ;

ISD::CTTZ zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i32 , Expand ) ;

ISD::ROTL zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i32,   Expand);


setOperationAction ( ISD :: ROTL , MVT :: i64 , Expand ) ;

ISD::ROTL zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTL,              MVT::i64,   Expand);


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i32 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i32 Expand


setOperationAction ( ISD :: DYNAMIC_STACKALLOC , MVT :: i64 , Expand ) ;

ISD::DYNAMIC_STACKALLOC zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);

ISD :: DYNAMIC_STACKALLOC MVT :: i64 Expand


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i32 , Expand ) ;

ISD::ROTR zmsplit MVT::i32 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i32,   Expand);


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: ROTR , MVT :: i64 , Expand ) ;

ISD::ROTR zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ROTR, MVT::i64,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f32 , Expand ) ;

ISD::FSIN zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f32,   Expand);


setOperationAction ( ISD :: FSIN , MVT :: f64 , Expand ) ;

ISD::FSIN zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSIN,              MVT::f64,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f32 , Expand ) ;

ISD::FCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f32,   Expand);


setOperationAction ( ISD :: FCOS , MVT :: f64 , Expand ) ;

ISD::FCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FCOS,              MVT::f64,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f32 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);


setOperationAction ( ISD :: FSINCOS , MVT :: f64 , Expand ) ;

ISD::FSINCOS zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f32 , Expand ) ;

ISD::FPOW zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f32,   Expand);


setOperationAction ( ISD :: FPOW , MVT :: f64 , Expand ) ;

ISD::FPOW zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FPOW,              MVT::f64,   Expand);


setOperationAction ( ISD :: FLOG , MVT :: f32 , Expand ) ;

ISD::FLOG zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG,              MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG2 , MVT :: f32 , Expand ) ;

ISD::FLOG2 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);


setOperationAction ( ISD :: FLOG10 , MVT :: f32 , Expand ) ;

ISD::FLOG10 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);


setOperationAction ( ISD :: FEXP , MVT :: f32 , Expand ) ;

ISD::FEXP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FEXP,              MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f32 , Expand ) ;

ISD::FMA zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f32,   Expand);


setOperationAction ( ISD :: FMA , MVT :: f64 , Expand ) ;

ISD::FMA zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FMA,               MVT::f64,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f32 , Expand ) ;

ISD::FREM zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f32,   Expand);


setOperationAction ( ISD :: FREM , MVT :: f64 , Expand ) ;

ISD::FREM zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FREM,              MVT::f64,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f32 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f32 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f32 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);


setOperationAction ( ISD :: FP16_TO_FP , MVT :: f64 , Expand ) ;

ISD::FP16_TO_FP zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);


setOperationAction ( ISD :: FP_TO_FP16 , MVT :: f64 , Expand ) ;

ISD::FP_TO_FP16 zmsplit MVT::f64 zmsplit Expand

setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);


setOperationAction ( ISD :: EH_RETURN , MVT :: Other , Custom ) ;

ISD::EH_RETURN zmsplit MVT::Other zmsplit Custom


setOperationAction ( ISD :: VASTART , MVT :: Other , Custom ) ;

ISD::VASTART zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VASTART,           MVT::Other, Custom);


setOperationAction ( ISD :: VAARG , MVT :: Other , Custom ) ;

ISD::VAARG zmsplit MVT::Other zmsplit Custom

setOperationAction(ISD::VAARG,             MVT::Other, Custom);


setOperationAction ( ISD :: VACOPY , MVT :: Other , Expand ) ;

ISD::VACOPY zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VACOPY,            MVT::Other, Expand);


setOperationAction ( ISD :: VAEND , MVT :: Other , Expand ) ;

ISD::VAEND zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::VAEND,             MVT::Other, Expand);


setStackPointerRegisterToSaveRestore ( # ) ;


computeRegisterProperties ( STI . getRegisterInfo ( ) ) ;


setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ;


setOperationAction ( ISD :: STACKSAVE , MVT :: Other , Expand ) ;

ISD::STACKSAVE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);


setOperationAction ( ISD :: STACKRESTORE , MVT :: Other , Expand ) ;

ISD::STACKRESTORE zmsplit MVT::Other zmsplit Expand

setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);


setOperationAction ( ISD :: ATOMIC_LOAD , MVT :: i64 , Expand ) ;

ISD::ATOMIC_LOAD zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);


setOperationAction ( ISD :: ATOMIC_STORE , MVT :: i64 , Expand ) ;

ISD::ATOMIC_STORE zmsplit MVT::i64 zmsplit Expand

setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);


if ( ! Subtarget . haszmtarzm32r2 ( ) ) {


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i8 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i8 zmsplit Expand

setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);

ISD :: SIGN_EXTEND_INREG MVT :: i8 Expand


setOperationAction ( ISD :: SIGN_EXTEND_INREG , MVT :: i16 , Expand ) ;

ISD::SIGN_EXTEND_INREG zmsplit MVT::i16 zmsplit Expand

ISD :: SIGN_EXTEND_INREG MVT :: i16 Expand


if ( Subtarget . inzmtarzm16Mode ( ) ) {


setOperationAction ( ISD :: CTLZ , MVT :: i32 , Expand ) ;

ISD::CTLZ zmsplit MVT::i32 zmsplit Expand


setOperationAction ( ISD :: CTLZ , MVT :: i64 , Expand ) ;

ISD::CTLZ zmsplit MVT::i64 zmsplit Expand


setOperationAction ( ISD :: BSWAP , MVT :: i32 , Expand ) ;

ISD::BSWAP zmsplit MVT::i32 zmsplit Expand


if ( ! Subtarget . haszmtarzm64r2 ( ) ) {


setOperationAction ( ISD :: BSWAP , MVT :: i64 , Expand ) ;

ISD::BSWAP zmsplit MVT::i64 zmsplit Expand


setLoadExtAction ( ISD :: SEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::SEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: SEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: ZEXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::ZEXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: ZEXTLOAD MVT :: i64 MVT :: i32 Custom


setLoadExtAction ( ISD :: EXTLOAD , MVT :: i64 , MVT :: i32 , Custom ) ;

ISD::EXTLOAD zmsplit MVT::i64 zmsplit MVT::i32 zmsplit Custom

setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);

ISD :: EXTLOAD MVT :: i64 MVT :: i32 Custom


setTruncStoreAction ( MVT :: i64 , MVT :: i32 , Custom ) ;

MVT::i64 zmsplit  MVT::i32 zmsplit  Custom


setOperationAction ( ISD :: TRAP , MVT :: Other , Legal ) ;

ISD::TRAP zmsplit MVT::Other zmsplit Legal


setTargetDAGCombine ( ISD :: SDIVREM ) ;


setTargetDAGCombine ( ISD :: UDIVREM ) ;


setTargetDAGCombine ( ISD :: AssertZext ) ;


setLibcallName ( RTLIB :: SHL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRL_I128 , nullptr ) ;


setLibcallName ( RTLIB :: SRA_I128 , nullptr ) ;


setMinStackArgumentAlignment ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? 8 : 4 ) ;

setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);


setStackPointerRegisterToSaveRestore(ABI.IsN64() ? zmtarzm::SP_64 : zmtarzm::SP);

setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? zmtarzm :: SP_64 : zmtarzm :: SP ) ;


FunctionPass * llvm :: createzmtarzmLoopMetadataLowering ( ) {


return new zmtarzmLoopMetadataLowering ( ) ;


virtual void getAnalysisUsage(AnalysisUsage &AU) const override {

virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


zmtarzmLoopMetadataLowering() : FunctionPass(ID) {

zmtarzmLoopMetadataLowering ( ) : FunctionPass ( ID ) {


initializezmtarzmLoopMetadataLowering ( * PassRegistry :: getPassRegistry ( ) ) ;


bool zmtarzmLoopMetadataLowering::runOnFunction(Function &F) {

bool zmtarzmLoopMetadataLowering :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


bool zmtarzmLoopMetadataLowering :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function :: iterator I = function . begin ( ) ;


TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


zmtarzmCall(unsigned T) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmCall ( unsigned T ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


static inline bool classof(const zmtarzmCall *C) {

static inline bool classof ( const zmtarzmCall * C ) {


return C->getType() == zmtarzmCall::FunctionType;

return C -> getType ( ) == zmtarzmCall :: FunctionType ;


static inline bool classof(const zmtarzmFunctionCall *) {

static inline bool classof ( const zmtarzmFunctionCall * ) {


static inline bool classof(const zmtarzmCall *) {

static inline bool classof ( const zmtarzmCall * ) {


static inline bool classof(const zmtarzmExternalSymbolCall *) {

static inline bool classof ( const zmtarzmExternalSymbolCall * ) {


return C->getType() == zmtarzmCall::ExternalSymbolType;

return C -> getType ( ) == zmtarzmCall :: ExternalSymbolType ;


zmtarzmExternalSymbolCall(const char *S) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmExternalSymbolCall ( const char * S ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


zmtarzmFunctionCall(const Function *F) : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmFunctionCall ( const Function * F ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


explicit zmtarzmFunctionInfo(MachineFunction &MF) : : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

explicit zmtarzmFunctionInfo ( MachineFunction & MF ) : : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


zmtarzmFunctionInfo() : UsesLR(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0) {

zmtarzmFunctionInfo ( ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) {


const std::vector<zmtarzmCall*> &getCalls() const {

const std :: vector < zmtarzmCall * > & getCalls ( ) const {


void setVarArgsFrameIndex ( int Index ) {


zmtarzmFunctionInfo :: ~ zmtarzmFunctionInfo ( ) {


static MCAsmInfo *createzmtarzmMCAsmInfo(const Target &T, StringRef TT) {

static MCAsmInfo * createzmtarzmMCAsmInfo ( const Target & T , StringRef TT ) {


MCAsmInfo *MAI = new zmtarzmMCAsmInfo(T, TT);

MCAsmInfo * MAI = new zmtarzmMCAsmInfo ( T , TT ) ;


MachineLocation Dst ( MachineLocation :: VirtualFP ) ;


MachineLocation Src ( zmtarzm :: XSP , 0 ) ;


MAI -> addInitialFrameState ( 0 , Dst , Src ) ;


MachineLocation Src ( zmtarzm :: SP , 0 ) ;


MachineLocation Src ( zmtarzm :: PC , 0 ) ;


MachineLocation Src ( zmtarzm :: XP , 0 ) ;


MachineLocation Src ( zmtarzm :: LR32 , 0 ) ;


static MCCodeGenInfo *createzmtarzmMCCodeGenInfo(StringRef TT,  Reloc::Model RM, CodeModel::Model CM) {

static MCCodeGenInfo * createzmtarzmMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) {


MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


static MCInstrInfo *createzmtarzmMCInstrInfo() {

static MCInstrInfo * createzmtarzmMCInstrInfo ( ) {


static MCRegisterInfo *createzmtarzmMCRegisterInfo(StringRef TT) {

static MCRegisterInfo * createzmtarzmMCRegisterInfo ( StringRef TT ) {


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R2 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R26 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: BLINK ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: LR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: r31 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RETS ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R11 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: X0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PC ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: GR6 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: SW ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R15 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: XX ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PSW ) ;


static MCRegisterInfo * createzmtarzmMCRegisterInfo ( StringRef TT ) {


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RCA ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RRA ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R1 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A0 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RA ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: LR ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: RA_REG ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R9 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: I7 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R14D ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: R51 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PCW ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: A11 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: SX10 ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: PC ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: dpI32_0 ) ;


static MCRegisterInfo * createzmtarzmMCRegisterInfo ( StringRef TT ) {


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: IP ) ;


InitzmtarzmMCRegisterInfo ( X , zmtarzm :: AR0 ) ;


static MCSubtargetInfo *createzmtarzmMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {

static MCSubtargetInfo * createzmtarzmMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) {


MCSubtargetInfo *X = new MCSubtargetInfo();

MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;


InitzmtarzmMCSubtargetInfo(X, TT, CPU, FS);

InitzmtarzmMCSubtargetInfo ( X , TT , CPU , FS ) ;


extern "C" void LLVMInitializezmtarzmTargetMC() {

extern "C" void LLVMInitializezmtarzmTargetMC ( ) {


RegisterMCAsmInfoFn X ( ThezmtarzmTarget , createzmtarzmMCAsmInfo ) ;


TargetRegistry :: RegisterMCCodeGenInfo ( ThezmtarzmTarget , createzmtarzmMCCodeGenInfo ) ;


TargetRegistry :: RegisterMCInstrInfo ( ThezmtarzmTarget , createzmtarzmMCInstrInfo ) ;


TargetRegistry :: RegisterMCRegInfo ( ThezmtarzmTarget , createzmtarzmMCRegisterInfo ) ;


TargetRegistry :: RegisterMCSubtargetInfo ( ThezmtarzmTarget , createzmtarzmMCSubtargetInfo ) ;


void zmtarzmRegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {

void zmtarzmRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


if ( ! TFI -> hasReservedCallFrame ( MF ) ) {


uint64_t Amount = Old->getOperand(0).getImm();

uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ;


unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();

unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ;


Amount = ( Amount + Align - 1 ) / Align * Align ;


if (Old->getOpcode() == zmtarzm::ADJUSTSTACKDOWN) {

if ( Old -> getOpcode ( ) == zmtarzm :: ADJUSTSTACKDOWN ) {


New=BuildMI(MF, Old->getDebugLoc(), TII.get(zmtarzm::LDA), zmtarzm::R30).addImm(-Amount).addReg(zmtarzm::R30);

New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( zmtarzm :: LDA ) , zmtarzm :: R30 ) . addImm ( - Amount ) . addReg ( zmtarzm :: R30 ) ;


assert ( Old -> getOpcode ( ) == zmtarzm :: ADJUSTSTACKUP ) ;


New=BuildMI(MF, Old->getDebugLoc(), TII.get(zmtarzm::LDA), zmtarzm::R30).addImm(Amount).addReg(zmtarzm::R30);

New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( zmtarzm :: LDA ) , zmtarzm :: R30 ) . addImm ( Amount ) . addReg ( zmtarzm :: R30 ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


assert
(
isUInt
<
6
>
(
Offset
)
&&
"Offset is out of range"
)
;

assert(isUInt<6>(Offset) && "Offset is out of range");


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


if ( MI . getOpcode ( ) == zmtarzm :: LDR ) {


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


if ( MI . getOpcode ( ) == zmtarzm :: STR ) {


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


void zmtarzmRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {

void zmtarzmRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

assert
(
SPAdj
==
0
&&
"Unexpected non-zero SPAdj value"
)
;


MachineFunction &MF = *MI.getParent()->getParent();

MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: SP , false ) ;


int OffsetOperandNo = FIOperandNum + 1 ;


int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm();

int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;


report_fatal_error("Frame offsets outside of the signed 16-bit range not supported");


MachineBasicBlock &MBB = *MI.getParent();

MachineBasicBlock & MBB = * MI . getParent ( ) ;


const MachineFunction &MF = *MI.getParent()->getParent();

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


const MachineFrameInfo &MFI = MF.getFrameInfo();

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineOperand &FIOp = MI.getOperand(FIOperandNum);

MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ;


const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ;


unsigned DstReg = MI.getOperand(0).getReg();

unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ;


MI . setDesc ( TII . get ( zmtarzm :: MOV ) ) ;


MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ;


MI . setDesc ( TII . get ( zmtarzm :: LI ) ) ;


MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ;


MachineInstr *New = BuildMI(MBB, II, DL, TII.get(zmtarzm::ADD), DstReg).addReg(DstReg, RegState::Kill).addReg(FrameReg);

MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( zmtarzm :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ;


New -> getOperand ( 3 ) . setIsDead ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)MF.getTarget();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) MF . getTarget ( ) ;


const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();

const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ;


Offset = Offset + MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;

Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ;


Offset = Offset + MI.getOperand(OffsetOperandNo).getImm();

Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ;


MI . getOperand ( FIOperandNum ) . ChangeToRegister ( zmtarzm :: A , false ) ;


uint64_t stackSize = MF.getFrameInfo()->getStackSize();

uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ;


int64_t spOffset = MF.getFrameInfo()->getObjectOffset(frameIndex);

int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ;


Register FrameReg = getFrameRegister(MF);

Register FrameReg = getFrameRegister ( MF ) ;


int64_t Offset = spOffset + (int64_t)stackSize;

int64_t Offset = spOffset + ( int64_t ) stackSize ;


MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ;


MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ;


MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);

MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ;


int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();

int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ;


FIOp . ChangeToRegister ( zmtarzm :: SP , false ) ;


MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


const unsigned * zmtarzmRegisterInfo::getArgRegs(const MachineFunction *MF) {

const unsigned * zmtarzmRegisterInfo :: getArgRegs ( const MachineFunction * MF ) {


const MCPhysReg *zmtarzmRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

const MCPhysReg * zmtarzmRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


const zmtarzzmFrameLowering *TFI = getFrameLowering(*MF);

const zmtarzzmFrameLowering * TFI = getFrameLowering ( * MF ) ;


static const MCPhysReg CalleeSavedRegs[] = {zmtarzm::S0, zmtarzm::SRB, zmtarzm::SRO,zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24,zmtarzm::R25, zmtarzm::R26, zmtarzm::R27, zmtarzm::R28,zmtarzm::P1, zmtarzm::P2, zmtarzm::P3, zmtarzm::P4,zmtarzm::P5, zmtarzm::P6, zmtarzm::P7,0

static const MCPhysReg CalleeSavedRegs [ ] = { zmtarzm :: S0 , zmtarzm :: SRB , zmtarzm :: SRO , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , zmtarzm :: R26 , zmtarzm :: R27 , zmtarzm :: R28 , zmtarzm :: P1 , zmtarzm :: P2 , zmtarzm :: P3 , zmtarzm :: P4 , zmtarzm :: P5 , zmtarzm :: P6 , zmtarzm :: P7 , 0


static const MCPhysReg CalleeSavedRegsFP[] = {

static const MCPhysReg CalleeSavedRegsFP [ ] = {


zmtarzm::S0, zmtarzm::SRB, zmtarzm::SRO,zmtarzm::R21, zmtarzm::R22, zmtarzm::R23, zmtarzm::R24,zmtarzm::R25, zmtarzm::R26, zmtarzm::R27, zmtarzm::R28,zmtarzm::RFP,zmtarzm::P1, zmtarzm::P2, zmtarzm::P3, zmtarzm::P4,zmtarzm::P5, zmtarzm::P6, zmtarzm::P7,0

zmtarzm :: S0 , zmtarzm :: SRB , zmtarzm :: SRO , zmtarzm :: R21 , zmtarzm :: R22 , zmtarzm :: R23 , zmtarzm :: R24 , zmtarzm :: R25 , zmtarzm :: R26 , zmtarzm :: R27 , zmtarzm :: R28 , zmtarzm :: RFP , zmtarzm :: P1 , zmtarzm :: P2 , zmtarzm :: P3 , zmtarzm :: P4 , zmtarzm :: P5 , zmtarzm :: P6 , zmtarzm :: P7 , 0


unsigned zmtarzmRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

unsigned zmtarzmRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


return TFI -> hasFP ( MF ) ? zmtarzm :: FP : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::FP : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: R28 : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::R28 : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: X2 : zmtarzm :: X1 ;

return TFI->hasFP(MF) ? zmtarzm::X2 : zmtarzm::X1  ;


return TFI -> hasFP ( MF ) ? zmtarzm :: J : zmtarzm :: SP ;

return TFI->hasFP(MF) ? zmtarzm::J : zmtarzm::SP;


return TFI -> hasFP ( MF ) ? zmtarzm :: RFP : zmtarzm :: RSP ;

return TFI->hasFP(MF) ? zmtarzm::RFP : zmtarzm::RSP;


return TFI -> hasFP ( MF ) ? zmtarzm :: R22 : zmtarzm :: R3 ;

return TFI->hasFP(MF) ? zmtarzm::R22 : zmtarzm::R3;


return TFI -> hasFP ( MF ) ? zmtarzm :: R30 : zmtarzm :: R31 ;

return TFI->hasFP(MF) ? zmtarzm::R30 : zmtarzm::R31;


return TFI -> hasFP ( MF ) ? zmtarzm :: A14 : zmtarzm :: A10 ;

return TFI->hasFP(MF) ? zmtarzm::A14 : zmtarzm::A10;


unsigned zmtarzmRegisterInfo::getNumArgRegs(const MachineFunction *MF) {

unsigned zmtarzmRegisterInfo :: getNumArgRegs ( const MachineFunction * MF ) {


return array_lengthof ( zmtarzm_ArgRegs ) ;


BitVector zmtarzmRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector zmtarzmRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const {


bool zmtarzmRegisterInfo::needsFrameMoves(const MachineFunction &MF) {

bool zmtarzmRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) {


return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow();

return MF . getMMI ( ) . hasDebugInfo ( ) || ! MF . getFunction ( ) -> doesNotThrow ( ) ;


void zmtarzmRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const {

void zmtarzmRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(#), TII(tii) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( # ) , TII ( tii ) {

zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: BLINK ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::BLINK), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: PR ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::PR), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: RCA ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::RCA), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: LR ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::LR), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: R7 ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::R7), TII(tii) {


zmtarzmRegisterInfo :: zmtarzmRegisterInfo ( const TargetInstrInfo & tii ) : zmtarzmGenRegisterInfo ( zmtarzm :: PC ) , TII ( tii ) {

zmtarzmRegisterInfo::zmtarzmRegisterInfo(const TargetInstrInfo &tii) : zmtarzmGenRegisterInfo(zmtarzm::PC), TII(tii) {


bool zmtarzmRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {

bool zmtarzmRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const {


const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;

const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();


bool zmtarzmRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {

bool zmtarzmRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const {


SDValue zmtarzmSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {

SDValue zmtarzmSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


const zmtarzmSubtarget &STI = DAG.getMachineFunction().getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) ;


return EmitMOPS(zmtarzmISD::MOPS_MEMCOPY, DAG, DL, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo);

return EmitMOPS ( zmtarzmISD :: MOPS_MEMCOPY , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ;


if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {

if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) {


return emitMemMem(DAG, DL, zmtarzmISD::MVC, zmtarzmISD::MVC_LOOP, Chain, Dst, Src, CSize->getZExtValue());

return emitMemMem ( DAG , DL , zmtarzmISD :: MVC , zmtarzmISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


return EmitTargetCodeForMemOp(DAG, dl, Chain, Dst, Src, Size, Alignment, isVolatile, AlwaysInline, MustPreserveCheriCapabilities, DstPtrInfo, SrcPtrInfo, true);

return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ;


if ( ! DAG . getMachineFunction ( ) . getSubtarget < zmtarzmSubtarget > ( ) . hasBulkMemory ( ) ) {


SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32);

SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ;


return DAG.getNode(zmtarzmISD::MEMORY_COPY, DL, MVT::Other, {Chain, MemIdx, MemIdx, Dst, Src, DAG.getZExtOrTrunc(Size, DL, MVT::i32)});

return DAG . getNode ( zmtarzmISD :: MEMORY_COPY , DL , MVT :: Other , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) } ) ;


zmtarzmSelectionDAGInfo::zmtarzmSelectionDAGInfo(const zmtarzmTargetMachine &TM) : TargetSelectionDAGInfo(TM), TLI(*TM.getTargetLowering()) {

zmtarzmSelectionDAGInfo :: zmtarzmSelectionDAGInfo ( const zmtarzmTargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) , TLI ( * TM . getTargetLowering ( ) ) {


zmtarzmSelectionDAGInfo :: ~ zmtarzmSelectionDAGInfo ( ) {


FunctionPass * llvm :: createzmtarzmSimpleBranchOptPass ( ) {


virtual const char *getPassName() const {

virtual const char * getPassName ( ) const {


return "zmtarzm branch to trap optimization";

return
"zmtarzm branch to trap optimization"
;


bool zmtarzmSimpleBranchOpt::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmSimpleBranchOpt :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


zmtarzmSimpleBranchOpt() : MachineFunctionPass(ID) {

zmtarzmSimpleBranchOpt ( ) : MachineFunctionPass ( ID ) {


FunctionPass * llvm :: createzmtarzmStackAnalysisPrepare ( ) {


return new zmtarzmStackAnalysisPrepare ( ) ;


virtual void getAnalysisUsage(AnalysisUsage &AU) const override {

virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


bool zmtarzmStackAnalysisPrepare::runOnFunction(Function &F) {

bool zmtarzmStackAnalysisPrepare :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();

auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? &TLIP->getTLI() : nullptr;

LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {

for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder<>(Func.getContext());

IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for (auto &GV : Func.getParent()->globals()) {

for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if (!I->getType()->isVoidTy() || isa<StoreInst>(I)) {

if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function::iterator I = function.begin();

Function :: iterator I = function . begin ( ) ;


TerminatorInst *firstTerminatorInst = (I++)->getTerminator();

TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for (Function::iterator E = function.end(); I != E; ++I) {

for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {

for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);

AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {

if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


bool zmtarzmStackAnalysisPrepare :: runOnFunction ( Function & F ) {


LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


SE = & getAnalysis < ScalarEvolution > ( ) ;


DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


DL = & F . getParent ( ) -> getDataLayout ( ) ;


auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ;


LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ;


for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) {


IRB = new IRBuilder < > ( Func . getContext ( ) ) ;


IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ;


for ( auto & GV : Func . getParent ( ) -> globals ( ) ) {


SmallVector < Instruction * > Worklist ;


for ( auto & I : instructions ( Func ) ) {


if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) {


IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ;


Function :: iterator I = function . begin ( ) ;


TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ;


for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) {


for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) {


AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ;


if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {


allocaInst -> moveBefore ( firstTerminatorInst ) ;


zmtarzmStackAnalysisPrepare() : FunctionPass(ID) {

zmtarzmStackAnalysisPrepare ( ) : FunctionPass ( ID ) {


initializezmtarzmStackAnalysisPrepare ( * PassRegistry :: getPassRegistry ( ) ) ;


FunctionPass * llvm :: createzmtarzmStackUsage ( ) {


virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override {


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


return "Calculates zmtarzm stack usage";

return
"Calculates zmtarzm stack usage"
;


bool zmtarzmStackUsage::runOnMachineFunction(MachineFunction &MF) {

bool zmtarzmStackUsage :: runOnMachineFunction ( MachineFunction & MF ) {


if ( skipFunction ( MF . getFunction ( ) ) ) {


const zmtarzmSubtarget &ST = MF.getSubtarget<zmtarzmSubtarget>();

const zmtarzmSubtarget & ST = MF . getSubtarget < zmtarzmSubtarget > ( ) ;


Changed = Changed | runOnMachineBasicBlock(MBB);

Changed = Changed | runOnMachineBasicBlock ( MBB ) ;


zmtarzmStackUsage() : MachineFunctionPass(ID) {

zmtarzmStackUsage ( ) : MachineFunctionPass ( ID ) {


zmtarzmSubtarget::zmtarzmSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : zmtarzmGenSubtargetInfo(TT, CPU, FS) {

zmtarzmSubtarget :: zmtarzmSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : zmtarzmGenSubtargetInfo ( TT , CPU , FS ) {


extern "C" void LLVMInitializezmtarzmTargetInfo() {

extern "C" void LLVMInitializezmtarzmTargetInfo ( ) {


RegisterTarget<Triple::zmtarzm> X(ThezmtarzmTarget, "zmtarzm", "zmtarzm");

RegisterTarget < Triple :: zmtarzm > X ( ThezmtarzmTarget , "zmtarzm" , "zmtarzm" ) ;


bool zmtarzmTargetMachine::addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmISelDag ( * this , OptLevel ) ) ;


bool zmtarzmTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmSimpleBranchOptPass ( ) ) ;


PM . add ( createzmtarzmStackUsage ( ) ) ;


bool zmtarzmTargetMachine::addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {

bool zmtarzmTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


PM . add ( createzmtarzmStackAnalysisPrepare ( ) ) ;


PM . add ( createzmtarzmLoopMetadataLowering ( ) ) ;


virtual const zmtarzmFrameLowering *getFrameLowering() const {

virtual const zmtarzmFrameLowering * getFrameLowering ( ) const {


virtual const zmtarzmInstrInfo *getInstrInfo() const {

virtual const zmtarzmInstrInfo * getInstrInfo ( ) const {


virtual const TargetRegisterInfo *getRegisterInfo() const {

virtual const TargetRegisterInfo * getRegisterInfo ( ) const {


return & InstrInfo . getRegisterInfo ( ) ;


virtual const zmtarzmSelectionDAGInfo* getSelectionDAGInfo() const {

virtual const zmtarzmSelectionDAGInfo * getSelectionDAGInfo ( ) const {


virtual const zmtarzmSubtarget *getSubtargetImpl() const {

virtual const zmtarzmSubtarget * getSubtargetImpl ( ) const {


virtual const TargetData *getTargetData() const {

virtual const TargetData * getTargetData ( ) const {


virtual const zmtarzmTargetLowering *getTargetLowering() const {

virtual const zmtarzmTargetLowering * getTargetLowering ( ) const {


extern "C" void LLVMInitializezmtarzmTarget() {

extern "C" void LLVMInitializezmtarzmTarget ( ) {


RegisterTargetMachine < zmtarzmTargetMachine > X ( ThezmtarzmTarget ) ;


zmtarzmTargetMachine::zmtarzmTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, Reloc::Model RM, CodeModel::Model CM) : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-v64:32:32-v128:32:32-n32"), InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) {


MCSection *zmtarzmTargetObjectFile::getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


StringRef SectionName = GO->getSection();

StringRef SectionName = GO -> getSection ( ) ;


if ( SectionName . startswith ( ".zmtarzm.comment." ) ) {


if (isExecuteOnlyFunction(GO, SK, TM)) {

if ( isExecuteOnlyFunction ( GO , SK , TM ) ) {


SK = SectionKind :: getExecuteOnly ( ) ;


return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);

return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ;


MCSection *zmtarzmELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const {

MCSection * zmtarzmELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const {


if ( isConstantInSmallSection ( DL , C ) ) {


return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment);

return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ;


void zmtarzmELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) {

void zmtarzmELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) {


TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


InitializeELF ( TM . Options . UseInitArray ) ;


SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);

SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


this->TM = &static_cast<const zmtarzmTargetMachine &>(TM);

this -> TM = & static_cast < const zmtarzmTargetMachine & > ( TM ) ;


MCSection *zmtarzmELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {

MCSection * zmtarzmELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const {


if ( isGlobalInSmallSection ( GO , TM ) ) {


return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM);

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


void zmtarzmAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {

void zmtarzmAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) {


if (MI->getOperand(opNum + 1).isImm() && MI->getOperand(opNum + 1).getImm() == 0) {

if ( MI -> getOperand ( opNum + 1 ) . isImm ( ) && MI -> getOperand ( opNum + 1 ) . getImm ( ) == 0 ) {


unsigned zmtarzmInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {

unsigned zmtarzmInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const {


const MachineBasicBlock &MBB = *MI->getParent();

const MachineBasicBlock & MBB = * MI -> getParent ( ) ;


const MachineFunction *MF = MBB.getParent();

const MachineFunction * MF = MBB . getParent ( ) ;


const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();

const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ;


if (MI->getOpcode() == zmtarzm::INLINEASM) {

if ( MI -> getOpcode ( ) == zmtarzm :: INLINEASM ) {


return getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ;


if ( Desc . getOpcode ( ) == TargetOpcode :: DBG_VALUE ) {

if (Desc.getOpcode() == TargetOpcode::DBG_VALUE) {


if ( Desc . getOpcode ( ) == TargetOpcode :: EH_LABEL ) {

if (Desc.getOpcode() == TargetOpcode::EH_LABEL) {


if ( Desc . getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) {

if (Desc.getOpcode() == TargetOpcode::IMPLICIT_DEF) {


if ( Desc . getOpcode ( ) == TargetOpcode :: KILL ) {

if (Desc.getOpcode() == TargetOpcode::KILL) {


const MachineFunction *MF = MI->getParent()->getParent();

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


const zmtarzmTargetMachine &TM = static_cast<const zmtarzmTargetMachine&>(MF->getTarget());

const zmtarzmTargetMachine & TM = static_cast < const zmtarzmTargetMachine & > ( MF -> getTarget ( ) ) ;


const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();

const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ;


return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


const char *AsmStr = MI->getOperand(0).getSymbolName();

const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ;


return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");


SDValue zmtarzmTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const {


SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;

SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ;


SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;

SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;


SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;

SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ;


DebugLoc &dl                          = CLI.DL;

DebugLoc &dl                          = CLI.DL;


SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;

SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ;


SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;

SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ;


SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;

SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ;


CallingConv::ID CallConv = CLI.CallConv;

CallingConv :: ID CallConv = CLI . CallConv ;


const char* zmtarzm16HelperFunction = 0;

const char * zmtarzm16HelperFunction = 0 ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {

if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) {


zmtarzm16HelperFunction = getzmtarzm16HelperFunction(CLI.RetTy, CLI.Args, needzmtarzm16Helper);

zmtarzm16HelperFunction = getzmtarzm16HelperFunction ( CLI . RetTy , CLI . Args , needzmtarzm16Helper ) ;


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


MachineFrameInfo *MFI = MF.getFrameInfo();

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();

const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ;


bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;

bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ;


if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


const GlobalValue * GV = G -> getGlobal ( ) ;


Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), getPointerTy(DAG.getDataLayout()));

Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, true, isVarArg);

analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ;


unsigned NumBytes = CCInfo.getNextStackOffset();

unsigned NumBytes = CCInfo . getNextStackOffset ( ) ;


CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeCallOperands ( Outs , CC_zmtarzm32 ) ;


unsigned ArgsSize = CCInfo.getNextStackOffset();

unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ;


MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {

for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) {


ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ;


unsigned Size = Flags . getByValSize ( ) ;


unsigned Align = Flags . getByValAlign ( ) ;


int FI = MFI->CreateStackObject(Size, Align, false);

int FI = MFI -> CreateStackObject ( Size , Align , false ) ;


SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());

SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


SDValue SizeNode = DAG.getConstant(Size, MVT::i32);

SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ;


Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, (Size <= 32), MachinePointerInfo(), MachinePointerInfo());

Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DL);

Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ;


SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;

SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ;


CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ;


zmtarzmCC zmtarzmCCInfo(CallConv, IsO32, CCInfo);

zmtarzmCC zmtarzmCCInfo ( CallConv , IsO32 , CCInfo ) ;


zmtarzmCCInfo . analyzeCallOperands ( Outs , isVarArg ) ;


unsigned NextStackOffset = CCInfo.getNextStackOffset();

unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;


isTailCall = IsEligibleForTailCallOptimization(zmtarzmCCInfo, NextStackOffset, *MF.getInfo<zmtarzmFunctionInfo>());

isTailCall = IsEligibleForTailCallOptimization ( zmtarzmCCInfo , NextStackOffset , * MF . getInfo < zmtarzmFunctionInfo > ( ) ) ;


unsigned StackAlignment = TFL->getStackAlignment();

unsigned StackAlignment = TFL -> getStackAlignment ( ) ;


NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);

NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ;


SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);

SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ;


Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);

Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ;


SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, IsN64 ? zmtarzm::SP_64 : zmtarzm::SP, getPointerTy());

SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? zmtarzm :: SP_64 : zmtarzm :: SP , getPointerTy ( ) ) ;


std::deque< std::pair<unsigned, SDValue> > RegsToPass;

std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ;


SmallVector < SDValue , 8 > MemOpChains ;


zmtarzmCC::byval_iterator ByValArg = zmtarzmCCInfo.byval_begin();

zmtarzmCC :: byval_iterator ByValArg = zmtarzmCCInfo . byval_begin ( ) ;


for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {

for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) {


MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();

MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ;


assert(!isTailCall && "Do not tail-call optimize if there is a byval argument.");


passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,  zmtarzmCCInfo, *ByValArg, Flags, Subtarget->isLittle());

passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , zmtarzmCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) {

if (VA.getLocInfo() == CCValAssign::SExt) {


Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ;


SDValue Lo = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(0, MVT::i32));

SDValue Lo = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ;


SDValue Hi = DAG.getNode(zmtarzmISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32));

SDValue Hi = DAG . getNode ( zmtarzmISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ;


unsigned LocRegLo = VA . getLocReg ( ) ;


unsigned LocRegHigh = getNextIntArgReg(LocRegLo);

unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ;


RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) {

if (VA.getLocInfo() == CCValAssign::ZExt) {


Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) {

if (VA.getLocInfo() == CCValAssign::AExt) {


Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ;


if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) {

if (VA.getLocInfo() == CCValAssign::BCvt) {


Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


SDValue StackPtr = DAG.getRegister(zmtarzm::O6, MVT::i32);

SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(64);

SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ;


PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);

PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


unsigned Offset = VA.getLocMemOffset() + StackOffset;

unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ;


SDValue PtrOff = DAG.getIntPtrConstant(Offset);

SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ;


SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);

SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ;


SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Arg, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4));

StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ;


SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, 0);

SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ;


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ;


CCValAssign & NextVA = ArgLocs [ ++ i ] ;


RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ;


unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ;


if ( VA . getLocVT ( ) != MVT :: f32 ) {


RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ;


Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);

Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ;


MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, dl, isTailCall, DAG));

MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ;


SDValue StackPtr = DAG . getRegister ( zmtarzm :: O6 , MVT :: i32 ) ;


SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);

SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ;


PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ;


MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,  MachinePointerInfo(),  false, false, 0));

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ;


for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {

for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) {


SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), DAG.getRegister(zmtarzm::SP, getPointerTy(DAG.getDataLayout())), DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));

SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( zmtarzm :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ;


Chain = DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0);

Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ;


Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);

Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ;


bool GlobalOrExternal = false, InternalLinkage = false;

bool GlobalOrExternal = false , InternalLinkage = false ;


if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {

if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ;


Callee = getAddrLocal(Callee, DAG, Haszmtarzm64);

Callee = getAddrLocal ( Callee , DAG , Haszmtarzm64 ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16,  zmtarzmII::MO_CALL_LO16);

Callee = getAddrGlobalLargeGOT ( Callee , DAG , zmtarzmII :: MO_CALL_HI16 , zmtarzmII :: MO_CALL_LO16 ) ;


Callee = getAddrGlobal(Callee, DAG, zmtarzmII::MO_GOT_CALL);

Callee = getAddrGlobal ( Callee , DAG , zmtarzmII :: MO_GOT_CALL ) ;


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , zmtarzmII :: MO_NO_FLAG ) ;


if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), zmtarzmII::MO_NO_FLAG);

Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , zmtarzmII :: MO_NO_FLAG ) ;


Callee = getAddrGlobalLargeGOT(Callee, DAG, zmtarzmII::MO_CALL_HI16, zmtarzmII::MO_CALL_LO16);


unsigned T9Reg = IsN64 ? zmtarzm::T9_64 : zmtarzm::T9;

unsigned T9Reg = IsN64 ? zmtarzm :: T9_64 : zmtarzm :: T9 ;


RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;


JumpTarget = DAG.getExternalSymbol(zmtarzm16HelperFunction, getPointerTy());

JumpTarget = DAG . getExternalSymbol ( zmtarzm16HelperFunction , getPointerTy ( ) ) ;


JumpTarget = getAddrGlobal(JumpTarget, DAG, zmtarzmII::MO_GOT);

JumpTarget = getAddrGlobal ( JumpTarget , DAG , zmtarzmII :: MO_GOT ) ;


RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ;


unsigned GPReg = IsN64 ? zmtarzm::GP_64 : zmtarzm::GP;

unsigned GPReg = IsN64 ? zmtarzm :: GP_64 : zmtarzm :: GP ;


EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ;


RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ;


unsigned Reg = RegsToPass [ i ] . first ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL);

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;

unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ;


if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {


Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);

Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ;


if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {

if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);

Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ;


Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ;


Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


const zmtarzmTargetMachine &TM = (const zmtarzmTargetMachine &)getTargetMachine();

const zmtarzmTargetMachine & TM = ( const zmtarzmTargetMachine & ) getTargetMachine ( ) ;


const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();

const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


const uint32_t *Mask = TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);

const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ;


assert(Mask && "Missing call preserved mask for calling convention");


Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ;


return DAG.getNode(zmtarzmISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());

return DAG . getNode ( zmtarzmISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ;


Chain = DAG.getNode(zmtarzmISD::CALL, DL, NodeTys, Ops);

Chain = DAG . getNode ( zmtarzmISD :: CALL , DL , NodeTys , Ops ) ;


Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ;


SmallVector < CCValAssign , 16 > RVLocs ;


CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());

CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ;


RVInfo . AnalyzeCallResult ( Ins , RetCC_zmtarzm32 ) ;


for (unsigned i = 0; i != RVLocs.size(); ++i) {

for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) {


unsigned Reg = RVLocs [ i ] . getLocReg ( ) ;


Reg = Reg - zmtarzm :: I0 + zmtarzm :: O0 ;


Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1);

Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ;


InVals . push_back ( Chain . getValue ( 0 ) ) ;


return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , DL , DAG , InVals ) ;

return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, InVals);


SDValue zmtarzmTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {

SDValue zmtarzmTargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const {


assert(Subtarget->isTargetWindows() && "unsupported target platform");

assert
(
Subtarget
->
isTargetWindows
(
)
&&
"unsupported target platform"
)
;


if ( isa < ConstantSDNode > ( Size ) ) {


return lowerDYNAMIC_STACKALLOCImpl ( Op , DAG ) ;


return zmtarzmTargetLowering :: LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) {


MaybeAlign Align = cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();

MaybeAlign Align = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) -> getMaybeAlignValue ( ) ;


SDValue SP = DAG.getCopyFromReg(Chain, DL, zmtarzm::SP, MVT::i32);

SDValue SP = DAG . getCopyFromReg ( Chain , DL , zmtarzm :: SP , MVT :: i32 ) ;


SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);

SP = DAG . getNode ( ISD :: SUB , DL , MVT :: i32 , SP , Size ) ;


SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0), DAG.getConstant(-(uint64_t)Align->value(), DL, MVT::i32));

SP = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , SP . getValue ( 0 ) , DAG . getConstant ( - ( uint64_t ) Align -> value ( ) , DL , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::SP, SP);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: SP , SP ) ;


SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size, DAG.getConstant(2, DL, MVT::i32));

SDValue Words = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , Size , DAG . getConstant ( 2 , DL , MVT :: i32 ) ) ;


Chain = DAG.getCopyToReg(Chain, DL, zmtarzm::R4, Words, Flag);

Chain = DAG . getCopyToReg ( Chain , DL , zmtarzm :: R4 , Words , Flag ) ;


SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ;


Chain = DAG.getNode(zmtarzmISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);

Chain = DAG . getNode ( zmtarzmISD :: WIN__CHKSTK , DL , NodeTys , Chain , Flag ) ;


SDValue NewSP = DAG.getCopyFromReg(Chain, DL, zmtarzm::SP, MVT::i32);

SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , zmtarzm :: SP , MVT :: i32 ) ;


SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, dl, PtrVT), Size);

SDValue NegSize = DAG . getNode ( ISD :: SUB , dl , PtrVT , DAG . getConstant ( 0 , dl , PtrVT ) , Size ) ;


SDValue FPSIdx = getFramePointerFrameIndex(DAG);

SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ;


SDValue Ops[3] = { Chain, NegSize, FPSIdx };

SDValue Ops [ 3 ] = { Chain , NegSize , FPSIdx } ;


SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);

SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other ) ;


return DAG.getNode(zmtarzmISD::DYNALLOC, dl, VTs, Ops);

return DAG . getNode ( zmtarzmISD :: DYNALLOC , dl , VTs , Ops ) ;


SDValue zmtarzmTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

SDValue zmtarzmTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


if ( CallCConv != CallingConv :: Fast ) {


report_fatal_error
(
"Unsupported calling convention"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Lowering formal arguments\n");

LLVM_DEBUG
(
dbgs
(
)
<<
"ISelDAG: Lowering formal arguments\n"
)
;


LLVM_DEBUG(dbgs() << "ISelDAG: Can't lower variadic arguments\n");


MachineFunction &MF = DAG.getMachineFunction();

MachineFunction & MF = DAG . getMachineFunction ( ) ;


zmtarzmMachineFunctionInfo *FuncInfo = MF.getInfo<zmtarzmMachineFunctionInfo>();

zmtarzmMachineFunctionInfo * FuncInfo = MF . getInfo < zmtarzmMachineFunctionInfo > ( ) ;


MachineFrameInfo &MFI = MF.getFrameInfo();

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


MachineRegisterInfo &MRI = MF.getRegInfo();

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


SmallVector < CCValAssign , 16 > ArgLocs ;


CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ;


CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ;